Commit 07b91e04 authored by Tristan Gingold's avatar Tristan Gingold

rtl: fix handling of no fifo_readout

The block cannot be completly removed as it defines some registers that
are still used even when the fifos are not present.
parent e4906dab
...@@ -386,10 +386,10 @@ begin ...@@ -386,10 +386,10 @@ begin
-- x5 FIFOS -- -- x5 FIFOS --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- A FIFO with the timestamps of each channel -- A FIFO with the timestamps of each channel
gen_enable_fifo_readout : if g_USE_FIFO_READOUT generate
gen_fifos : for i in 0 to 4 generate gen_fifos : for i in 0 to 4 generate
U_TheFifo : entity work.timestamp_fifo U_TheFifo : entity work.timestamp_fifo
generic map ( generic map (
g_enable => g_USE_FIFO_READOUT,
g_channel => i) g_channel => i)
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
...@@ -408,9 +408,7 @@ begin ...@@ -408,9 +408,7 @@ begin
raw_enable_o => raw_enable(i)); raw_enable_o => raw_enable(i));
timestamp_stb(i) <= tdc_timestamp_valid_p(i); timestamp_stb(i) <= tdc_timestamp_valid_p(i);
end generate gen_fifos; end generate gen_fifos;
end generate gen_enable_fifo_readout;
-- generic map ( -- generic map (
-- g_USE_FIFO_READOUT => g_USE_FIFO_READOUT) -- g_USE_FIFO_READOUT => g_USE_FIFO_READOUT)
......
...@@ -29,6 +29,7 @@ use work.gencores_pkg.all; ...@@ -29,6 +29,7 @@ use work.gencores_pkg.all;
entity timestamp_fifo is entity timestamp_fifo is
generic ( generic (
g_enable : boolean;
g_channel : integer g_channel : integer
); );
port ( port (
...@@ -63,10 +64,8 @@ architecture rtl of timestamp_fifo is ...@@ -63,10 +64,8 @@ architecture rtl of timestamp_fifo is
signal buf_irq_int : std_logic; signal buf_irq_int : std_logic;
signal buf_count : unsigned(9 downto 0); signal buf_count : unsigned(9 downto 0);
signal last_ts : std_logic_vector(127 downto 0);
signal regs_in : t_tsf_in_registers; signal regs_in : t_tsf_in_registers;
signal regs_out : t_tsf_out_registers; signal regs_out : t_tsf_out_registers;
signal channel_id : std_logic_vector(2 downto 0);
signal ts_match : std_logic; signal ts_match : std_logic;
...@@ -80,25 +79,10 @@ architecture rtl of timestamp_fifo is ...@@ -80,25 +79,10 @@ architecture rtl of timestamp_fifo is
signal sub_result : t_tdc_timestamp; signal sub_result : t_tdc_timestamp;
signal sub_result_latched : t_tdc_timestamp; signal sub_result_latched : t_tdc_timestamp;
signal sub_out_valid_latched : std_logic; signal sub_out_valid_latched : std_logic;
begin
ts_offset_o.tai <= regs_out.offset1_o;
ts_offset_o.coarse <= regs_out.offset2_o;
ts_offset_o.frac <= regs_out.offset3_o(11 downto 0);
reset_seq_o <= regs_out.csr_rst_seq_o;
raw_enable_o <= regs_out.csr_raw_mode_o;
timestamp_with_seq(31 downto 0) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
timestamp_with_seq(63 downto 32) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
timestamp_with_seq(95 downto 64) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
timestamp_with_seq(98 downto 96) <= timestamp_i(g_channel).channel;
timestamp_with_seq(99) <= timestamp_i(g_channel).slope;
timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);
begin
-- Registers decoder
U_WB_Slave : entity work.timestamp_fifo_wb U_WB_Slave : entity work.timestamp_fifo_wb
port map ( port map (
rst_n_i => rst_sys_n_i, rst_n_i => rst_sys_n_i,
...@@ -108,116 +92,148 @@ begin ...@@ -108,116 +92,148 @@ begin
regs_i => regs_in, regs_i => regs_in,
regs_o => regs_out); regs_o => regs_out);
buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10); -- Common parts
ts_offset_o.tai <= regs_out.offset1_o;
ts_offset_o.coarse <= regs_out.offset2_o;
ts_offset_o.frac <= regs_out.offset3_o(11 downto 0);
reset_seq_o <= regs_out.csr_rst_seq_o;
raw_enable_o <= regs_out.csr_raw_mode_o;
ts_match <= timestamp_valid_i(g_channel); -- Enable the fifo part only if the fifo readout is enabled.
gen_fifos: if g_enable generate
timestamp_with_seq(31 downto 0) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).tai), 32));
timestamp_with_seq(63 downto 32) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).coarse), 32));
timestamp_with_seq(95 downto 64) <= std_logic_vector(resize(unsigned(timestamp_i(g_channel).frac), 32));
timestamp_with_seq(98 downto 96) <= timestamp_i(g_channel).channel;
timestamp_with_seq(99) <= timestamp_i(g_channel).slope;
timestamp_with_seq(127 downto 100) <= timestamp_i(g_channel).seq(27 downto 0);
p_fifo_write : process(clk_sys_i) buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
regs_in.fifo_wr_req_i <= '0';
else
if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then ts_match <= timestamp_valid_i(g_channel);
regs_in.fifo_wr_req_i <= '1';
else p_fifo_write : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_sys_n_i = '0' then
regs_in.fifo_wr_req_i <= '0'; regs_in.fifo_wr_req_i <= '0';
else
if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then
regs_in.fifo_wr_req_i <= '1';
else
regs_in.fifo_wr_req_i <= '0';
end if;
end if; end if;
end if; end if;
end if; end process;
end process;
regs_in.fifo_ts0_i <= timestamp_with_seq(31 downto 0);
regs_in.fifo_ts0_i <= timestamp_with_seq(31 downto 0); regs_in.fifo_ts1_i <= timestamp_with_seq(63 downto 32);
regs_in.fifo_ts1_i <= timestamp_with_seq(63 downto 32); regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64);
regs_in.fifo_ts2_i <= timestamp_with_seq(95 downto 64); regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
regs_in.fifo_ts3_i <= timestamp_with_seq(127 downto 96);
p_latch_ref_timestamp : process(clk_sys_i)
p_latch_ref_timestamp : process(clk_sys_i) begin
begin if rising_edge(clk_sys_i) then
if rising_edge(clk_sys_i) then if rst_sys_n_i = '0' or enable_i = '0' then
if rst_sys_n_i = '0' or enable_i = '0' then ref_valid <= '0';
ref_valid <= '0'; else
else -- latch only the last rising edge TS
-- latch only the last rising edge TS if (enable_i = '1' and timestamp_valid_i(ref_channel) = '1') then
if (enable_i = '1' and timestamp_valid_i(ref_channel) = '1') then ref_valid <= '1';
ref_valid <= '1'; ref_ts <= timestamp_i(ref_channel);
ref_ts <= timestamp_i(ref_channel); end if;
end if; end if;
end if; end if;
end if; end process;
end process;
sub_valid <= ref_valid and ts_match;
sub_valid <= ref_valid and ts_match;
U_Subtractor: entity work.tdc_ts_sub
U_Subtractor: entity work.tdc_ts_sub port map (
port map ( clk_i => clk_sys_i,
clk_i => clk_sys_i, rst_n_i => rst_sys_n_i,
rst_n_i => rst_sys_n_i, valid_i => sub_in_valid,
valid_i => sub_in_valid, enable_i => enable_i,
enable_i => enable_i, a_i => timestamp_i(g_channel),
a_i => timestamp_i(g_channel), b_i => ref_ts,
b_i => ref_ts, valid_o => sub_out_valid,
valid_o => sub_out_valid, q_o => sub_result);
q_o => sub_result);
p_latch_deltas : process(clk_sys_i)
p_latch_deltas : process(clk_sys_i) begin
begin if rising_edge(clk_sys_i) then
if rising_edge(clk_sys_i) then if rst_sys_n_i = '0' or enable_i = '0' then
if rst_sys_n_i = '0' or enable_i = '0' then
sub_out_valid_latched <= '0';
else
if regs_out.csr_delta_read_o = '1' then
sub_out_valid_latched <= '0'; sub_out_valid_latched <= '0';
regs_in.delta1_i <= sub_result_latched.tai; else
regs_in.delta2_i <= sub_result_latched.coarse; if regs_out.csr_delta_read_o = '1' then
regs_in.delta3_i <= x"00000" & sub_result_latched.frac; sub_out_valid_latched <= '0';
end if; regs_in.delta1_i <= sub_result_latched.tai;
regs_in.delta2_i <= sub_result_latched.coarse;
if(sub_out_valid = '1') then regs_in.delta3_i <= x"00000" & sub_result_latched.frac;
sub_out_valid_latched <= '1'; end if;
sub_result_latched <= sub_result;
if(sub_out_valid = '1') then
sub_out_valid_latched <= '1';
sub_result_latched <= sub_result;
end if;
end if; end if;
end if; end if;
end if; end process;
end process;
regs_in.csr_delta_ready_i <= sub_out_valid_latched;
regs_in.csr_delta_ready_i <= sub_out_valid_latched;
p_coalesce_irq : process(clk_sys_i)
p_coalesce_irq : process(clk_sys_i) begin
begin if rising_edge(clk_sys_i) then
if rising_edge(clk_sys_i) then if rst_sys_n_i = '0' or enable_i = '0' then
if rst_sys_n_i = '0' or enable_i = '0' then
buf_irq_int <= '0';
else
if(regs_out.fifo_wr_empty_o = '1') then
buf_irq_int <= '0'; buf_irq_int <= '0';
tmr_timeout <= (others => '0');
else else
-- Simple interrupt coalescing : if(regs_out.fifo_wr_empty_o = '1') then
buf_irq_int <= '0';
tmr_timeout <= (others => '0');
else
-- Simple interrupt coalescing :
-- Case 1: There is some data in the buffer
-- (but not exceeding the threshold) - assert the IRQ line after a
-- certain timeout.
if(buf_irq_int = '0') then
if(tmr_timeout = unsigned(irq_timeout_i(9 downto 0))) then
buf_irq_int <= '1';
tmr_timeout <= (others => '0');
elsif(tick_i = '1') then
tmr_timeout <= tmr_timeout + 1;
end if;
end if;
-- Case 1: There is some data in the buffer -- Case 2: amount of data exceeded the threshold - assert the IRQ
-- (but not exceeding the threshold) - assert the IRQ line after a -- line immediately.
-- certain timeout. if(regs_out.fifo_wr_full_o = '1' or (buf_count > unsigned(irq_threshold_i(9 downto 0)))) then
if(buf_irq_int = '0') then
if(tmr_timeout = unsigned(irq_timeout_i(9 downto 0))) then
buf_irq_int <= '1'; buf_irq_int <= '1';
tmr_timeout <= (others => '0');
elsif(tick_i = '1') then
tmr_timeout <= tmr_timeout + 1;
end if; end if;
end if; end if;
-- Case 2: amount of data exceeded the threshold - assert the IRQ
-- line immediately.
if(regs_out.fifo_wr_full_o = '1' or (buf_count > unsigned(irq_threshold_i(9 downto 0)))) then
buf_irq_int <= '1';
end if;
end if; end if;
end if; end if;
end if; end process;
end process;
irq_o <= buf_irq_int;
irq_o <= buf_irq_int; end generate;
-- Disable the fifo part. Unfortunately even when the fifos are disabled we still need a few
-- register of the map.
gen_no_fifos: if not g_enable generate
regs_in.fifo_wr_req_i <= '0';
irq_o <= '0';
regs_in.fifo_ts0_i <= (others => '0');
regs_in.fifo_ts1_i <= (others => '0');
regs_in.fifo_ts2_i <= (others => '0');
regs_in.fifo_ts3_i <= (others => '0');
regs_in.delta1_i <= (others => '0');
regs_in.delta2_i <= (others => '0');
regs_in.delta3_i <= (others => '0');
regs_in.csr_delta_ready_i <= '0';
end generate;
end rtl; end rtl;
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