wr_spec_tdc.xise 103 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
12
    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
13 14
  </header>

Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
15 16 17
  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

  <files>
18 19 20
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="261"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="244"/>
21
    </file>
22 23 24
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="262"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="243"/>
25
    </file>
26 27 28
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="263"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="229"/>
29
    </file>
30 31 32
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="264"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="228"/>
33
    </file>
34 35 36
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="265"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
37
    </file>
38 39 40
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="266"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
41
    </file>
42 43 44
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="267"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
45
    </file>
46 47 48
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="268"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
49
    </file>
50
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
51
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="269"/>
52
      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
53
    </file>
54 55 56
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="270"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
57
    </file>
58 59 60
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="271"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
61
    </file>
62 63 64
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="272"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="173"/>
65
    </file>
66 67 68
    <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
69
    </file>
70 71 72
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="274"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
73
    </file>
74 75 76
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="275"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
77
    </file>
78 79 80
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="276"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="227"/>
81
    </file>
82 83 84
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="277"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
85
    </file>
86 87 88
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="278"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
89
    </file>
90 91 92
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="279"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
93
    </file>
94 95 96
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
97
    </file>
98 99 100
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="281"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
101
    </file>
102 103 104
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="282"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
105
    </file>
106 107 108
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="283"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="242"/>
109
    </file>
110 111 112
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="284"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
113
    </file>
114 115 116
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="285"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
117
    </file>
118 119 120
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="286"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
121
    </file>
122 123 124
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="287"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
125
    </file>
126 127 128
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="288"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
129
    </file>
130 131 132
    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="289"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
133
    </file>
134 135 136
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="290"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
137
    </file>
138 139 140
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="291"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
141
    </file>
142 143 144
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="292"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
145
    </file>
146 147 148
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="293"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
149
    </file>
150 151 152
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="294"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
153
    </file>
154 155 156
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="295"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
157
    </file>
158 159 160
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="296"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
161
    </file>
162 163 164
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="297"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
165
    </file>
166 167 168
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="298"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
169
    </file>
170 171 172
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="299"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
173
    </file>
174 175 176
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="300"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
177
    </file>
178 179 180
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="301"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
181
    </file>
182 183 184
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="302"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
185
    </file>
186 187 188
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="303"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
189
    </file>
190 191 192
    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="304"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
193
    </file>
194 195 196
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="305"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="170"/>
197
    </file>
198 199 200
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="306"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
201
    </file>
202 203 204
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="307"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
205
    </file>
206 207 208
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="308"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
209
    </file>
210 211 212
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="309"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
213
    </file>
214 215 216
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="310"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="226"/>
217
    </file>
218 219 220
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="311"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="241"/>
221
    </file>
222 223 224
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="312"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
225
    </file>
226 227 228
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="313"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
229
    </file>
230 231 232
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="314"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
233
    </file>
234 235 236
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="315"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
237
    </file>
238 239 240
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="316"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
241
    </file>
242 243 244
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="317"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
245
    </file>
246 247 248
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="318"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
249
    </file>
250 251 252
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="319"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
253
    </file>
254 255 256
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="320"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
257
    </file>
258 259 260
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="321"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
261
    </file>
262 263 264
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="322"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
265
    </file>
266 267 268
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="323"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
269
    </file>
270 271 272
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="324"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
273
    </file>
274 275 276
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="325"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
277
    </file>
278 279 280
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="326"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
281
    </file>
282 283 284
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="327"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
285
    </file>
286 287 288
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_metadata/xwb_metadata.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="328"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="248"/>
289
    </file>
290 291 292
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="329"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
293
    </file>
294 295 296
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="330"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
297
    </file>
298 299 300
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="331"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
301
    </file>
302 303 304
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="332"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
305
    </file>
306 307 308
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="333"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
309
    </file>
310 311 312
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="334"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
313
    </file>
314 315 316
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="335"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
317
    </file>
318 319 320
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="336"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
321
    </file>
322 323 324
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="337"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="240"/>
325
    </file>
326 327 328
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_split/xwb_split.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="338"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="239"/>
329
    </file>
330 331 332
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
333
    </file>
334 335 336
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
337
    </file>
338 339 340
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="341"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
341
    </file>
342 343 344
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="342"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
345
    </file>
346 347 348
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="343"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
349
    </file>
350 351 352
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="344"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
353
    </file>
354 355 356
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="345"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
357
    </file>
358 359 360
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="346"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
361
    </file>
362 363 364
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="347"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
365
    </file>
366 367 368
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="348"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="238"/>
369
    </file>
370 371 372
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="349"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
373
    </file>
374 375 376
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="350"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
377
    </file>
378 379 380
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="351"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
381
    </file>
382 383 384
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="352"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
385
    </file>
386 387 388
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="353"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
389
    </file>
390 391 392
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/dma_controller_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="354"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
393
    </file>
394
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
395
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="355"/>
396
      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
397
    </file>
398 399 400
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="356"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
401
    </file>
402 403 404
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="357"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
405
    </file>
406 407 408
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="358"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
409
    </file>
410 411 412
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="359"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
413
    </file>
414 415 416
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="360"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
417
    </file>
418 419 420
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="361"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
421
    </file>
422 423 424
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="362"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
425
    </file>
426 427 428
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="363"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
429
    </file>
430 431 432
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="364"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
433
    </file>
434 435 436
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="365"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
437
    </file>
438 439 440
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="366"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
441
    </file>
442 443 444
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/spartan6/xwb_gn4124_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="367"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="237"/>
445
    </file>
446 447 448
    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="368"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
449
    </file>
450 451 452
    <file xil_pn:name="../../ip_cores/spec/hdl/rtl/sourceid_spec_base_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="369"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="236"/>
453
    </file>
454 455 456
    <file xil_pn:name="../../ip_cores/spec/hdl/rtl/spec_base_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="370"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="235"/>
457
    </file>
458 459 460
    <file xil_pn:name="../../ip_cores/spec/hdl/rtl/spec_base_wr.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="371"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="247"/>
461
    </file>
462 463
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_base_common.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
464
    </file>
465 466
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_base_ddr3.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
467
    </file>
468 469
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_base_onewire.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
470
    </file>
471 472
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_base_spi.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
473
    </file>
474 475
    <file xil_pn:name="../../ip_cores/spec/hdl/syn/common/spec_base_wr.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
476
    </file>
477 478 479
    <file xil_pn:name="../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="377"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
480
    </file>
481 482 483
    <file xil_pn:name="../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="378"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
484
    </file>
485 486 487
    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="379"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
488
    </file>
489 490 491
    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="380"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="234"/>
492
    </file>
493 494 495
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="381"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
496
    </file>
497 498 499
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="382"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
500
    </file>
501 502 503
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="383"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
504
    </file>
505 506 507 508 509 510 511
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="384"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
    </file>
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="385"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
512
    </file>
513 514 515
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="386"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
516
    </file>
517 518 519
    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="387"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="135"/>
520
    </file>
521 522 523
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="388"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
524
    </file>
525 526 527
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_sampler.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="389"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
528
    </file>
529 530 531
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="390"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
532
    </file>
533 534 535
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="391"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="134"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
536
    </file>
537
    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper_sync.vhd" xil_pn:type="FILE_VHDL">
538
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="392"/>
539
      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
540
    </file>
541 542 543
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="393"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
544
    </file>
545 546 547
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="394"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
548
    </file>
549 550 551
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="395"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
552
    </file>
553 554 555
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="396"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
556
    </file>
557 558 559
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="397"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
560
    </file>
561 562 563
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="398"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
564
    </file>
565 566 567
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="399"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
568
    </file>
569 570 571
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="400"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
572
    </file>
573 574 575
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="401"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
576
    </file>
577 578 579
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="402"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
580
    </file>
581 582 583
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="403"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
584
    </file>
585 586 587
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="404"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
588
    </file>
589 590 591
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="405"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
592
    </file>
593 594 595
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="406"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
596
    </file>
597 598 599
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="407"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
600
    </file>
601 602 603
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="408"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
604
    </file>
605 606 607
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="409"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
608
    </file>
609 610 611
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="410"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
612
    </file>
613 614 615
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="411"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
616
    </file>
617 618 619
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="412"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
620
    </file>
621 622 623
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="413"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
624
    </file>
625 626 627
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="414"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
628
    </file>
629 630 631
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="415"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
632
    </file>
633 634 635
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="416"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
636
    </file>
637 638 639
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="417"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
640
    </file>
641 642 643
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="418"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
644
    </file>
645 646 647
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="419"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
648
    </file>
649 650 651
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="420"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
652
    </file>
653 654 655
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="421"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
656
    </file>
657 658 659
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="422"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
660
    </file>
661 662 663
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="423"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
664
    </file>
665 666 667
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="424"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
668
    </file>
669 670 671
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="425"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
672
    </file>
673 674 675
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="426"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
676
    </file>
677 678 679
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="427"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
680
    </file>
681 682 683
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="428"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
684
    </file>
685 686 687
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="429"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
688
    </file>
689 690 691
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="430"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
692
    </file>
693 694 695
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="431"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
696
    </file>
697 698 699
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="432"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
700
    </file>
701 702 703
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="433"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
704
    </file>
705 706 707
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="434"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
708
    </file>
709 710 711
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="435"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
712
    </file>
713 714 715
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="436"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
716
    </file>
717 718 719
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="437"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
720
    </file>
721 722 723
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="438"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
724
    </file>
725 726 727
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="439"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
728
    </file>
729 730 731
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="440"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
732
    </file>
733 734 735
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="441"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
736
    </file>
737
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
738
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="442"/>
739
      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
740
    </file>
741 742 743
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="443"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
744
    </file>
745 746 747
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="444"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
748
    </file>
749 750 751
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="445"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
752
    </file>
753 754 755
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="446"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
756
    </file>
757 758 759
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="447"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
760
    </file>
761 762 763
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_delay.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="448"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
764
    </file>
765
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd" xil_pn:type="FILE_VHDL">
766
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="449"/>
767
      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
768
    </file>
769 770 771
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="450"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
772
    </file>
773 774 775
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="451"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
776
    </file>
777 778 779
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/ts_restore_tai.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="452"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
780
    </file>
781 782 783
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="453"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
784
    </file>
785 786 787
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="454"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
788
    </file>
789 790 791
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="455"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
792
    </file>
793 794 795
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="456"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
796
    </file>
797 798 799
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="457"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
800
    </file>
801 802 803
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="458"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
804
    </file>
805 806 807
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="459"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
808
    </file>
809 810 811
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="460"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
812
    </file>
813 814 815
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="461"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
816
    </file>
817 818 819
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="462"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
820
    </file>
821 822 823
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="463"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
824
    </file>
825 826 827
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="464"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
828
    </file>
829 830 831
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="465"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
832
    </file>
833 834 835
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="466"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
836
    </file>
837 838 839
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="467"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
840
    </file>
841 842 843
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="468"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
844
    </file>
845 846 847
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="469"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
848
    </file>
849 850 851
    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="470"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
852
    </file>
853 854
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_icon.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
855
    </file>
856 857
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_spartan6_ila.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
858
    </file>
859 860 861
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="473"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
862
    </file>
863 864 865
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="474"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
866
    </file>
867 868 869
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="475"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
870
    </file>
871 872 873
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="476"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
874
    </file>
875 876 877
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="477"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
878
    </file>
879 880 881
    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="478"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
882
    </file>
883 884 885
    <file xil_pn:name="../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="479"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
886
    </file>
887 888 889
    <file xil_pn:name="../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="480"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
890
    </file>
891 892 893
    <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="481"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="233"/>
894
    </file>
895 896 897
    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="482"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
898
    </file>
899 900 901
    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="483"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
902
    </file>
903 904 905
    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="484"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
906
    </file>
907 908 909
    <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="485"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
910
    </file>
911
    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
912
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="486"/>
913
      <association xil_pn:name="Implementation" xil_pn:seqID="232"/>
914
    </file>
915 916 917
    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="487"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
918
    </file>
919 920 921
    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="488"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
922
    </file>
923 924 925
    <file xil_pn:name="../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="489"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="231"/>
926
    </file>
927 928 929 930 931 932 933 934 935 936 937
    <file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="490"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="246"/>
    </file>
    <file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="491"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
    </file>
    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="492"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
938
    </file>
939
    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
940
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="493"/>
941
      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
942
    </file>
943 944 945
    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="494"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
946
    </file>
947 948 949
    <file xil_pn:name="../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="495"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
950
    </file>
951 952 953
    <file xil_pn:name="../../rtl/reg_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="496"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
954
    </file>
955 956 957
    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="497"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
958
    </file>
959 960 961
    <file xil_pn:name="../../rtl/tdc_buffer_control_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="498"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
962
    </file>
963 964 965
    <file xil_pn:name="../../rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="499"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
966
    </file>
967 968 969
    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="500"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
970
    </file>
971 972 973
    <file xil_pn:name="../../rtl/tdc_dma_channel.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="501"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="179"/>
974
    </file>
975 976 977
    <file xil_pn:name="../../rtl/tdc_dma_engine.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="502"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
978
    </file>
979 980 981
    <file xil_pn:name="../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="503"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
982
    </file>
983 984 985
    <file xil_pn:name="../../rtl/tdc_onewire_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="504"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
986
    </file>
987 988 989
    <file xil_pn:name="../../rtl/tdc_onewire_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="505"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="178"/>
990
    </file>
991 992 993
    <file xil_pn:name="../../rtl/tdc_ts_addsub.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="506"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
994
    </file>
995 996 997
    <file xil_pn:name="../../rtl/tdc_ts_sub.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="507"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
998
    </file>
999 1000 1001
    <file xil_pn:name="../../rtl/timestamp_convert_filter.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="508"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
Evangelia Gousiou's avatar
Evangelia Gousiou committed
1002
    </file>
1003 1004 1005
    <file xil_pn:name="../../rtl/timestamp_fifo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="509"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
1006
    </file>
1007 1008 1009
    <file xil_pn:name="../../rtl/timestamp_fifo_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="510"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
1010
    </file>
1011 1012 1013
    <file xil_pn:name="../../rtl/timestamp_fifo_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="511"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
1014
    </file>
1015 1016 1017
    <file xil_pn:name="../../rtl/wbgen2_eic_nomask.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="512"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
1018
    </file>
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
    <file xil_pn:name="../../rtl/wrabbit_sync.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="513"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
    </file>
    <file xil_pn:name="buildinfo_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="514"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="230"/>
    </file>
    <file xil_pn:name="sourceid_wr_spec_tdc_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="515"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="245"/>
    </file>
    <file xil_pn:name="../../top/spec/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
1032
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
Evangelia Gousiou's avatar
Evangelia Gousiou committed
1033
    </file>
1034 1035 1036 1037
    <file xil_pn:name="../../top/spec/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="517"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="249"/>
    </file>
1038 1039
  </files>

Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
  <properties>
    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
1065
    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076
    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
1077
    <property xil_pn:name="Consider Include Files in Search" xil_pn:value="false" xil_pn:valueState="default"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104
    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
1105 1106
    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
Tomasz Wlostowski's avatar
Tomasz Wlostowski committed
1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
1118
    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>