dma_eic
GN4124 DMA enhanced interrupt controller
Enhanced interrrupt controller for GN4124 DMA.
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. Interrupt disable register
3.2. Interrupt enable register
3.3. Interrupt mask register
3.4. Interrupt status register
5. Interrupts
5.1. DMA done interrupt
5.2. DMA error interrupt
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⇒
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wb_adr_i[3:0]
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DMA done interrupt:
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⇒
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wb_dat_i[31:0]
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irq_dma_done_i
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←
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⇐
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wb_dat_o[31:0]
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→
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wb_cyc_i
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DMA error interrupt:
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⇒
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wb_sel_i[3:0]
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irq_dma_error_i
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←
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→
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wb_stb_i
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→
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wb_we_i
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←
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wb_ack_o
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←
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wb_err_o
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←
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wb_rty_o
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←
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wb_stall_o
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←
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wb_int_o
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HW prefix:
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dma_eic_eic_idr
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HW address:
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0x8
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C prefix:
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EIC_IDR
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C offset:
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0x20
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Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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-
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-
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-
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15
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14
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13
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12
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11
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10
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9
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8
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-
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-
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-
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-
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-
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-
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-
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-
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7
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6
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5
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4
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3
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2
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1
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0
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-
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-
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-
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-
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-
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-
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DMA_ERROR
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DMA_DONE
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-
DMA_DONE
[write-only]: DMA done interrupt
write 1: disable interrupt 'DMA done interrupt'
write 0: no effect
-
DMA_ERROR
[write-only]: DMA error interrupt
write 1: disable interrupt 'DMA error interrupt'
write 0: no effect
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HW prefix:
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dma_eic_eic_ier
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HW address:
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0x9
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C prefix:
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EIC_IER
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C offset:
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0x24
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Writing 1 enables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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-
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-
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-
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15
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14
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13
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12
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11
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10
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9
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8
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-
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-
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-
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-
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-
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-
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-
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-
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7
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6
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5
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4
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3
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2
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1
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0
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-
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-
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-
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-
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-
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-
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DMA_ERROR
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DMA_DONE
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-
DMA_DONE
[write-only]: DMA done interrupt
write 1: enable interrupt 'DMA done interrupt'
write 0: no effect
-
DMA_ERROR
[write-only]: DMA error interrupt
write 1: enable interrupt 'DMA error interrupt'
write 0: no effect
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HW prefix:
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dma_eic_eic_imr
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HW address:
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0xa
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C prefix:
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EIC_IMR
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C offset:
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0x28
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Shows which interrupts are enabled. 1 means that the interrupt associated with the bitfield is enabled
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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-
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-
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-
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15
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14
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13
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12
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11
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10
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9
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8
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-
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-
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-
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-
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-
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-
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-
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-
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7
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6
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5
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4
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3
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2
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1
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0
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-
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-
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-
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-
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-
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-
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DMA_ERROR
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DMA_DONE
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-
DMA_DONE
[read-only]: DMA done interrupt
read 1: interrupt 'DMA done interrupt' is enabled
read 0: interrupt 'DMA done interrupt' is disabled
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DMA_ERROR
[read-only]: DMA error interrupt
read 1: interrupt 'DMA error interrupt' is enabled
read 0: interrupt 'DMA error interrupt' is disabled
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HW prefix:
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dma_eic_eic_isr
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HW address:
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0xb
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C prefix:
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EIC_ISR
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C offset:
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0x2c
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Each bit represents the state of corresponding interrupt. 1 means the interrupt is pending. Writing 1 to a bit clears the corresponding interrupt. Writing 0 has no effect.
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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-
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-
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-
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15
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14
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13
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12
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11
|
10
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9
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8
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-
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-
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-
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-
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-
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-
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-
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-
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7
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6
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5
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4
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3
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2
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1
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0
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-
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-
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-
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-
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-
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-
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DMA_ERROR
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DMA_DONE
|
-
DMA_DONE
[read/write]: DMA done interrupt
read 1: interrupt 'DMA done interrupt' is pending
read 0: interrupt not pending
write 1: clear interrupt 'DMA done interrupt'
write 0: no effect
-
DMA_ERROR
[read/write]: DMA error interrupt
read 1: interrupt 'DMA error interrupt' is pending
read 0: interrupt not pending
write 1: clear interrupt 'DMA error interrupt'
write 0: no effect
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HW prefix:
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dma_eic_dma_done
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C prefix:
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DMA_DONE
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Trigger:
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rising edge
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DMA done interrupt line (rising edge sensitive).
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HW prefix:
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dma_eic_dma_error
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C prefix:
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DMA_ERROR
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Trigger:
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rising edge
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DMA error interrupt line (rising edge sensitive).