H/W Address | Type | Name | VHDL/Verilog prefix | C prefix |
---|---|---|---|---|
0x0 | REG | Control/Status register | tdc_buf_csr | CSR |
0x1 | REG | Current buffer base address register | tdc_buf_cur_base | CUR_BASE |
0x2 | REG | Current buffer base count register | tdc_buf_cur_count | CUR_COUNT |
0x3 | REG | Current buffer base size/valid flag register | tdc_buf_cur_size | CUR_SIZE |
0x4 | REG | Next buffer base address register | tdc_buf_next_base | NEXT_BASE |
0x5 | REG | Next buffer base size/valid flag register | tdc_buf_next_size | NEXT_SIZE |
⇒ | wb_adr_i[2:0] | Control/Status register: | ||
⇒ | wb_dat_i[31:0] | tdc_buf_csr_enable_o | → | |
⇐ | wb_dat_o[31:0] | tdc_buf_csr_irq_timeout_o[9:0] | ⇒ | |
→ | wb_cyc_i | tdc_buf_csr_burst_size_o[9:0] | ⇒ | |
⇒ | wb_sel_i[3:0] | tdc_buf_csr_switch_buffers_o | → | |
→ | wb_stb_i | tdc_buf_csr_done_o | → | |
→ | wb_we_i | tdc_buf_csr_done_i | ← | |
← | wb_ack_o | tdc_buf_csr_done_load_o | → | |
← | wb_err_o | tdc_buf_csr_overflow_o | → | |
← | wb_rty_o | tdc_buf_csr_overflow_i | ← | |
← | wb_stall_o | tdc_buf_csr_overflow_load_o | → | |
Current buffer base address register: | ||||
tdc_buf_cur_base_o[31:0] | ⇒ | |||
tdc_buf_cur_base_i[31:0] | ⇐ | |||
tdc_buf_cur_base_load_o | → | |||
Current buffer base count register: | ||||
tdc_buf_cur_count_i[31:0] | ⇐ | |||
Current buffer base size/valid flag register: | ||||
tdc_buf_cur_size_size_o[29:0] | ⇒ | |||
tdc_buf_cur_size_size_i[29:0] | ⇐ | |||
tdc_buf_cur_size_size_load_o | → | |||
tdc_buf_cur_size_valid_o | → | |||
tdc_buf_cur_size_valid_i | ← | |||
tdc_buf_cur_size_valid_load_o | → | |||
Next buffer base address register: | ||||
tdc_buf_next_base_o[31:0] | ⇒ | |||
tdc_buf_next_base_i[31:0] | ⇐ | |||
tdc_buf_next_base_load_o | → | |||
Next buffer base size/valid flag register: | ||||
tdc_buf_next_size_size_o[29:0] | ⇒ | |||
tdc_buf_next_size_size_i[29:0] | ⇐ | |||
tdc_buf_next_size_size_load_o | → | |||
tdc_buf_next_size_valid_o | → | |||
tdc_buf_next_size_valid_i | ← | |||
tdc_buf_next_size_valid_load_o | → |
HW prefix: | tdc_buf_csr |
HW address: | 0x0 |
C prefix: | CSR |
C offset: | 0x0 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
- | - | - | - | - | - | - | - |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | ||||
OVERFLOW | DONE | SWITCH_BUFFERS | BURST_SIZE[9:5] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||||||
BURST_SIZE[4:0] | IRQ_TIMEOUT[9:7] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||||||
IRQ_TIMEOUT[6:0] | ENABLE |
HW prefix: | tdc_buf_cur_base |
HW address: | 0x1 |
C prefix: | CUR_BASE |
C offset: | 0x4 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
CUR_BASE[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
CUR_BASE[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
CUR_BASE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
CUR_BASE[7:0] |
HW prefix: | tdc_buf_cur_count |
HW address: | 0x2 |
C prefix: | CUR_COUNT |
C offset: | 0x8 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
CUR_COUNT[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
CUR_COUNT[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
CUR_COUNT[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
CUR_COUNT[7:0] |
HW prefix: | tdc_buf_cur_size |
HW address: | 0x3 |
C prefix: | CUR_SIZE |
C offset: | 0xc |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
- | VALID | SIZE[29:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
SIZE[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
SIZE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
SIZE[7:0] |
HW prefix: | tdc_buf_next_base |
HW address: | 0x4 |
C prefix: | NEXT_BASE |
C offset: | 0x10 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||||
NEXT_BASE[31:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
NEXT_BASE[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
NEXT_BASE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
NEXT_BASE[7:0] |
HW prefix: | tdc_buf_next_size |
HW address: | 0x5 |
C prefix: | NEXT_SIZE |
C offset: | 0x14 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |||||
- | VALID | SIZE[29:24] |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |||||||
SIZE[23:16] |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |||||||
SIZE[15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |||||||
SIZE[7:0] |