fmc_tdc_direct_readout_wb_slave

TDC Direct Readout WB Slave

Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Channel Enable Register
3.2. Dead Time Register
3.3. FIFO 'Readout FIFO' data output register 0
3.4. FIFO 'Readout FIFO' data output register 1
3.5. FIFO 'Readout FIFO' data output register 2
3.6. FIFO 'Readout FIFO' control/status register

1. Memory map summary

H/W Address Type Name VHDL/Verilog prefix C prefix
0x0 REG Channel Enable Register dr_chan_enable CHAN_ENABLE
0x1 REG Dead Time Register dr_dead_time DEAD_TIME
0x2 FIFOREG FIFO 'Readout FIFO' data output register 0 dr_fifo_r0 FIFO_R0
0x3 FIFOREG FIFO 'Readout FIFO' data output register 1 dr_fifo_r1 FIFO_R1
0x4 FIFOREG FIFO 'Readout FIFO' data output register 2 dr_fifo_r2 FIFO_R2
0x5 REG FIFO 'Readout FIFO' control/status register dr_fifo_csr FIFO_CSR

2. HDL symbol

wb_adr_i[2:0] Readout FIFO:
wb_dat_i[31:0] dr_fifo_wr_req_i
wb_dat_o[31:0] dr_fifo_wr_full_o
wb_cyc_i dr_fifo_wr_empty_o
wb_sel_i[3:0] dr_fifo_wr_usedw_o[7:0]
wb_stb_i dr_fifo_seconds_i[31:0]
wb_we_i dr_fifo_cycles_i[31:0]
wb_ack_o dr_fifo_bins_i[17:0]
wb_err_o dr_fifo_edge_i
wb_rty_o dr_fifo_channel_i[3:0]
wb_stall_o  
Channel Enable Register:
dr_chan_enable_o[4:0]
 
Dead Time Register:
dr_dead_time_o[23:0]
 
FIFO 'Readout FIFO' data output register 0:
 
FIFO 'Readout FIFO' data output register 1:
 
FIFO 'Readout FIFO' data output register 2:

3. Register description

3.1. Channel Enable Register

HW prefix: dr_chan_enable
HW address: 0x0
C prefix: CHAN_ENABLE
C offset: 0x0
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - CHAN_ENABLE[4:0]

3.2. Dead Time Register

HW prefix: dr_dead_time
HW address: 0x1
C prefix: DEAD_TIME
C offset: 0x4
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
DEAD_TIME[23:16]
15 14 13 12 11 10 9 8
DEAD_TIME[15:8]
7 6 5 4 3 2 1 0
DEAD_TIME[7:0]

3.3. FIFO 'Readout FIFO' data output register 0

HW prefix: dr_fifo_r0
HW address: 0x2
C prefix: FIFO_R0
C offset: 0x8
31 30 29 28 27 26 25 24
SECONDS[31:24]
23 22 21 20 19 18 17 16
SECONDS[23:16]
15 14 13 12 11 10 9 8
SECONDS[15:8]
7 6 5 4 3 2 1 0
SECONDS[7:0]

3.4. FIFO 'Readout FIFO' data output register 1

HW prefix: dr_fifo_r1
HW address: 0x3
C prefix: FIFO_R1
C offset: 0xc
31 30 29 28 27 26 25 24
CYCLES[31:24]
23 22 21 20 19 18 17 16
CYCLES[23:16]
15 14 13 12 11 10 9 8
CYCLES[15:8]
7 6 5 4 3 2 1 0
CYCLES[7:0]

3.5. FIFO 'Readout FIFO' data output register 2

HW prefix: dr_fifo_r2
HW address: 0x4
C prefix: FIFO_R2
C offset: 0x10
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- CHANNEL[3:0] EDGE BINS[17:16]
15 14 13 12 11 10 9 8
BINS[15:8]
7 6 5 4 3 2 1 0
BINS[7:0]

3.6. FIFO 'Readout FIFO' control/status register

HW prefix: dr_fifo_csr
HW address: 0x5
C prefix: FIFO_CSR
C offset: 0x14
31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - EMPTY FULL
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
USEDW[7:0]