SVEC TDC Release 7.0
Binary
Memory map
See the "SVEC Memory Map" section of the Gateware Architecture Manual
Sources
Release date
19.12.2017
Release notes
Important changes:
- Redesigned clock tree. Now the Wishbone port of the TDC core is operating in the common system clock domain (no cross-clock transfer needed).
- Redesigned readout: separate per-channel FIFO instead of a circular buffer.
- Added last received pulse timestamp registers.
- Added hardware timestamp sequencing.
- Added per-channel input enable.
- Updated the WR Core to the latest v4.2.
- Updated the VM64x-core to the latest v2.0.
- Dropped the non-WR version of the firmware.
_Back to the gateware release page_
T.Wlostowski, Greg Daniluk, 19 December 2017