FMC TDC 1ns 5cha - Gateware:master commitshttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commits/master2017-12-19T13:27:30Zhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/b10c63a4835259b730abbe0ef98b629e0ef29730Merge branch 'greg-wrpc-v4.2'2017-12-19T13:27:30ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/c8b144e8faacde4c9e31abf7e9b2851712c33a45update xilinx project files for SPEC and SVEC2017-12-19T13:26:56ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/04550a4d7e618cba9e6847c3b725cd1a38ae8f24update submodules to use WRPC v4.2 release2017-12-18T22:48:18ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d6596ec5df7cc8b3753f99012e7eb32da6f6da20svec: use the latest v2.0 vme64x-core release2017-12-18T22:47:40ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/0109fa2b6af76a6fe1346593dee770500df4cfectop/spec: disconnect WRPC from FMC EEPROM, now we use Flash2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/fb772c1d27ac78ed1e65c95a1c03d950f59ef925top/spec: cleanup indentation, remove unused signals2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/02083afae73b254ac552f54b9961e5913d53e25etop/spec: reorganized to use WRPC Board wrapper2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/3a1b732786c83c2d93e9927100d80b7149bbf039top/svec: bool2int function is now in general_cores2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/4f827cec522d6723014027421aafd798b5fe778atop/svec: disconnect WRPC from FMC EEPROM, now we use Flash2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/4c7d3f56ebc1b272fbbf99991d7a6bfc2bb1c8b7top/svec: cleanup indentation and remove unused signals2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6185eb76bcf1e2a43b6585b004db60fdb6e3187etop/svec: reorganized to use WRPC Board wrapper2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/e665f6c13702a06fc7f8acdae6aab3fa5bbcb749update wr-cores2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/48f0a742e2505a4e7300f9ef0477f107e63d9192top/spec: cleanup, ports rename2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/98bb71d946c6a91c553f75c58d86ffa81948d0a3adding etherbone submodule (needed for WR board wrapper)2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/86a9d8950e5edebc7b6c107a1d7323a259d687b9update vme64x-core to the latest one by Tristan2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/5ee897b8ae8ba47089cd3c39761342eb2f6548d4svec: vme ports to lower case2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/269cc7d1608d7b60b29d80fd7d0a3d050fff13caupdate general-cores to match wr-cores v4.2rc2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/52395a8eecf184017d6289201df06dc5f5180271update wr-cores to the latest proposed_master2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/e49fb3dc39d4e27efcab7f8fdfabed53468f2ed4svec: output 1-PPS to LEMO2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6b5e46a86d1271283ca77b893c437455ef210469svec_tdc: add SPI Flash and 1-PPS out signals2017-12-11T14:00:26ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/572973e607bd7f7086fa07dba23d67a4ef2dc917Uploaded v7.0 sources with wrpc v 4.12017-12-11T14:00:26ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d4e10fafa32c804ef6a2406ca6a35d3f3515bb18fmc_tdc_core: decrease timestamp FIFO size to 512 (so that it fits in the SPE...2017-12-11T13:58:13ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/b2433b14aec72bdc806c6430dd0766692a613a10update wrc.ram for spec to fix DAC range problem on some SPECs2017-03-08T08:53:36ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/7b2bad61e2532f425871f0a44a0c772d81857f3finclude WRPC LM32 firmware v2.1 for SVEC2017-01-17T16:16:10ZEvangelia Gousiouegousiou@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/8597e333f13c1b56d40242b23ab3286458b32a1dinclude WRPC LM32 firmware v2.12017-01-17T09:23:06ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/4d681a60ce75e4cdb6f8a268fbc15cec9877a04aadding Xilinx ISE project file for SPEC2017-01-17T09:15:15ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/1170651f8ca0d61be7702257cf19d128b7714f63update gennum core version2017-01-17T09:15:05ZGrzegorz Danilukgrzegorz.daniluk@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/3b60a1ece3a179d24d1c983eb9e7e2f603c3764btop: updated synthesis descriptors2015-05-22T09:17:59ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/5765c94d3f0b118adcc9bfea880aca75ecef6001hdl: SPEC top level with refurbished TDC core2015-05-19T08:05:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/caaf87ad18e30a1c06016076454af3cf5d893c0atop/spec: removed non-WR top level2015-05-18T21:13:08ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/c2a10e64a6678d357f1f3f47f7e9f310e6d69be3hdl: independent FIFO buffers per channel - top level verified on the SVEC2015-04-29T12:31:21ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/8b8002319edd2ee8acf93d28cd87176d8f379737first version with per-channel FIFOs instead of a shared circular buffer2015-04-14T15:59:32ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/4e08d33baa719a8d5747d80df41ab54e8dba4871fmc_tdc_wrapper: squeezed direct readout into 64kB address range2015-04-10T14:21:11ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/8600d4e25a9e76f3032b16049aa6b6fcfd281224hdl/syn/svec: added missing Manifest file2015-04-10T12:22:23ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/5ae41634d85ed2ee1e26cec70f9788e108285663hdl: use proposed_master of general-cores2015-04-10T12:21:30ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d23de3f53ef1e5cb35afe2f6da2681d7cb9736f9hdl: various fixes:2015-04-09T09:43:28ZTomasz Włostowskitomasz.wlostowski@cern.ch- squeezed A24 address range to 0.5 MB (to fit a full 24-slot VME crate with TDCs)
- fixed IRQ line synchronization issuehttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/35b478e1b1216e7f62569a81d5ac75fe5cbd6ce8hdl/ip_cores: use latest VME core2015-04-09T09:16:51ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/92b7f5e72f1247ce19b99a82d12718521d6d165etop/svec: single, WR-only top level2015-04-03T13:43:32ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/3ee4e288a90af5794ce9a63f07fd7fa4e9e0aec5fixed .gitignore2015-03-26T13:36:14ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/389734e7e2f7f71a981b0e08906814d418c4eef0testbench: sample top level testbench for SVEC2015-03-26T13:35:54ZTomasz Włostowskitomasz.wlostowski@cern.ch