FMC TDC 1ns 5cha - Gateware:dlamprid-dev commitshttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commits/dlamprid-dev2019-09-29T20:36:51Zhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/e66d3b45345e1c518697ad5574f80cb825527465[hdl] move offset calculation outside of channel generation loop.2019-09-29T20:36:51ZDimitris Lampridisdimitris.lampridis@cern.ch
This reduces the required resources since we only use one set of adders for all channels (instead of one per).
There is no issue with multiple timestamps arriving simultaneously, since the previous stages serialise the
delivery of timestamps and this stage is fully pipelined, so it can process one timestamp per cycle.https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d693db67e70e07d2fdea3bcf1b7f3577ae515b38[hdl] do not filter out falling edges in direct readout. This can be done if…2019-09-29T20:36:08ZDimitris Lampridisdimitris.lampridis@cern.ch[hdl] do not filter out falling edges in direct readout. This can be done if necessary by setting the relevant ACAM registers
https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/242740999a629035c62f686a7e1f3141e71591ab[hdl] [bugfix] fix (again) offset calculation2019-09-29T20:33:27ZDimitris Lampridisdimitris.lampridis@cern.ch
Previous fix did not correctly account for when the most significant bit of a.frac was '1', as it would incorrectly consider it as a negative number.
Also updated the header notes.https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/31e4f6f5afe6446ac362471881bad4a39255f578[hdl] [bugfix] clean up leftover code causing multiple fake timestamps being ...2019-09-28T09:28:43ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/aa3a163b79d38bb58a14a9410abc16e442fc124a[hdl] Split channel CSR from FIFO readout. *PLEASE TEST g_use_fifo_readout mo...2019-09-27T08:59:58ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d5ef17f8130fe9d9718a799a2923487e2d89811b[hdl] stop using an async FIFO for direct readout, timestamps are already in ...2019-09-27T08:59:58ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/b5bc6601451950c6a04413fed92e2de59252b5bc[hdl] use the same timestamp data path for fifo_readout, dma_readout and dire...2019-09-27T08:59:53ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6ed2a2562181ec283a130bd4f4b6b0133115c47d[hdl] make pulse width filtering optional2019-09-26T17:16:10ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/97684cd32139171facf33b5e33b07782fdb6c1b7[hdl] isolate sequence counter in separate process and move it after the offs...2019-09-26T17:16:05ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6409e0efb96a60393dee174f6b3dd51f394abc22[hdl] stop passing the timestamps from all five channels to each FIFO2019-09-26T11:22:53ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6cdecdbadfbd9711364da000aaa2a8c2911afb29[hdl] [bugfix] Properly sign-extend timestamp values in timestamp adder/subtr...2019-09-26T09:50:30ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/7b243fd4a1bd21f60c04676225c3ed45ca9e0c6e[hdl] [bugfix] Fix overflow/underflow check in timestamp adder/subtractor2019-09-26T09:49:15ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/84ffc99fcd77897a9610b7736a2f95a353d10717Update submodules. Please test!2019-05-24T12:20:05ZDimitris Lampridisdimitris.lampridis@cern.ch
The following changes were done:
1. Point all submodules to new OHWR
2. update ddr3-sp6-core to latest master because the previous commit
(8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test!
3. remove etherbone-core
4. update general-cores to latest master and use the updated gc_ds182x_readout modulehttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/8d26f09308c4c1302a40ac840f90dc2c299df70cImprove simulation speed by reducing PPS period2019-05-24T12:08:38ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d56f09c3b888df7c542fa1ef533a0ccf25e9fdc7fix direct timestamp mapping after latest changes2019-05-24T12:07:43ZDimitris Lampridisdimitris.lampridis@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/b69e7d0cb8531ec7c1c9f6063c776af9642ca4betop/spec: enable FIFO readout following addition of the corresponding generic2018-09-21T09:23:03ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/7b5a81bec478728c039c4693cdac8b2264949debhdl: clean up rewritten start retrigger unit2018-09-21T08:49:44ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/94b0709ec889b4f0d08f3190bcecc100d0e3f8datestbench: initial version of SPEC tb2018-09-21T08:30:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/3164f18635aa16f6a848cd159de338501d03f92btestbench: crude ACAM I-mode SV model2018-09-21T08:29:43ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/c0e6db665c0a956556d1f6905dc5d0f73b27d620fmc_tdc_core: rewrite the bloody f****ing crap called 'start_retrigger_block'...2018-09-21T08:29:09ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/d0dc3163373fa3f6c29523b0a207f376445119f3hdl: change TEST1 register layout2018-09-21T08:27:50ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/a388eab5ebefcfa2cb02d590209a13cc08eb824dhdl: make FIFO readout and EIC optional2018-09-21T08:27:31ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/abad9a6f47e3f6093e6259e1afd61b8d759aadd5hdl: post-merge fixes, brought back direct readout interface2018-09-17T12:09:49ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/8cb0063144f72d5cf4e145e56f98623ed1b55e32Merge branch 'tom-sep16' into tom-tmp-sep172018-09-17T11:53:03ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/264a637336d92ba6b87714fb9a37887a7faf977dacam_databus_interface: remove unused ports2018-09-17T10:09:50ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/062157266508ccacb5a6eb32ab1d45fd29454429updated submodules2018-09-16T22:22:46ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/df0daab8c32ceb8197d0666fb9dd7887923f3fe7spec: relaxed FIFO timing2018-09-16T22:22:21ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/1e6474461aa25c1008cc56636b3e0cf92420117cfmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line…2018-09-16T22:21:40ZTomasz Włostowskitomasz.wlostowski@cern.chfmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bug
https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/e0addd9d9b0a3656353dcffc0753a12e0391d3c0hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use…2018-09-16T22:20:45ZTomasz Włostowskitomasz.wlostowski@cern.chhdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead
https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/1e074bd0137a4a7d4b4c779448e0d6aeadd2afc6acam_databus_interface: fix combinatorial loop on reset (a typo in fact)2018-09-16T22:19:58ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/f1aadd5f1c0ab1302c0f0e5e28384eb03f73d53ertl/data_engine: don't use possibly metastable ef1_meta/ef2_meta signals.2018-09-12T11:58:10ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/5818355eeb5c18ac1854f802c2744749d21275fcrtl/acam_databus_interface: make design fully synchronous, extend read cycle…2018-09-12T09:33:22ZTomasz Wlostowskitomasz.wlostowski@cern.chrtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/ea9db60d0e6864a47a28863fcccb9273f607bac2syn/spec: updated ISE project2018-09-11T12:36:19ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/b1a6f959a7ce7b18f060906bba8c153f81731f8dtop/spec: re-enabled WR support, signal integrity improvements2018-09-11T12:36:01ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/44e726464d8d0dbf6b859c5d52eae47a6205526crtl: replace Sockit onewire master with a hardware DS18xx interface, clean up...2018-09-11T12:33:22ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/fc5df2b2d97aa196df91ae91ddb9b6039c3f9473rtl: store debug metadata in upper 20 bits of frac field, added raw readout m...2018-09-11T12:31:27ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/bb0af513b30407fd7c55effc15e72d5287644e86rtl: clean up debug metadata and pass it to the DMA engine2018-09-11T12:29:59ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/6e2113b94dd2922bacf44fade4aefd0b38eafe4frtl/leds_manager: adapt to new readout model and simplify code2018-09-11T12:27:28ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/70171d1374db942ed071b579a5332dce0c08f3e0rtl/data_formatting: clean up temporary debugging code2018-09-11T12:26:59ZTomasz Wlostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-tdc-1ns-5cha-gw/commit/2dcf1100f74e6b63fd4e555e60257902ccc92176rtl/data_engine: don't use possibly metastable ef1_meta/ef2_meta signals.2018-09-11T12:26:23ZTomasz Wlostowskitomasz.wlostowski@cern.ch