testbench/spec: Tom's work on DMA

- initialize TDC DMA Engine (buffer controller) - reset the SPEC/DDR contoller prior to operation (still wip) - feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time. This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented. Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..

testbench/spec: Tom's work on DMA
- initialize TDC DMA Engine (buffer controller) - reset the SPEC/DDR contoller prior to operation (still wip) - feed the design with fake timestamps bypassing ACAM, let's debug one thing at a time. This is a WIP commit, I see the core writing the timestamps to the DDR, but the Gennum-side DMA as well as double-buffering of the DDR timestamps is yet to be implemented. Note: I've never managed to simulate DMA with the crappy Gennum VHDL model. I guess we need to fix it or write a new one..
ffbd8dd8 · Tomasz Wlostowski · 9c68bf4e · ffbd8dd8 · ffbd8dd8 · ffbd8dd8
Commit ffbd8dd8 authored Apr 24, 2020 by Tomasz Wlostowski
Hide whitespace changes
Inline Side-by-side

Showing with 939 additions and 182 deletions

buildinfo_pkg.vhd hdl/testbench/spec/buildinfo_pkg.vhd +3 -3

main.sv hdl/testbench/spec/main.sv +276 -62

wave.do hdl/testbench/spec/wave.do +660 -117

No files found.
--- a/hdl/testbench/spec/buildinfo_pkg.vhd
+++ b/hdl/testbench/spec/buildinfo_pkg.vhd
@@ -6,8 +6,8 @@ package buildinfo_pkg is
  constant buildinfo : string :=
       "buildinfo:1" & LF
     & "module:main" & LF
-     & "commit:29c1fdd2e474c7bdb52e11db26e94b502814290e" & LF
+     & "commit:745e912cee76d4ee9e8c3fded1c9ee9b5e694cdd" & LF
     & "syntool:modelsim" & LF
-     & "syndate:2020-04-24, 17:39 CEST" & LF
-     & "synauth:Evangelia Gousiou" & LF;
+     & "syndate:2020-04-24, 22:37 CEST" & LF
+     & "synauth:Tomasz Wlostowski" & LF;
 end buildinfo_pkg;
--- a/hdl/testbench/spec/main.sv
+++ b/hdl/testbench/spec/main.sv
@@ -6,10 +6,19 @@
 `include "vic_wb.vh"
 `include "dma_controller_wb.vh"

+`include "regs/tdc_buffer_control_regs.vh"
+`include "regs/spec_base_regs.vh"

 `include "gn4124_bfm.svh"
 `include "acam_model.svh"

+`undef USE_ACAM_MODEL
+
+import tdc_core_pkg::*;
+
+
+`define SPEC_CSR_BASE 'h0000
+
 `define DMA_BASE 'h00c0
 `define VIC_BASE 'h0100

@@ -30,10 +39,58 @@ typedef struct {

 typedef fmc_tdc_timestamp_t fmc_tdc_timestamp_queue_t[$];

+class FakeTimestampGenerator;
+   protected fmc_tdc_timestamp_queue_t m_queue;
+   protected int m_seq, m_channel;
+
+
+   function new(int channel);
+      m_channel = channel;
+      m_seq = 0;
+   endfunction // new
+   
+
+   
+   function automatic fmc_tdc_timestamp_queue_t get_queue();
+      return m_queue;
+   endfunction // get_queue
+   
+   function automatic t_tdc_timestamp generate_hw_timestamp(  int slope = 0);
+      fmc_tdc_timestamp_t ts;
+      t_tdc_timestamp ts_hw;
+      
+      ts.tai = $random % 10000;
+      ts.coarse = $random % 125000000;
+      ts.frac = $random % 4096;
+      ts.seq = m_seq;
+      ts.slope = slope;
+      ts.channel = m_channel;
+
+      ts_hw.tai = ts.tai;
+      ts_hw.coarse = ts.coarse;
+      ts_hw.frac = ts.frac;
+      ts_hw.channel = ts.channel;
+      ts_hw.slope = ts.slope;
+      ts_hw.seq = ts.seq;
+      
+      m_seq++;
+      return ts_hw;
+   endfunction // generate_hw_timestamp
+   
+   
+   
+endclass // FakeTimestampGenerator
+
+
 class FmcTdcDriver;
   CBusAccessor m_acc;
   uint64_t     m_base;

+   protected const uint32_t BASE_DMA = 'h6000;
+   protected const uint32_t TDC_CHANNEL_BUFFER_SIZE_BYTES = 'h1000;
+
+   protected const int dma_buf_ddr_burst_size_default = 16;
+
   fmc_tdc_timestamp_queue_t m_queues[5];
   
   // new
@@ -54,7 +111,98 @@ class FmcTdcDriver;
      m_acc.read(addr + m_base , rv);
      //$display("[Info] readl %x: %x", addr+m_base, rv);
      value = rv;
-   endtask
+   endtask // readl
+
+   task automatic buffer_burst_disable(int channel);
+      uint32_t tmp;
+      uint32_t base = BASE_DMA + ('h40 * channel);
+      
+      readl( base + `ADDR_TDC_BUF_CSR, tmp );
+      tmp &= ~`TDC_BUF_CSR_ENABLE;
+      writel(base + `ADDR_TDC_BUF_CSR, tmp );
+   endtask // buffer_burst_disable
+   
+   task automatic buffer_burst_enable(int channel);
+      uint32_t tmp;
+      uint32_t base = BASE_DMA + ('h40 * channel);
+
+      readl( base + `ADDR_TDC_BUF_CSR, tmp );
+      tmp |= `TDC_BUF_CSR_ENABLE;
+      writel( base + `ADDR_TDC_BUF_CSR, tmp );
+      
+   endtask // buffer_burst_disable
+   
+   task automatic buffer_burst_size_set(int channel, int size);
+      uint32_t tmp;
+      uint32_t base = BASE_DMA + ('h40 * channel);
+
+      readl( base + `ADDR_TDC_BUF_CSR, tmp );
+
+      tmp &= ~`TDC_BUF_CSR_BURST_SIZE;
+      tmp |= size << `TDC_BUF_CSR_BURST_SIZE_OFFSET;
+
+      writel( base + `ADDR_TDC_BUF_CSR, tmp );
+   endtask // buffer_burst_size_set
+   
+
+   typedef struct 
+		  {
+		     uint32_t addr[2];
+		     uint32_t active_buffer;
+		     uint32_t size;
+		  } tdc_dma_buffer_t;
+
+   protected tdc_dma_buffer_t m_buffers[5];
+   
+   
+   
+   task automatic configure_buffers();
+      int channel;
+      uint32_t rv, val;
+      
+
+      for(channel=0;channel<5;channel++)
+	begin
+	   uint32_t base = BASE_DMA + ('h40 * channel);
+
+
+	   m_buffers[channel].active_buffer = 0;
+	   m_buffers[channel].size = TDC_CHANNEL_BUFFER_SIZE_BYTES;
+	   
+	   buffer_burst_disable(channel);
+	   
+	/* Buffer 1 */
+	   m_buffers[channel].addr[0] = TDC_CHANNEL_BUFFER_SIZE_BYTES * (2 * channel);
+	   writel ( base + `ADDR_TDC_BUF_CUR_BASE, m_buffers[channel].addr[0] );
+
+	   val = (m_buffers[channel].size << `TDC_BUF_CUR_SIZE_SIZE_OFFSET);
+	   val |= `TDC_BUF_CUR_SIZE_VALID;
+	   writel( base + `ADDR_TDC_BUF_CUR_SIZE, val );
+
+	/* Buffer 2 */
+	   m_buffers[channel].addr[1] = TDC_CHANNEL_BUFFER_SIZE_BYTES * (2 * channel + 1);
+	   writel ( base + `ADDR_TDC_BUF_NEXT_BASE, m_buffers[channel].addr[1] );
+
+	   val = (m_buffers[channel].size << `TDC_BUF_NEXT_SIZE_SIZE_OFFSET);
+	   val |= `TDC_BUF_NEXT_SIZE_VALID;
+	   writel( base + `ADDR_TDC_BUF_NEXT_SIZE, val );
+
+	   buffer_burst_size_set(channel, dma_buf_ddr_burst_size_default);
+	   buffer_burst_enable(channel);
+
+	   
+	   $display("[buf] Config channel %d: base = %x buf[0] = 0x%08x, buf[1] = 0x%08x, %d timestamps per buffer",
+		 channel, base, m_buffers[channel].addr[0],
+		    m_buffers[channel].addr[1],
+		    m_buffers[channel].size );
+
+
+	   readl( base + `ADDR_TDC_BUF_CSR, val);
+	end // for (channel=0;channel<5;channel++)
+      
+
+   endtask // configure_buffers
+   
   
   // init
   task automatic init();
@@ -85,48 +233,53 @@ class FmcTdcDriver;
      $display("[Info] Setting up TDC core..");
      writel(`ADDR_TDC_CORE_CSR_UTC+`TDC_CORE_CFG_BASE, 1234);  // set UTC
      writel(`ADDR_TDC_CORE_CSR_CTRL+`TDC_CORE_CFG_BASE, 1<<9); // load UTC
-      writel(`ADDR_TDC_CORE_CSR_ENABLE+`TDC_CORE_CFG_BASE, 'h1f0000); // enable all ACAM inputs
      writel(`ADDR_TDC_CORE_CSR_IRQ_TSTAMP_THRESH+`TDC_CORE_CFG_BASE, 2); // FIFO threshold = 2 ts
      writel(`ADDR_TDC_CORE_CSR_IRQ_TIME_THRESH+`TDC_CORE_CFG_BASE, 2); // FIFO threshold = 2 ms
-      writel(`ADDR_TDC_CORE_CSR_CTRL+`TDC_CORE_CFG_BASE, (1<<0)); // start acquisition
      writel('h20bc, ((-1)<<1)); // test?
      
      $display("[Info] TDC acquisition started");
      
-   endtask 
+   endtask // init
+
+   task start_acquisition();
+      writel(`ADDR_TDC_CORE_CSR_ENABLE+`TDC_CORE_CFG_BASE, 'h1f0000); // enable all ACAM inputs
+      writel(`ADDR_TDC_CORE_CSR_CTRL+`TDC_CORE_CFG_BASE, (1<<0)); // start acquisition
+   endtask // start_acquisition
+   
+	
   
   // update	 
   task automatic update();
      automatic uint32_t csr, t[4];

-    for(int i = 0; i < 1; i++) //(int i = 0; i < 5; i++)
-	  begin
-	    automatic uint32_t FIFObase = `FIFO1_BASE + i * 'h100;
-	    automatic fmc_tdc_timestamp_t ts, ts1, ts2;
+      for(int i = 0; i < 1; i++) //(int i = 0; i < 5; i++)
+	begin
+	   automatic uint32_t FIFObase = `FIFO1_BASE + i * 'h100;
+	   automatic fmc_tdc_timestamp_t ts, ts1, ts2;
 	   
-	    readl(FIFObase + `ADDR_TSF_FIFO_CSR, csr);
-        //$display("!!!csr %x: %x", FIFObase + `ADDR_TSF_FIFO_CSR, csr);
+	   readl(FIFObase + `ADDR_TSF_FIFO_CSR, csr);
+           //$display("!!!csr %x: %x", FIFObase + `ADDR_TSF_FIFO_CSR, csr);

 	   
-	    if( ! (csr & `TSF_FIFO_CSR_EMPTY ) ) begin
-            //$display("!!!FIFO not empty!!! csr %x; empty: %x", csr, `TSF_FIFO_CSR_EMPTY);
-		    readl(FIFObase + `ADDR_TSF_FIFO_R0, t[0]);
-		    readl(FIFObase + `ADDR_TSF_FIFO_R1, t[1]);
-		    readl(FIFObase + `ADDR_TSF_FIFO_R2, t[2]);
-		    readl(FIFObase + `ADDR_TSF_FIFO_R3, t[3]);
-
-            ts.tai = t[0];
-		    ts.coarse = t[1];
-		    ts.frac = t[2] & 'hfff;
-	    	ts.slope = t[3] & 'h8 ? 1: 0;
-	    	ts.seq = t[3] >> 4;
-		    ts.channel = i;
-		
-		    m_queues[i].push_back(ts);	
-            //$display("!!!Pushed in FIFO!!!");
-	      end
-	   end // for (int i = 0; i < 5; i++)
-  endtask // update
+	   if( ! (csr & `TSF_FIFO_CSR_EMPTY ) ) begin
+              //$display("!!!FIFO not empty!!! csr %x; empty: %x", csr, `TSF_FIFO_CSR_EMPTY);
+	      readl(FIFObase + `ADDR_TSF_FIFO_R0, t[0]);
+	      readl(FIFObase + `ADDR_TSF_FIFO_R1, t[1]);
+	      readl(FIFObase + `ADDR_TSF_FIFO_R2, t[2]);
+	      readl(FIFObase + `ADDR_TSF_FIFO_R3, t[3]);
+
+              ts.tai = t[0];
+	      ts.coarse = t[1];
+	      ts.frac = t[2] & 'hfff;
+	      ts.slope = t[3] & 'h8 ? 1: 0;
+	      ts.seq = t[3] >> 4;
+	      ts.channel = i;
+	      
+	      m_queues[i].push_back(ts);	
+              //$display("!!!Pushed in FIFO!!!");
+	   end
+	end // for (int i = 0; i < 5; i++)
+   endtask // update

  function int poll();
    //$display("[Info] m_queues[0].size: %d", m_queues[0].size());
@@ -137,6 +290,7 @@ class FmcTdcDriver;
    return m_queues[0].pop_front();
  endfunction // get

+   /*
  // update DMA i/f		 
  task automatic update_dma();
 	automatic uint32_t DMA_CH_base = `TDC_DMA_BASE + 'h100;
@@ -170,7 +324,7 @@ class FmcTdcDriver;
    writel(`DMA_BASE + `ADDR_DMA_STAT, 'h04); // clear DMA IRQ
    writel(`VIC_BASE + `ADDR_DMA_NEXTH, 'h0);
  endtask // update_dma
-
+*/
   
 endclass // FmcTdcDriver

@@ -217,6 +371,13 @@ module main;
   wire [2:0]  ddr_ba;
   wire        ddr_rzq;

+   reg         sim_ts_valid = 0;
+   wire        sim_ts_ready;
+          t_tdc_timestamp sim_ts;
+   
+   
+
+`ifdef USE_ACAM_MODEL
   
   // ACAM model instantiation  
   tdc_gpx_model 
@@ -252,13 +413,20 @@ module main;
      .D(tdc_data)
      );

+`endif // !`ifdef USE_ACAM_MODEL
+   
+
+     
   // GN4124 model instantiation  
   IGN4124PCIMaster Host ();
+     
+   

   // TDC core instantiation
   wr_spec_tdc 
     #(
-       .g_simulation(1)
+       .g_simulation(1),
+       .g_use_fake_timestamps_for_sim(1)
       ) DUT (
 		     .clk_125m_pllref_p_i(clk_125m),
 		     .clk_125m_pllref_n_i(~clk_125m),
@@ -329,7 +497,12 @@ module main;
      .ddr_udm_o                 (ddr_dm[1]),
      .ddr_udqs_n_b              (ddr_dqs_n[1]),
      .ddr_udqs_p_b              (ddr_dqs_p[1]),
-      .ddr_we_n_o                (ddr_we_n)
+      .ddr_we_n_o                (ddr_we_n),
+
+	      .sim_timestamp_valid_i(sim_ts_valid),
+	      .sim_timestamp_ready_o(sim_ts_ready),
+	      .sim_timestamp_i(sim_ts)
+	      
      );

   // DDR3 model instantiation
@@ -359,6 +532,30 @@ module main;
      .odt     (ddr_odt)
      );

+`ifndef USE_ACAM_MODEL
+   FakeTimestampGenerator fakeTsGen;
+
+   initial 
+     begin
+	fakeTsGen = new( 0 );
+
+	
+	forever begin
+	   repeat(100) @(posedge DUT.clk_sys_62m5);
+	   sim_ts <= fakeTsGen.generate_hw_timestamp(0);
+	   sim_ts_valid <= 1;
+	   
+	   @(posedge DUT.clk_sys_62m5);
+	   while(!sim_ts_ready)
+	     @(posedge DUT.clk_sys_62m5);
+	   sim_ts_valid <= 0;
+	   @(posedge DUT.clk_sys_62m5);
+	end
+     end // initial begin
+   
+   
+`endif
+   


   assign tdc_stop_dis[4] = tdc_stop_dis[1];
@@ -374,46 +571,63 @@ module main;
 	 acc = Host.get_accessor();
 	
 	 #5us;
-	
+
+
+      // un-reset the DDR controller
+      $error("unreset");
+//      acc.write( `SPEC_CSR_BASE + `ADDR_SPEC_BASE_REGS_CSR, 0);
+
+      #500us;
+
+      // fixme: poll SPEC reigsters...
+      $display("DDR3 calibration complete");
+      
+
     // test read
-     acc.read('h2208c, d); 
+      acc.read('h2208c, d); 

    // device instantiation
-	drv = new (acc, `TDC_CORE_BASE, 0 );
-	drv.init();
+      drv = new (acc, `TDC_CORE_BASE, 0 );
+      drv.init();
+      drv.configure_buffers();
+      drv.start_acquisition();
+
+
+
+      
 	
 	$display("[Info] Start operation");
      
-	fork
-	  forever begin
-	     drv.update();
-         if(drv.poll()) begin
-         fmc_tdc_timestamp_t ts1, ts2;
-	     uint64_t timestmp1, timestmp2, diff;
-           ts1 = drv.get();
-           timestmp1 = ts1.tai*1e12 + ts1.coarse*8e3 + ts1.frac*81.03;
-           $display("[Info] ts%d [%d:%d:%d src %d, slp: %d]: %d ps", ts1.seq, ts1.tai, ts1.coarse, ts1.frac, ts1.channel, ts1.slope, timestmp1);
-           ts2 = drv.get();
-           timestmp2 = ts2.tai*1e12 + ts2.coarse*8e3 + ts2.frac*81.03;
-           $display("[Info] ts%d [%d:%d:%d src %d, slp: %d]:  %d ps", ts2.seq, ts2.tai, ts2.coarse, ts2.frac, ts2.channel, ts2.slope, timestmp2);
-           if (timestmp1 > timestmp2) begin
-             diff = timestmp1 - timestmp2;
-             $display("[Info] Period: ts%d - ts%d:  %d",  ts1.seq, ts2.seq, diff); 
-           end else begin 
-             diff = timestmp2 - timestmp1;
-             $display("[Info] Period: ts%d - ts%d:  %d",  ts2.seq, ts1.seq, diff);       
-           end
-	     end
-	   end
-	   	   
-	  forever begin
-         // generate pulses to TDC channel 1
+      fork
+	 forever begin
+	    drv.update();
+            if(drv.poll()) begin
+               fmc_tdc_timestamp_t ts1, ts2;
+	       uint64_t timestmp1, timestmp2, diff;
+               ts1 = drv.get();
+               timestmp1 = ts1.tai*1e12 + ts1.coarse*8e3 + ts1.frac*81.03;
+               $display("[Info] ts%d [%d:%d:%d src %d, slp: %d]: %d ps", ts1.seq, ts1.tai, ts1.coarse, ts1.frac, ts1.channel, ts1.slope, timestmp1);
+               ts2 = drv.get();
+               timestmp2 = ts2.tai*1e12 + ts2.coarse*8e3 + ts2.frac*81.03;
+               $display("[Info] ts%d [%d:%d:%d src %d, slp: %d]:  %d ps", ts2.seq, ts2.tai, ts2.coarse, ts2.frac, ts2.channel, ts2.slope, timestmp2);
+               if (timestmp1 > timestmp2) begin
+		  diff = timestmp1 - timestmp2;
+		  $display("[Info] Period: ts%d - ts%d:  %d",  ts1.seq, ts2.seq, diff); 
+               end else begin 
+		  diff = timestmp2 - timestmp1;
+		  $display("[Info] Period: ts%d - ts%d:  %d",  ts2.seq, ts1.seq, diff);       
+               end
+	    end
+	 end
+	 
+	 forever begin
+            // generate pulses to TDC channel 1
 	    #700ns;
 	    tdc_stop[1] <= 1;
 	    #300ns;
 	    tdc_stop[1] <= 0;
-	  end
-	join
+	 end
+      join
    end
   
 endmodule // main

--- a/hdl/testbench/spec/wave.do
+++ b/hdl/testbench/spec/wave.do
 onerror {resume}
 quietly WaveActivateNextPane {} 0
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/clk_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/utc_p_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/state_active_p_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/activate_acq_p_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/deactivate_acq_p_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_from_fpga_o
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/stop_dis_o
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_pulse
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_utc
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_n
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_state_active
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_i
-add wave -noupdate /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_n_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/fmc_id_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/address_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ef1_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ef2_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_led_stat_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/onewire_b
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_valid_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_valid_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_ready_o
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_fifo
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_dma
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_valid
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_ready
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_valid
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_ready
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_valid_p
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/channel_enable
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ts_offset
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reset_seq
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/raw_enable
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/regs_ow_out
-add wave -noupdate -expand -group FmcTdcMezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/regs_ow_in
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_n_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/fmc_id_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/address_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ef1_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ef2_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_led_stat_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/slave_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/dma_wb_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/onewire_b
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_valid_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_valid_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sim_timestamp_ready_o
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_fifo
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_dma
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_valid
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_ready
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_valid
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_ready
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tdc_timestamp_valid_p
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/channel_enable
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/ts_offset
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/reset_seq
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/raw_enable
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/regs_ow_out
+add wave -noupdate -group Mezz /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/regs_ow_in
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/clk_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/rst_n_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/enable_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/raw_mode_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/ts_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/ts_valid_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/ts_ready_o
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/slave_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/slave_o
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/irq_o
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/dma_wb_o
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/dma_wb_i
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/cr_cnx_master_out
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/cr_cnx_master_in
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/dma_cnx_slave_out
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/dma_cnx_slave_in
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/c_CR_CNX_BASE_ADDR
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/c_CR_CNX_BASE_MASK
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/irq_tick_div
+add wave -noupdate -group DMAEng /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/irq_tick
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/clk_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/rst_n_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/enable_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/raw_mode_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/ts_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/ts_valid_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/ts_ready_o
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/slave_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/slave_o
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/irq_tick_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/irq_o
+add wave -noupdate -group DMACh0 -expand /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/dma_wb_o
+add wave -noupdate -group DMACh0 -expand /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/dma_wb_i
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/cur_base
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/cur_size
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/cur_valid
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/cur_pos
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/next_base
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/next_size
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/next_valid
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/addr
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/count
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/burst_count
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/irq_timer
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/regs_out
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/regs_in
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_in
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_out
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_rd
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_wr
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_full
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_empty
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_clear
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_valid
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/fifo_count
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/state
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/dma_state
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/ts
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/buffer_switch_latched
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/dma_addr
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/burst_add
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/burst_sub
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/bursts_in_fifo
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/ack_count
+add wave -noupdate -group DMACh0 -expand /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/dma_wb_out
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/irq_req
+add wave -noupdate -group DMACh0 /main/DUT/cmp_fmc_tdc_mezzanine/cmp_tdc_mezz/gen_with_dma_readout/U_DMA_Engine/gen_channels(0)/U_DMA_Channel/overflow
+add wave -noupdate -group ddr3 /main/DUT/ddr_a_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_ba_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_cas_n_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_ck_n_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_ck_p_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_cke_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_dq_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_ldm_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_ldqs_n_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_ldqs_p_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_odt_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_ras_n_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_reset_n_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_rzq_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_udm_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_udqs_n_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_udqs_p_b
+add wave -noupdate -group ddr3 /main/DUT/ddr_we_n_o
+add wave -noupdate -group ddr3 /main/DUT/ddr_wr_fifo_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/clk_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/rst_n_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/status_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_dq_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_a_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_ba_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_ras_n_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_cas_n_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_we_n_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_odt_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_rst_n_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_cke_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_dm_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_udm_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_dqs_p_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_dqs_n_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_udqs_p_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_udqs_n_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_clk_p_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_clk_n_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_rzq_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/ddr3_zio_b
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_rst_n_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_clk_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_sel_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_cyc_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_stb_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_we_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_addr_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_data_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_data_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_ack_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb0_stall_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_count_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_overflow_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_error_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_count_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_underrun_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_error_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_rst_n_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_clk_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_sel_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_cyc_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_stb_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_we_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_addr_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_data_i
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_data_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_ack_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/wb1_stall_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_count_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_overflow_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_error_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_full_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_empty_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_count_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_underrun_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_error_o
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_instr
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_bl
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_byte_addr
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_cmd_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_mask
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_data
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_count
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_underrun
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_wr_error
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_data
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_count
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_overflow
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p0_rd_error
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_instr
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_bl
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_byte_addr
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_cmd_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_mask
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_data
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_count
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_underrun
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_wr_error
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_clk
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_en
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_data
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_full
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_empty
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_count
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_overflow
+add wave -noupdate -group ddr3ctrl /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/p1_rd_error
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_pllref_p_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_pllref_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_20m_vcxo_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_gtp_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_gtp_p_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_aux_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_rst_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_clk_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_clk_p_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_rdy_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_dframe_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_valid_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p2l_data_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_wr_req_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_wr_rdy_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_rx_error_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_clk_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_clk_p_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_dframe_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_valid_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_edb_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_data_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l2p_rdy_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_l_wr_rdy_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_p_rd_d_rdy_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_tx_error_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_vc_rdy_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_gpio_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_scl_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_sda_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_prsnt_m2c_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/onewire_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_sclk_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_ncs_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_mosi_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/spi_miso_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pcbrev_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/led_act_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/led_link_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/button1_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/uart_rxd_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/uart_txd_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/plldac_sclk_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/plldac_din_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pll25dac_cs_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pll20dac_cs_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_txp_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_txn_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rxp_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rxn_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def0_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def1_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_mod_def2_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_rate_select_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_tx_fault_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_tx_disable_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_los_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_a_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ba_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_cas_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ck_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ck_p_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_cke_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dq_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldm_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldqs_n_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ldqs_p_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_odt_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_ras_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_reset_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_rzq_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udm_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udqs_n_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_udqs_p_b
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_we_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_clk_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_rst_n_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_cyc_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_stb_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_adr_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_sel_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_we_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_dat_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_ack_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_stall_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_dma_wb_dat_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_wr_fifo_empty_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_62m5_sys_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_62m5_sys_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_ref_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_125m_ref_n_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/irq_user_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrf_src_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrf_src_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrf_snk_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrf_snk_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_data_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_valid_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_dreq_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_last_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_flush_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_tx_cfg_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_first_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_last_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_data_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_valid_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_dreq_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrs_rx_cfg_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wb_eth_master_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wb_eth_master_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_link_up_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_time_valid_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_tai_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_cycles_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_dac_value_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_dac_wr_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_clk_aux_lock_en_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/tm_clk_aux_locked_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pps_p_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/pps_led_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/link_ok_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/app_wb_o
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/app_wb_i
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_62m5_sys
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_pll_aux
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_pll_aux_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_333m_ddr
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_333m_ddr_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_rst
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_status
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/ddr_calib_done
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_wb_ddr_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_wb_ddr_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_wb_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gn_wb_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/carrier_wb_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/carrier_wb_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/gennum_status
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/metadata_addr
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/metadata_data
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/buildinfo_addr
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/buildinfo_data
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/therm_id_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/therm_id_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc_i2c_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc_i2c_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/dma_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/dma_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/flash_spi_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/flash_spi_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/vic_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/vic_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrc_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrc_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrc_out_sh
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/csr_rst_gbl
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/csr_rst_app
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_csr_app_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_csr_app_sync_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_gbl_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_scl_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_sda_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_scl_oen
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc0_sda_oen
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/fmc_presence
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/irq_master
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/irqs
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_62m5_sys_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/rst_125m_ref_n
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_125m_ref
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/clk_10m_ext
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/eeprom_sda_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/eeprom_sda_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/eeprom_scl_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/eeprom_scl_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_sda_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_sda_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_scl_in
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/sfp_scl_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrc_abscal_txts_out
+add wave -noupdate -group SpecBase /main/DUT/inst_spec_base/wrc_abscal_rxts_out
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/rst_n_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/clk_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_cyc_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_stb_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_adr_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_sel_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_we_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_dat_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_ack_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_err_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_rty_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_stall_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_dat_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_addr_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_data_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_data_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_wr_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_app_offset_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_resets_global_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_resets_appl_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_fmc_presence_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_gn4124_status_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_ddr_status_calib_done_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_pcb_rev_rev_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_addr_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_data_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_data_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_wr_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_i
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_o
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/rd_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wr_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/rd_ack_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wr_ack_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_en
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/ack_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_rip
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wb_wip
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/metadata_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_resets_global_reg
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/csr_resets_appl_reg
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/therm_id_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/fmc_i2c_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/flash_spi_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/dma_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/vic_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/buildinfo_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_re
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_wt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_rt
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_tr
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_wack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/wrc_regs_rack
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/reg_rdat_int
+add wave -noupdate -group SpecCsr /main/DUT/inst_spec_base/inst_devs/rd_ack1_int
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dq
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_a
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ba
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ras_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cas_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_we_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_odt
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_reset_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_cke
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dm
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udqs_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_rzq
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_udm
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_rst_i
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_calib_done
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_clk0
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_rst0
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_dqs_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/mcb3_dram_ck_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_instr
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_bl
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_byte_addr
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_cmd_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_mask
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_data
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_count
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_underrun
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_wr_error
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_data
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_count
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_overflow
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p0_rd_error
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_instr
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_bl
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_byte_addr
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_cmd_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_mask
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_data
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_count
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_underrun
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_wr_error
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_en
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_data
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_full
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_empty
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_count
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_overflow
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_p1_rd_error
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_p
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sys_clk_n
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_async_rst
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_sysclk_2x_180
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_0
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_ce_90
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_pll_lock
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_mcb_drp_clk
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_error
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data_valid
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_modify_enable
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_error_status
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_data_mode_value
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_vio_addr_mode_value
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_cmp_data
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_enter
+add wave -noupdate -expand -group DdrTop /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_32b_32b/cmp_ddr3_ctrl/c3_selfrefresh_mode
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {10122127 ps} 0}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 1} {135721 ps} 0}
 configure wave -namecolwidth 383
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left
@@ -131,4 +674,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {8005809 ps} {9332857 ps}
+WaveRestoreZoom {0 ps} {1625634 ps}