Commit fbdc4006 authored by penacoba's avatar penacoba

New Register Control module for the core based in RAM block


git-svn-id: http://svn.ohwr.org/fmc-tdc@49 85dfdc96-de2c-444c-878d-45b388be74a9
parent 8c49a6d8
......@@ -36,7 +36,7 @@ entity circular_buffer is
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(19 downto 0);
class_adr_i : in std_logic_vector(g_width-1 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
......@@ -49,7 +49,7 @@ entity circular_buffer is
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(19 downto 0);
pipe_adr_i : in std_logic_vector(g_width-1 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
......@@ -66,17 +66,19 @@ end circular_buffer;
----------------------------------------------------------------------------------------------------
architecture rtl of circular_buffer is
component blk_mem_gen_v6_2
component blk_mem_gen_v6_3
port(
clka : in std_logic;
addra : in std_logic_vector(6 downto 0);
dina : in std_logic_vector(127 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
douta : out std_logic_vector(127 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(8 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
......@@ -92,6 +94,7 @@ signal class_clk : std_logic;
signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal class_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal class_en : std_logic;
signal class_reset : std_logic;
signal class_stb : std_logic;
signal class_we : std_logic_vector(0 downto 0);
......@@ -102,6 +105,7 @@ signal pipe_clk : std_logic;
signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal pipe_data_wr : std_logic_vector(g_width-1 downto 0);
signal pipe_en : std_logic;
signal pipe_reset : std_logic;
signal pipe_stb : std_logic;
signal pipe_we : std_logic_vector(0 downto 0);
......@@ -179,17 +183,19 @@ begin
end case;
end process;
memory_block: blk_mem_gen_v6_2
memory_block: blk_mem_gen_v6_3
port map(
clka => class_clk,
addra => class_adr,
dina => class_data_wr,
ena => class_en,
wea => class_we,
douta => class_data_rd,
clkb => pipe_clk,
addrb => pipe_adr,
dinb => pipe_data_wr,
enb => pipe_en,
web => pipe_we,
doutb => pipe_data_rd
);
......@@ -201,6 +207,7 @@ begin
class_adr <= class_adr_i(6 downto 0);
class_cyc <= class_cyc_i;
class_data_wr <= class_dat_i;
class_en <= class_cyc;
class_stb <= class_stb_i;
class_we(0) <= class_we_i;
......@@ -210,6 +217,7 @@ begin
pipe_adr <= pipe_adr_i(8 downto 0);
pipe_cyc <= pipe_cyc_i;
pipe_data_wr <= pipe_dat_i;
pipe_en <= pipe_cyc;
pipe_stb <= pipe_stb_i;
pipe_we(0) <= pipe_we_i;
......
......@@ -6,7 +6,8 @@
-- author : G. Penacoba
-- date : May 2011
-- version : Revision 1
-- description : generates one pulse every second synchronously with the acam reference clock
-- description : generates one pulse every second synchronously with the acam reference clock.
-- The phase with the reference clock can be adjusted.
-- dependencies:
-- references :
-- modified by :
......@@ -32,9 +33,9 @@ entity one_hz_gen is
port(
acam_refclk_i : in std_logic;
clk_i : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0);
pulse_delay_i : in std_logic_vector(g_width-1 downto 0);
reset_i : in std_logic;
clock_period_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods for 1s
pulse_delay_i : in std_logic_vector(g_width-1 downto 0); -- nb of clock periods phase delay
reset_i : in std_logic; -- with respect to reference clock
one_hz_p_o : out std_logic
);
......
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : Clock and reset management unit (clk_rst_managr.vhd)
-- author : G. Penacoba
-- date : May 2011
-- version : Revision 1
-- description : independent block that uses the spec clk to parameterize
-- the TDC mezzanine PLL that will be used by all the other
-- blocks. Includes input clk buffers for Xilinx Spartan6.
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for clk_rst_managr
----------------------------------------------------------------------------------------------------
entity clk_rst_managr is
generic(
nb_of_reg : integer:=68
);
port(
acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
gnum_reset_i : in std_logic;
spec_clk_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic;
general_reset_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
spec_clk_o : out std_logic;
tdc_clk_o : out std_logic
);
end clk_rst_managr;
----------------------------------------------------------------------------------------------------
-- architecture declaration for clk_rst_managr
----------------------------------------------------------------------------------------------------
architecture rtl of clk_rst_managr is
component incr_counter
generic(
width : integer :=32
);
port(
clk : in std_logic;
end_value : in std_logic_vector(width-1 downto 0);
incr : in std_logic;
reset : in std_logic;
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
subtype t_wd is std_logic_vector(15 downto 0);
subtype t_byte is std_logic_vector(7 downto 0);
type t_instr is array (nb_of_reg-1 downto 0) of t_wd;
type t_stream is array (nb_of_reg-1 downto 0) of t_byte;
type t_pll_init_st is (start, sending_instruction, sending_data, rest, done);
-- the PLL circuit AD9516-4 needs to be configured through 68 registers
-- the values and addresses are obtained from a dedicated Analog Devices
-- software and from the datasheet.
constant reg_000 : t_byte:=x"18";
constant reg_001 : t_byte:=x"00";
constant reg_002 : t_byte:=x"10";
constant reg_003 : t_byte:=x"C3";
constant reg_004 : t_byte:=x"00";
constant reg_010 : t_byte:=x"7C";
constant reg_011 : t_byte:=x"01";
constant reg_012 : t_byte:=x"00";
constant reg_013 : t_byte:=x"03";
constant reg_014 : t_byte:=x"09";
constant reg_015 : t_byte:=x"00";
constant reg_016 : t_byte:=x"04";
constant reg_017 : t_byte:=x"00";
constant reg_018 : t_byte:=x"07";
constant reg_019 : t_byte:=x"00";
constant reg_01A : t_byte:=x"00";
constant reg_01B : t_byte:=x"00";
constant reg_01C : t_byte:=x"02";
constant reg_01D : t_byte:=x"00";
constant reg_01E : t_byte:=x"00";
constant reg_01F : t_byte:=x"0E";
constant reg_0A0 : t_byte:=x"01";
constant reg_0A1 : t_byte:=x"00";
constant reg_0A2 : t_byte:=x"00";
constant reg_0A3 : t_byte:=x"01";
constant reg_0A4 : t_byte:=x"00";
constant reg_0A5 : t_byte:=x"00";
constant reg_0A6 : t_byte:=x"01";
constant reg_0A7 : t_byte:=x"00";
constant reg_0A8 : t_byte:=x"00";
constant reg_0A9 : t_byte:=x"01";
constant reg_0AA : t_byte:=x"00";
constant reg_0AB : t_byte:=x"00";
constant reg_0F0 : t_byte:=x"0A";
constant reg_0F1 : t_byte:=x"0A";
constant reg_0F2 : t_byte:=x"0A";
constant reg_0F3 : t_byte:=x"0A";
constant reg_0F4 : t_byte:=x"0A";
constant reg_0F5 : t_byte:=x"0A";
constant reg_140 : t_byte:=x"4A";
constant reg_141 : t_byte:=x"5A";
constant reg_142 : t_byte:=x"43";
constant reg_143 : t_byte:=x"42";
constant reg_190 : t_byte:=x"00";
constant reg_191 : t_byte:=x"80";
constant reg_192 : t_byte:=x"00";
constant reg_193 : t_byte:=x"00";
constant reg_194 : t_byte:=x"80";
constant reg_195 : t_byte:=x"00";
constant reg_196 : t_byte:=x"00";
constant reg_197 : t_byte:=x"80";
constant reg_198 : t_byte:=x"00";
constant reg_199 : t_byte:=x"22";
constant reg_19A : t_byte:=x"00";
constant reg_19B : t_byte:=x"11";
constant reg_19C : t_byte:=x"00";
constant reg_19D : t_byte:=x"00";
constant reg_19E : t_byte:=x"22";
constant reg_19F : t_byte:=x"00";
constant reg_1A0 : t_byte:=x"11";
constant reg_1A1 : t_byte:=x"20";
constant reg_1A2 : t_byte:=x"00";
constant reg_1A3 : t_byte:=x"00";
constant reg_1E0 : t_byte:=x"00";
constant reg_1E1 : t_byte:=x"02";
constant reg_230 : t_byte:=x"00";
constant reg_231 : t_byte:=x"00";
constant reg_232 : t_byte:=x"01";
signal pll_init_st : t_pll_init_st;
signal nxt_pll_init_st : t_pll_init_st;
signal config_reg : t_stream;
signal address : t_instr;
signal acam_refclk_buf : std_logic;
signal spec_clk_buf : std_logic;
signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic;
signal pll_sclk : std_logic;
signal spec_clk : std_logic;
signal tdc_clk : std_logic;
signal bit_being_sent : std_logic;
signal word_being_sent : t_wd;
signal bit_index : integer range 15 downto 0;
signal byte_index : integer range nb_of_reg-1 downto 0;
signal silly_altern : std_logic;
signal gnum_reset : std_logic;
signal gral_incr : std_logic;
signal inv_reset : std_logic;
signal cs : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
--Clock input buffer instantiations
-----------------------------------
tdc_clk125_ibuf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
O => tdc_clk_buf, -- Buffer output
I => tdc_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => tdc_clk_n_i -- Diff_n buffer input (connect directly to top-level port)
);
tdc_clk125_gbuf : BUFG
port map (
O => tdc_clk,
I => tdc_clk_buf
);
spec_clk_ibuf : IBUFG
port map (
I => spec_clk_i,
O => spec_clk_buf
);
spec_clk_gbuf : BUFG
port map (
O => spec_clk,
I => spec_clk_buf
);
-- acam_refclk_ibuf : IBUFG
-- port map (
-- I => acam_refclk_i,
-- O => acam_refclk_buf
-- );
--
-- acam_refclk_gbuf : BUFG
-- port map (
-- O => acam_refclk,
-- I => acam_refclk_buf
-- );
acam_refclk <= acam_refclk_i;
general_poreset: incr_counter
port map(
clk => spec_clk,
end_value => x"0000007D", -- 125 clk ticks
incr => gral_incr,
reset => gnum_reset,
count_done => inv_reset,
current_value => open
);
silly: process
begin
if gnum_reset ='1' then
silly_altern <= '0';
else
silly_altern <= not(silly_altern);
end if;
wait until spec_clk ='1';
end process;
gral_reset_incr: process(silly_altern, tdc_clk)
begin
if silly_altern ='0' then
gral_incr <= '0';
elsif rising_edge(tdc_clk) then
gral_incr <= '1';
end if;
end process;
-- Processes for initialization of the PLL
------------------------------------------
pll_initialization_seq: process
begin
if gnum_reset ='1' then
pll_init_st <= start;
else
pll_init_st <= nxt_pll_init_st;
end if;
wait until spec_clk ='1';
end process;
pll_initialization_comb: process(pll_init_st, byte_index, bit_index, pll_sclk)
begin
case pll_init_st is
when start =>
cs <= '1';
if pll_sclk ='1' then
nxt_pll_init_st <= sending_instruction;
else
nxt_pll_init_st <= start;
end if;
when sending_instruction =>
cs <= '0';
if bit_index = 0
and pll_sclk = '1' then
nxt_pll_init_st <= sending_data;
else
nxt_pll_init_st <= sending_instruction;
end if;
when sending_data =>
cs <= '0';
if bit_index = 0
and pll_sclk = '1' then
nxt_pll_init_st <= rest;
else
nxt_pll_init_st <= sending_data;
end if;
when rest =>
cs <= '1';
if pll_sclk = '1' then
if byte_index = 0 then
nxt_pll_init_st <= done;
else
nxt_pll_init_st <= sending_instruction;
end if;
else
nxt_pll_init_st <= rest;
end if;
when done =>
cs <= '1';
nxt_pll_init_st <= done;
when others =>
cs <= '1';
nxt_pll_init_st <= start;
end case;
end process;
index_control: process
begin
if gnum_reset ='1' then
bit_index <= 15;
elsif cs ='1' then
bit_index <= 15;
elsif pll_sclk ='1' then
if bit_index = 0 then
bit_index <= 7;
else
bit_index <= bit_index -1;
end if;
end if;
if gnum_reset ='1' then
byte_index <= nb_of_reg -1;
elsif pll_init_st = rest and pll_sclk ='1' then
if byte_index = 0 then
byte_index <= nb_of_reg-1;
else
byte_index <= byte_index -1;
end if;
end if;
wait until spec_clk ='1';
end process;
pll_sclk_generator: process
begin
if gnum_reset ='1' then
pll_sclk <= '0';
else
pll_sclk <= not(pll_sclk);
end if;
wait until spec_clk ='1';
end process;
bit_being_sent <= word_being_sent(bit_index);
word_being_sent <= address(byte_index) when pll_init_st = sending_instruction
else x"00" & config_reg(byte_index);
-- Assignement of the values to be sent for the configurations of the PLL
-------------------------------------------------------------------------
-- according to the datasheet the register 232 should be written last
-- to validate the transfer from the buffer to the valid registers
-- the 16-bit instruction word indicates always a write cycle of byte
address(0) <= x"0232";
address(1) <= x"0000";
address(2) <= x"0001";
address(3) <= x"0002";
address(4) <= x"0003";
address(5) <= x"0004";
address(6) <= x"0010";
address(7) <= x"0011";
address(8) <= x"0012";
address(9) <= x"0013";
address(10) <= x"0014";
address(11) <= x"0015";
address(12) <= x"0016";
address(13) <= x"0017";
address(14) <= x"0018";
address(15) <= x"0019";
address(16) <= x"001A";
address(17) <= x"001B";
address(18) <= x"001C";
address(19) <= x"001D";
address(20) <= x"001E";
address(21) <= x"001F";
address(22) <= x"00A0";
address(23) <= x"00A1";
address(24) <= x"00A2";
address(25) <= x"00A3";
address(26) <= x"00A4";
address(27) <= x"00A5";
address(28) <= x"00A6";
address(29) <= x"00A7";
address(30) <= x"00A8";
address(31) <= x"00A9";
address(32) <= x"00AA";
address(33) <= x"00AB";
address(34) <= x"00F0";
address(35) <= x"00F1";
address(36) <= x"00F2";
address(37) <= x"00F3";
address(38) <= x"00F4";
address(39) <= x"00F5";
address(40) <= x"0140";
address(41) <= x"0141";
address(42) <= x"0142";
address(43) <= x"0143";
address(44) <= x"0190";
address(45) <= x"0191";
address(46) <= x"0192";
address(47) <= x"0193";
address(48) <= x"0194";
address(49) <= x"0195";
address(50) <= x"0196";
address(51) <= x"0197";
address(52) <= x"0198";
address(53) <= x"0199";
address(54) <= x"019A";
address(55) <= x"019B";
address(56) <= x"019C";
address(57) <= x"019D";
address(58) <= x"019E";
address(59) <= x"019F";
address(60) <= x"01A0";
address(61) <= x"01A1";
address(62) <= x"01A2";
address(63) <= x"01A3";
address(64) <= x"01E0";
address(65) <= x"01E1";
address(66) <= x"0230";
address(67) <= x"0231";
config_reg(0) <= reg_232;
config_reg(1) <= reg_000;
config_reg(2) <= reg_001;
config_reg(3) <= reg_002;
config_reg(4) <= reg_003;
config_reg(5) <= reg_004;
config_reg(6) <= reg_010;
config_reg(7) <= reg_011;
config_reg(8) <= reg_012;
config_reg(9) <= reg_013;
config_reg(10) <= reg_014;
config_reg(11) <= reg_015;
config_reg(12) <= reg_016;
config_reg(13) <= reg_017;
config_reg(14) <= reg_018;
config_reg(15) <= reg_019;
config_reg(16) <= reg_01A;
config_reg(17) <= reg_01B;
config_reg(18) <= reg_01C;
config_reg(19) <= reg_01D;
config_reg(20) <= reg_01E;
config_reg(21) <= reg_01F;
config_reg(22) <= reg_0A0;
config_reg(23) <= reg_0A1;
config_reg(24) <= reg_0A2;
config_reg(25) <= reg_0A3;
config_reg(26) <= reg_0A4;
config_reg(27) <= reg_0A5;
config_reg(28) <= reg_0A6;
config_reg(29) <= reg_0A7;
config_reg(30) <= reg_0A8;
config_reg(31) <= reg_0A9;
config_reg(32) <= reg_0AA;
config_reg(33) <= reg_0AB;
config_reg(34) <= reg_0F0;
config_reg(35) <= reg_0F1;
config_reg(36) <= reg_0F2;
config_reg(37) <= reg_0F3;
config_reg(38) <= reg_0F4;
config_reg(39) <= reg_0F5;
config_reg(40) <= reg_140;
config_reg(41) <= reg_141;
config_reg(42) <= reg_142;
config_reg(43) <= reg_143;
config_reg(44) <= reg_190;
config_reg(45) <= reg_191;
config_reg(46) <= reg_192;
config_reg(47) <= reg_193;
config_reg(48) <= reg_194;
config_reg(49) <= reg_195;
config_reg(50) <= reg_196;
config_reg(51) <= reg_197;
config_reg(52) <= reg_198;
config_reg(53) <= reg_199;
config_reg(54) <= reg_19A;
config_reg(55) <= reg_19B;
config_reg(56) <= reg_19C;
config_reg(57) <= reg_19D;
config_reg(58) <= reg_19E;
config_reg(59) <= reg_19F;
config_reg(60) <= reg_1A0;
config_reg(61) <= reg_1A1;
config_reg(62) <= reg_1A2;
config_reg(63) <= reg_1A3;
config_reg(64) <= reg_1E0;
config_reg(65) <= reg_1E1;
config_reg(66) <= reg_230;
config_reg(67) <= reg_231;
-- Input and Output signals
---------------------------
gnum_reset <= gnum_reset_i;
acam_refclk_o <= acam_refclk;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : Clock and reset management unit (clk_rst_managr.vhd)
-- author : G. Penacoba
-- date : May 2011
-- version : Revision 1
-- description : independent block that uses the spec clk to parameterize
-- the TDC mezzanine PLL that will be used by all the other
-- blocks. Includes input clk buffers for Xilinx Spartan6.
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for clk_rst_managr
----------------------------------------------------------------------------------------------------
entity clk_rst_managr is
generic(
nb_of_reg : integer:=563
);
port(
acam_refclk_i : in std_logic;
pll_ld_i : in std_logic;
pll_refmon_i : in std_logic;
pll_sdo_i : in std_logic;
pll_status_i : in std_logic;
gnum_reset_i : in std_logic;
spec_clk_i : in std_logic;
tdc_clk_p_i : in std_logic;
tdc_clk_n_i : in std_logic;
acam_refclk_o : out std_logic;
general_reset_o : out std_logic;
pll_cs_o : out std_logic;
pll_dac_sync_o : out std_logic;
pll_sdi_o : out std_logic;
pll_sclk_o : out std_logic;
spec_clk_o : out std_logic;
tdc_clk_o : out std_logic
);
end clk_rst_managr;
----------------------------------------------------------------------------------------------------
-- architecture declaration for clk_rst_managr
----------------------------------------------------------------------------------------------------
architecture rtl of clk_rst_managr is
component incr_counter
generic(
width : integer :=32
);
port(
clk : in std_logic;
end_value : in std_logic_vector(width-1 downto 0);
incr : in std_logic;
reset : in std_logic;
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
subtype t_byte is std_logic_vector(7 downto 0);
type t_instr is array (1 downto 0) of t_byte;
type t_stream is array (nb_of_reg-1 downto 0) of t_byte;
type t_pll_init_st is (start, sending_instruction, sending_data, done);
-- the PLL circuit AD9516-4 needs to be configured through 68 registers
-- the values and addresses are obtained from a dedicated Analog Devices
-- software and from the datasheet.
constant reg_000 : t_byte:=x"18";
constant reg_001 : t_byte:=x"00";
constant reg_002 : t_byte:=x"10";
constant reg_003 : t_byte:=x"C3";
constant reg_004 : t_byte:=x"00";
constant reg_010 : t_byte:=x"7C";
constant reg_011 : t_byte:=x"01";
constant reg_012 : t_byte:=x"00";
constant reg_013 : t_byte:=x"03";
constant reg_014 : t_byte:=x"09";
constant reg_015 : t_byte:=x"00";
constant reg_016 : t_byte:=x"04";
constant reg_017 : t_byte:=x"00";
constant reg_018 : t_byte:=x"06";
constant reg_019 : t_byte:=x"00";
constant reg_01A : t_byte:=x"00";
constant reg_01B : t_byte:=x"00";
constant reg_01C : t_byte:=x"02";
constant reg_01D : t_byte:=x"00";
constant reg_01E : t_byte:=x"00";
constant reg_01F : t_byte:=x"0E";
constant reg_0A0 : t_byte:=x"01";
constant reg_0A1 : t_byte:=x"00";
constant reg_0A2 : t_byte:=x"00";
constant reg_0A3 : t_byte:=x"01";
constant reg_0A4 : t_byte:=x"00";
constant reg_0A5 : t_byte:=x"00";
constant reg_0A6 : t_byte:=x"01";
constant reg_0A7 : t_byte:=x"00";
constant reg_0A8 : t_byte:=x"00";
constant reg_0A9 : t_byte:=x"01";
constant reg_0AA : t_byte:=x"00";
constant reg_0AB : t_byte:=x"00";
constant reg_0F0 : t_byte:=x"0A";
constant reg_0F1 : t_byte:=x"0A";
constant reg_0F2 : t_byte:=x"0A";
constant reg_0F3 : t_byte:=x"0A";
constant reg_0F4 : t_byte:=x"0A";
constant reg_0F5 : t_byte:=x"0A";
constant reg_140 : t_byte:=x"4A";
constant reg_141 : t_byte:=x"5A";
constant reg_142 : t_byte:=x"43";
constant reg_143 : t_byte:=x"42";
constant reg_190 : t_byte:=x"00";
constant reg_191 : t_byte:=x"80";
constant reg_192 : t_byte:=x"00";
constant reg_193 : t_byte:=x"00";
constant reg_194 : t_byte:=x"80";
constant reg_195 : t_byte:=x"00";
constant reg_196 : t_byte:=x"00";
constant reg_197 : t_byte:=x"80";
constant reg_198 : t_byte:=x"00";
constant reg_199 : t_byte:=x"22";
constant reg_19A : t_byte:=x"00";
constant reg_19B : t_byte:=x"11";
constant reg_19C : t_byte:=x"00";
constant reg_19D : t_byte:=x"00";
constant reg_19E : t_byte:=x"22";
constant reg_19F : t_byte:=x"00";
constant reg_1A0 : t_byte:=x"11";
constant reg_1A1 : t_byte:=x"20";
constant reg_1A2 : t_byte:=x"00";
constant reg_1A3 : t_byte:=x"00";
constant reg_1E0 : t_byte:=x"00";
constant reg_1E1 : t_byte:=x"02";
constant reg_230 : t_byte:=x"00";
constant reg_231 : t_byte:=x"00";
constant reg_232 : t_byte:=x"01";
-- the 16-bit instruction word indicates a write cycle
-- in streaming mode starting in address 231
constant instr_wd_msb : t_byte:=x"62";
constant instr_wd_lsb : t_byte:=x"31";
constant blank : t_byte:=x"00";
signal blank_registers : boolean;
signal pll_init_st : t_pll_init_st;
signal nxt_pll_init_st : t_pll_init_st;
signal stream : t_stream:=(others => blank);
signal instruction : t_instr;
signal acam_refclk_buf : std_logic;
signal spec_clk_buf : std_logic;
signal tdc_clk_buf : std_logic;
signal acam_refclk : std_logic;
signal pll_sclk : std_logic;
signal spec_clk : std_logic;
signal tdc_clk : std_logic;
signal bit_being_sent : std_logic;
signal byte_being_sent : t_byte;
signal bit_index : integer range 7 downto 0;
signal byte_index : integer range nb_of_reg-1 downto 0;
signal silly_altern : std_logic;
signal gnum_reset : std_logic;
signal gral_incr : std_logic;
signal inv_reset : std_logic;
signal cs : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
--Clock input buffer instantiations
-----------------------------------
tdc_clk125_ibuf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT"
)
port map (
I => tdc_clk_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => tdc_clk_n_i, -- Diff_n buffer input (connect directly to top-level port)
O => tdc_clk_buf -- Buffer output
);
tdc_clk125_gbuf : BUFG
port map (
I => tdc_clk_buf,
O => tdc_clk
);
spec_clk_ibuf : IBUFG
port map (
I => spec_clk_i,
O => spec_clk_buf
);
spec_clk_gbuf : BUFG
port map (
I => spec_clk_buf,
O => spec_clk
);
-- acam_refclk_ibuf : IBUFG
-- port map (
-- I => acam_refclk_i,
-- O => acam_refclk_buf
-- );
--
-- acam_refclk_gbuf : BUFG
-- port map (
-- O => acam_refclk,
-- I => acam_refclk_buf
-- );
acam_refclk <= acam_refclk_i;
general_poreset: incr_counter
port map(
clk => spec_clk,
end_value => x"0000007D", -- 125 clk ticks
incr => gral_incr,
reset => gnum_reset,
count_done => inv_reset,
current_value => open
);
silly: process
begin
if gnum_reset ='1' then
silly_altern <= '0';
else
silly_altern <= not(silly_altern);
end if;
wait until spec_clk ='1';
end process;
gral_reset_incr: process(silly_altern, tdc_clk)
begin
if silly_altern ='0' then
gral_incr <= '0';
elsif rising_edge(tdc_clk) then
gral_incr <= '1';
end if;
end process;
-- Processes for initialization of the PLL
------------------------------------------
pll_initialization_seq: process
begin
if gnum_reset ='1' then
pll_init_st <= start;
else
pll_init_st <= nxt_pll_init_st;
end if;
wait until spec_clk ='1';
end process;
pll_initialization_comb: process(pll_init_st, byte_index, bit_index, pll_sclk)
begin
case pll_init_st is
when start =>
cs <= '1';
if pll_sclk ='1' then
nxt_pll_init_st <= sending_instruction;
else
nxt_pll_init_st <= start;
end if;
when sending_instruction =>
cs <= '0';
if byte_index = 0
and bit_index = 0
and pll_sclk = '1' then
nxt_pll_init_st <= sending_data;
else
nxt_pll_init_st <= sending_instruction;
end if;
when sending_data =>
cs <= '0';
if byte_index = 0
and bit_index = 0
and pll_sclk = '1' then
nxt_pll_init_st <= done;
else
nxt_pll_init_st <= sending_data;
end if;
when done =>
cs <= '1';
nxt_pll_init_st <= done;
when others =>
cs <= '1';
nxt_pll_init_st <= start;
end case;
end process;
index_control: process
begin
if gnum_reset ='1' then
bit_index <= 7;
elsif pll_sclk ='1'
and cs ='0' then
if bit_index = 0 then
bit_index <= 7;
else
bit_index <= bit_index -1;
end if;
end if;
if gnum_reset ='1' then
byte_index <= 1;
elsif pll_sclk ='1'
and cs ='0'
and bit_index = 0 then
if byte_index = 0 then
byte_index <= nb_of_reg-1;
else
byte_index <= byte_index -1;
end if;
end if;
wait until spec_clk ='1';
end process;
pll_sclk_generator: process
begin
if gnum_reset ='1' then
pll_sclk <= '0';
else
pll_sclk <= not(pll_sclk);
end if;
wait until spec_clk ='1';
end process;
bit_being_sent <= byte_being_sent(bit_index);
byte_being_sent <= instruction(byte_index) when pll_init_st = sending_instruction
-- else blank when blank_registers
else stream(byte_index);
-- blank_registers <= TRUE when (5 < byte_index and byte_index < 17)
-- or (32 < byte_index and byte_index < 161)
-- or (172 < byte_index and byte_index < 241)
-- or (246 < byte_index and byte_index < 321)
-- or (324 < byte_index and byte_index < 401)
-- or (420 < byte_index and byte_index < 481)
-- or (482 < byte_index and byte_index < 561)
-- else FALSE;
-- Assignement of the values to be sent for the configurations of the PLL
-------------------------------------------------------------------------
instruction(1) <= instr_wd_msb;
instruction(0) <= instr_wd_lsb;
-- according to the datasheet the register 232 should be written last
-- to validate the transfer from the buffer to the valid registers
stream(0) <= reg_232;
stream(1) <= reg_000;
stream(2) <= reg_001;
stream(3) <= reg_002;
stream(4) <= reg_003;
stream(5) <= reg_004;
stream(17) <= reg_010;
stream(18) <= reg_011;
stream(19) <= reg_012;
stream(20) <= reg_013;
stream(21) <= reg_014;
stream(22) <= reg_015;
stream(23) <= reg_016;
stream(24) <= reg_017;
stream(25) <= reg_018;
stream(26) <= reg_019;
stream(27) <= reg_01A;
stream(28) <= reg_01B;
stream(29) <= reg_01C;
stream(30) <= reg_01D;
stream(31) <= reg_01E;
stream(32) <= reg_01F;
stream(161) <= reg_0A0;
stream(162) <= reg_0A1;
stream(163) <= reg_0A2;
stream(164) <= reg_0A3;
stream(165) <= reg_0A4;
stream(166) <= reg_0A5;
stream(167) <= reg_0A6;
stream(168) <= reg_0A7;
stream(169) <= reg_0A8;
stream(170) <= reg_0A9;
stream(171) <= reg_0AA;
stream(172) <= reg_0AB;
stream(241) <= reg_0F0;
stream(242) <= reg_0F1;
stream(243) <= reg_0F2;
stream(244) <= reg_0F3;
stream(245) <= reg_0F4;
stream(246) <= reg_0F5;
stream(321) <= reg_140;
stream(322) <= reg_141;
stream(323) <= reg_142;
stream(324) <= reg_143;
stream(401) <= reg_190;
stream(402) <= reg_191;
stream(403) <= reg_192;
stream(404) <= reg_193;
stream(405) <= reg_194;
stream(406) <= reg_195;
stream(407) <= reg_196;
stream(408) <= reg_197;
stream(409) <= reg_198;
stream(410) <= reg_199;
stream(411) <= reg_19A;
stream(412) <= reg_19B;
stream(413) <= reg_19C;
stream(414) <= reg_19D;
stream(415) <= reg_19E;
stream(416) <= reg_19F;
stream(417) <= reg_1A0;
stream(418) <= reg_1A1;
stream(419) <= reg_1A2;
stream(420) <= reg_1A3;
stream(481) <= reg_1E0;
stream(482) <= reg_1E1;
stream(561) <= reg_230;
stream(562) <= reg_231;
-- Input and Output signals
---------------------------
gnum_reset <= gnum_reset_i;
acam_refclk_o <= acam_refclk;
general_reset_o <= not(inv_reset);
pll_cs_o <= cs;
pll_sdi_o <= bit_being_sent;
pll_sclk_o <= pll_sclk;
spec_clk_o <= spec_clk;
tdc_clk_o <= tdc_clk;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- CERN-BE-CO-HT
----------------------------------------------------------------------------------------------------
--
-- unit name : Register control block including RAM memory for storage (reg_ctrl)
-- author : G. Penacoba
-- date : Oct 2011
-- version : Revision 1
-- description : contains the RAM block (64 x 32) and the wishbone classic slave interfaces.
-- Processes the TDC_control register.
-- dependencies:
-- references :
-- modified by :
--
----------------------------------------------------------------------------------------------------
-- last changes:
----------------------------------------------------------------------------------------------------
-- to do:
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for reg_ctrl
----------------------------------------------------------------------------------------------------
entity reg_ctrl is
generic(
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i : in std_logic;
appli_reset_i : in std_logic;
appli_adr_i : in std_logic_vector(g_width-1 downto 0);
appli_cyc_i : in std_logic;
appli_dat_i : in std_logic_vector(g_width-1 downto 0);
appli_stb_i : in std_logic;
appli_we_i : in std_logic;
appli_ack_o : out std_logic;
appli_dat_o : out std_logic_vector(g_width-1 downto 0);
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i : in std_logic;
host_reset_i : in std_logic;
host_adr_i : in std_logic_vector(g_width-1 downto 0);
host_cyc_i : in std_logic;
host_dat_i : in std_logic_vector(g_width-1 downto 0);
host_stb_i : in std_logic;
host_we_i : in std_logic;
host_ack_o : out std_logic;
host_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other application internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
-- configuration registers for the modules of the TDC core
starting_utc_time_o : out std_logic_vector(31 downto 0);
clk_freq_o : out std_logic_vector(31 downto 0);
ref_clk_freq_o : out std_logic_vector(31 downto 0);
start_phase_o : out std_logic_vector(31 downto 0);
one_hz_phase_o : out std_logic_vector(31 downto 0);
retrig_freq_o : out std_logic_vector(31 downto 0)
);
end reg_ctrl;
----------------------------------------------------------------------------------------------------
-- architecture declaration for reg_ctrl
----------------------------------------------------------------------------------------------------
architecture rtl of reg_ctrl is
component reg_mem_gen_v6_2
port(
clka : in std_logic;
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
douta : out std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
signal appli_ack : std_logic;
signal appli_adr : std_logic_vector(5 downto 0);
signal appli_clk : std_logic;
signal appli_cyc : std_logic;
signal appli_data_rd : std_logic_vector(g_width-1 downto 0);
signal appli_data_wr : std_logic_vector(g_width-1 downto 0);
signal appli_en : std_logic;
signal appli_reset : std_logic;
signal appli_stb : std_logic;
signal appli_we : std_logic_vector(0 downto 0);
signal host_ack : std_logic;
signal host_adr : std_logic_vector(5 downto 0);
signal host_clk : std_logic;
signal host_cyc : std_logic;
signal host_data_rd : std_logic_vector(g_width-1 downto 0);
signal host_data_wr : std_logic_vector(g_width-1 downto 0);
signal host_en : std_logic;
signal host_reset : std_logic;
signal host_stb : std_logic;
signal host_we : std_logic_vector(0 downto 0);
signal starting_utc_time : std_logic_vector(31 downto 0);
signal clk_freq : std_logic_vector(31 downto 0);
signal ref_clk_freq : std_logic_vector(31 downto 0);
signal start_phase : std_logic_vector(31 downto 0);
signal one_hz_phase : std_logic_vector(31 downto 0);
signal retrig_freq : std_logic_vector(31 downto 0);
signal control_register : std_logic_vector(31 downto 0);
signal clear_ctrl_reg : std_logic;
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
-- Wishbone classic interface compatible slave for the application side
application_interface: process
begin
if appli_reset ='1' then
appli_ack <= '0';
else
appli_ack <= appli_stb and appli_cyc;
end if;
wait until appli_clk ='1';
end process;
-- Wishbone classic interface compatible slave for the side of the communication with the host
host_side_interface: process
begin
if host_reset ='1' then
host_ack <= '0';
else
host_ack <= host_stb and host_cyc;
end if;
wait until host_clk ='1';
end process;
-- config registers for TDC core
config_reg: process
begin
if host_reset ='1' then
starting_utc_time <= (others =>'0');
clk_freq <= (others =>'0');
ref_clk_freq <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
retrig_freq <= (others =>'0');
elsif host_cyc ='1' and host_stb ='1' and host_we(0) ='1' then
if host_adr = x"20" then
starting_utc_time <= host_data_wr;
end if;
if host_adr = x"21" then
clk_freq <= host_data_wr;
end if;
if host_adr = x"22" then
ref_clk_freq <= host_data_wr;
end if;
if host_adr = x"23" then
start_phase <= host_data_wr;
end if;
if host_adr = x"24" then
one_hz_phase <= host_data_wr;
end if;
if host_adr = x"25" then
retrig_freq <= host_data_wr;
end if;
end if;
wait until host_clk ='1';
end process;
-- control register for TDC core
control_reg: process
begin
if host_reset ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif host_cyc ='1' and host_stb ='1' and host_we(0) ='1' then
if host_adr_i = x"00020040" then -- address outside of the memory block
control_register <= host_data_wr;
clear_ctrl_reg <= '1';
end if;
end if;
wait until host_clk ='1';
end process;
memory_block: reg_mem_gen_v6_2
port map(
clka => appli_clk,
addra => appli_adr,
dina => appli_data_wr,
ena => appli_en,
wea => appli_we,
douta => appli_data_rd,
clkb => host_clk,
addrb => host_adr,
dinb => host_data_wr,
enb => host_en,
web => host_we,
doutb => host_data_rd
);
-- inputs from other blocks
appli_clk <= appli_clk_i;
appli_reset <= appli_reset_i;
appli_adr <= appli_adr_i(5 downto 0);
appli_cyc <= appli_cyc_i;
appli_data_wr <= appli_dat_i;
appli_en <= appli_cyc;
appli_stb <= appli_stb_i;
appli_we(0) <= appli_we_i;
host_clk <= host_clk_i;
host_reset <= host_reset_i;
host_adr <= host_adr_i(5 downto 0);
host_cyc <= host_cyc_i;
host_data_wr <= host_dat_i;
host_en <= host_cyc;
host_stb <= host_stb_i;
host_we(0) <= host_we_i;
-- outputs to other blocks
appli_ack_o <= appli_ack;
appli_dat_o <= appli_data_rd;
host_ack_o <= host_ack;
host_dat_o <= host_data_rd;
activate_acq_o <= control_register(0);
deactivate_acq_o <= control_register(1);
load_utc_o <= control_register(2);
load_tdc_config_o <= control_register(3);
load_acam_config_o <= control_register(4);
read_acam_config_o <= control_register(5);
reset_acam_o <= control_register(6);
read_acam_status_o <= control_register(8);
read_ififo1_o <= control_register(9);
read_ififo2_o <= control_register(10);
read_start01_o <= control_register(11);
starting_utc_time_o <= starting_utc_time;
clk_freq_o <= clk_freq;
ref_clk_freq_o <= ref_clk_freq;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
retrig_freq_o <= retrig_freq;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
......@@ -244,7 +244,7 @@ architecture rtl of top_tdc is
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(19 downto 0);
class_adr_i : in std_logic_vector(g_width-1 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
......@@ -257,7 +257,7 @@ architecture rtl of top_tdc is
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(19 downto 0);
pipe_adr_i : in std_logic_vector(g_width-1 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
......@@ -295,6 +295,60 @@ architecture rtl of top_tdc is
tdc_clk_o : out std_logic
);
end component;
component reg_ctrl
generic(
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i : in std_logic;
appli_reset_i : in std_logic;
appli_adr_i : in std_logic_vector(g_width-1 downto 0);
appli_cyc_i : in std_logic;
appli_dat_i : in std_logic_vector(g_width-1 downto 0);
appli_stb_i : in std_logic;
appli_we_i : in std_logic;
appli_ack_o : out std_logic;
appli_dat_o : out std_logic_vector(g_width-1 downto 0);
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i : in std_logic;
host_reset_i : in std_logic;
host_adr_i : in std_logic_vector(g_width-1 downto 0);
host_cyc_i : in std_logic;
host_dat_i : in std_logic_vector(g_width-1 downto 0);
host_stb_i : in std_logic;
host_we_i : in std_logic;
host_ack_o : out std_logic;
host_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other application internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
-- configuration registers for the modules of the TDC core
starting_utc_time_o : out std_logic_vector(31 downto 0);
clk_freq_o : out std_logic_vector(31 downto 0);
ref_clk_freq_o : out std_logic_vector(31 downto 0);
start_phase_o : out std_logic_vector(31 downto 0);
one_hz_phase_o : out std_logic_vector(31 downto 0);
retrig_freq_o : out std_logic_vector(31 downto 0)
);
end component;
component gn4124_core
generic(
......@@ -435,25 +489,25 @@ signal dma_irq : std_logic_vector(1 downto 0);
signal irq_p : std_logic;
signal csr_adr : std_logic_vector(18 downto 0);
signal csr_cyc : std_logic_vector(0 downto 0);
signal csr_dat_r : std_logic_vector(31 downto 0);
signal csr_sel : std_logic_vector(3 downto 0);
signal csr_stb : std_logic;
signal csr_we : std_logic;
signal csr_cyc : std_logic_vector(0 downto 0);
signal csr_dat_w : std_logic_vector(31 downto 0);
signal csr_ack : std_logic_vector(0 downto 0);
signal csr_dat_w : std_logic_vector(31 downto 0);
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_cyc : std_logic;
signal dma_dat_w : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_cyc : std_logic;
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_ack : std_logic;
signal dma_dat_r : std_logic_vector(31 downto 0);
signal dma_stall : std_logic;
signal mem_class_adr : std_logic_vector(19 downto 0);
signal mem_class_adr : std_logic_vector(g_width-1 downto 0);
signal mem_class_cyc : std_logic;
signal mem_class_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal mem_class_stb : std_logic;
......@@ -461,7 +515,7 @@ signal mem_class_we : std_logic;
signal mem_class_ack : std_logic;
signal mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal mem_pipe_adr : std_logic_vector(19 downto 0);
signal mem_pipe_adr : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_cyc : std_logic;
signal mem_pipe_data_wr : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stb : std_logic;
......@@ -470,6 +524,40 @@ signal mem_pipe_ack : std_logic;
signal mem_pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stall : std_logic;
signal reg_appli_adr : std_logic_vector(g_width-1 downto 0);
signal reg_appli_cyc : std_logic;
signal reg_appli_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_appli_stb : std_logic;
signal reg_appli_we : std_logic;
signal reg_appli_ack : std_logic;
signal reg_appli_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_host_adr : std_logic_vector(g_width-1 downto 0);
signal reg_host_cyc : std_logic;
signal reg_host_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_host_stb : std_logic;
signal reg_host_we : std_logic;
signal reg_host_ack : std_logic;
signal reg_host_data_rd : std_logic_vector(g_width-1 downto 0);
signal activate_acq : std_logic;
signal deactivate_acq : std_logic;
signal load_utc : std_logic;
signal load_tdc_config : std_logic;
signal load_acam_config : std_logic;
signal read_acam_config : std_logic;
signal reset_acam : std_logic;
signal read_acam_status : std_logic;
signal read_ififo1 : std_logic;
signal read_ififo2 : std_logic;
signal read_start01 : std_logic;
signal starting_utc_time : std_logic_vector(31 downto 0);
signal clk_freq : std_logic_vector(31 downto 0);
signal ref_clk_freq : std_logic_vector(31 downto 0);
signal start_phase : std_logic_vector(31 downto 0);
signal one_hz_phase : std_logic_vector(31 downto 0);
signal retrig_freq : std_logic_vector(31 downto 0);
signal acam_refclk : std_logic;
signal clk : std_logic;
signal spec_clk : std_logic;
......@@ -617,6 +705,59 @@ begin
pipe_stall_o => mem_pipe_stall
);
reg_control_block: reg_ctrl
generic map(
g_width => g_width
)
port map(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i => clk,
appli_reset_i => general_reset,
appli_adr_i => reg_appli_adr,
appli_cyc_i => reg_appli_cyc,
appli_dat_i => reg_appli_data_wr,
appli_stb_i => reg_appli_stb,
appli_we_i => reg_appli_we,
appli_ack_o => reg_appli_ack,
appli_dat_o => reg_appli_data_rd,
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i => clk,
host_reset_i => general_reset,
host_adr_i => reg_host_adr,
host_cyc_i => reg_host_cyc,
host_dat_i => reg_host_data_wr,
host_stb_i => reg_host_stb,
host_we_i => reg_host_we,
host_ack_o => reg_host_ack,
host_dat_o => reg_host_data_rd,
-- control signals for interface with other application internal modules
activate_acq_o => activate_acq,
deactivate_acq_o => deactivate_acq,
load_utc_o => load_utc,
load_tdc_config_o => load_tdc_config,
load_acam_config_o => load_acam_config,
read_acam_config_o => read_acam_config,
reset_acam_o => reset_acam,
read_acam_status_o => read_acam_status,
read_ififo1_o => read_ififo1,
read_ififo2_o => read_ififo2,
read_start01_o => read_start01,
-- configuration registers for the modules of the TDC core
starting_utc_time_o => starting_utc_time,
clk_freq_o => clk_freq,
ref_clk_freq_o => ref_clk_freq,
start_phase_o => start_phase,
one_hz_phase_o => one_hz_phase,
retrig_freq_o => retrig_freq
);
gnum_interface_block: gn4124_core
generic map(
g_CSR_WB_SLAVES_NB => 1
......@@ -653,23 +794,23 @@ begin
wb_clk_i => clk,
wb_adr_o => csr_adr,
wb_cyc_o => csr_cyc,
wb_dat_o => csr_dat_w,
wb_sel_o => csr_sel,
wb_stb_o => csr_stb,
wb_we_o => csr_we,
wb_cyc_o => csr_cyc,
wb_dat_i => csr_dat_r,
wb_ack_i => csr_ack,
wb_dat_i => csr_dat_r,
dma_clk_i => clk,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_i,
dma_cyc_o => dma_cyc,
dma_dat_o => dma_dat_w,
dma_sel_o => dma_sel,
dma_stb_o => dma_stb,
dma_we_o => dma_we,
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_O,
dma_ack_i => dma_ack,
dma_dat_i => dma_dat_r,
dma_stall_i => dma_stall
);
......@@ -768,6 +909,8 @@ begin
-- internal signals
spec_led_green <= pll_ld_i;
-- CSR master connected directly to ACAM slave
-----------------------------------------------
-- acm_adr(19) <= '0';
-- acm_adr(18 downto 0) <= csr_adr;
-- acm_cyc <= csr_cyc(0);
......@@ -777,21 +920,55 @@ begin
-- csr_ack(0) <= acm_ack;
-- csr_dat_r <= acm_dat_r;
mem_class_adr(19) <= '0';
mem_class_adr(18 downto 0) <= csr_adr;
mem_class_cyc <= csr_cyc(0);
mem_class_stb <= csr_stb;
mem_class_we <= csr_we;
mem_class_data_wr(127 downto 32) <= (others=>'0');
mem_class_data_wr(31 downto 0) <= csr_dat_w;
csr_ack(0) <= mem_class_ack;
csr_dat_r <= mem_class_data_rd(31 downto 0);
mem_pipe_adr <= (others=>'0');
mem_pipe_cyc <= '0';
mem_pipe_stb <= '0';
mem_pipe_we <= '0';
mem_pipe_data_wr <= (others=>'0');
-- CSR master connected to circular buffer slave
-- DMA master connected to circular buffer pipelined slave
-----------------------------------------------------------
-- -- (address decoding)
-- mem_class_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 7)=x"400" else '0';
-- mem_class_adr(31 downto 19) <= (others=>'0');
-- mem_class_adr(18 downto 0) <= csr_adr;
--
-- mem_class_stb <= csr_stb;
-- mem_class_we <= csr_we;
-- mem_class_data_wr(127 downto 32) <= (others=>'0');
-- mem_class_data_wr(31 downto 0) <= csr_dat_w;
-- csr_ack(0) <= mem_class_ack;
-- csr_dat_r <= mem_class_data_rd(31 downto 0);
-- (address decoding)
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 9)=x"00000" & "000" else '0';
mem_pipe_adr <= dma_adr;
mem_pipe_stb <= dma_stb;
mem_pipe_we <= dma_we;
mem_pipe_data_wr <= dma_dat_w;
dma_ack <= mem_pipe_ack;
dma_dat_r <= mem_pipe_data_rd;
dma_stall <= mem_pipe_stall;
-- CSR master connected to register memory slave
-----------------------------------------------------------
-- -- (address decoding)
-- reg_appli_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 6)="0" & x"800" else '0';
-- reg_appli_adr(31 downto 19) <= (others=>'0');
-- reg_appli_adr(18 downto 0) <= csr_adr;
--
-- reg_appli_stb <= csr_stb;
-- reg_appli_we <= csr_we;
-- reg_appli_data_wr <= csr_dat_w;
-- csr_ack(0) <= reg_appli_ack;
-- csr_dat_r <= reg_appli_data_rd;
-- (address decoding)
reg_host_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 6)="0" & x"800" else '0';
reg_host_adr(31 downto 19) <= (others=>'0');
reg_host_adr(18 downto 0) <= csr_adr;
reg_host_stb <= csr_stb;
reg_host_we <= csr_we;
reg_host_data_wr <= csr_dat_w;
csr_ack(0) <= reg_host_ack;
csr_dat_r <= reg_host_data_rd;
-- inputs
-- gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
......
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