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FMC TDC 1ns 5cha - Gateware
Commit f238ebb5 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated submodules and tweaks to meet timing

parent fc3898af
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Showing with 1836 additions and 1618 deletions
general-cores @ 64f7e518
Subproject commit 96728bc02801f5343597e2a7bb916fde33dc0139
Subproject commit 64f7e518bab2bf0489077f4b9eb26e8cccbf1411
spec @ 44e9007a
Subproject commit cbe5c7ee4c1adcff1f4c987772066af26908062c
Subproject commit 44e9007a2953f91c686bcabf38b92d2f6ecfb217
svec @ 1b803764
Subproject commit 5224fb1b51a64b7b2454e840452b2d6f6acfaf71
Subproject commit 1b803764d842462233fb479d4cc0aa5418a9109f
vme64x-core @ 366ca4db
Subproject commit 633d31749b104d4ca04c569cf3e30c5a6c9902b5
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
wr-cores @ a72a4223
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
hdl/rtl/acam_timecontrol_interface.vhd
View file @ f238ebb5
......@@ -80,7 +80,7 @@ end entity;
--=================================================================================================
architecture rtl of acam_timecontrol_interface is
signal acam_intflag_f_edge_p : std_logic;
signal acam_intflag_f_edge_p, stop_dis_d1 : std_logic;
signal start_pulse, wait_for_utc, rst_n, wait_for_state_active : std_logic;
--=================================================================================================
......@@ -108,7 +108,7 @@ begin
wait_for_utc <= '0';
start_pulse <= '0';
wait_for_state_active <= '0';
stop_dis_o <= '1';
stop_dis_d1 <= '1';
else
if activate_acq_p_i = '1' then
wait_for_utc <= '1';
......@@ -119,7 +119,7 @@ begin
wait_for_state_active <= '1';
elsif wait_for_state_active = '1' and state_active_p_i = '1' then
-- data_engine starts following ACAM EF
stop_dis_o <= '0';
stop_dis_d1 <= '0';
wait_for_state_active <= '0';
else
start_pulse <= '0';
......@@ -128,6 +128,17 @@ begin
end if;
end process;
stop_dis_extra_dff : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
stop_dis_o <= '1';
else
stop_dis_o <= stop_dis_d1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
extend_pulse : gc_extend_pulse
generic map (g_width => 4)
......
hdl/syn/spec/syn_extra_steps.tcl
View file @ f238ebb5
......@@ -16,8 +16,8 @@ xilinx::project open $project_file
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "Off" -process "Map"
xilinx::project set "Enable Multi-Threading" "2" -process "Place & Route"
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
......@@ -27,7 +27,7 @@ xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Placer Effort Level Map" "High"
xilinx::project set "Placer Extra Effort Map" "Continue on Impossible"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Continue on Impossible"
xilinx::project save
......
hdl/syn/spec/wr_spec_tdc.xise
View file @ f238ebb5
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/svec/Manifest.py
View file @ f238ebb5
......@@ -10,4 +10,29 @@ syn_top = "wr_svec_tdc"
syn_project = "wr_svec_tdc.xise"
syn_tool = "ise"
modules = { "local" : [ "../../top/svec" ] }
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/syn/svec/syn_extra_steps.tcl 0 → 100644
View file @ f238ebb5
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Duplication Map" "On"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Placer Effort Level Map" "High"
xilinx::project set "Placer Extra Effort Map" "Continue on Impossible"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/syn/svec/wr_svec_tdc.xise
View file @ f238ebb5
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/svec/wr_svec_tdc.ucf
View file @ f238ebb5
......@@ -387,3 +387,10 @@ NET "fmc1_tdc_data_bus_io[0]" SLEW = FAST;
#TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
#----------------------------------------
# IOB exceptions
#----------------------------------------
INST "cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_fmc_onewire/*" IOB = FALSE;
INST "cmp_tdc_mezzanine_2/cmp_tdc_mezz/cmp_fmc_onewire/*" IOB = FALSE;
hdl/top/svec/wr_svec_tdc.vhd
View file @ f238ebb5
......@@ -368,6 +368,7 @@ architecture rtl of wr_svec_tdc is
-- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1 and TDC2
signal clk_ref_125m : std_logic;
signal clk_ref_div2 : std_logic;
signal clk_dmtd_125m : std_logic;
signal fmc0_tdc_clk_125m : std_logic;
signal fmc1_tdc_clk_125m : std_logic;
signal areset_n : std_logic;
......@@ -456,6 +457,7 @@ begin
clk_aux_i(1) => fmc1_tdc_clk_125m,
clk_10m_ext_i => '0',
pps_ext_i => '0',
clk_dmtd_125m_o => clk_dmtd_125m,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
......
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