Commit e69cf523 authored by Evangelia Gousiou's avatar Evangelia Gousiou

Merge branch 'tom-may08' into feature/convention

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parents 182ada36 1bd089d1
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
Subproject commit 3879a6d33227704f8925e76eb68064da155de2b0
Subproject commit b3d2bfc24e01b95acef5d4240cb476c3f2f42566
Subproject commit cbe5c7ee4c1adcff1f4c987772066af26908062c
......@@ -448,7 +448,8 @@ begin
gen_with_dma_readout : if g_USE_DMA_READOUT generate
U_DMA_Engine : entity work.tdc_dma_engine
generic map (
g_CLOCK_FREQ => 62500000)
g_CLOCK_FREQ => 62500000,
g_SIMULATION => g_SIMULATION)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
......@@ -656,7 +657,8 @@ begin
end loop;
end process;
timestamp_ready <= (others => '1');
sim_timestamp_ready_o <= '1'; -- fixme: do we care about flow control in simulations?
end generate gen_use_fake_timestamps;
......
......@@ -159,7 +159,7 @@ package tdc_core_pkg is
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
addr_last => x"000000000000003F",
product =>
(vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000605", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
......@@ -192,7 +192,7 @@ package tdc_core_pkg is
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
addr_last => x"000000000000003F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
......@@ -814,6 +814,7 @@ package body tdc_core_pkg is
function f_pack_raw_acam_timestamp ( ts : t_raw_acam_timestamp ) return std_logic_vector is
variable rv : std_logic_vector(127 downto 0);
begin
rv:= (others => '0');
rv(31 downto 0) := ts.seconds;
rv(48 downto 32) := ts.acam_bins(16 downto 0);
rv(56 downto 49) := ts.acam_start_nb;
......
......@@ -10,7 +10,8 @@ use work.gencores_pkg.all;
entity tdc_dma_engine is
generic (
g_CLOCK_FREQ : integer := 62500000
g_CLOCK_FREQ : integer := 62500000;
g_SIMULATION : boolean := false
);
port (
clk_i : in std_logic;
......@@ -55,9 +56,19 @@ architecture rtl of tdc_dma_engine is
3 => x"000001c0",
4 => x"000001c0");
constant c_TIMER_PERIOD_MS : integer := 1;
constant c_TIMER_DIVIDER_VALUE : integer := g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
impure function f_pick_timer_divider return integer is
begin
if g_SIMULATION then
return 1000;
else
return g_CLOCK_FREQ * c_TIMER_PERIOD_MS / 1000 - 1;
end if;
end f_pick_timer_divider;
constant c_TIMER_DIVIDER_VALUE : integer := f_pick_timer_divider;
signal irq_tick_div : unsigned(15 downto 0);
signal irq_tick : std_logic;
......
`define SPEC_BASE_REGS_SIZE 8192
`define ADDR_SPEC_BASE_REGS_METADATA 'h0
`define SPEC_BASE_REGS_METADATA_SIZE 64
`define ADDR_SPEC_BASE_REGS_CSR 'h40
`define SPEC_BASE_REGS_CSR_SIZE 32
`define ADDR_SPEC_BASE_REGS_CSR_APP_OFFSET 'h40
`define ADDR_SPEC_BASE_REGS_CSR_RESETS 'h44
`define SPEC_BASE_REGS_CSR_RESETS_GLOBAL_OFFSET 0
`define SPEC_BASE_REGS_CSR_RESETS_GLOBAL 'h1
`define SPEC_BASE_REGS_CSR_RESETS_APPL_OFFSET 1
`define SPEC_BASE_REGS_CSR_RESETS_APPL 'h2
`define ADDR_SPEC_BASE_REGS_CSR_FMC_PRESENCE 'h48
`define ADDR_SPEC_BASE_REGS_CSR_GN4124_STATUS 'h4c
`define ADDR_SPEC_BASE_REGS_CSR_DDR_STATUS 'h50
`define SPEC_BASE_REGS_CSR_DDR_STATUS_CALIB_DONE_OFFSET 0
`define SPEC_BASE_REGS_CSR_DDR_STATUS_CALIB_DONE 'h1
`define ADDR_SPEC_BASE_REGS_CSR_PCB_REV 'h54
`define SPEC_BASE_REGS_CSR_PCB_REV_REV_OFFSET 0
`define SPEC_BASE_REGS_CSR_PCB_REV_REV 'hf
`define ADDR_SPEC_BASE_REGS_THERM_ID 'h70
`define SPEC_BASE_REGS_THERM_ID_SIZE 16
`define ADDR_SPEC_BASE_REGS_FMC_I2C 'h80
`define SPEC_BASE_REGS_FMC_I2C_SIZE 32
`define ADDR_SPEC_BASE_REGS_FLASH_SPI 'ha0
`define SPEC_BASE_REGS_FLASH_SPI_SIZE 32
`define ADDR_SPEC_BASE_REGS_DMA 'hc0
`define SPEC_BASE_REGS_DMA_SIZE 64
`define ADDR_SPEC_BASE_REGS_VIC 'h100
`define SPEC_BASE_REGS_VIC_SIZE 256
`define ADDR_SPEC_BASE_REGS_BUILDINFO 'h200
`define SPEC_BASE_REGS_BUILDINFO_SIZE 256
`define ADDR_SPEC_BASE_REGS_WRC_REGS 'h1000
`define SPEC_BASE_REGS_WRC_REGS_SIZE 4096
`define ADDR_TDC_BUF_CSR 5'h0
`define TDC_BUF_CSR_ENABLE_OFFSET 0
`define TDC_BUF_CSR_ENABLE 32'h00000001
`define TDC_BUF_CSR_IRQ_TIMEOUT_OFFSET 1
`define TDC_BUF_CSR_IRQ_TIMEOUT 32'h000007fe
`define TDC_BUF_CSR_BURST_SIZE_OFFSET 11
`define TDC_BUF_CSR_BURST_SIZE 32'h001ff800
`define TDC_BUF_CSR_SWITCH_BUFFERS_OFFSET 21
`define TDC_BUF_CSR_SWITCH_BUFFERS 32'h00200000
`define TDC_BUF_CSR_DONE_OFFSET 22
`define TDC_BUF_CSR_DONE 32'h00400000
`define TDC_BUF_CSR_OVERFLOW_OFFSET 23
`define TDC_BUF_CSR_OVERFLOW 32'h00800000
`define ADDR_TDC_BUF_CUR_BASE 5'h4
`define ADDR_TDC_BUF_CUR_COUNT 5'h8
`define ADDR_TDC_BUF_CUR_SIZE 5'hc
`define TDC_BUF_CUR_SIZE_SIZE_OFFSET 0
`define TDC_BUF_CUR_SIZE_SIZE 32'h3fffffff
`define TDC_BUF_CUR_SIZE_VALID_OFFSET 30
`define TDC_BUF_CUR_SIZE_VALID 32'h40000000
`define ADDR_TDC_BUF_NEXT_BASE 5'h10
`define ADDR_TDC_BUF_NEXT_SIZE 5'h14
`define TDC_BUF_NEXT_SIZE_SIZE_OFFSET 0
`define TDC_BUF_NEXT_SIZE_SIZE 32'h3fffffff
`define TDC_BUF_NEXT_SIZE_VALID_OFFSET 30
`define TDC_BUF_NEXT_SIZE_VALID 32'h40000000
`define ADDR_TDC_EIC_EIC_IDR 6'h20
`define ADDR_TDC_EIC_EIC_IDR 6'h00
`define TDC_EIC_EIC_IDR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IDR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IDR_TDC_FIFO2_OFFSET 1
......@@ -19,7 +19,7 @@
`define TDC_EIC_EIC_IDR_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IDR_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IDR_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_IER 6'h24
`define ADDR_TDC_EIC_EIC_IER 6'h04
`define TDC_EIC_EIC_IER_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IER_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IER_TDC_FIFO2_OFFSET 1
......@@ -40,7 +40,7 @@
`define TDC_EIC_EIC_IER_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IER_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IER_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_IMR 6'h28
`define ADDR_TDC_EIC_EIC_IMR 6'h08
`define TDC_EIC_EIC_IMR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_IMR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_IMR_TDC_FIFO2_OFFSET 1
......@@ -61,7 +61,7 @@
`define TDC_EIC_EIC_IMR_TDC_DMA4 32'h00000100
`define TDC_EIC_EIC_IMR_TDC_DMA5_OFFSET 9
`define TDC_EIC_EIC_IMR_TDC_DMA5 32'h00000200
`define ADDR_TDC_EIC_EIC_ISR 6'h2c
`define ADDR_TDC_EIC_EIC_ISR 6'h0c
`define TDC_EIC_EIC_ISR_TDC_FIFO1_OFFSET 0
`define TDC_EIC_EIC_ISR_TDC_FIFO1 32'h00000001
`define TDC_EIC_EIC_ISR_TDC_FIFO2_OFFSET 1
......
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:29c1fdd2e474c7bdb52e11db26e94b502814290e" & LF
& "commit:745e912cee76d4ee9e8c3fded1c9ee9b5e694cdd" & LF
& "syntool:modelsim" & LF
& "syndate:2020-04-24, 17:39 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
& "syndate:2020-04-24, 22:37 CEST" & LF
& "synauth:Tomasz Wlostowski" & LF;
end buildinfo_pkg;
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......@@ -400,7 +400,7 @@ architecture rtl of wr_spec_tdc is
end if;
end f_to_string;
signal dma_reg_adr : std_logic_vector(31 downto 0);
signal dma_wb_adr : std_logic_vector(31 downto 0);
......@@ -409,6 +409,8 @@ architecture rtl of wr_spec_tdc is
--=================================================================================================
begin
dma_wb_adr <= "00" & fmc0_wb_ddr_out.adr(31 downto 2);
-- synthesis translate_off
sim_ts <= sim_timestamp_i;
sim_ts_valid <= sim_timestamp_valid_i;
......@@ -556,11 +558,11 @@ begin
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
----------------------------------
ddr_dma_clk_i => clk_ref_125m,
ddr_dma_rst_n_i => rst_ref_125m_n,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_cyc_i => fmc0_wb_ddr_out.cyc,
ddr_dma_wb_stb_i => fmc0_wb_ddr_out.stb,
ddr_dma_wb_adr_i => fmc0_wb_ddr_out.adr,
ddr_dma_wb_adr_i => dma_wb_adr,
ddr_dma_wb_sel_i => fmc0_wb_ddr_out.sel,
ddr_dma_wb_we_i => fmc0_wb_ddr_out.we,
ddr_dma_wb_dat_i => fmc0_wb_ddr_out.dat,
......@@ -705,7 +707,13 @@ begin
dma_wb_o => fmc0_wb_ddr_out,
irq_o => irq_vector(0),
clk_125m_tdc_o => tdc0_clk_125m);
clk_125m_tdc_o => tdc0_clk_125m,
sim_timestamp_i => sim_ts,
sim_timestamp_valid_i => sim_ts_valid,
sim_timestamp_ready_o => sim_ts_ready
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
fmc0_wb_ddr_in.err <= '0';
......
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