Commit dc894263 authored by penacoba's avatar penacoba

git-svn-id: http://svn.ohwr.org/fmc-tdc@50 85dfdc96-de2c-444c-878d-45b388be74a9
parent fbdc4006
......@@ -27,7 +27,8 @@ use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
entity acam_databus_interface is
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- signals external to the chip: interface with acam
......@@ -43,11 +44,17 @@ entity acam_databus_interface is
rd_n_o : out std_logic;
wr_n_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_ef1_o : out std_logic;
acam_ef2_o : out std_logic;
acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic;
-- wishbone slave signals internal to the chip: interface with other modules
clk_i : in std_logic;
reset_i : in std_logic;
adr_i : in std_logic_vector(19 downto 0);
adr_i : in std_logic_vector(g_span-1 downto 0);
cyc_i : in std_logic;
dat_i : in std_logic_vector(g_width-1 downto 0);
stb_i : in std_logic;
......@@ -74,7 +81,7 @@ signal lf2 : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal adr : std_logic_vector(19 downto 0);
signal adr : std_logic_vector(g_span-1 downto 0);
signal cyc : std_logic;
signal stb : std_logic;
signal we : std_logic;
......@@ -84,6 +91,7 @@ signal rd : std_logic;
signal rd_extend : std_logic;
signal wr : std_logic;
signal wr_extend : std_logic;
signal wr_remove : std_logic;
signal ack : std_logic;
----------------------------------------------------------------------------------------------------
......@@ -109,6 +117,7 @@ begin
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
if stb ='1' and cyc ='1' then
if we = '1' then
nxt_acam_data_st <= wr_start;
......@@ -124,6 +133,7 @@ begin
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= read;
......@@ -132,6 +142,7 @@ begin
cs_extend <= '1';
rd_extend <= '1';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= rd_ack;
......@@ -140,6 +151,7 @@ begin
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
......@@ -148,6 +160,7 @@ begin
cs_extend <= '1';
rd_extend <= '0';
wr_extend <= '1';
wr_remove <= '0';
nxt_acam_data_st <= write;
......@@ -156,6 +169,7 @@ begin
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '1';
nxt_acam_data_st <= wr_ack;
......@@ -164,6 +178,7 @@ begin
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
......@@ -172,6 +187,7 @@ begin
cs_extend <= '0';
rd_extend <= '0';
wr_extend <= '0';
wr_remove <= '0';
nxt_acam_data_st <= idle;
end case;
......@@ -179,7 +195,7 @@ begin
cs <= ((stb and cyc) or cs_extend) and not(ack);
rd <= ((stb and cyc and not(we)) or rd_extend) and not(ack);
wr <= ((stb and cyc and we) or wr_extend) and not(ack);
wr <= ((stb and cyc and we) or wr_extend) and not(wr_remove) and not(ack);
-- inputs from other blocks
clk <= clk_i;
......@@ -196,13 +212,29 @@ begin
dat_o <= ef1 & ef2 & lf1 & lf2 & data_bus_io;
-- inputs from the ACAM
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
input_registers: process
begin
if reset ='1' then
ef1 <= '1';
ef2 <= '1';
lf1 <= '1';
lf2 <= '1';
else
ef1 <= ef1_i;
ef2 <= ef2_i;
lf1 <= lf1_i;
lf2 <= lf2_i;
end if;
wait until clk ='1';
end process;
-- outputs to the ACAM
address_o <= adr(3 downto 0);
acam_ef1_o <= ef1;
acam_ef2_o <= ef2;
acam_lf1_o <= lf1;
acam_lf2_o <= lf2;
output_registers: process
begin
......
......@@ -29,14 +29,15 @@ use IEEE.numeric_std.all;
----------------------------------------------------------------------------------------------------
entity circular_buffer is
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface RAM with the internal modules providing the timestamps
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_width-1 downto 0);
class_adr_i : in std_logic_vector(g_span-1 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
......@@ -49,7 +50,7 @@ entity circular_buffer is
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_width-1 downto 0);
pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
......
......@@ -29,27 +29,42 @@ use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
entity data_engine is
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone master signals internal to the chip: interface with other modules
-- wishbone master signals internal to the chip: interface with the ACAM data core
ack_i : in std_logic;
dat_i : in std_logic_vector(g_width-1 downto 0);
adr_o : out std_logic_vector(19 downto 0);
adr_o : out std_logic_vector(g_span-1 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(g_width-1 downto 0);
stb_o : out std_logic;
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
acam_config_reg_i : in config_vector;
clk_i : in std_logic;
load_acam_config_i : in std_logic;
one_hz_p_i : in std_logic;
reset_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef2_i : in std_logic;
activate_acq_i : in std_logic;
deactivate_acq_i : in std_logic;
load_acam_config_i : in std_logic;
read_acam_config_i : in std_logic;
read_acam_status_i : in std_logic;
read_ififo1_i : in std_logic;
read_ififo2_i : in std_logic;
read_start01_i : in std_logic;
reset_acam_i : in std_logic;
acam_config_i : in config_vector;
acam_start01_o : out std_logic_vector(16 downto 0);
acam_config_rdbk_o : out config_vector;
acam_status_o : out std_logic_vector(g_width-1 downto 0);
acam_ififo1_o : out std_logic_vector(g_width-1 downto 0);
acam_ififo2_o : out std_logic_vector(g_width-1 downto 0);
acam_start01_o : out std_logic_vector(g_width-1 downto 0);
acam_timestamp_o : out std_logic_vector(28 downto 0);
acam_timestamp_valid_o : out std_logic
);
......@@ -60,15 +75,47 @@ end data_engine;
----------------------------------------------------------------------------------------------------
architecture rtl of data_engine is
type engine_state_ty is (idle, wr_config, rest_wr, rd_timestamp, rest_rd);
type engine_state_ty is (active, inactive, get_stamp1, get_stamp2,
wr_config, rdbk_config, rd_status, rd_ififo1, rd_ififo2, rd_start01, wr_reset);
signal engine_st, nxt_engine_st : engine_state_ty;
signal ef1 : std_logic;
signal ef2 : std_logic;
signal acam_ef1 : std_logic;
signal acam_ef2 : std_logic;
signal acam_ack : std_logic;
signal acam_adr : std_logic_vector(7 downto 0);
signal acam_cyc : std_logic;
signal acam_stb : std_logic;
signal acam_we : std_logic;
signal acam_data_rd : std_logic_vector(g_width-1 downto 0);
signal acam_data_wr : std_logic_vector(g_width-1 downto 0);
signal clk : std_logic;
signal reset : std_logic;
signal activate_acq : std_logic;
signal deactivate_acq : std_logic;
signal load_acam_config : std_logic;
signal read_acam_config : std_logic;
signal read_acam_status : std_logic;
signal read_ififo1 : std_logic;
signal read_ififo2 : std_logic;
signal read_start01 : std_logic;
signal reset_acam : std_logic;
signal config_adr_counter : unsigned(7 downto 0);
signal acam_config : config_vector;
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal reset_word : std_logic_vector(g_width-1 downto 0);
signal reg4 : std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
......@@ -77,22 +124,348 @@ begin
data_engine_seq_fsm: process
begin
if reset ='1' then
engine_st <= idle;
engine_st <= inactive;
else
engine_st <= nxt_engine_st;
end if;
wait until clk ='1';
end process;
-- data_engine_comb_fsm: process
-- begin
-- case engine_st is
-- when waiting =>
--
data_engine_comb_fsm: process(engine_st, activate_acq, deactivate_acq, acam_ef1, acam_ef2,
load_acam_config, read_acam_config, read_acam_status,
read_ififo1, read_ififo2, read_start01, reset_acam,
acam_ack, acam_adr)
begin
case engine_st is
when inactive =>
acam_cyc <= '0';
acam_stb <= '0';
acam_we <= '0';
if activate_acq ='1' then
nxt_engine_st <= active;
elsif load_acam_config ='1' then
nxt_engine_st <= wr_config;
elsif read_acam_config ='1' then
nxt_engine_st <= rdbk_config;
elsif read_acam_status ='1' then
nxt_engine_st <= rd_status;
elsif read_ififo1 ='1' then
nxt_engine_st <= rd_ififo1;
elsif read_ififo2 ='1' then
nxt_engine_st <= rd_ififo2;
elsif read_start01 ='1' then
nxt_engine_st <= rd_start01;
elsif reset_acam ='1' then
nxt_engine_st <= wr_reset;
else
nxt_engine_st <= inactive;
end if;
when active =>
acam_cyc <= '0';
acam_stb <= '0';
acam_we <= '0';
if deactivate_acq ='1' then
nxt_engine_st <= inactive;
elsif acam_ef1 ='1' then
nxt_engine_st <= get_stamp1;
elsif acam_ef2 ='1' then
nxt_engine_st <= get_stamp2;
else
nxt_engine_st <= active;
end if;
when get_stamp1 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
if acam_ef2 ='1' then
nxt_engine_st <= get_stamp2;
else
nxt_engine_st <= active;
end if;
else
nxt_engine_st <= get_stamp1;
end if;
when get_stamp2 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
if acam_ef1 ='1' then
nxt_engine_st <= get_stamp1;
else
nxt_engine_st <= active;
end if;
else
nxt_engine_st <= get_stamp2;
end if;
when wr_config =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '1';
if acam_ack ='1' and acam_adr =x"0E" then
nxt_engine_st <= inactive;
else
nxt_engine_st <= wr_config;
end if;
when rdbk_config =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' and acam_adr =x"0E" then
nxt_engine_st <= inactive;
else
nxt_engine_st <= rdbk_config;
end if;
when rd_status =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
else
nxt_engine_st <= rd_status;
end if;
when rd_ififo1 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
else
nxt_engine_st <= rd_ififo1;
end if;
when rd_ififo2 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
else
nxt_engine_st <= rd_ififo2;
end if;
when rd_start01 =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '0';
if acam_ack ='1' then
nxt_engine_st <= inactive;
else
nxt_engine_st <= rd_start01;
end if;
when wr_reset =>
acam_cyc <= '1';
acam_stb <= '1';
acam_we <= '1';
if acam_ack ='1' then
nxt_engine_st <= inactive;
else
nxt_engine_st <= wr_reset;
end if;
when others =>
acam_cyc <= '0';
acam_stb <= '0';
acam_we <= '0';
nxt_engine_st <= inactive;
end case;
end process;
address_generation: process(engine_st, config_adr_counter)
begin
case engine_st is
when inactive =>
acam_adr <= x"00";
when active =>
acam_adr <= x"00";
when get_stamp1 =>
acam_adr <= x"08";
when get_stamp2 =>
acam_adr <= x"09";
when wr_config =>
acam_adr <= std_logic_vector(config_adr_counter);
when rdbk_config =>
acam_adr <= std_logic_vector(config_adr_counter);
when rd_status =>
acam_adr <= x"0C";
when rd_ififo1 =>
acam_adr <= x"08";
when rd_ififo2 =>
acam_adr <= x"09";
when rd_start01 =>
acam_adr <= x"0A";
when wr_reset =>
acam_adr <= x"04";
when others =>
acam_adr <= x"00";
end case;
end process;
config_adr: process -- process to generate the valid addresses for the ACAM registers
begin
if reset ='1' then
config_adr_counter <= x"00";
elsif load_acam_config ='1' or read_acam_config ='1' then
config_adr_counter <= x"00";
elsif acam_ack ='1' then
if config_adr_counter= x"0E" then
config_adr_counter <= x"0E";
elsif config_adr_counter= x"0C" then
config_adr_counter <= x"0E";
elsif config_adr_counter= x"07" then
config_adr_counter <= x"0B";
else
config_adr_counter <= config_adr_counter + 1;
end if;
end if;
wait until clk ='1';
end process;
data_config_decoding: process(acam_adr, engine_st, acam_config, reset_word)
begin
case acam_adr is
when x"00" =>
acam_data_wr <= acam_config(0);
when x"01" =>
acam_data_wr <= acam_config(1);
when x"02" =>
acam_data_wr <= acam_config(2);
when x"03" =>
acam_data_wr <= acam_config(3);
when x"04" =>
if engine_st = wr_reset then
acam_data_wr <= reset_word;
else
acam_data_wr <= acam_config(4);
end if;
when x"05" =>
acam_data_wr <= acam_config(5);
when x"06" =>
acam_data_wr <= acam_config(6);
when x"07" =>
acam_data_wr <= acam_config(7);
when x"0B" =>
acam_data_wr <= acam_config(8);
when x"0C" =>
acam_data_wr <= acam_config(9);
when x"0E" =>
acam_data_wr <= acam_config(10);
when others =>
acam_data_wr <= (others =>'0');
end case;
end process;
data_readback_decoding: process
begin
if acam_cyc ='1' and acam_stb ='1' and acam_ack ='1' and acam_we ='0' then
if acam_adr= x"00" then
acam_config_rdbk(0) <= acam_data_rd;
end if;
if acam_adr= x"01" then
acam_config_rdbk(1) <= acam_data_rd;
end if;
if acam_adr= x"02" then
acam_config_rdbk(2) <= acam_data_rd;
end if;
if acam_adr= x"03" then
acam_config_rdbk(3) <= acam_data_rd;
end if;
if acam_adr= x"04" then
acam_config_rdbk(4) <= acam_data_rd;
end if;
if acam_adr= x"05" then
acam_config_rdbk(5) <= acam_data_rd;
end if;
if acam_adr= x"06" then
acam_config_rdbk(6) <= acam_data_rd;
end if;
if acam_adr= x"07" then
acam_config_rdbk(7) <= acam_data_rd;
end if;
if acam_adr= x"0B" then
acam_config_rdbk(8) <= acam_data_rd;
end if;
if acam_adr= x"0C" then
acam_config_rdbk(9) <= acam_data_rd;
end if;
if acam_adr= x"0E" then
acam_config_rdbk(10) <= acam_data_rd;
end if;
if acam_adr= x"08" then
acam_ififo1 <= acam_data_rd;
end if;
if acam_adr= x"09" then
acam_ififo2 <= acam_data_rd;
end if;
if acam_adr= x"0A" then
acam_start01 <= acam_data_rd;
end if;
end if;
wait until clk ='1';
end process;
acam_status <= acam_config_rdbk(9);
reg4 <= acam_config(4);
reset_word <= reg4(31 downto 24) & "01" & reg4(21 downto 0);
-- inputs
clk <= clk_i;
reset <= reset_i;
acam_ack <= ack_i;
acam_data_rd <= dat_i;
acam_ef1 <= acam_ef1_i;
acam_ef2 <= acam_ef2_i;
activate_acq <= activate_acq_i;
deactivate_acq <= deactivate_acq_i;
load_acam_config <= load_acam_config_i;
read_acam_config <= read_acam_config_i;
read_acam_status <= read_acam_status_i;
read_ififo1 <= read_ififo1_i;
read_ififo2 <= read_ififo2_i;
read_start01 <= read_start01_i;
reset_acam <= reset_acam_i;
acam_config <= acam_config_i;
--outputs
adr_o <= x"000000" & acam_adr;
cyc_o <= acam_cyc;
dat_o <= acam_data_wr;
stb_o <= acam_stb;
we_o <= acam_we;
acam_config_rdbk_o <= acam_config_rdbk;
acam_status_o <= acam_status;
acam_ififo1_o <= acam_ififo1;
acam_ififo2_o <= acam_ififo2;
acam_start01_o <= acam_start01;
end rtl;
----------------------------------------------------------------------------------------------------
......
......@@ -6,8 +6,8 @@
-- author : G. Penacoba
-- date : Oct 2011
-- version : Revision 1
-- description : contains the RAM block (64 x 32) and the wishbone classic slave interfaces.
-- Processes the TDC_control register.
-- description : Interfaces with the CSR wishbone bus of the GNUM core. Holds the configuration
-- registers for the ACAM and other modules of the TDC core.
-- dependencies:
-- references :
-- modified by :
......@@ -21,61 +21,59 @@
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
----------------------------------------------------------------------------------------------------
-- entity declaration for reg_ctrl
----------------------------------------------------------------------------------------------------
entity reg_ctrl is
generic(
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i : in std_logic;
appli_reset_i : in std_logic;
appli_adr_i : in std_logic_vector(g_width-1 downto 0);
appli_cyc_i : in std_logic;
appli_dat_i : in std_logic_vector(g_width-1 downto 0);
appli_stb_i : in std_logic;
appli_we_i : in std_logic;
appli_ack_o : out std_logic;
appli_dat_o : out std_logic_vector(g_width-1 downto 0);
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i : in std_logic;
host_reset_i : in std_logic;
reg_clk_i : in std_logic;
reg_reset_i : in std_logic;
host_adr_i : in std_logic_vector(g_width-1 downto 0);
host_cyc_i : in std_logic;
host_dat_i : in std_logic_vector(g_width-1 downto 0);
host_stb_i : in std_logic;
host_we_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
host_ack_o : out std_logic;
host_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other application internal modules
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
-- configuration registers for the modules of the TDC core
starting_utc_time_o : out std_logic_vector(31 downto 0);
clk_freq_o : out std_logic_vector(31 downto 0);
ref_clk_freq_o : out std_logic_vector(31 downto 0);
start_phase_o : out std_logic_vector(31 downto 0);
one_hz_phase_o : out std_logic_vector(31 downto 0);
retrig_freq_o : out std_logic_vector(31 downto 0)
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
current_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
clk_freq_o : out std_logic_vector(g_width-1 downto 0);
ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
);
end reg_ctrl;
......@@ -84,54 +82,52 @@ end reg_ctrl;
----------------------------------------------------------------------------------------------------
architecture rtl of reg_ctrl is
component reg_mem_gen_v6_2
port(
clka : in std_logic;
addra : in std_logic_vector(5 downto 0);
dina : in std_logic_vector(31 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
douta : out std_logic_vector(31 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(5 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
doutb : out std_logic_vector(31 downto 0)
);
end component;
signal appli_ack : std_logic;
signal appli_adr : std_logic_vector(5 downto 0);
signal appli_clk : std_logic;
signal appli_cyc : std_logic;
signal appli_data_rd : std_logic_vector(g_width-1 downto 0);
signal appli_data_wr : std_logic_vector(g_width-1 downto 0);
signal appli_en : std_logic;
signal appli_reset : std_logic;
signal appli_stb : std_logic;
signal appli_we : std_logic_vector(0 downto 0);
signal host_ack : std_logic;
signal host_adr : std_logic_vector(5 downto 0);
signal host_clk : std_logic;
signal host_cyc : std_logic;
signal host_data_rd : std_logic_vector(g_width-1 downto 0);
signal host_data_wr : std_logic_vector(g_width-1 downto 0);
signal host_en : std_logic;
signal host_reset : std_logic;
signal host_stb : std_logic;
signal host_we : std_logic_vector(0 downto 0);
signal starting_utc_time : std_logic_vector(31 downto 0);
signal clk_freq : std_logic_vector(31 downto 0);
signal ref_clk_freq : std_logic_vector(31 downto 0);
signal start_phase : std_logic_vector(31 downto 0);
signal one_hz_phase : std_logic_vector(31 downto 0);
signal retrig_freq : std_logic_vector(31 downto 0);
signal control_register : std_logic_vector(31 downto 0);
--component reg_mem_gen_v6_2
-- port(
-- clka : in std_logic;
-- addra : in std_logic_vector(5 downto 0);
-- dina : in std_logic_vector(31 downto 0);
-- ena : in std_logic;
-- wea : in std_logic_vector(0 downto 0);
-- douta : out std_logic_vector(31 downto 0);
--
-- clkb : in std_logic;
-- addrb : in std_logic_vector(5 downto 0);
-- dinb : in std_logic_vector(31 downto 0);
-- enb : in std_logic;
-- web : in std_logic_vector(0 downto 0);
-- doutb : out std_logic_vector(31 downto 0)
-- );
--end component;
signal reg_ack : std_logic;
signal reg_adr : std_logic_vector(7 downto 0);
signal reg_clk : std_logic;
signal reg_cyc : std_logic;
signal reg_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_en : std_logic;
signal reg_reset : std_logic;
signal reg_stb : std_logic;
signal reg_we : std_logic;
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal current_utc : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal clk_freq : std_logic_vector(g_width-1 downto 0);
signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal retrig_freq : std_logic_vector(g_width-1 downto 0);
signal control_register : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
----------------------------------------------------------------------------------------------------
......@@ -139,138 +135,216 @@ signal clear_ctrl_reg : std_logic;
----------------------------------------------------------------------------------------------------
begin
-- Wishbone classic interface compatible slave for the application side
application_interface: process
-- Wishbone classic interface compatible slave for the side of the communication with the host
csr_interface: process
begin
if appli_reset ='1' then
appli_ack <= '0';
if reg_reset ='1' then
reg_ack <= '0';
else
appli_ack <= appli_stb and appli_cyc;
reg_ack <= reg_stb and reg_cyc;
end if;
wait until appli_clk ='1';
wait until reg_clk ='1';
end process;
-- Wishbone classic interface compatible slave for the side of the communication with the host
host_side_interface: process
-- config registers for ACAM
acam_config_reg: process
begin
if host_reset ='1' then
host_ack <= '0';
else
host_ack <= host_stb and host_cyc;
if reg_reset ='1' then
acam_config(0) <= (others =>'0');
acam_config(1) <= (others =>'0');
acam_config(2) <= (others =>'0');
acam_config(3) <= (others =>'0');
acam_config(4) <= (others =>'0');
acam_config(5) <= (others =>'0');
acam_config(6) <= (others =>'0');
acam_config(7) <= (others =>'0');
acam_config(8) <= (others =>'0');
acam_config(9) <= (others =>'0');
acam_config(10) <= (others =>'0');
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"00" then -- corresponds to address 80000 of the gnum BAR 0
acam_config(0) <= reg_data_wr;
end if;
if reg_adr = x"01" then -- corresponds to address 80004 of the gnum BAR 00
acam_config(1) <= reg_data_wr;
end if;
if reg_adr = x"02" then -- corresponds to address 80008 of the gnum BAR 0
acam_config(2) <= reg_data_wr;
end if;
if reg_adr = x"03" then -- corresponds to address 8000C of the gnum BAR 0
acam_config(3) <= reg_data_wr;
end if;
if reg_adr = x"04" then -- corresponds to address 80010 of the gnum BAR 0
acam_config(4) <= reg_data_wr;
end if;
if reg_adr = x"05" then -- corresponds to address 80014 of the gnum BAR 0
acam_config(5) <= reg_data_wr;
end if;
if reg_adr = x"06" then -- corresponds to address 80018 of the gnum BAR 0
acam_config(6) <= reg_data_wr;
end if;
if reg_adr = x"07" then -- corresponds to address 8001C of the gnum BAR 0
acam_config(7) <= reg_data_wr;
end if;
if reg_adr = x"0B" then -- corresponds to address 8002C of the gnum BAR 0
acam_config(8) <= reg_data_wr;
end if;
if reg_adr = x"0C" then -- corresponds to address 80030 of the gnum BAR 0
acam_config(9) <= reg_data_wr;
end if;
if reg_adr = x"0E" then -- corresponds to address 80038 of the gnum BAR 0
acam_config(10) <= reg_data_wr;
end if;
end if;
wait until host_clk ='1';
wait until reg_clk ='1';
end process;
-- config registers for TDC core
config_reg: process
-- config registers for TDC core
core_config_reg: process
begin
if host_reset ='1' then
starting_utc_time <= (others =>'0');
if reg_reset ='1' then
starting_utc <= (others =>'0');
clk_freq <= (others =>'0');
ref_clk_freq <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
retrig_freq <= (others =>'0');
elsif host_cyc ='1' and host_stb ='1' and host_we(0) ='1' then
if host_adr = x"20" then
starting_utc_time <= host_data_wr;
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"20" then -- corresponds to address 80080 of the gnum BAR 0
starting_utc <= reg_data_wr;
end if;
if host_adr = x"21" then
clk_freq <= host_data_wr;
if reg_adr = x"21" then -- corresponds to address 80084 of the gnum BAR 0
clk_freq <= reg_data_wr;
end if;
if host_adr = x"22" then
ref_clk_freq <= host_data_wr;
if reg_adr = x"22" then -- corresponds to address 80088 of the gnum BAR 0
ref_clk_freq <= reg_data_wr;
end if;
if host_adr = x"23" then
start_phase <= host_data_wr;
if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
start_phase <= reg_data_wr;
end if;
if host_adr = x"24" then
one_hz_phase <= host_data_wr;
if reg_adr = x"24" then -- corresponds to address 80090 of the gnum BAR 0
one_hz_phase <= reg_data_wr;
end if;
if host_adr = x"25" then
retrig_freq <= host_data_wr;
if reg_adr = x"25" then -- corresponds to address 80094 of the gnum BAR 0
retrig_freq <= reg_data_wr;
end if;
end if;
wait until host_clk ='1';
wait until reg_clk ='1';
end process;
-- control register for TDC core
control_reg: process
begin
if host_reset ='1' then
if reg_reset ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif host_cyc ='1' and host_stb ='1' and host_we(0) ='1' then
if host_adr_i = x"00020040" then -- address outside of the memory block
control_register <= host_data_wr;
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"3F" then -- corresponds to address 800FC of the gnum BAR 0
control_register <= reg_data_wr;
clear_ctrl_reg <= '1';
end if;
end if;
wait until host_clk ='1';
wait until reg_clk ='1';
end process;
memory_block: reg_mem_gen_v6_2
port map(
clka => appli_clk,
addra => appli_adr,
dina => appli_data_wr,
ena => appli_en,
wea => appli_we,
douta => appli_data_rd,
clkb => host_clk,
addrb => host_adr,
dinb => host_data_wr,
enb => host_en,
web => host_we,
doutb => host_data_rd
);
-- All control and status registers read back
with reg_adr select
reg_data_rd <= acam_config(0) when x"00",
acam_config(1) when x"01",
acam_config(2) when x"02",
acam_config(3) when x"03",
acam_config(4) when x"04",
acam_config(5) when x"05",
acam_config(6) when x"06",
acam_config(7) when x"07",
acam_config(8) when x"0B",
acam_config(9) when x"0C",
acam_config(10) when x"0E",
acam_config_rdbk(0) when x"10",
acam_config_rdbk(1) when x"11",
acam_config_rdbk(2) when x"12",
acam_config_rdbk(3) when x"13",
acam_config_rdbk(4) when x"14",
acam_config_rdbk(5) when x"15",
acam_config_rdbk(6) when x"16",
acam_config_rdbk(7) when x"17",
acam_ififo1 when x"18",
acam_ififo2 when x"19",
acam_start01 when x"1A",
acam_config_rdbk(8) when x"1B",
acam_config_rdbk(9) when x"1C",
acam_config_rdbk(10) when x"1E",
starting_utc when x"20",
clk_freq when x"21",
ref_clk_freq when x"22",
start_phase when x"23",
one_hz_phase when x"24",
retrig_freq when x"25",
current_utc when x"26",
irq_code when x"27",
x"FFFFFFFF" when others;
-- inputs from other blocks
appli_clk <= appli_clk_i;
appli_reset <= appli_reset_i;
appli_adr <= appli_adr_i(5 downto 0);
appli_cyc <= appli_cyc_i;
appli_data_wr <= appli_dat_i;
appli_en <= appli_cyc;
appli_stb <= appli_stb_i;
appli_we(0) <= appli_we_i;
reg_clk <= reg_clk_i;
reg_reset <= reg_reset_i;
reg_adr <= reg_adr_i(7 downto 0);
reg_cyc <= reg_cyc_i;
reg_data_wr <= reg_dat_i;
reg_en <= reg_cyc;
reg_stb <= reg_stb_i;
reg_we <= reg_we_i;
host_clk <= host_clk_i;
host_reset <= host_reset_i;
host_adr <= host_adr_i(5 downto 0);
host_cyc <= host_cyc_i;
host_data_wr <= host_dat_i;
host_en <= host_cyc;
host_stb <= host_stb_i;
host_we(0) <= host_we_i;
acam_config_rdbk <= acam_config_rdbk_i;
acam_status <= acam_status_i;
acam_ififo1 <= acam_ififo1_i;
acam_ififo2 <= acam_ififo2_i;
acam_start01 <= acam_start01_i;
irq_code <= irq_code_i;
-- outputs to other blocks
appli_ack_o <= appli_ack;
appli_dat_o <= appli_data_rd;
host_ack_o <= host_ack;
host_dat_o <= host_data_rd;
reg_ack_o <= reg_ack;
reg_dat_o <= reg_data_rd;
acam_config_o <= acam_config;
activate_acq_o <= control_register(0);
deactivate_acq_o <= control_register(1);
load_utc_o <= control_register(2);
load_tdc_config_o <= control_register(3);
load_acam_config_o <= control_register(4);
read_acam_config_o <= control_register(5);
reset_acam_o <= control_register(6);
read_acam_status_o <= control_register(8);
read_ififo1_o <= control_register(9);
read_ififo2_o <= control_register(10);
read_start01_o <= control_register(11);
starting_utc_time_o <= starting_utc_time;
load_acam_config_o <= control_register(2);
read_acam_config_o <= control_register(3);
read_acam_status_o <= control_register(4);
read_ififo1_o <= control_register(5);
read_ififo2_o <= control_register(6);
read_start01_o <= control_register(7);
reset_acam_o <= control_register(8);
load_utc_o <= control_register(9);
load_tdc_config_o <= control_register(10);
starting_utc_o <= starting_utc;
clk_freq_o <= clk_freq;
ref_clk_freq_o <= ref_clk_freq;
start_phase_o <= start_phase;
......@@ -281,6 +355,3 @@ end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
......@@ -78,7 +78,7 @@ constant spec_led_period_syn : std_logic_vector(data_width-1 downto 0):=x"013
constant blink_length_syn : std_logic_vector(data_width-1 downto 0):=x"00BEBC20"; -- 100 ms at 125 MHz
constant blink_length_sim : std_logic_vector(data_width-1 downto 0):=x"000004E2"; -- 10 us at 125 MHz
subtype config_register is std_logic_vector(27 downto 0);
subtype config_register is std_logic_vector(data_width-1 downto 0);
type config_vector is array (10 downto 0) of config_register;
......
......@@ -28,6 +28,7 @@ use work.gn4124_core_pkg.all;
----------------------------------------------------------------------------------------------------
entity top_tdc is
generic(
g_span : integer :=32;
g_width : integer :=32;
values_for_simulation : boolean :=FALSE
);
......@@ -206,6 +207,7 @@ architecture rtl of top_tdc is
component acam_databus_interface
generic(
g_span : integer :=32;
g_width : integer :=32
);
port(
......@@ -221,30 +223,79 @@ architecture rtl of top_tdc is
rd_n_o : out std_logic;
wr_n_o : out std_logic;
acam_ef1_o : out std_logic;
acam_ef2_o : out std_logic;
acam_lf1_o : out std_logic;
acam_lf2_o : out std_logic;
clk_i : in std_logic;
reset_i : in std_logic;
adr_i : in std_logic_vector(19 downto 0);
adr_i : in std_logic_vector(g_span-1 downto 0);
cyc_i : in std_logic;
dat_i : in std_logic_vector(31 downto 0);
dat_i : in std_logic_vector(g_width-1 downto 0);
stb_i : in std_logic;
we_i : in std_logic;
ack_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0)
dat_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
component data_engine
generic(
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone master signals internal to the chip: interface with other modules
ack_i : in std_logic;
dat_i : in std_logic_vector(g_width-1 downto 0);
adr_o : out std_logic_vector(g_span-1 downto 0);
cyc_o : out std_logic;
dat_o : out std_logic_vector(g_width-1 downto 0);
stb_o : out std_logic;
we_o : out std_logic;
-- signals internal to the chip: interface with other modules
clk_i : in std_logic;
reset_i : in std_logic;
acam_ef1_i : in std_logic;
acam_ef2_i : in std_logic;
activate_acq_i : in std_logic;
deactivate_acq_i : in std_logic;
load_acam_config_i : in std_logic;
read_acam_config_i : in std_logic;
read_acam_status_i : in std_logic;
read_ififo1_i : in std_logic;
read_ififo2_i : in std_logic;
read_start01_i : in std_logic;
reset_acam_i : in std_logic;
acam_config_i : in config_vector;
acam_config_rdbk_o : out config_vector;
acam_status_o : out std_logic_vector(g_width-1 downto 0);
acam_ififo1_o : out std_logic_vector(g_width-1 downto 0);
acam_ififo2_o : out std_logic_vector(g_width-1 downto 0);
acam_start01_o : out std_logic_vector(g_width-1 downto 0);
acam_timestamp_o : out std_logic_vector(28 downto 0);
acam_timestamp_valid_o : out std_logic
);
end component;
component circular_buffer
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface RAM with the modules providing the timestamps
class_clk_i : in std_logic;
class_reset_i : in std_logic;
class_adr_i : in std_logic_vector(g_width-1 downto 0);
class_adr_i : in std_logic_vector(g_span-1 downto 0);
class_cyc_i : in std_logic;
class_dat_i : in std_logic_vector(4*g_width-1 downto 0);
class_stb_i : in std_logic;
......@@ -257,7 +308,7 @@ architecture rtl of top_tdc is
pipe_clk_i : in std_logic;
pipe_reset_i : in std_logic;
pipe_adr_i : in std_logic_vector(g_width-1 downto 0);
pipe_adr_i : in std_logic_vector(g_span-1 downto 0);
pipe_cyc_i : in std_logic;
pipe_dat_i : in std_logic_vector(g_width-1 downto 0);
pipe_stb_i : in std_logic;
......@@ -298,55 +349,52 @@ architecture rtl of top_tdc is
component reg_ctrl
generic(
g_width : integer :=32
g_span : integer :=32;
g_width : integer :=32
);
port(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i : in std_logic;
appli_reset_i : in std_logic;
appli_adr_i : in std_logic_vector(g_width-1 downto 0);
appli_cyc_i : in std_logic;
appli_dat_i : in std_logic_vector(g_width-1 downto 0);
appli_stb_i : in std_logic;
appli_we_i : in std_logic;
appli_ack_o : out std_logic;
appli_dat_o : out std_logic_vector(g_width-1 downto 0);
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i : in std_logic;
host_reset_i : in std_logic;
host_adr_i : in std_logic_vector(g_width-1 downto 0);
host_cyc_i : in std_logic;
host_dat_i : in std_logic_vector(g_width-1 downto 0);
host_stb_i : in std_logic;
host_we_i : in std_logic;
host_ack_o : out std_logic;
host_dat_o : out std_logic_vector(g_width-1 downto 0);
reg_clk_i : in std_logic;
reg_reset_i : in std_logic;
reg_adr_i : in std_logic_vector(g_span-1 downto 0);
reg_cyc_i : in std_logic;
reg_dat_i : in std_logic_vector(g_width-1 downto 0);
reg_stb_i : in std_logic;
reg_we_i : in std_logic;
reg_ack_o : out std_logic;
reg_dat_o : out std_logic_vector(g_width-1 downto 0);
-- control signals for interface with other internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
-- control signals for interface with other application internal modules
activate_acq_o : out std_logic;
deactivate_acq_o : out std_logic;
load_utc_o : out std_logic;
load_tdc_config_o : out std_logic;
load_acam_config_o : out std_logic;
read_acam_config_o : out std_logic;
reset_acam_o : out std_logic;
read_acam_status_o : out std_logic;
read_ififo1_o : out std_logic;
read_ififo2_o : out std_logic;
read_start01_o : out std_logic;
-- configuration registers for the modules of the TDC core
starting_utc_time_o : out std_logic_vector(31 downto 0);
clk_freq_o : out std_logic_vector(31 downto 0);
ref_clk_freq_o : out std_logic_vector(31 downto 0);
start_phase_o : out std_logic_vector(31 downto 0);
one_hz_phase_o : out std_logic_vector(31 downto 0);
retrig_freq_o : out std_logic_vector(31 downto 0)
-- configuration registers from and for the ACAM and the modules of the TDC core
acam_config_rdbk_i : in config_vector;
acam_status_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
acam_start01_i : in std_logic_vector(g_width-1 downto 0);
current_utc_i : in std_logic_vector(g_width-1 downto 0);
irq_code_i : in std_logic_vector(g_width-1 downto 0);
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
clk_freq_o : out std_logic_vector(g_width-1 downto 0);
ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
);
end component;
......@@ -461,11 +509,15 @@ signal tdc_led_trig3 : std_logic:='0';
signal tdc_led_trig4 : std_logic:='0';
signal tdc_led_trig5 : std_logic:='0';
signal acam_ef1 : std_logic;
signal acam_ef2 : std_logic;
signal acam_lf1 : std_logic;
signal acam_lf2 : std_logic;
signal acam_fall_errflag_p : std_logic;
signal acam_rise_errflag_p : std_logic;
signal acam_fall_intflag_p : std_logic;
signal acam_rise_intflag_p : std_logic;
signal acam_start01 : std_logic_vector(16 downto 0);
--signal acam_start01 : std_logic_vector(16 downto 0);
signal acam_timestamp : std_logic_vector(28 downto 0);
signal acam_timestamp_valid : std_logic;
signal full_timestamp : std_logic_vector(3*g_width-1 downto 0);
......@@ -477,7 +529,7 @@ signal start_trig : std_logic;
signal start_timer_reg : std_logic_vector(7 downto 0);
signal utc_current_time : std_logic_vector(g_width-1 downto 0);
signal acm_adr : std_logic_vector(19 downto 0);
signal acm_adr : std_logic_vector(g_span-1 downto 0);
signal acm_cyc : std_logic;
signal acm_stb : std_logic;
signal acm_we : std_logic;
......@@ -507,7 +559,7 @@ signal dma_ack : std_logic;
signal dma_dat_r : std_logic_vector(31 downto 0);
signal dma_stall : std_logic;
signal mem_class_adr : std_logic_vector(g_width-1 downto 0);
signal mem_class_adr : std_logic_vector(g_span-1 downto 0);
signal mem_class_cyc : std_logic;
signal mem_class_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal mem_class_stb : std_logic;
......@@ -515,7 +567,7 @@ signal mem_class_we : std_logic;
signal mem_class_ack : std_logic;
signal mem_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
signal mem_pipe_adr : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_adr : std_logic_vector(g_span-1 downto 0);
signal mem_pipe_cyc : std_logic;
signal mem_pipe_data_wr : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stb : std_logic;
......@@ -524,21 +576,13 @@ signal mem_pipe_ack : std_logic;
signal mem_pipe_data_rd : std_logic_vector(g_width-1 downto 0);
signal mem_pipe_stall : std_logic;
signal reg_appli_adr : std_logic_vector(g_width-1 downto 0);
signal reg_appli_cyc : std_logic;
signal reg_appli_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_appli_stb : std_logic;
signal reg_appli_we : std_logic;
signal reg_appli_ack : std_logic;
signal reg_appli_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_host_adr : std_logic_vector(g_width-1 downto 0);
signal reg_host_cyc : std_logic;
signal reg_host_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_host_stb : std_logic;
signal reg_host_we : std_logic;
signal reg_host_ack : std_logic;
signal reg_host_data_rd : std_logic_vector(g_width-1 downto 0);
signal reg_adr : std_logic_vector(g_span-1 downto 0);
signal reg_cyc : std_logic;
signal reg_data_wr : std_logic_vector(g_width-1 downto 0);
signal reg_stb : std_logic;
signal reg_we : std_logic;
signal reg_ack : std_logic;
signal reg_data_rd : std_logic_vector(g_width-1 downto 0);
signal activate_acq : std_logic;
signal deactivate_acq : std_logic;
......@@ -551,12 +595,21 @@ signal read_acam_status : std_logic;
signal read_ififo1 : std_logic;
signal read_ififo2 : std_logic;
signal read_start01 : std_logic;
signal starting_utc_time : std_logic_vector(31 downto 0);
signal clk_freq : std_logic_vector(31 downto 0);
signal ref_clk_freq : std_logic_vector(31 downto 0);
signal start_phase : std_logic_vector(31 downto 0);
signal one_hz_phase : std_logic_vector(31 downto 0);
signal retrig_freq : std_logic_vector(31 downto 0);
signal starting_utc : std_logic_vector(g_width-1 downto 0);
signal clk_freq : std_logic_vector(g_width-1 downto 0);
signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
signal retrig_freq : std_logic_vector(g_width-1 downto 0);
signal acam_config_rdbk : config_vector;
signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal current_utc : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal acam_refclk : std_logic;
signal clk : std_logic;
......@@ -596,22 +649,22 @@ begin
start_trig_o => open
);
data_formatting_block: data_formatting
generic map(
g_width => g_width
)
port map(
acam_start01_i => acam_start01,
acam_timestamp_i => acam_timestamp,
acam_timestamp_valid_i => acam_timestamp_valid,
clk_i => clk,
reset_i => general_reset,
start_nb_offset_i => start_nb_offset,
utc_current_time_i => utc_current_time,
full_timestamp_o => full_timestamp,
full_timestamp_valid_o => full_timestamp_valid
);
-- data_formatting_block: data_formatting
-- generic map(
-- g_width => g_width
-- )
-- port map(
-- acam_start01_i => acam_start01,
-- acam_timestamp_i => acam_timestamp,
-- acam_timestamp_valid_i => acam_timestamp_valid,
-- clk_i => clk,
-- reset_i => general_reset,
-- start_nb_offset_i => start_nb_offset,
-- utc_current_time_i => utc_current_time,
--
-- full_timestamp_o => full_timestamp,
-- full_timestamp_valid_o => full_timestamp_valid
-- );
acam_timing_block: acam_timecontrol_interface
generic map(
......@@ -642,6 +695,7 @@ begin
acam_data_block: acam_databus_interface
generic map(
g_span => g_span,
g_width => g_width
)
port map(
......@@ -658,6 +712,11 @@ begin
rd_n_o => rd_n_o,
wr_n_o => wr_n_o,
acam_ef1_o => acam_ef1,
acam_ef2_o => acam_ef2,
acam_lf1_o => acam_lf1,
acam_lf2_o => acam_lf2,
-- signals internal to the chip: interface with other modules
clk_i => clk,
reset_i => general_reset,
......@@ -671,9 +730,52 @@ begin
ack_o => acm_ack,
dat_o => acm_dat_r
);
data_engine_block: data_engine
generic map(
g_span => g_span,
g_width => g_width
)
port map(
-- wishbone master signals internal to the chip: interface with the ACAM core
ack_i => acm_ack,
dat_i => acm_dat_r,
adr_o => acm_adr,
cyc_o => acm_cyc,
dat_o => acm_dat_w,
stb_o => acm_stb,
we_o => acm_we,
-- signals internal to the chip: interface with other modules
clk_i => clk,
reset_i => general_reset,
acam_ef1_i => acam_ef1,
acam_ef2_i => acam_ef2,
activate_acq_i => activate_acq,
deactivate_acq_i => deactivate_acq,
load_acam_config_i => load_acam_config,
read_acam_config_i => read_acam_config,
read_acam_status_i => read_acam_status,
read_ififo1_i => read_ififo1,
read_ififo2_i => read_ififo2,
read_start01_i => read_start01,
reset_acam_i => reset_acam,
acam_config_i => acam_config,
acam_config_rdbk_o => acam_config_rdbk,
acam_status_o => acam_status,
acam_ififo1_o => acam_ififo1,
acam_ififo2_o => acam_ififo2,
acam_start01_o => acam_start01,
acam_timestamp_o => open,
acam_timestamp_valid_o => open
);
circular_buffer_block: circular_buffer
generic map(
g_span => g_span,
g_width => g_width
)
port map(
......@@ -707,34 +809,22 @@ begin
reg_control_block: reg_ctrl
generic map(
g_span => g_span,
g_width => g_width
)
port map(
-- wishbone classic slave signals to interface the registers with the internal application modules
appli_clk_i => clk,
appli_reset_i => general_reset,
appli_adr_i => reg_appli_adr,
appli_cyc_i => reg_appli_cyc,
appli_dat_i => reg_appli_data_wr,
appli_stb_i => reg_appli_stb,
appli_we_i => reg_appli_we,
appli_ack_o => reg_appli_ack,
appli_dat_o => reg_appli_data_rd,
-- wishbone classic slave signals to interface with the host through the gnum core and the gnum chip
host_clk_i => clk,
host_reset_i => general_reset,
reg_clk_i => clk,
reg_reset_i => general_reset,
host_adr_i => reg_host_adr,
host_cyc_i => reg_host_cyc,
host_dat_i => reg_host_data_wr,
host_stb_i => reg_host_stb,
host_we_i => reg_host_we,
reg_adr_i => reg_adr,
reg_cyc_i => reg_cyc,
reg_dat_i => reg_data_wr,
reg_stb_i => reg_stb,
reg_we_i => reg_we,
host_ack_o => reg_host_ack,
host_dat_o => reg_host_data_rd,
reg_ack_o => reg_ack,
reg_dat_o => reg_data_rd,
-- control signals for interface with other application internal modules
activate_acq_o => activate_acq,
......@@ -743,14 +833,23 @@ begin
load_tdc_config_o => load_tdc_config,
load_acam_config_o => load_acam_config,
read_acam_config_o => read_acam_config,
reset_acam_o => reset_acam,
read_acam_status_o => read_acam_status,
read_ififo1_o => read_ififo1,
read_ififo2_o => read_ififo2,
read_start01_o => read_start01,
reset_acam_o => reset_acam,
-- configuration registers for the modules of the TDC core
starting_utc_time_o => starting_utc_time,
acam_config_rdbk_i => acam_config_rdbk,
acam_status_i => acam_status,
acam_ififo1_i => acam_ififo1,
acam_ififo2_i => acam_ififo2,
acam_start01_i => acam_start01,
current_utc_i => current_utc,
irq_code_i => irq_code,
acam_config_o => acam_config,
starting_utc_o => starting_utc,
clk_freq_o => clk_freq,
ref_clk_freq_o => ref_clk_freq,
start_phase_o => start_phase,
......@@ -935,7 +1034,7 @@ begin
-- csr_ack(0) <= mem_class_ack;
-- csr_dat_r <= mem_class_data_rd(31 downto 0);
-- (address decoding)
-- (address decoding: memory used has 512 bytes depth)
mem_pipe_cyc <= '1' when dma_cyc='1' and dma_adr(31 downto 9)=x"00000" & "000" else '0';
mem_pipe_adr <= dma_adr;
......@@ -948,27 +1047,16 @@ begin
-- CSR master connected to register memory slave
-----------------------------------------------------------
-- -- (address decoding)
-- reg_appli_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 6)="0" & x"800" else '0';
-- reg_appli_adr(31 downto 19) <= (others=>'0');
-- reg_appli_adr(18 downto 0) <= csr_adr;
--
-- reg_appli_stb <= csr_stb;
-- reg_appli_we <= csr_we;
-- reg_appli_data_wr <= csr_dat_w;
-- csr_ack(0) <= reg_appli_ack;
-- csr_dat_r <= reg_appli_data_rd;
-- (address decoding)
reg_host_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 6)="0" & x"800" else '0';
reg_host_adr(31 downto 19) <= (others=>'0');
reg_host_adr(18 downto 0) <= csr_adr;
reg_host_stb <= csr_stb;
reg_host_we <= csr_we;
reg_host_data_wr <= csr_dat_w;
csr_ack(0) <= reg_host_ack;
csr_dat_r <= reg_host_data_rd;
-- address decoding: first 512 kB for GNUM core, second 512 kB for TDC application (of which only 256 bytes are reserved)
reg_cyc <= '1' when csr_cyc(0)='1' and csr_adr(18 downto 8)="010" & x"00" else '0';
reg_adr(31 downto 19) <= (others=>'0');
reg_adr(18 downto 0) <= csr_adr;
reg_stb <= csr_stb;
reg_we <= csr_we;
reg_data_wr <= csr_dat_w;
csr_ack(0) <= reg_ack;
csr_dat_r <= reg_data_rd;
-- inputs
-- gnum_reset <= not(rst_n_a_i) or not(spec_aux1_i);
......
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