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FMC TDC 1ns 5cha - Gateware
Commit cb30b5d1 authored by penacoba's avatar penacoba
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cleaned up version of the PLL test synthesis results 


git-svn-id: http://svn.ohwr.org/fmc-tdc@35 85dfdc96-de2c-444c-878d-45b388be74a9
parent b5ae1362
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hdl/spec/syn/test_tdc_pll/_xmsgs/bitgen.xmsgs deleted 100644 → 0
View file @ b5ae1362
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(2)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(3)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(4)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(5)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(6)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(7)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(8)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(9)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(10)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(11)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(12)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(13)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(14)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(15)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_rd_d_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_rd_d_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">ef1_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">ef2_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_clk_n_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_clk_p_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">lf1_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">lf2_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_valid_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(2)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(3)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(4)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(5)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(6)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(7)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(8)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(9)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">tx_error_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_sdo_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_dframe_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">acam_refclk_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_refmon_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l2p_rdy_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">err_flag_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_status_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l_wr_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l_wr_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(10)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(11)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(12)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(20)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(13)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(21)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(22)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(14)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(23)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(15)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(24)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(16)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(25)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(17)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(26)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(18)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(27)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(19)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">int_flag_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>
hdl/spec/syn/test_tdc_pll/_xmsgs/map.xmsgs deleted 100644 → 0
View file @ b5ae1362
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Map" num="220" delta="new" >The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">acam_refclk_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">pll_sdo_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">ef1_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">lf1_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(2)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(3)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(4)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(5)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(6)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(7)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(8)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">int_flag_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(2)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(9)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(3)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(4)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(5)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(6)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(7)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(8)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(9)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_valid_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(13)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(14)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">ef2_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(15)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">l_wr_rdy_i(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">l_wr_rdy_i(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_dframe_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">pll_status_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">lf2_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(14)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(15)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(16)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(17)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(20)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(18)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(21)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(19)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(22)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(23)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(24)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(10)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(25)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(11)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(26)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_data_i(12)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(27)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">pll_refmon_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(10)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(11)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(12)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">data_bus_io(13)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p_rd_d_rdy_i(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p_rd_d_rdy_i(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_clk_p_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">err_flag_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">p2l_clk_n_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">l2p_rdy_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="LIT" num="243" delta="new" >Logical network <arg fmt="%s" index="1">tx_error_i_IBUF</arg> has no load.
</msg>
<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>
<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
</msg>
<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>
<msg type="info" file="Place" num="834" delta="new" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">135</arg> IOs, <arg fmt="%d" index="2">134</arg> are locked and <arg fmt="%d" index="3">1</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg>
</msg>
<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(2)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(3)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(4)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(5)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(6)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(7)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(8)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(9)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(10)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(11)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(12)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(13)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(14)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_data_i(15)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_rd_d_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_rd_d_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">ef1_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">ef2_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_clk_n_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_clk_p_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">lf1_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">lf2_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_valid_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(2)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(3)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(4)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(5)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(6)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(7)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(8)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(9)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">tx_error_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_sdo_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">p2l_dframe_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">acam_refclk_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_refmon_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l2p_rdy_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">err_flag_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">pll_status_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l_wr_rdy_i(0)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">l_wr_rdy_i(1)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(10)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(11)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(12)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(20)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(13)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(21)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(22)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(14)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(23)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(15)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(24)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(16)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(25)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(17)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(26)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(18)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(27)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">data_bus_io(19)_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="367" delta="new" >The signal &lt;<arg fmt="%s" index="1">int_flag_i_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>
<msg type="warning" file="PhysDesignRules" num="2410" delta="new" >This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999.
</msg>
</messages>
hdl/spec/syn/test_tdc_pll/_xmsgs/ngdbuild.xmsgs deleted 100644 → 0
View file @ b5ae1362
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
hdl/spec/syn/test_tdc_pll/_xmsgs/par.xmsgs deleted 100644 → 0
View file @ b5ae1362
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(2)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(3)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(4)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(5)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(6)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(7)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(8)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(9)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(10)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(11)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(12)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(13)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(14)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_data_i(15)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_rd_d_rdy_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_rd_d_rdy_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">ef1_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">ef2_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_clk_n_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_clk_p_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">lf1_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">lf2_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">vc_rdy_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_valid_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(2)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(3)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(4)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(5)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(6)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(7)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(8)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(9)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p_wr_req_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">tx_error_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_sdo_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">p2l_dframe_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">acam_refclk_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_refmon_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">l2p_rdy_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">err_flag_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">pll_status_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">l_wr_rdy_i(0)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">l_wr_rdy_i(1)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(10)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(11)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(12)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(20)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(13)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(21)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(22)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(14)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(23)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(15)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(24)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(16)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(25)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(17)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(26)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(18)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(27)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">data_bus_io(19)_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="288" delta="new" >The signal <arg fmt="%s" index="1">int_flag_i_IBUF</arg> has no load. PAR will not attempt to route this signal.
</msg>
<msg type="warning" file="Par" num="468" delta="new" >Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select &quot;Post-Place &amp;
Route Static Timing Report&quot;). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -&gt; Design Goals &amp; Strategies) to ensure the best options are set in the tools for timing closure.
</msg>
<msg type="warning" file="ParHelpers" num="361" delta="new" >There are <arg fmt="%d" index="1">68</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
<msg type="warning" file="Par" num="283" delta="new" >There are <arg fmt="%d" index="1">68</arg> loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
</msg>
</messages>
hdl/spec/syn/test_tdc_pll/_xmsgs/trce.xmsgs deleted 100644 → 0
View file @ b5ae1362
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="3386" delta="new" >Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</msg>
<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="2761" delta="new" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages>
hdl/spec/syn/test_tdc_pll/coreip/fifo_32x512.ngc deleted 100644 → 0
View file @ b5ae1362
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
hdl/spec/syn/test_tdc_pll/coreip/fifo_64x512.ngc deleted 100644 → 0
View file @ b5ae1362
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/netlist.lst
View file @ cb30b5d1
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.edf 1310751057
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.edf 1310975041
OK
hdl/spec/syn/test_tdc_pll/par_tdc.ncd
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/par_tdc.pad
View file @ cb30b5d1
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:01 2011
Mon Jul 18 09:44:59 2011
# NOTE: This file is designed to be imported into a spreadsheet program
......@@ -190,7 +190,7 @@ F14||IOBM|IO_L36P_GCLK15_0|UNUSED||0|||||||||
F15||IOBS|IO_L36N_GCLK14_0|UNUSED||0|||||||||
F16||IOBS|IO_L37N_GCLK12_0|UNUSED||0|||||||||
F17||IOBS|IO_L51N_0|UNUSED||0|||||||||
F18|spec_aux4_o|IOB|IO_L1P_A25_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
F18|spec_aux4_o|IOB|IO_L1P_A25_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|YES|NONE|
F19||IOBS|IO_L1N_A24_VREF_1|UNUSED||1|||||||||
F20|spec_aux3_o|IOB|IO_L29N_A22_M1A14_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
F21|p2l_data_i(14)|IOB|IO_L31P_A19_M1CKE_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
......@@ -213,7 +213,7 @@ G15||IOBS|IO_L49N_0|UNUSED||0|||||||||
G16||IOBM|IO_L51P_0|UNUSED||0|||||||||
G17|||TDO||||||||||||
G18|||GND||||||||||||
G19|spec_aux2_o|IOB|IO_L29P_A23_M1A13_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|YES|NONE|
G19|spec_aux2_o|IOB|IO_L29P_A23_M1A13_1|OUTPUT|LVCMOS18|1|12|||||LOCATED|NO|NONE|
G20|p2l_data_i(6)|IOB|IO_L35P_A11_M1A7_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
G21|||VCCO_1|||1|||||1.80||||
G22|p2l_data_i(5)|IOB|IO_L35N_A10_M1A2_1|INPUT|LVCMOS25*|1||||NONE||LOCATED|NO|NONE|
......
hdl/spec/syn/test_tdc_pll/par_tdc.par
View file @ cb30b5d1
Release 13.1 par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
lxplus427.cern.ch:: Fri Jul 15 19:31:40 2011
lxplus427.cern.ch:: Mon Jul 18 09:44:37 2011
par -ol high syn_tdc.ncd par_tdc
......@@ -27,11 +27,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 176 out of 27,288 1%
Number using O6 output only: 108
Number using O5 output only: 30
Number using O5 and O6: 38
Number of Slice LUTs: 193 out of 27,288 1%
Number used as logic: 192 out of 27,288 1%
Number using O6 output only: 121
Number using O5 output only: 31
Number using O5 and O6: 40
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
......@@ -40,11 +40,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 63 out of 6,822 1%
Number of LUT Flip Flop pairs used: 179
Number with an unused Flip Flop: 93 out of 179 51%
Number with an unused LUT: 2 out of 179 1%
Number of fully used LUT-FF pairs: 84 out of 179 46%
Number of occupied Slices: 80 out of 6,822 1%
Number of LUT Flip Flop pairs used: 195
Number with an unused Flip Flop: 109 out of 195 55%
Number with an unused LUT: 2 out of 195 1%
Number of fully used LUT-FF pairs: 84 out of 195 43%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -166,29 +166,29 @@ WARNING:Par:288 - The signal int_flag_i_IBUF has no load. PAR will not attempt
Starting Router
Phase 1 : 1007 unrouted; REAL time: 7 secs
Phase 1 : 1136 unrouted; REAL time: 7 secs
Phase 2 : 716 unrouted; REAL time: 9 secs
Phase 2 : 827 unrouted; REAL time: 9 secs
Phase 3 : 149 unrouted; REAL time: 10 secs
Phase 3 : 180 unrouted; REAL time: 10 secs
Phase 4 : 150 unrouted; (Setup:19402, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Phase 4 : 181 unrouted; (Setup:24717, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Updating file: par_tdc.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:20177, Hold:0, Component Switching Limit:0) REAL time: 13 secs
Phase 5 : 0 unrouted; (Setup:27847, Hold:0, Component Switching Limit:0) REAL time: 12 secs
Phase 6 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 17 secs
Phase 6 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 17 secs
Updating file: par_tdc.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 7 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 8 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 8 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 9 : 0 unrouted; (Setup:20151, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 9 : 0 unrouted; (Setup:27646, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 10 : 0 unrouted; (Setup:17366, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Phase 10 : 0 unrouted; (Setup:19904, Hold:0, Component Switching Limit:0) REAL time: 20 secs
Total REAL time to Router completion: 20 secs
Total CPU time to Router completion: 20 secs
......@@ -208,9 +208,9 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| spec_clk | BUFGMUX_X2Y3| No | 26 | 0.659 | 2.387 |
| spec_clk | BUFGMUX_X2Y3| No | 42 | 0.669 | 2.387 |
+---------------------+--------------+------+------+------------+-------------+
| clk | BUFGMUX_X3Y7| No | 13 | 0.667 | 2.382 |
| clk | BUFGMUX_X3Y7| No | 13 | 0.659 | 2.382 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
......@@ -218,7 +218,7 @@ only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 17366 (Setup: 17366, Hold: 0, Component Switching Limit: 0)
Timing Score: 19904 (Setup: 19904, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
......@@ -249,15 +249,15 @@ Asterisk (*) preceding a constraint indicates it was not met.
P "spec_aux0_i" TO TIMEGRP "clk" 6 | HOLD | 6.080ns| | 0| 0
ns | | | | |
----------------------------------------------------------------------------------------------------------
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.369ns| 7.369ns| 8| 11437
i" 5 ns HIGH 50% | HOLD | 0.437ns| | 0| 0
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.332ns| 7.332ns| 17| 13975
i" 5 ns HIGH 50% | HOLD | 0.429ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc_led_status_o_clk = MAXDELAY FROM T | MAXDELAY | 2.191ns| 3.809ns| 0| 0
IMEGRP "clk" TO TIMEGRP "tdc_led_ | | | | |
status_o" 6 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.272ns| 4.728ns| 0| 0
0% | HOLD | 0.497ns| | 0| 0
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.102ns| 4.898ns| 0| 0
0% | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_spec_led_green_o_spec_clk = MAXDELAY F | MAXDELAY | 44.140ns| 3.860ns| 0| 0
ROM TIMEGRP "spec_clk" TO TIMEGRP | | | | |
......@@ -277,14 +277,14 @@ All signals are completely routed.
WARNING:Par:283 - There are 68 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 22 secs
Total REAL time to PAR completion: 21 secs
Total CPU time to PAR completion: 21 secs
Peak Memory Usage: 504 MB
Peak Memory Usage: 511 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 9 errors found.
Timing: Completed - 18 errors found.
Number of error messages: 0
Number of warning messages: 71
......
hdl/spec/syn/test_tdc_pll/par_tdc.ptwx
View file @ cb30b5d1
......@@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.369" best="7.369" units="ns" errors="8" score="11437"/><twConstData type="HOLD" slack="0.437" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.272" best="4.728" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.497" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">2</twUnmetConstCnt></twSumRpt></twBody></twReport>
<twReport><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.332" best="7.332" units="ns" errors="17" score="13975"/><twConstData type="HOLD" slack="0.429" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.102" best="4.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="3">2</twUnmetConstCnt></twSumRpt></twBody></twReport>
hdl/spec/syn/test_tdc_pll/par_tdc.twr
View file @ cb30b5d1
......@@ -36,15 +36,15 @@ Asterisk (*) preceding a constraint indicates it was not met.
P "spec_aux0_i" TO TIMEGRP "clk" 6 | HOLD | 6.080ns| | 0| 0
ns | | | | |
----------------------------------------------------------------------------------------------------------
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.369ns| 7.369ns| 8| 11437
i" 5 ns HIGH 50% | HOLD | 0.437ns| | 0| 0
* TS_spec_clk_i = PERIOD TIMEGRP "spec_clk_ | SETUP | -2.332ns| 7.332ns| 17| 13975
i" 5 ns HIGH 50% | HOLD | 0.429ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_tdc_led_status_o_clk = MAXDELAY FROM T | MAXDELAY | 2.191ns| 3.809ns| 0| 0
IMEGRP "clk" TO TIMEGRP "tdc_led_ | | | | |
status_o" 6 ns | | | | |
----------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.272ns| 4.728ns| 0| 0
0% | HOLD | 0.497ns| | 0| 0
TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | SETUP | 3.102ns| 4.898ns| 0| 0
0% | HOLD | 0.463ns| | 0| 0
----------------------------------------------------------------------------------------------------------
TS_spec_led_green_o_spec_clk = MAXDELAY F | MAXDELAY | 44.140ns| 3.860ns| 0| 0
ROM TIMEGRP "spec_clk" TO TIMEGRP | | | | |
......@@ -53,14 +53,14 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_spec_clk = PERIOD TIMEGRP "spec_clk" 5 | MINPERIOD | 46.430ns| 3.570ns| 0| 0
0 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained OFFSET IN BEFORE analysis f | SETUP | N/A| 20.944ns| N/A| 0
Unconstrained OFFSET IN BEFORE analysis f | SETUP | N/A| 13.053ns| N/A| 0
or clock "spec_clk" | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained OFFSET OUT AFTER analysis f | MAXDELAY | N/A| 17.070ns| N/A| 0
Unconstrained OFFSET OUT AFTER analysis f | MAXDELAY | N/A| 19.174ns| N/A| 0
or clock "spec_clk" | | | | |
----------------------------------------------------------------------------------------------------------
Unconstrained path analysis | MAXDELAY | N/A| 17.050ns| N/A| 0
| HOLD | 1.402ns| | 0| 0
| HOLD | 2.135ns| | 0| 0
----------------------------------------------------------------------------------------------------------
......@@ -80,9 +80,9 @@ Setup/Hold to clock spec_clk_i
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
rst_n_a_i | 20.944(R)| SLOW | -0.113(R)| SLOW |spec_clk | 0.000|
rst_n_a_i | 13.053(R)| SLOW | -1.570(R)| SLOW |spec_clk | 0.000|
spec_aux0_i | 8.165(R)| SLOW | -4.426(R)| FAST |spec_clk | 0.000|
spec_aux1_i | 18.568(R)| SLOW | -2.071(R)| FAST |spec_clk | 0.000|
spec_aux1_i | 9.761(R)| SLOW | -1.373(R)| SLOW |spec_clk | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Setup/Hold to clock tdc_clk_n_i
......@@ -106,12 +106,12 @@ Clock spec_clk_i to Pad
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
pll_cs_o | 14.728(R)| SLOW | 6.361(R)| FAST |spec_clk | 0.000|
pll_cs_o | 14.889(R)| SLOW | 6.586(R)| FAST |spec_clk | 0.000|
pll_sclk_o | 8.380(R)| SLOW | 3.127(R)| FAST |spec_clk | 0.000|
pll_sdi_o | 17.070(R)| SLOW | 6.277(R)| FAST |spec_clk | 0.000|
spec_aux2_o | 8.249(R)| SLOW | 2.997(R)| FAST |spec_clk | 0.000|
spec_aux3_o | 15.826(R)| SLOW | 5.584(R)| FAST |spec_clk | 0.000|
spec_aux4_o | 14.681(R)| SLOW | 6.332(R)| FAST |spec_clk | 0.000|
pll_sdi_o | 19.174(R)| SLOW | 6.499(R)| FAST |spec_clk | 0.000|
spec_aux2_o | 18.339(R)| SLOW | 6.040(R)| FAST |spec_clk | 0.000|
spec_aux3_o | 15.031(R)| SLOW | 6.706(R)| FAST |spec_clk | 0.000|
spec_aux4_o | 8.266(R)| SLOW | 3.014(R)| FAST |spec_clk | 0.000|
spec_led_red_o | 8.412(R)| SLOW | 3.209(R)| FAST |spec_clk | 0.000|
tdc_led_trig1_o| 8.381(R)| SLOW | 3.128(R)| FAST |spec_clk | 0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+
......@@ -139,9 +139,9 @@ Clock to Setup on destination clock spec_clk_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.369| | | |
tdc_clk_n_i | 4.475| | | |
tdc_clk_p_i | 4.475| | | |
spec_clk_i | 7.332| | | |
tdc_clk_n_i | 5.950| | | |
tdc_clk_p_i | 5.950| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc_clk_n_i
......@@ -149,9 +149,9 @@ Clock to Setup on destination clock tdc_clk_n_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.224| | | |
tdc_clk_n_i | 4.728| | | |
tdc_clk_p_i | 4.728| | | |
spec_clk_i | 11.383| | | |
tdc_clk_n_i | 4.898| | | |
tdc_clk_p_i | 4.898| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock tdc_clk_p_i
......@@ -159,9 +159,9 @@ Clock to Setup on destination clock tdc_clk_p_i
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
spec_clk_i | 7.224| | | |
tdc_clk_n_i | 4.728| | | |
tdc_clk_p_i | 4.728| | | |
spec_clk_i | 11.383| | | |
tdc_clk_n_i | 4.898| | | |
tdc_clk_p_i | 4.898| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
......@@ -169,30 +169,30 @@ Pad to Pad
Source Pad |Destination Pad | Delay |
---------------+----------------+---------+
pll_ld_i |spec_led_green_o| 12.366|
rst_n_a_i |spec_aux5_o | 11.006|
rst_n_a_i |spec_aux5_o | 14.919|
spec_aux0_i |tdc_led_trig3_o | 15.691|
spec_aux0_i |tdc_led_trig4_o | 15.691|
spec_aux0_i |tdc_led_trig5_o | 17.050|
spec_aux1_i |spec_aux5_o | 8.917|
spec_aux1_i |spec_aux5_o | 8.387|
---------------+----------------+---------+
Timing summary:
---------------
Timing errors: 9 Score: 17366 (Setup/Max: 17366, Hold: 0)
Timing errors: 18 Score: 19904 (Setup/Max: 19904, Hold: 0)
Constraints cover 5229 paths, 0 nets, and 709 connections
Constraints cover 5298 paths, 0 nets, and 836 connections
Design statistics:
Minimum period: 11.929ns (Maximum frequency: 83.829MHz)
Maximum combinational path delay: 17.050ns
Maximum path delay from/to any node: 11.929ns
Minimum input required time before clock: 20.944ns
Maximum output delay after clock: 17.070ns
Minimum input required time before clock: 13.053ns
Maximum output delay after clock: 19.174ns
Analysis completed Fri Jul 15 19:32:08 2011
Analysis completed Mon Jul 18 09:45:06 2011
--------------------------------------------------------------------------------
Trace Settings:
......
hdl/spec/syn/test_tdc_pll/par_tdc.twx
View file @ cb30b5d1
......@@ -332,7 +332,7 @@
<twReport><twHead anchorID="1"><twExecVer>Release 13.1 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/bin/lin64/unwrapped/trce -u
par_tdc.ncd syn_tdc.pcf
</twCmdLine><twDesign>par_tdc.ncd</twDesign><twDesignPath>par_tdc.ncd</twDesignPath><twPCF>syn_tdc.pcf</twPCF><twPcfPath>syn_tdc.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx45t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.17 2011-02-03</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twSum" dlyHyperLnks="t" ><twItemLimit>0</twItemLimit><twUnconst></twUnconst></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.369" best="7.369" units="ns" errors="8" score="11437"/><twConstData type="HOLD" slack="0.437" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.272" best="4.728" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.497" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained OFFSET IN BEFORE analysis for clock &quot;spec_clk&quot;</twConstName><twConstData type="SETUP" best="20.944" units="ns" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained OFFSET OUT AFTER analysis for clock &quot;spec_clk&quot;</twConstName><twConstData type="MAXDELAY" best="17.070" units="ns" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained path analysis</twConstName><twConstData type="MAXDELAY" best="17.050" units="ns" score="0"/><twConstData type="HOLD" slack="1.402" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="4">2</twUnmetConstCnt><twInfo anchorID="5">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo><twDataSheet anchorID="6" twNameLen="16"><twSUH2ClkList anchorID="7" twDestWidth="11" twPhaseWidth="8"><twDest>spec_clk_i</twDest><twSUH2Clk ><twSrc>rst_n_a_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">20.944</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="f">-0.113</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">8.165</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.426</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>spec_aux1_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">18.568</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-2.071</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twSUH2ClkList anchorID="8" twDestWidth="11" twPhaseWidth="3"><twDest>tdc_clk_n_i</twDest><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">7.924</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.267</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twSUH2ClkList anchorID="9" twDestWidth="11" twPhaseWidth="3"><twDest>tdc_clk_p_i</twDest><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">7.925</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.267</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="10" twDestWidth="15" twPhaseWidth="8"><twSrc>spec_clk_i</twSrc><twClk2Out twOutPad = "pll_cs_o" twMinTime = "6.361" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "14.728" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "pll_sclk_o" twMinTime = "3.127" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.380" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "pll_sdi_o" twMinTime = "6.277" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "17.070" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux2_o" twMinTime = "2.997" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.249" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux3_o" twMinTime = "5.584" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "15.826" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux4_o" twMinTime = "6.332" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "14.681" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_led_red_o" twMinTime = "3.209" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.412" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig1_o" twMinTime = "3.128" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.381" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2OutList anchorID="11" twDestWidth="16" twPhaseWidth="3"><twSrc>tdc_clk_n_i</twSrc><twClk2Out twOutPad = "tdc_led_status_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.564" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig2_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.564" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2OutList anchorID="12" twDestWidth="16" twPhaseWidth="3"><twSrc>tdc_clk_p_i</twSrc><twClk2Out twOutPad = "tdc_led_status_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.563" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig2_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.563" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="13" twDestWidth="11"><twDest>spec_clk_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>7.369</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>4.475</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>4.475</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="14" twDestWidth="11"><twDest>tdc_clk_n_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>7.224</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>4.728</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>4.728</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="15" twDestWidth="11"><twDest>tdc_clk_p_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>7.224</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>4.728</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>4.728</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="16" twSrcWidth="11" twDestWidth="16"><twPad2Pad><twSrc>pll_ld_i</twSrc><twDest>spec_led_green_o</twDest><twDel>12.366</twDel></twPad2Pad><twPad2Pad><twSrc>rst_n_a_i</twSrc><twDest>spec_aux5_o</twDest><twDel>11.006</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig3_o</twDest><twDel>15.691</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig4_o</twDest><twDel>15.691</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig5_o</twDest><twDel>17.050</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux1_i</twSrc><twDest>spec_aux5_o</twDest><twDel>8.917</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twSumRpt></twBody><twSum anchorID="17"><twErrCnt>9</twErrCnt><twScore>17366</twScore><twSetupScore>17366</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>5229</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>709</twConnCnt></twConstCov><twStats anchorID="18"><twMinPer>11.929</twMinPer><twMaxFreq>83.829</twMaxFreq><twMaxCombDel>17.050</twMaxCombDel><twMaxFromToDel>11.929</twMaxFromToDel><twMinInBeforeClk>20.944</twMinInBeforeClk><twMaxOutBeforeClk>17.070</twMaxOutBeforeClk></twStats></twSum><twFoot><twTimestamp>Fri Jul 15 19:32:08 2011 </twTimestamp></twFoot><twClientInfo anchorID="19"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
</twCmdLine><twDesign>par_tdc.ncd</twDesign><twDesignPath>par_tdc.ncd</twDesignPath><twPCF>syn_tdc.pcf</twPCF><twPcfPath>syn_tdc.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="fgg484"><twDevName>xc6slx45t</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.17 2011-02-03</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twSum" dlyHyperLnks="t" ><twItemLimit>0</twItemLimit><twUnconst></twUnconst></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.</twInfo><twInfo anchorID="3">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twSumRpt><twConstSummaryTable twEmptyConstraints = "1" ><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_aux0_i_clk = MAXDELAY FROM TIMEGRP &quot;spec_aux0_i&quot; TO TIMEGRP &quot;clk&quot; 6 ns</twConstName><twConstData type="SETUP" slack="-5.929" best="11.929" units="ns" errors="1" score="5929"/><twConstData type="HOLD" slack="6.080" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk_i = PERIOD TIMEGRP &quot;spec_clk_i&quot; 5 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="-2.332" best="7.332" units="ns" errors="17" score="13975"/><twConstData type="HOLD" slack="0.429" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_tdc_led_status_o_clk = MAXDELAY FROM TIMEGRP &quot;clk&quot; TO TIMEGRP &quot;tdc_led_status_o&quot; 6 ns</twConstName><twConstData type="MAXDELAY" slack="2.191" best="3.809" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_clk = PERIOD TIMEGRP &quot;clk&quot; 8 ns HIGH 50%</twConstName><twConstData type="SETUP" slack="3.102" best="4.898" units="ns" errors="0" score="0"/><twConstData type="HOLD" slack="0.463" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_led_green_o_spec_clk = MAXDELAY FROM TIMEGRP &quot;spec_clk&quot; TO TIMEGRP &quot;spec_led_green_o&quot; 48 ns</twConstName><twConstData type="MAXDELAY" slack="44.140" best="3.860" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">TS_spec_clk = PERIOD TIMEGRP &quot;spec_clk&quot; 50 ns HIGH 50%</twConstName><twConstData type="MINPERIOD" slack="46.430" best="3.570" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained OFFSET IN BEFORE analysis for clock &quot;spec_clk&quot;</twConstName><twConstData type="SETUP" best="13.053" units="ns" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained OFFSET OUT AFTER analysis for clock &quot;spec_clk&quot;</twConstName><twConstData type="MAXDELAY" best="19.174" units="ns" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Unconstrained path analysis</twConstName><twConstData type="MAXDELAY" best="17.050" units="ns" score="0"/><twConstData type="HOLD" slack="2.135" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="4">2</twUnmetConstCnt><twInfo anchorID="5">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo><twDataSheet anchorID="6" twNameLen="16"><twSUH2ClkList anchorID="7" twDestWidth="11" twPhaseWidth="8"><twDest>spec_clk_i</twDest><twSUH2Clk ><twSrc>rst_n_a_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">13.053</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="f">-1.570</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">8.165</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.426</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>spec_aux1_i</twSrc><twSUHTime twInternalClk ="spec_clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">9.761</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="f">-1.373</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twSUH2ClkList anchorID="8" twDestWidth="11" twPhaseWidth="3"><twDest>tdc_clk_n_i</twDest><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">7.924</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.267</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twSUH2ClkList anchorID="9" twDestWidth="11" twPhaseWidth="3"><twDest>tdc_clk_p_i</twDest><twSUH2Clk ><twSrc>spec_aux0_i</twSrc><twSUHTime twInternalClk ="clk" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">7.925</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-4.267</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="10" twDestWidth="15" twPhaseWidth="8"><twSrc>spec_clk_i</twSrc><twClk2Out twOutPad = "pll_cs_o" twMinTime = "6.586" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "14.889" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "pll_sclk_o" twMinTime = "3.127" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.380" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "pll_sdi_o" twMinTime = "6.499" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "19.174" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux2_o" twMinTime = "6.040" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "18.339" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux3_o" twMinTime = "6.706" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "15.031" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_aux4_o" twMinTime = "3.014" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.266" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "spec_led_red_o" twMinTime = "3.209" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.412" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig1_o" twMinTime = "3.128" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.381" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="spec_clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2OutList anchorID="11" twDestWidth="16" twPhaseWidth="3"><twSrc>tdc_clk_n_i</twSrc><twClk2Out twOutPad = "tdc_led_status_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.564" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig2_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.564" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2OutList anchorID="12" twDestWidth="16" twPhaseWidth="3"><twSrc>tdc_clk_p_i</twSrc><twClk2Out twOutPad = "tdc_led_status_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.563" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "tdc_led_trig2_o" twMinTime = "3.324" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "8.563" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="13" twDestWidth="11"><twDest>spec_clk_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>7.332</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>5.950</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>5.950</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="14" twDestWidth="11"><twDest>tdc_clk_n_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>11.383</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>4.898</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>4.898</twRiseRise></twClk2SU></twClk2SUList><twClk2SUList anchorID="15" twDestWidth="11"><twDest>tdc_clk_p_i</twDest><twClk2SU><twSrc>spec_clk_i</twSrc><twRiseRise>11.383</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_n_i</twSrc><twRiseRise>4.898</twRiseRise></twClk2SU><twClk2SU><twSrc>tdc_clk_p_i</twSrc><twRiseRise>4.898</twRiseRise></twClk2SU></twClk2SUList><twPad2PadList anchorID="16" twSrcWidth="11" twDestWidth="16"><twPad2Pad><twSrc>pll_ld_i</twSrc><twDest>spec_led_green_o</twDest><twDel>12.366</twDel></twPad2Pad><twPad2Pad><twSrc>rst_n_a_i</twSrc><twDest>spec_aux5_o</twDest><twDel>14.919</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig3_o</twDest><twDel>15.691</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig4_o</twDest><twDel>15.691</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux0_i</twSrc><twDest>tdc_led_trig5_o</twDest><twDel>17.050</twDel></twPad2Pad><twPad2Pad><twSrc>spec_aux1_i</twSrc><twDest>spec_aux5_o</twDest><twDel>8.387</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twSumRpt></twBody><twSum anchorID="17"><twErrCnt>18</twErrCnt><twScore>19904</twScore><twSetupScore>19904</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>5298</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>836</twConnCnt></twConstCov><twStats anchorID="18"><twMinPer>11.929</twMinPer><twMaxFreq>83.829</twMaxFreq><twMaxCombDel>17.050</twMaxCombDel><twMaxFromToDel>11.929</twMaxFromToDel><twMinInBeforeClk>13.053</twMinInBeforeClk><twMaxOutBeforeClk>19.174</twMaxOutBeforeClk></twStats></twSum><twFoot><twTimestamp>Mon Jul 18 09:45:06 2011 </twTimestamp></twFoot><twClientInfo anchorID="19"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 348 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
hdl/spec/syn/test_tdc_pll/par_tdc.unroutes
View file @ cb30b5d1
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:02 2011
Mon Jul 18 09:44:59 2011
All signals are completely routed.
......
hdl/spec/syn/test_tdc_pll/par_tdc_pad.csv
View file @ cb30b5d1
#Release 13.1 - par O.40d (lin64)
#Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
#Fri Jul 15 19:32:01 2011
#Mon Jul 18 09:44:59 2011
#
## NOTE: This file is designed to be imported into a spreadsheet program
......@@ -190,7 +190,7 @@ F14,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,,
F15,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,,
F16,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,,
F17,,IOBS,IO_L51N_0,UNUSED,,0,,,,,,,,,
F18,spec_aux4_o,IOB,IO_L1P_A25_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
F18,spec_aux4_o,IOB,IO_L1P_A25_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,YES,NONE,
F19,,IOBS,IO_L1N_A24_VREF_1,UNUSED,,1,,,,,,,,,
F20,spec_aux3_o,IOB,IO_L29N_A22_M1A14_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
F21,p2l_data_i(14),IOB,IO_L31P_A19_M1CKE_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
......@@ -213,7 +213,7 @@ G15,,IOBS,IO_L49N_0,UNUSED,,0,,,,,,,,,
G16,,IOBM,IO_L51P_0,UNUSED,,0,,,,,,,,,
G17,,,TDO,,,,,,,,,,,,
G18,,,GND,,,,,,,,,,,,
G19,spec_aux2_o,IOB,IO_L29P_A23_M1A13_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,YES,NONE,
G19,spec_aux2_o,IOB,IO_L29P_A23_M1A13_1,OUTPUT,LVCMOS18,1,12,,,,,LOCATED,NO,NONE,
G20,p2l_data_i(6),IOB,IO_L35P_A11_M1A7_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
G21,,,VCCO_1,,,1,,,,,1.80,,,,
G22,p2l_data_i(5),IOB,IO_L35N_A10_M1A2_1,INPUT,LVCMOS25*,1,,,,NONE,,LOCATED,NO,NONE,
......
hdl/spec/syn/test_tdc_pll/par_tdc_pad.txt
View file @ cb30b5d1
Release 13.1 - par O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:02 2011
Mon Jul 18 09:44:59 2011
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
......@@ -191,7 +191,7 @@ Pinout by Pin Number:
|F15 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | |
|F16 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | |
|F17 | |IOBS |IO_L51N_0 |UNUSED | |0 | | | | | | | | |
|F18 |spec_aux4_o |IOB |IO_L1P_A25_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|F18 |spec_aux4_o |IOB |IO_L1P_A25_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |YES |NONE |
|F19 | |IOBS |IO_L1N_A24_VREF_1 |UNUSED | |1 | | | | | | | | |
|F20 |spec_aux3_o |IOB |IO_L29N_A22_M1A14_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|F21 |p2l_data_i(14) |IOB |IO_L31P_A19_M1CKE_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
......@@ -214,7 +214,7 @@ Pinout by Pin Number:
|G16 | |IOBM |IO_L51P_0 |UNUSED | |0 | | | | | | | | |
|G17 | | |TDO | | | | | | | | | | | |
|G18 | | |GND | | | | | | | | | | | |
|G19 |spec_aux2_o |IOB |IO_L29P_A23_M1A13_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |YES |NONE |
|G19 |spec_aux2_o |IOB |IO_L29P_A23_M1A13_1 |OUTPUT |LVCMOS18 |1 |12 | | | | |LOCATED |NO |NONE |
|G20 |p2l_data_i(6) |IOB |IO_L35P_A11_M1A7_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
|G21 | | |VCCO_1 | | |1 | | | | |1.80 | | | |
|G22 |p2l_data_i(5) |IOB |IO_L35N_A10_M1A2_1 |INPUT |LVCMOS25* |1 | | | |NONE | |LOCATED |NO |NONE |
......
hdl/spec/syn/test_tdc_pll/par_usage_statistics.html
View file @ cb30b5d1
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>269</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>709</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>601</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>287</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>836</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>836</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>711</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>9.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>10.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>10.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>11.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>12.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>20.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>20.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>12.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>17.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>20.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>20.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>12.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>7.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>5.4</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>8.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>8.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0271</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0277</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
hdl/spec/syn/test_tdc_pll/rpt_top_tdc.areasrr
View file @ cb30b5d1
......@@ -14,7 +14,7 @@ Name Total elements Utilization Notes
REGISTERS 92 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.70 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.04 % Utilization)
COMBINATIONAL LOGIC
......@@ -22,13 +22,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 178 100 %
LUTS 196 100 %
MUXCY 70 100 %
XORCY 71 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 320 (65.04 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 338 (66.27 % Utilization)
MEMORY ELEMENTS
......@@ -69,7 +69,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 66 100 %
=================================================
Total IO PADS in the block top_tdc: 66 (13.41 % Utilization)
Total IO PADS in the block top_tdc: 66 (12.94 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_pll/rpt_top_tdc_areasrr.htm
View file @ cb30b5d1
......@@ -16,7 +16,7 @@ Name Total elements Utilization Notes
REGISTERS 92 100 %
LATCHES 0 0 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.70 % Utilization)
Total SEQUENTIAL ELEMENTS in the block top_tdc: 92 (18.04 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -25,13 +25,13 @@ COMBINATIONAL LOGIC
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 178 100 %
LUTS 196 100 %
MUXCY 70 100 %
XORCY 71 100 %
MULT18x18/MULT18x18S 1 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 320 (65.04 % Utilization)
Total COMBINATIONAL LOGIC in the block top_tdc: 338 (66.27 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
......@@ -76,7 +76,7 @@ Name Total elements Utilization Notes
-------------------------------------------------
PADS 66 100 %
=================================================
Total IO PADS in the block top_tdc: 66 (13.41 % Utilization)
Total IO PADS in the block top_tdc: 66 (12.94 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
......
hdl/spec/syn/test_tdc_pll/run_options.txt
View file @ cb30b5d1
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/run_options.txt
#-- Written on Fri Jul 15 19:30:52 2011
#-- Written on Mon Jul 18 09:43:56 2011
#project files
......
hdl/spec/syn/test_tdc_pll/scratchproject.prs
View file @ cb30b5d1
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/scratchproject.prs
#-- Written on Fri Jul 15 19:30:52 2011
#-- Written on Mon Jul 18 09:43:56 2011
#project files
......
hdl/spec/syn/test_tdc_pll/syn_tdc.bld
View file @ cb30b5d1
......@@ -37,10 +37,10 @@ NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 311956 kilobytes
Total memory usage is 312080 kilobytes
Writing NGD file "syn_tdc.ngd" ...
Total REAL time to NGDBUILD completion: 9 sec
Total REAL time to NGDBUILD completion: 10 sec
Total CPU time to NGDBUILD completion: 3 sec
Writing NGDBUILD log file "syn_tdc.bld"...
hdl/spec/syn/test_tdc_pll/syn_tdc.edf
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.map
View file @ cb30b5d1
......@@ -8,7 +8,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jul 15 19:31:22 2011
Mapped Date : Mon Jul 18 09:44:18 2011
Mapping design into LUTs...
Writing file syn_tdc.ngm...
......@@ -19,59 +19,59 @@ INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 8 secs
Total CPU time at the beginning of Placer: 7 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:8e69df18) REAL time: 9 secs
Phase 1.1 Initial Placement Analysis (Checksum:8e53cbb8) REAL time: 9 secs
Phase 2.7 Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 135 IOs, 134 are locked
and 1 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
Phase 2.7 Design Feasibility Check (Checksum:8e69df18) REAL time: 9 secs
Phase 2.7 Design Feasibility Check (Checksum:8e53cbb8) REAL time: 9 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:8e69df18) REAL time: 9 secs
Phase 3.31 Local Placement Optimization (Checksum:8e53cbb8) REAL time: 9 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:4ab12e71) REAL time: 14 secs
(Checksum:5135e245) REAL time: 14 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:4ab12e71) REAL time: 14 secs
Phase 5.36 Local Placement Optimization (Checksum:5135e245) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:4ab12e71) REAL time: 14 secs
Phase 6.30 Global Clock Region Assignment (Checksum:5135e245) REAL time: 14 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:7f94c7c9) REAL time: 14 secs
Phase 7.3 Local Placement Optimization (Checksum:31c1d851) REAL time: 14 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:7f94c7c9) REAL time: 14 secs
Phase 8.5 Local Placement Optimization (Checksum:31c1d851) REAL time: 14 secs
Phase 9.8 Global Placement
..............
......................
................
........
Phase 9.8 Global Placement (Checksum:e99791f2) REAL time: 15 secs
............
.................................................................
.......................
...
Phase 9.8 Global Placement (Checksum:78e18431) REAL time: 15 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:e99791f2) REAL time: 15 secs
Phase 10.5 Local Placement Optimization (Checksum:78e18431) REAL time: 15 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:708689a4) REAL time: 16 secs
Phase 11.18 Placement Optimization (Checksum:fe7345b3) REAL time: 17 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:708689a4) REAL time: 16 secs
Phase 12.5 Local Placement Optimization (Checksum:fe7345b3) REAL time: 17 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:6ccb73df) REAL time: 16 secs
Phase 13.34 Placement Validation (Checksum:f80c1b30) REAL time: 17 secs
Total REAL time to Placer completion: 16 secs
Total CPU time to Placer completion: 15 secs
Total REAL time to Placer completion: 17 secs
Total CPU time to Placer completion: 17 secs
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:367 - The signal <p2l_data_i(0)_IBUF> is incomplete. The
......@@ -227,11 +227,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 176 out of 27,288 1%
Number using O6 output only: 108
Number using O5 output only: 30
Number using O5 and O6: 38
Number of Slice LUTs: 193 out of 27,288 1%
Number used as logic: 192 out of 27,288 1%
Number using O6 output only: 121
Number using O5 output only: 31
Number using O5 and O6: 40
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
......@@ -240,11 +240,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 63 out of 6,822 1%
Number of LUT Flip Flop pairs used: 179
Number with an unused Flip Flop: 93 out of 179 51%
Number with an unused LUT: 2 out of 179 1%
Number of fully used LUT-FF pairs: 84 out of 179 46%
Number of occupied Slices: 80 out of 6,822 1%
Number of LUT Flip Flop pairs used: 195
Number with an unused Flip Flop: 109 out of 195 55%
Number with an unused LUT: 2 out of 195 1%
Number of fully used LUT-FF pairs: 84 out of 195 43%
Number of unique control sets: 6
Number of slice register sites lost
to control set restrictions: 18 out of 54,576 1%
......@@ -289,11 +289,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.20
Average Fanout of Non-Clock Nets: 2.34
Peak Memory Usage: 606 MB
Total REAL time to MAP completion: 17 secs
Total CPU time to MAP completion: 16 secs
Peak Memory Usage: 607 MB
Total REAL time to MAP completion: 18 secs
Total CPU time to MAP completion: 17 secs
Mapping completed.
See MAP report file "syn_tdc.mrp" for details.
hdl/spec/syn/test_tdc_pll/syn_tdc.mrp
View file @ cb30b5d1
......@@ -8,7 +8,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Jul 15 19:31:22 2011
Mapped Date : Mon Jul 18 09:44:18 2011
Design Summary
--------------
......@@ -20,11 +20,11 @@ Slice Logic Utilization:
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 177 out of 27,288 1%
Number used as logic: 176 out of 27,288 1%
Number using O6 output only: 108
Number using O5 output only: 30
Number using O5 and O6: 38
Number of Slice LUTs: 193 out of 27,288 1%
Number used as logic: 192 out of 27,288 1%
Number using O6 output only: 121
Number using O5 output only: 31
Number using O5 and O6: 40
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 1
......@@ -33,11 +33,11 @@ Slice Logic Utilization:
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 63 out of 6,822 1%
Number of LUT Flip Flop pairs used: 179
Number with an unused Flip Flop: 93 out of 179 51%
Number with an unused LUT: 2 out of 179 1%
Number of fully used LUT-FF pairs: 84 out of 179 46%
Number of occupied Slices: 80 out of 6,822 1%
Number of LUT Flip Flop pairs used: 195
Number with an unused Flip Flop: 109 out of 195 55%
Number with an unused LUT: 2 out of 195 1%
Number of fully used LUT-FF pairs: 84 out of 195 43%
Number of unique control sets: 6
Number of slice register sites lost
to control set restrictions: 18 out of 54,576 1%
......@@ -82,11 +82,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 2.20
Average Fanout of Non-Clock Nets: 2.34
Peak Memory Usage: 606 MB
Total REAL time to MAP completion: 17 secs
Total CPU time to MAP completion: 16 secs
Peak Memory Usage: 607 MB
Total REAL time to MAP completion: 18 secs
Total CPU time to MAP completion: 17 secs
Table of Contents
-----------------
......@@ -340,7 +340,7 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
2 block(s) optimized away
180 Block(s) redundant
179 Block(s) redundant
Section 5 - Removed Logic
-------------------------
......@@ -423,6 +423,7 @@ LOCALBUF tdc_led_counter.value_cry[28]/MUXCY_L_BUF
LOCALBUF tdc_led_counter.value_cry[29]/MUXCY_L_BUF
LOCALBUF tdc_led_counter.value_cry[30]/MUXCY_L_BUF
LOCALBUF tdc_led_counter.value_RNI7QVF[13]/LUT2_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_RNITDB5[10]/LUT2_L_BUF
LOCALBUF tdc_led_counter.value_RNIUJ66[1]/LUT1_L_BUF
LOCALBUF tdc_led_counter.value_RNIVN66[2]/LUT1_L_BUF
LOCALBUF tdc_led_counter.value_RNI0S66[3]/LUT1_L_BUF
......@@ -454,53 +455,51 @@ LOCALBUF tdc_led_counter.value_RNIB1[28]/LUT1_L_BUF
LOCALBUF tdc_led_counter.value_RNIC1[29]/LUT1_L_BUF
LOCALBUF tdc_led_counter.value_RNI65[30]/LUT1_L_BUF
LOCALBUF tdc_led_counter.value_s_RNO[31]/LUT1_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[31]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[30]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[29]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[28]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[27]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[26]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[25]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[24]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[23]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[22]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[21]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[20]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[19]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[18]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[17]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[16]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[15]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[14]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[13]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[12]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[11]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[10]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[9]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[8]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[7]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[6]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[5]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[4]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[3]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[2]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[1]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[31]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[30]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[29]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[28]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[27]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[26]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[25]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[24]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[23]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[22]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[21]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[20]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[19]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[18]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[17]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[16]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[15]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[14]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[13]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[12]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[11]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[10]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[9]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[8]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[7]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[6]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[5]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[4]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[3]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[2]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[1]/LUT6_L_BUF
LOCALBUF tdc_led_status_e/LUT2_L_BUF
LOCALBUF spec_led_red_e/LUT2_L_BUF
LOCALBUF tdc_led_counter.count_done_RNO/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_srsts_i[3]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.count_done_RNO/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_srsts_i_o2[3]/LUT6_L_BUF
LOCALBUF tdc_led_counter.value_RNI2PVN[27]/LUT4_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_RNIUV8Q[20]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_RNI9VG9[7]/LUT2_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_srsts_i[2]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_RNO[1]/LUT6_L_BUF
LOCALBUF spec_led_red_counter.count_done_RNO/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[0]/LUT4_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_RNO[2]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_RNO[3]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.bit_index_RNO[3]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.bit_index_RNO[2]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.bit_index_RNO[0]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.bit_index_RNO[1]/LUT5_L_BUF
LOCALBUF clks_rsts_mgment.bit_index_RNO[0]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.count_done_RNO/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.pll_init_st_RNO_0[3]/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_RNI70OA[20]/LUT4_L_BUF
LOCALBUF spec_led_red_counter.count_done_RNO/LUT6_L_BUF
LOCALBUF clks_rsts_mgment.general_poreset.value_lm_0[0]/LUT6_L_BUF
LUT1 clks_rsts_mgment.general_poreset.value_s_RNO[31]
LUT1 clks_rsts_mgment.general_poreset.value_RNI0LL2[30]
LUT1 clks_rsts_mgment.general_poreset.value_RNI8PM2[29]
......@@ -648,9 +647,9 @@ Section 6 - IOB Properties
| spare_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| spec_aux0_i | IOB | INPUT | LVCMOS18 | | | | | | |
| spec_aux1_i | IOB | INPUT | LVCMOS18 | | | | | | |
| spec_aux2_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | OFF | | |
| spec_aux2_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| spec_aux3_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| spec_aux4_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| spec_aux4_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | OFF | | |
| spec_aux5_o | IOB | OUTPUT | LVCMOS18 | | 12 | SLOW | | | |
| spec_clk_i | IOB | INPUT | LVCMOS25 | | | | | | |
| spec_led_green_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
......@@ -721,13 +720,13 @@ Section 12 - Control Set Information
+--------------------------------------------------------------------------------------------------------------+
| Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count |
+--------------------------------------------------------------------------------------------------------------+
| clk | N_51_i | | | 8 | 32 |
| clk | N_39_i | | | 8 | 32 |
| clk | clks_rsts_mgment.inv_reset_i | | | 2 | 2 |
| clk | pll_sclk_i | | | 1 | 1 |
| clk | pll_sclk_o_c_i | | | 1 | 1 |
+--------------------------------------------------------------------------------------------------------------+
| spec_clk | | | | 5 | 11 |
| spec_clk | N_132_i_iso | | | 6 | 8 |
| spec_clk | N_132_i_iso | | N_10_i | 9 | 32 |
| spec_clk | | | | 9 | 11 |
| spec_clk | N_188_i_iso | | | 7 | 8 |
| spec_clk | N_188_i_iso | | N_18_i | 20 | 32 |
+--------------------------------------------------------------------------------------------------------------+
Section 13 - Utilization by Hierarchy
......@@ -735,7 +734,7 @@ Section 13 - Utilization by Hierarchy
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| top_tdc/ | | 63/63 | 86/86 | 146/146 | 0/0 | 1/1 | 1/1 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | top_tdc |
| top_tdc/ | | 80/80 | 86/86 | 162/162 | 0/0 | 1/1 | 1/1 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | top_tdc |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
......
hdl/spec/syn/test_tdc_pll/syn_tdc.ncd
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.ngd
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.ngm
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.ngo
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.pcf
View file @ cb30b5d1
//! **************************************************************************
// Written by: Map O.40d on Fri Jul 15 19:31:38 2011
// Written by: Map O.40d on Mon Jul 18 09:44:36 2011
//! **************************************************************************
SCHEMATIC START;
......@@ -153,6 +153,7 @@ TIMEGRP spec_clk_i = BEL "clks_rsts_mgment.spec_clk_gbuf" BEL
BEL "clks_rsts_mgment.bit_index[2]" BEL
"clks_rsts_mgment.bit_index[3]" BEL "clks_rsts_mgment.pll_sclk" PIN
"spec_led_red_counter.value[31:0]_pins<92>" BEL
"clks_rsts_mgment.general_poreset.count_done_rep0_i" BEL
"clks_rsts_mgment.general_poreset.value[0]" BEL
"clks_rsts_mgment.general_poreset.value[1]" BEL
"clks_rsts_mgment.general_poreset.value[2]" BEL
......@@ -185,8 +186,7 @@ TIMEGRP spec_clk_i = BEL "clks_rsts_mgment.spec_clk_gbuf" BEL
"clks_rsts_mgment.general_poreset.value[29]" BEL
"clks_rsts_mgment.general_poreset.value[30]" BEL
"clks_rsts_mgment.general_poreset.value[31]" BEL "spec_led_red_oreg"
BEL "clks_rsts_mgment.pll_sclk_oreg" BEL
"clks_rsts_mgment.pll_sclk_oreg_0" PIN
BEL "clks_rsts_mgment.pll_sclk_oreg" PIN
"clks_rsts_mgment.un7_word_being_sent_0_0_pins<26>" BEL
"tdc_led_trig1_o" BEL "spec_led_red" BEL
"spec_led_red_counter.count_done" BEL
......@@ -203,6 +203,7 @@ TIMEGRP spec_clk = BEL "clks_rsts_mgment.general_poreset.count_done" BEL
BEL "clks_rsts_mgment.bit_index[2]" BEL
"clks_rsts_mgment.bit_index[3]" BEL "clks_rsts_mgment.pll_sclk" PIN
"spec_led_red_counter.value[31:0]_pins<92>" BEL
"clks_rsts_mgment.general_poreset.count_done_rep0_i" BEL
"clks_rsts_mgment.general_poreset.value[0]" BEL
"clks_rsts_mgment.general_poreset.value[1]" BEL
"clks_rsts_mgment.general_poreset.value[2]" BEL
......@@ -235,8 +236,7 @@ TIMEGRP spec_clk = BEL "clks_rsts_mgment.general_poreset.count_done" BEL
"clks_rsts_mgment.general_poreset.value[29]" BEL
"clks_rsts_mgment.general_poreset.value[30]" BEL
"clks_rsts_mgment.general_poreset.value[31]" BEL "spec_led_red_oreg"
BEL "clks_rsts_mgment.pll_sclk_oreg" BEL
"clks_rsts_mgment.pll_sclk_oreg_0" PIN
BEL "clks_rsts_mgment.pll_sclk_oreg" PIN
"clks_rsts_mgment.un7_word_being_sent_0_0_pins<26>" BEL
"tdc_led_trig1_o" BEL "spec_led_red" BEL
"spec_led_red_counter.count_done" BEL
......
hdl/spec/syn/test_tdc_pll/syn_tdc.sap
View file @ cb30b5d1
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......
hdl/spec/syn/test_tdc_pll/syn_tdc.srl
View file @ cb30b5d1
......@@ -6,7 +6,7 @@
#
# Created by Synplify VHDL Compiler version comp500rc, Build 027R from Synplicity, Inc.
# Copyright 1994-2010 Synopsys, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jul 15 19:30:53 2011
# Synthesis Netlist written on Mon Jul 18 09:43:57 2011
#
#
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
......@@ -45,11 +45,11 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1310750802
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1310974921
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd":1306400619
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd":1307641333
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1307642203
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_pll/top_test_pll.vhd":1310736179
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_pll/top_test_pll.vhd":1310973394
f "/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd"; # file 0
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"; # file 1
......@@ -355,269 +355,268 @@ mb=#COO_DF _
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--------4-Rj-jjj4jjRj4Rjj
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jR---------j--jjRj4Rjjjjj4j-R
-----j-jj4jjRjjj4jjRjj4jR-
-----4----Rj4jj4jjjRjjR4j
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j44jjjjRjjjj4444jj;
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jj44jj4Rj44jj4jj4j;
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jj444j4Rj44jjjj44j;
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j4444jjRj44jjj4jjj;
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4jjjjjjRj44jj44jjj;
4jjjjj4Rj44jj44j4j;
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4jjj4j4Rj4444jjj4j;
44jjjjjRj44444jjjj;
44jjjj4Rj44444jj4j;
44jj4jjRj4444jj4jj;
44jj4j4Rj4444jj44j;
4jj4jjjR4jj4jjjjjj;
4jj4jj4R4jj4jjjj4j;
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44j4jj4R4j4j4jjj4j;
44j44jjR4j4j44jjjj;
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4j4jjjjR4j4j4jj4jj;
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4j4j4j4R4j4j44j44j;
444jjjjR4j4j4j4jjj;
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444j4j4R4j4j444j4j;
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44444jjR444jj4jjjj;
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jjjjjj4R4444jjjj44;
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jjjj444Rj4jj4jjj4";
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Rd@@.(:4U::(4:(U4#cR8sVVRDbD_D#O DRbDO_#Db RD#D_O_D oCCMsFN0sb\3D#D_O_D dbR#COO_DF _
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Rd@@.g:.46:4:4.g:R.(NPM8R0MG_DbD_HHM00_#_#j_JGlkNGRM0D_bDM_HH#0_0__j#kJlGbNRD#D_O
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--@
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-y---------------------------------
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b@n@d:ddc::d4d:cdcL6Rk0VR8DO_C08_s6Ho_0FR8DO_C08_s6Ho_0FR8DO_C08_sdHo_4F_;R
b@:@j4::44R:.LRkV0lCs__CM4R_F0lCs__CM4R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM.R_F0lCs__CM.R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMdR_F0lCs__CMdR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMcR_F0lCs__CMcR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM6R_F0lCs__CM6R_F0Csk;R
b@n@d::dnUn:d:R4nLRkVOM#__OFR#__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVH_sJbR_FH_sJbR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbD_O __MF.RDbD_O __MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bO_D bR_FD_.bO_D bR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbV_8sCNl_DFR.8b_VlsNCR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDb8_CLR_FD_.bC_8LFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bPHND8R_FD_.bPHND8R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVCRF_FM_R_FCMR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RbD8_s$R_Fb_.Ds_8$FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVsM8__sFR8__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVsCG_sssF_sFRGs_Cs_FsFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#sbNCR_F#sbNCR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#N_s08_H#F0R#N_s08_H#FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#s0N0s_VFVl_b_oNF0R#N_s0VlsF_oVbNR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#F8b_HF#_RF#0bH_8#R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVsRI_FM_R_IsMR_FNlON_sCsVoDN_
b;b@R@d4n:U(g::g4U:R.j#V8Vs0CR8DO_C#8_0kN0#8R0OC_D80_#N#0kRO08_8DC\830OC_D80_#N#0k_R.
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SF0kM_M8FC8=0OC_D8F_Ok_M08CFM
kSOsMsC0N_PDrkCdj4:9M=k48_0OC_D8F_OkCM0s4rd:;j9
@sR@:dn.:UncU:.nd:.RsIF sRVCOC_F0kMCssR0#DRb_COD_C8s_C8OMFk0
CsS OD=C#bOD_O C
SMDNLCs=0kSC
sCC#0b=#CNO_k_G6F#
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FSOk_M08CFM=C#bOC_D8F_Ok_M08CFM
kSOsMsC0N_PDrkCdj4:9M=k4b_#CDO_Cs8_CO8_F0kMCdsr49:j;R
b@n@d::ncUc:n:R46LRkV#ObC_8DC_CosCFM_RC#bOC_D8s_oC_CMFDRbD8_D_
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#;b@R@d.n:ndn:4n:.n(:dRVLkRDbD_H#8_bFRD#D_8FH_RDbD_H#8;R
b@n@d:n.n::d4.:nndL(Rk#VRb_CON.kG_#FRb_CON.kG_bFRD#D_8
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b@n@d:dd.::6jd:.dnHcRMkPRMod_M_klsCC#0MRkdM_oksl_C0#CRC#bOk_NGH4_;R
b@n@d:dd.::d.d:.dcHcRMkPRMo6_M_klsCC#0MRk6M_oksl_C0#CR0s#_NM__
H;b@R@ddn:cdd:4c:dd6:cRPHMRO08_8DC_H0soFd__04R8DO_C08_sdHo_4F_RC#bOk_NGHj_;R
b@:@j4::44R:.0CskRk0sCsR0k
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;N3HRs_0DFosHMCNlR8"0OC_D8s_0H_o.F
";b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soFd_RO08_8DC_H0soFd_RO08_8DC_H0soFd__
4;b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soFc_RO08_8DC_H0soFc_RO08_8DC_H0soFd__
4;b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soF6_RO08_8DC_H0soF6_RO08_8DC_H0soFd__
4;b@R@j::44::4.kRLVCR0sCl_M__4FCR0sCl_M__4FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__.FCR0sCl_M__.FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__dFCR0sCl_M__dFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__cFCR0sCl_M__cFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__6FCR0sCl_M__6FsR0k
C;b@R@ddn:n::Ud4n:nkRLV#RO_FM_R_O#MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVsRHJ__bFsRHJ__bFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bO_D MR_FD_.bO_D MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbD_O __bF.RDbD_O __bFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.b8NVslFC_RbD._s8VN_lCFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bC_8LF.RDb8_CLR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbN_PD_H8F.RDbN_PD_H8FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVFMC__FFRC__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVb_.Ds_8$F.RbD8_s$R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV8Rs_FM_R_s8MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVGRs_sCsFFs_R_sGCFsssR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVbR#N_sCFbR#N_sCFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#s0N0H_8#R_F#s0N0H_8#R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#N_s0VlsF_oVbNR_F#s0N0s_VFVl_b_oNFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#b0F_#8H_#FR0_Fb8_H#FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVIMs__IFRs__MFORNNCl_sDsVNbo_;R
b@n@d:g4U:4(:U.g:j8R#VCVsRO08_8DC_N#00Rk#0_8OD_C8#00Nk0#R8DO_C38\0_8OD_C8#00Nk.#_
RRRR ODRC#bOk_NGFc_RO08_8DC_kOFM80_F;MC
RNH3Ds0_HFsolMNC0R"8DO_C#8_0kN0#
";b@R@ddn:.dd:..:ddc:nRPFsRC#bOk_NGF6_RC#bOk_NGF6_RdkM_koMlC_s#RC0k_M6olMk_#sCC
0;b@R@d4n:U(U::U4U:R4U#V8Vs#CRb_COD_C8sRC8#ObC_8DC_8sCRC#bOC_D8#\3b_COD_C8s_C84bR#COO_DR
......
hdl/spec/syn/test_tdc_pll/syn_tdc.srm
View file @ cb30b5d1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/spec/syn/test_tdc_pll/syn_tdc.srr
View file @ cb30b5d1
......@@ -5,10 +5,10 @@
#Implementation: test_tdc_pll
#Fri Jul 15 19:30:52 2011
#Mon Jul 18 09:43:56 2011
$ Start of Compile
#Fri Jul 15 19:30:52 2011
#Mon Jul 18 09:43:56 2011
Synopsys VHDL Compiler, version comp500rc, Build 027R, built Feb 19 2010
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
......@@ -131,7 +131,7 @@ State machine has 5 reachable states with original encodings of:
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_pll/top_test_pll.vhd":89:8:89:12|Input lf2_i is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 15 19:30:53 2011
# Mon Jul 18 09:43:57 2011
###########################################################]
Synopsys Xilinx Technology Mapper, Version map510rc, Build 068R, Built Feb 22 2010 15:14:03
......@@ -147,10 +147,8 @@ Adding property syn_netlist_hierarchy, value 0 to view:work.top_tdc(rtl)
@N: MF257 |Gated clock conversion enabled
Adding property syn_pad_type, value "LVCMOS_25", to instance spec_led_green_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_cs_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sdi_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sclk_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sdi_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig1_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig2_o
......@@ -363,34 +361,34 @@ Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Me
@N: FX430 |Found 2 global buffers instantiated by user
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 125MB)
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_00 = 00000000000000000000000000000000000000000000000001E009E102300231
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_04 = 101600171C18001900120C13241400150C030004F01004110632600000014002
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_05 = 04A600A700A804A900A204A300A400A5001E381F04A000A1001A001B081C001D
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_06 = 0190019101920193294069410D42094328F228F328F428F500AA00AB28F028F1
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_07 = 45A081A101A201A3019C019D899E019F01988999019A459B0194019501960197
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INITP_00 = 0000008220550000000000000000C40000000000000000000000000000000000
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_00 = 000000000000000000000000000000000000000000000000FD1FF51EFECFFECE
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_04 = ECE9FCE8E0E7FCE6FCEDF0ECD8EBFCEAF0FCFCFB0CEFF8EEFACD9CFFFCFEBCFD
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_05 = F859FC58FC57F856FC5DF85CFC5BFC5AFCE1C4E0F85FFC5EFCE5FCE4F4E3FCE2
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_06 = FD6FFD6EFD6DFD6CD5BF95BEF1BDF5BCD40DD40CD40BD40AFC55FC54D40FD40E
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INIT_07 = B95F7D5EFD5DFD5CFD63FD627561FD60FD677566FD65B964FD6BFD6AFD69FD68
@N: FX276 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":381:41:381:50|Startup value clks_rsts_mgment.un7_word_being_sent_0_0.INITP_00 = FFFFFF7DDFAAFFFFFFFFFFFFFFFF3BFF000000000000000000000000000000FF
@N: FX211 |Packed ROM clks_rsts_mgment.un7_word_being_sent_0[17:0] (7 input, 18 output) to Block SelectRAM
@A: BN291 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd":35:7:35:11|Boundary register spec_led_red_counter.value[31:0] has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell.
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 127MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 126MB peak: 127MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)
Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)
Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 127MB peak: 127MB)
Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 126MB peak: 127MB)
Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 127MB peak: 127MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -3.67ns 188 / 92
2 0h:00m:01s -3.67ns 188 / 92
1 0h:00m:01s -3.68ns 200 / 92
2 0h:00m:01s -3.68ns 200 / 92
------------------------------------------------------------
Timing driven replication report
@N: FX271 :|Instance "N_132_i" with 44 loads has been replicated 1 time(s) to improve timing
@N: FX271 :|Instance "N_188_i" with 44 loads has been replicated 1 time(s) to improve timing
Added 0 Registers via timing driven replication
Added 1 LUTs via timing driven replication
......@@ -408,17 +406,14 @@ No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -3.14ns 182 / 92
1 0h:00m:01s -3.15ns 201 / 92
Timing driven replication report
No replication required.
2 0h:00m:01s -3.14ns 182 / 92
3 0h:00m:01s -3.14ns 182 / 92
4 0h:00m:01s -3.14ns 183 / 92
5 0h:00m:01s -3.14ns 183 / 92
6 0h:00m:01s -3.14ns 183 / 92
7 0h:00m:01s -3.14ns 183 / 92
8 0h:00m:01s -3.14ns 183 / 92
2 0h:00m:01s -3.15ns 201 / 92
3 0h:00m:01s -3.15ns 202 / 92
4 0h:00m:01s -3.15ns 202 / 92
5 0h:00m:01s -3.15ns 202 / 92
------------------------------------------------------------
Timing driven replication report
......@@ -429,19 +424,19 @@ No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:01s -3.14ns 184 / 92
1 0h:00m:01s -3.15ns 202 / 92
Timing driven replication report
No replication required.
2 0h:00m:01s -3.14ns 184 / 92
3 0h:00m:01s -3.14ns 184 / 92
4 0h:00m:01s -3.14ns 184 / 92
2 0h:00m:01s -3.15ns 202 / 92
3 0h:00m:01s -3.15ns 202 / 92
4 0h:00m:01s -3.15ns 202 / 92
------------------------------------------------------------
Net buffering Report for view:work.top_tdc(rtl):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 128MB)
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 127MB)
@N: FX623 |Packing into LUT62
Finished restoring hierarchy (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 128MB)
......@@ -451,7 +446,7 @@ Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current
Writing EDIF Netlist and constraint files
D-2010.03
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 127MB peak: 129MB)
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:03s; Memory used current: 127MB peak: 129MB)
Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 126MB peak: 129MB)
......@@ -481,7 +476,7 @@ Port spec_led_red_o - has output constraint of 2.00ns w.r.t. clock spec_clk20:r
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jul 15 19:30:57 2011
# Timing Report written on Mon Jul 18 09:44:01 2011
#
......@@ -498,14 +493,14 @@ Performance Summary
*******************
Worst slack in design: -2.997
Worst slack in design: -3.015
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------
spec_clk20 20.0 MHz 104.2 MHz 50.000 9.592 40.408 declared default_clkgroup__2
tdc_clk125 125.0 MHz 90.9 MHz 8.000 10.997 -2.997 declared default_clkgroup__1
top_tdc|spec_clk_i 200.0 MHz 167.5 MHz 5.000 5.971 -0.971 inferred Inferred_clkgroup_0
tdc_clk125 125.0 MHz 90.8 MHz 8.000 11.015 -3.015 declared default_clkgroup__1
top_tdc|spec_clk_i 200.0 MHz 161.3 MHz 5.000 6.201 -1.201 inferred Inferred_clkgroup_0
==========================================================================================================================
......@@ -519,14 +514,14 @@ Clocks | rise to rise | fall to fa
-------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-------------------------------------------------------------------------------------------------------------------------------
tdc_clk125 tdc_clk125 | 8.000 -2.997 | No paths - | No paths - | No paths -
tdc_clk125 tdc_clk125 | 8.000 -3.015 | No paths - | No paths - | No paths -
tdc_clk125 spec_clk20 | Diff grp - | No paths - | No paths - | No paths -
tdc_clk125 top_tdc|spec_clk_i | Diff grp - | No paths - | No paths - | No paths -
spec_clk20 tdc_clk125 | Diff grp - | No paths - | No paths - | No paths -
spec_clk20 spec_clk20 | 50.000 40.408 | No paths - | No paths - | No paths -
top_tdc|spec_clk_i tdc_clk125 | Diff grp - | No paths - | No paths - | No paths -
top_tdc|spec_clk_i spec_clk20 | Diff grp - | No paths - | No paths - | No paths -
top_tdc|spec_clk_i top_tdc|spec_clk_i | 5.000 -0.971 | No paths - | No paths - | No paths -
top_tdc|spec_clk_i top_tdc|spec_clk_i | 5.000 -1.201 | No paths - | No paths - | No paths -
===============================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
......@@ -610,9 +605,9 @@ pll_ld_i spec_clk20 (rising) 2.000 2.000 42.408
pll_refmon_i spec_clk20 (rising) 2.000 NA NA NA
pll_sdo_i spec_clk20 (rising) 2.000 NA NA NA
pll_status_i spec_clk20 (rising) 2.000 NA NA NA
rst_n_a_i tdc_clk125 (rising) 2.000 2.000 -0.997 -2.997
rst_n_a_i tdc_clk125 (rising) 2.000 2.000 -1.015 -3.015
spec_aux0_i tdc_clk125 (rising) 2.000 2.000 -0.581 -2.581
spec_aux1_i tdc_clk125 (rising) 2.000 2.000 -0.997 -2.997
spec_aux1_i tdc_clk125 (rising) 2.000 2.000 -1.015 -3.015
spec_clk_i NA NA NA NA NA
tdc_clk_n_i tdc_clk125 (rising) 2.000 NA NA NA
tdc_clk_p_i tdc_clk125 (rising) 2.000 NA NA NA
......@@ -628,13 +623,13 @@ Port Starting User
Name Reference Constraint Time Time Slack
Clock
-----------------------------------------------------------------------------------------------------------------
pll_cs_o top_tdc|spec_clk_i (rising) 2.000(spec_clk20 rising) 10.827 NA NA
pll_cs_o top_tdc|spec_clk_i (rising) 2.000(spec_clk20 rising) 10.836 NA NA
pll_sclk_o top_tdc|spec_clk_i (rising) 2.000(spec_clk20 rising) 5.344 NA NA
pll_sdi_o top_tdc|spec_clk_i (rising) 2.000(spec_clk20 rising) 16.613 NA NA
spec_aux2_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 5.344 NA NA
spec_aux3_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 16.613 NA NA
spec_aux4_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 10.827 NA NA
spec_aux5_o tdc_clk125 (rising) 2.000(tdc_clk125 rising) 8.997 6.000 -2.997
pll_sdi_o top_tdc|spec_clk_i (rising) 2.000(spec_clk20 rising) 17.785 NA NA
spec_aux2_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 17.785 NA NA
spec_aux3_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 10.836 NA NA
spec_aux4_o top_tdc|spec_clk_i (rising) 2.000(tdc_clk125 rising) 5.344 NA NA
spec_aux5_o tdc_clk125 (rising) 2.000(tdc_clk125 rising) 9.015 6.000 -3.015
spec_led_green_o spec_clk20 (rising) 2.000(spec_clk20 rising) 7.592 48.000 40.408
spec_led_red_o spec_clk20 (rising) 2.000(spec_clk20 rising) 2.500 48.000 45.500
tdc_led_status_o tdc_clk125 (rising) 2.000(tdc_clk125 rising) 2.500 6.000 3.500
......@@ -920,16 +915,16 @@ Starting Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
rst_n_a_i tdc_clk125 Port rst_n_a_i rst_n_a_i 2.000 -2.997
spec_aux1_i tdc_clk125 Port spec_aux1_i spec_aux1_i 2.000 -2.997
rst_n_a_i tdc_clk125 Port rst_n_a_i rst_n_a_i 2.000 -3.015
spec_aux1_i tdc_clk125 Port spec_aux1_i spec_aux1_i 2.000 -3.015
spec_aux0_i tdc_clk125 Port spec_aux0_i spec_aux0_i 2.000 -2.581
tdc_led_counter.value[17] tdc_clk125 FDR Q un1_tdc_led_counter[17] 2.296 1.477
tdc_led_counter.value[18] tdc_clk125 FDR Q un1_tdc_led_counter[18] 2.296 1.477
tdc_led_counter.value[19] tdc_clk125 FDS Q un1_tdc_led_counter[19] 2.296 1.477
tdc_led_counter.value[27] tdc_clk125 FDR Q un1_tdc_led_counter[27] 2.296 1.477
tdc_led_counter.value[23] tdc_clk125 FDS Q un1_tdc_led_counter[23] 2.296 1.507
tdc_led_counter.value[25] tdc_clk125 FDS Q un1_tdc_led_counter[25] 2.296 1.507
tdc_led_counter.value[26] tdc_clk125 FDR Q un1_tdc_led_counter[26] 2.296 1.507
tdc_led_counter.value[16] tdc_clk125 FDS Q un1_tdc_led_counter[16] 2.296 1.266
tdc_led_counter.value[17] tdc_clk125 FDR Q un1_tdc_led_counter[17] 2.296 1.266
tdc_led_counter.value[18] tdc_clk125 FDR Q un1_tdc_led_counter[18] 2.296 1.266
tdc_led_counter.value[19] tdc_clk125 FDS Q un1_tdc_led_counter[19] 2.296 1.266
tdc_led_counter.value[20] tdc_clk125 FDS Q un1_tdc_led_counter[20] 2.296 1.266
tdc_led_counter.value[21] tdc_clk125 FDS Q un1_tdc_led_counter[21] 2.296 1.266
tdc_led_counter.value[22] tdc_clk125 FDR Q un1_tdc_led_counter[22] 2.296 1.266
====================================================================================================================
......@@ -940,16 +935,16 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------------
spec_aux5_o tdc_clk125 Port spec_aux5_o spec_aux5_o 6.000 -2.997
spec_aux5_o tdc_clk125 Port spec_aux5_o spec_aux5_o 6.000 -3.015
tdc_led_trig3_o tdc_clk125 Port tdc_led_trig3_o tdc_led_trig3_o 6.000 -2.581
tdc_led_trig4_o tdc_clk125 Port tdc_led_trig4_o tdc_led_trig4_o 6.000 -2.581
tdc_led_trig5_o tdc_clk125 Port tdc_led_trig5_o tdc_led_trig5_o 6.000 -2.581
tdc_led_counter.value[0] tdc_clk125 FDS S N_51_i 9.000 1.477
tdc_led_counter.value[1] tdc_clk125 FDS S N_51_i 9.000 1.477
tdc_led_counter.value[2] tdc_clk125 FDS S N_51_i 9.000 1.477
tdc_led_counter.value[3] tdc_clk125 FDS S N_51_i 9.000 1.477
tdc_led_counter.value[4] tdc_clk125 FDS S N_51_i 9.000 1.477
tdc_led_counter.value[5] tdc_clk125 FDR R N_51_i 9.000 1.477
tdc_led_counter.value[0] tdc_clk125 FDS S N_39_i 9.000 1.266
tdc_led_counter.value[1] tdc_clk125 FDS S N_39_i 9.000 1.266
tdc_led_counter.value[2] tdc_clk125 FDS S N_39_i 9.000 1.266
tdc_led_counter.value[3] tdc_clk125 FDS S N_39_i 9.000 1.266
tdc_led_counter.value[4] tdc_clk125 FDS S N_39_i 9.000 1.266
tdc_led_counter.value[5] tdc_clk125 FDR R N_39_i 9.000 1.266
================================================================================================================
......@@ -963,9 +958,9 @@ Path information for path number 1:
- User constraint on ending point: 2.000
= Required time: 6.000
- Propagation time: 6.997
- Propagation time: 7.015
- User constraint on starting point: 2.000
= Slack (critical) : -2.997
= Slack (critical) : -3.015
Number of logic level(s): 3
Starting point: rst_n_a_i / rst_n_a_i
......@@ -980,16 +975,16 @@ rst_n_a_i Port rst_n_a_i In 0.000 2.000
rst_n_a_i Net - - 0.000 - 1
rst_n_a_i_ibuf IBUF I In - 2.000 -
rst_n_a_i_ibuf IBUF O Out 1.290 3.290 -
rst_n_a_i_c Net - - 1.160 - 14
spec_aux5_o_obuf_RNO LUT2 I0 In - 4.450 -
spec_aux5_o_obuf_RNO LUT2 O Out 0.244 4.694 -
N_132_i Net - - 0.862 - 1
spec_aux5_o_obuf OBUF I In - 5.557 -
spec_aux5_o_obuf OBUF O Out 3.440 8.997 -
rst_n_a_i_c Net - - 1.179 - 16
spec_aux5_o_obuf_RNO LUT2 I0 In - 4.469 -
spec_aux5_o_obuf_RNO LUT2 O Out 0.244 4.713 -
N_188_i Net - - 0.862 - 1
spec_aux5_o_obuf OBUF I In - 5.575 -
spec_aux5_o_obuf OBUF O Out 3.440 9.015 -
spec_aux5_o Net - - 0.000 - 1
spec_aux5_o Port spec_aux5_o Out - 8.997 -
spec_aux5_o Port spec_aux5_o Out - 9.015 -
==========================================================================================
Total path delay (propagation time + setup) of 6.997 is 4.974(71.1%) logic and 2.023(28.9%) route.
Total path delay (propagation time + setup) of 7.015 is 4.974(70.9%) logic and 2.041(29.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -998,9 +993,9 @@ Path information for path number 2:
- User constraint on ending point: 2.000
= Required time: 6.000
- Propagation time: 6.997
- Propagation time: 7.015
- User constraint on starting point: 2.000
= Slack (critical) : -2.997
= Slack (critical) : -3.015
Number of logic level(s): 3
Starting point: spec_aux1_i / spec_aux1_i
......@@ -1015,16 +1010,16 @@ spec_aux1_i Port spec_aux1_i In 0.000 2.000
spec_aux1_i Net - - 0.000 - 1
spec_aux1_i_ibuf IBUF I In - 2.000 -
spec_aux1_i_ibuf IBUF O Out 1.290 3.290 -
spec_aux1_i_c Net - - 1.160 - 14
spec_aux5_o_obuf_RNO LUT2 I1 In - 4.450 -
spec_aux5_o_obuf_RNO LUT2 O Out 0.244 4.694 -
N_132_i Net - - 0.862 - 1
spec_aux5_o_obuf OBUF I In - 5.557 -
spec_aux5_o_obuf OBUF O Out 3.440 8.997 -
spec_aux1_i_c Net - - 1.179 - 16
spec_aux5_o_obuf_RNO LUT2 I1 In - 4.469 -
spec_aux5_o_obuf_RNO LUT2 O Out 0.244 4.713 -
N_188_i Net - - 0.862 - 1
spec_aux5_o_obuf OBUF I In - 5.575 -
spec_aux5_o_obuf OBUF O Out 3.440 9.015 -
spec_aux5_o Net - - 0.000 - 1
spec_aux5_o Port spec_aux5_o Out - 8.997 -
spec_aux5_o Port spec_aux5_o Out - 9.015 -
==========================================================================================
Total path delay (propagation time + setup) of 6.997 is 4.974(71.1%) logic and 2.023(28.9%) route.
Total path delay (propagation time + setup) of 7.015 is 4.974(70.9%) logic and 2.041(29.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1148,16 +1143,16 @@ Starting Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[23] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[23] 5.140 -0.971
clks_rsts_mgment.general_poreset.value[25] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[25] 5.140 -0.971
clks_rsts_mgment.general_poreset.value[26] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[26] 5.140 -0.971
clks_rsts_mgment.general_poreset.value[22] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[22] 5.140 -0.879
clks_rsts_mgment.general_poreset.value[24] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[24] 5.140 -0.879
clks_rsts_mgment.general_poreset.value[7] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[7] 5.140 -0.871
clks_rsts_mgment.general_poreset.value[8] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[8] 5.140 -0.871
clks_rsts_mgment.general_poreset.value[13] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[13] 5.140 -0.831
clks_rsts_mgment.general_poreset.value[14] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[14] 5.140 -0.831
clks_rsts_mgment.general_poreset.value[1] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[1] 5.140 -0.791
clks_rsts_mgment.general_poreset.value[10] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[10] 5.140 -1.201
clks_rsts_mgment.general_poreset.value[11] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[11] 5.140 -1.201
clks_rsts_mgment.general_poreset.value[1] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[1] 5.140 -1.116
clks_rsts_mgment.general_poreset.value[2] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[2] 5.140 -1.116
clks_rsts_mgment.general_poreset.value[12] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[12] 5.140 -1.116
clks_rsts_mgment.general_poreset.value[13] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[13] 5.140 -1.116
clks_rsts_mgment.general_poreset.value[20] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[20] 5.140 -0.933
clks_rsts_mgment.general_poreset.value[21] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[21] 5.140 -0.933
clks_rsts_mgment.general_poreset.value[22] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[22] 5.140 -0.930
clks_rsts_mgment.general_poreset.value[23] top_tdc|spec_clk_i FDRE Q clks_rsts_mgment.general_poreset.value_qxu[23] 5.140 -0.930
============================================================================================================================================================
......@@ -1168,16 +1163,16 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[0] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[1] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[2] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[3] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[4] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[5] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[6] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[7] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[8] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[9] top_tdc|spec_clk_i FDRE CE N_10_i 9.257 -0.971
clks_rsts_mgment.general_poreset.value[0] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[1] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[2] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[3] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[4] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[5] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[6] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[7] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[8] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
clks_rsts_mgment.general_poreset.value[9] top_tdc|spec_clk_i FDRE CE N_18_i 9.257 -1.201
====================================================================================================================
......@@ -1192,33 +1187,33 @@ Path information for path number 1:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 5.673
- Propagation time: 5.903
- Clock delay at starting point: 4.555
= Slack (non-critical) : -0.971
= Slack (non-critical) : -1.201
Number of logic level(s): 3
Starting point: clks_rsts_mgment.general_poreset.value[23] / Q
Starting point: clks_rsts_mgment.general_poreset.value[10] / Q
Ending point: clks_rsts_mgment.general_poreset.value[0] / CE
The start point is clocked by top_tdc|spec_clk_i [rising] on pin C
The end point is clocked by top_tdc|spec_clk_i [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[23] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[23] Net - - 0.935 - 2
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 I0 In - 6.075 -
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 O Out 0.427 6.502 -
m11_0_a2_2 Net - - 0.910 - 2
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L I5 In - 7.412 -
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L LO Out 0.195 7.608 -
N_2251 Net - - 1.050 - 1
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I5 In - 8.658 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.287 8.945 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 10.228 -
===================================================================================================================
Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[10] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[10] Net - - 0.985 - 4
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L I0 In - 6.125 -
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L LO Out 0.244 6.369 -
m15_0_1 Net - - 1.050 - 1
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 I5 In - 7.418 -
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 O Out 0.342 7.761 -
m15_2 Net - - 1.292 - 33
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I5 In - 9.053 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.122 9.175 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 10.458 -
====================================================================================================================
Total path delay (propagation time + setup) of 6.201 is 1.591(25.7%) logic and 4.610(74.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1237,7 +1232,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[23] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[10] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1266,33 +1261,33 @@ Path information for path number 2:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 5.673
- Propagation time: 5.903
- Clock delay at starting point: 4.555
= Slack (non-critical) : -0.971
= Slack (non-critical) : -1.201
Number of logic level(s): 3
Starting point: clks_rsts_mgment.general_poreset.value[25] / Q
Starting point: clks_rsts_mgment.general_poreset.value[11] / Q
Ending point: clks_rsts_mgment.general_poreset.value[0] / CE
The start point is clocked by top_tdc|spec_clk_i [rising] on pin C
The end point is clocked by top_tdc|spec_clk_i [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[25] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[25] Net - - 0.935 - 2
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 I1 In - 6.075 -
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 O Out 0.427 6.502 -
m11_0_a2_2 Net - - 0.910 - 2
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L I5 In - 7.412 -
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L LO Out 0.195 7.608 -
N_2251 Net - - 1.050 - 1
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I5 In - 8.658 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.287 8.945 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 10.228 -
===================================================================================================================
Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[11] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[11] Net - - 0.985 - 4
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L I1 In - 6.125 -
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L LO Out 0.244 6.369 -
m15_0_1 Net - - 1.050 - 1
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 I5 In - 7.418 -
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 O Out 0.342 7.761 -
m15_2 Net - - 1.292 - 33
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I5 In - 9.053 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.122 9.175 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 10.458 -
====================================================================================================================
Total path delay (propagation time + setup) of 6.201 is 1.591(25.7%) logic and 4.610(74.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1311,7 +1306,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[25] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[11] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1340,33 +1335,33 @@ Path information for path number 3:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 5.673
- Propagation time: 5.903
- Clock delay at starting point: 4.555
= Slack (non-critical) : -0.971
= Slack (non-critical) : -1.201
Number of logic level(s): 3
Starting point: clks_rsts_mgment.general_poreset.value[26] / Q
Ending point: clks_rsts_mgment.general_poreset.value[0] / CE
Starting point: clks_rsts_mgment.general_poreset.value[10] / Q
Ending point: clks_rsts_mgment.general_poreset.value[31] / CE
The start point is clocked by top_tdc|spec_clk_i [rising] on pin C
The end point is clocked by top_tdc|spec_clk_i [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[26] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[26] Net - - 0.935 - 2
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 I2 In - 6.075 -
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 O Out 0.427 6.502 -
m11_0_a2_2 Net - - 0.910 - 2
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L I5 In - 7.412 -
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L LO Out 0.195 7.608 -
N_2251 Net - - 1.050 - 1
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I5 In - 8.658 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.287 8.945 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 10.228 -
===================================================================================================================
Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[10] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[10] Net - - 0.985 - 4
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L I0 In - 6.125 -
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L LO Out 0.244 6.369 -
m15_0_1 Net - - 1.050 - 1
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 I5 In - 7.418 -
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 O Out 0.342 7.761 -
m15_2 Net - - 1.292 - 33
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I5 In - 9.053 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.122 9.175 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[31] FDRE CE In - 10.458 -
====================================================================================================================
Total path delay (propagation time + setup) of 6.201 is 1.591(25.7%) logic and 4.610(74.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1385,27 +1380,27 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[26] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[10] FDRE C In - 4.555 -
=============================================================================================================================
End clock path:
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------
Start Clock : top_tdc|spec_clk_i
------------
spec_clk_i Port spec_clk_i In - 0.000 -
spec_clk_i Net - - 0.000 - 1
clks_rsts_mgment.spec_clk_ibuf IBUFG I In - 0.000 -
clks_rsts_mgment.spec_clk_ibuf IBUFG O Out 1.290 1.290 -
clks_rsts_mgment.spec_clk_buf Net - - 1.304 - 1
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[0] FDRE C In - 4.555 -
============================================================================================================================
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------
Start Clock : top_tdc|spec_clk_i
------------
spec_clk_i Port spec_clk_i In - 0.000 -
spec_clk_i Net - - 0.000 - 1
clks_rsts_mgment.spec_clk_ibuf IBUFG I In - 0.000 -
clks_rsts_mgment.spec_clk_ibuf IBUFG O Out 1.290 1.290 -
clks_rsts_mgment.spec_clk_buf Net - - 1.304 - 1
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[31] FDRE C In - 4.555 -
=============================================================================================================================
Path information for path number 4:
......@@ -1414,33 +1409,33 @@ Path information for path number 4:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 5.673
- Propagation time: 5.903
- Clock delay at starting point: 4.555
= Slack (non-critical) : -0.971
= Slack (non-critical) : -1.201
Number of logic level(s): 3
Starting point: clks_rsts_mgment.general_poreset.value[23] / Q
Ending point: clks_rsts_mgment.general_poreset.value[31] / CE
Starting point: clks_rsts_mgment.general_poreset.value[10] / Q
Ending point: clks_rsts_mgment.general_poreset.value[30] / CE
The start point is clocked by top_tdc|spec_clk_i [rising] on pin C
The end point is clocked by top_tdc|spec_clk_i [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[23] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[23] Net - - 0.935 - 2
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 I0 In - 6.075 -
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 O Out 0.427 6.502 -
m11_0_a2_2 Net - - 0.910 - 2
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L I5 In - 7.412 -
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L LO Out 0.195 7.608 -
N_2251 Net - - 1.050 - 1
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I5 In - 8.658 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.287 8.945 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[31] FDRE CE In - 10.228 -
===================================================================================================================
Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[10] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[10] Net - - 0.985 - 4
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L I0 In - 6.125 -
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L LO Out 0.244 6.369 -
m15_0_1 Net - - 1.050 - 1
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 I5 In - 7.418 -
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 O Out 0.342 7.761 -
m15_2 Net - - 1.292 - 33
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I5 In - 9.053 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.122 9.175 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[30] FDRE CE In - 10.458 -
====================================================================================================================
Total path delay (propagation time + setup) of 6.201 is 1.591(25.7%) logic and 4.610(74.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1459,7 +1454,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[23] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[10] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1478,7 +1473,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[31] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[30] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1488,33 +1483,33 @@ Path information for path number 5:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 5.673
- Propagation time: 5.903
- Clock delay at starting point: 4.555
= Slack (non-critical) : -0.971
= Slack (non-critical) : -1.201
Number of logic level(s): 3
Starting point: clks_rsts_mgment.general_poreset.value[23] / Q
Ending point: clks_rsts_mgment.general_poreset.value[30] / CE
Starting point: clks_rsts_mgment.general_poreset.value[10] / Q
Ending point: clks_rsts_mgment.general_poreset.value[29] / CE
The start point is clocked by top_tdc|spec_clk_i [rising] on pin C
The end point is clocked by top_tdc|spec_clk_i [rising] on pin C
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[23] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[23] Net - - 0.935 - 2
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 I0 In - 6.075 -
clks_rsts_mgment.general_poreset.value_RNIBN28[23] LUT3 O Out 0.427 6.502 -
m11_0_a2_2 Net - - 0.910 - 2
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L I5 In - 7.412 -
clks_rsts_mgment.general_poreset.value_RNIUV8Q[20] LUT6_L LO Out 0.195 7.608 -
N_2251 Net - - 1.050 - 1
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I5 In - 8.658 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.287 8.945 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[30] FDRE CE In - 10.228 -
===================================================================================================================
Total path delay (propagation time + setup) of 5.971 is 1.793(30.0%) logic and 4.178(70.0%) route.
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[10] FDRE Q Out 0.585 5.140 -
clks_rsts_mgment.general_poreset.value_qxu[10] Net - - 0.985 - 4
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L I0 In - 6.125 -
clks_rsts_mgment.general_poreset.value_RNITDB5[10] LUT2_L LO Out 0.244 6.369 -
m15_0_1 Net - - 1.050 - 1
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 I5 In - 7.418 -
clks_rsts_mgment.general_poreset.value_RNI1JF01[15] LUT6 O Out 0.342 7.761 -
m15_2 Net - - 1.292 - 33
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I5 In - 9.053 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.122 9.175 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[29] FDRE CE In - 10.458 -
====================================================================================================================
Total path delay (propagation time + setup) of 6.201 is 1.591(25.7%) logic and 4.610(74.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1533,7 +1528,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[23] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[10] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1552,7 +1547,7 @@ clks_rsts_mgment.spec_clk_buf Net -
clks_rsts_mgment.spec_clk_gbuf BUFG I In - 2.594 -
clks_rsts_mgment.spec_clk_gbuf BUFG O Out 0.250 2.844 -
spec_clk_i_0 Net - - 1.711 - 0
clks_rsts_mgment.general_poreset.value[30] FDRE C In - 4.555 -
clks_rsts_mgment.general_poreset.value[29] FDRE C In - 4.555 -
=============================================================================================================================
......@@ -1571,7 +1566,7 @@ Starting Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr System FDC Q clks_rsts_mgment.gral_incr 0.585 1.045
clks_rsts_mgment.gral_incr System FDC Q clks_rsts_mgment.gral_incr 0.585 1.026
==============================================================================================================
......@@ -1582,16 +1577,16 @@ Ending Points with Worst Slack
Instance Reference Type Pin Net Time Slack
Clock
----------------------------------------------------------------------------------------------------------
clks_rsts_mgment.general_poreset.value[0] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[1] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[2] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[3] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[4] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[5] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[6] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[7] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[8] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[9] System FDRE CE N_10_i 4.702 1.045
clks_rsts_mgment.general_poreset.value[0] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[1] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[2] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[3] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[4] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[5] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[6] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[7] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[8] System FDRE CE N_18_i 4.702 1.026
clks_rsts_mgment.general_poreset.value[9] System FDRE CE N_18_i 4.702 1.026
==========================================================================================================
......@@ -1606,9 +1601,9 @@ Path information for path number 1:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 3.657
- Propagation time: 3.676
- Estimated clock delay at start point: 4.555
= Slack (non-critical) : 1.045
= Slack (non-critical) : 1.026
Number of logic level(s): 1
Starting point: clks_rsts_mgment.gral_incr / Q
......@@ -1620,13 +1615,13 @@ Instance / Net Pin Pin
Name Type Name Dir Delay Time Fan Out(s)
--------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr FDC Q Out 0.585 0.585 -
clks_rsts_mgment.gral_incr Net - - 0.935 - 2
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I0 In - 1.520 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.854 2.374 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 3.657 -
clks_rsts_mgment.gral_incr Net - - 0.955 - 3
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I0 In - 1.540 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.854 2.394 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[0] FDRE CE In - 3.676 -
========================================================================================================
Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
Total path delay (propagation time + setup) of 3.974 is 1.737(43.7%) logic and 2.237(56.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1665,9 +1660,9 @@ Path information for path number 2:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 3.657
- Propagation time: 3.676
- Estimated clock delay at start point: 4.555
= Slack (non-critical) : 1.045
= Slack (non-critical) : 1.026
Number of logic level(s): 1
Starting point: clks_rsts_mgment.gral_incr / Q
......@@ -1679,13 +1674,13 @@ Instance / Net Pin Pin
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr FDC Q Out 0.585 0.585 -
clks_rsts_mgment.gral_incr Net - - 0.935 - 2
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I0 In - 1.520 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.854 2.374 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[31] FDRE CE In - 3.657 -
clks_rsts_mgment.gral_incr Net - - 0.955 - 3
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I0 In - 1.540 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.854 2.394 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[31] FDRE CE In - 3.676 -
=========================================================================================================
Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
Total path delay (propagation time + setup) of 3.974 is 1.737(43.7%) logic and 2.237(56.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1724,9 +1719,9 @@ Path information for path number 3:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 3.657
- Propagation time: 3.676
- Estimated clock delay at start point: 4.555
= Slack (non-critical) : 1.045
= Slack (non-critical) : 1.026
Number of logic level(s): 1
Starting point: clks_rsts_mgment.gral_incr / Q
......@@ -1738,13 +1733,13 @@ Instance / Net Pin Pin
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr FDC Q Out 0.585 0.585 -
clks_rsts_mgment.gral_incr Net - - 0.935 - 2
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I0 In - 1.520 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.854 2.374 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[30] FDRE CE In - 3.657 -
clks_rsts_mgment.gral_incr Net - - 0.955 - 3
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I0 In - 1.540 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.854 2.394 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[30] FDRE CE In - 3.676 -
=========================================================================================================
Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
Total path delay (propagation time + setup) of 3.974 is 1.737(43.7%) logic and 2.237(56.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1783,9 +1778,9 @@ Path information for path number 4:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 3.657
- Propagation time: 3.676
- Estimated clock delay at start point: 4.555
= Slack (non-critical) : 1.045
= Slack (non-critical) : 1.026
Number of logic level(s): 1
Starting point: clks_rsts_mgment.gral_incr / Q
......@@ -1797,13 +1792,13 @@ Instance / Net Pin Pin
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr FDC Q Out 0.585 0.585 -
clks_rsts_mgment.gral_incr Net - - 0.935 - 2
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I0 In - 1.520 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.854 2.374 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[29] FDRE CE In - 3.657 -
clks_rsts_mgment.gral_incr Net - - 0.955 - 3
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I0 In - 1.540 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.854 2.394 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[29] FDRE CE In - 3.676 -
=========================================================================================================
Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
Total path delay (propagation time + setup) of 3.974 is 1.737(43.7%) logic and 2.237(56.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1842,9 +1837,9 @@ Path information for path number 5:
+ Clock delay at ending point: 4.555
= Required time: 9.257
- Propagation time: 3.657
- Propagation time: 3.676
- Estimated clock delay at start point: 4.555
= Slack (non-critical) : 1.045
= Slack (non-critical) : 1.026
Number of logic level(s): 1
Starting point: clks_rsts_mgment.gral_incr / Q
......@@ -1856,13 +1851,13 @@ Instance / Net Pin Pin
Name Type Name Dir Delay Time Fan Out(s)
---------------------------------------------------------------------------------------------------------
clks_rsts_mgment.gral_incr FDC Q Out 0.585 0.585 -
clks_rsts_mgment.gral_incr Net - - 0.935 - 2
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 I0 In - 1.520 -
clks_rsts_mgment.gral_incr_RNIIVJI3 LUT6 O Out 0.854 2.374 -
N_10_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[28] FDRE CE In - 3.657 -
clks_rsts_mgment.gral_incr Net - - 0.955 - 3
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 I0 In - 1.540 -
clks_rsts_mgment.gral_incr_RNIJDSQ2 LUT6 O Out 0.854 2.394 -
N_18_i Net - - 1.283 - 32
clks_rsts_mgment.general_poreset.value[28] FDRE CE In - 3.676 -
=========================================================================================================
Total path delay (propagation time + setup) of 3.955 is 1.737(43.9%) logic and 2.218(56.1%) route.
Total path delay (propagation time + setup) of 3.974 is 1.737(43.7%) logic and 2.237(56.3%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value
......@@ -1906,20 +1901,20 @@ Cell usage:
DSP48A1 1 use
FD 13 uses
FDC 1 use
FDR 23 uses
FDR 22 uses
FDRE 34 uses
FDS 21 uses
FDS 22 uses
GND 1 use
MUXCY_L 70 uses
RAMB8BWER 1 use
VCC 1 use
XORCY 71 uses
LUT1 63 uses
LUT2 18 uses
LUT3 16 uses
LUT4 8 uses
LUT5 37 uses
LUT6 35 uses
LUT2 29 uses
LUT3 17 uses
LUT4 10 uses
LUT5 6 uses
LUT6 70 uses
LUT6_2 1 use
I/O ports: 135
......@@ -1945,14 +1940,14 @@ Global Clock Buffers: 2 of 16 (12%)
Number of unique control sets: 9
C(spec_clk_i_0), CLR(GND), PRE(GND), CE(VCC) : 11
C(clk_i), CLR(pll_sclk_i), PRE(GND), CE(VCC) : 1
C(clk_i), CLR(pll_sclk_o_c_i), PRE(GND), CE(VCC) : 1
C(clk), R(clks_rsts_mgment.inv_reset_i), S(GND), CE(VCC) : 2
C(spec_clk), R(N_132_i_iso), S(GND), CE(VCC) : 2
C(clk), R(GND), S(N_51_i), CE(VCC) : 17
C(clk), R(N_51_i), S(GND), CE(VCC) : 15
C(spec_clk_i_0), R(N_132_i_iso), S(GND), CE(N_10_i) : 32
C(spec_clk_i_0), R(N_132_i_iso), S(GND), CE(VCC) : 2
C(spec_clk_i_0), R(GND), S(N_132_i_iso), CE(VCC) : 4
C(spec_clk), R(N_188_i_iso), S(GND), CE(VCC) : 2
C(clk), R(GND), S(N_39_i), CE(VCC) : 17
C(clk), R(N_39_i), S(GND), CE(VCC) : 15
C(spec_clk_i_0), R(N_188_i_iso), S(GND), CE(N_18_i) : 32
C(spec_clk_i_0), R(N_188_i_iso), S(GND), CE(VCC) : 2
C(spec_clk_i_0), R(GND), S(N_188_i_iso), CE(VCC) : 4
Total load per clock:
top_tdc|spec_clk_i: 53
......@@ -1960,10 +1955,10 @@ Total load per clock:
tdc_clk125: 36
Mapping Summary:
Total LUTs: 178 (0%)
Total LUTs: 196 (0%)
Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Jul 15 19:30:57 2011
# Mon Jul 18 09:44:01 2011
###########################################################]
hdl/spec/syn/test_tdc_pll/syn_tdc.srs
View file @ cb30b5d1
......@@ -6,7 +6,7 @@
#
# Created by Synplify VHDL Compiler version comp500rc, Build 027R from Synplicity, Inc.
# Copyright 1994-2010 Synopsys, Inc. , All rights reserved.
# Synthesis Netlist written on Fri Jul 15 19:30:53 2011
# Synthesis Netlist written on Mon Jul 18 09:43:57 2011
#
#
#OPTIONS:"|-top|top_tdc|-dspmac|-pqdpadd|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-dfltencoding|onehot|-encrypt|-pro|-lite|-ll|2000|-ui|-fid2|-ram|-sharing|off|-autosm|-ignore_undefined_lib|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work|-lib|work"
......@@ -45,11 +45,11 @@
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd":1310389590
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1310750802
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd":1310974921
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd":1306400619
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_nb_offset_gen.vhd":1307641333
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd":1307642203
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_pll/top_test_pll.vhd":1310736179
#CUR:"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/test_tdc_pll/top_test_pll.vhd":1310973394
f "/afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/vhd/std.vhd"; # file 0
af .is_vhdl 1;
f "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"; # file 1
......@@ -355,269 +355,268 @@ mb=#COO_DF _
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Rd@@.c:dg6:4:gdc:R.gNPM8R0LH_8HMCjG__l#JkRGNL_H0HCM8G__j#kJlGHNRMG8C_MOF0DsF\M3kUD_bDO_#DR
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RRMRk4D_bDO_#D
;b@R@dd.:(.U:((:dU4:cRkblGDRbD8_#HR_Fb_DD#_8HFFRIsL8_CoHM_M#C09rj,4kM_0LH_8HMC4Gr6R9
RIRRF_s8LMCHoC_#M40r9M,k4H_L0M_H8rCG4Rc9I8Fs_HLCM#o_CrM0.k9,ML4_HH0_MG8Cr94d
RRRRsIF8C_LH_Mo#0CMr,d9k_M4L_H0HCM8G.r49FRIsL8_CoHM_M#C09rc,4kM_0LH_8HMC4Gr4R9
RIRRF_s8LMCHoC_#M60r9M,k4H_L0M_H8rCG4Rj9I8Fs_HLCM#o_CrM0nk9,ML4_HH0_MG8Cr
g9RRRRI8Fs_HLCM#o_CrM0(k9,ML4_HH0_MG8CrRU9I8Fs_HLCM#o_CrM0Uk9,ML4_HH0_MG8Cr
(9RRRRI8Fs_HLCM#o_CrM0gk9,ML4_HH0_MG8CrRn9V#NDCM,k4H_L0M_H8_CG4N;
HHR3MG8ClRkG4b;
Rd@@.U:46::(4:U64#nR8bVVNR0sLC$0_8HMCnGr:Rj9LC$0_8HMCnGr:Rj9k_M4LC$0_8HMCjGr9$,L0HC_MG8C_66r:,.9k_M4LC$0_8HMC6Gr:
n9RRRR#ObC_ OD_oFRM_klsCC#0;_H
RNH3#sCCN0b0GR"GGGGG;G"
RNH3#sCCN0b04R"jjjj4;4"
RNH3Ds0_HFsolMNCLR"$_0CHCM8G
";b@R@dd.:cUc::cdc:bgRlRkGHCM8GF_OMF0sDL\3HH0_MG8C_dnr:Rj9HCM8GF_OMF0sDL\3HH0_MG8C_dnr:
j9RRRR0Csk,k0sCs,0k0C,s,kCb_DDOF#_RDVN#0C,s,kC0Csk,k0sCH,L0M_H8_CGjJ_#lNkG
RRRR4kM_0LH_8HMC.G_rdj:9M,k4H_L0M_H8_CG4J_#lNkG;R
b@.@d:c4U:4(:U4c:68R#VRV#L_H0HCM8G:rdjL9RHH0_MG8Crjd:9MRH8_CGO0FMs\FD30LH_8HMCnG_rjd:9R
RRbR#COO_DF _RkoMlC_s#_C0HN;
HsR30FD_sMHoNRlC"0LH_8HMC;G"
-y---------------------------------
@
ftell;
@E@MR@:4U4(6:::464IURFRs VCsC_kOFMs0CRDs0;P
NR#3HPDE8R
......@@ -997,73 +996,71 @@ bS#COO_DH _=C#bOD_O
_HSO08_ OD_Hb_=O08_ OD_Hb_
8S0OD_O __MH8=0OD_O __MHN
SO_NlsOCVDF _=NNOlC_sV OD
CSoMNCsDC_s#_C0FC=oMNCsDC_s#
C0SDbD__O#FD=bD#_O
DSbDN_8O$_#MFO_=DbD_O8N_M#$O
_FSDbD_H#8_bF=D#D_8SH
b_DD# OD_bF=D#D_O
D SC#bOD_O =_F#ObC_ OD
CSoMNCsDC_s#_C0Fb=#CNO_k_GcFb
SDOD_#=_Fb_DDOS#
b_DD8_NO#O$M_bF=D8D_N#O_$_MOFb
SD#D_8FH_=DbD_H#8
DSbDO_#DF _=DbD_D#O
_FSC#bOD_O =_F#ObC_ OD
8S0OD_O =_FO;D
@sR@:dn.:(.c(:..U:4RsIF sRVCOC_F0kMCssR00DR8DO_CO8_F0kMCSs
O=D O
D SNCML=DC0Csk
CSs#=C0oCCMs_NDsCC#0#
S00Ns_DPNkdCr49:j=DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,k0sCs,0k0C,s,kCV#NDCs,0k0C,s,kC0Csk,DVN#VC,NCD#,k0sCs,0kVC,NCD#,k0sCN,VD,#C0Csk,k0sCN,VD,#CV#NDCs,0kVC,NCD#,k0sCN,VD,#CV#NDCN,VD,#CV#NDCN,VD
#CSkOFM80_F=MC0_8OD_C8OMFk0F_8MSC
OsksC_M0PkNDC4rd:=j9k_M40_8OD_C8OMFk0rCsdj4:9s;
Rd@@nU:.n::c.:Un.IdRFRs VCsC_kOFMs0CRDs0RC#bOC_D8C_s8F_OkCM0sO
SD# =b_COO
D SNCML=DC0Csk
CSs#=C0#ObC_GNk6
_FSN#0sP0_NCDkr:d4jV9=NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,k0sCN,VD,#CV#NDCs,0k0C,s,kCV#NDCN,VD,#CV#NDCs,0kVC,NCD#,DVN#0C,s,kCV#NDCs,0k0C,s,kCV#NDCs,0kVC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#SC
OMFk0F_8M#C=b_COD_C8OMFk0F_8MSC
OsksC_M0PkNDC4rd:=j9k_M4#ObC_8DC_8sC_kOFMs0Cr:d4j
9;b@R@dnn:c::Un4c:6kRLVbR#CDO_Co8_sMCC_#FRb_COD_C8oCsCMR_Fb_DDDH8_;R
b@n@d:c.n::d4.:ncdLnRkbVRDOD_#R_Fb_DDOF#_RDbD_;O#
@bR@:dn.:ncd.4:ndc:nkRLVbR#CNO_k_GcFbR#CNO_k_GcFDRbD#_O;R
b@n@d:n.n::d4.:nndL(RkbVRD#D_8FH_RDbD_H#8_bFRD#D_8
H;b@R@d.n:ndn:4n:.n(:dRVLkRC#bOk_NGFd_RC#bOk_NGFd_RDbD_H#8;R
b@n@d:(.n::d4.:n(dLURkbVRD#D_O_D FDRbDO_#DF _RDbD_D#O b;
Rd@@nn:.(4:d:(.n:RdULRkV#ObC_GNk.R_F#ObC_GNk.R_Fb_DD# OD;R
b@n@d:6dj::d6d:j66H.RM0PR8DO_C38\0_8OD_C8#00Nk.#_RO08_8DC\830OC_D80_#N#0k_0.R8DO_C#8_0kN0#b;
Rd@@n4:d66:d:6d4:R6jHRMP#ObC_8DC\b3#CDO_Cs8_C48_RC#bOC_D8#\3b_COD_C8s_C84bR#CDO_Cs8_C
8;b@R@ddn:.6d:j.:ddc:nRPHMRdkM_koMlC_s#RC0k_MdolMk_#sCC#0Rb_CON4kG_
H;b@R@ddn:.dd:..:ddc:cRPHMR6kM_koMlC_s#RC0k_M6olMk_#sCCs0R#M0__HN_;R
b@n@d:ddc::d4d:cdcH6RM0PR8DO_C08_sdHo_4F_RO08_8DC_H0soFd__#4Rb_CONjkG_
H;b@R@j::44::4.sR0k0CRsRkC0Csk;R
b@:@j4::44R:.V#NDCNRVDR#CV#NDCb;
Rj@@:44::.4:RR8O88OROb;
Rd@@nn:d:dU:nn:4RR8ONlON_sCsVoDN_NbRO_NlCVssD_Nobb;
Rd@@nj:4j::U4:jj.8.RV0VR8DO_C08_s4Ho_0FR8DO_C08_s4Ho_#FRb_CONjkG_#HRb_COO;D
RNH3Ds0_HFsolMNC0R"8DO_C08_s4Ho_;F"
@bR@:dn4:j4Uj:44.:.RV8VRO08_8DC_H0soF._RO08_8DC_H0soF._RC#bOk_NGHj_R OD;H
NR03sDs_FHNoMl"CR0_8OD_C80osH."_F;R
b@n@d:ddc::d4d:cdcL6Rk0VR8DO_C08_sdHo_0FR8DO_C08_sdHo_0FR8DO_C08_sdHo_4F_;R
b@n@d:ddc::d4d:cdcL6Rk0VR8DO_C08_scHo_0FR8DO_C08_scHo_0FR8DO_C08_sdHo_4F_;R
b@n@d:ddc::d4d:cdcL6Rk0VR8DO_C08_s6Ho_0FR8DO_C08_s6Ho_0FR8DO_C08_sdHo_4F_;R
b@:@j4::44R:.LRkV0lCs__CM4R_F0lCs__CM4R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM.R_F0lCs__CM.R_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMdR_F0lCs__CMdR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CMcR_F0lCs__CMcR_F0Csk;R
b@:@j4::44R:.LRkV0lCs__CM6R_F0lCs__CM6R_F0Csk;R
b@n@d::dnUn:d:R4nLRkVOM#__OFR#__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVH_sJbR_FH_sJbR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbD_O __MF.RDbD_O __MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bO_D bR_FD_.bO_D bR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbV_8sCNl_DFR.8b_VlsNCR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDb8_CLR_FD_.bC_8LFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bPHND8R_FD_.bPHND8R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVCRF_FM_R_FCMR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RbD8_s$R_Fb_.Ds_8$FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVsM8__sFR8__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVsCG_sssF_sFRGs_Cs_FsFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#sbNCR_F#sbNCR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#N_s08_H#F0R#N_s08_H#FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#s0N0s_VFVl_b_oNF0R#N_s0VlsF_oVbNR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#F8b_HF#_RF#0bH_8#R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVsRI_FM_R_IsMR_FNlON_sCsVoDN_
b;b@R@d4n:U(g::g4U:R.j#V8Vs0CR8DO_C#8_0kN0#8R0OC_D80_#N#0kRO08_8DC\830OC_D80_#N#0k_R.
RORRDo RCsMCNsD_C0#CRO08_8DC_kOFM80_F;MC
CSs#=C0#ObC_GNkc
_FSN#0sP0_NCDkr:d4jV9=NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#0C,s,kC0Csk,k0sCN,VD,#C0Csk,k0sCs,0kVC,NCD#,DVN#0C,s,kC0Csk,DVN#0C,s,kCV#NDCs,0k0C,s,kCV#NDCN,VD,#C0Csk,DVN#0C,s,kCV#NDCN,VD,#CV#NDCN,VD,#CV#NDCO
SF0kM_M8FC8=0OC_D8F_Ok_M08CFM
kSOsMsC0N_PDrkCdj4:9M=k48_0OC_D8F_OkCM0s4rd:;j9
@sR@:dn.:UncU:.nd:.RsIF sRVCOC_F0kMCssR0#DRb_COD_C8s_C8OMFk0
CsS OD=C#bOD_O C
SMDNLCs=0kSC
sCC#0b=#CNO_k_G6F#
S00Ns_DPNkdCr49:j=DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#0C,s,kCV#NDCN,VD,#C0Csk,k0sCN,VD,#CV#NDCN,VD,#C0Csk,DVN#VC,NCD#,k0sCN,VD,#C0Csk,k0sCN,VD,#C0Csk,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#,DVN#VC,NCD#
FSOk_M08CFM=C#bOC_D8F_Ok_M08CFM
kSOsMsC0N_PDrkCdj4:9M=k4b_#CDO_Cs8_CO8_F0kMCdsr49:j;R
b@n@d::ncUc:n:R46LRkV#ObC_8DC_CosCFM_RC#bOC_D8s_oC_CMFDRbD8_D_
H;b@R@d.n:ndc:4n:.cn:dRVLkRDbD__O#FDRbD#_O_bFRDOD_#b;
Rd@@nn:.c4:d:c.n:RdnLRkV#ObC_GNkdR_F#ObC_GNkdR_Fb_DDO
#;b@R@d.n:ndn:4n:.n(:dRVLkRDbD_H#8_bFRD#D_8FH_RDbD_H#8;R
b@n@d:n.n::d4.:nndL(Rk#VRb_CON.kG_#FRb_CON.kG_bFRD#D_8
H;b@R@ddn:jd6:6j:d6.:6RPHMRO08_8DC\830OC_D80_#N#0k_0.R8DO_C38\0_8OD_C8#00Nk.#_RO08_8DC_N#00;k#
@bR@:dnd:46dd6:466:jMRHPbR#CDO_C38\#ObC_8DC_8sC_#4Rb_COD\C83C#bOC_D8C_s8R_4#ObC_8DC_8sC;R
b@n@d:dd.::6jd:.dnHcRMkPRMod_M_klsCC#0MRkdM_oksl_C0#CRC#bOk_NGH4_;R
b@n@d:dd.::d.d:.dcHcRMkPRMo6_M_klsCC#0MRk6M_oksl_C0#CR0s#_NM__
H;b@R@ddn:cdd:4c:dd6:cRPHMRO08_8DC_H0soFd__04R8DO_C08_sdHo_4F_RC#bOk_NGHj_;R
b@:@j4::44R:.0CskRk0sCsR0k
C;b@R@j::44::4.NRVDR#CV#NDCNRVD;#C
@bR@4j::44::8.ROOR8R;8O
@bR@:dndUn:::dn48nROORNNCl_sDsVNbo_RNNOls_CsNVDo;_b
@bR@:dn4:jjUj:4j.:.RV8VRO08_8DC_H0soF4_RO08_8DC_H0soF4_RC#bOk_NGHj_RC#bOD_O N;
HsR30FD_sMHoNRlC"O08_8DC_H0soF4_"b;
Rd@@nj:44::U4:j4.8.RV0VR8DO_C08_s.Ho_0FR8DO_C08_s.Ho_#FRb_CONjkG_OHRD
;N3HRs_0DFosHMCNlR8"0OC_D8s_0H_o.F
";b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soFd_RO08_8DC_H0soFd_RO08_8DC_H0soFd__
4;b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soFc_RO08_8DC_H0soFc_RO08_8DC_H0soFd__
4;b@R@ddn:cdd:4c:dd6:cRVLkRO08_8DC_H0soF6_RO08_8DC_H0soF6_RO08_8DC_H0soFd__
4;b@R@j::44::4.kRLVCR0sCl_M__4FCR0sCl_M__4FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__.FCR0sCl_M__.FsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__dFCR0sCl_M__dFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__cFCR0sCl_M__cFsR0k
C;b@R@j::44::4.kRLVCR0sCl_M__6FCR0sCl_M__6FsR0k
C;b@R@ddn:n::Ud4n:nkRLV#RO_FM_R_O#MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVsRHJ__bFsRHJ__bFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bO_D MR_FD_.bO_D MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbD_O __bF.RDbD_O __bFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.b8NVslFC_RbD._s8VN_lCFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVD_.bC_8LF.RDb8_CLR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV.RDbN_PD_H8F.RDbN_PD_H8FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVFMC__FFRC__MFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVb_.Ds_8$F.RbD8_s$R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV8Rs_FM_R_s8MR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVGRs_sCsFFs_R_sGCFsssR_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLVbR#N_sCFbR#N_sCFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#s0N0H_8#R_F#s0N0H_8#R_FNlON_sCsVoDN_
b;b@R@ddn:n::Ud4n:nkRLV0R#N_s0VlsF_oVbNR_F#s0N0s_VFVl_b_oNFORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkV#b0F_#8H_#FR0_Fb8_H#FORNNCl_sDsVNbo_;R
b@n@d::dnUn:d:R4nLRkVIMs__IFRs__MFORNNCl_sDsVNbo_;R
b@n@d:g4U:4(:U.g:j8R#VCVsRO08_8DC_N#00Rk#0_8OD_C8#00Nk0#R8DO_C38\0_8OD_C8#00Nk.#_
RRRR ODRC#bOk_NGFc_RO08_8DC_kOFM80_F;MC
RNH3Ds0_HFsolMNC0R"8DO_C#8_0kN0#
";b@R@ddn:.dd:..:ddc:nRPFsRC#bOk_NGF6_RC#bOk_NGF6_RdkM_koMlC_s#RC0k_M6olMk_#sCC
0;b@R@d4n:U(U::U4U:R4U#V8Vs#CRb_COD_C8sRC8#ObC_8DC_8sCRC#bOC_D8#\3b_COD_C8s_C84bR#COO_DR
......
hdl/spec/syn/test_tdc_pll/syn_tdc_ngdbuild.xrpt
View file @ cb30b5d1
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Jul 15 19:31:20 2011">
<application stringID="NgdBuild" timeStamp="Mon Jul 18 09:44:16 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -80,9 +80,9 @@
<item dataType="int" stringID="NGDBUILD_NUM_DSP48A1" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="23"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="21"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="22"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="72"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFDS" value="1"/>
......@@ -90,16 +90,16 @@
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="32"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1_L" value="31"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="14"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="16"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5_L" value="34"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="27"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="17"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT5_L" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6" value="30"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6_2" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6_L" value="8"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT6_L" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY_L" value="70"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="60"/>
<item dataType="int" stringID="NGDBUILD_NUM_RAMB8BWER" value="1"/>
......
hdl/spec/syn/test_tdc_pll/syn_tdc_usage.xml
View file @ cb30b5d1
......@@ -5,33 +5,33 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="2">
<DesignStatistics TimeStamp="Fri Jul 15 19:32:20 2011"><group name="NetStatistics">
<DesignStatistics TimeStamp="Mon Jul 18 09:45:17 2011"><group name="NetStatistics">
<item name="NumNets_Active" rev="2">
<attrib name="value" value="472"/></item>
<attrib name="value" value="490"/></item>
<item name="NumNets_Gnd" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="2">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_BOUNCEACROSS" rev="2">
<attrib name="value" value="13"/></item>
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Active_BOUNCEIN" rev="2">
<attrib name="value" value="37"/></item>
<attrib name="value" value="39"/></item>
<item name="NumNodesOfType_Active_BUFGOUT" rev="2">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_BUFHINP2OUT" rev="2">
<attrib name="value" value="10"/></item>
<attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="2">
<attrib name="value" value="38"/></item>
<attrib name="value" value="54"/></item>
<item name="NumNodesOfType_Active_CLKPINFEED" rev="2">
<attrib name="value" value="12"/></item>
<attrib name="value" value="14"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="2">
<attrib name="value" value="41"/></item>
<attrib name="value" value="64"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="2">
<attrib name="value" value="230"/></item>
<attrib name="value" value="321"/></item>
<item name="NumNodesOfType_Active_GENERIC" rev="2">
<attrib name="value" value="25"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="2">
<attrib name="value" value="67"/></item>
<attrib name="value" value="78"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="2">
<attrib name="value" value="30"/></item>
<item name="NumNodesOfType_Active_IOBIN2OUT" rev="2">
......@@ -39,35 +39,35 @@
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="2">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Active_LUTINPUT" rev="2">
<attrib name="value" value="567"/></item>
<attrib name="value" value="655"/></item>
<item name="NumNodesOfType_Active_OUTBOUND" rev="2">
<attrib name="value" value="299"/></item>
<attrib name="value" value="319"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="2">
<attrib name="value" value="271"/></item>
<attrib name="value" value="290"/></item>
<item name="NumNodesOfType_Active_PADINPUT" rev="2">
<attrib name="value" value="16"/></item>
<item name="NumNodesOfType_Active_PADOUTPUT" rev="2">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_PINBOUNCE" rev="2">
<attrib name="value" value="104"/></item>
<attrib name="value" value="106"/></item>
<item name="NumNodesOfType_Active_PINFEED" rev="2">
<attrib name="value" value="671"/></item>
<attrib name="value" value="788"/></item>
<item name="NumNodesOfType_Active_PINFEED2" rev="2">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Active_QUAD" rev="2">
<attrib name="value" value="298"/></item>
<attrib name="value" value="371"/></item>
<item name="NumNodesOfType_Active_REGINPUT" rev="2">
<attrib name="value" value="11"/></item>
<item name="NumNodesOfType_Active_SINGLE" rev="2">
<attrib name="value" value="369"/></item>
<attrib name="value" value="407"/></item>
<item name="NumNodesOfType_Gnd_BOUNCEIN" rev="2">
<attrib name="value" value="20"/></item>
<attrib name="value" value="22"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="2">
<attrib name="value" value="19"/></item>
<item name="NumNodesOfType_Gnd_GENERIC" rev="2">
<attrib name="value" value="40"/></item>
<item name="NumNodesOfType_Gnd_HGNDOUT" rev="2">
<attrib name="value" value="7"/></item>
<attrib name="value" value="8"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="2">
<attrib name="value" value="170"/></item>
<item name="NumNodesOfType_Gnd_IOBIN2OUT" rev="2">
......@@ -81,15 +81,15 @@
<item name="NumNodesOfType_Gnd_PADINPUT" rev="2">
<attrib name="value" value="40"/></item>
<item name="NumNodesOfType_Gnd_PINBOUNCE" rev="2">
<attrib name="value" value="45"/></item>
<attrib name="value" value="43"/></item>
<item name="NumNodesOfType_Gnd_PINFEED" rev="2">
<attrib name="value" value="191"/></item>
<attrib name="value" value="194"/></item>
<item name="NumNodesOfType_Gnd_SINGLE" rev="2">
<attrib name="value" value="24"/></item>
<item name="NumNodesOfType_Vcc_GENERIC" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_HVCCOUT" rev="2">
<attrib name="value" value="29"/></item>
<attrib name="value" value="31"/></item>
<item name="NumNodesOfType_Vcc_INPUT" rev="2">
<attrib name="value" value="17"/></item>
<item name="NumNodesOfType_Vcc_IOBIN2OUT" rev="2">
......@@ -99,13 +99,13 @@
<item name="NumNodesOfType_Vcc_KVCCOUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_LUTINPUT" rev="2">
<attrib name="value" value="67"/></item>
<attrib name="value" value="69"/></item>
<item name="NumNodesOfType_Vcc_PADINPUT" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_PINBOUNCE" rev="2">
<attrib name="value" value="5"/></item>
<item name="NumNodesOfType_Vcc_PINFEED" rev="2">
<attrib name="value" value="85"/></item>
<attrib name="value" value="87"/></item>
<item name="NumNodesOfType_Vcc_REGINPUT" rev="2">
<attrib name="value" value="1"/></item>
</group>
......@@ -117,9 +117,9 @@
<item name="IOB-IOBS" rev="2">
<attrib name="value" value="66"/></item>
<item name="SLICEL-SLICEM" rev="2">
<attrib name="value" value="16"/></item>
<attrib name="value" value="10"/></item>
<item name="SLICEX-SLICEL" rev="2">
<attrib name="value" value="9"/></item>
<attrib name="value" value="17"/></item>
<item name="SLICEX-SLICEM" rev="2">
<attrib name="value" value="5"/></item>
</group>
......@@ -131,17 +131,17 @@
<item name="AGG_LOCED_IO" rev="1">
<attrib name="value" value="134"/></item>
<item name="AGG_SLICE" rev="1">
<attrib name="value" value="63"/></item>
<attrib name="value" value="80"/></item>
<item name="NUM_BONDED_IOB" rev="1">
<attrib name="value" value="135"/></item>
<item name="NUM_BSFULL" rev="1">
<attrib name="value" value="84"/></item>
<item name="NUM_BSLUTONLY" rev="1">
<attrib name="value" value="93"/></item>
<attrib name="value" value="109"/></item>
<item name="NUM_BSREGONLY" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_BSUSED" rev="1">
<attrib name="value" value="179"/></item>
<attrib name="value" value="195"/></item>
<item name="NUM_BUFG" rev="1">
<attrib name="value" value="2"/></item>
<item name="NUM_DSP48A1" rev="1">
......@@ -151,11 +151,11 @@
<item name="NUM_LOCED_IOB" rev="1">
<attrib name="value" value="134"/></item>
<item name="NUM_LOGIC_O5ANDO6" rev="1">
<attrib name="value" value="38"/></item>
<attrib name="value" value="40"/></item>
<item name="NUM_LOGIC_O5ONLY" rev="1">
<attrib name="value" value="30"/></item>
<attrib name="value" value="31"/></item>
<item name="NUM_LOGIC_O6ONLY" rev="1">
<attrib name="value" value="108"/></item>
<attrib name="value" value="121"/></item>
<item name="NUM_LUT_RT_DRIVES_CARRY4" rev="1">
<attrib name="value" value="1"/></item>
<item name="NUM_LUT_RT_EXO6" rev="1">
......@@ -169,22 +169,22 @@
<item name="NUM_SLICEL" rev="1">
<attrib name="value" value="19"/></item>
<item name="NUM_SLICEX" rev="1">
<attrib name="value" value="44"/></item>
<attrib name="value" value="61"/></item>
<item name="NUM_SLICE_CARRY4" rev="1">
<attrib name="value" value="19"/></item>
<item name="NUM_SLICE_CONTROLSET" rev="1">
<attrib name="value" value="6"/></item>
<item name="NUM_SLICE_CYINIT" rev="1">
<attrib name="value" value="248"/></item>
<attrib name="value" value="266"/></item>
<item name="NUM_SLICE_FF" rev="1">
<attrib name="value" value="86"/></item>
<item name="NUM_SLICE_UNUSEDCTRL" rev="1">
<attrib name="value" value="32"/></item>
<attrib name="value" value="33"/></item>
<item name="NUM_UNUSABLE_FF_BELS" rev="1">
<attrib name="value" value="18"/></item>
</group>
</DesignStatistics>
<DeviceUsage TimeStamp="Fri Jul 15 19:32:20 2011"><group name="SiteSummary">
<DeviceUsage TimeStamp="Mon Jul 18 09:45:17 2011"><group name="SiteSummary">
<item name="BUFG" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="BUFG_BUFG" rev="2">
......@@ -208,9 +208,9 @@
<item name="IOB_OUTBUF" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="60"/></item>
<item name="LUT5" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="68"/></item>
<attrib name="total" value="1000000"/><attrib name="used" value="71"/></item>
<item name="LUT6" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="177"/></item>
<attrib name="total" value="1000000"/><attrib name="used" value="192"/></item>
<item name="NULLMUX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="OLOGIC2" rev="2">
......@@ -228,10 +228,10 @@
<item name="SLICEL" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="SLICEX" rev="2">
<attrib name="total" value="1000000"/><attrib name="used" value="44"/></item>
<attrib name="total" value="1000000"/><attrib name="used" value="61"/></item>
</group>
</DeviceUsage>
<ReportConfigData TimeStamp="Fri Jul 15 19:32:20 2011"><group name="DSP48A1">
<ReportConfigData TimeStamp="Mon Jul 18 09:45:17 2011"><group name="DSP48A1">
<item name="CEA" rev="2">
<attrib name="CEA_INV" value="0"/><attrib name="CEA" value="1"/></item>
<item name="CEB" rev="2">
......@@ -355,7 +355,7 @@
</group>
<group name="SLICEX">
<item name="CLK" rev="2">
<attrib name="CLK" value="23"/><attrib name="CLK_INV" value="0"/></item>
<attrib name="CLK" value="39"/><attrib name="CLK_INV" value="0"/></item>
</group>
<group name="OLOGIC2">
<item name="CLK0" rev="2">
......@@ -393,7 +393,7 @@
<item name="OUTFFTYPE" rev="2">
<attrib name="FF" value="6"/></item>
<item name="SRINIT_OQ" rev="2">
<attrib name="0" value="6"/></item>
<attrib name="0" value="5"/><attrib name="1" value="1"/></item>
<item name="SRTYPE_OQ" rev="2">
<attrib name="SYNC" value="4"/></item>
</group>
......@@ -456,7 +456,7 @@
<attrib name="WRITE_FIRST" value="1"/></item>
</group>
</ReportConfigData>
<ReportPinData TimeStamp="Fri Jul 15 19:32:20 2011"><group name="DSP48A1">
<ReportPinData TimeStamp="Mon Jul 18 09:45:17 2011"><group name="DSP48A1">
<item name="A0" rev="2">
<attrib name="value" value="1"/></item>
<item name="A1" rev="2">
......@@ -1159,14 +1159,18 @@
<attrib name="value" value="8"/></item>
<item name="CX" rev="2">
<attrib name="value" value="2"/></item>
<item name="D2" rev="2">
<attrib name="value" value="1"/></item>
<item name="D3" rev="2">
<attrib name="value" value="1"/></item>
<item name="D4" rev="2">
<attrib name="value" value="9"/></item>
<attrib name="value" value="10"/></item>
<item name="D5" rev="2">
<attrib name="value" value="9"/></item>
<attrib name="value" value="10"/></item>
<item name="D6" rev="2">
<attrib name="value" value="16"/></item>
<item name="DMUX" rev="2">
<attrib name="value" value="9"/></item>
<attrib name="value" value="10"/></item>
<item name="DQ" rev="2">
<attrib name="value" value="8"/></item>
<item name="DX" rev="2">
......@@ -1182,83 +1186,87 @@
</group>
<group name="SLICEX">
<item name="A" rev="2">
<attrib name="value" value="18"/></item>
<attrib name="value" value="20"/></item>
<item name="A1" rev="2">
<attrib name="value" value="11"/></item>
<attrib name="value" value="17"/></item>
<item name="A2" rev="2">
<attrib name="value" value="21"/></item>
<attrib name="value" value="20"/></item>
<item name="A3" rev="2">
<attrib name="value" value="26"/></item>
<attrib name="value" value="22"/></item>
<item name="A4" rev="2">
<attrib name="value" value="29"/></item>
<attrib name="value" value="23"/></item>
<item name="A5" rev="2">
<attrib name="value" value="32"/></item>
<attrib name="value" value="31"/></item>
<item name="A6" rev="2">
<attrib name="value" value="33"/></item>
<attrib name="value" value="32"/></item>
<item name="AMUX" rev="2">
<attrib name="value" value="2"/></item>
<attrib name="value" value="3"/></item>
<item name="AQ" rev="2">
<attrib name="value" value="16"/></item>
<attrib name="value" value="14"/></item>
<item name="AX" rev="2">
<attrib name="value" value="1"/></item>
<item name="B" rev="2">
<attrib name="value" value="18"/></item>
<attrib name="value" value="15"/></item>
<item name="B1" rev="2">
<attrib name="value" value="13"/></item>
<attrib name="value" value="17"/></item>
<item name="B2" rev="2">
<attrib name="value" value="23"/></item>
<attrib name="value" value="18"/></item>
<item name="B3" rev="2">
<attrib name="value" value="24"/></item>
<attrib name="value" value="20"/></item>
<item name="B4" rev="2">
<attrib name="value" value="25"/></item>
<attrib name="value" value="21"/></item>
<item name="B5" rev="2">
<attrib name="value" value="27"/></item>
<attrib name="value" value="25"/></item>
<item name="B6" rev="2">
<attrib name="value" value="28"/></item>
<attrib name="value" value="26"/></item>
<item name="BMUX" rev="2">
<attrib name="value" value="3"/></item>
<attrib name="value" value="1"/></item>
<item name="BQ" rev="2">
<attrib name="value" value="11"/></item>
<attrib name="value" value="12"/></item>
<item name="C" rev="2">
<attrib name="value" value="8"/></item>
<attrib name="value" value="17"/></item>
<item name="C1" rev="2">
<attrib name="value" value="8"/></item>
<attrib name="value" value="26"/></item>
<item name="C2" rev="2">
<attrib name="value" value="16"/></item>
<attrib name="value" value="26"/></item>
<item name="C3" rev="2">
<attrib name="value" value="17"/></item>
<attrib name="value" value="28"/></item>
<item name="C4" rev="2">
<attrib name="value" value="18"/></item>
<attrib name="value" value="29"/></item>
<item name="C5" rev="2">
<attrib name="value" value="19"/></item>
<attrib name="value" value="30"/></item>
<item name="C6" rev="2">
<attrib name="value" value="20"/></item>
<attrib name="value" value="32"/></item>
<item name="CE" rev="2">
<attrib name="value" value="9"/></item>
<attrib name="value" value="20"/></item>
<item name="CLK" rev="2">
<attrib name="value" value="23"/></item>
<attrib name="value" value="39"/></item>
<item name="CMUX" rev="2">
<attrib name="value" value="2"/></item>
<attrib name="value" value="4"/></item>
<item name="CQ" rev="2">
<attrib name="value" value="13"/></item>
<attrib name="value" value="17"/></item>
<item name="D" rev="2">
<attrib name="value" value="13"/></item>
<attrib name="value" value="20"/></item>
<item name="D1" rev="2">
<attrib name="value" value="6"/></item>
<attrib name="value" value="15"/></item>
<item name="D2" rev="2">
<attrib name="value" value="14"/></item>
<attrib name="value" value="17"/></item>
<item name="D3" rev="2">
<attrib name="value" value="15"/></item>
<attrib name="value" value="19"/></item>
<item name="D4" rev="2">
<attrib name="value" value="16"/></item>
<attrib name="value" value="20"/></item>
<item name="D5" rev="2">
<attrib name="value" value="18"/></item>
<attrib name="value" value="25"/></item>
<item name="D6" rev="2">
<attrib name="value" value="22"/></item>
<attrib name="value" value="28"/></item>
<item name="DMUX" rev="2">
<attrib name="value" value="1"/></item>
<item name="DQ" rev="2">
<attrib name="value" value="12"/></item>
<attrib name="value" value="9"/></item>
<item name="DX" rev="2">
<attrib name="value" value="2"/></item>
<attrib name="value" value="1"/></item>
<item name="SR" rev="2">
<attrib name="value" value="18"/></item>
<attrib name="value" value="30"/></item>
</group>
<group name="BUFG_BUFG">
<item name="I0" rev="2">
......@@ -1522,33 +1530,33 @@
</group>
<group name="LUT5">
<item name="A1" rev="2">
<attrib name="value" value="2"/></item>
<attrib name="value" value="4"/></item>
<item name="A2" rev="2">
<attrib name="value" value="3"/></item>
<attrib name="value" value="7"/></item>
<item name="A3" rev="2">
<attrib name="value" value="6"/></item>
<attrib name="value" value="8"/></item>
<item name="A4" rev="2">
<attrib name="value" value="6"/></item>
<attrib name="value" value="8"/></item>
<item name="A5" rev="2">
<attrib name="value" value="5"/></item>
<item name="O5" rev="2">
<attrib name="value" value="68"/></item>
<attrib name="value" value="71"/></item>
</group>
<group name="LUT6">
<item name="A1" rev="2">
<attrib name="value" value="38"/></item>
<item name="A2" rev="2">
<attrib name="value" value="73"/></item>
<item name="A2" rev="2">
<attrib name="value" value="77"/></item>
<item name="A3" rev="2">
<attrib name="value" value="81"/></item>
<attrib name="value" value="87"/></item>
<item name="A4" rev="2">
<attrib name="value" value="127"/></item>
<attrib name="value" value="132"/></item>
<item name="A5" rev="2">
<attrib name="value" value="137"/></item>
<attrib name="value" value="152"/></item>
<item name="A6" rev="2">
<attrib name="value" value="176"/></item>
<attrib name="value" value="191"/></item>
<item name="O6" rev="2">
<attrib name="value" value="177"/></item>
<attrib name="value" value="192"/></item>
</group>
<group name="IOB_IMUX">
<item name="I" rev="2">
......
hdl/spec/syn/test_tdc_pll/syntmp/fifo_32x512.ngc deleted 100644 → 0
View file @ b5ae1362
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
hdl/spec/syn/test_tdc_pll/syntmp/fifo_64x512.ngc deleted 100644 → 0
View file @ b5ae1362
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hdl/spec/syn/test_tdc_pll/syntmp/multadd.tlg deleted 100644 → 0
View file @ b5ae1362
Selecting top level module DSP48A1
@N: CG364 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4561:7:4561:13|Synthesizing module DSP48A1
@W: CG532 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4689:4:4689:10|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4730:12:4730:19|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4731:12:4731:18|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4741:26:4741:33|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4742:26:4742:32|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4886:19:4886:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4887:19:4887:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4924:19:4924:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4925:19:4925:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4965:19:4965:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4966:19:4966:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5008:19:5008:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5009:19:5009:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5048:19:5048:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5049:19:5049:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5088:19:5088:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5089:19:5089:25|System task $finish is not supported yet
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5105:19:5105:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5106:19:5106:25|System task $finish is not supported yet
@W: CG296 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5114:13:5114:87|Incomplete sensitivity list - assuming completeness
@W: CG290 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5118:12:5118:19|Referenced variable add_flag is not in sensitivity list
@N: CG793 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5160:19:5160:26|Ignoring System task $display
@N: CG512 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5161:19:5161:25|System task $finish is not supported yet
@W: CG133 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4650:18:4650:24|No assignment to b_o_mux
@W: CG133 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4667:8:4667:21|No assignment to invalid_opmode
@W: CG360 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4673:22:4673:28|No assignment to wire bcin_in
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5071:4:5071:9|Pruning Register qopmode_o_reg1[7:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5029:4:5029:9|Pruning Register qcarryin_o_reg1
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":5029:4:5029:9|Pruning Register qcarryout_o_reg1
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4949:4:4949:9|Pruning Register qmult_o_reg1[35:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4908:4:4908:9|Pruning Register qd_o_reg1[17:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4870:4:4870:9|Pruning Register qc_o_reg1[47:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4807:4:4807:9|Pruning Register qb_o_reg1[17:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4807:4:4807:9|Pruning Register qb_o_reg2[17:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4766:4:4766:9|Pruning Register qa_o_reg1[17:0]
@W: CL169 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4766:4:4766:9|Pruning Register qa_o_reg2[17:0]
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4589:10:4589:16|Input CARRYIN is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4590:10:4590:12|Input CEA is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4591:10:4591:12|Input CEB is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4592:10:4592:12|Input CEC is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4593:10:4593:18|Input CECARRYIN is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4594:10:4594:12|Input CED is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4595:10:4595:12|Input CEM is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4596:10:4596:17|Input CEOPMODE is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4602:10:4602:13|Input RSTA is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4603:10:4603:13|Input RSTB is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4604:10:4604:13|Input RSTC is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4605:10:4605:19|Input RSTCARRYIN is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4606:10:4606:13|Input RSTD is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4607:10:4607:13|Input RSTM is unused
@W: CL159 :"/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syntmp/multadd.v":4608:10:4608:18|Input RSTOPMODE is unused
hdl/spec/syn/test_tdc_pll/syntmp/sap.log deleted 100644 → 0
View file @ b5ae1362
Synopsys Xilinx Technology Mapper, Version map510rc, Build 068R, Built Feb 22 2010 15:14:03
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
Product Version D-2010.03
Reading constraint file: /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc
Adding property syn_input_delay1, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
Adding property syn_output_delay2, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=tdc_clk125:r" to view:work.top_tdc(rtl)
Adding property syn_useioff, value 1 to view:work.top_tdc(rtl)
Adding property syn_noarrayports, value 1 to view:work.top_tdc(rtl)
Adding property syn_netlist_hierarchy, value 0 to view:work.top_tdc(rtl)
@N: MF249 |Running in 64-bit mode.
@N: MF257 |Gated clock conversion enabled
Adding property syn_pad_type, value "LVCMOS_25", to instance spec_led_green_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_cs_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sdi_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance pll_sclk_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig1_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance tdc_led_trig5_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_1_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_2_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_3_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_4_o
Adding property syn_pad_type, value "LVCMOS_25", to instance term_en_5_o
Adding property syn_pad_type, value "LVCMOS_25", to instance cs_n_o
Adding property syn_pad_type, value "LVCMOS_25", to instance irq_p_o
Adding property syn_pad_type, value "SSTL_18_Class_II", to instance l2p_clk_n_o
Adding property syn_pad_type, value "SSTL_18_Class_II", to instance l2p_clk_p_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_dframe_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_edb_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to instance l2p_valid_o
Adding property syn_pad_type, value "LVCMOS_25", to instance oe_n_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to instance p2l_rdy_o
Adding property syn_pad_type, value "LVCMOS_25", to instance rd_n_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to instance rx_error_o
Adding property syn_pad_type, value "LVCMOS_25", to instance spare_o
Adding property syn_pad_type, value "LVCMOS_25", to instance start_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to instance start_from_fpga_o
Adding property syn_pad_type, value "LVCMOS_25", to instance stop_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to instance wr_n_o
Adding property syn_pad_type, value "LVCMOS18", to instance spec_aux5_o
Adding property syn_loc, value "N20", to port rst_n_a_i
Adding property syn_pad_type, value "LVCMOS18", to port rst_n_a_i
Adding property syn_loc, value "M20", to port p2l_clk_p_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_p_i
Adding property syn_loc, value "M19", to port p2l_clk_n_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port p2l_clk_n_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_data_i[15:0]
Adding property syn_loc, value "J22", to port p2l_dframe_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_dframe_i
Adding property syn_loc, value "L19", to port p2l_valid_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_valid_i
Adding property syn_loc, value "J16", to port p2l_rdy_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p2l_rdy_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_req_i[1:0]
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_wr_rdy_o[1:0]
Adding property syn_loc, value "J17", to port rx_error_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port rx_error_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port vc_rdy_i[1:0]
Adding property syn_loc, value "K21", to port l2p_clk_p_o
Adding property syn_pad_type, value "SSTL_18_Class_II", to port l2p_clk_p_o
Adding property syn_loc, value "K22", to port l2p_clk_n_o
Adding property syn_pad_type, value "SSTL_18_Class_II", to port l2p_clk_n_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_data_o[15:0]
Adding property syn_loc, value "U22", to port l2p_dframe_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_dframe_o
Adding property syn_loc, value "T18", to port l2p_valid_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_valid_o
Adding property syn_loc, value "U20", to port l2p_edb_o
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_edb_o
Adding property syn_loc, value "U19", to port l2p_rdy_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l2p_rdy_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port l_wr_rdy_i[1:0]
Adding property syn_pad_type, value "SSTL_18_Class_I", to port p_rd_d_rdy_i[1:0]
Adding property syn_loc, value "M17", to port tx_error_i
Adding property syn_pad_type, value "SSTL_18_Class_I", to port tx_error_i
Adding property syn_loc, value "U16", to port irq_p_o
Adding property syn_pad_type, value "LVCMOS_25", to port irq_p_o
Adding property syn_loc, value "AB19", to port spare_o
Adding property syn_pad_type, value "LVCMOS_25", to port spare_o
Adding property syn_loc, value "E16", to port acam_refclk_i
Adding property syn_pad_type, value "LVCMOS_25", to port acam_refclk_i
Adding property syn_input_delay8, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_ld_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_ld_i
Adding property syn_loc, value "C18", to port pll_ld_i
Adding property syn_input_delay9, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_refmon_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_refmon_i
Adding property syn_loc, value "D17", to port pll_refmon_i
Adding property syn_input_delay10, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdo_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdo_i
Adding property syn_loc, value "AB18", to port pll_sdo_i
Adding property syn_input_delay11, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_status_i
Adding property syn_pad_type, value "LVCMOS_25", to port pll_status_i
Adding property syn_loc, value "Y18", to port pll_status_i
Adding property syn_loc, value "L20", to port tdc_clk_p_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_p_i
Adding property syn_loc, value "L22", to port tdc_clk_n_i
Adding property syn_pad_type, value "DIFF_SSTL_18_Class_II", to port tdc_clk_n_i
Adding property syn_output_delay6, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_cs_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_cs_o
Adding property syn_loc, value "Y17", to port pll_cs_o
Adding property syn_loc, value "AB16", to port pll_dac_sync_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_dac_sync_o
Adding property syn_output_delay5, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sdi_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sdi_o
Adding property syn_loc, value "AA18", to port pll_sdi_o
Adding property syn_output_delay7, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port pll_sclk_o
Adding property syn_pad_type, value "LVCMOS_25", to port pll_sclk_o
Adding property syn_loc, value "AB17", to port pll_sclk_o
Adding property syn_loc, value "V11", to port err_flag_i
Adding property syn_pad_type, value "LVCMOS_25", to port err_flag_i
Adding property syn_loc, value "W11", to port int_flag_i
Adding property syn_pad_type, value "LVCMOS_25", to port int_flag_i
Adding property syn_loc, value "T15", to port start_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port start_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port start_from_fpga_o
Adding property syn_loc, value "U15", to port stop_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port stop_dis_o
Adding property syn_pad_type, value "LVCMOS_25", to port data_bus_io[27:0]
Adding property syn_loc, value "W12", to port ef1_i
Adding property syn_pad_type, value "LVCMOS_25", to port ef1_i
Adding property syn_loc, value "R11", to port ef2_i
Adding property syn_pad_type, value "LVCMOS_25", to port ef2_i
Adding property syn_loc, value "Y12", to port lf1_i
Adding property syn_pad_type, value "LVCMOS_25", to port lf1_i
Adding property syn_loc, value "T11", to port lf2_i
Adding property syn_pad_type, value "LVCMOS_25", to port lf2_i
Adding property syn_pad_type, value "LVCMOS_25", to port address_o[3:0]
Adding property syn_loc, value "T14", to port cs_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port cs_n_o
Adding property syn_loc, value "V13", to port oe_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port oe_n_o
Adding property syn_loc, value "AB13", to port rd_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port rd_n_o
Adding property syn_loc, value "Y13", to port wr_n_o
Adding property syn_pad_type, value "LVCMOS_25", to port wr_n_o
Adding property syn_loc, value "C19", to port mute_inputs_o
Adding property syn_pad_type, value "LVCMOS_25", to port mute_inputs_o
Adding property syn_loc, value "W13", to port tdc_led_status_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_status_o
Adding property syn_loc, value "W14", to port tdc_led_trig1_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig1_o
Adding property syn_loc, value "Y14", to port tdc_led_trig2_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig2_o
Adding property syn_loc, value "Y16", to port tdc_led_trig3_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig3_o
Adding property syn_loc, value "W15", to port tdc_led_trig4_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig4_o
Adding property syn_loc, value "V17", to port tdc_led_trig5_o
Adding property syn_pad_type, value "LVCMOS_25", to port tdc_led_trig5_o
Adding property syn_loc, value "W18", to port term_en_1_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_1_o
Adding property syn_loc, value "B20", to port term_en_2_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_2_o
Adding property syn_loc, value "A20", to port term_en_3_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_3_o
Adding property syn_loc, value "H10", to port term_en_4_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_4_o
Adding property syn_loc, value "E6", to port term_en_5_o
Adding property syn_pad_type, value "LVCMOS_25", to port term_en_5_o
Adding property syn_loc, value "C22", to port spec_aux0_i
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux0_i
Adding property syn_loc, value "D21", to port spec_aux1_i
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux1_i
Adding property syn_loc, value "G19", to port spec_aux2_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux2_o
Adding property syn_loc, value "F20", to port spec_aux3_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux3_o
Adding property syn_loc, value "F18", to port spec_aux4_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux4_o
Adding property syn_loc, value "C20", to port spec_aux5_o
Adding property syn_pad_type, value "LVCMOS18", to port spec_aux5_o
Adding property syn_output_delay3, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port spec_led_green_o
Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_green_o
Adding property syn_loc, value "E5", to port spec_led_green_o
Adding property syn_output_delay4, value "r=2.00,f=2.00,rs=0.0,fs=0.0,improve=0,route=0,ref=spec_clk20:r", to port spec_led_red_o
Adding property syn_pad_type, value "LVCMOS_25", to port spec_led_red_o
Adding property syn_loc, value "D5", to port spec_led_red_o
Adding property syn_loc, value "H12", to port spec_clk_i
Adding property syn_pad_type, value "LVCMOS_25", to port spec_clk_i
Adding property syn_keep, value "true", to net spec_clk
Reading Xilinx I/O pad type table from file </afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/x_io_tbl.txt>
Reading Xilinx Rocket I/O parameter type table from file </afs/cern.ch/project/parc/elec/synplify/D-2010.03/lib/xilinx/gttype.txt>
@N|Running in logic synthesis mode without enhanced optimization
@N: MF284 |Setting synthesis effort to very_low for the design
@N: BN225 |Writing default property annotation file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/syn_tdc.sap.
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 15 19:30:53 2011
###########################################################]
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@P: Worst Slack : -2.997
@P: spec_clk20 - Estimated Frequency : 104.2 MHz
@P: spec_clk20 - Requested Frequency : 20.0 MHz
@P: spec_clk20 - Estimated Period : 9.592
@P: spec_clk20 - Requested Period : 50.000
@P: spec_clk20 - Slack : 40.408
@P: tdc_clk125 - Estimated Frequency : 90.9 MHz
@P: tdc_clk125 - Requested Frequency : 125.0 MHz
@P: tdc_clk125 - Estimated Period : 10.997
@P: tdc_clk125 - Requested Period : 8.000
@P: tdc_clk125 - Slack : -2.997
@P: top_tdc|spec_clk_i - Estimated Frequency : 167.5 MHz
@P: top_tdc|spec_clk_i - Requested Frequency : 200.0 MHz
@P: top_tdc|spec_clk_i - Estimated Period : 5.971
@P: top_tdc|spec_clk_i - Requested Period : 5.000
@P: top_tdc|spec_clk_i - Slack : -0.971
@P: top_tdc Part : xc6slx45tfgg484-2
@P: top_tdc I/O primitives : 66
@P: top_tdc I/O Register bits : 6
@P: top_tdc Register bits (Non I/O) : 86 (0%)
@P: top_tdc Block Rams : 1 of 116 (0%)
@P: top_tdc Total Luts : 178 (0%)
@P: CPU Time : 0h:00m:03s
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<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap class="content" valign="top">
<body bgcolor="#e0e0ff">
<font size=3><b>Log File Links:</b><br></font>
<br><b>test_tdc_pll</b><br>
<dt><a href="/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/rpt_top_tdc.areasrr:@XP_FILE" target="srrFrame">Hierarchical Area Report (/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/test_tdc_pll/rpt_top_tdc)</a> (19:30 15-Jul)</dt><br>
<br><br><a href="/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/stdout.log:@XP_FILE" target="srrFrame">Session Log</a><br>
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This source diff could not be displayed because it is too large. You can view the blob instead.
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<table border="0" cellpadding="0" cellspacing="2">
<tr>
<td nowrap class="content" valign="top">
<body bgcolor="#e0e0ff">
<dl>
<font size=3><b>test_tdc_pll (syn_tdc)</b><br></font>
<b><a href="syn_tdc_srr.htm#compilerReport512" target="srrFrame">Compiler Report</a></b><br>
<b><a href="syn_tdc_srr.htm#mapperReport513" target="srrFrame">Mapper Report</a></b><br>
<b><a href="syn_tdc_srr.htm#timingReport514" target="srrFrame">Timing Report</a></b><br>
<a href="syn_tdc_srr.htm#performanceSummary515" target="srrFrame">Performance Summary</a><br>
<a href="syn_tdc_srr.htm#clockRelationships516" target="srrFrame">Clock Relationships</a><br>
<a href="syn_tdc_srr.htm#interfaceInfo517" target="srrFrame">Interface Information</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#inputPorts518" target="srrFrame">Input Ports</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#outputPorts519" target="srrFrame">Output Ports</a><br>
<a href="syn_tdc_srr.htm#clockReport520" target="srrFrame">Detailed Report for Clock: spec_clk20</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#startingSlack521" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#endingSlack522" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#worstPaths523" target="srrFrame">Worst Path Information</a><br>
<a href="syn_tdc_srr.htm#clockReport524" target="srrFrame">Detailed Report for Clock: tdc_clk125</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#startingSlack525" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#endingSlack526" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#worstPaths527" target="srrFrame">Worst Path Information</a><br>
<a href="syn_tdc_srr.htm#clockReport528" target="srrFrame">Detailed Report for Clock: top_tdc|spec_clk_i</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#startingSlack529" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#endingSlack530" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#worstPaths531" target="srrFrame">Worst Path Information</a><br>
<a href="syn_tdc_srr.htm#clockReport532" target="srrFrame">Detailed Report for Clock: System</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#startingSlack533" target="srrFrame">Starting Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#endingSlack534" target="srrFrame">Ending Points with Worst Slack</a><br>
&nbsp;&nbsp;&nbsp;<a href="syn_tdc_srr.htm#worstPaths535" target="srrFrame">Worst Path Information</a><br>
<b><a href="syn_tdc_srr.htm#resourceUsage536" target="srrFrame">Resource Utilization</a></b><br>
hdl/spec/syn/test_tdc_pll/tdc.bgn
View file @ cb30b5d1
......@@ -4,7 +4,7 @@ Loading device for application Rf_Device from file '6slx45t.nph' in environment
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/.
"top_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -2
Fri Jul 15 19:32:12 2011
Mon Jul 18 09:45:10 2011
/afs/cern.ch/project/parc/elec/xilinx131/ISE_DS/ISE/bin/lin64/unwrapped/bitgen par_tdc.ncd tdc
......
hdl/spec/syn/test_tdc_pll/tdc.drc
View file @ cb30b5d1
Release 13.1 Drc O.40d (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Fri Jul 15 19:32:12 2011
Mon Jul 18 09:45:10 2011
drc -z par_tdc.ncd
......
hdl/spec/syn/test_tdc_pll/top_tdc_map.xrpt
View file @ cb30b5d1
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Fri Jul 15 19:31:39 2011">
<application stringID="Map" timeStamp="Mon Jul 18 09:44:36 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -74,10 +74,10 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="177">
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="193">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="30"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="108"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="38"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="122"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="40"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -120,9 +120,9 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="69"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="620916"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="17 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="16 secs "/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="621108"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="18 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="17 secs "/>
</section>
<section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="54576" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="86">
......@@ -131,10 +131,10 @@
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="177">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="30"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="108"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="38"/>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTs" stringID="MAP_SLICE_LUTS" value="193">
<item dataType="int" label="Number using O5 output only" stringID="MAP_NUM_LOGIC_O5ONLY" value="31"/>
<item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="121"/>
<item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="40"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
......@@ -154,13 +154,13 @@
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
<item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="6822" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="63">
<item AVAILABLE="6822" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="80">
<item AVAILABLE="1809" dataType="int" stringID="MAP_NUM_SLICEL" value="19"/>
<item AVAILABLE="1602" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
<item AVAILABLE="3411" dataType="int" stringID="MAP_NUM_SLICEX" value="44"/>
<item AVAILABLE="3411" dataType="int" stringID="MAP_NUM_SLICEX" value="61"/>
</item>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="179">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="93"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="195">
<item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="109"/>
<item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="2"/>
<item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="84"/>
</item>
......@@ -905,7 +905,6 @@
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS18"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
</row>
<row stringID="row" value="110">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="spec_aux3_o"/>
......@@ -922,6 +921,7 @@
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS18"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="Reg&#xA;(s)" stringID="REGS" value="OFF"/>
</row>
<row stringID="row" value="112">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="spec_aux5_o"/>
......@@ -1131,7 +1131,7 @@
<node stringID="MAP_CLOCK_SIGNAL" value="clk">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="11"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="35"/>
<node stringID="MAP_RESET_SIGNAL" value="N_51_i">
<node stringID="MAP_RESET_SIGNAL" value="N_39_i">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="8"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="32"/>
</node>
......@@ -1139,19 +1139,19 @@
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="2"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="2"/>
</node>
<node stringID="MAP_RESET_SIGNAL" value="pll_sclk_i">
<node stringID="MAP_RESET_SIGNAL" value="pll_sclk_o_c_i">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="1"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="1"/>
</node>
</node>
<node stringID="MAP_CLOCK_SIGNAL" value="spec_clk">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="20"/>
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="36"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="51"/>
<node stringID="MAP_RESET_SIGNAL" value="N_132_i_iso">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="15"/>
<node stringID="MAP_RESET_SIGNAL" value="N_188_i_iso">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="27"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="40"/>
<node stringID="MAP_ENABLE_SIGNAL" value="N_10_i">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="9"/>
<node stringID="MAP_ENABLE_SIGNAL" value="N_18_i">
<item dataType="int" label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT" value="20"/>
<item dataType="int" label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT" value="32"/>
</node>
</node>
......@@ -1174,9 +1174,9 @@
<property label="PLL_ADV" stringID="MAP_PLL_ADV"/>
<node label="Module Name" stringID="MAP_MODULE" value="top_tdc">
<item label="Partition" stringID="MAP_PARTITION" value=""/>
<item ACCUMULATED="63" dataType="int" label="Slices" stringID="MAP_SLICES" value="63"/>
<item ACCUMULATED="80" dataType="int" label="Slices" stringID="MAP_SLICES" value="80"/>
<item ACCUMULATED="86" dataType="int" label="Slice Reg" stringID="MAP_SLICE_REG" value="86"/>
<item ACCUMULATED="146" dataType="int" label="LUTs" stringID="MAP_LUTS" value="146"/>
<item ACCUMULATED="162" dataType="int" label="LUTs" stringID="MAP_LUTS" value="162"/>
<item ACCUMULATED="0" dataType="int" label="LUTRAM" stringID="MAP_LUTRAM" value="0"/>
<item ACCUMULATED="1" dataType="int" label="BRAM/FIFO" stringID="MAP_BRAM_FIFO" value="1"/>
<item ACCUMULATED="1" dataType="int" label="DSP48A1" stringID="MAP_DSP48A1" value="1"/>
......
hdl/spec/syn/test_tdc_pll/top_tdc_par.xrpt
View file @ cb30b5d1
......@@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Fri Jul 15 19:31:46 2011">
<application stringID="par" timeStamp="Mon Jul 18 09:44:43 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -71,8 +71,8 @@
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="20 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="20 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="17366.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="22 secs "/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="19904.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="21 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="21 secs "/>
</section>
</task>
......@@ -92,8 +92,8 @@
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y3"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="26.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.659000"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="42.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.669000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.387000"/>
</row>
<row stringID="row" value="2">
......@@ -102,7 +102,7 @@
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X3Y7"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="13.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.667000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.659000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="2.382000"/>
</row>
</table>
......@@ -1349,7 +1349,7 @@
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="173">
......@@ -1520,7 +1520,7 @@
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="1"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="YES"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row>
<row stringID="row" value="196">
......@@ -3900,7 +3900,7 @@
</task>
</application>
<application stringID="Par" timeStamp="Fri Jul 15 19:31:46 2011">
<application stringID="Par" timeStamp="Mon Jul 18 09:44:44 2011">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
......@@ -3964,10 +3964,10 @@
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHTHRU" value="0"/>
<item dataType="int" stringID="PAR_NUM_SLICE_LATCHLOGIC" value="0"/>
</item>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="177">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="30"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="108"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="38"/>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTS" stringID="PAR_SLICE_LUTS" value="193">
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ONLY" value="31"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O6ONLY" value="121"/>
<item dataType="int" stringID="PAR_NUM_LOGIC_O5ANDO6" value="40"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O6ONLY" value="0"/>
<item dataType="int" stringID="PAR_NUM_ROM_O5ANDO6" value="0"/>
......@@ -3987,13 +3987,13 @@
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_CARRY4" value="1"/>
<item dataType="int" stringID="PAR_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
</item>
<item AVAILABLE="6822" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="63">
<item AVAILABLE="6822" dataType="int" stringID="PAR_OCCUPIED_SLICES" value="80">
<item AVAILABLE="1809" dataType="int" stringID="PAR_NUM_SLICEL" value="19"/>
<item AVAILABLE="1602" dataType="int" stringID="PAR_NUM_SLICEM" value="0"/>
<item AVAILABLE="3411" dataType="int" stringID="PAR_NUM_SLICEX" value="44"/>
<item AVAILABLE="3411" dataType="int" stringID="PAR_NUM_SLICEX" value="61"/>
</item>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="179">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="93"/>
<item dataType="int" stringID="PAR_OCCUPIED_LUT_AND_FF" value="195">
<item dataType="int" stringID="PAR_OCCUPIED_LUT_ONLY" value="109"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_ONLY" value="2"/>
<item dataType="int" stringID="PAR_OCCUPIED_FF_AND_LUT" value="84"/>
</item>
......
hdl/spec/syn/test_tdc_pll/xplace/fifo_32x512.ngc deleted 100644 → 0
View file @ b5ae1362
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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hdl/spec/syn/test_tdc_pll/xplace/fifo_64x512.ngc deleted 100644 → 0
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