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FMC TDC 1ns 5cha - Gateware
Commit b4d12c32 authored by penacoba's avatar penacoba
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First versions for hardware test 



git-svn-id: http://svn.ohwr.org/fmc-tdc@32 85dfdc96-de2c-444c-878d-45b388be74a9
parent 4c9264e1
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hdl/spec/sim/.nclaunch.dd 0 → 100644
View file @ b4d12c32
# DO NOT EDIT -- automatically generated design data file -- DO NOT EDIT!!!
list \
workdir {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim} \
cdslib {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/cds.lib} \
worklib {worklib} \
mode {0} \
filters {*} \
sesslist {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
hdl/spec/sim/.nclaunch.dd.bak 0 → 100644
View file @ b4d12c32
# DO NOT EDIT -- automatically generated design data file -- DO NOT EDIT!!!
list \
workdir {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim} \
cdslib {/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/cds.lib} \
worklib {worklib} \
mode {0} \
filters {*} \
sesslist {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
ToolOption_NCVhdl {-logfile ncvhdl.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/AMS {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_NCVlog/SV {-logfile ncvlog.log -errormax 15 -update -linedebug -status} \
ToolOption_irun {-gui {} +linedebug +access rwc -q} \
ToolOption_NCElab {-logfile ncelab.log -errormax 15 -status -access +wc} \
ToolOption_NCSim {-gui -logfile ncsim.log -errormax 15 -status} \
ToolOption_NCSdfc {-logfile ncsdfc.log -compile -status} \
ToolOption_HAL {-logfile hal.log} \
ToolOption_SimVision {} \
ToolOption_Update {-errormax 15 -force} \
ToolOption_Comparescan {} \
ToolOption_NCBrowse {} \
ToolOption_HALDefEdit {} \
ToolOption_PLI Wizard {} \
ToolOption_NCShell {-view shell -logfile ncshell.log -errormax 15 -suffix .v} \
ToolOption_NCProtect {-logfile ncprotect.log} \
ToolOption_NCDC {-logfile ncdc.log -messages -status} \
ToolOption_DBUtil {} \
hdl/spec/sim/.nclaunch.err 0 → 100644
View file @ b4d12c32
Thu 07 Jul 2011 06:32:13 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:54 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:55 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:56 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:56 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:57 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 06:32:57 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 07:32:59 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Thu 07 Jul 2011 07:32:59 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Fri 08 Jul 2011 03:05:19 PM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:04:27 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:05:27 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:05:30 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:31 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:31 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:06:32 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:01 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:01 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
Mon 11 Jul 2011 11:40:42 AM CEST
visadev: *F,DLNOLK: Failed to get a shared lock on library 'worklib' (Resource temporarily unavailable).
hdl/spec/sim/cds.lib 0 → 100644
View file @ b4d12c32
include $CDS_INST_DIR/tools/inca/files/cds.lib
define worklib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/worklib
DEFINE unimacro /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unimacro
DEFINE unisim /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/unisim
DEFINE xilinxcorelib /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/sim/INCA_libs/xilinxcorelib
hdl/spec/sim/data_vectors/acam_test_cmd0.vec 0 → 100644
View file @ b4d12c32
-------------------------------------------------------------------------------
-- acam_test.vec
-------------------------------------------------------------------------------
-- Select the GN4124 Primary BFM
model 0
-- Initialize the BFM to its default state
init
-------------------------------------------------------------------------------
-- Initialize the Primary GN412x BFM model
-------------------------------------------------------------------------------
-- These address ranges will generate traffic from the BFM to the FPGA
-- bar BAR ADDR SIZE VC TC S
bar 0 0000000000000000 00100000 0 7 0
-- This allocates a RAM block inside the BFM for the FPGA to access
-- bfm_bar BAR ADDR SIZE
bfm_bar 0 0000000040000000 20000000
bfm_bar 1 0000000020000000 20000000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d50000
-- Drive reset to the FPGA
reset %d320
-- Wait until the FPGA is un-reset and ready for traffic on the local bus
wait %d20000
-------------------------------------------------------------------------------
-- Access the tdc core register space
-------------------------------------------------------------------------------
-- the following writes will go out in a single packet
wr 0000000000000000 F 0000AFA1
wait %d1
wr 0000000000080004 F 1000AFA2
hdl/spec/sim/data_vectors/pulses.txt 0 → 100644
View file @ b4d12c32
1300 us,1,5 us
6 us,2,505 ns
162 ps,3,505 ns
840 us,4,505 ns
1400 ps,5,505 ns
400 ps,1,505 ns
hdl/spec/sim/hdl.var 0 → 100644
View file @ b4d12c32
define WORK worklib
include $CDS_INST_DIR/tools/inca/files/hdl.var
hdl/spec/sim/sim.tcl 0 → 100644
View file @ b4d12c32
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/gn4124_core_pkg_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/ip_cores/fifo_32x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/ip_cores/fifo_64x512.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_n_to_1_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_n_to_1_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_ser_s6.vhd
ncvhdl -controlrelax NLSTEX -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_1_to_n_data_s2_se.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_des_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_decode32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/wbmaster32.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/dma_controller_wb_slave.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/dma_controller.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/p2l_dma_master.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/l2p_arbiter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/gnum_core/gn4124_core_s6.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/tdc_core_pkg.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/free_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/incr_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/countdown_counter.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/clk_rst_managr.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/one_hz_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/start_nb_offset_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/data_formatting.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/acam_timecontrol_interface.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/acam_databus_interface.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/top_tdc.vhd
#ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/test_tdc_acam/top_test_acam.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/design/test_tdc_pll/top_test_pll.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/util.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/textutil.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/mem_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/cmd_router1.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/cmd_router.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/gnum_model/gn412x_bfm.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_timing_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_fifo_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_data_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/acam_model.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/start_stop_gen.vhd
ncvhdl -nocopyright -nolog -messages -linedebug -v93 -cdslib ./cds.lib -work worklib ../src/test_bench/tb_tdc.vhd
ncelab -nocopyright -nolog -messages -access +wc -messages -v93 -cdslib ./cds.lib -work worklib worklib.tb_tdc:behavioral
#ncelab -nocopyright -nolog -messages -access +wc -messages -v93 -cdslib ./cds.lib -work worklib worklib.tdc_top:rtl
#ncsim -gui -cdslib ./cds.lib -nocopyright -nolog -nokey worklib.tb_tdc:behavioral -input waves.tcl
hdl/spec/sim/waves.tcl 0 → 100644
View file @ b4d12c32
probe -create -shm -waveform :spec_clk_i
probe -create -shm -waveform :dut:por_reset
probe -create -shm -waveform :dut:internal_reset
probe -create -shm -waveform :dut:clk
probe -create -shm -waveform :dut:acam_refclk
probe -create -shm -waveform :dut:gnum_reset
probe -create -shm -waveform :dut:general_reset
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:half_clk
probe -create -shm -waveform :dut:clocks_and_resets_management_block:cs
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:bit_index
probe -create -shm -waveform :dut:clocks_and_resets_management_block:byte_index
probe -create -shm -waveform :dut:clocks_and_resets_management_block:bit_being_sent
probe -create -shm -waveform :dut:clocks_and_resets_management_block:byte_being_sent
probe -create -shm -waveform :dut:clocks_and_resets_management_block:pll_init_st
probe -create -shm -waveform :dut:clocks_and_resets_management_block:gral_incr
probe -create -shm -waveform :dut:clocks_and_resets_management_block:inv_reset
probe -create -shm -waveform :dut:clocks_and_resets_management_block:general_power_on_reset:current_value
#probe -create -shm -waveform :dut:clocks_and_resets_management_block:nxt_pll_init_st
probe -create -shm -waveform :spec_led_green
probe -create -shm -waveform :spec_led_red
probe -create -shm -waveform :tdc_led_status
probe -create -shm -waveform :dut:tdc_led_count_done
probe -create -shm -waveform :dut:spec_led_count_done
#probe -create -shm -waveform :RSTINn
#probe -create -shm -waveform :RSTOUT18n
#probe -create -shm -waveform :RSTOUT33n
#probe -create -shm -waveform :LCLK
#probe -create -shm -waveform :LCLKn
probe -create -shm -waveform :P2L_CLKp
probe -create -shm -waveform :P2L_CLKn
probe -create -shm -waveform :P2L_DATA
probe -create -shm -waveform :P2L_DATA_32
probe -create -shm -waveform :P2L_DFRAME
probe -create -shm -waveform :P2L_VALID
probe -create -shm -waveform :P2L_RDY
probe -create -shm -waveform :P_WR_REQ
probe -create -shm -waveform :P_WR_RDY
probe -create -shm -waveform :RX_ERROR
probe -create -shm -waveform :VC_RDY
#probe -create -shm -waveform :L2P_CLKp, L2P_CLKn
#probe -create -shm -waveform :L2P_DATA
#probe -create -shm -waveform :L2P_DATA_32
#probe -create -shm -waveform :L2P_DFRAME
#probe -create -shm -waveform :L2P_VALID
#probe -create -shm -waveform :L2P_EDB
#probe -create -shm -waveform :L2P_RDY
#probe -create -shm -waveform :L_WR_RDY
#probe -create -shm -waveform :P_RD_D_RDY
#probe -create -shm -waveform :TX_ERROR
probe -create -shm -waveform :GPIO
#probe -create -shm -waveform :dut:acm_adr
#probe -create -shm -waveform :dut:acm_cyc
#probe -create -shm -waveform :dut:acm_dat_w
#probe -create -shm -waveform :dut:acm_stb
#probe -create -shm -waveform :dut:acm_we
#probe -create -shm -waveform :dut:acm_ack
#probe -create -shm -waveform :dut:acm_dat_r
probe -create -shm -waveform :dut:csr_clk
probe -create -shm -waveform :dut:csr_cyc
probe -create -shm -waveform :dut:csr_sel
probe -create -shm -waveform :dut:csr_adr
probe -create -shm -waveform :dut:csr_dat_r
probe -create -shm -waveform :dut:csr_dat_w
probe -create -shm -waveform :dut:csr_stb
probe -create -shm -waveform :dut:csr_ack
probe -create -shm -waveform :dut:csr_we
probe -create -shm -waveform :dut:acam_data_block:acam_data_st
probe -create -shm -waveform :dut:acam_data_block:nxt_acam_data_st
probe -create -shm -waveform :dut:data_bus_io
probe -create -shm -waveform :dut:address_o
probe -create -shm -waveform :dut:cs_n_o
probe -create -shm -waveform :dut:oe_n_o
probe -create -shm -waveform :dut:rd_n_o
probe -create -shm -waveform :dut:wr_n_o
#probe -create -shm -waveform :acam:data_block:wr_falling_time
#probe -create -shm -waveform :acam:data_block:wr_rising_time
#probe -create -shm -waveform :dut:one_second_block:acam_refclk_i
#probe -create -shm -waveform :dut:one_second_block:s_acam_refclk
#probe -create -shm -waveform :dut:one_second_block:refclk_edge
#probe -create -shm -waveform :dut:one_second_block:onesec_counter_en
#probe -create -shm -waveform :dut:one_second_block:total_delay
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_pre
#probe -create -shm -waveform :dut:one_second_block:one_hz_p_post
probe -create -shm -waveform :dut:one_second_block:one_hz_p_o
#probe -create -shm -waveform :dut:acam_timing_block:counter_reset
#probe -create -shm -waveform :dut:acam_timing_block:window_inverted
#probe -create -shm -waveform :dut:acam_timing_block:start_window
#probe -create -shm -waveform :dut:acam_timing_block:start_dis_o
#probe -create -shm -waveform :dut:acam_timing_block:int_flag_i
#probe -create -shm -waveform :dut:start_nb_block:acam_irflag_p_i
#probe -create -shm -waveform :dut:start_nb_block:start_nb_offset_o
#probe -create -shm -waveform :start_dis_o
probe -create -shm -waveform :start_from_fpga_o
probe -create -shm -waveform :acam_refclk_i
#probe -create -shm -waveform :stop_dis_o
probe -create -shm -waveform :tstop1
probe -create -shm -waveform :tstop2
probe -create -shm -waveform :tstop3
probe -create -shm -waveform :tstop4
probe -create -shm -waveform :tstop5
#probe -create -shm -waveform :pulses_generator:pulse_channel
#probe -create -shm -waveform :pulses_generator:sequence:pulse_ch
#probe -create -shm -waveform :acam:timing_block:timestamp_for_fifo1
#probe -create -shm -waveform :acam:timing_block:timestamp_for_fifo2
#probe -create -shm -waveform :acam:timing_block:tstart
#probe -create -shm -waveform :acam:timing_block:tstop1
#probe -create -shm -waveform :acam:timing_block:tstop2
#probe -create -shm -waveform :acam:timing_block:tstop3
#probe -create -shm -waveform :acam:timing_block:tstop4
#probe -create -shm -waveform :acam:timing_block:tstop5
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo[0]
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo[1]
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo[2]
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo[3]
#probe -create -shm -waveform :acam:data_block:interface_fifo1:fifo[4]
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo[0]
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo[1]
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo[2]
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo[3]
#probe -create -shm -waveform :acam:data_block:interface_fifo2:fifo[4]
#probe -create -shm -waveform :acam:timing_block:start_trig
#probe -create -shm -waveform :acam:timing_block:stop1_trig
#probe -create -shm -waveform :acam:timing_block:stop1
#probe -create -shm -waveform :acam:timing_block:stop2_trig
#probe -create -shm -waveform :acam:timing_block:stop2
#probe -create -shm -waveform :acam:timing_block:stop3_trig
#probe -create -shm -waveform :acam:timing_block:stop3
#probe -create -shm -waveform :acam:timing_block:stop4_trig
#probe -create -shm -waveform :acam:timing_block:stop4
#probe -create -shm -waveform :acam:timing_block:stop5_trig
#probe -create -shm -waveform :acam:timing_block:stop5
probe -create -shm -waveform :acam:timing_block:start01
probe -create -shm -waveform :acam:timing_block:start_retrig_p
probe -create -shm -waveform :acam:timing_block:start_retrig_nb
#probe -create -shm -waveform :acam:timing_block:int_flag_o
#probe -create -shm -waveform :acam:timing_block:start_nb1
#probe -create -shm -waveform :acam:timing_block:start_nb2
#probe -create -shm -waveform :acam:timing_block:start_nb3
#probe -create -shm -waveform :acam:timing_block:start_nb4
#probe -create -shm -waveform :acam:timing_block:start_nb5
set intovf_severity_level warning
run 1 ms
hdl/spec/src/ip_cores/gnum_core/clock_generator_ddr_s2_diff.vhd 0 → 100644
View file @ b4d12c32
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: clock_generator_ddr_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
-- and instantiates two sets of 2 BUFIO2s, one for each half bank
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator_ddr_s2_diff is
generic (
S : integer := 2; -- Parameter to set the serdes factor
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p, clkin_n : in std_logic; -- differential clock input
ioclkap : out std_logic; -- A P ioclock from BUFIO2
ioclkan : out std_logic; -- A N ioclock from BUFIO2
serdesstrobea : out std_logic; -- A serdes strobe from BUFIO2
ioclkbp : out std_logic; -- B P ioclock from BUFIO2 - leave open if not required
ioclkbn : out std_logic; -- B N ioclock from BUFIO2 - leave open if not required
serdesstrobeb : out std_logic; -- B serdes strobe from BUFIO2 - leave open if not required
gclk : out std_logic) ; -- global clock output from BUFIO2
end clock_generator_ddr_s2_diff;
architecture arch_clock_generator_ddr_s2_diff of clock_generator_ddr_s2_diff is
signal clkint : std_logic; --
signal gclk_int : std_logic; --
signal freqgen_in_p : std_logic; --
signal tx_bufio2_x1 : std_logic; --
begin
gclk <= gclk_int;
iob_freqgen_in : IBUFGDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => freqgen_in_p);
bufio2_inst1 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkap, -- Output Clock for IO
DIVCLK => tx_bufio2_x1, -- Output Divided Clock
SERDESSTROBE => serdesstrobea) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst2 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkan, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst3 : BUFIO2 generic map(
DIVIDE => S, -- The DIVCLK divider divide-by value; default 1
I_INVERT => false, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => true) --
port map (
I => freqgen_in_p, -- Input source clock 0 degrees
IOCLK => ioclkbp, -- Output Clock for IO
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => serdesstrobeb) ; -- Output SERDES strobe (Clock Enable)
bufio2_inst4 : BUFIO2 generic map(
I_INVERT => true, --
DIVIDE_BYPASS => false, --
USE_DOUBLER => false) --
port map (
I => freqgen_in_p, -- N_clk input from IDELAY
IOCLK => ioclkbn, -- Output Clock
DIVCLK => open, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
bufg_tx : BUFG port map (I => tx_bufio2_x1, O => gclk_int);
end arch_clock_generator_ddr_s2_diff;
hdl/spec/src/ip_cores/gnum_core/dma_controller.vhd 0 → 100644
View file @ b4d12c32
This diff is collapsed.
hdl/spec/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd 0 → 100644
View file @ b4d12c32
This diff is collapsed.
hdl/spec/src/ip_cores/gnum_core/dummy_ctrl_regs.vhd 0 → 100644
View file @ b4d12c32
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Dummy control registers
---------------------------------------------------------------------------------------