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FMC TDC 1ns 5cha - Gateware
Commit 9e320175 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated submodules; added sourceid feature in metadata

parent 232f3275
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Showing with 1066 additions and 1153 deletions
ddr3-sp6-core @ 70f9de31
Subproject commit ba3e6787e6c98cd1fd944fbea18d081c3cb96904
Subproject commit 70f9de318f155764fdd4b7e1ae7f9c5b77131930
general-cores @ 258eb8e0
Subproject commit b9925c97707698310e232ae2736e3d3d4b1b5971
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
gn4124-core @ e7637624
Subproject commit d5e7a9f24aad042caa27a907c5389ddd94e99a3c
Subproject commit e763762405dd5274d342285dbc64683221f1fb15
spec @ 1e9e50ec
Subproject commit f5c15451d0a8a42fcde96de954c7b2558ef79569
Subproject commit 1e9e50ecafc0584d42eb0ccd5682fb08ed32549d
hdl/syn/spec/Manifest.py
View file @ 9e320175
......@@ -12,8 +12,7 @@ syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
top_module = "wr_spec_tdc"
files = ["buildinfo_pkg.vhd"]
files = ["buildinfo_pkg.vhd", "sourceid_wr_spec_tdc_pkg.vhd"]
modules = { "local" : [ "../../top/spec" ] }
......@@ -23,6 +22,15 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'wr_spec_tdc'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
spec_base_ucf = ['wr', 'ddr3', 'onewire', 'spi']
......
hdl/syn/spec/wr_spec_tdc.xise
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hdl/syn/svec/Manifest.py
View file @ 9e320175
board = "svec"
target = "xilinx"
action = "synthesis"
......@@ -9,21 +10,11 @@ syn_package = "fgg900"
syn_top = "wr_svec_tdc"
syn_project = "wr_svec_tdc.xise"
syn_tool = "ise"
#top_module = "wr_svec_tdc"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = ["buildinfo_pkg.vhd", "sourceid_wr_svec_tdc_pkg.vhd"]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/svec",
],
}
modules = { "local" : [ "../../top/svec" ] }
# Do not fail during hdlmake fetch
try:
......@@ -31,6 +22,15 @@ try:
except:
pass
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open(fetchto + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'wr_svec_tdc'})
except Exception as e:
print("Error: cannot generate source id file")
raise
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
svec_base_ucf = ['wr', 'led', 'gpio']
......
hdl/syn/svec/wr_svec_tdc.xise
View file @ 9e320175
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/top/spec/Manifest.py
View file @ 9e320175
files = ["synthesis_descriptor.vhd",
"wr_spec_tdc.ucf",
files = ["wr_spec_tdc.ucf",
"wr_spec_tdc.vhd"];
fetchto = "../../ip_cores"
......
hdl/top/spec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ 232f3275
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2017-09-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20170920",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
);
end package synthesis_descriptor;
hdl/top/spec/wr_spec_tdc.vhd
View file @ 9e320175
......@@ -92,10 +92,10 @@ use IEEE.numeric_std.all;
use work.tdc_core_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.synthesis_descriptor.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_spec_pkg.all;
use work.sourceid_wr_spec_tdc_pkg;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -420,10 +420,10 @@ begin
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_0001", -- WRTD Node (WN) 1
g_VERSION => x"0100_0000",
g_DEVICE_ID => x"574E_0001", -- SPEC + TDC
g_VERSION => x"0800_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
g_COMMIT_ID => sourceid_wr_spec_tdc_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
......
hdl/top/svec/synthesis_descriptor.vhd deleted 100644 → 0
View file @ 232f3275
------------------------------------------------------------------------------
-- Title : TDC FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2015-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_svec_tdc ",
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150527",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
);
end package synthesis_descriptor;
hdl/top/svec/wr_svec_tdc.vhd
View file @ 9e320175
......@@ -110,6 +110,7 @@ use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.sourceid_wr_svec_tdc_pkg;
library UNISIM;
use UNISIM.vcomponents.all;
......@@ -354,7 +355,7 @@ architecture rtl of wr_svec_tdc is
constant c_WB_LAYOUT_MASK :
t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
c_WB_SLAVE_METADATA => x"0003_ffc0", -- 0x40 bytes: not(0x40 -1) = not(0x3F) = c0
c_WB_SLAVE_FMC0_TDC => x"0003_0000", -- 0x10000 bytes
c_WB_SLAVE_FMC0_TDC => x"0003_0000",
c_WB_SLAVE_FMC1_TDC => x"0003_0000");
......@@ -426,6 +427,24 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
areset_n <= vme_sysreset_n_i and rst_n_i;
---------------------------------------------------------------------------------------------------
-- TDC specific Metadata ROM --
---------------------------------------------------------------------------------------------------
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_0002", -- SVEC + 2xTDC
g_VERSION => x"0800_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => sourceid_wr_svec_tdc_pkg.sourceid)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
---------------------------------------------------------------------------------------------------
-- SVEC Board Base --
---------------------------------------------------------------------------------------------------
......@@ -488,13 +507,6 @@ begin
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
---------------------------------------------------------
-- DDR - not used
---------------------------------------------------------
ddr4_clk_i => '0',
ddr4_rst_n_i => '1',
ddr5_clk_i => '0',
ddr5_rst_n_i => '1',
---------------------------------------------------------
-- Carrier peripherals
---------------------------------------------------------
......@@ -618,7 +630,7 @@ begin
clk_sys_i => clk_sys_62m5,
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n, ------------ to be removed
fmc_id_i => '1', -- '0' for SPEC; '0' and '1' for each of the TDCs of SVEC
fmc_id_i => '0', -- '0' for SPEC; '0' and '1' for each of the TDCs of SVEC
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_n_o,
......
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