Commit 7f3e7a0e authored by penacoba's avatar penacoba

Timing problems solved by adding registers on the Term En outputs


git-svn-id: http://svn.ohwr.org/fmc-tdc@59 85dfdc96-de2c-444c-878d-45b388be74a9
parent d4b1ca52
......@@ -67,17 +67,17 @@ end circular_buffer;
----------------------------------------------------------------------------------------------------
architecture rtl of circular_buffer is
component blk_mem_gen_v6_3
component blk_mem_circ_buff_v6_4
port(
clka : in std_logic;
addra : in std_logic_vector(6 downto 0);
addra : in std_logic_vector(7 downto 0);
dina : in std_logic_vector(127 downto 0);
ena : in std_logic;
wea : in std_logic_vector(0 downto 0);
douta : out std_logic_vector(127 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(8 downto 0);
addrb : in std_logic_vector(9 downto 0);
dinb : in std_logic_vector(31 downto 0);
enb : in std_logic;
web : in std_logic_vector(0 downto 0);
......@@ -90,7 +90,7 @@ type t_wb_pipelined_mem_interface is (idle, mem_access, mem_access_and
signal wb_pipelined_st, nxt_wb_pipelined_st : t_wb_pipelined_mem_interface;
signal class_ack : std_logic;
signal class_adr : std_logic_vector(6 downto 0);
signal class_adr : std_logic_vector(7 downto 0);
signal class_clk : std_logic;
signal class_cyc : std_logic;
signal class_data_rd : std_logic_vector(4*g_width-1 downto 0);
......@@ -101,7 +101,7 @@ signal class_stb : std_logic;
signal class_we : std_logic_vector(0 downto 0);
signal pipe_ack : std_logic;
signal pipe_adr : std_logic_vector(8 downto 0);
signal pipe_adr : std_logic_vector(9 downto 0);
signal pipe_clk : std_logic;
signal pipe_cyc : std_logic;
signal pipe_data_rd : std_logic_vector(g_width-1 downto 0);
......@@ -186,7 +186,7 @@ begin
end case;
end process;
memory_block: blk_mem_gen_v6_3
memory_block: blk_mem_circ_buff_v6_4
port map(
clka => class_clk,
addra => class_adr,
......@@ -207,7 +207,7 @@ begin
class_clk <= class_clk_i;
class_reset <= class_reset_i;
class_adr <= class_adr_i(6 downto 0);
class_adr <= class_adr_i(7 downto 0);
class_cyc <= class_cyc_i;
class_data_wr <= class_dat_i;
class_en <= class_cyc;
......@@ -217,7 +217,7 @@ begin
pipe_clk <= pipe_clk_i;
pipe_reset <= pipe_reset_i;
pipe_adr <= pipe_adr_i(8 downto 0);
pipe_adr <= pipe_adr_i(9 downto 0);
pipe_cyc <= pipe_cyc_i;
pipe_data_wr <= pipe_dat_i;
pipe_en <= pipe_cyc;
......
......@@ -64,6 +64,8 @@ end data_formatting;
----------------------------------------------------------------------------------------------------
architecture rtl of data_formatting is
constant buff_size : unsigned(g_width-1 downto 0):= x"00000100";
signal acam_timestamp1 : std_logic_vector(g_width-1 downto 0);
signal acam_timestamp1_valid : std_logic;
signal acam_timestamp2 : std_logic_vector(g_width-1 downto 0);
......@@ -109,46 +111,38 @@ signal mem_data_wr : std_logic_vector(4*g_width-1 downto 0);
signal mem_stb : std_logic;
signal mem_we : std_logic;
--signal reserved : std_logic_vector(2 downto 0):=(others=>'0');
--signal u_start_nb_offset : unsigned(g_width-1 downto 0);
--signal u_acam_start_nb : unsigned(7 downto 0);
--signal start_nb : std_logic_vector(g_width-1 downto 0);
----------------------------------------------------------------------------------------------------
-- architecture begins
----------------------------------------------------------------------------------------------------
begin
-- classic wishbone to write the full timestamps into the circular buffer memory
pushing_data_to_buffer: process
begin
if reset ='1' then
-- mem_adr <= (others =>'0');
mem_cyc <= '0';
-- mem_data_wr <= (others =>'0');
mem_stb <= '0';
mem_we <= '0';
elsif acam_timestamp1_valid ='1' or acam_timestamp2_valid ='1' then
-- mem_adr <= std_logic_vector(wr_pointer);
mem_cyc <= '1';
-- mem_data_wr <= full_timestamp;
mem_stb <= '1';
mem_we <= '1';
elsif mem_ack ='1' then
-- mem_adr <= std_logic_vector(wr_pointer);
mem_cyc <= '0';
-- mem_data_wr <= full_timestamp;
mem_stb <= '0';
mem_we <= '0';
end if;
wait until clk ='1';
end process;
-- the wr_pointer indicates which one is the next address to write
-- it will be used by the PCIe host to configure the DMA coherently
pointer_update: process
begin
if reset ='1' then
wr_pointer <= (others=>'0');
elsif mem_cyc ='1' and mem_stb ='1' and mem_we ='1' and mem_ack ='1' then
if wr_pointer = 127 then
if wr_pointer = buff_size - 1 then
wr_pointer <= (others=>'0');
else
wr_pointer <= wr_pointer + 1;
......@@ -157,18 +151,22 @@ begin
wait until clk ='1';
end process;
-- the Da Capo flag indicates if the circular buffer has been written completely
-- it is cleared by the PCIe host.
dacapo_flag_update: process
begin
if reset ='1' then
dacapo_flag <= '0';
elsif clear_dacapo_flag ='1' then
dacapo_flag <= '0';
elsif wr_pointer = 127 then
elsif wr_pointer = buff_size - 1 then
dacapo_flag <= '1';
end if;
wait until clk ='1';
end process;
-- the 28-bits word received from the Acam is interpreted according to the datasheet
-- and the corresponding values will be used to build the full timestamp
acam_data_slicing: process
begin
if reset ='1' then
......@@ -196,11 +194,21 @@ begin
wait until clk ='1';
end process;
-- coarse_time <= x"000000"
-- & acam_start_nb;
mem_adr <= std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp;
-- the full timestamp is a 128-bits word divided in four 32-bits words
-- the highest weight word contains the metadata for each timestamp
-- the following 32-bits word contains the local UTC time with 1s resolution
-- then the coarse timing of the timestamp within the current second with 8 ns resolution
-- finally the fine time for the timestamp with 81.03 ps resolution
-- the metadata field contains extra information about the timestamp
full_timestamp(127 downto 96) <= metadata;
full_timestamp(95 downto 64) <= local_utc;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(31 downto 0) <= fine_time;
-- the metadata field contains extra information about the timestamp
metadata <= x"0000"
& "000" & acam_fifo_ef
& "000" & acam_fifo_lf
......@@ -209,7 +217,6 @@ begin
-- the UTC time is updated every second by the one_hz_pulse
local_utc <= local_utc_i;
-- the coarse time is expressed as the number of 125 MHz clock cycles since the last one_hz_pulse.
......@@ -245,19 +252,10 @@ begin
-- the fine time is directly provided by the ACAM as a number of BINs since the last
-- internal retrigger.
fine_time <= x"000"
& "000"
& acam_fine_timestamp;
full_timestamp(127 downto 96) <= metadata;
full_timestamp(95 downto 64) <= local_utc;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(31 downto 0) <= fine_time;
mem_adr <= std_logic_vector(wr_pointer);
mem_data_wr <= full_timestamp;
-- inputs
acam_timestamp1 <= acam_timestamp1_i;
acam_timestamp1_valid <= acam_timestamp1_valid_i;
......@@ -283,11 +281,6 @@ begin
stb_o <= mem_stb;
we_o <= mem_we;
-- u_start_nb_offset <= unsigned(start_nb_offset);
-- u_acam_start_nb <= unsigned(acam_timestamp(25 downto 18));
-- start_nb <= std_logic_vector(u_start_nb_offset + u_acam_start_nb);
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
......@@ -7,7 +7,7 @@
-- date : Oct 2011
-- version : Revision 1
-- description : Interfaces with the CSR wishbone bus of the GNUM core. Holds the configuration
-- registers for the ACAM and other modules of the TDC core.
-- and status registers for the ACAM and other modules of the TDC core.
-- dependencies:
-- references :
-- modified by :
......@@ -56,7 +56,6 @@ entity reg_ctrl is
read_start01_o : out std_logic;
reset_acam_o : out std_logic;
load_utc_o : out std_logic;
-- load_tdc_config_o : out std_logic;
clear_dacapo_flag_o : out std_logic;
-- configuration registers from and for the ACAM and the modules of the TDC core
......@@ -72,11 +71,9 @@ entity reg_ctrl is
acam_config_o : out config_vector;
starting_utc_o : out std_logic_vector(g_width-1 downto 0);
-- clk_freq_o : out std_logic_vector(g_width-1 downto 0);
-- ref_clk_freq_o : out std_logic_vector(g_width-1 downto 0);
in_en_ctrl_o : out std_logic_vector(g_width-1 downto 0);
start_phase_o : out std_logic_vector(g_width-1 downto 0);
one_hz_phase_o : out std_logic_vector(g_width-1 downto 0)
-- retrig_freq_o : out std_logic_vector(g_width-1 downto 0)
);
end reg_ctrl;
......@@ -85,24 +82,6 @@ end reg_ctrl;
----------------------------------------------------------------------------------------------------
architecture rtl of reg_ctrl is
--component reg_mem_gen_v6_2
-- port(
-- clka : in std_logic;
-- addra : in std_logic_vector(5 downto 0);
-- dina : in std_logic_vector(31 downto 0);
-- ena : in std_logic;
-- wea : in std_logic_vector(0 downto 0);
-- douta : out std_logic_vector(31 downto 0);
--
-- clkb : in std_logic;
-- addrb : in std_logic_vector(5 downto 0);
-- dinb : in std_logic_vector(31 downto 0);
-- enb : in std_logic;
-- web : in std_logic_vector(0 downto 0);
-- doutb : out std_logic_vector(31 downto 0)
-- );
--end component;
signal reg_ack : std_logic;
signal reg_adr : std_logic_vector(7 downto 0);
signal reg_clk : std_logic;
......@@ -119,18 +98,16 @@ signal acam_status : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1 : std_logic_vector(g_width-1 downto 0);
signal acam_ififo2 : std_logic_vector(g_width-1 downto 0);
signal acam_start01 : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal core_status : std_logic_vector(g_width-1 downto 0);
signal irq_code : std_logic_vector(g_width-1 downto 0);
signal local_utc : std_logic_vector(g_width-1 downto 0);
signal wr_pointer : std_logic_vector(g_width-1 downto 0);
signal acam_config : config_vector;
signal starting_utc : std_logic_vector(g_width-1 downto 0);
--signal clk_freq : std_logic_vector(g_width-1 downto 0);
--signal ref_clk_freq : std_logic_vector(g_width-1 downto 0);
signal in_en_ctrl : std_logic_vector(g_width-1 downto 0);
signal start_phase : std_logic_vector(g_width-1 downto 0);
signal one_hz_phase : std_logic_vector(g_width-1 downto 0);
--signal retrig_freq : std_logic_vector(g_width-1 downto 0);
signal control_register : std_logic_vector(g_width-1 downto 0);
signal clear_ctrl_reg : std_logic;
......@@ -220,11 +197,9 @@ begin
begin
if reg_reset ='1' then
starting_utc <= (others =>'0');
-- clk_freq <= (others =>'0');
-- ref_clk_freq <= (others =>'0');
in_en_ctrl <= (others =>'0');
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
-- retrig_freq <= (others =>'0');
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"20" then -- corresponds to address 80080 of the gnum BAR 0
......@@ -232,41 +207,41 @@ begin
end if;
if reg_adr = x"21" then -- corresponds to address 80084 of the gnum BAR 0
start_phase <= reg_data_wr;
in_en_ctrl <= reg_data_wr;
end if;
if reg_adr = x"22" then -- corresponds to address 80088 of the gnum BAR 0
start_phase <= reg_data_wr;
end if;
if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
one_hz_phase <= reg_data_wr;
end if;
-- if reg_adr = x"23" then -- corresponds to address 8008C of the gnum BAR 0
-- start_phase <= reg_data_wr;
-- end if;
--
-- if reg_adr = x"24" then -- corresponds to address 80090 of the gnum BAR 0
-- one_hz_phase <= reg_data_wr;
-- end if;
--
-- if reg_adr = x"25" then -- corresponds to address 80094 of the gnum BAR 0
-- retrig_freq <= reg_data_wr;
-- end if;
end if;
wait until reg_clk ='1';
end process;
-- control register for TDC core
-- control register for TDC core:
-- written from the PCIe host to control the data_engine state machine.
-- the contents are cleared after one clock cycle.
-- only one bit should be written at a time.
control_reg: process
begin
if reg_reset ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif clear_ctrl_reg ='1' then
control_register <= (others =>'0');
clear_ctrl_reg <= '0';
elsif reg_cyc ='1' and reg_stb ='1' and reg_we ='1' then
if reg_adr = x"3F" then -- corresponds to address 800FC of the gnum BAR 0
if reg_adr = x"3F" then -- corresponds to address 800FC of the gnum BAR 0
control_register <= reg_data_wr;
clear_ctrl_reg <= '1';
end if;
end if;
wait until reg_clk ='1';
......@@ -305,17 +280,19 @@ begin
acam_config_rdbk(10) when x"1E",
starting_utc when x"20",
start_phase when x"21",
one_hz_phase when x"22",
-- when x"23",
irq_code when x"24",
in_en_ctrl when x"21",
start_phase when x"22",
one_hz_phase when x"23",
-- RESERVED when x"24",
local_utc when x"25",
-- when x"26",
irq_code when x"26",
wr_pointer when x"27",
core_status when x"28",
x"FFFFFFFF" when others;
-- inputs from other blocks
-- inputs
reg_clk <= reg_clk_i;
reg_reset <= reg_reset_i;
......@@ -331,12 +308,13 @@ begin
acam_ififo1 <= acam_ififo1_i;
acam_ififo2 <= acam_ififo2_i;
acam_start01 <= acam_start01_i;
irq_code <= irq_code_i;
local_utc <= local_utc_i;
irq_code <= irq_code_i;
wr_pointer <= wr_pointer_i;
core_status <= core_status_i;
-- outputs to other blocks
-- outputs
reg_ack_o <= reg_ack;
reg_dat_o <= reg_data_rd;
......@@ -354,11 +332,9 @@ begin
clear_dacapo_flag_o <= control_register(10);
starting_utc_o <= starting_utc;
-- clk_freq_o <= clk_freq;
-- ref_clk_freq_o <= ref_clk_freq;
in_en_ctrl_o <= in_en_ctrl;
start_phase_o <= start_phase;
one_hz_phase_o <= one_hz_phase;
-- retrig_freq_o <= retrig_freq;
end rtl;
----------------------------------------------------------------------------------------------------
......
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