Commit 7eca4264 authored by Tristan Gingold's avatar Tristan Gingold

syn/spec: adjust Manifest.py

parent d928d757
......@@ -2,7 +2,8 @@ board = "spec"
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
......@@ -10,6 +11,7 @@ syn_package = "fgg484"
syn_top = "wr_spec_tdc"
syn_project = "wr_spec_tdc.xise"
syn_tool = "ise"
#syn_tool = "planahead"
top_module = "wr_spec_tdc"
files = ["buildinfo_pkg.vhd", "sourceid_wr_spec_tdc_pkg.vhd"]
......
......@@ -4,13 +4,14 @@ files = ["wr_spec_tdc.ucf",
fetchto = "../../ip_cores"
modules = {
"local" : [ "../../rtl/",
"../../ip_cores/general-cores",
"../../ip_cores/gn4124-core",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/ddr3-sp6-core",
"../../ip_cores/spec"
"local" : [ "../../rtl/" ],
"git" : [
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/wr-cores/board/spec.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"https://ohwr.org/project/spec.git"
]
}
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