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FMC TDC 1ns 5cha - Gateware
Commit 7d68c05f authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated xise project

parent 51db9c0e
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Showing with 21 additions and 13 deletions
hdl/syn/spec/wr_spec_tdc.xise
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...@@ -149,7 +149,7 @@ ...@@ -149,7 +149,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="215"/> <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
...@@ -157,7 +157,7 @@ ...@@ -157,7 +157,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="220"/> <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
...@@ -185,7 +185,7 @@ ...@@ -185,7 +185,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="221"/> <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
...@@ -241,7 +241,7 @@ ...@@ -241,7 +241,7 @@
</file> </file>
<file xil_pn:name="../../top/spec/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../top/spec/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="224"/> <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
...@@ -293,7 +293,7 @@ ...@@ -293,7 +293,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="214"/> <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
...@@ -321,7 +321,7 @@ ...@@ -321,7 +321,7 @@
</file> </file>
<file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="217"/> <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
...@@ -329,7 +329,7 @@ ...@@ -329,7 +329,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="222"/> <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
...@@ -357,7 +357,7 @@ ...@@ -357,7 +357,7 @@
</file> </file>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="219"/> <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
...@@ -481,7 +481,7 @@ ...@@ -481,7 +481,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="119"/>
<association xil_pn:name="Implementation" xil_pn:seqID="213"/> <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file> </file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
...@@ -609,7 +609,7 @@ ...@@ -609,7 +609,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="../../rtl/tdc_buffer_control_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/tdc_buffer_control_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
...@@ -709,7 +709,7 @@ ...@@ -709,7 +709,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="176"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="176"/>
<association xil_pn:name="Implementation" xil_pn:seqID="223"/> <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/>
...@@ -849,7 +849,7 @@ ...@@ -849,7 +849,7 @@
</file> </file>
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/>
<association xil_pn:name="Implementation" xil_pn:seqID="216"/> <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="212"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="212"/>
...@@ -893,7 +893,7 @@ ...@@ -893,7 +893,7 @@
</file> </file>
<file xil_pn:name="../../rtl/dma_eic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/dma_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/>
<association xil_pn:name="Implementation" xil_pn:seqID="218"/> <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="275"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="275"/>
...@@ -919,6 +919,14 @@ ...@@ -919,6 +919,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
<association xil_pn:name="Implementation" xil_pn:seqID="192"/> <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="247"/>
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="248"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
</files> </files>
<properties> <properties>
......
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