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FMC TDC 1ns 5cha - Gateware
Commit 572973e6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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Uploaded v7.0 sources with wrpc v 4.1

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.gitignore
View file @ 572973e6
......@@ -7,5 +7,9 @@ modelsim.ini
*.vstf
work
*.bak
syn/*
transcript
\ No newline at end of file
hdl/syn/*
transcript
work/
NullFile
*.orig
*.html
\ No newline at end of file
general-cores @ 96295346
Subproject commit 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980
Subproject commit 96295346bb6742b03b43930a4e8a5c73028f4572
gn4124-core @ 9c9bffc9
Subproject commit 7082c5833a2569b24ad69d5f94269eaeff1c7af3
Subproject commit 9c9bffc908e371ea298cdc52d9b12abb35e05dc3
wr-cores @ bcd1f0a3
Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
Subproject commit bcd1f0a3be98c58d2648b788d2f15fdcb3ed820a
hdl/syn/svec/Manifest.py
View file @ 572973e6
......@@ -8,5 +8,6 @@ syn_grade = "-3"
syn_package = "fgg900"
syn_top = "wr_svec_tdc"
syn_project = "wr_svec_tdc.xise"
syn_tool = "ise"
modules = { "local" : [ "../../top/svec" ] }
hdl/syn/svec/wr_svec_tdc.xise
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hdl/top/spec/synthesis_descriptor.vhd
View file @ 572973e6
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150522",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
);
end package synthesis_descriptor;
-------------------------------------------------------------------------------
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2017-09-20
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "wr_spec_tdc ",
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20170920",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
);
end package synthesis_descriptor;
hdl/top/spec/wr_spec_tdc.ucf
View file @ 572973e6
......@@ -416,9 +416,6 @@ TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
......@@ -428,3 +425,8 @@ NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GT
TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
hdl/top/spec/wr_spec_tdc.vhd
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hdl/top/svec/synthesis_descriptor.vhd
View file @ 572973e6
......@@ -6,7 +6,7 @@
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2015-04-08
-- Last update: 2015-05-27
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -46,12 +46,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150522",
syn_date => x"20150527",
syn_username => "twlostow ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/fmc-tdc "
repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git "
);
end package synthesis_descriptor;
hdl/top/svec/wr_svec_tdc.ucf
View file @ 572973e6
......@@ -661,29 +661,6 @@ TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_ph
# PlanAhead Generated miscellaneous constraints
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
# PlanAhead Generated IO constraints
NET "tdc1_address_o[3]" SLEW = FAST;
NET "tdc1_address_o[2]" SLEW = FAST;
NET "tdc1_address_o[1]" SLEW = FAST;
......@@ -748,3 +725,8 @@ NET "tdc2_data_bus_io[3]" SLEW = FAST;
NET "tdc2_data_bus_io[2]" SLEW = FAST;
NET "tdc2_data_bus_io[1]" SLEW = FAST;
NET "tdc2_data_bus_io[0]" SLEW = FAST;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
\ No newline at end of file
hdl/top/svec/wr_svec_tdc.vhd
View file @ 572973e6
......@@ -459,8 +459,8 @@ architecture rtl of wr_svec_tdc is
signal tm_dac_wr_p : std_logic_vector(1 downto 0);
-- White Rabbit PHY
signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
signal phy_tx_k, phy_rx_k : std_logic_vector(0 downto 0);
signal phy_tx_enc_err, phy_rx_rbclk,phy_tx_disparity : std_logic;
signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- White Rabbit serial DAC
......@@ -667,17 +667,20 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
(g_simulation => f_bool2int(g_simulation),
(g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_board_name => "SVEC",
g_aux_clks => 2,
g_ep_rxbuf_size => 1024,
g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4,
g_dpram_initf => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
g_softpll_enable_debugger => false,
g_pcs_16bit => false,
g_records_for_phy => false)
port map
(clk_sys_i => clk_62m5_sys,
clk_dmtd_i => clk_dmtd,
......@@ -764,12 +767,12 @@ begin
ch0_loopen_i => '0',
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
......
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