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FMC TDC 1ns 5cha - Gateware
Commit 442adcb5 authored by penacoba's avatar penacoba
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Modifications of the Acam enable and start from FPGA for correct operation 


git-svn-id: http://svn.ohwr.org/fmc-tdc@42 85dfdc96-de2c-444c-878d-45b388be74a9
parent d7077e06
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hdl/spec/src/rtl/acam_timecontrol_interface.vhd
View file @ 442adcb5
...@@ -38,9 +38,11 @@ entity acam_timecontrol_interface is ...@@ -38,9 +38,11 @@ entity acam_timecontrol_interface is
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
start_trig_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0);
acam_rise_errflag_p_o : out std_logic; acam_rise_errflag_p_o : out std_logic;
acam_fall_errflag_p_o : out std_logic; acam_fall_errflag_p_o : out std_logic;
...@@ -54,6 +56,21 @@ end acam_timecontrol_interface; ...@@ -54,6 +56,21 @@ end acam_timecontrol_interface;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
architecture rtl of acam_timecontrol_interface is architecture rtl of acam_timecontrol_interface is
component countdown_counter
generic(
width : integer :=32
);
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
start_value : in std_logic_vector(width-1 downto 0);
count_done : out std_logic;
current_value : out std_logic_vector(width-1 downto 0)
);
end component;
component incr_counter component incr_counter
generic( generic(
width : integer :=32 width : integer :=32
...@@ -69,20 +86,27 @@ architecture rtl of acam_timecontrol_interface is ...@@ -69,20 +86,27 @@ architecture rtl of acam_timecontrol_interface is
); );
end component; end component;
signal acam_refclk : std_logic;
signal clk : std_logic; signal clk : std_logic;
signal counter_reset : std_logic; signal counter_reset : std_logic;
signal counter_value : std_logic_vector(g_width-1 downto 0);
signal start_trig : std_logic; signal refclk_edge : std_logic;
signal refclk_r : unsigned(3 downto 0);
signal reset : std_logic; signal reset : std_logic;
signal s_int_flag : unsigned(2 downto 0); signal int_flag_r : unsigned(2 downto 0);
signal s_err_flag : unsigned(2 downto 0); signal err_flag_r : unsigned(2 downto 0);
signal start_dis : std_logic; signal start_dis : std_logic;
signal start_from_fpga : std_logic; signal start_from_fpga : std_logic;
signal start_window : std_logic; signal start_trig : std_logic;
signal start_window_reg : unsigned(2 downto 0); signal start_trig_r : unsigned(2 downto 0);
signal start_window_edge : std_logic; signal start_trig_edge : std_logic;
signal waitingfor_refclk : std_logic;
signal window_active : std_logic;
signal window_delay : std_logic_vector(g_width-1 downto 0);
signal window_inverted : std_logic; signal window_inverted : std_logic;
signal window_prepulse : std_logic;
signal window_start : std_logic;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- architecture begins -- architecture begins
...@@ -92,10 +116,10 @@ begin ...@@ -92,10 +116,10 @@ begin
sync_err_flag: process -- synchronisation registers for ERR external signal sync_err_flag: process -- synchronisation registers for ERR external signal
begin begin
if reset ='1' then if reset ='1' then
s_err_flag <= (others=>'0'); err_flag_r <= (others=>'0');
else else
s_err_flag <= shift_right(s_err_flag,1); err_flag_r <= shift_right(err_flag_r,1);
s_err_flag(2) <= err_flag_i; err_flag_r(2) <= err_flag_i;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
...@@ -103,27 +127,41 @@ begin ...@@ -103,27 +127,41 @@ begin
sync_int_flag: process -- synchronisation registers for INT external signal sync_int_flag: process -- synchronisation registers for INT external signal
begin begin
if reset ='1' then if reset ='1' then
s_int_flag <= (others=>'0'); int_flag_r <= (others=>'0');
else else
s_int_flag <= shift_right(s_int_flag,1); int_flag_r <= shift_right(int_flag_r,1);
s_int_flag(2) <= int_flag_i; int_flag_r(2) <= int_flag_i;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
acam_fall_errflag_p_o <= not(s_err_flag(1)) and s_err_flag(0); acam_fall_errflag_p_o <= not(err_flag_r(1)) and err_flag_r(0);
acam_rise_errflag_p_o <= s_err_flag(1) and not(s_err_flag(0)); acam_rise_errflag_p_o <= err_flag_r(1) and not(err_flag_r(0));
acam_fall_intflag_p_o <= not(s_int_flag(1)) and s_int_flag(0); acam_fall_intflag_p_o <= not(int_flag_r(1)) and int_flag_r(0);
acam_rise_intflag_p_o <= s_int_flag(1) and not(s_int_flag(0)); acam_rise_intflag_p_o <= int_flag_r(1) and not(int_flag_r(0));
-- generation of the start pulse and the enable window: -- generation of the start pulse and the enable window:
-- the start pulse originates from an internal signal -- the start pulse originates from an internal signal
-- at the same time, the StartDis is de-asserted. -- at the same time, the StartDis is de-asserted.
window_counter: incr_counter window_delayer_counter: countdown_counter -- all signals are synchronized
generic map( generic map( -- to the refclk of the ACAM
width => g_width -- But their delays are configurable.
)
port map(
clk => clk,
reset => reset,
start => window_prepulse,
start_value => window_delay,
count_done => window_start,
current_value => open
);
window_active_counter: incr_counter -- Defines the de-assertion window
generic map( -- for the StartDisable signal
width => g_width width => g_width
) )
port map( port map(
...@@ -133,51 +171,85 @@ begin ...@@ -133,51 +171,85 @@ begin
reset => counter_reset, reset => counter_reset,
count_done => window_inverted, count_done => window_inverted,
current_value => open current_value => counter_value
); );
start_window <= not(window_inverted); window_active <= not(window_inverted);
start_disable_control: process -- After many tests with the ACAM chip, the Start Disable feature
begin -- doesn't seem to be stable. It has therefore been decided to
-- avoid its usage.
-- start_disable_control: process
-- begin
-- if reset ='1' then
-- start_dis <='1';
-- else
-- start_dis <= not(window_active);
-- end if;
-- wait until clk ='1';
-- end process;
start_dis <= '0';
start_pulse_from_fpga: process -- Start pulse in the middle of the
begin -- de-assertion window of StartDisable
if reset ='1' then if reset ='1' then
start_dis <='1'; start_from_fpga <= '0';
elsif counter_value >= x"00000001" and counter_value <= x"00000002" then
start_from_fpga <= '1';
else else
start_dis <= not(start_window); start_from_fpga <= '0';
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
start_window_synchronizer: process -- synchronization with refclk when the start_trig signal is received.
ready_to_trigger: process
begin begin
if reset ='1' then if reset ='1' then
start_window_reg <= (others=>'0'); waitingfor_refclk <= '0';
else elsif start_trig_edge ='1' then
start_window_reg <= shift_right(start_window_reg,1); waitingfor_refclk <= '1';
start_window_reg(2) <= start_window; elsif refclk_edge ='1' then
waitingfor_refclk <= '0';
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
start_pulse: process inputs_synchronizer: process
begin begin
if reset ='1' then if reset ='1' then
start_from_fpga <= '0'; start_trig_r <= (others=>'0');
elsif start_window_edge ='1' then refclk_r <= (others=>'0');
start_from_fpga <= '1';
else else
start_from_fpga <= '0'; start_trig_r <= shift_right(start_trig_r,1);
start_trig_r(2) <= start_trig;
refclk_r <= shift_right(refclk_r,1);
refclk_r(3) <= acam_refclk;
end if; end if;
wait until clk ='1'; wait until clk ='1';
end process; end process;
counter_reset <= reset or start_trig; refclk_edge <= refclk_r(3) and
start_window_edge <= start_window_reg(2) and not(start_window_reg(1)) and not(start_window_reg(0)); not(refclk_r(2)) and
not(refclk_r(1)) and
refclk_r(0);
start_trig_edge <= start_trig_r(2) and
not(start_trig_r(1)) and
not(start_trig_r(0));
window_prepulse <= waitingfor_refclk and refclk_edge;
counter_reset <= reset or window_start;
-- inputs -- inputs
clk <= clk_i; clk <= clk_i;
reset <= reset_i; reset <= reset_i;
start_trig <= start_trig_i; start_trig <= start_trig_i;
acam_refclk <= acam_refclk_i;
window_delay <= window_delay_i;
-- outputs -- outputs
start_dis_o <= start_dis; start_dis_o <= start_dis;
......
hdl/spec/src/rtl/data_engine.vhd
View file @ 442adcb5
...@@ -15,8 +15,8 @@ ...@@ -15,8 +15,8 @@
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- last changes: -- last changes:
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- to do: -- to do: REPLACE THE POLLING BY INTERRUPT FROM THE EMPTY SIGNALS. ADD RESET ACAM COMMAND
-- -- AND GET STATUS COMMAND
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
library IEEE; library IEEE;
......
hdl/spec/src/rtl/start_retrigger_control.vhd
View file @ 442adcb5
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- last changes: -- last changes:
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
-- to do: -- to do: NEEDS TO BE COMPLETELY REVAMPED AFTER DECISION FOR UNIQUE START. ROLL OVER COUNTER etc..
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
library IEEE; library IEEE;
......
hdl/spec/src/rtl/top_tdc.vhd
View file @ 442adcb5
...@@ -191,9 +191,11 @@ architecture rtl of top_tdc is ...@@ -191,9 +191,11 @@ architecture rtl of top_tdc is
stop_dis_o : out std_logic; stop_dis_o : out std_logic;
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_refclk_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
start_trig_i : in std_logic; start_trig_i : in std_logic;
reset_i : in std_logic; reset_i : in std_logic;
window_delay_i : in std_logic_vector(g_width-1 downto 0);
acam_rise_errflag_p_o : out std_logic; acam_rise_errflag_p_o : out std_logic;
acam_fall_errflag_p_o : out std_logic; acam_fall_errflag_p_o : out std_logic;
...@@ -357,6 +359,7 @@ signal visible_blink_length : std_logic_vector(g_width-1 downto 0); ...@@ -357,6 +359,7 @@ signal visible_blink_length : std_logic_vector(g_width-1 downto 0);
-- will be registers of the core -- will be registers of the core
signal pulse_delay : std_logic_vector(g_width-1 downto 0); signal pulse_delay : std_logic_vector(g_width-1 downto 0);
signal window_delay : std_logic_vector(g_width-1 downto 0);
signal clock_period : std_logic_vector(g_width-1 downto 0); signal clock_period : std_logic_vector(g_width-1 downto 0);
signal gnum_reset : std_logic; signal gnum_reset : std_logic;
...@@ -484,16 +487,16 @@ begin ...@@ -484,16 +487,16 @@ begin
int_flag_i => int_flag_i, int_flag_i => int_flag_i,
-- this is the config for acam test, in normal application connect the outputs -- this is the config for acam test, in normal application connect the outputs
-- start_dis_o => start_dis_o, start_dis_o => start_dis_o,
-- start_from_fpga_o => start_from_fpga_o, start_from_fpga_o => start_from_fpga_o,
start_dis_o => open,
start_from_fpga_o => open,
stop_dis_o => stop_dis_o, stop_dis_o => stop_dis_o,
-- signals internal to the chip: interface with other modules -- signals internal to the chip: interface with other modules
acam_refclk_i => acam_refclk,
clk_i => clk, clk_i => clk,
start_trig_i => start_trig, start_trig_i => start_trig,
reset_i => general_reset, reset_i => general_reset,
window_delay_i => window_delay,
acam_fall_errflag_p_o => acam_fall_errflag_p, acam_fall_errflag_p_o => acam_fall_errflag_p,
acam_rise_errflag_p_o => acam_rise_errflag_p, acam_rise_errflag_p_o => acam_rise_errflag_p,
...@@ -711,6 +714,7 @@ begin ...@@ -711,6 +714,7 @@ begin
-- these will evolve as we implement all the features -- these will evolve as we implement all the features
pulse_delay <= x"00000001"; pulse_delay <= x"00000001";
window_delay <= x"00000002";
mute_inputs_o <= '1'; mute_inputs_o <= '1';
term_en_1_o <= '1'; term_en_1_o <= '1';
term_en_2_o <= '1'; term_en_2_o <= '1';
...@@ -742,9 +746,6 @@ begin ...@@ -742,9 +746,6 @@ begin
end process; end process;
start_trig <= tdc_in_fpga_5_i; start_trig <= tdc_in_fpga_5_i;
start_from_fpga_o <= tdc_in_fpga_5_i;
start_dis_o <= '0';
end rtl; end rtl;
---------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------
......
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