diff --git a/hdl/syn/spec/Makefile b/hdl/syn/spec/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..645ab3cd25d5a690b51cbe559def2d5ef62b917e
--- /dev/null
+++ b/hdl/syn/spec/Makefile
@@ -0,0 +1,438 @@
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := wr_spec_tdc.xise
+ISE_CRAP := *.b wr_spec_tdc_summary.html *.tcl wr_spec_tdc.bld wr_spec_tdc.cmd_log *.drc wr_spec_tdc.lso *.ncd wr_spec_tdc.ngc wr_spec_tdc.ngd wr_spec_tdc.ngr wr_spec_tdc.pad wr_spec_tdc.par wr_spec_tdc.pcf wr_spec_tdc.prj wr_spec_tdc.ptwx wr_spec_tdc.stx wr_spec_tdc.syr wr_spec_tdc.twr wr_spec_tdc.twx wr_spec_tdc.gise $(PROJECT).gise wr_spec_tdc.bgn wr_spec_tdc.unroutes wr_spec_tdc.ut wr_spec_tdc.xpi wr_spec_tdc.xst wr_spec_tdc_bitgen.xwbt wr_spec_tdc_envsettings.html wr_spec_tdc_guide.ncd wr_spec_tdc_map.map wr_spec_tdc_map.mrp wr_spec_tdc_map.ncd wr_spec_tdc_map.ngm wr_spec_tdc_map.xrpt wr_spec_tdc_ngdbuild.xrpt wr_spec_tdc_pad.csv wr_spec_tdc_pad.txt wr_spec_tdc_par.xrpt wr_spec_tdc_summary.xml wr_spec_tdc_usage.xml wr_spec_tdc_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
+
+generate_tcl:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Synthesize - XST}" >> run.tcl
+		echo "process run {Translate}" >> run.tcl
+		echo "process run {Map}" >> run.tcl
+		echo "process run {Place & Route}" >> run.tcl
+		echo "process run {Generate Programming File}" >> run.tcl
+
+synthesis:
+		/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
+
+check_tool:
+		
+
+syn_post_cmd:
+		
+
+syn_pre_cmd:
+		
+
+#target for cleaning all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
+
+USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
+SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
+ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
+R_NAME:=greg/wr_spec_tdc
+PORT:=22
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
+endif
+ifeq (x$(ISE_PATH),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
+../../rtl/local_pps_gen.vhd \
+../../rtl/start_retrig_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
+../../rtl/acam_timecontrol_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
+../../rtl/fmc_tdc_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../rtl/timestamp_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
+../../rtl/tdc_eic.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+../../rtl/fmc_tdc_direct_readout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
+../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
+../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
+../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc \
+../../rtl/decr_counter.vhd \
+../../rtl/reg_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../rtl/incr_counter.vhd \
+run.tcl \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
+../../top/spec/wr_spec_tdc.ucf \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
+wr_spec_tdc.xise \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd \
+../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+../../rtl/leds_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../rtl/wrabbit_sync.vhd \
+../../rtl/carrier_info.vhd \
+../../rtl/fmc_tdc_direct_readout_slave.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+../../top/spec/wr_spec_tdc.vhd \
+../../rtl/acam_databus_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd \
+../../rtl/free_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd \
+../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
+../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd \
+../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
+../../rtl/tdc_core_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+../../top/spec/synthesis_descriptor.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../rtl/clks_rsts_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../rtl/fmc_tdc_wrapper.vhd \
+../../ip_cores/general-cores/modules/common/gc_reset.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
+../../rtl/timestamp_fifo_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/wr-cores/board/spec/wrc_board_spec.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd \
+../../rtl/fmc_tdc_mezzanine.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
+../../rtl/data_engine.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd \
+../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
+../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd \
+../../rtl/data_formatting.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd
+
+#target for running synthesis in the remote location
+remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
+		ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
+else
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
+endif
+
+
+sync: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
diff --git a/hdl/syn/spec/wr_spec_tdc.xise b/hdl/syn/spec/wr_spec_tdc.xise
index 990168ec379f423ffc850033204d2c731e276424..cc558cdc722125b0c62fa2bb832398ea377c706d 100644
--- a/hdl/syn/spec/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise
@@ -341,798 +341,1053 @@
   <libraries/>
 
   <files>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="../../top/spec/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
     </file>
     <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     </file>
-    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
     </file>
-    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
-    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+    </file>
+    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    <file xil_pn:name="../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+    </file>
+    <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
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     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
     </file>
-    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+    </file>
   </files>
 
   <bindings/>
diff --git a/hdl/syn/svec/Makefile b/hdl/syn/svec/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..67a4b2033cd30a779ffc5cbb423ddf49d0c6d888
--- /dev/null
+++ b/hdl/syn/svec/Makefile
@@ -0,0 +1,429 @@
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := wr_svec_tdc.xise
+ISE_CRAP := *.b wr_svec_tdc_summary.html *.tcl wr_svec_tdc.bld wr_svec_tdc.cmd_log *.drc wr_svec_tdc.lso *.ncd wr_svec_tdc.ngc wr_svec_tdc.ngd wr_svec_tdc.ngr wr_svec_tdc.pad wr_svec_tdc.par wr_svec_tdc.pcf wr_svec_tdc.prj wr_svec_tdc.ptwx wr_svec_tdc.stx wr_svec_tdc.syr wr_svec_tdc.twr wr_svec_tdc.twx wr_svec_tdc.gise $(PROJECT).gise wr_svec_tdc.bgn wr_svec_tdc.unroutes wr_svec_tdc.ut wr_svec_tdc.xpi wr_svec_tdc.xst wr_svec_tdc_bitgen.xwbt wr_svec_tdc_envsettings.html wr_svec_tdc_guide.ncd wr_svec_tdc_map.map wr_svec_tdc_map.mrp wr_svec_tdc_map.ncd wr_svec_tdc_map.ngm wr_svec_tdc_map.xrpt wr_svec_tdc_ngdbuild.xrpt wr_svec_tdc_pad.csv wr_svec_tdc_pad.txt wr_svec_tdc_par.xrpt wr_svec_tdc_summary.xml wr_svec_tdc_usage.xml wr_svec_tdc_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
+
+generate_tcl:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Synthesize - XST}" >> run.tcl
+		echo "process run {Translate}" >> run.tcl
+		echo "process run {Map}" >> run.tcl
+		echo "process run {Place & Route}" >> run.tcl
+		echo "process run {Generate Programming File}" >> run.tcl
+
+synthesis:
+		/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
+
+check_tool:
+		
+
+syn_post_cmd:
+		
+
+syn_pre_cmd:
+		
+
+#target for cleaning all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
+
+USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
+SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
+ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
+R_NAME:=greg/wr_svec_tdc
+PORT:=22
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
+endif
+ifeq (x$(ISE_PATH),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
+../../rtl/start_retrig_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
+../../rtl/acam_timecontrol_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
+../../rtl/fmc_tdc_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../rtl/timestamp_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
+../../rtl/tdc_eic.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+../../top/svec/wr_svec_tdc.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+../../rtl/fmc_tdc_direct_readout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
+../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
+../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd \
+../../top/svec/wr_svec_tdc.ucf \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
+../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+../../rtl/reg_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../rtl/incr_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
+../../rtl/decr_counter.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd \
+../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
+../../ip_cores/wr-cores/board/svec/wrc_board_svec.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+../../rtl/leds_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
+wr_svec_tdc.xise \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
+../../top/svec/synthesis_descriptor.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../rtl/wrabbit_sync.vhd \
+../../rtl/carrier_info.vhd \
+../../rtl/fmc_tdc_direct_readout_slave.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+../../rtl/acam_databus_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
+run.tcl \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd \
+../../rtl/free_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd \
+../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
+../../rtl/local_pps_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
+../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd \
+../../rtl/tdc_core_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../rtl/clks_rsts_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../rtl/fmc_tdc_wrapper.vhd \
+../../ip_cores/general-cores/modules/common/gc_reset.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd \
+../../ip_cores/wr-cores/board/svec/wr_svec_pkg.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
+../../rtl/timestamp_fifo_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/wr-cores/board/svec/xwrc_board_svec.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd \
+../../rtl/fmc_tdc_mezzanine.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
+../../rtl/data_engine.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd \
+../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
+../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd \
+../../rtl/data_formatting.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd
+
+#target for running synthesis in the remote location
+remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
+		ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
+else
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
+endif
+
+
+sync: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
diff --git a/hdl/syn/svec/wr_svec_tdc.xise b/hdl/syn/svec/wr_svec_tdc.xise
index 947adc59aa6f8d6aad6010d3d9c644e8494c4706..e1921842d1b4471119fcebb1b5eea8fb76a76fc4 100644
--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
@@ -138,7 +138,7 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_svec_tdc|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_svec_tdc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/wr_svec_tdc.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_svec_tdc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -361,959 +361,1020 @@
     <file xil_pn:name="../../top/svec/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../top/svec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+    </file>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/board/svec/wrc_board_svec.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
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-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
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     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
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     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
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-    </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
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     <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
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-    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    </file>
+    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
     </file>
   </files>
 
-  <bindings>
-    <binding xil_pn:location="/wr_svec_tdc" xil_pn:name="../../top/svec/wr_svec_tdc.ucf"/>
-  </bindings>
+  <bindings/>
 
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>