diff --git a/.gitignore b/.gitignore
index 58989e196d1c7343c61031ac974af6250c238c24..ddd5c2fbd77836173646e9a3a3c373544cebb9d2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,5 +7,9 @@ modelsim.ini
 *.vstf
 work
 *.bak
-syn/*
-transcript
\ No newline at end of file
+hdl/syn/*
+transcript
+work/
+NullFile
+*.orig
+*.html
\ No newline at end of file
diff --git a/.gitmodules b/.gitmodules
index 222a1c7a914d8c13d6a84d8ea77f470e9da0d8d2..559e1e895f7f0647acb810ec62aa45ab854a06ee 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
 [submodule "hdl/ip_cores/gn4124-core"]
 	path = hdl/ip_cores/gn4124-core
 	url = git://ohwr.org/hdl-core-lib/gn4124-core.git
+[submodule "hdl/ip_cores/etherbone-core"]
+	path = hdl/ip_cores/etherbone-core
+	url = git://ohwr.org/hdl-core-lib/etherbone-core.git
diff --git a/hdl/ip_cores/etherbone-core b/hdl/ip_cores/etherbone-core
new file mode 160000
index 0000000000000000000000000000000000000000..8489445985ff2afe6c72712014a92a271869f20a
--- /dev/null
+++ b/hdl/ip_cores/etherbone-core
@@ -0,0 +1 @@
+Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores
index 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980..5205d9754b1e0887df5914a47f8aa745e4f3c2fe 160000
--- a/hdl/ip_cores/general-cores
+++ b/hdl/ip_cores/general-cores
@@ -1 +1 @@
-Subproject commit 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980
+Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
diff --git a/hdl/ip_cores/gn4124-core b/hdl/ip_cores/gn4124-core
index 7082c5833a2569b24ad69d5f94269eaeff1c7af3..9b9625bb4270114266cd357f199d649f3d799f04 160000
--- a/hdl/ip_cores/gn4124-core
+++ b/hdl/ip_cores/gn4124-core
@@ -1 +1 @@
-Subproject commit 7082c5833a2569b24ad69d5f94269eaeff1c7af3
+Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
diff --git a/hdl/ip_cores/vme64x-core b/hdl/ip_cores/vme64x-core
index d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7..fa34d06e35ca0bfad8eac24aa51713e81639da64 160000
--- a/hdl/ip_cores/vme64x-core
+++ b/hdl/ip_cores/vme64x-core
@@ -1 +1 @@
-Subproject commit d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7
+Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
diff --git a/hdl/ip_cores/wr-cores b/hdl/ip_cores/wr-cores
index 598a2f6ccbf1ac937ff589c0797cd2a487306efe..69cc4cc3132530c836cd57ce1b282e8377fe7a07 160000
--- a/hdl/ip_cores/wr-cores
+++ b/hdl/ip_cores/wr-cores
@@ -1 +1 @@
-Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
+Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
diff --git a/hdl/rtl/fmc_tdc_core.vhd b/hdl/rtl/fmc_tdc_core.vhd
index 9dfa16763e1fa59d2703c29bdd25539e52ce895b..5b2a849a2cd89afd26a991f681e2144bc11d0164 100644
--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
@@ -156,77 +156,77 @@ use work.genram_pkg.all;
 --=================================================================================================
 entity fmc_tdc_core is
   generic
-    (g_span                 : integer := 32;                              -- address span in bus interfaces
-     g_width                : integer := 32;                              -- data width in bus interfaces
-     g_simulation       : boolean := FALSE);                          -- this generic is set to TRUE
-                                                                          -- when instantiated in a test-bench
+    (g_span       : integer := 32;      -- address span in bus interfaces
+     g_width      : integer := 32;      -- data width in bus interfaces
+     g_simulation : boolean := false);  -- this generic is set to TRUE
+                                        -- when instantiated in a test-bench
   port
     (
-      clk_sys_i : in std_logic;
+      clk_sys_i   : in std_logic;
       rst_n_sys_i : in std_logic;
 
-      clk_tdc_i             : in    std_logic;                            -- 125 MHz reference from the PLL 
-      rst_tdc_i                           : in    std_logic;                            -- global reset, synched to clk_tdc_i
+      clk_tdc_i : in std_logic;         -- 125 MHz reference from the PLL 
+      rst_tdc_i : in std_logic;         -- global reset, synched to clk_tdc_i
 
-      acam_refclk_r_edge_p_i : in    std_logic;                            -- rising edge on 31.25MHz ACAM reference clock
-      send_dac_word_p_o      : out   std_logic;                            -- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
-      dac_word_o             : out   std_logic_vector(23 downto 0);        -- new DAC configuration word from GN4124/VME
+      acam_refclk_r_edge_p_i : in    std_logic;  -- rising edge on 31.25MHz ACAM reference clock
+      send_dac_word_p_o      : out   std_logic;  -- command from GN4124/VME to reconfigure the TDC mezz DAC with dac_word_o
+      dac_word_o             : out   std_logic_vector(23 downto 0);  -- new DAC configuration word from GN4124/VME
       -- Signals for the timing interface with the ACAM on TDC mezzanine
-      start_from_fpga_o      : out   std_logic;                            -- start pulse
-      err_flag_i             : in    std_logic;                            -- error flag
-      int_flag_i             : in    std_logic;                            -- interrupt flag
-      start_dis_o            : out   std_logic;                            -- start disable, not used
-      stop_dis_o             : out   std_logic;                            -- disables all acam channels
+      start_from_fpga_o      : out   std_logic;  -- start pulse
+      err_flag_i             : in    std_logic;  -- error flag
+      int_flag_i             : in    std_logic;  -- interrupt flag
+      start_dis_o            : out   std_logic;  -- start disable, not used
+      stop_dis_o             : out   std_logic;  -- disables all acam channels
       -- Signals for the data interface with the ACAM on TDC mezzanine
       data_bus_io            : inout std_logic_vector(27 downto 0);
       address_o              : out   std_logic_vector(3 downto 0);
-      cs_n_o                 : out   std_logic;                            -- chip select   for ACAM
-      oe_n_o                 : out   std_logic;                            -- output enable for ACAM
-      rd_n_o                 : out   std_logic;                            -- read   signal for ACAM
-      wr_n_o                 : out   std_logic;                            -- write  signal for ACAM
-      ef1_i                  : in    std_logic;                            -- empty flag of ACAM iFIFO1
-      ef2_i                  : in    std_logic;                            -- empty flag of ACAM iFIFO2
+      cs_n_o                 : out   std_logic;  -- chip select   for ACAM
+      oe_n_o                 : out   std_logic;  -- output enable for ACAM
+      rd_n_o                 : out   std_logic;  -- read   signal for ACAM
+      wr_n_o                 : out   std_logic;  -- write  signal for ACAM
+      ef1_i                  : in    std_logic;  -- empty flag of ACAM iFIFO1
+      ef2_i                  : in    std_logic;  -- empty flag of ACAM iFIFO2
       -- Signals for the Input Logic on TDC mezzanine
-      enable_inputs_o        : out   std_logic;                            -- enables all 5 inputs
-      term_en_1_o            : out   std_logic;                            -- Ch.1 termination enable of 50 Ohm termination
-      term_en_2_o            : out   std_logic;                            -- Ch.2 termination enable of 50 Ohm termination
-      term_en_3_o            : out   std_logic;                            -- Ch.3 termination enable of 50 Ohm termination
-      term_en_4_o            : out   std_logic;                            -- Ch.4 termination enable of 50 Ohm termination
-      term_en_5_o            : out   std_logic;                            -- Ch.5 termination enable of 50 Ohm termination
+      enable_inputs_o        : out   std_logic;  -- enables all 5 inputs
+      term_en_1_o            : out   std_logic;  -- Ch.1 termination enable of 50 Ohm termination
+      term_en_2_o            : out   std_logic;  -- Ch.2 termination enable of 50 Ohm termination
+      term_en_3_o            : out   std_logic;  -- Ch.3 termination enable of 50 Ohm termination
+      term_en_4_o            : out   std_logic;  -- Ch.4 termination enable of 50 Ohm termination
+      term_en_5_o            : out   std_logic;  -- Ch.5 termination enable of 50 Ohm termination
       -- LEDs on TDC mezzanine
-      tdc_led_status_o       : out   std_logic;                            -- amber led on front pannel, division of clk_tdc_i
-      tdc_led_trig1_o        : out   std_logic;                            -- amber led on front pannel, Ch.1 termination
-      tdc_led_trig2_o        : out   std_logic;                            -- amber led on front pannel, Ch.2 termination
-      tdc_led_trig3_o        : out   std_logic;                            -- amber led on front pannel, Ch.3 termination
-      tdc_led_trig4_o        : out   std_logic;                            -- amber led on front pannel, Ch.4 termination
-      tdc_led_trig5_o        : out   std_logic;                            -- amber led on front pannel, Ch.5 termination
+      tdc_led_status_o       : out   std_logic;  -- amber led on front pannel, division of clk_tdc_i
+      tdc_led_trig1_o        : out   std_logic;  -- amber led on front pannel, Ch.1 termination
+      tdc_led_trig2_o        : out   std_logic;  -- amber led on front pannel, Ch.2 termination
+      tdc_led_trig3_o        : out   std_logic;  -- amber led on front pannel, Ch.3 termination
+      tdc_led_trig4_o        : out   std_logic;  -- amber led on front pannel, Ch.4 termination
+      tdc_led_trig5_o        : out   std_logic;  -- amber led on front pannel, Ch.5 termination
       -- TDC input signals, also arriving to the FPGA; not used currently
-      tdc_in_fpga_1_i        : in    std_logic;                            -- TDC input Ch.1, not used
-      tdc_in_fpga_2_i        : in    std_logic;                            -- TDC input Ch.2, not used
-      tdc_in_fpga_3_i        : in    std_logic;                            -- TDC input Ch.3, not used
-      tdc_in_fpga_4_i        : in    std_logic;                            -- TDC input Ch.4, not used
-      tdc_in_fpga_5_i        : in    std_logic;                            -- TDC input Ch.5, not used
+      tdc_in_fpga_1_i        : in    std_logic;  -- TDC input Ch.1, not used
+      tdc_in_fpga_2_i        : in    std_logic;  -- TDC input Ch.2, not used
+      tdc_in_fpga_3_i        : in    std_logic;  -- TDC input Ch.3, not used
+      tdc_in_fpga_4_i        : in    std_logic;  -- TDC input Ch.4, not used
+      tdc_in_fpga_5_i        : in    std_logic;  -- TDC input Ch.5, not used
 
 
 -- White Rabbit control and status registers
-      wrabbit_status_reg_i   : in    std_logic_vector(g_width-1 downto 0);
-      wrabbit_ctrl_reg_o     : out   std_logic_vector(g_width-1 downto 0);
+      wrabbit_status_reg_i : in  std_logic_vector(g_width-1 downto 0);
+      wrabbit_ctrl_reg_o   : out std_logic_vector(g_width-1 downto 0);
       -- White Rabbit timing
-      wrabbit_synched_i      : in    std_logic;
-      wrabbit_tai_p_i        : in    std_logic;
-      wrabbit_tai_i          : in    std_logic_vector(31 downto 0);
+      wrabbit_synched_i    : in  std_logic;
+      wrabbit_tai_p_i      : in  std_logic;
+      wrabbit_tai_i        : in  std_logic_vector(31 downto 0);
 
       -- WISHBONE bus interface with the GN4124/VME core for the configuration
       -- of the TDC core (clk_sys)
-      cfg_slave_i: in t_wishbone_slave_in;
-      cfg_slave_o: out t_wishbone_slave_out;
-      
+      cfg_slave_i : in  t_wishbone_slave_in;
+      cfg_slave_o : out t_wishbone_slave_out;
+
       timestamp_o     : out std_logic_vector(127 downto 0);
-      timestamp_stb_o : out  std_logic;
+      timestamp_stb_o : out std_logic;
 
       channel_enable_o : out std_logic_vector(4 downto 0);
-      irq_threshold_o : out std_logic_vector(9 downto 0);
-      irq_timeout_o : out std_logic_vector(9 downto 0)
+      irq_threshold_o  : out std_logic_vector(9 downto 0);
+      irq_timeout_o    : out std_logic_vector(9 downto 0)
       );
 end fmc_tdc_core;
 
@@ -237,44 +237,44 @@ end fmc_tdc_core;
 architecture rtl of fmc_tdc_core is
 
   -- ACAM communication
-  signal acm_adr                                            : std_logic_vector(7 downto 0);
-  signal acm_cyc, acm_stb, acm_we, acm_ack                  : std_logic;
-  signal acm_dat_r, acm_dat_w                               : std_logic_vector(g_width-1 downto 0);
-  signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta   : std_logic;
-  signal acam_errflag_f_edge_p, acam_errflag_r_edge_p       : std_logic;
-  signal acam_intflag_f_edge_p                              : std_logic;
-  signal acam_tstamp1, acam_tstamp2                         : std_logic_vector(g_width-1 downto 0);
-  signal acam_tstamp1_ok_p, acam_tstamp2_ok_p               : std_logic;
+  signal acm_adr                                             : std_logic_vector(7 downto 0);
+  signal acm_cyc, acm_stb, acm_we, acm_ack                   : std_logic;
+  signal acm_dat_r, acm_dat_w                                : std_logic_vector(g_width-1 downto 0);
+  signal acam_ef1, acam_ef2, acam_ef1_meta, acam_ef2_meta    : std_logic;
+  signal acam_errflag_f_edge_p, acam_errflag_r_edge_p        : std_logic;
+  signal acam_intflag_f_edge_p                               : std_logic;
+  signal acam_tstamp1, acam_tstamp2                          : std_logic_vector(g_width-1 downto 0);
+  signal acam_tstamp1_ok_p, acam_tstamp2_ok_p                : std_logic;
   -- control unit
-  signal activate_acq_p, deactivate_acq_p, load_acam_config : std_logic;
-  signal read_acam_config, read_acam_status, read_ififo1    : std_logic;
-  signal read_ififo2, read_start01, reset_acam, load_utc    : std_logic;
-  signal roll_over_incr_recent        : std_logic;
-  signal deactivate_chan                                    : std_logic_vector(4 downto 0);
-  signal pulse_delay, window_delay, clk_period              : std_logic_vector(g_width-1 downto 0);
-  signal starting_utc, acam_inputs_en                       : std_logic_vector(g_width-1 downto 0);
-  signal acam_ififo1, acam_ififo2, acam_start01             : std_logic_vector(g_width-1 downto 0);
-  signal irq_tstamp_threshold, irq_time_threshold           : std_logic_vector(g_width-1 downto 0);
-  signal local_utc                                : std_logic_vector(g_width-1 downto 0);
-  signal acam_config, acam_config_rdbk                      : config_vector;
-  signal start_from_fpga, state_active_p       : std_logic;
+  signal activate_acq_p, deactivate_acq_p, load_acam_config  : std_logic;
+  signal read_acam_config, read_acam_status, read_ififo1     : std_logic;
+  signal read_ififo2, read_start01, reset_acam, load_utc     : std_logic;
+  signal roll_over_incr_recent                               : std_logic;
+  signal deactivate_chan                                     : std_logic_vector(4 downto 0);
+  signal pulse_delay, window_delay, clk_period               : std_logic_vector(g_width-1 downto 0);
+  signal starting_utc, acam_inputs_en                        : std_logic_vector(g_width-1 downto 0);
+  signal acam_ififo1, acam_ififo2, acam_start01              : std_logic_vector(g_width-1 downto 0);
+  signal irq_tstamp_threshold, irq_time_threshold            : std_logic_vector(g_width-1 downto 0);
+  signal local_utc                                           : std_logic_vector(g_width-1 downto 0);
+  signal acam_config, acam_config_rdbk                       : config_vector;
+  signal start_from_fpga, state_active_p                     : std_logic;
   -- retrigger control
-  signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset: std_logic_vector(g_width-1 downto 0);
-  signal local_utc_p                                        : std_logic;
-  signal current_retrig_nb                                  : std_logic_vector(g_width-1 downto 0);
+  signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
+  signal local_utc_p                                         : std_logic;
+  signal current_retrig_nb                                   : std_logic_vector(g_width-1 downto 0);
   -- UTC
-  signal utc_p                                              : std_logic;
-  signal utc, wrabbit_ctrl_reg                              : std_logic_vector(g_width-1 downto 0);
+  signal utc_p                                               : std_logic;
+  signal utc, wrabbit_ctrl_reg                               : std_logic_vector(g_width-1 downto 0);
 
   -- LEDs
-  signal acam_channel                                       : std_logic_vector(5 downto 0);
-  signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3        : std_logic_vector(1 downto 0);
-  signal tdc_in_fpga_4, tdc_in_fpga_5                       : std_logic_vector(1 downto 0);
-  signal acam_tstamp_channel                                : std_logic_vector(2 downto 0);
+  signal acam_channel                                : std_logic_vector(5 downto 0);
+  signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
+  signal tdc_in_fpga_4, tdc_in_fpga_5                : std_logic_vector(1 downto 0);
+  signal acam_tstamp_channel                         : std_logic_vector(2 downto 0);
 
-  signal rst_sys: std_logic;
+  signal rst_sys         : std_logic;
   signal timestamp_valid : std_logic;
-  signal timestamp : std_logic_vector(127 downto 0);
+  signal timestamp       : std_logic_vector(127 downto 0);
 
 
 --=================================================================================================
@@ -287,59 +287,65 @@ begin
 ---------------------------------------------------------------------------------------------------
 --                                   TDC REGISTERS CONTROLLER                                    --
 ---------------------------------------------------------------------------------------------------
-  reg_control_block: reg_ctrl
-  generic map
-    (g_span                => g_span,
-     g_width               => g_width)
-  port map
-    (clk_tdc_i                 => clk_tdc_i,
-     rst_tdc_i                 => rst_tdc_i,
-     clk_sys_i => clk_sys_i,
+  reg_control_block : reg_ctrl
+    generic map
+    (g_span  => g_span,
+     g_width => g_width)
+    port map
+    (clk_tdc_i   => clk_tdc_i,
+     rst_tdc_i   => rst_tdc_i,
+     clk_sys_i   => clk_sys_i,
      rst_n_sys_i => rst_n_sys_i,
 
 
      slave_i => cfg_slave_i,
      slave_o => cfg_slave_o,
-     
-     activate_acq_p_o      => activate_acq_p,
-     deactivate_acq_p_o    => deactivate_acq_p,
-     acam_wr_config_p_o    => load_acam_config,
-     acam_rdbk_config_p_o  => read_acam_config,
-     acam_rdbk_status_p_o  => read_acam_status,
-     acam_rdbk_ififo1_p_o  => read_ififo1,
-     acam_rdbk_ififo2_p_o  => read_ififo2,
-     acam_rdbk_start01_p_o => read_start01,
-     acam_rst_p_o          => reset_acam,
-     load_utc_p_o          => load_utc,
-     acam_config_rdbk_i    => acam_config_rdbk,
-     acam_ififo1_i         => acam_ififo1,
-     acam_ififo2_i         => acam_ififo2,
-     acam_start01_i        => acam_start01,
-     local_utc_i           => utc,
-     irq_code_i            => x"00000000",
-     core_status_i         => x"00000000",
-     wrabbit_status_reg_i  => wrabbit_status_reg_i,
-     wrabbit_ctrl_reg_o    => wrabbit_ctrl_reg,
-     acam_config_o         => acam_config,
-     starting_utc_o        => starting_utc,
-     acam_inputs_en_o      => acam_inputs_en,
-     start_phase_o         => window_delay,
-     irq_tstamp_threshold_o=> irq_tstamp_threshold,
-     irq_time_threshold_o  => irq_time_threshold,
-     send_dac_word_p_o     => send_dac_word_p_o,
-     dac_word_o            => dac_word_o,
-     one_hz_phase_o        => pulse_delay);
-
-  irq_threshold_o <=irq_tstamp_threshold(9 downto 0);
-  irq_timeout_o <= irq_time_threshold(9 downto 0);
-  
-  
+
+     activate_acq_p_o       => activate_acq_p,
+     deactivate_acq_p_o     => deactivate_acq_p,
+     acam_wr_config_p_o     => load_acam_config,
+     acam_rdbk_config_p_o   => read_acam_config,
+     acam_rdbk_status_p_o   => read_acam_status,
+     acam_rdbk_ififo1_p_o   => read_ififo1,
+     acam_rdbk_ififo2_p_o   => read_ififo2,
+     acam_rdbk_start01_p_o  => read_start01,
+     acam_rst_p_o           => reset_acam,
+     load_utc_p_o           => load_utc,
+     acam_config_rdbk_i     => acam_config_rdbk,
+     acam_ififo1_i          => acam_ififo1,
+     acam_ififo2_i          => acam_ififo2,
+     acam_start01_i         => acam_start01,
+     local_utc_i            => utc,
+     irq_code_i             => x"00000000",
+     core_status_i          => x"00000000",
+     wrabbit_status_reg_i   => wrabbit_status_reg_i,
+     wrabbit_ctrl_reg_o     => wrabbit_ctrl_reg,
+     acam_config_o          => acam_config,
+     starting_utc_o         => starting_utc,
+     acam_inputs_en_o       => acam_inputs_en,
+     start_phase_o          => window_delay,
+     irq_tstamp_threshold_o => irq_tstamp_threshold,
+     irq_time_threshold_o   => irq_time_threshold,
+     send_dac_word_p_o      => send_dac_word_p_o,
+     dac_word_o             => dac_word_o,
+     one_hz_phase_o         => pulse_delay);
+
+  process(clk_tdc_i)
+  begin
+    if rising_edge(clk_tdc_i) then
+      irq_threshold_o <= irq_tstamp_threshold(9 downto 0);
+      irq_timeout_o   <= irq_time_threshold(9 downto 0);
+    end if;
+  end process;
+
+
+
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  wrabbit_ctrl_reg_o  <= wrabbit_ctrl_reg;
+  wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- termination enable registers
-  term_enable_regs: process (clk_tdc_i)
+  term_enable_regs : process (clk_tdc_i)
   begin
     if rising_edge (clk_tdc_i) then
       if rst_tdc_i = '1' then
@@ -364,10 +370,10 @@ begin
 ---------------------------------------------------------------------------------------------------
 --                                   LOCAL ONE HZ GENERATOR                                      --
 ---------------------------------------------------------------------------------------------------
-  local_one_second_block: local_pps_gen
-  generic map
-    (g_width                => g_width)
-  port map
+  local_one_second_block : local_pps_gen
+    generic map
+    (g_width => g_width)
+    port map
     (acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
      clk_i                  => clk_tdc_i,
      clk_period_i           => clk_period,
@@ -378,11 +384,11 @@ begin
      local_utc_o            => local_utc,
      local_utc_p_o          => local_utc_p);
 
-clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
+  clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
 ---------------------------------------------------------------------------------------------------
 --                                   ACAM TIMECONTROL INTERFACE                                  --
 ---------------------------------------------------------------------------------------------------
-  acam_timing_block: acam_timecontrol_interface
+  acam_timing_block : acam_timecontrol_interface
     port map
     (err_flag_i              => err_flag_i,
      int_flag_i              => int_flag_i,
@@ -405,43 +411,43 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
 ---------------------------------------------------------------------------------------------------
 --                                     ACAM DATABUS INTERFACE                                    --
 ---------------------------------------------------------------------------------------------------
-  acam_data_block: acam_databus_interface
-  port map
-    (ef1_i        => ef1_i,
-     ef2_i        => ef2_i,
-     data_bus_io  => data_bus_io,
-     adr_o        => address_o,
-     cs_n_o       => cs_n_o,
-     oe_n_o       => oe_n_o,
-     rd_n_o       => rd_n_o,
-     wr_n_o       => wr_n_o,
-     ef1_o        => acam_ef1,
-     ef1_meta_o   => acam_ef1_meta,
-     ef2_o        => acam_ef2,
-     ef2_meta_o   => acam_ef2_meta,
-     clk_i        => clk_tdc_i,
-     rst_i        => rst_tdc_i,
-     adr_i        => acm_adr,
-     cyc_i        => acm_cyc,
-     dat_i        => acm_dat_w,
-     stb_i        => acm_stb,
-     we_i         => acm_we,
-     ack_o        => acm_ack,
-     dat_o        => acm_dat_r);
+  acam_data_block : acam_databus_interface
+    port map
+    (ef1_i       => ef1_i,
+     ef2_i       => ef2_i,
+     data_bus_io => data_bus_io,
+     adr_o       => address_o,
+     cs_n_o      => cs_n_o,
+     oe_n_o      => oe_n_o,
+     rd_n_o      => rd_n_o,
+     wr_n_o      => wr_n_o,
+     ef1_o       => acam_ef1,
+     ef1_meta_o  => acam_ef1_meta,
+     ef2_o       => acam_ef2,
+     ef2_meta_o  => acam_ef2_meta,
+     clk_i       => clk_tdc_i,
+     rst_i       => rst_tdc_i,
+     adr_i       => acm_adr,
+     cyc_i       => acm_cyc,
+     dat_i       => acm_dat_w,
+     stb_i       => acm_stb,
+     we_i        => acm_we,
+     ack_o       => acm_ack,
+     dat_o       => acm_dat_r);
 
 
 ---------------------------------------------------------------------------------------------------
 --                                ACAM START RETRIGGER CONTROLLER                                --
 ---------------------------------------------------------------------------------------------------
-  start_retrigger_block: start_retrig_ctrl
-  generic map
-    (g_width                 => g_width)
-  port map
+  start_retrigger_block : start_retrig_ctrl
+    generic map
+    (g_width => g_width)
+    port map
     (acam_intflag_f_edge_p_i => acam_intflag_f_edge_p,
      clk_i                   => clk_tdc_i,
      utc_p_i                 => utc_p,
      rst_i                   => rst_tdc_i,
-     current_retrig_nb_o     => current_retrig_nb, -- for debug
+     current_retrig_nb_o     => current_retrig_nb,  -- for debug
      roll_over_incr_recent_o => roll_over_incr_recent,
      clk_i_cycles_offset_o   => clk_i_cycles_offset,
      roll_over_nb_o          => roll_over_nb,
@@ -451,10 +457,10 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
 ---------------------------------------------------------------------------------------------------
 --                                          DATA ENGINE                                          --
 ---------------------------------------------------------------------------------------------------
-  data_engine_block: data_engine
+  data_engine_block : data_engine
     generic map(
-      g_simulation => g_simulation )
-  port map
+      g_simulation => g_simulation)
+    port map
     (acam_ack_i            => acm_ack,
      acam_dat_i            => acm_dat_r,
      acam_adr_o            => acm_adr,
@@ -493,8 +499,8 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
 ---------------------------------------------------------------------------------------------------
 --                                       DATA FORMATTING                                         --
 ---------------------------------------------------------------------------------------------------
-  data_formatting_block: data_formatting
-  port map
+  data_formatting_block : data_formatting
+    port map
     (clk_i                   => clk_tdc_i,
      rst_i                   => rst_tdc_i,
      acam_tstamp1_i          => acam_tstamp1,
@@ -507,8 +513,8 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
      retrig_nb_offset_i      => retrig_nb_offset,
      utc_p_i                 => utc_p,
      utc_i                   => utc,
-     timestamp_o => timestamp,
-     timestamp_valid_o => timestamp_valid
+     timestamp_o             => timestamp,
+     timestamp_valid_o       => timestamp_valid
      );
 
 
@@ -519,16 +525,16 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
   utc_p <= wrabbit_tai_p_i when wrabbit_synched_i = '1' else local_utc_p;
 
   timestamp_stb_o <= timestamp_valid;
-  timestamp_o <= timestamp;
+  timestamp_o     <= timestamp;
 
 ---------------------------------------------------------------------------------------------------
 --                                              TDC LEDs                                         --
 ---------------------------------------------------------------------------------------------------  
-  TDCboard_leds: leds_manager
-  generic map
-    (g_width          => 32,
+  TDCboard_leds : leds_manager
+    generic map
+    (g_width      => 32,
      g_simulation => g_simulation)
-  port map
+    port map
     (clk_i            => clk_tdc_i,
      rst_i            => rst_tdc_i,
      utc_p_i          => local_utc_p,
diff --git a/hdl/rtl/timestamp_fifo.vhd b/hdl/rtl/timestamp_fifo.vhd
index ac16b2112ab57dcc12f4e5ac0507dc2c64c6aca0..f44d640405f14f7e7324fa67e6e3869feb838082 100644
--- a/hdl/rtl/timestamp_fifo.vhd
+++ b/hdl/rtl/timestamp_fifo.vhd
@@ -113,7 +113,7 @@ begin
       regs_i     => regs_in,
       regs_o     => regs_out);
 
-  buf_count <= unsigned(regs_out.fifo_wr_usedw_o);
+  buf_count <= resize(unsigned(regs_out.fifo_wr_usedw_o), 10);
 
   ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0';
   
diff --git a/hdl/rtl/timestamp_fifo_wb.vhd b/hdl/rtl/timestamp_fifo_wb.vhd
index d673990e59f4949ae5de5dce7168240159df2911..77598eab222b95404d6a7407eec4af344a8692f9 100644
--- a/hdl/rtl/timestamp_fifo_wb.vhd
+++ b/hdl/rtl/timestamp_fifo_wb.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : timestamp_fifo_wb.vhd
 -- Author         : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
--- Created        : Mon Apr 20 17:34:12 2015
+-- Created        : Wed Sep 20 18:41:08 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
@@ -89,26 +89,16 @@ signal tsf_csr_rst_seq_sync2                    : std_logic      ;
 signal tsf_fifo_full_int                        : std_logic      ;
 signal tsf_fifo_empty_int                       : std_logic      ;
 signal tsf_fifo_clear_bus_int                   : std_logic      ;
-signal tsf_fifo_usedw_int                       : std_logic_vector(9 downto 0);
+signal tsf_fifo_usedw_int                       : std_logic_vector(8 downto 0);
 signal ack_sreg                                 : std_logic_vector(9 downto 0);
 signal rddata_reg                               : std_logic_vector(31 downto 0);
 signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal bwsel_reg                                : std_logic_vector(3 downto 0);
 signal rwaddr_reg                               : std_logic_vector(3 downto 0);
 signal ack_in_progress                          : std_logic      ;
-signal wr_int                                   : std_logic      ;
-signal rd_int                                   : std_logic      ;
-signal allones                                  : std_logic_vector(31 downto 0);
-signal allzeros                                 : std_logic_vector(31 downto 0);
 
 begin
--- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
   wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
   process (clk_sys_i, rst_n_i)
@@ -310,7 +300,8 @@ begin
             rddata_reg(16) <= tsf_fifo_full_int;
             rddata_reg(17) <= tsf_fifo_empty_int;
             rddata_reg(18) <= '0';
-            rddata_reg(9 downto 0) <= tsf_fifo_usedw_int;
+            rddata_reg(8 downto 0) <= tsf_fifo_usedw_int;
+            rddata_reg(9) <= 'X';
             rddata_reg(10) <= 'X';
             rddata_reg(11) <= 'X';
             rddata_reg(12) <= 'X';
@@ -353,9 +344,9 @@ begin
   tsf_fifo_rst_n <= rst_n_i and (not tsf_fifo_clear_bus_int);
   tsf_fifo_INST : wbgen2_fifo_async
     generic map (
-      g_size               => 1024,
+      g_size               => 512,
       g_width              => 128,
-      g_usedw_size         => 10
+      g_usedw_size         => 9
     )
     port map (
       wr_req_i             => regs_i.fifo_wr_req_i,
diff --git a/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd b/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
index 770d9fcb04bf144e436316df84826edc44882fac..13f2a32916def97a54cbfef34a691be2e7d86575 100644
--- a/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
+++ b/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : timestamp_fifo_wbgen2_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
--- Created        : Mon Apr 20 17:34:12 2015
+-- Created        : Wed Sep 20 18:41:08 2017
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
@@ -51,7 +51,7 @@ package tsf_wbgen2_pkg is
     type t_tsf_out_registers is record
       fifo_wr_full_o                           : std_logic;
       fifo_wr_empty_o                          : std_logic;
-      fifo_wr_usedw_o                          : std_logic_vector(9 downto 0);
+      fifo_wr_usedw_o                          : std_logic_vector(8 downto 0);
       csr_last_valid_o                         : std_logic;
       csr_last_valid_load_o                    : std_logic;
       csr_rst_seq_o                            : std_logic;
diff --git a/hdl/rtl/wbgen/timestamp_fifo_wb.wb b/hdl/rtl/wbgen/timestamp_fifo_wb.wb
index 95fa4569fd191ed3ff12dcfd0fb43ea280826c87..743fa75a57a43a4a5214bd19bd6cc2ab32e18e71 100644
--- a/hdl/rtl/wbgen/timestamp_fifo_wb.wb
+++ b/hdl/rtl/wbgen/timestamp_fifo_wb.wb
@@ -9,7 +9,7 @@ peripheral {
 	 -- TXTSU shared FIFO
 
 	 fifo_reg {
-			size = 1024; -- or more. We'll see :)
+			size = 512; -- or more. We'll see :)
 			direction = CORE_TO_BUS;
 			prefix = "fifo";
 			name = "Timestamp FIFO";
diff --git a/hdl/syn/spec/Makefile b/hdl/syn/spec/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..645ab3cd25d5a690b51cbe559def2d5ef62b917e
--- /dev/null
+++ b/hdl/syn/spec/Makefile
@@ -0,0 +1,438 @@
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := wr_spec_tdc.xise
+ISE_CRAP := *.b wr_spec_tdc_summary.html *.tcl wr_spec_tdc.bld wr_spec_tdc.cmd_log *.drc wr_spec_tdc.lso *.ncd wr_spec_tdc.ngc wr_spec_tdc.ngd wr_spec_tdc.ngr wr_spec_tdc.pad wr_spec_tdc.par wr_spec_tdc.pcf wr_spec_tdc.prj wr_spec_tdc.ptwx wr_spec_tdc.stx wr_spec_tdc.syr wr_spec_tdc.twr wr_spec_tdc.twx wr_spec_tdc.gise $(PROJECT).gise wr_spec_tdc.bgn wr_spec_tdc.unroutes wr_spec_tdc.ut wr_spec_tdc.xpi wr_spec_tdc.xst wr_spec_tdc_bitgen.xwbt wr_spec_tdc_envsettings.html wr_spec_tdc_guide.ncd wr_spec_tdc_map.map wr_spec_tdc_map.mrp wr_spec_tdc_map.ncd wr_spec_tdc_map.ngm wr_spec_tdc_map.xrpt wr_spec_tdc_ngdbuild.xrpt wr_spec_tdc_pad.csv wr_spec_tdc_pad.txt wr_spec_tdc_par.xrpt wr_spec_tdc_summary.xml wr_spec_tdc_usage.xml wr_spec_tdc_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
+
+generate_tcl:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Synthesize - XST}" >> run.tcl
+		echo "process run {Translate}" >> run.tcl
+		echo "process run {Map}" >> run.tcl
+		echo "process run {Place & Route}" >> run.tcl
+		echo "process run {Generate Programming File}" >> run.tcl
+
+synthesis:
+		/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
+
+check_tool:
+		
+
+syn_post_cmd:
+		
+
+syn_pre_cmd:
+		
+
+#target for cleaning all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
+
+USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
+SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
+ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
+R_NAME:=greg/wr_spec_tdc
+PORT:=22
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
+endif
+ifeq (x$(ISE_PATH),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
+../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
+../../rtl/local_pps_gen.vhd \
+../../rtl/start_retrig_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd \
+../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
+../../rtl/acam_timecontrol_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd \
+../../rtl/fmc_tdc_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
+../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
+../../rtl/timestamp_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd \
+../../rtl/tdc_eic.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
+../../rtl/fmc_tdc_direct_readout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
+../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
+../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
+../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd \
+../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
+../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_path.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
+../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
+../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
+../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
+../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc \
+../../rtl/decr_counter.vhd \
+../../rtl/reg_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_fsm.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
+../../rtl/incr_counter.vhd \
+run.tcl \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd \
+../../top/spec/wr_spec_tdc.ucf \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_reg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
+../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
+../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
+../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
+../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
+../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
+../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
+../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_scubus_channel.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
+../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
+../../rtl/timestamp_fifo_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_detector.vhd \
+wr_spec_tdc.xise \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
+../../ip_cores/wr-cores/board/spec/wr_spec_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd \
+../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
+../../rtl/leds_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
+../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
+../../rtl/wrabbit_sync.vhd \
+../../rtl/carrier_info.vhd \
+../../rtl/fmc_tdc_direct_readout_slave.vhd \
+../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd \
+../../top/spec/wr_spec_tdc.vhd \
+../../rtl/acam_databus_interface.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_wb.vhd \
+../../rtl/free_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd \
+../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/escape_inserter.vhd \
+../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
+../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_diags_pkg.vhd \
+../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
+../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_auto_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd \
+../../ip_cores/wr-cores/board/spec/xwrc_board_spec.vhd \
+../../rtl/tdc_core_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
+../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
+../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
+../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
+../../top/spec/synthesis_descriptor.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
+../../rtl/clks_rsts_manager.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
+../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
+../../rtl/fmc_tdc_wrapper.vhd \
+../../ip_cores/general-cores/modules/common/gc_reset.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_msi.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_free.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd \
+../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/dropping_buffer.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
+../../rtl/timestamp_fifo_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/wr-cores/board/spec/wrc_board_spec.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd \
+../../rtl/fmc_tdc_mezzanine.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
+../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
+../../rtl/data_engine.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd \
+../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
+../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd \
+../../rtl/data_formatting.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd
+
+#target for running synthesis in the remote location
+remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
+		ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
+else
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
+endif
+
+
+sync: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
diff --git a/hdl/syn/spec/wr_spec_tdc.xise b/hdl/syn/spec/wr_spec_tdc.xise
index 990168ec379f423ffc850033204d2c731e276424..cc558cdc722125b0c62fa2bb832398ea377c706d 100644
--- a/hdl/syn/spec/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise
@@ -341,798 +341,1053 @@
   <libraries/>
 
   <files>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="../../top/spec/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
     </file>
     <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
     </file>
-    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
     </file>
-    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
-    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+    </file>
+    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    <file xil_pn:name="../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="133"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+    </file>
+    <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+    </file>
+    <file xil_pn:name="../../rtl/timestamp_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
+    </file>
+    <file xil_pn:name="../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_scan.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
+    </file>
+    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/board/common/xwrc_board_common.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    <file xil_pn:name="../../rtl/timestamp_fifo_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
     </file>
-    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/board/spec/wrc_board_spec.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+    <file xil_pn:name="../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
     </file>
-    <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
+    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
     </file>
-    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="177"/>
+    </file>
   </files>
 
   <bindings/>
diff --git a/hdl/syn/svec/Makefile b/hdl/syn/svec/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..67a4b2033cd30a779ffc5cbb423ddf49d0c6d888
--- /dev/null
+++ b/hdl/syn/svec/Makefile
@@ -0,0 +1,429 @@
+########################################
+#  This file was generated by hdlmake  #
+#  http://ohwr.org/projects/hdl-make/  #
+########################################
+
+PROJECT := wr_svec_tdc.xise
+ISE_CRAP := *.b wr_svec_tdc_summary.html *.tcl wr_svec_tdc.bld wr_svec_tdc.cmd_log *.drc wr_svec_tdc.lso *.ncd wr_svec_tdc.ngc wr_svec_tdc.ngd wr_svec_tdc.ngr wr_svec_tdc.pad wr_svec_tdc.par wr_svec_tdc.pcf wr_svec_tdc.prj wr_svec_tdc.ptwx wr_svec_tdc.stx wr_svec_tdc.syr wr_svec_tdc.twr wr_svec_tdc.twx wr_svec_tdc.gise $(PROJECT).gise wr_svec_tdc.bgn wr_svec_tdc.unroutes wr_svec_tdc.ut wr_svec_tdc.xpi wr_svec_tdc.xst wr_svec_tdc_bitgen.xwbt wr_svec_tdc_envsettings.html wr_svec_tdc_guide.ncd wr_svec_tdc_map.map wr_svec_tdc_map.mrp wr_svec_tdc_map.ncd wr_svec_tdc_map.ngm wr_svec_tdc_map.xrpt wr_svec_tdc_ngdbuild.xrpt wr_svec_tdc_pad.csv wr_svec_tdc_pad.txt wr_svec_tdc_par.xrpt wr_svec_tdc_summary.xml wr_svec_tdc_usage.xml wr_svec_tdc_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
+
+#target for performing local synthesis
+local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
+
+generate_tcl:
+		echo "project open $(PROJECT)" > run.tcl
+		echo "process run {Synthesize - XST}" >> run.tcl
+		echo "process run {Translate}" >> run.tcl
+		echo "process run {Map}" >> run.tcl
+		echo "process run {Place & Route}" >> run.tcl
+		echo "process run {Generate Programming File}" >> run.tcl
+
+synthesis:
+		/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
+
+check_tool:
+		
+
+syn_post_cmd:
+		
+
+syn_pre_cmd:
+		
+
+#target for cleaning all intermediate stuff
+clean:
+		rm -f $(ISE_CRAP)
+		rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
+
+#target for cleaning final files
+mrproper:
+		rm -f *.bit *.bin *.mcs
+
+.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
+
+USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
+SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
+ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
+R_NAME:=greg/wr_svec_tdc
+PORT:=22
+
+__test_for_remote_synthesis_variables:
+ifeq (x$(USER),x)
+	@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
+endif
+ifeq (x$(SERVER),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
+endif
+ifeq (x$(ISE_PATH),x)
+	@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
+endif
+
+CWD := $(shell pwd)
+
+FILES := ../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd \
+../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd \
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+../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
+../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd \
+../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc \
+../../rtl/timestamp_fifo_wb.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/xwrc_diags_wb.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
+../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
+../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
+../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
+../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
+../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
+../../ip_cores/wr-cores/board/svec/xwrc_board_svec.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_rmw.vhd \
+../../rtl/fmc_tdc_mezzanine.vhd \
+../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd \
+../../rtl/data_engine.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/tx_streamer.vhd \
+../../ip_cores/wr-cores/board/common/wr_board_pkg.vhd \
+../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
+../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd \
+../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
+../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd \
+../../rtl/data_formatting.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd \
+../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_queue_auto.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
+../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
+../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
+../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd \
+../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
+../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
+../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd \
+../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd
+
+#target for running synthesis in the remote location
+remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
+__send_back: __do_synthesis
+__do_synthesis: __send
+__send: __test_for_remote_synthesis_variables
+
+__send:
+		ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
+		rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
+
+__do_synthesis:
+ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
+		ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
+else
+		ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
+endif
+
+
+sync: 
+		cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
+
+#target for removing stuff from the remote location
+cleanremote:
+		ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
+
diff --git a/hdl/syn/svec/Manifest.py b/hdl/syn/svec/Manifest.py
index f45df84961f65504340e5a559c341d6f1320d28c..dce428519a3dab75f1380b8cfc66df8ad70a3fb8 100644
--- a/hdl/syn/svec/Manifest.py
+++ b/hdl/syn/svec/Manifest.py
@@ -8,5 +8,6 @@ syn_grade = "-3"
 syn_package = "fgg900"
 syn_top = "wr_svec_tdc"
 syn_project = "wr_svec_tdc.xise"
+syn_tool = "ise"
 
 modules = { "local" : [ "../../top/svec" ] }
diff --git a/hdl/syn/svec/wr_svec_tdc.xise b/hdl/syn/svec/wr_svec_tdc.xise
index 5b5107ba5aadebd1bf6649585c9f3cbab1dde70c..e1921842d1b4471119fcebb1b5eea8fb76a76fc4 100644
--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
@@ -36,7 +36,7 @@
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -138,7 +138,7 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_svec_tdc|rtl" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_svec_tdc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/wr_svec_tdc.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_svec_tdc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -182,7 +182,7 @@
     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -236,7 +236,7 @@
     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
@@ -352,798 +352,1026 @@
   <libraries/>
 
   <files>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="../../top/svec/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
     </file>
-    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
     </file>
-    <file xil_pn:name="../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
     </file>
-    <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
     </file>
-    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
     </file>
-    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
     </file>
-    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
     </file>
-    <file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tlu.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
     </file>
-    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
-    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/wrabbit_sync.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo_wb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
-    <file xil_pn:name="../../top/svec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
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-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
+    </file>
   </files>
 
   <bindings/>
diff --git a/hdl/top/spec/Manifest.py b/hdl/top/spec/Manifest.py
index c4644d0a7844b2da1c9581767c6b4fbf59471458..afcdf5c2a42be4da31b4c8d8a6b0906a0df45581 100644
--- a/hdl/top/spec/Manifest.py
+++ b/hdl/top/spec/Manifest.py
@@ -8,7 +8,11 @@ modules = {
     "local" : [	"../../rtl/", 
 		"../../ip_cores/gn4124-core",
 		"../../ip_cores/general-cores",
-		"../../ip_cores/wr-cores"
-	    ]
+		"../../ip_cores/wr-cores",
+                "../../ip_cores/wr-cores/board/spec"
+	    ],
+    "git"   :   [
+        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+        ],
     }
 
diff --git a/hdl/top/spec/synthesis_descriptor.vhd b/hdl/top/spec/synthesis_descriptor.vhd
index e2aa0d1d10aa9bc25a5597fa0b00e51228ae4cc0..6e3abf13183115566c4191e9d47ef727507fcbcd 100644
--- a/hdl/top/spec/synthesis_descriptor.vhd
+++ b/hdl/top/spec/synthesis_descriptor.vhd
@@ -1,57 +1,57 @@
--------------------------------------------------------------------------------
--- Title      : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
--- Project    : TDC FMC (fmc-tdc-1ns-5cha)
--------------------------------------------------------------------------------
--- File       : synthesis_descriptor.vhd
--- Author     : Evangelia Gousiou
--- Company    : CERN
--- Created    : 2013-04-16
--- Last update: 2013-04-16
--- Platform   : FPGA-generic
--- Standard   : VHDL'93
--------------------------------------------------------------------------------
--- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
--- Contains synthesis & source repository information.
--- Warning: this file is modified whenever a synthesis is executed.
--------------------------------------------------------------------------------
---
--- Copyright (c) 2013 CERN / BE-CO-HT
---
--- This source file is free software; you can redistribute it   
--- and/or modify it under the terms of the GNU Lesser General   
--- Public License as published by the Free Software Foundation; 
--- either version 2.1 of the License, or (at your option) any   
--- later version.                                               
---
--- This source is distributed in the hope that it will be       
--- useful, but WITHOUT ANY WARRANTY; without even the implied   
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
--- PURPOSE.  See the GNU Lesser General Public License for more 
--- details.                                                     
---
--- You should have received a copy of the GNU Lesser General    
--- Public License along with this source; if not, download it   
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
-library ieee;
-use ieee.STD_LOGIC_1164.all;
-use work.wishbone_pkg.all;
-
-package synthesis_descriptor is
-  
-constant c_sdb_synthesis_info : t_sdb_synthesis :=
-  (
-    syn_module_name => "wr_spec_tdc     ",
-    syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
-    syn_tool_name => "ISE     ",
-    syn_tool_version => x"00000147",
-    syn_date => x"20150522",
-    syn_username => "twlostow       ");
-
-constant c_sdb_repo_url : t_sdb_repo_url :=
-  (
-    repo_url => "http://svn.ohwr.org/fmc-tdc                                    " 
-  );
-
-end package synthesis_descriptor;
+-------------------------------------------------------------------------------
+-- Title      : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
+-- Project    : TDC FMC (fmc-tdc-1ns-5cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Evangelia Gousiou
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2017-09-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+  constant c_sdb_synthesis_info : t_sdb_synthesis :=
+    (
+      syn_module_name  => "wr_spec_tdc     ",
+      syn_commit_id    => "5765c94d3f0b118adcc9bfea880aca75",
+      syn_tool_name    => "ISE     ",
+      syn_tool_version => x"00000147",
+      syn_date         => x"20170920",
+      syn_username     => "twlostow       ");
+
+  constant c_sdb_repo_url : t_sdb_repo_url :=
+    (
+      repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git    "
+      );
+
+end package synthesis_descriptor;
diff --git a/hdl/top/spec/wr_spec_tdc.ucf b/hdl/top/spec/wr_spec_tdc.ucf
index 5320a1808a4395c4c5ca2db1dce1a965017d385e..36ccc8e4a70b89b1b35f7e0894dc9098856fcb53 100644
--- a/hdl/top/spec/wr_spec_tdc.ucf
+++ b/hdl/top/spec/wr_spec_tdc.ucf
@@ -38,136 +38,130 @@ TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
 ##################################################################### 
 ### Gennum ports
 ##################################################################### 
-NET "L_RST_N" LOC = N20;
-NET "L_RST_N" IOSTANDARD = "LVCMOS18";
-
-NET "GPIO[1]" LOC = U16;
-NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
-NET "GPIO[0]" LOC = AB19;
-NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
-
-NET "P2L_RDY" LOC = J16;
-NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
-
-NET "P2L_CLKN" LOC = M19;
-NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
-NET "P2L_CLKP" LOC = M20;
-NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
-NET "P2L_DATA[0]" LOC = K20;
-NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[1]" LOC = H22;
-NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[2]" LOC = H21;
-NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[3]" LOC = L17;
-NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[4]" LOC = K17;
-NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[5]" LOC = G22;
-NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[6]" LOC = G20;
-NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[7]" LOC = K18;
-NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[8]" LOC = K19;
-NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[9]" LOC = H20;
-NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[10]" LOC = J19;
-NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[11]" LOC = E22;
-NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[12]" LOC = E20;
-NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[13]" LOC = F22;
-NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[14]" LOC = F21;
-NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
-NET "P2L_DATA[15]" LOC = H19;
-NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
-
-
-NET "P2L_DFRAME" LOC = J22;
-NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
-
-NET "P2L_VALID" LOC = L19;
-NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
-
-NET "P_WR_REQ[0]" LOC = M22;
-NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
-NET "P_WR_REQ[1]" LOC = M21;
-NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
-
-NET "P_WR_RDY[0]" LOC = L15;
-NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "P_WR_RDY[1]" LOC = K16;
-NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
-
-NET "RX_ERROR" LOC = J17;
-NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
-
-
-
-NET "L2P_DATA[0]" LOC = P16;
-NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[1]" LOC = P21;
-NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[2]" LOC = P18;
-NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[3]" LOC = T20;
-NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[4]" LOC = V21;
-NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[5]" LOC = V19;
-NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[6]" LOC = W22;
-NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[7]" LOC = Y22;
-NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[8]" LOC = P22;
-NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[9]" LOC = R22;
-NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[10]" LOC = T21;
-NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[11]" LOC = T19;
-NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[12]" LOC = V22;
-NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[13]" LOC = V20;
-NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[14]" LOC = W20;
-NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DATA[15]" LOC = Y21;
-NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
-NET "L2P_DFRAME" LOC = U22;
-NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
-NET "L2P_VALID" LOC = T18;
-NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
-NET "L2P_CLKN" LOC = K22;
-NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
-NET "L2P_CLKP" LOC = K21;
-NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
-NET "L2P_EDB" LOC = U20;
-NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
-
-
-NET "L2P_RDY" LOC = U19;
-NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
-NET "L_WR_RDY[0]" LOC = R20;
-NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "L_WR_RDY[1]" LOC = T22;
-NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
-NET "P_RD_D_RDY[0]" LOC = N16;
-NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "P_RD_D_RDY[1]" LOC = P19;
-NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
-NET "TX_ERROR" LOC = M17;
-NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
-NET "VC_RDY[0]" LOC = B21;
-NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
-NET "VC_RDY[1]" LOC = B22;
-NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_rst_n" LOC = N20;
+NET "gn_rst_n" IOSTANDARD = "LVCMOS18";
+
+NET "gn_gpio[1]" LOC = U16;
+NET "gn_gpio[1]" IOSTANDARD = "LVCMOS25";
+NET "gn_gpio[0]" LOC = AB19;
+NET "gn_gpio[0]" IOSTANDARD = "LVCMOS25";
+
+NET "gn_p2l_rdy" LOC = J16;
+NET "gn_p2l_rdy" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_clkn" LOC = M19;
+NET "gn_p2l_clkn" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_clkp" LOC = M20;
+NET "gn_p2l_clkp" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_p2l_data[0]" LOC = K20;
+NET "gn_p2l_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[1]" LOC = H22;
+NET "gn_p2l_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[2]" LOC = H21;
+NET "gn_p2l_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[3]" LOC = L17;
+NET "gn_p2l_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[4]" LOC = K17;
+NET "gn_p2l_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[5]" LOC = G22;
+NET "gn_p2l_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[6]" LOC = G20;
+NET "gn_p2l_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[7]" LOC = K18;
+NET "gn_p2l_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[8]" LOC = K19;
+NET "gn_p2l_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[9]" LOC = H20;
+NET "gn_p2l_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[10]" LOC = J19;
+NET "gn_p2l_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[11]" LOC = E22;
+NET "gn_p2l_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[12]" LOC = E20;
+NET "gn_p2l_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[13]" LOC = F22;
+NET "gn_p2l_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[14]" LOC = F21;
+NET "gn_p2l_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_data[15]" LOC = H19;
+NET "gn_p2l_data[15]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p2l_dframe" LOC = J22;
+NET "gn_p2l_dframe" IOSTANDARD = "SSTL18_I";
+NET "gn_p2l_valid" LOC = L19;
+NET "gn_p2l_valid" IOSTANDARD = "SSTL18_I";
+
+NET "gn_p_wr_req[0]" LOC = M22;
+NET "gn_p_wr_req[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_req[1]" LOC = M21;
+NET "gn_p_wr_req[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[0]" LOC = L15;
+NET "gn_p_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_wr_rdy[1]" LOC = K16;
+NET "gn_p_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+
+NET "gn_rx_error" LOC = J17;
+NET "gn_rx_error" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_data[0]" LOC = P16;
+NET "gn_l2p_data[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[1]" LOC = P21;
+NET "gn_l2p_data[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[2]" LOC = P18;
+NET "gn_l2p_data[2]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[3]" LOC = T20;
+NET "gn_l2p_data[3]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[4]" LOC = V21;
+NET "gn_l2p_data[4]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[5]" LOC = V19;
+NET "gn_l2p_data[5]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[6]" LOC = W22;
+NET "gn_l2p_data[6]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[7]" LOC = Y22;
+NET "gn_l2p_data[7]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[8]" LOC = P22;
+NET "gn_l2p_data[8]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[9]" LOC = R22;
+NET "gn_l2p_data[9]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[10]" LOC = T21;
+NET "gn_l2p_data[10]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[11]" LOC = T19;
+NET "gn_l2p_data[11]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[12]" LOC = V22;
+NET "gn_l2p_data[12]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[13]" LOC = V20;
+NET "gn_l2p_data[13]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[14]" LOC = W20;
+NET "gn_l2p_data[14]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_data[15]" LOC = Y21;
+NET "gn_l2p_data[15]" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_dframe" LOC = U22;
+NET "gn_l2p_dframe" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_valid" LOC = T18;
+NET "gn_l2p_valid" IOSTANDARD = "SSTL18_I";
+NET "gn_l2p_clkn" LOC = K22;
+NET "gn_l2p_clkn" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_clkp" LOC = K21;
+NET "gn_l2p_clkp" IOSTANDARD = "DIFF_SSTL18_I";
+NET "gn_l2p_edb" LOC = U20;
+NET "gn_l2p_edb" IOSTANDARD = "SSTL18_I";
+
+NET "gn_l2p_rdy" LOC = U19;
+NET "gn_l2p_rdy" IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[0]" LOC = R20;
+NET "gn_l_wr_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_l_wr_rdy[1]" LOC = T22;
+NET "gn_l_wr_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[0]" LOC = N16;
+NET "gn_p_rd_d_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_p_rd_d_rdy[1]" LOC = P19;
+NET "gn_p_rd_d_rdy[1]" IOSTANDARD = "SSTL18_I";
+NET "gn_tx_error" LOC = M17;
+NET "gn_tx_error" IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[0]" LOC = B21;
+NET "gn_vc_rdy[0]" IOSTANDARD = "SSTL18_I";
+NET "gn_vc_rdy[1]" LOC = B22;
+NET "gn_vc_rdy[1]" IOSTANDARD = "SSTL18_I";
 
 #----------------------------------------
 # FMC slot
@@ -343,24 +337,22 @@ NET "tdc_in_fpga_1_i" IOSTANDARD = "LVCMOS25";
 #----------------------------------------
 # Carrier Generic Stuff
 #----------------------------------------
-NET "led_red" LOC = D5;
-NET "led_red" IOSTANDARD = "LVCMOS25";
-NET "led_green" LOC = E5;
-NET "led_green" IOSTANDARD = "LVCMOS25";
-NET "dac_cs1_n_o" LOC = A3;
-NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";
-NET "dac_cs2_n_o" LOC = B3;
-NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";
+NET "led_act_o" LOC = D5;
+NET "led_act_o" IOSTANDARD = "LVCMOS25";
+NET "led_link_o" LOC = E5;
+NET "led_link_o" IOSTANDARD = "LVCMOS25";
+NET "wr_25dac_cs_n_o" LOC = A3;
+NET "wr_25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
+NET "wr_20dac_cs_n_o" LOC = B3;
+NET "wr_20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
 #NET "dac_clr_n_o" LOC = F7;
 #NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
-NET "dac_din_o" LOC = C4;
-NET "dac_din_o" IOSTANDARD = "LVCMOS25";
-NET "dac_sclk_o" LOC = A4;
-NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_din_o" LOC = C4;
+NET "wr_dac_din_o" IOSTANDARD = "LVCMOS25";
+NET "wr_dac_sclk_o" LOC = A4;
+NET "wr_dac_sclk_o" IOSTANDARD = "LVCMOS25";
 NET "button1_i" LOC = C22;
 NET "button1_i" IOSTANDARD = "LVCMOS18";
-NET "button2_i" LOC = D21;
-NET "button2_i" IOSTANDARD = "LVCMOS18";
 
 
 #----------------------------------------
@@ -373,12 +365,12 @@ NET "sfp_txn_o" LOC= A16;
 
 NET "sfp_mod_def1_b" LOC = C17;
 NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
-NET "sfp_mod_def0_b" LOC = G15;
-NET "sfp_mod_def0_b" IOSTANDARD = "LVCMOS25";
+NET "sfp_mod_def0_i" LOC = G15;
+NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
 NET "sfp_mod_def2_b" LOC = G16;
 NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
-NET "sfp_rate_select_b" LOC = H14;
-NET "sfp_rate_select_b" IOSTANDARD = "LVCMOS25";
+NET "sfp_rate_select_o" LOC = H14;
+NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
 NET "sfp_tx_fault_i" LOC = A17;
 NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
 NET "sfp_tx_disable_o" LOC = F17;
@@ -394,37 +386,46 @@ NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
 NET "uart_txd_o" LOC= B2;
 NET "uart_txd_o" IOSTANDARD=LVCMOS25;
 
+#----------------------------------------
+# Flash memory SPI interface
+#----------------------------------------
+NET "flash_ncs_o"  LOC = AA3;
+NET "flash_ncs_o"  IOSTANDARD = "LVCMOS25";
+NET "flash_sclk_o" LOC = Y20;
+NET "flash_sclk_o" IOSTANDARD = "LVCMOS25";
+NET "flash_mosi_o" LOC = AB20;
+NET "flash_mosi_o" IOSTANDARD = "LVCMOS25";
+NET "flash_miso_i" LOC = AA20;
+NET "flash_miso_i" IOSTANDARD = "LVCMOS25";
+
 
 #----------------------------------------
 # False Path
 #----------------------------------------
 # GN4124
-NET "l_rst_n" TIG;
+NET "gn_rst_n" TIG;
 NET "cmp_gn4124_core/rst_*" TIG;
 NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
 TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
 
 
-NET "clk_62m5_sys" TNM_NET = clk_62m5_sys;
-TIMESPEC ts_ignore_crossclock = FROM "clk_62m5_sys" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
-TIMESPEC ts_ignore_crossclock2 = FROM "tdc_clk_125m_p_i" TO "clk_62m5_sys" 10ns  DATAPATHONLY;
-TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "clk_125m_pllref_n_i" 10ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_62m5_sys" 10ns DATAPATHONLY;
+NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
+TIMESPEC ts_ignore_crossclock = FROM "clk_sys_62m5" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
+TIMESPEC ts_ignore_crossclock2 = FROM "tdc_clk_125m_p_i" TO "clk_sys_62m5" 10ns  DATAPATHONLY;
+TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "clk_125m_pllref_n_i" 10ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_sys_62m5" 10ns DATAPATHONLY;
 
-TIMESPEC ts_x3 = FROM "clk_62m5_sys" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
-TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
+TIMESPEC ts_x3 = FROM "clk_sys_62m5" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
+TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_sys_62m5" 10ns DATAPATHONLY;
 
 
-##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
-TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
-
-#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
-INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
-TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 2 ns DATAPATHONLY;
-#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/05/19
-NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
-TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
+#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
+NET "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
 NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
 TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
+
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
diff --git a/hdl/top/spec/wr_spec_tdc.vhd b/hdl/top/spec/wr_spec_tdc.vhd
index 8913af0523c86ae9a91646d69a94f28231f0a18a..fbf1eb82ef3adb5865f11fc12db66214189651de 100644
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -74,6 +74,7 @@
 --                                                                                                |
 -- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
 --              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+--              Grzegorz Daniluk  (Grzegorz.Daniluk@cern.ch)
 -- Date         06/2014                                                                           |
 -- Version      v6                                                                                |
 -- Depends on                                                                                     |
@@ -97,6 +98,7 @@
 --     04/2013  v4  EG  added SDB; fixed bugs in data_formatting; added carrier CSR information   |
 --     01/2014  v5  EG  added VIC and EIC in the TDC mezzanine                                    |
 --     06/2014  v6  EG  added White Rabbit support                                                |
+--     12/2017  v7  GD  Top file reorganized to benefit from WRPC Board wrapper.                  |
 --                                                                                                |
 ---------------------------------------------------------------------------------------------------
 
@@ -113,9 +115,6 @@
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
 ---------------------------------------------------------------------------------------------------
 
---=================================================================================================
---                                       Libraries & Packages
---=================================================================================================
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
@@ -124,162 +123,142 @@ use work.gn4124_core_pkg.all;
 use work.gencores_pkg.all;
 use work.synthesis_descriptor.all;
 use work.wishbone_pkg.all;
-use work.wrcore_pkg.all;
-use work.wr_fabric_pkg.all;
-use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_spec_pkg.all;
 
 library UNISIM;
 use UNISIM.vcomponents.all;
 
-
---=================================================================================================
---                            Entity declaration for wr_spec_tdc
---=================================================================================================
 entity wr_spec_tdc is
   generic
-    (g_with_wr_phy : boolean := true;
-     g_simulation  : boolean := false);    -- this generic is set to TRUE
-                                           -- when instantiated in a test-bench
-  port
-    (                                      -- SPEC carrier
-      clk_125m_pllref_p_i : in std_logic;  -- 125 MHz PLL reference
-      clk_125m_pllref_n_i : in std_logic;
-
-      clk_125m_gtp_n_i : in std_logic;  -- 125 MHz GTP reference
-      clk_125m_gtp_p_i : in std_logic;
-
-      clk_20m_vcxo_i : in std_logic;    -- 20 MHz VCXO
-
-      dac_sclk_o  : out std_logic;      -- PLL VCXO DAC Drive
-      dac_din_o   : out std_logic;
-      dac_cs1_n_o : out std_logic;
-      dac_cs2_n_o : out std_logic;
-
-      sfp_txp_o         : out   std_logic;  -- SFP
-      sfp_txn_o         : out   std_logic;
-      sfp_rxp_i         : in    std_logic := '0';
-      sfp_rxn_i         : in    std_logic := '1';
-      sfp_mod_def0_b    : in    std_logic;  -- SFP detect pin
-      sfp_mod_def1_b    : inout std_logic;  -- SFP scl
-      sfp_mod_def2_b    : inout std_logic;  -- SFP sda
-      sfp_rate_select_b : inout std_logic := '0';
-      sfp_tx_fault_i    : in    std_logic := '0';
-      sfp_tx_disable_o  : out   std_logic;
-      sfp_los_i         : in    std_logic := '0';
-
-      uart_rxd_i : in  std_logic := '1';  -- UART
-      uart_txd_o : out std_logic;
-
-      carrier_scl_b : inout std_logic;  -- SPEC EEPROM
-      carrier_sda_b : inout std_logic;
-
-      carrier_onewire_b : inout std_logic;  -- SPEC 1-wire
-
-      button1_i : in std_logic := '1';
-      button2_i : in std_logic := '1';
-
-      ------------------------------------------------------------------------
-      -- GN4124 PCI bridge pins
-      ------------------------------------------------------------------------
-      
-      l_rst_n : in std_logic;           -- reset from gn4124 (rstout18_n)
-      
-      -- general purpose interface
-      gpio       : inout std_logic_vector(1 downto 0);  -- gpio[0] -> gn4124 gpio8
-                                        -- gpio[1] -> gn4124 gpio9
-      -- pcie to local [inbound data] - rx
-      p2l_rdy    : out   std_logic;     -- rx buffer full flag
-      p2l_clkn   : in    std_logic;     -- receiver source synchronous clock-
-      p2l_clkp   : in    std_logic;     -- receiver source synchronous clock+
-      p2l_data   : in    std_logic_vector(15 downto 0);  -- parallel receive data
-      p2l_dframe : in    std_logic;     -- receive frame
-      p2l_valid  : in    std_logic;     -- receive data valid
-
-      -- inbound buffer request/status
-      p_wr_req : in  std_logic_vector(1 downto 0);  -- pcie write request
-      p_wr_rdy : out std_logic_vector(1 downto 0);  -- pcie write ready
-      rx_error : out std_logic;                     -- receive error
-
-      -- local to parallel [outbound data] - tx
-      l2p_data   : out std_logic_vector(15 downto 0);  -- parallel transmit data
-      l2p_dframe : out std_logic;       -- transmit data frame
-      l2p_valid  : out std_logic;       -- transmit data valid
-      l2p_clkn   : out std_logic;  -- transmitter source synchronous clock-
-      l2p_clkp   : out std_logic;  -- transmitter source synchronous clock+
-      l2p_edb    : out std_logic;       -- packet termination and discard
-
-      -- outbound buffer status
-      l2p_rdy    : in std_logic;        -- tx buffer full flag
-      l_wr_rdy   : in std_logic_vector(1 downto 0);  -- local-to-pcie write
-      p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- pcie-to-local read response data ready
-      tx_error   : in std_logic;        -- transmit error
-      vc_rdy     : in std_logic_vector(1 downto 0);  -- channel ready
-
-      -- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
-      pll_sclk_o       : out std_logic;  -- SPI clock
-      pll_sdi_o        : out std_logic;  -- data line for PLL and DAC
-      pll_cs_o         : out std_logic;  -- PLL chip select
-      pll_dac_sync_o   : out std_logic;  -- DAC chip select
-      pll_sdo_i        : in  std_logic;  -- not used for the moment
-      pll_status_i     : in  std_logic;  -- PLL Digital Lock Detect, active high
-      tdc_clk_125m_p_i : in  std_logic;  -- 125 MHz differential clock: system clock
-      tdc_clk_125m_n_i : in  std_logic;  -- 125 MHz differential clock: system clock
-      acam_refclk_p_i  : in  std_logic;  -- 31.25 MHz differential clock: ACAM ref clock
-      acam_refclk_n_i  : in  std_logic;  -- 31.25 MHz differential clock: ACAM ref clock
-
-      -- Timing interface with the ACAM on TDC mezzanine
-      start_from_fpga_o : out   std_logic;  -- start signal
-      err_flag_i        : in    std_logic;  -- error flag
-      int_flag_i        : in    std_logic;  -- interrupt flag
-      start_dis_o       : out   std_logic;  -- start disable, not used
-      stop_dis_o        : out   std_logic;  -- stop disable, not used
-      -- Data interface with the ACAM on TDC mezzanine
-      data_bus_io       : inout std_logic_vector(27 downto 0);
-      address_o         : out   std_logic_vector(3 downto 0);
-      cs_n_o            : out   std_logic;  -- chip select for ACAM
-      oe_n_o            : out   std_logic;  -- output enable for ACAM
-      rd_n_o            : out   std_logic;  -- read  signal for ACAM
-      wr_n_o            : out   std_logic;  -- write signal for ACAM
-      ef1_i             : in    std_logic;  -- empty flag iFIFO1
-      ef2_i             : in    std_logic;  -- empty flag iFIFO2
-
-      -- Enable of input Logic on TDC mezzanine
-      enable_inputs_o : out std_logic;  -- enables all 5 inputs
-      term_en_1_o     : out std_logic;  -- Ch.1 termination enable of 50 Ohm termination
-      term_en_2_o     : out std_logic;  -- Ch.2 termination enable of 50 Ohm termination
-      term_en_3_o     : out std_logic;  -- Ch.3 termination enable of 50 Ohm termination
-      term_en_4_o     : out std_logic;  -- Ch.4 termination enable of 50 Ohm termination
-      term_en_5_o     : out std_logic;  -- Ch.5 termination enable of 50 Ohm termination
-
-      -- LEDs on TDC mezzanine
-      tdc_led_status_o : out std_logic;  -- amber led on front pannel, division of 125 MHz tdc_clk
-      tdc_led_trig1_o  : out std_logic;  -- amber led on front pannel, Ch.1 enable
-      tdc_led_trig2_o  : out std_logic;  -- amber led on front pannel, Ch.2 enable
-      tdc_led_trig3_o  : out std_logic;  -- amber led on front pannel, Ch.3 enable
-      tdc_led_trig4_o  : out std_logic;  -- amber led on front pannel, Ch.4 enable
-      tdc_led_trig5_o  : out std_logic;  -- amber led on front pannel, Ch.5 enable
-
-      -- Input Logic on TDC mezzanine (not used currently)
-      tdc_in_fpga_1_i : in std_logic;   -- Ch.1 for ACAM, also received by FPGA
-      tdc_in_fpga_2_i : in std_logic;   -- Ch.2 for ACAM, also received by FPGA
-      tdc_in_fpga_3_i : in std_logic;   -- Ch.3 for ACAM, also received by FPGA
-      tdc_in_fpga_4_i : in std_logic;   -- Ch.4 for ACAM, also received by FPGA
-      tdc_in_fpga_5_i : in std_logic;   -- Ch.5 for ACAM, also received by FPGA
-
-      -- I2C EEPROM interface on TDC mezzanine
-      mezz_sys_scl_b : inout std_logic := '1';  -- Mezzanine system EEPROM I2C clock
-      mezz_sys_sda_b : inout std_logic := '1';  -- Mezzanine system EEPROM I2C data
-
-      -- 1-wire interface on TDC mezzanine
-      mezz_onewire_b : inout std_logic;
-
-      -- font panel leds
-      led_red   : out std_logic;
-      led_green : out std_logic;
-
-      -- Carrier other signals
-      pcb_ver_i     : in std_logic_vector(3 downto 0);  -- PCB version
-      prsnt_m2c_n_i : in std_logic);    -- Mezzanine presence (active low)
+    (g_simulation  : boolean := false);  -- this generic is set to TRUE
+                                         -- when instantiated in a test-bench
+  port(
+    clk_125m_pllref_p_i : in std_logic;  -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+    clk_125m_gtp_n_i    : in std_logic;  -- 125 MHz GTP reference
+    clk_125m_gtp_p_i    : in std_logic;
+    clk_20m_vcxo_i      : in std_logic;  -- 20 MHz VCXO
+
+    wr_dac_sclk_o   : out std_logic;     -- PLL VCXO DAC Drive
+    wr_dac_din_o    : out std_logic;
+    wr_25dac_cs_n_o : out std_logic;
+    wr_20dac_cs_n_o : out std_logic;
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic := '0';
+    sfp_rxn_i         : in    std_logic := '1';
+    sfp_mod_def0_i    : in    std_logic;  -- SFP detect pin
+    sfp_mod_def1_b    : inout std_logic;  -- SFP scl
+    sfp_mod_def2_b    : inout std_logic;  -- SFP sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic := '0';
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic := '0';
+
+    uart_rxd_i        : in    std_logic := '1';
+    uart_txd_o        : out   std_logic;
+    flash_sclk_o      : out   std_logic;
+    flash_ncs_o       : out   std_logic;
+    flash_mosi_o      : out   std_logic;
+    flash_miso_i      : in    std_logic;
+    carrier_onewire_b : inout std_logic;  -- SPEC 1-wire
+    button1_i         : in    std_logic := '1';
+
+    ------------------------------------------------------------------------
+    -- GN4124 PCI bridge pins
+    ------------------------------------------------------------------------
+
+    gn_rst_n   : in std_logic;           -- reset from gn4124 (rstout18_n)
+    -- general purpose interface
+    gn_gpio    : inout std_logic_vector(1 downto 0);  -- gpio[0] -> gn4124 gpio8
+    -- pcie to local [inbound data] - rx
+    gn_p2l_rdy    : out   std_logic;     -- rx buffer full flag
+    gn_p2l_clkn   : in    std_logic;     -- receiver source synchronous clock-
+    gn_p2l_clkp   : in    std_logic;     -- receiver source synchronous clock+
+    gn_p2l_data   : in    std_logic_vector(15 downto 0);  -- parallel receive data
+    gn_p2l_dframe : in    std_logic;     -- receive frame
+    gn_p2l_valid  : in    std_logic;     -- receive data valid
+    -- inbound buffer request/status
+    gn_p_wr_req : in  std_logic_vector(1 downto 0);  -- pcie write request
+    gn_p_wr_rdy : out std_logic_vector(1 downto 0);  -- pcie write ready
+    gn_rx_error : out std_logic;                     -- receive error
+    -- local to parallel [outbound data] - tx
+    gn_l2p_data   : out std_logic_vector(15 downto 0);  -- parallel transmit data
+    gn_l2p_dframe : out std_logic;       -- transmit data frame
+    gn_l2p_valid  : out std_logic;       -- transmit data valid
+    gn_l2p_clkn   : out std_logic;  -- transmitter source synchronous clock-
+    gn_l2p_clkp   : out std_logic;  -- transmitter source synchronous clock+
+    gn_l2p_edb    : out std_logic;       -- packet termination and discard
+    -- outbound buffer status
+    gn_l2p_rdy    : in std_logic;        -- tx buffer full flag
+    gn_l_wr_rdy   : in std_logic_vector(1 downto 0);  -- local-to-pcie write
+    gn_p_rd_d_rdy : in std_logic_vector(1 downto 0);  -- pcie-to-local read response data ready
+    gn_tx_error   : in std_logic;        -- transmit error
+    gn_vc_rdy     : in std_logic_vector(1 downto 0);  -- channel ready
+
+    ------------------------------------------------------------------------
+    -- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
+    ------------------------------------------------------------------------
+    pll_sclk_o       : out std_logic;  -- SPI clock
+    pll_sdi_o        : out std_logic;  -- data line for PLL and DAC
+    pll_cs_o         : out std_logic;  -- PLL chip select
+    pll_dac_sync_o   : out std_logic;  -- DAC chip select
+    pll_sdo_i        : in  std_logic;  -- not used for the moment
+    pll_status_i     : in  std_logic;  -- PLL Digital Lock Detect, active high
+    tdc_clk_125m_p_i : in  std_logic;  -- 125 MHz differential clock: system clock
+    tdc_clk_125m_n_i : in  std_logic;  -- 125 MHz differential clock: system clock
+    acam_refclk_p_i  : in  std_logic;  -- 31.25 MHz differential clock: ACAM ref clock
+    acam_refclk_n_i  : in  std_logic;  -- 31.25 MHz differential clock: ACAM ref clock
+
+    -- Timing interface with the ACAM on TDC mezzanine
+    start_from_fpga_o : out   std_logic;  -- start signal
+    err_flag_i        : in    std_logic;  -- error flag
+    int_flag_i        : in    std_logic;  -- interrupt flag
+    start_dis_o       : out   std_logic;  -- start disable, not used
+    stop_dis_o        : out   std_logic;  -- stop disable, not used
+    -- Data interface with the ACAM on TDC mezzanine
+    data_bus_io       : inout std_logic_vector(27 downto 0);
+    address_o         : out   std_logic_vector(3 downto 0);
+    cs_n_o            : out   std_logic;  -- chip select for ACAM
+    oe_n_o            : out   std_logic;  -- output enable for ACAM
+    rd_n_o            : out   std_logic;  -- read  signal for ACAM
+    wr_n_o            : out   std_logic;  -- write signal for ACAM
+    ef1_i             : in    std_logic;  -- empty flag iFIFO1
+    ef2_i             : in    std_logic;  -- empty flag iFIFO2
+    -- Enable of input Logic on TDC mezzanine
+    enable_inputs_o   : out std_logic;  -- enables all 5 inputs
+    term_en_1_o       : out std_logic;  -- Ch.1 termination enable of 50 Ohm termination
+    term_en_2_o       : out std_logic;  -- Ch.2 termination enable of 50 Ohm termination
+    term_en_3_o       : out std_logic;  -- Ch.3 termination enable of 50 Ohm termination
+    term_en_4_o       : out std_logic;  -- Ch.4 termination enable of 50 Ohm termination
+    term_en_5_o       : out std_logic;  -- Ch.5 termination enable of 50 Ohm termination
+    -- LEDs on TDC mezzanine
+    tdc_led_status_o  : out std_logic;  -- amber led on front pannel, division of 125 MHz tdc_clk
+    tdc_led_trig1_o   : out std_logic;  -- amber led on front pannel, Ch.1 enable
+    tdc_led_trig2_o   : out std_logic;  -- amber led on front pannel, Ch.2 enable
+    tdc_led_trig3_o   : out std_logic;  -- amber led on front pannel, Ch.3 enable
+    tdc_led_trig4_o   : out std_logic;  -- amber led on front pannel, Ch.4 enable
+    tdc_led_trig5_o   : out std_logic;  -- amber led on front pannel, Ch.5 enable
+    -- Input Logic on TDC mezzanine (not used currently)
+    tdc_in_fpga_1_i   : in std_logic;   -- Ch.1 for ACAM, also received by FPGA
+    tdc_in_fpga_2_i   : in std_logic;   -- Ch.2 for ACAM, also received by FPGA
+    tdc_in_fpga_3_i   : in std_logic;   -- Ch.3 for ACAM, also received by FPGA
+    tdc_in_fpga_4_i   : in std_logic;   -- Ch.4 for ACAM, also received by FPGA
+    tdc_in_fpga_5_i   : in std_logic;   -- Ch.5 for ACAM, also received by FPGA
+    -- I2C EEPROM interface on TDC mezzanine
+    mezz_sys_scl_b    : inout std_logic := '1';  -- Mezzanine system EEPROM I2C clock
+    mezz_sys_sda_b    : inout std_logic := '1';  -- Mezzanine system EEPROM I2C data
+    -- 1-wire interface on TDC mezzanine
+    mezz_onewire_b    : inout std_logic;
+
+    -- font panel leds
+    led_act_o     : out std_logic;
+    led_link_o    : out std_logic;
+    -- Carrier other signals
+    pcb_ver_i     : in std_logic_vector(3 downto 0);  -- PCB version
+    prsnt_m2c_n_i : in std_logic);    -- Mezzanine presence (active low)
 
 end wr_spec_tdc;
 
@@ -288,36 +267,25 @@ end wr_spec_tdc;
 --=================================================================================================
 architecture rtl of wr_spec_tdc is
 
-
-  function f_bool2int (x : boolean) return integer is
-  begin
-    if(x) then
-      return 1;
-    else
-      return 0;
-    end if;
-  end f_bool2int;
-
-
 ---------------------------------------------------------------------------------------------------
 --                                         SDB CONSTANTS                                         --
 ---------------------------------------------------------------------------------------------------
 
-    constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
-    (abi_class     => x"0000",               -- undocumented device
+  constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
+    (abi_class     => x"0000",          -- undocumented device
      abi_ver_major => x"01",
      abi_ver_minor => x"01",
      wbd_endian    => c_sdb_endian_big,
-     wbd_width     => x"4",                  -- 32-bit port granularity
+     wbd_width     => x"4",             -- 32-bit port granularity
      sdb_component =>
-       (addr_first  => x"0000000000000000",
-        addr_last   => x"000000000000001F",
-        product     =>
-          (vendor_id => x"000000000000CE42", -- CERN
-           device_id => x"00000603",         -- "WB-SPEC.CSR        " | md5sum | cut -c1-8
-           version   => x"00000001",
-           date      => x"20121116",
-           name      => "WB-SPEC.CSR        ")));
+     (addr_first   => x"0000000000000000",
+      addr_last    => x"000000000000001F",
+      product =>
+      (vendor_id   => x"000000000000CE42",  -- CERN
+       device_id   => x"00000603",  -- "WB-SPEC.CSR        " | md5sum | cut -c1-8
+       version     => x"00000001",
+       date        => x"20121116",
+       name        => "WB-SPEC.CSR        ")));
 
 -- Note: All address in sdb and crossbar are BYTE addresses!
 
@@ -326,7 +294,7 @@ architecture rtl of wr_spec_tdc is
   constant c_WB_SLAVE_SPEC_INFO : integer := 0;  -- Info on SPEC control and status registers
   constant c_WB_SLAVE_VIC       : integer := 1;  -- Interrupt controller
   constant c_WB_SLAVE_TDC       : integer := 2;  -- TDC core configuration
-  constant c_SLAVE_WRCORE       : integer := 3;  -- White Rabbit PTP core
+  constant c_WB_SLAVE_WRC       : integer := 3;  -- White Rabbit PTP core
 
   -- SDB header address
   constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
@@ -346,7 +314,7 @@ architecture rtl of wr_spec_tdc is
      4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
      5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
 
-  
+
 ---------------------------------------------------------------------------------------------------
 --                                         VIC CONSTANT                                          --
 ---------------------------------------------------------------------------------------------------
@@ -356,359 +324,120 @@ architecture rtl of wr_spec_tdc is
 ---------------------------------------------------------------------------------------------------
 --                                            Signals                                            --
 ---------------------------------------------------------------------------------------------------
-  -- WRabbit clocks
-  signal pllout_clk_sys, pllout_clk_dmtd                  : std_logic;
-  signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd         : std_logic;
-  signal clk_125m_pllref, clk_125m_gtp                    : std_logic;
-  signal clk_dmtd                                         : std_logic;
-  attribute buffer_type                                   : string;  --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
-  attribute buffer_type of clk_125m_pllref                : signal is "BUFG";
-  -- TDC core clocks and resets
-  signal clk_20m_vcxo, clk_20m_vcxo_buf                   : std_logic;
-  signal clk_62m5_sys, sys_locked                         : std_logic;
-  signal rst_n_sys                               : std_logic;
+  -- Clocks and resets
+  signal clk_sys_62m5   : std_logic;
+  signal rst_sys_62m5_n : std_logic;
   -- DAC configuration through PCIe/VME
   -- WISHBONE from crossbar master port
-  signal cnx_master_out                                   : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
-  signal cnx_master_in                                    : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_out           : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in            : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
   -- WISHBONE to crossbar slave port
-  signal cnx_slave_out                                    : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
-  signal cnx_slave_in                                     : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
-  signal gn_wb_adr                                        : std_logic_vector(31 downto 0);
+  signal cnx_slave_out            : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in             : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal gn_wb_adr                : std_logic_vector(31 downto 0);
   -- Carrier CSR info
-  signal gn4124_status                                    : std_logic_vector(31 downto 0);
-  -- Carrier 1-wire
-  signal carrier_owr_en, carrier_owr_i                    : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
+  signal gn4124_status            : std_logic_vector(31 downto 0);
   -- VIC
-  signal irq_to_gn4124                       : std_logic;
+  signal irq_to_gn4124            : std_logic;
   -- WRabbit time
-  signal tm_link_up, tm_time_valid, tm_dac_wr_p           : std_logic;
-  signal tm_tai                                           : std_logic_vector(39 downto 0);
-  signal tm_cycles                                        : std_logic_vector(27 downto 0);
-  signal tm_dac_value, tm_dac_value_reg                   : std_logic_vector(23 downto 0);
-  signal tm_clk_aux_lock_en, tm_clk_aux_locked            : std_logic;
-  -- WRabbit PHY
-  signal phy_tx_data, phy_rx_data                         : std_logic_vector(7 downto 0);
-  signal phy_tx_k, phy_tx_disparity, phy_rx_k             : std_logic;
-  signal phy_tx_enc_err, phy_rx_rbclk                     : std_logic;
-  signal phy_rx_enc_err, phy_rst, phy_loopen              : std_logic;
-  signal phy_rx_bitslide                                  : std_logic_vector(3 downto 0);
-  -- DAC configuration through WRabbit
-  signal dac_hpll_load_p1, dac_dpll_load_p1               : std_logic;
-  signal dac_hpll_data, dac_dpll_data                     : std_logic_vector(15 downto 0);
+  signal tm_link_up, tm_time_valid: std_logic;
+  signal tm_dac_wr_p              : std_logic;
+  signal tm_tai                   : std_logic_vector(39 downto 0);
+  signal tm_cycles                : std_logic_vector(27 downto 0);
+  signal tm_dac_value             : std_logic_vector(23 downto 0);
+  signal tm_clk_aux_lock_en       : std_logic;
+  signal tm_clk_aux_locked        : std_logic;
   -- EEPROM on mezzanine
-  signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
-  signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in : std_logic;
-  signal tdc_scl_oen, tdc_sda_oen                         : std_logic;
+  signal tdc_scl_oen, tdc_scl_in  : std_logic;
+  signal tdc_sda_oen, tdc_sda_in  : std_logic;
   -- SFP EEPROM on mezzanine  
-  signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
+  signal sfp_scl_out, sfp_scl_in  : std_logic;
+  signal sfp_sda_out, sfp_sda_in  : std_logic;
   -- Carrier 1-Wire
-  signal wrc_owr_en, wrc_owr_in                           : std_logic_vector(1 downto 0);
+  signal wrc_owr_oe, wrc_owr_data : std_logic;
   -- aux
 
-  signal tdc0_irq: std_logic;
-  signal tdc0_clk_125m : std_logic;
-  signal tdc0_soft_rst_n: std_logic;
-
-  signal powerup_rst_cnt                      : unsigned(7 downto 0) := "00000000";
-  signal carrier_info_fmc_rst                 : std_logic_vector(30 downto 0);
+  signal tdc0_irq             : std_logic;
+  signal tdc0_clk_125m        : std_logic;
+  signal tdc0_soft_rst_n      : std_logic;
+  signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
 
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
 begin
 
----------------------------------------------------------------------------------------------------
---                                     62.5 MHz system clock                                     --
----------------------------------------------------------------------------------------------------
-
-  cmp_clk_vcxo_ibuf : IBUFG
-    port map
-    (O => clk_20m_vcxo_buf,
-     I => clk_20m_vcxo_i);
-
-  cmp_clk_vcxo_gbuf : BUFG
-    port map
-    (O => clk_20m_vcxo,
-     I => clk_20m_vcxo_buf);
-
-  cmp_sys_clk_pll : PLL_BASE
-    generic map
-    (BANDWIDTH          => "OPTIMIZED",
-     CLK_FEEDBACK       => "CLKFBOUT",
-     COMPENSATION       => "INTERNAL",
-     DIVCLK_DIVIDE      => 1,
-     CLKFBOUT_MULT      => 50,
-     CLKFBOUT_PHASE     => 0.000,
-     CLKOUT0_DIVIDE     => 16,          -- 62.5 MHz
-     CLKOUT0_PHASE      => 0.000,
-     CLKOUT0_DUTY_CYCLE => 0.500,
-     CLKOUT1_DIVIDE     => 16,          -- not used
-     CLKOUT1_PHASE      => 0.000,
-     CLKOUT1_DUTY_CYCLE => 0.500,
-     CLKOUT2_DIVIDE     => 16,
-     CLKOUT2_PHASE      => 0.000,
-     CLKOUT2_DUTY_CYCLE => 0.500,
-     CLKIN_PERIOD       => 50.0,
-     REF_JITTER         => 0.016)
-    port map
-    (CLKFBOUT => pllout_clk_fb_pllref,
-     CLKOUT0  => pllout_clk_sys,
-     CLKOUT1  => open,
-     CLKOUT2  => open,
-     CLKOUT3  => open,
-     CLKOUT4  => open,
-     CLKOUT5  => open,
-     LOCKED   => sys_locked,
-     RST      => '0',
-     CLKFBIN  => pllout_clk_fb_pllref,
-     CLKIN    => clk_20m_vcxo);
-
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_clk_sys_buf : BUFG
-    port map
-    (O => clk_62m5_sys,
-     I => pllout_clk_sys);      
+  tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
 
+-------------------------------------------------------------------------------
+--            SPEC Board Wrapper                                             --
+-------------------------------------------------------------------------------
 
----------------------------------------------------------------------------------------------------
---                                      62.5 MHz DMTD clock                                      --
----------------------------------------------------------------------------------------------------
-
-  cmp_dmtd_clk_pll : PLL_BASE
-    generic map
-    (BANDWIDTH          => "OPTIMIZED",
-     CLK_FEEDBACK       => "CLKFBOUT",
-     COMPENSATION       => "INTERNAL",
-     DIVCLK_DIVIDE      => 1,
-     CLKFBOUT_MULT      => 50,
-     CLKFBOUT_PHASE     => 0.000,
-     CLKOUT0_DIVIDE     => 16,          -- 62.5 MHz
-     CLKOUT0_PHASE      => 0.000,
-     CLKOUT0_DUTY_CYCLE => 0.500,
-     CLKOUT1_DIVIDE     => 16,          -- not used
-     CLKOUT1_PHASE      => 0.000,
-     CLKOUT1_DUTY_CYCLE => 0.500,
-     CLKOUT2_DIVIDE     => 8,
-     CLKOUT2_PHASE      => 0.000,
-     CLKOUT2_DUTY_CYCLE => 0.500,
-     CLKIN_PERIOD       => 50.0,
-     REF_JITTER         => 0.016)
-    port map
-    (CLKFBOUT => pllout_clk_fb_dmtd,
-     CLKOUT0  => pllout_clk_dmtd,
-     CLKOUT1  => open,
-     CLKOUT2  => open,
-     CLKOUT3  => open,
-     CLKOUT4  => open,
-     CLKOUT5  => open,
-     LOCKED   => open,
-     RST      => '0',
-     CLKFBIN  => pllout_clk_fb_dmtd,
-     CLKIN    => clk_20m_vcxo_buf);
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_clk_dmtd_buf : BUFG
-    port map
-    (O => clk_dmtd,
-     I => pllout_clk_dmtd);
-
----------------------------------------------------------------------------------------------------
---                               125 MHz clk for White Rabbit core                               --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_Buf_CLK_PLL : IBUFGDS
-    generic map
-    (DIFF_TERM    => true,
-     IBUF_LOW_PWR => true)  -- Low power (TRUE) vs. performance (FALSE) setting for referenced
-    port map
-    (O  => clk_125m_pllref,             -- Buffer output
-     I  => clk_125m_pllref_p_i,  -- Diff_p buffer input (connect directly to top-level port)
-     IB => clk_125m_pllref_n_i);  -- Diff_n buffer input (connect directly to top-level port)
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_Buf_CLK_GTP : IBUFDS
-    generic map
-    (DIFF_TERM    => true,
-     IBUF_LOW_PWR => false)
-    port map
-    (O  => clk_125m_gtp,
-     I  => clk_125m_gtp_p_i,
-     IB => clk_125m_gtp_n_i);
-
----------------------------------------------------------------------------------------------------
---                                         62.5 MHz Reset                                        --
----------------------------------------------------------------------------------------------------
--- SPEC power-up reset in the clk_62m5_sys domain: rst_n_sys is asserted asynchronously upon VME
--- reset or SVEC AFPGA power-on reset. If none of these signals is asserted at startup, the process
--- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
--- the reset.
-
-  p_powerup_reset : process(clk_62m5_sys,l_rst_n)
-  begin
-    if(l_rst_n = '0') then
-      rst_n_sys           <= '0';
-    elsif rising_edge(clk_62m5_sys) then
-      if sys_locked = '1' then
-        if(powerup_rst_cnt = "11111111") then
-          rst_n_sys       <= '1';
-        else
-          rst_n_sys       <= '0';
-          powerup_rst_cnt <= powerup_rst_cnt + 1;
-        end if;
-      else
-        rst_n_sys         <= '0';
-        powerup_rst_cnt   <= "00000000";
-      end if;
-    end if;
-  end process;
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  tdc0_soft_rst_n             <= carrier_info_fmc_rst(0) and rst_n_sys;
-
----------------------------------------------------------------------------------------------------
---                                  White Rabbit Core + PHY                                      --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_WR_CORE : xwr_core
-    generic map
-    (g_simulation                => f_bool2int(g_simulation),
-     g_phys_uart                 => true,
-     g_virtual_uart              => true,
-     g_with_external_clock_input => false,
-     g_aux_clks                  => 1,
-     g_ep_rxbuf_size             => 1024,
-     g_dpram_initf => "wrc.ram",
-     g_dpram_size                => 90112/4,
-     g_interface_mode            => PIPELINED,
-     g_address_granularity       => BYTE,
-     g_softpll_enable_debugger   => false)
-    port map
-    (clk_sys_i               => clk_62m5_sys,
-     clk_dmtd_i              => clk_dmtd,
-     clk_ref_i               => clk_125m_pllref,
-     clk_aux_i(0)            => tdc0_clk_125m,
-     rst_n_i                 => rst_n_sys,
-     -- DAC
-     dac_hpll_load_p1_o      => dac_hpll_load_p1,
-     dac_hpll_data_o         => dac_hpll_data,
-     dac_dpll_load_p1_o      => dac_dpll_load_p1,
-     dac_dpll_data_o         => dac_dpll_data,
-     -- PHY
-     phy_ref_clk_i           => clk_125m_pllref,
-     phy_tx_data_o           => phy_tx_data,
-     phy_tx_k_o              => phy_tx_k,
-     phy_tx_disparity_i      => phy_tx_disparity,
-     phy_tx_enc_err_i        => phy_tx_enc_err,
-     phy_rx_data_i           => phy_rx_data,
-     phy_rx_rbclk_i          => phy_rx_rbclk,
-     phy_rx_k_i              => phy_rx_k,
-     phy_rx_enc_err_i        => phy_rx_enc_err,
-     phy_rx_bitslide_i       => phy_rx_bitslide,
-     phy_rst_o               => phy_rst,
-     phy_loopen_o            => phy_loopen,
-     -- SPEC LEDs
-     led_act_o               => LED_RED,
-     led_link_o              => LED_GREEN,
-     -- SFP
-     scl_o                   => wrc_scl_out,
-     scl_i                   => wrc_scl_in,
-     sda_o                   => wrc_sda_out,
-     sda_i                   => wrc_sda_in,
-     sfp_scl_o               => sfp_scl_out,
-     sfp_scl_i               => sfp_scl_in,
-     sfp_sda_o               => sfp_sda_out,
-     sfp_sda_i               => sfp_sda_in,
-     sfp_det_i               => sfp_mod_def0_b,
-     uart_rxd_i              => uart_rxd_i,
-     uart_txd_o              => uart_txd_o,
-     -- 1-wire
-     owr_en_o                => wrc_owr_en,
-     owr_i                   => wrc_owr_in,
-     -- WISHBONE
-     slave_i                 => cnx_master_out(c_SLAVE_WRCORE),
-     slave_o                 => cnx_master_in(c_SLAVE_WRCORE),
-     -- Timimg info for TDC core
-     tm_link_up_o            => tm_link_up,
-     tm_dac_value_o          => tm_dac_value,
-     tm_dac_wr_o(0)          => tm_dac_wr_p,
-     tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
-     tm_clk_aux_locked_o(0)  => tm_clk_aux_locked,
-     tm_time_valid_o         => tm_time_valid,
-     tm_tai_o                => tm_tai,
-     tm_cycles_o             => tm_cycles,
-     -- not used
-     btn1_i                  => '1',
-     btn2_i                  => '1',
-     pps_p_o                 => open,
-     -- aux reset
-     rst_aux_n_o             => open);
-
-gen_with_wr_phy:  if g_with_wr_phy generate
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_GTP : wr_gtp_phy_spartan6
-    generic map
-    (g_simulation => 0,
-     g_enable_ch0 => 0,
-     g_enable_ch1 => 1)
-    port map
-    (gtp_clk_i          => clk_125m_gtp,
-     ch0_ref_clk_i      => clk_125m_pllref,
-     ch0_tx_data_i      => x"00",
-     ch0_tx_k_i         => '0',
-     ch0_tx_disparity_o => open,
-     ch0_tx_enc_err_o   => open,
-     ch0_rx_rbclk_o     => open,
-     ch0_rx_data_o      => open,
-     ch0_rx_k_o         => open,
-     ch0_rx_enc_err_o   => open,
-     ch0_rx_bitslide_o  => open,
-     ch0_rst_i          => '1',
-     ch0_loopen_i       => '0',
-     ch1_ref_clk_i      => clk_125m_pllref,
-     ch1_tx_data_i      => phy_tx_data,
-     ch1_tx_k_i         => phy_tx_k,
-     ch1_tx_disparity_o => phy_tx_disparity,
-     ch1_tx_enc_err_o   => phy_tx_enc_err,
-     ch1_rx_data_o      => phy_rx_data,
-     ch1_rx_rbclk_o     => phy_rx_rbclk,
-     ch1_rx_k_o         => phy_rx_k,
-     ch1_rx_enc_err_o   => phy_rx_enc_err,
-     ch1_rx_bitslide_o  => phy_rx_bitslide,
-     ch1_rst_i          => phy_rst,
-     ch1_loopen_i       => '0',         -- phy_loopen,
-     pad_txn0_o         => open,
-     pad_txp0_o         => open,
-     pad_rxn0_i         => '0',
-     pad_rxp0_i         => '0',
-     pad_txn1_o         => sfp_txn_o,
-     pad_txp1_o         => sfp_txp_o,
-     pad_rxn1_i         => sfp_rxn_i,
-     pad_rxp1_i         => sfp_rxp_i);
-
-
-  end generate gen_with_wr_phy;
-  
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_DAC_ARB : spec_serial_dac_arb
-    generic map
-    (g_invert_sclk    => false,
-     g_num_extra_bits => 8)
-    port map
-    (clk_i         => clk_62m5_sys,
-     rst_n_i       => rst_n_sys,
-     val1_i        => dac_dpll_data,
-     load1_i       => dac_dpll_load_p1,
-     val2_i        => dac_hpll_data,
-     load2_i       => dac_hpll_load_p1,
-     dac_cs_n_o(0) => dac_cs1_n_o,
-     dac_cs_n_o(1) => dac_cs2_n_o,
-     -- dac_clr_n_o   => open,
-     dac_sclk_o    => dac_sclk_o,
-     dac_din_o     => dac_din_o);
+  cmp_xwrc_board_spec : xwrc_board_spec
+    generic map (
+      g_simulation                => f_bool2int(g_simulation),
+      g_with_external_clock_input => FALSE,
+      g_aux_clks                  => 1,
+      g_dpram_initf               => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
+      g_fabric_iface              => PLAIN)
+    port map (
+      areset_n_i          => button1_i,
+      areset_edge_n_i     => gn_rst_n,
+      clk_20m_vcxo_i      => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
+      clk_sys_62m5_o      => clk_sys_62m5,
+      clk_aux_i(0)        => tdc0_clk_125m,
+      rst_sys_62m5_n_o    => rst_sys_62m5_n,
+      plldac_sclk_o       => wr_dac_sclk_o,
+      plldac_din_o        => wr_dac_din_o,
+      pll25dac_cs_n_o     => wr_25dac_cs_n_o,
+      pll20dac_cs_n_o     => wr_20dac_cs_n_o,
+      sfp_txp_o           => sfp_txp_o,
+      sfp_txn_o           => sfp_txn_o,
+      sfp_rxp_i           => sfp_rxp_i,
+      sfp_rxn_i           => sfp_rxn_i,
+      sfp_det_i           => sfp_mod_def0_i,
+      sfp_sda_i           => sfp_sda_in,
+      sfp_sda_o           => sfp_sda_out,
+      sfp_scl_i           => sfp_scl_in,
+      sfp_scl_o           => sfp_scl_out,
+      sfp_rate_select_o   => sfp_rate_select_o,
+      sfp_tx_fault_i      => sfp_tx_fault_i,
+      sfp_tx_disable_o    => sfp_tx_disable_o,
+      sfp_los_i           => sfp_los_i,
+      onewire_i           => wrc_owr_data,
+      onewire_oen_o       => wrc_owr_oe,
+      uart_rxd_i          => uart_rxd_i,
+      uart_txd_o          => uart_txd_o,
+      flash_sclk_o        => flash_sclk_o,
+      flash_ncs_o         => flash_ncs_o,
+      flash_mosi_o        => flash_mosi_o,
+      flash_miso_i        => flash_miso_i,
+      wb_slave_o          => cnx_master_in(c_WB_SLAVE_WRC),
+      wb_slave_i          => cnx_master_out(c_WB_SLAVE_WRC),
+      tm_link_up_o        => tm_link_up,
+      tm_dac_value_o      => tm_dac_value,
+      tm_dac_wr_o(0)          => tm_dac_wr_p,
+      tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
+      tm_clk_aux_locked_o(0)  => tm_clk_aux_locked,
+      tm_time_valid_o     => tm_time_valid,
+      tm_tai_o            => tm_tai,
+      tm_cycles_o         => tm_cycles,
+      led_link_o          => led_link_o,
+      led_act_o           => led_act_o);
 
+  -- Tristates for SFP EEPROM
+  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+  sfp_scl_in     <= sfp_mod_def1_b;
+  sfp_sda_in     <= sfp_mod_def2_b;
+  -- Tristates for 1-wire thermometer
+  carrier_onewire_b <= '0' when wrc_owr_oe = '1' else 'Z';
+  wrc_owr_data      <= carrier_onewire_b;
 
 ---------------------------------------------------------------------------------------------------
 --                                     CSR WISHBONE CROSSBAR                                     --
@@ -732,8 +461,8 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      g_layout      => c_INTERCONNECT_LAYOUT,
      g_sdb_addr    => c_SDB_ADDRESS)
     port map
-    (clk_sys_i => clk_62m5_sys,
-     rst_n_i   => rst_n_sys,
+    (clk_sys_i => clk_sys_62m5,
+     rst_n_i   => rst_sys_62m5_n,
      slave_i   => cnx_slave_in,
      slave_o   => cnx_slave_out,
      master_i  => cnx_master_in,
@@ -745,46 +474,46 @@ gen_with_wr_phy:  if g_with_wr_phy generate
 ---------------------------------------------------------------------------------------------------
   cmp_gn4124_core : gn4124_core
     port map
-    (rst_n_a_i       => l_rst_n,
-     status_o        => gn4124_status,
-      ---------------------------------------------------------
-      -- P2L Direction
-      --
-      -- Source Sync DDR related signals
-      p2l_clk_p_i  => P2L_CLKp,
-      p2l_clk_n_i  => P2L_CLKn,
-      p2l_data_i   => P2L_DATA,
-      p2l_dframe_i => P2L_DFRAME,
-      p2l_valid_i  => P2L_VALID,
-      -- P2L Control
-      p2l_rdy_o    => P2L_RDY,
-      p_wr_req_i   => P_WR_REQ,
-      p_wr_rdy_o   => P_WR_RDY,
-      rx_error_o   => RX_ERROR,
-      vc_rdy_i     => VC_RDY,
-
-      ---------------------------------------------------------
-      -- L2P Direction
-      --
-      -- Source Sync DDR related signals
-      l2p_clk_p_o  => L2P_CLKp,
-      l2p_clk_n_o  => L2P_CLKn,
-      l2p_data_o   => L2P_DATA,
-      l2p_dframe_o => L2P_DFRAME,
-      l2p_valid_o  => L2P_VALID,
-      -- L2P Control
-      l2p_edb_o    => L2P_EDB,
-      l2p_rdy_i    => L2P_RDY,
-      l_wr_rdy_i   => L_WR_RDY,
-      p_rd_d_rdy_i => P_RD_D_RDY,
-      tx_error_i   => TX_ERROR,
+    (rst_n_a_i    => gn_rst_n,
+     status_o     => gn4124_status,
+     ---------------------------------------------------------
+     -- P2L Direction
+     --
+     -- Source Sync DDR related signals
+     p2l_clk_p_i  => gn_p2l_clkp,
+     p2l_clk_n_i  => gn_p2l_clkn,
+     p2l_data_i   => gn_p2l_data,
+     p2l_dframe_i => gn_p2l_dframe,
+     p2l_valid_i  => gn_p2l_valid,
+     -- P2L Control
+     p2l_rdy_o    => gn_p2l_rdy,
+     p_wr_req_i   => gn_p_wr_req,
+     p_wr_rdy_o   => gn_p_wr_rdy,
+     rx_error_o   => gn_rx_error,
+     vc_rdy_i     => gn_vc_rdy,
+
+     ---------------------------------------------------------
+     -- L2P Direction
+     --
+     -- Source Sync DDR related signals
+     l2p_clk_p_o  => gn_l2p_clkp,
+     l2p_clk_n_o  => gn_l2p_clkn,
+     l2p_data_o   => gn_l2p_data,
+     l2p_dframe_o => gn_l2p_dframe,
+     l2p_valid_o  => gn_l2p_valid,
+     -- L2P Control
+     l2p_edb_o    => gn_l2p_edb,
+     l2p_rdy_i    => gn_l2p_rdy,
+     l_wr_rdy_i   => gn_l_wr_rdy,
+     p_rd_d_rdy_i => gn_p_rd_d_rdy,
+     tx_error_i   => gn_tx_error,
 
      dma_irq_o => open,
      irq_p_i   => '0',
      irq_p_o   => open,
 
      -- CSR WISHBONE interface (master pipelined)
-     csr_clk_i       => clk_62m5_sys,
+     csr_clk_i       => clk_sys_62m5,
      csr_adr_o       => gn_wb_adr,
      csr_dat_o       => cnx_slave_in(c_MASTER_GENNUM).dat,
      csr_sel_o       => cnx_slave_in(c_MASTER_GENNUM).sel,
@@ -794,33 +523,24 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      csr_dat_i       => cnx_slave_out(c_MASTER_GENNUM).dat,
      csr_ack_i       => cnx_slave_out(c_MASTER_GENNUM).ack,
      csr_stall_i     => cnx_slave_out(c_MASTER_GENNUM).stall,
-     csr_err_i => '0',
-     csr_rty_i => '0',
-     csr_int_i => '0',
+     csr_err_i       => cnx_slave_out(c_MASTER_GENNUM).err,
+     csr_rty_i       => cnx_slave_out(c_MASTER_GENNUM).rty,
+     csr_int_i       => cnx_slave_out(c_MASTER_GENNUM).int,
      -- DMA: not used
-     dma_clk_i       => clk_62m5_sys,
-     dma_adr_o       => open,
-     dma_cyc_o       => open,
-     dma_dat_o       => open,
-     dma_sel_o       => open,
-     dma_stb_o       => open,
-     dma_we_o        => open,
+     dma_clk_i       => clk_sys_62m5,
      dma_ack_i       => '1',
      dma_dat_i       => (others => '0'),
      dma_stall_i     => '0',
-     dma_err_i => '0',
-     dma_rty_i => '0',
-     dma_int_i => '0',
-     dma_reg_clk_i   => clk_62m5_sys,
+     dma_err_i       => '0',
+     dma_rty_i       => '0',
+     dma_int_i       => '0',
+     dma_reg_clk_i   => clk_sys_62m5,
      dma_reg_adr_i   => (others => '0'),
      dma_reg_dat_i   => (others => '0'),
      dma_reg_sel_i   => (others => '0'),
      dma_reg_stb_i   => '0',
      dma_reg_we_i    => '0',
-     dma_reg_cyc_i   => '0',
-     dma_reg_dat_o   => open,
-     dma_reg_ack_o   => open,
-     dma_reg_stall_o => open);
+     dma_reg_cyc_i   => '0');
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Convert 32-bit word address into byte address for crossbar
@@ -831,8 +551,8 @@ gen_with_wr_phy:  if g_with_wr_phy generate
       g_simulation          => g_simulation,
       g_with_direct_readout => false)
     port map (
-      clk_sys_i            => clk_62m5_sys,
-      rst_sys_n_i          => rst_n_sys,
+      clk_sys_i            => clk_sys_62m5,
+      rst_sys_n_i          => rst_sys_62m5_n,
       rst_n_a_i            => tdc0_soft_rst_n,
       pll_sclk_o           => pll_sclk_o,
       pll_sdi_o            => pll_sdi_o,
@@ -893,7 +613,7 @@ gen_with_wr_phy:  if g_with_wr_phy generate
       irq_o                => tdc0_irq,
       clk_125m_tdc_o       => tdc0_clk_125m);
 
-  
+
 ---------------------------------------------------------------------------------------------------
 --                                              VIC                                              --
 ---------------------------------------------------------------------------------------------------
@@ -904,16 +624,16 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      g_num_interrupts      => 1,
      g_init_vectors        => c_VIC_VECTOR_TABLE)
     port map
-    (clk_sys_i    => clk_62m5_sys,
-     rst_n_i      => rst_n_sys,
+    (clk_sys_i    => clk_sys_62m5,
+     rst_n_i      => rst_sys_62m5_n,
      slave_i      => cnx_master_out(c_WB_SLAVE_VIC),
      slave_o      => cnx_master_in(c_WB_SLAVE_VIC),
      irqs_i(0)    => tdc0_irq,
      irq_master_o => irq_to_gn4124);
 
-  gpio(0) <= irq_to_gn4124;
-  gpio(1) <= '0';
-  
+  gn_gpio(0) <= irq_to_gn4124;
+  gn_gpio(1) <= '0';
+
 ---------------------------------------------------------------------------------------------------
 --                                    Carrier CSR information                                    --
 ---------------------------------------------------------------------------------------------------
@@ -921,8 +641,8 @@ gen_with_wr_phy:  if g_with_wr_phy generate
 
   cmp_carrier_info : carrier_info
     port map
-    (rst_n_i                           => rst_n_sys,
-     clk_sys_i                         => clk_62m5_sys,
+    (rst_n_i                           => rst_sys_62m5_n,
+     clk_sys_i                         => clk_sys_62m5,
      wb_adr_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
      wb_dat_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
      wb_dat_o                          => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
@@ -937,18 +657,20 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      carrier_info_carrier_type_i       => c_CARRIER_TYPE,
      carrier_info_stat_fmc_pres_i      => prsnt_m2c_n_i,
      carrier_info_stat_p2l_pll_lck_i   => gn4124_status(0),
-     carrier_info_stat_sys_pll_lck_i   => sys_locked,
+     -- SPEC board wrapper releases rst_sys_62m5_n only when system clock pll is
+     -- locked. Therefore we report here '1' - pll locked
+     carrier_info_stat_sys_pll_lck_i   => '1',
      carrier_info_stat_ddr3_cal_done_i => '0',
      carrier_info_stat_reserved_i      => x"0000000",
-     
-     carrier_info_ctrl_led_green_o     => open,
-     carrier_info_ctrl_led_red_o       => open,
-     carrier_info_ctrl_dac_clr_n_o     => open,
-     carrier_info_ctrl_reserved_o      => open,
-     carrier_info_rst_fmc0_n_o         => open,
-     carrier_info_rst_fmc0_n_i         => '1',
-     carrier_info_rst_fmc0_n_load_o    => open,
-     carrier_info_rst_reserved_o       => carrier_info_fmc_rst);
+
+     carrier_info_ctrl_led_green_o  => open,
+     carrier_info_ctrl_led_red_o    => open,
+     carrier_info_ctrl_dac_clr_n_o  => open,
+     carrier_info_ctrl_reserved_o   => open,
+     carrier_info_rst_fmc0_n_o      => open,
+     carrier_info_rst_fmc0_n_i      => '1',
+     carrier_info_rst_fmc0_n_load_o => open,
+     carrier_info_rst_reserved_o    => carrier_info_fmc_rst);
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Unused wishbone signals
@@ -956,33 +678,13 @@ gen_with_wr_phy:  if g_with_wr_phy generate
   cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
   cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
 
-
-    --  --  --  --  --  --
-  sfp_tx_disable_o <= '0';
-  -- dac_clr_n_o   <= '1';
-
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Tristates for TDC mezzanine EEPROM
-  mezz_sys_scl_b <= '0' when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
-  mezz_sys_sda_b <= '0' when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
-  wrc_scl_in     <= mezz_sys_scl_b;
-  wrc_sda_in     <= mezz_sys_sda_b;
+  mezz_sys_scl_b <= '0' when (tdc_scl_oen = '0') else 'Z';
+  mezz_sys_sda_b <= '0' when (tdc_sda_oen = '0') else 'Z';
   tdc_scl_in     <= mezz_sys_scl_b;
   tdc_sda_in     <= mezz_sys_sda_b;
 
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  -- Tristates for SFP EEPROM
-  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
-  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
-  sfp_scl_in     <= sfp_mod_def1_b;
-  sfp_sda_in     <= sfp_mod_def2_b;
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
-  wrc_owr_in(0)     <= carrier_onewire_b;
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-
-
 end rtl;
 ----------------------------------------------------------------------------------------------------
 --  architecture ends
diff --git a/hdl/top/svec/Manifest.py b/hdl/top/svec/Manifest.py
index ba02fd2dc14f410b35f7ff4782d5d52e9e513c52..1fa9c3806df7ba2e5eff4b88dcae8b7fb46631d5 100644
--- a/hdl/top/svec/Manifest.py
+++ b/hdl/top/svec/Manifest.py
@@ -8,7 +8,13 @@ modules = {
     "local" : [	"../../rtl/", 
 		"../../ip_cores/vme64x-core",
 		"../../ip_cores/general-cores",
-		"../../ip_cores/wr-cores"
-	    ]
+		"../../ip_cores/wr-cores",
+                "../../ip_cores/wr-cores/board/svec"
+	    ],
+    "git" : [ 
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+        "git://ohwr.org/hdl-core-lib/vme64x-core.git",
+        "git://ohwr.org/hdl-core-lib/etherbone-core.git",
+        ],
     }
 
diff --git a/hdl/top/svec/synthesis_descriptor.vhd b/hdl/top/svec/synthesis_descriptor.vhd
index 13b68c29369d2ae035bb62eba969e3ea98368c21..1e070dc8da0a3de3dcfde8373ac18fdb76fafebb 100644
--- a/hdl/top/svec/synthesis_descriptor.vhd
+++ b/hdl/top/svec/synthesis_descriptor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Evangelia Gousiou
 -- Company    : CERN
 -- Created    : 2013-04-16
--- Last update: 2015-04-08
+-- Last update: 2015-05-27
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -46,12 +46,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
     syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
     syn_tool_name => "ISE     ",
     syn_tool_version => x"00000147",
-    syn_date => x"20150522",
+    syn_date => x"20150527",
     syn_username => "twlostow       ");
 
 constant c_sdb_repo_url : t_sdb_repo_url :=
   (
-    repo_url => "http://svn.ohwr.org/fmc-tdc                                    " 
+    repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git    "
   );
 
 end package synthesis_descriptor;
diff --git a/hdl/top/svec/wr_svec_tdc.ucf b/hdl/top/svec/wr_svec_tdc.ucf
index 8e916aab13f79416114b25936487f7d201de6f56..f77c1a047b74133d5c48ffb5c12452331c99fa29 100644
--- a/hdl/top/svec/wr_svec_tdc.ucf
+++ b/hdl/top/svec/wr_svec_tdc.ucf
@@ -7,6 +7,32 @@ NET "tdc2_prsntm2c_n_i" LOC = AE29;
 NET "tdc1_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
 NET "tdc2_prsntm2c_n_i" IOSTANDARD = LVCMOS33;
 
+#----------------------------------------
+#----------------------------------------
+#
+NET "fp_gpio1_o"      LOC = T28;
+#NET "fp_gpio2_o"      LOC = R30;
+#NET "fp_gpio3_i"      LOC = V27;
+#NET "fp_gpio4_i"      LOC = U29;
+NET "fp_gpio1_a2b_o"  LOC = T30;
+#NET "fp_gpio2_a2b_o"  LOC = R29;
+#NET "fp_gpio34_a2b_o" LOC = V28;
+NET "fp_term_en_o[1]" LOC = AB1;
+NET "fp_term_en_o[2]" LOC = W5; 
+NET "fp_term_en_o[3]" LOC = W4; 
+NET "fp_term_en_o[4]" LOC = V4; 
+NET "fp_gpio1_o"      IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio2_o"      IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio3_i"      IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio4_i"      IOSTANDARD = "LVCMOS33";
+NET "fp_gpio1_a2b_o"  IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio2_a2b_o"  IOSTANDARD = "LVCMOS33";
+#NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
+NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
+NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
+NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
+NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
+
 #----------------------------------------
 # FMC1/FMC2 I2C
 #----------------------------------------
@@ -28,6 +54,18 @@ NET "tdc2_sda_b" IOSTANDARD = LVCMOS33;
 NET "carrier_onewire_b" LOC = AC30;
 NET "carrier_onewire_b" IOSTANDARD = LVCMOS33;
 
+#----------------------------------------
+# SPI FLASH
+#----------------------------------------
+NET "spi_ncs_o"  LOC = AG27;
+NET "spi_ncs_o"  IOSTANDARD = "LVCMOS33";
+NET "spi_sclk_o" LOC = AG26;
+NET "spi_sclk_o"  IOSTANDARD = "LVCMOS33";
+NET "spi_mosi_o" LOC = AH26;
+NET "spi_mosi_o"  IOSTANDARD = "LVCMOS33";
+NET "spi_miso_i" LOC = AH27;
+NET "spi_miso_i"  IOSTANDARD = "LVCMOS33";
+
 #----------------------------------------
 # PCB version
 #----------------------------------------
@@ -65,209 +103,209 @@ NET "fp_led_column_o[3]" IOSTANDARD = LVCMOS33;
 #----------------------------------------
 # VME interface
 #----------------------------------------
-NET "VME_WRITE_n_i" LOC = R1;
-NET "VME_RST_n_i" LOC = P4;
+NET "vme_write_n_i" LOC = R1;
+NET "vme_rst_n_i" LOC = P4;
 #NET "vme_sysclk_i" LOC = P3;
-NET "VME_RETRY_OE_o" LOC = R4;
-NET "VME_RETRY_n_o" LOC = AB2;
-NET "VME_LWORD_n_b" LOC = M7;
-NET "VME_IACKOUT_n_o" LOC = N3;
-NET "VME_IACKIN_n_i" LOC = P7;
-NET "VME_IACK_n_i" LOC = N1;
-NET "VME_GA_i[5]" LOC = M6;
-NET "VME_DTACK_OE_o" LOC = T1;
-NET "VME_DTACK_n_o" LOC = R5;
-NET "VME_DS_n_i[1]" LOC = Y7;
-NET "VME_DS_n_i[0]" LOC = Y6;
-NET "VME_DATA_OE_N_o" LOC = P1;
-NET "VME_DATA_DIR_o" LOC = P2;
-NET "VME_BERR_o" LOC = R3;
-NET "VME_AS_n_i" LOC = P6;
-NET "VME_ADDR_OE_N_o" LOC = N4;
-NET "VME_ADDR_DIR_o" LOC = N5;
-NET "VME_IRQ_n_o[6]" LOC = R7;
-NET "VME_IRQ_n_o[5]" LOC = AH2;
-NET "VME_IRQ_n_o[4]" LOC = AF2;
-NET "VME_IRQ_n_o[3]" LOC = N9;
-NET "VME_IRQ_n_o[2]" LOC = N10;
-NET "VME_IRQ_n_o[1]" LOC = AH4;
-NET "VME_IRQ_n_o[0]" LOC = AG4;
-NET "VME_GA_i[4]" LOC = V9;
-NET "VME_GA_i[3]" LOC = V10;
-NET "VME_GA_i[2]" LOC = AJ1;
-NET "VME_GA_i[1]" LOC = AH1;
-NET "VME_GA_i[0]" LOC = V7;
-NET "VME_DATA_b[31]" LOC = AK3;
-NET "VME_DATA_b[30]" LOC = AH3;
-NET "VME_DATA_b[29]" LOC = T8;
-NET "VME_DATA_b[28]" LOC = T9;
-NET "VME_DATA_b[27]" LOC = AK4;
-NET "VME_DATA_b[26]" LOC = AJ4;
-NET "VME_DATA_b[25]" LOC = W6;
-NET "VME_DATA_b[24]" LOC = W7;
-NET "VME_DATA_b[23]" LOC = AB6;
-NET "VME_DATA_b[22]" LOC = AB7;
-NET "VME_DATA_b[21]" LOC = W9;
-NET "VME_DATA_b[20]" LOC = W10;
-NET "VME_DATA_b[19]" LOC = AK5;
-NET "VME_DATA_b[18]" LOC = AH5;
-NET "VME_DATA_b[17]" LOC = AD6;
-NET "VME_DATA_b[16]" LOC = AC6;
-NET "VME_DATA_b[15]" LOC = AA6;
-NET "VME_DATA_b[14]" LOC = AA7;
-NET "VME_DATA_b[13]" LOC = T6;
-NET "VME_DATA_b[12]" LOC = T7;
-NET "VME_DATA_b[11]" LOC = AG5;
-NET "VME_DATA_b[10]" LOC = AE5;
-NET "VME_DATA_b[9]" LOC = Y11;
-NET "VME_DATA_b[8]" LOC = W11;
-NET "VME_DATA_b[7]" LOC = AF6;
-NET "VME_DATA_b[6]" LOC = AE6;
-NET "VME_DATA_b[5]" LOC = Y8;
-NET "VME_DATA_b[4]" LOC = Y9;
-NET "VME_DATA_b[3]" LOC = AE7;
-NET "VME_DATA_b[2]" LOC = AD7;
-NET "VME_DATA_b[1]" LOC = AA9;
-NET "VME_DATA_b[0]" LOC = AA10;
-NET "VME_AM_i[5]" LOC = V8;
-NET "VME_AM_i[4]" LOC = AG3;
-NET "VME_AM_i[3]" LOC = AF3;
-NET "VME_AM_i[2]" LOC = AF4;
-NET "VME_AM_i[1]" LOC = AE4;
-NET "VME_AM_i[0]" LOC = AK2;
-NET "VME_ADDR_b[31]" LOC = T2;
-NET "VME_ADDR_b[30]" LOC = T3;
-NET "VME_ADDR_b[29]" LOC = T4;
-NET "VME_ADDR_b[28]" LOC = U1;
-NET "VME_ADDR_b[27]" LOC = U3;
-NET "VME_ADDR_b[26]" LOC = U4;
-NET "VME_ADDR_b[25]" LOC = U5;
-NET "VME_ADDR_b[24]" LOC = V1;
-NET "VME_ADDR_b[23]" LOC = V2;
-NET "VME_ADDR_b[22]" LOC = W1;
-NET "VME_ADDR_b[21]" LOC = W3;
-NET "VME_ADDR_b[20]" LOC = AA4;
-NET "VME_ADDR_b[19]" LOC = AA5;
-NET "VME_ADDR_b[18]" LOC = Y1;
-NET "VME_ADDR_b[17]" LOC = Y2;
-NET "VME_ADDR_b[16]" LOC = Y3;
-NET "VME_ADDR_b[15]" LOC = Y4;
-NET "VME_ADDR_b[14]" LOC = AC1;
-NET "VME_ADDR_b[13]" LOC = AC3;
-NET "VME_ADDR_b[12]" LOC = AD1;
-NET "VME_ADDR_b[11]" LOC = AD2;
-NET "VME_ADDR_b[10]" LOC = AB3;
-NET "VME_ADDR_b[9]" LOC = AB4;
-NET "VME_ADDR_b[8]" LOC = AD3;
-NET "VME_ADDR_b[7]" LOC = AD4;
-NET "VME_ADDR_b[6]" LOC = AC4;
-NET "VME_ADDR_b[5]" LOC = AC5;
-NET "VME_ADDR_b[4]" LOC = N7;
-NET "VME_ADDR_b[3]" LOC = N8;
-NET "VME_ADDR_b[2]" LOC = AE1;
-NET "VME_ADDR_b[1]" LOC = AE3;
-
-NET "VME_WRITE_n_i" IOSTANDARD = LVCMOS33;
-NET "VME_RST_n_i" IOSTANDARD = LVCMOS33;
+NET "vme_retry_oe_o" LOC = R4;
+NET "vme_retry_n_o" LOC = AB2;
+NET "vme_lword_n_b" LOC = M7;
+NET "vme_iackout_n_o" LOC = N3;
+NET "vme_iackin_n_i" LOC = P7;
+NET "vme_iack_n_i" LOC = N1;
+NET "vme_ga_i[5]" LOC = M6;
+NET "vme_dtack_oe_o" LOC = T1;
+NET "vme_dtack_n_o" LOC = R5;
+NET "vme_ds_n_i[1]" LOC = Y7;
+NET "vme_ds_n_i[0]" LOC = Y6;
+NET "vme_data_oe_n_o" LOC = P1;
+NET "vme_data_dir_o" LOC = P2;
+NET "vme_berr_o" LOC = R3;
+NET "vme_as_n_i" LOC = P6;
+NET "vme_addr_oe_n_o" LOC = N4;
+NET "vme_addr_dir_o" LOC = N5;
+NET "vme_irq_o[6]" LOC = R7;
+NET "vme_irq_o[5]" LOC = AH2;
+NET "vme_irq_o[4]" LOC = AF2;
+NET "vme_irq_o[3]" LOC = N9;
+NET "vme_irq_o[2]" LOC = N10;
+NET "vme_irq_o[1]" LOC = AH4;
+NET "vme_irq_o[0]" LOC = AG4;
+NET "vme_ga_i[4]" LOC = V9;
+NET "vme_ga_i[3]" LOC = V10;
+NET "vme_ga_i[2]" LOC = AJ1;
+NET "vme_ga_i[1]" LOC = AH1;
+NET "vme_ga_i[0]" LOC = V7;
+NET "vme_data_b[31]" LOC = AK3;
+NET "vme_data_b[30]" LOC = AH3;
+NET "vme_data_b[29]" LOC = T8;
+NET "vme_data_b[28]" LOC = T9;
+NET "vme_data_b[27]" LOC = AK4;
+NET "vme_data_b[26]" LOC = AJ4;
+NET "vme_data_b[25]" LOC = W6;
+NET "vme_data_b[24]" LOC = W7;
+NET "vme_data_b[23]" LOC = AB6;
+NET "vme_data_b[22]" LOC = AB7;
+NET "vme_data_b[21]" LOC = W9;
+NET "vme_data_b[20]" LOC = W10;
+NET "vme_data_b[19]" LOC = AK5;
+NET "vme_data_b[18]" LOC = AH5;
+NET "vme_data_b[17]" LOC = AD6;
+NET "vme_data_b[16]" LOC = AC6;
+NET "vme_data_b[15]" LOC = AA6;
+NET "vme_data_b[14]" LOC = AA7;
+NET "vme_data_b[13]" LOC = T6;
+NET "vme_data_b[12]" LOC = T7;
+NET "vme_data_b[11]" LOC = AG5;
+NET "vme_data_b[10]" LOC = AE5;
+NET "vme_data_b[9]" LOC = Y11;
+NET "vme_data_b[8]" LOC = W11;
+NET "vme_data_b[7]" LOC = AF6;
+NET "vme_data_b[6]" LOC = AE6;
+NET "vme_data_b[5]" LOC = Y8;
+NET "vme_data_b[4]" LOC = Y9;
+NET "vme_data_b[3]" LOC = AE7;
+NET "vme_data_b[2]" LOC = AD7;
+NET "vme_data_b[1]" LOC = AA9;
+NET "vme_data_b[0]" LOC = AA10;
+NET "vme_am_i[5]" LOC = V8;
+NET "vme_am_i[4]" LOC = AG3;
+NET "vme_am_i[3]" LOC = AF3;
+NET "vme_am_i[2]" LOC = AF4;
+NET "vme_am_i[1]" LOC = AE4;
+NET "vme_am_i[0]" LOC = AK2;
+NET "vme_addr_b[31]" LOC = T2;
+NET "vme_addr_b[30]" LOC = T3;
+NET "vme_addr_b[29]" LOC = T4;
+NET "vme_addr_b[28]" LOC = U1;
+NET "vme_addr_b[27]" LOC = U3;
+NET "vme_addr_b[26]" LOC = U4;
+NET "vme_addr_b[25]" LOC = U5;
+NET "vme_addr_b[24]" LOC = V1;
+NET "vme_addr_b[23]" LOC = V2;
+NET "vme_addr_b[22]" LOC = W1;
+NET "vme_addr_b[21]" LOC = W3;
+NET "vme_addr_b[20]" LOC = AA4;
+NET "vme_addr_b[19]" LOC = AA5;
+NET "vme_addr_b[18]" LOC = Y1;
+NET "vme_addr_b[17]" LOC = Y2;
+NET "vme_addr_b[16]" LOC = Y3;
+NET "vme_addr_b[15]" LOC = Y4;
+NET "vme_addr_b[14]" LOC = AC1;
+NET "vme_addr_b[13]" LOC = AC3;
+NET "vme_addr_b[12]" LOC = AD1;
+NET "vme_addr_b[11]" LOC = AD2;
+NET "vme_addr_b[10]" LOC = AB3;
+NET "vme_addr_b[9]" LOC = AB4;
+NET "vme_addr_b[8]" LOC = AD3;
+NET "vme_addr_b[7]" LOC = AD4;
+NET "vme_addr_b[6]" LOC = AC4;
+NET "vme_addr_b[5]" LOC = AC5;
+NET "vme_addr_b[4]" LOC = N7;
+NET "vme_addr_b[3]" LOC = N8;
+NET "vme_addr_b[2]" LOC = AE1;
+NET "vme_addr_b[1]" LOC = AE3;
+
+NET "vme_write_n_i" IOSTANDARD = LVCMOS33;
+NET "vme_rst_n_i" IOSTANDARD = LVCMOS33;
 #NET "vme_sysclk_i" IOSTANDARD = "LVCMOS33";
-NET "VME_RETRY_OE_o" IOSTANDARD = LVCMOS33;
-NET "VME_RETRY_n_o" IOSTANDARD = LVCMOS33;
-NET "VME_LWORD_n_b" IOSTANDARD = LVCMOS33;
-NET "VME_IACKOUT_n_o" IOSTANDARD = LVCMOS33;
-NET "VME_IACKIN_n_i" IOSTANDARD = LVCMOS33;
-NET "VME_IACK_n_i" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[5]" IOSTANDARD = LVCMOS33;
-NET "VME_DTACK_OE_o" IOSTANDARD = LVCMOS33;
-NET "VME_DTACK_n_o" IOSTANDARD = LVCMOS33;
-NET "VME_DS_n_i[1]" IOSTANDARD = LVCMOS33;
-NET "VME_DS_n_i[0]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_OE_N_o" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_DIR_o" IOSTANDARD = LVCMOS33;
-NET "VME_BERR_o" IOSTANDARD = LVCMOS33;
-NET "VME_AS_n_i" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_OE_N_o" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_DIR_o" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[6]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[5]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[4]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[3]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[2]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[1]" IOSTANDARD = LVCMOS33;
-NET "VME_IRQ_n_o[0]" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[4]" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[3]" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[2]" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[1]" IOSTANDARD = LVCMOS33;
-NET "VME_GA_i[0]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[31]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[30]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[29]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[28]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[27]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[26]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[25]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[24]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[23]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[22]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[21]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[20]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[19]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[18]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[17]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[16]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[15]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[14]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[13]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[12]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[11]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[10]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[9]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[8]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[7]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[6]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[5]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[4]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[3]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[2]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[1]" IOSTANDARD = LVCMOS33;
-NET "VME_DATA_b[0]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[5]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[4]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[3]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[2]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[1]" IOSTANDARD = LVCMOS33;
-NET "VME_AM_i[0]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[31]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[30]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[29]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[28]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[27]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[26]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[25]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[24]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[23]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[22]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[21]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[20]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[19]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[18]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[17]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[16]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[15]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[14]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[13]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[12]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[11]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[10]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[9]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[8]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[7]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[6]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[5]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[4]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[3]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[2]" IOSTANDARD = LVCMOS33;
-NET "VME_ADDR_b[1]" IOSTANDARD = LVCMOS33;
+NET "vme_retry_oe_o" IOSTANDARD = LVCMOS33;
+NET "vme_retry_n_o" IOSTANDARD = LVCMOS33;
+NET "vme_lword_n_b" IOSTANDARD = LVCMOS33;
+NET "vme_iackout_n_o" IOSTANDARD = LVCMOS33;
+NET "vme_iackin_n_i" IOSTANDARD = LVCMOS33;
+NET "vme_iack_n_i" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[5]" IOSTANDARD = LVCMOS33;
+NET "vme_dtack_oe_o" IOSTANDARD = LVCMOS33;
+NET "vme_dtack_n_o" IOSTANDARD = LVCMOS33;
+NET "vme_ds_n_i[1]" IOSTANDARD = LVCMOS33;
+NET "vme_ds_n_i[0]" IOSTANDARD = LVCMOS33;
+NET "vme_data_oe_n_o" IOSTANDARD = LVCMOS33;
+NET "vme_data_dir_o" IOSTANDARD = LVCMOS33;
+NET "vme_berr_o" IOSTANDARD = LVCMOS33;
+NET "vme_as_n_i" IOSTANDARD = LVCMOS33;
+NET "vme_addr_oe_n_o" IOSTANDARD = LVCMOS33;
+NET "vme_addr_dir_o" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[6]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[5]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[4]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[3]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[2]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[1]" IOSTANDARD = LVCMOS33;
+NET "vme_irq_o[0]" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[4]" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[3]" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[2]" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[1]" IOSTANDARD = LVCMOS33;
+NET "vme_ga_i[0]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[31]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[30]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[29]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[28]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[27]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[26]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[25]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[24]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[23]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[22]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[21]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[20]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[19]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[18]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[17]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[16]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[15]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[14]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[13]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[12]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[11]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[10]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[9]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[8]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[7]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[6]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[5]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[4]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[3]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[2]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[1]" IOSTANDARD = LVCMOS33;
+NET "vme_data_b[0]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[5]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[4]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[3]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[2]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[1]" IOSTANDARD = LVCMOS33;
+NET "vme_am_i[0]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[31]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[30]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[29]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[28]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[27]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[26]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[25]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[24]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[23]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[22]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[21]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[20]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[19]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[18]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[17]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[16]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[15]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[14]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[13]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[12]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[11]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[10]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[9]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[8]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[7]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[6]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[5]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[4]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[3]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[2]" IOSTANDARD = LVCMOS33;
+NET "vme_addr_b[1]" IOSTANDARD = LVCMOS33;
 
 
 #----------------------------------------
@@ -562,7 +600,7 @@ NET "sfp_rxp_i" LOC = D22;
 NET "sfp_rxn_i" LOC = C22;
 
 NET "sfp_los_i" LOC = W25;
-NET "sfp_mod_def0_b" LOC = Y26;
+NET "sfp_mod_def0_i" LOC = Y26;
 NET "sfp_mod_def1_b" LOC = Y27;
 NET "sfp_mod_def2_b" LOC = AA24;
 #NET "sfp_rate_select_o" LOC = W24;
@@ -570,7 +608,7 @@ NET "sfp_tx_disable_o" LOC = AA25;
 NET "sfp_tx_fault_i" LOC = AA27;
 
 NET "sfp_los_i" IOSTANDARD = LVCMOS33;
-NET "sfp_mod_def0_b" IOSTANDARD = LVCMOS33;
+NET "sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
 NET "sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
 NET "sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
 #NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
@@ -611,7 +649,7 @@ NET "por_n_i" IOSTANDARD = LVCMOS33;
 NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
 
 # 62.5MHz Xilinx PLL clock/reset
-NET "clk_62m5_sys" TNM_NET = "clk_62m5_sys";
+NET "clk_sys_62m5" TNM_NET = "clk_sys_62m5";
 
 # 125MHz PLL ref
 NET "clk_125m_pllref_n_i" LOC = AB30;
@@ -643,47 +681,23 @@ NET "tdc2_125m_clk_n_i" TNM_NET = "tdc2_125m_clk_n_i";
 TIMESPEC TS_tdc2_tdc_125m_clk_n_i = PERIOD "tdc2_125m_clk_n_i" 8 ns HIGH 50 %;
 
 # TS_IGNORE
-
-TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock1 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20 ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock3 = FROM "clk_62m5_sys" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_62m5_sys" 20ns DATAPATHONLY;
-
-TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_62m5_sys" 200ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
-TIMESPEC ts_ignore_xclock4 = FROM "clk_62m5_sys" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
-#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2015/03/31
-NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
-TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
+TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock1 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock2 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20 ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock3 = FROM "clk_sys_62m5" TO "tdc2_125m_clk" 20 ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock4 = FROM "tdc2_125m_clk" TO "clk_sys_62m5" 20ns DATAPATHONLY;
+
+TIMESPEC ts_ignore_xclock4 = FROM "clk_20m_vcxo_i" TO "clk_sys_62m5" 200ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200ns DATAPATHONLY;
+TIMESPEC ts_ignore_xclock4 = FROM "clk_sys_62m5" TO "clk_20m_vcxo_i" 200 ns DATAPATHONLY;
+#TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50 %;
+#Created by Constraints Editor (xc6slx150t-fgg900-3) - 2017/12/06
+NET "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_cmp_xwrc_board_svec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
 
 # PlanAhead Generated miscellaneous constraints 
-
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-
-# PlanAhead Generated IO constraints 
-
 NET "tdc1_address_o[3]" SLEW = FAST;
 NET "tdc1_address_o[2]" SLEW = FAST;
 NET "tdc1_address_o[1]" SLEW = FAST;
@@ -748,3 +762,14 @@ NET "tdc2_data_bus_io[3]" SLEW = FAST;
 NET "tdc2_data_bus_io[2]" SLEW = FAST;
 NET "tdc2_data_bus_io[1]" SLEW = FAST;
 NET "tdc2_data_bus_io[0]" SLEW = FAST;
+
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
+
+# Force PPS output to always be placed as IOB register
+INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
+# External async reset
+NET "por_n_i" TIG;
+NET "vme_rst_n_i" TIG;
diff --git a/hdl/top/svec/wr_svec_tdc.vhd b/hdl/top/svec/wr_svec_tdc.vhd
index 2735555c8a2cfe6ec241cbba52d1795119b69508..c839b753e3e99cfe544b7f9ab47923543d185c51 100644
--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -87,6 +87,7 @@
 --                                                                                                |
 -- Authors      Gonzalo Penacoba  (Gonzalo.Penacoba@cern.ch)                                      |
 --              Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
+--              Grzegorz Daniluk  (Grzegorz.Daniluk@cern.ch)
 -- Date         05/2014                                                                           |
 -- Version      v2                                                                                |
 -- Depends on                                                                                     |
@@ -95,6 +96,7 @@
 -- Last changes                                                                                   |
 --     08/2013  v1  EG  design for SVEC; two cores; synchronizer between vme and the cores        |
 --     05/2014  v2  EG  added White Rabbit                                                        |
+--     12/2017  v7  GD  Top file reorganized to benefit from WRPC Board wrapper.
 ---------------------------------------------------------------------------------------------------
 
 ---------------------------------------------------------------------------------------------------
@@ -119,10 +121,9 @@ use IEEE.numeric_std.all;
 use work.tdc_core_pkg.all;
 use work.gencores_pkg.all;
 use work.wishbone_pkg.all;
-use work.wrcore_pkg.all;
-use work.wr_fabric_pkg.all;
-use work.wr_xilinx_pkg.all;
-use work.xvme64x_core_pkg.all;
+use work.vme64x_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_svec_pkg.all;
 
 library UNISIM;
 use UNISIM.vcomponents.all;
@@ -134,183 +135,190 @@ use work.synthesis_descriptor.all;
 --=================================================================================================
 entity wr_svec_tdc is
   generic (
-     g_simulation           : boolean := false;
-     g_with_wr_phy : boolean := true);
-  port
-    (-- SVEC carrier
-      -- VCXO clock, PoR
-      por_n_i                : in    std_logic;        -- PoR
-      clk_20m_vcxo_i         : in    std_logic;        -- 20 MHz VCXO
-      -- 125 MHz PLL reference
-      clk_125m_pllref_p_i    : in    std_logic;
-      clk_125m_pllref_n_i    : in    std_logic;
-      -- 125 MHz GTP reference
-      clk_125m_gtp_p_i       : in    std_logic;
-      clk_125m_gtp_n_i       : in    std_logic;
-      -- SFP
-      sfp_txp_o              : out   std_logic;
-      sfp_txn_o              : out   std_logic;
-      sfp_rxp_i              : in    std_logic := '0';
-      sfp_rxn_i              : in    std_logic := '1';
-      sfp_mod_def0_b         : in    std_logic;        -- SFP detect pin
-      sfp_mod_def1_b         : inout std_logic;        -- SFP scl
-      sfp_mod_def2_b         : inout std_logic;        -- SFP sda
-      sfp_rate_select_b      : inout std_logic := '0';
-      sfp_tx_fault_i         : in    std_logic := '0';
-      sfp_tx_disable_o       : out   std_logic;
-      sfp_los_i              : in    std_logic := '0';
-      -- Serial DAC
-      pll20dac_din_o         : out   std_logic;
-      pll20dac_sclk_o        : out   std_logic;
-      pll20dac_sync_n_o      : out   std_logic;
-      pll25dac_din_o         : out   std_logic;
-      pll25dac_sclk_o        : out   std_logic;
-      pll25dac_sync_n_o      : out   std_logic;
-      -- UART
-      uart_rxd_i             : in    std_logic := '1';
-      uart_txd_o             : out   std_logic;
-      -- 1-wire
-      carrier_onewire_b      : inout std_logic;        
-      -- SVEC PCB version
-      pcb_ver_i              : in    std_logic_vector(3 downto 0);
-      -- Mezzanines presence
-      tdc1_prsntm2c_n_i      : in    std_logic;        -- Presence of mezzanine #1
-      tdc2_prsntm2c_n_i      : in    std_logic;        -- Presence of mezzanine #2
-      -- SVEC Front panel LEDs
-      fp_led_line_oen_o      : out   std_logic_vector(1 downto 0);
-      fp_led_line_o          : out   std_logic_vector(1 downto 0);
-      fp_led_column_o        : out   std_logic_vector(3 downto 0);
-
-     -- VME interface
-      VME_AS_n_i             : in    std_logic;
-      VME_RST_n_i            : in    std_logic;
-      VME_WRITE_n_i          : in    std_logic;
-      VME_AM_i               : in    std_logic_vector(5 downto 0);
-      VME_DS_n_i             : in    std_logic_vector(1 downto 0);
-      VME_GA_i               : in    std_logic_vector(5 downto 0);
-      VME_BERR_o             : inout std_logic;
-      VME_DTACK_n_o          : inout std_logic;
-      VME_RETRY_n_o          : out   std_logic;
-      VME_RETRY_OE_o         : out   std_logic;
-      VME_LWORD_n_b          : inout std_logic;
-      VME_ADDR_b             : inout std_logic_vector(31 downto 1);
-      VME_DATA_b             : inout std_logic_vector(31 downto 0);
-      VME_BBSY_n_i           : in    std_logic;
-      VME_IRQ_n_o            : out   std_logic_vector(6 downto 0);
-      VME_IACK_n_i           : in    std_logic;
-      VME_IACKIN_n_i         : in    std_logic;
-      VME_IACKOUT_n_o        : out   std_logic;
-      VME_DTACK_OE_o         : inout std_logic;
-      VME_DATA_DIR_o         : inout std_logic;
-      VME_DATA_OE_N_o        : inout std_logic;
-      VME_ADDR_DIR_o         : inout std_logic;
-      VME_ADDR_OE_N_o        : inout std_logic;
-
-     -- TDC mezzanine board on FMC slot 1
-      -- TDC1 PLL AD9516 and DAC AD5662 interface
-      tdc1_pll_sclk_o        : out   std_logic;
-      tdc1_pll_sdi_o         : out   std_logic;
-      tdc1_pll_cs_n_o        : out   std_logic;
-      tdc1_pll_dac_sync_n_o  : out   std_logic;
-      tdc1_pll_sdo_i         : in    std_logic;
-      tdc1_pll_status_i      : in    std_logic;
-      tdc1_125m_clk_p_i      : in    std_logic;
-      tdc1_125m_clk_n_i      : in    std_logic;
-      tdc1_acam_refclk_p_i   : in    std_logic;
-      tdc1_acam_refclk_n_i   : in    std_logic;
-      -- TDC1 ACAM timing interface
-      tdc1_start_from_fpga_o : out   std_logic;
-      tdc1_err_flag_i        : in    std_logic;
-      tdc1_int_flag_i        : in    std_logic;
-      tdc1_start_dis_o       : out   std_logic;
-      tdc1_stop_dis_o        : out   std_logic;
-      -- TDC1 ACAM data interface
-      tdc1_data_bus_io       : inout std_logic_vector(27 downto 0);
-      tdc1_address_o         : out   std_logic_vector(3 downto 0);
-      tdc1_cs_n_o            : out   std_logic;
-      tdc1_oe_n_o            : out   std_logic;
-      tdc1_rd_n_o            : out   std_logic;
-      tdc1_wr_n_o            : out   std_logic;
-      tdc1_ef1_i             : in    std_logic;
-      tdc1_ef2_i             : in    std_logic;
-      -- TDC1 Input Logic
-      tdc1_enable_inputs_o   : out   std_logic;
-      tdc1_term_en_1_o       : out   std_logic;
-      tdc1_term_en_2_o       : out   std_logic;
-      tdc1_term_en_3_o       : out   std_logic;
-      tdc1_term_en_4_o       : out   std_logic;
-      tdc1_term_en_5_o       : out   std_logic;
-      -- TDC1 1-wire UniqueID & Thermometer
-      tdc1_onewire_b         : inout std_logic;
-      -- TDC1 EEPROM I2C
-      tdc1_scl_b             : inout std_logic;
-      tdc1_sda_b             : inout std_logic;
-      -- TDC1 LEDs
-      tdc1_led_status_o      : out   std_logic;
-      tdc1_led_trig1_o       : out   std_logic;
-      tdc1_led_trig2_o       : out   std_logic;
-      tdc1_led_trig3_o       : out   std_logic;
-      tdc1_led_trig4_o       : out   std_logic;
-      tdc1_led_trig5_o       : out   std_logic;
-      -- TDC1 Input channels, also arriving to the FPGA (not used for the moment)
-      tdc1_in_fpga_1_i       : in    std_logic;
-      tdc1_in_fpga_2_i       : in    std_logic;
-      tdc1_in_fpga_3_i       : in    std_logic;
-      tdc1_in_fpga_4_i       : in    std_logic;
-      tdc1_in_fpga_5_i       : in    std_logic;
-
-     -- TDC mezzanine board on FMC slot 2
-      -- TDC2 PLL AD9516 and DAC AD5662 interface
-      tdc2_pll_sclk_o        : out   std_logic;
-      tdc2_pll_sdi_o         : out   std_logic;
-      tdc2_pll_cs_n_o        : out   std_logic;
-      tdc2_pll_dac_sync_n_o  : out   std_logic;
-      tdc2_pll_sdo_i         : in    std_logic;
-      tdc2_pll_status_i      : in    std_logic;
-      tdc2_125m_clk_p_i      : in    std_logic;
-      tdc2_125m_clk_n_i      : in    std_logic;
-      tdc2_acam_refclk_p_i   : in    std_logic;
-      tdc2_acam_refclk_n_i   : in    std_logic;
-      -- TDC2 ACAM timing interface
-      tdc2_start_from_fpga_o : out   std_logic;
-      tdc2_err_flag_i        : in    std_logic;
-      tdc2_int_flag_i        : in    std_logic;
-      tdc2_start_dis_o       : out   std_logic;
-      tdc2_stop_dis_o        : out   std_logic;
-      -- TDC2 ACAM data interface
-      tdc2_data_bus_io       : inout std_logic_vector(27 downto 0);
-      tdc2_address_o         : out   std_logic_vector(3 downto 0);
-      tdc2_cs_n_o            : out   std_logic;
-      tdc2_oe_n_o            : out   std_logic;
-      tdc2_rd_n_o            : out   std_logic;
-      tdc2_wr_n_o            : out   std_logic;
-      tdc2_ef1_i             : in    std_logic;
-      tdc2_ef2_i             : in    std_logic;
-      -- TDC2 Input Logic
-      tdc2_enable_inputs_o   : out   std_logic;
-      tdc2_term_en_1_o       : out   std_logic;
-      tdc2_term_en_2_o       : out   std_logic;
-      tdc2_term_en_3_o       : out   std_logic;
-      tdc2_term_en_4_o       : out   std_logic;
-      tdc2_term_en_5_o       : out   std_logic;
-      -- TDC2 1-wire UniqueID & Thermometer
-      tdc2_onewire_b         : inout std_logic;
-      -- TDC2 EEPROM I2C
-      tdc2_scl_b             : inout std_logic;
-      tdc2_sda_b             : inout std_logic;
-      -- TDC2 LEDs
-      tdc2_led_status_o      : out   std_logic;
-      tdc2_led_trig1_o       : out   std_logic;
-      tdc2_led_trig2_o       : out   std_logic;
-      tdc2_led_trig3_o       : out   std_logic;
-      tdc2_led_trig4_o       : out   std_logic;
-      tdc2_led_trig5_o       : out   std_logic;
-      -- TDC2 Input channels, also arriving to the FPGA (not used for the moment)
-      tdc2_in_fpga_1_i       : in    std_logic;
-      tdc2_in_fpga_2_i       : in    std_logic;
-      tdc2_in_fpga_3_i       : in    std_logic;
-      tdc2_in_fpga_4_i       : in    std_logic;
-      tdc2_in_fpga_5_i       : in    std_logic);
+    g_simulation           : boolean := false);
+  port (
+    -- VCXO clock, PoR
+    por_n_i                : in    std_logic;        -- PoR
+    clk_20m_vcxo_i         : in    std_logic;        -- 20 MHz VCXO
+    -- 125 MHz PLL reference
+    clk_125m_pllref_p_i    : in    std_logic;
+    clk_125m_pllref_n_i    : in    std_logic;
+    -- 125 MHz GTP reference
+    clk_125m_gtp_p_i       : in    std_logic;
+    clk_125m_gtp_n_i       : in    std_logic;
+    -- SFP
+    sfp_txp_o              : out   std_logic;
+    sfp_txn_o              : out   std_logic;
+    sfp_rxp_i              : in    std_logic := '0';
+    sfp_rxn_i              : in    std_logic := '1';
+    sfp_mod_def0_i         : in    std_logic;        -- SFP detect pin
+    sfp_mod_def1_b         : inout std_logic;        -- SFP scl
+    sfp_mod_def2_b         : inout std_logic;        -- SFP sda
+    sfp_rate_select_b      : inout std_logic := '0';
+    sfp_tx_fault_i         : in    std_logic := '0';
+    sfp_tx_disable_o       : out   std_logic;
+    sfp_los_i              : in    std_logic := '0';
+    -- Serial DAC
+    pll20dac_din_o         : out   std_logic;
+    pll20dac_sclk_o        : out   std_logic;
+    pll20dac_sync_n_o      : out   std_logic;
+    pll25dac_din_o         : out   std_logic;
+    pll25dac_sclk_o        : out   std_logic;
+    pll25dac_sync_n_o      : out   std_logic;
+    -- UART
+    uart_rxd_i             : in    std_logic := '1';
+    uart_txd_o             : out   std_logic;
+    -- 1-wire
+    carrier_onewire_b      : inout std_logic;        
+    -- SPI Flash
+    spi_sclk_o             : out   std_logic;
+    spi_ncs_o              : out   std_logic;
+    spi_mosi_o             : out   std_logic;
+    spi_miso_i             : in    std_logic;
+    -- SVEC PCB version
+    pcb_ver_i              : in    std_logic_vector(3 downto 0);
+    -- Mezzanines presence
+    tdc1_prsntm2c_n_i      : in    std_logic;        -- Presence of mezzanine #1
+    tdc2_prsntm2c_n_i      : in    std_logic;        -- Presence of mezzanine #2
+    -- SVEC Front panel LEDs
+    fp_led_line_oen_o      : out   std_logic_vector(1 downto 0);
+    fp_led_line_o          : out   std_logic_vector(1 downto 0);
+    fp_led_column_o        : out   std_logic_vector(3 downto 0);
+    -- SVEC Front panel LEMOs
+    fp_gpio1_o             : out   std_logic;        -- PPS output
+    fp_term_en_o           : out   std_logic_vector(4 downto 1); 
+    fp_gpio1_a2b_o         : out   std_logic;
+
+    -- VME interface
+    vme_as_n_i             : in    std_logic;
+    vme_rst_n_i            : in    std_logic;
+    vme_write_n_i          : in    std_logic;
+    vme_am_i               : in    std_logic_vector(5 downto 0);
+    vme_ds_n_i             : in    std_logic_vector(1 downto 0);
+    vme_ga_i               : in    std_logic_vector(5 downto 0);
+    vme_berr_o             : inout std_logic;
+    vme_dtack_n_o          : inout std_logic;
+    vme_retry_n_o          : out   std_logic;
+    vme_retry_oe_o         : out   std_logic;
+    vme_lword_n_b          : inout std_logic;
+    vme_addr_b             : inout std_logic_vector(31 downto 1);
+    vme_data_b             : inout std_logic_vector(31 downto 0);
+    vme_bbsy_n_i           : in    std_logic;
+    vme_irq_o              : out   std_logic_vector(6 downto 0);
+    vme_iack_n_i           : in    std_logic;
+    vme_iackin_n_i         : in    std_logic;
+    vme_iackout_n_o        : out   std_logic;
+    vme_dtack_oe_o         : inout std_logic;
+    vme_data_dir_o         : inout std_logic;
+    vme_data_oe_n_o        : inout std_logic;
+    vme_addr_dir_o         : inout std_logic;
+    vme_addr_oe_n_o        : inout std_logic;
+
+    -- TDC mezzanine board on FMC slot 1
+    -- TDC1 PLL AD9516 and DAC AD5662 interface
+    tdc1_pll_sclk_o        : out   std_logic;
+    tdc1_pll_sdi_o         : out   std_logic;
+    tdc1_pll_cs_n_o        : out   std_logic;
+    tdc1_pll_dac_sync_n_o  : out   std_logic;
+    tdc1_pll_sdo_i         : in    std_logic;
+    tdc1_pll_status_i      : in    std_logic;
+    tdc1_125m_clk_p_i      : in    std_logic;
+    tdc1_125m_clk_n_i      : in    std_logic;
+    tdc1_acam_refclk_p_i   : in    std_logic;
+    tdc1_acam_refclk_n_i   : in    std_logic;
+    -- TDC1 ACAM timing interface
+    tdc1_start_from_fpga_o : out   std_logic;
+    tdc1_err_flag_i        : in    std_logic;
+    tdc1_int_flag_i        : in    std_logic;
+    tdc1_start_dis_o       : out   std_logic;
+    tdc1_stop_dis_o        : out   std_logic;
+    -- TDC1 ACAM data interface
+    tdc1_data_bus_io       : inout std_logic_vector(27 downto 0);
+    tdc1_address_o         : out   std_logic_vector(3 downto 0);
+    tdc1_cs_n_o            : out   std_logic;
+    tdc1_oe_n_o            : out   std_logic;
+    tdc1_rd_n_o            : out   std_logic;
+    tdc1_wr_n_o            : out   std_logic;
+    tdc1_ef1_i             : in    std_logic;
+    tdc1_ef2_i             : in    std_logic;
+    -- TDC1 Input Logic
+    tdc1_enable_inputs_o   : out   std_logic;
+    tdc1_term_en_1_o       : out   std_logic;
+    tdc1_term_en_2_o       : out   std_logic;
+    tdc1_term_en_3_o       : out   std_logic;
+    tdc1_term_en_4_o       : out   std_logic;
+    tdc1_term_en_5_o       : out   std_logic;
+    -- TDC1 1-wire UniqueID & Thermometer
+    tdc1_onewire_b         : inout std_logic;
+    -- TDC1 EEPROM I2C
+    tdc1_scl_b             : inout std_logic;
+    tdc1_sda_b             : inout std_logic;
+    -- TDC1 LEDs
+    tdc1_led_status_o      : out   std_logic;
+    tdc1_led_trig1_o       : out   std_logic;
+    tdc1_led_trig2_o       : out   std_logic;
+    tdc1_led_trig3_o       : out   std_logic;
+    tdc1_led_trig4_o       : out   std_logic;
+    tdc1_led_trig5_o       : out   std_logic;
+    -- TDC1 Input channels, also arriving to the FPGA (not used for the moment)
+    tdc1_in_fpga_1_i       : in    std_logic;
+    tdc1_in_fpga_2_i       : in    std_logic;
+    tdc1_in_fpga_3_i       : in    std_logic;
+    tdc1_in_fpga_4_i       : in    std_logic;
+    tdc1_in_fpga_5_i       : in    std_logic;
+
+    -- TDC mezzanine board on FMC slot 2
+    -- TDC2 PLL AD9516 and DAC AD5662 interface
+    tdc2_pll_sclk_o        : out   std_logic;
+    tdc2_pll_sdi_o         : out   std_logic;
+    tdc2_pll_cs_n_o        : out   std_logic;
+    tdc2_pll_dac_sync_n_o  : out   std_logic;
+    tdc2_pll_sdo_i         : in    std_logic;
+    tdc2_pll_status_i      : in    std_logic;
+    tdc2_125m_clk_p_i      : in    std_logic;
+    tdc2_125m_clk_n_i      : in    std_logic;
+    tdc2_acam_refclk_p_i   : in    std_logic;
+    tdc2_acam_refclk_n_i   : in    std_logic;
+    -- TDC2 ACAM timing interface
+    tdc2_start_from_fpga_o : out   std_logic;
+    tdc2_err_flag_i        : in    std_logic;
+    tdc2_int_flag_i        : in    std_logic;
+    tdc2_start_dis_o       : out   std_logic;
+    tdc2_stop_dis_o        : out   std_logic;
+    -- TDC2 ACAM data interface
+    tdc2_data_bus_io       : inout std_logic_vector(27 downto 0);
+    tdc2_address_o         : out   std_logic_vector(3 downto 0);
+    tdc2_cs_n_o            : out   std_logic;
+    tdc2_oe_n_o            : out   std_logic;
+    tdc2_rd_n_o            : out   std_logic;
+    tdc2_wr_n_o            : out   std_logic;
+    tdc2_ef1_i             : in    std_logic;
+    tdc2_ef2_i             : in    std_logic;
+    -- TDC2 Input Logic
+    tdc2_enable_inputs_o   : out   std_logic;
+    tdc2_term_en_1_o       : out   std_logic;
+    tdc2_term_en_2_o       : out   std_logic;
+    tdc2_term_en_3_o       : out   std_logic;
+    tdc2_term_en_4_o       : out   std_logic;
+    tdc2_term_en_5_o       : out   std_logic;
+    -- TDC2 1-wire UniqueID & Thermometer
+    tdc2_onewire_b         : inout std_logic;
+    -- TDC2 EEPROM I2C
+    tdc2_scl_b             : inout std_logic;
+    tdc2_sda_b             : inout std_logic;
+    -- TDC2 LEDs
+    tdc2_led_status_o      : out   std_logic;
+    tdc2_led_trig1_o       : out   std_logic;
+    tdc2_led_trig2_o       : out   std_logic;
+    tdc2_led_trig3_o       : out   std_logic;
+    tdc2_led_trig4_o       : out   std_logic;
+    tdc2_led_trig5_o       : out   std_logic;
+    -- TDC2 Input channels, also arriving to the FPGA (not used for the moment)
+    tdc2_in_fpga_1_i       : in    std_logic;
+    tdc2_in_fpga_2_i       : in    std_logic;
+    tdc2_in_fpga_3_i       : in    std_logic;
+    tdc2_in_fpga_4_i       : in    std_logic;
+    tdc2_in_fpga_5_i       : in    std_logic);
 end wr_svec_tdc;
 
 --=================================================================================================
@@ -318,32 +326,6 @@ end wr_svec_tdc;
 --=================================================================================================
 architecture rtl of wr_svec_tdc is
 
-  function f_bool2int (x : boolean) return integer is
-  begin
-    if(x) then
-      return 1;
-    else
-      return 0;
-    end if;
-  end f_bool2int;
-
-  component spec_serial_dac is
-    generic (
-      g_num_data_bits  : integer;
-      g_num_extra_bits : integer;
-      g_num_cs_select  : integer);
-    port (
-      clk_i         : in  std_logic;
-      rst_n_i       : in  std_logic;
-      value_i       : in  std_logic_vector(g_num_data_bits-1 downto 0);
-      cs_sel_i      : in  std_logic_vector(g_num_cs_select-1 downto 0);
-      load_i        : in  std_logic;
-      sclk_divsel_i : in  std_logic_vector(2 downto 0);
-      dac_cs_n_o    : out std_logic_vector(g_num_cs_select-1 downto 0);
-      dac_sclk_o    : out std_logic;
-      dac_sdata_o   : out std_logic;
-      xdone_o       : out std_logic);
-  end component spec_serial_dac;
 ---------------------------------------------------------------------------------------------------
 --                                         SDB CONSTANTS                                         --
 ---------------------------------------------------------------------------------------------------
@@ -403,77 +385,49 @@ architecture rtl of wr_svec_tdc is
 --                                            Signals                                            --
 ---------------------------------------------------------------------------------------------------
 
- -- Clocks
-  -- CLOCK DOMAIN: 20 MHz VCXO clock on SVEC carrier board: clk_20m_vcxo_i
-  signal clk_20m_vcxo_buf, clk_20m_vcxo       : std_logic;
+  signal areset_n : std_logic;
+
+  -- Clocks
   -- CLOCK DOMAIN: 62.5 MHz system clock derived from clk_20m_vcxo_i by a Xilinx PLL: clk_62m5_sys
-  signal clk_62m5_sys, pllout_clk_sys         : std_logic;
-  signal pllout_clk_sys_fb, sys_locked        : std_logic;
-  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1: tdc1_125m_clk
-  signal tdc1_125m_clk       : std_logic;
-  signal tdc1_send_dac_word_p                 : std_logic;
-  signal tdc1_dac_word                        : std_logic_vector(23 downto 0);
-  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC2: tdc2_125m_clk
-  signal tdc2_125m_clk       : std_logic;
-  signal tdc2_send_dac_word_p                 : std_logic;
-  signal tdc2_dac_word                        : std_logic_vector(23 downto 0);
-  -- WHITE RABBIT CLOCKS:
-  signal pllout_clk_dmtd, pllout_clk_fb_dmtd  : std_logic;
-  signal pllout_clk_fb_pllref                 : std_logic;
-  signal clk_125m_pllref, clk_125m_gtp        : std_logic;
-  signal clk_dmtd                             : std_logic;
-
-  attribute buffer_type                       : string;  --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
-  attribute buffer_type of clk_125m_pllref    : signal is "BUFG";
+  signal clk_sys_62m5  : std_logic;
+  -- CLOCK DOMAIN: 125 MHz clock from PLL on TDC1 and TDC2
+  signal tdc1_125m_clk : std_logic;
+  signal tdc2_125m_clk : std_logic;
 
 ---------------------------------------------------------------------------------------------------
- -- Resets
-  -- asynchronous reset from the FPGA inputs VME_RST_n_i and por_n_i
-  signal por_rst_n_a                          : std_logic;
-  signal powerup_rst_cnt                      : unsigned(7 downto 0) := "00000000";
+  -- Resets
   -- system reset, synched with 62.5 MHz clock,driven by the VME reset and power-up reset pins.
-  signal rst_n_sys                            : std_logic;
+  signal rst_sys_62m5_n       : std_logic;
   -- reset input to the clks_rsts_manager units of the two TDC cores;
   -- this reset initiates the configuration of the mezzanines PLL
-  signal tdc1_soft_rst_n                      : std_logic; -- driven by carrier CSR reserved bit 0
-  signal tdc2_soft_rst_n                      : std_logic; -- driven by carrier CSR reserved bit 1
-  signal carrier_info_fmc_rst                 : std_logic_vector(30 downto 0);
-  signal carrier_info_stat_reserv             : std_logic_vector(27 downto 0);
+  signal tdc1_soft_rst_n      : std_logic; -- driven by carrier CSR reserved bit 0
+  signal tdc2_soft_rst_n      : std_logic; -- driven by carrier CSR reserved bit 1
+  signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
 
 ---------------------------------------------------------------------------------------------------
  -- VME interface
-  signal VME_DATA_b_out                       : std_logic_vector(31 downto 0);
-  signal VME_ADDR_b_out                       : std_logic_vector(31 downto 1);
-  signal VME_LWORD_n_b_out                    : std_logic;
-  signal VME_DATA_DIR_int                     : std_logic;
-  signal VME_ADDR_DIR_int                     : std_logic;
+  signal vme_data_b_out       : std_logic_vector(31 downto 0);
+  signal vme_addr_b_out       : std_logic_vector(31 downto 1);
+  signal vme_lword_n_b_out    : std_logic;
+  signal vme_data_dir_int     : std_logic;
+  signal vme_addr_dir_int     : std_logic;
+  signal vme_berr_n           : std_logic;
+  signal vme_irq_n            : std_logic_vector(6 downto 0);
 
 ---------------------------------------------------------------------------------------------------
   -- White Rabbit signals to TDC mezzanine
   signal tm_link_up, tm_time_valid            : std_logic;
-  signal tm_utc                               : std_logic_vector(39 downto 0);
+  signal tm_tai                               : std_logic_vector(39 downto 0);
   signal tm_cycles                            : std_logic_vector(27 downto 0);
   signal tm_clk_aux_lock_en, tm_clk_aux_locked: std_logic_vector(1 downto 0);
   -- White Rabbit signals to clks_rsts_manager
   signal tm_dac_value                         : std_logic_vector(23 downto 0);
   signal tm_dac_wr_p                          : std_logic_vector(1 downto 0);
-  -- White Rabbit PHY
-  signal phy_tx_data, phy_rx_data             : std_logic_vector(7 downto 0);
-  signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
-  signal phy_tx_enc_err, phy_rx_rbclk         : std_logic;
-  signal phy_rx_enc_err, phy_rst, phy_loopen  : std_logic;
-  signal phy_rx_bitslide                      : std_logic_vector(3 downto 0);
-  -- White Rabbit serial DAC
-  signal dac_hpll_load_p1, dac_dpll_load_p1   : std_logic;
-  signal dac_hpll_data, dac_dpll_data         : std_logic_vector(15 downto 0);
-  -- White Rabbit to mezzanine EEPROM
-  signal wrc_scl_out, wrc_scl_in              : std_logic;
-  signal wrc_sda_out, wrc_sda_in              : std_logic;
   -- White Rabbit to SFP EEPROM
   signal sfp_scl_out, sfp_scl_in              : std_logic;
   signal sfp_sda_out, sfp_sda_in              : std_logic;
   -- White Rabbit Carrier 1-Wire
-  signal wrc_owr_en, wrc_owr_in               : std_logic_vector(1 downto 0);
+  signal wrc_owr_oe, wrc_owr_data             : std_logic;
 
 ---------------------------------------------------------------------------------------------------
  -- Crossbar
@@ -483,6 +437,7 @@ architecture rtl of wr_svec_tdc is
   -- WISHBONE to crossbar slave port
   signal cnx_slave_out                        : t_wishbone_slave_out_array (c_NUM_WB_SLAVES-1 downto 0);
   signal cnx_slave_in                         : t_wishbone_slave_in_array  (c_NUM_WB_SLAVES-1 downto 0);
+  signal vme_wb_in                            : t_wishbone_master_in;
 
 ---------------------------------------------------------------------------------------------------
 -- Interrupts
@@ -496,331 +451,21 @@ architecture rtl of wr_svec_tdc is
   signal tdc2_scl_oen, tdc2_scl_in            : std_logic;
   signal tdc2_sda_oen, tdc2_sda_in            : std_logic;
 
-  signal carrier_owr_en, carrier_owr_i        : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
   -- LEDs
   signal led_state                            : std_logic_vector(15 downto 0);
   signal tdc1_ef, tdc2_ef, led_tdc1_ef        : std_logic;
   signal led_tdc2_ef, led_vme_access          : std_logic;
-  signal wrabbit_led_red, wrabbit_led_green   : std_logic;
+  signal wr_led_act, wr_led_link              : std_logic;
 
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
 begin
 
----------------------------------------------------------------------------------------------------
---                                     62.5 MHz system clock                                     --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  svec_clk_ibuf : IBUFG
-  port map
-  (I => clk_20m_vcxo_i,
-   O => clk_20m_vcxo_buf);
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_sys_clk_pll : PLL_BASE
-  generic map
-    (BANDWIDTH          => "OPTIMIZED",
-     CLK_FEEDBACK       => "CLKFBOUT",
-     COMPENSATION       => "INTERNAL",
-     DIVCLK_DIVIDE      => 1,
-     CLKFBOUT_MULT      => 8,    -- 125 MHz x 8 = 1 GHz
-     CLKFBOUT_PHASE     => 0.000,
-     CLKOUT0_DIVIDE     => 16,    -- 62.5 MHz
-     CLKOUT0_PHASE      => 0.000,
-     CLKOUT0_DUTY_CYCLE => 0.500,
-     CLKOUT1_DIVIDE     => 16,    -- 125 MHz, not used
-     CLKOUT1_PHASE      => 0.000,
-     CLKOUT1_DUTY_CYCLE => 0.500,
-     CLKOUT2_DIVIDE     => 16,
-     CLKOUT2_PHASE      => 0.000,
-     CLKOUT2_DUTY_CYCLE => 0.500,
-     CLKIN_PERIOD       => 8.0,
-     REF_JITTER         => 0.016)
-  port map
-    (CLKFBOUT => pllout_clk_sys_fb,
-     CLKOUT0  => pllout_clk_sys,
-     CLKOUT1  => open,
-     CLKOUT2  => open,
-     CLKOUT3  => open,
-     CLKOUT4  => open,
-     CLKOUT5  => open,
-     LOCKED   => sys_locked,
-     RST      => '0',
-     CLKFBIN  => pllout_clk_sys_fb,
-     CLKIN    => clk_125m_pllref);
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_clk_sys_buf : BUFG
-  port map
-    (O => clk_62m5_sys,
-     I => pllout_clk_sys);
-
-
----------------------------------------------------------------------------------------------------
---                                         62.5 MHz Reset                                        --
----------------------------------------------------------------------------------------------------
--- SVEC power-up reset in the clk_62m5_sys domain: rst_n_sys is asserted asynchronously upon VME
--- reset or SVEC AFPGA power-on reset. If none of these signals is asserted at startup, the process
--- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
--- the reset.
-
-  p_powerup_reset : process(clk_62m5_sys, por_rst_n_a)
-  begin
-    if(por_rst_n_a = '0') then
-      rst_n_sys           <= '0';
-    elsif rising_edge(clk_62m5_sys) then
-      if sys_locked = '1' then
-        if(powerup_rst_cnt = "11111111") then
-          rst_n_sys       <= '1';
-        else
-          rst_n_sys       <= '0';
-          powerup_rst_cnt <= powerup_rst_cnt + 1;
-        end if;
-      else
-        rst_n_sys         <= '0';
-        powerup_rst_cnt   <= "00000000";
-      end if;
-    end if;
-  end process;
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  por_rst_n_a <= VME_RST_n_i and por_n_i;
-
-
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  tdc1_soft_rst_n             <= carrier_info_fmc_rst(0) and rst_n_sys;
-  tdc2_soft_rst_n              <= carrier_info_fmc_rst(1) and rst_n_sys;
-
-
----------------------------------------------------------------------------------------------------
---                                      62.5 MHz DMTD clock                                      --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_dmtd_clk_pll : PLL_BASE
-  generic map
-    (BANDWIDTH          => "OPTIMIZED",
-     CLK_FEEDBACK       => "CLKFBOUT",
-     COMPENSATION       => "INTERNAL",
-     DIVCLK_DIVIDE      => 1,
-     CLKFBOUT_MULT      => 50,
-     CLKFBOUT_PHASE     => 0.000,
-     CLKOUT0_DIVIDE     => 16,         -- 62.5 MHz
-     CLKOUT0_PHASE      => 0.000,
-     CLKOUT0_DUTY_CYCLE => 0.500,
-     CLKOUT1_DIVIDE     => 16,         -- not used
-     CLKOUT1_PHASE      => 0.000,
-     CLKOUT1_DUTY_CYCLE => 0.500,
-     CLKOUT2_DIVIDE     => 8,
-     CLKOUT2_PHASE      => 0.000,
-     CLKOUT2_DUTY_CYCLE => 0.500,
-     CLKIN_PERIOD       => 50.0,
-     REF_JITTER         => 0.016)
-  port map
-    (CLKFBOUT           => pllout_clk_fb_dmtd,
-     CLKOUT0            => pllout_clk_dmtd,
-     CLKOUT1            => open,
-     CLKOUT2            => open,
-     CLKOUT3            => open,
-     CLKOUT4            => open,
-     CLKOUT5            => open,
-     LOCKED             => open,
-     RST                => '0',
-     CLKFBIN            => pllout_clk_fb_dmtd,
-     CLKIN              => clk_20m_vcxo_buf);
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_clk_dmtd_buf : BUFG
-  port map
-    (O => clk_dmtd,
-     I => pllout_clk_dmtd);
-
-
----------------------------------------------------------------------------------------------------
---                               125 MHz clk for White Rabbit core                               --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_Buf_CLK_PLL : IBUFGDS
-  generic map
-    (DIFF_TERM    => true,
-     IBUF_LOW_PWR => true)       -- Low power (TRUE) vs. performance (FALSE) setting for referenced
-  port map
-    (O  => clk_125m_pllref,      -- Buffer output
-     I  => clk_125m_pllref_p_i,  -- Diff_p buffer input (connect directly to top-level port)
-     IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
-
-     --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_Buf_CLK_GTP : IBUFDS
-  generic map
-    (DIFF_TERM   => true,
-     IBUF_LOW_PWR => false)
-  port map
-    (O  => clk_125m_gtp,
-     I  => clk_125m_gtp_p_i,
-     IB => clk_125m_gtp_n_i);
-
-
----------------------------------------------------------------------------------------------------
---                                  White Rabbit Core + PHY                                      --
----------------------------------------------------------------------------------------------------
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_WR_CORE : xwr_core
-  generic map
-    (g_simulation                => f_bool2int(g_simulation),
-     g_phys_uart                 => true,
-     g_virtual_uart              => true,
-     g_with_external_clock_input => false,
-     g_aux_clks                  => 2,
-     g_ep_rxbuf_size             => 1024,
-     g_dpram_initf               => "wrc.ram",
-     g_dpram_size                => 90112/4,
-     g_interface_mode            => PIPELINED,
-     g_address_granularity       => BYTE,
-     g_softpll_enable_debugger   => false)
-  port map
-    (clk_sys_i                   => clk_62m5_sys,
-     clk_dmtd_i                  => clk_dmtd,
-     clk_ref_i                   => clk_125m_pllref,
-     clk_aux_i(0)                => tdc1_125m_clk,
-     clk_aux_i(1)                => tdc2_125m_clk,
-     rst_n_i                     => rst_n_sys,
-     -- DAC
-     dac_hpll_load_p1_o          => dac_hpll_load_p1,
-     dac_hpll_data_o             => dac_hpll_data,
-     dac_dpll_load_p1_o          => dac_dpll_load_p1,
-     dac_dpll_data_o             => dac_dpll_data,
-     -- PHY
-     phy_ref_clk_i               => clk_125m_pllref,
-     phy_tx_data_o               => phy_tx_data,
-     phy_tx_k_o                  => phy_tx_k,
-     phy_tx_disparity_i          => phy_tx_disparity,
-     phy_tx_enc_err_i            => phy_tx_enc_err,
-     phy_rx_data_i               => phy_rx_data,
-     phy_rx_rbclk_i              => phy_rx_rbclk,
-     phy_rx_k_i                  => phy_rx_k,
-     phy_rx_enc_err_i            => phy_rx_enc_err,
-     phy_rx_bitslide_i           => phy_rx_bitslide,
-     phy_rst_o                   => phy_rst,
-     phy_loopen_o                => phy_loopen,
-     -- SPEC LEDs
-     led_act_o                   => wrabbit_led_red,
-     led_link_o                  => wrabbit_led_green,
-     -- SFP
-     scl_o                       => wrc_scl_out,
-     scl_i                       => wrc_scl_in,
-     sda_o                       => wrc_sda_out,
-     sda_i                       => wrc_sda_in,
-     sfp_scl_o                   => sfp_scl_out,
-     sfp_scl_i                   => sfp_scl_in,
-     sfp_sda_o                   => sfp_sda_out,
-     sfp_sda_i                   => sfp_sda_in,
-     sfp_det_i                   => sfp_mod_def0_b,
-
-     uart_rxd_i                  => uart_rxd_i,
-     uart_txd_o                  => uart_txd_o,
-     -- 1-wire
-     owr_en_o                    => wrc_owr_en,
-     owr_i                       => wrc_owr_in,
-     -- WISHBONE
-     slave_i                     => cnx_master_out(c_SLAVE_WRCORE),
-     slave_o                     => cnx_master_in(c_SLAVE_WRCORE),
-     -- Timimg info for TDC core
-     tm_link_up_o                => tm_link_up,
-     tm_dac_value_o              => tm_dac_value,
-     tm_dac_wr_o                 => tm_dac_wr_p,
-     tm_clk_aux_lock_en_i        => tm_clk_aux_lock_en,
-     tm_clk_aux_locked_o         => tm_clk_aux_locked,
-     tm_time_valid_o             => tm_time_valid,
-     tm_tai_o                    => tm_utc,
-     tm_cycles_o                 => tm_cycles,
-     -- not used
-     btn1_i                      => '0',
-     btn2_i                      => '0',
-     pps_p_o                     => open,
-     -- aux reset
-     rst_aux_n_o                 => open);
-
-  gen_with_wr_phy: if g_with_wr_phy generate
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_GTP : wr_gtp_phy_spartan6
-  generic map
-    (g_simulation       => 0,
-     g_enable_ch0       => 0,
-     g_enable_ch1       => 1)
-  port map
-    (gtp_clk_i          => clk_125m_gtp,
-     ch0_ref_clk_i      => clk_125m_pllref,
-     ch0_tx_data_i      => x"00",
-     ch0_tx_k_i         => '0',
-     ch0_tx_disparity_o => open,
-     ch0_tx_enc_err_o   => open,
-     ch0_rx_rbclk_o     => open,
-     ch0_rx_data_o      => open,
-     ch0_rx_k_o         => open,
-     ch0_rx_enc_err_o   => open,
-     ch0_rx_bitslide_o  => open,
-     ch0_rst_i          => '1',
-     ch0_loopen_i       => '0',
-     ch1_ref_clk_i      => clk_125m_pllref,
-     ch1_tx_data_i      => phy_tx_data,
-     ch1_tx_k_i         => phy_tx_k,
-     ch1_tx_disparity_o => phy_tx_disparity,
-     ch1_tx_enc_err_o   => phy_tx_enc_err,
-     ch1_rx_data_o      => phy_rx_data,
-     ch1_rx_rbclk_o     => phy_rx_rbclk,
-     ch1_rx_k_o         => phy_rx_k,
-     ch1_rx_enc_err_o   => phy_rx_enc_err,
-     ch1_rx_bitslide_o  => phy_rx_bitslide,
-     ch1_rst_i          => phy_rst,
-     ch1_loopen_i       => '0', -- phy_loopen,
-     pad_txn0_o         => open,
-     pad_txp0_o         => open,
-     pad_rxn0_i         => '0',
-     pad_rxp0_i         => '0',
-     pad_txn1_o         => sfp_txn_o,
-     pad_txp1_o         => sfp_txp_o,
-     pad_rxn1_i         => sfp_rxn_i,
-     pad_rxp1_i         => sfp_rxp_i);
-
-  end generate gen_with_wr_phy;
-
-  
---  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_DAC_Helper : spec_serial_dac
-  generic map
-    (g_num_data_bits  => 16,
-     g_num_extra_bits => 8,
-     g_num_cs_select  => 1)
-  port map
-    (clk_i            => clk_62m5_sys,
-     rst_n_i          => rst_n_sys,
-     value_i          => dac_hpll_data,
-     cs_sel_i         => "1",
-     load_i           => dac_hpll_load_p1,
-     sclk_divsel_i    => "010",
-     dac_cs_n_o(0)    => pll20dac_sync_n_o,
-     dac_sclk_o       => pll20dac_sclk_o,
-     dac_sdata_o      => pll20dac_din_o,
-     xdone_o          => open);
-
-  U_DAC_Main : spec_serial_dac
-  generic map
-    (g_num_data_bits  => 16,
-     g_num_extra_bits => 8,
-     g_num_cs_select  => 1)
-  port map
-    (clk_i         => clk_62m5_sys,
-     rst_n_i       => rst_n_sys,
-     value_i       => dac_dpll_data,
-     cs_sel_i      => "1",
-     load_i        => dac_dpll_load_p1,
-     sclk_divsel_i => "010",
-     dac_cs_n_o(0) => pll25dac_sync_n_o,
-     dac_sclk_o    => pll25dac_sclk_o,
-     dac_sdata_o   => pll25dac_din_o,
-     xdone_o       => open);
-
+  areset_n <= vme_rst_n_i and por_n_i;
+  tdc1_soft_rst_n  <= carrier_info_fmc_rst(0) and rst_sys_62m5_n;
+  tdc2_soft_rst_n  <= carrier_info_fmc_rst(1) and rst_sys_62m5_n;
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Tristates for mezzanine EEPROM
@@ -828,21 +473,77 @@ begin
   tdc2_scl_b   <= '0' when (tdc2_scl_oen = '0') else 'Z';
   tdc2_sda_b   <= '0' when (tdc2_sda_oen = '0') else 'Z';
 
+---------------------------------------------------------------------------------------------------
+--                                      SVEC Board Wrapper                                       --
+---------------------------------------------------------------------------------------------------
+  cmp_xwrc_board_svec : xwrc_board_svec
+    generic map (
+      g_simulation                => f_bool2int(g_simulation),
+      g_with_external_clock_input => FALSE,
+      g_dpram_initf               => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
+      g_fabric_iface              => plain,
+      g_aux_clks                  => 2)
+    port map (
+      clk_20m_vcxo_i      => clk_20m_vcxo_i,
+      clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+      clk_125m_gtp_n_i    => clk_125m_gtp_n_i,
+      clk_125m_gtp_p_i    => clk_125m_gtp_p_i,
+      clk_aux_i(0)        => tdc1_125m_clk,
+      clk_aux_i(1)        => tdc2_125m_clk,
+      areset_n_i          => areset_n,
+      clk_sys_62m5_o      => clk_sys_62m5,
+      rst_sys_62m5_n_o    => rst_sys_62m5_n,
+      pll20dac_din_o      => pll20dac_din_o,
+      pll20dac_sclk_o     => pll20dac_sclk_o,
+      pll20dac_sync_n_o   => pll20dac_sync_n_o,
+      pll25dac_din_o      => pll25dac_din_o,
+      pll25dac_sclk_o     => pll25dac_sclk_o,
+      pll25dac_sync_n_o   => pll25dac_sync_n_o,
+      sfp_txp_o           => sfp_txp_o,
+      sfp_txn_o           => sfp_txn_o,
+      sfp_rxp_i           => sfp_rxp_i,
+      sfp_rxn_i           => sfp_rxn_i,
+      sfp_det_i           => sfp_mod_def0_i,
+      sfp_sda_i           => sfp_sda_in,
+      sfp_sda_o           => sfp_sda_out,
+      sfp_scl_i           => sfp_scl_in,
+      sfp_scl_o           => sfp_scl_out,
+      sfp_rate_select_o   => sfp_rate_select_b,
+      sfp_tx_fault_i      => sfp_tx_fault_i,
+      sfp_tx_disable_o    => sfp_tx_disable_o,
+      sfp_los_i           => sfp_los_i,
+      onewire_i           => wrc_owr_data,
+      onewire_oen_o       => wrc_owr_oe,
+      uart_rxd_i          => uart_rxd_i,
+      uart_txd_o          => uart_txd_o,
+      spi_sclk_o          => spi_sclk_o,
+      spi_ncs_o           => spi_ncs_o,
+      spi_mosi_o          => spi_mosi_o,
+      spi_miso_i          => spi_miso_i,
+      wb_slave_o          => cnx_master_in(c_SLAVE_WRCORE),
+      wb_slave_i          => cnx_master_out(c_SLAVE_WRCORE),
+      tm_link_up_o        => tm_link_up,
+      tm_dac_value_o      => tm_dac_value,
+      tm_dac_wr_o         => tm_dac_wr_p,
+      tm_clk_aux_lock_en_i=> tm_clk_aux_lock_en,
+      tm_clk_aux_locked_o => tm_clk_aux_locked,
+      tm_time_valid_o     => tm_time_valid,
+      tm_tai_o            => tm_tai,
+      tm_cycles_o         => tm_cycles,
+      pps_p_o             => fp_gpio1_o,
+
+      led_link_o          => wr_led_link,
+      led_act_o           => wr_led_act);
 
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Tristates for SFP EEPROM
-  sfp_mod_def1_b      <= '0' when sfp_scl_out = '0' else 'Z';
-  sfp_mod_def2_b      <= '0' when sfp_sda_out = '0' else 'Z';
-  sfp_scl_in          <= sfp_mod_def1_b;
-  sfp_sda_in          <= sfp_mod_def2_b;
-
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  carrier_onewire_b   <= '0' when wrc_owr_en(0) = '1' else 'Z';
-  wrc_owr_in(0)       <= carrier_onewire_b;
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-
-  -- The SFP is permanently enabled.
-  sfp_tx_disable_o <= '0';
+  sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+  sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+  sfp_scl_in     <= sfp_mod_def1_b;
+  sfp_sda_in     <= sfp_mod_def2_b;
+  -- Tristates for 1-wire thermometer
+  carrier_onewire_b   <= '0' when wrc_owr_oe = '1' else 'Z';
+  wrc_owr_data        <= carrier_onewire_b;
 
 ---------------------------------------------------------------------------------------------------
 --                                     CSR WISHBONE CROSSBAR                                     --
@@ -864,8 +565,8 @@ begin
      g_layout      => c_INTERCONNECT_LAYOUT,
      g_sdb_addr    => c_SDB_ADDRESS)
   port map
-    (clk_sys_i => clk_62m5_sys,
-     rst_n_i   => rst_n_sys,
+    (clk_sys_i => clk_sys_62m5,
+     rst_n_i   => rst_sys_62m5_n,
      slave_i   => cnx_slave_in,
      slave_o   => cnx_slave_out,
      master_i  => cnx_master_in,
@@ -877,59 +578,75 @@ begin
 ---------------------------------------------------------------------------------------------------
   U_VME_Core : xvme64x_core
   generic map (
-    g_clock_freq => 62500000,
-    g_adem_a24   => x"fff80000")
+    g_CLOCK_PERIOD    => 16,
+    g_DECODE_AM       => True,
+    g_USER_CSR_EXT    => False,
+    g_WB_GRANULARITY  => BYTE,
+    g_MANUFACTURER_ID => c_CERN_ID,
+    g_BOARD_ID        => c_SVEC_ID,
+    g_REVISION_ID     => c_SVEC_REVISION_ID,
+    g_PROGRAM_ID      => c_SVEC_PROGRAM_ID)
   port map
-    (clk_i           => clk_62m5_sys,
-     rst_n_i         => rst_n_sys,
-     VME_AS_n_i      => VME_AS_n_i,
-     VME_RST_n_i     => VME_RST_n_i,
-     VME_WRITE_n_i   => VME_WRITE_n_i,
-     VME_AM_i        => VME_AM_i,
-     VME_DS_n_i      => VME_DS_n_i,
-     VME_GA_i        => VME_GA_i,
-     VME_BERR_o      => VME_BERR_o,
-     VME_DTACK_n_o   => VME_DTACK_n_o,
-     VME_RETRY_n_o   => VME_RETRY_n_o,
-     VME_RETRY_OE_o  => VME_RETRY_OE_o,
-     VME_LWORD_n_b_i => VME_LWORD_n_b,
-     VME_LWORD_n_b_o => VME_LWORD_n_b_out,
-     VME_ADDR_b_i    => VME_ADDR_b,
-     VME_DATA_b_o    => VME_DATA_b_out,
-     VME_ADDR_b_o    => VME_ADDR_b_out,
-     VME_DATA_b_i    => VME_DATA_b,
-     VME_IRQ_n_o     => VME_IRQ_n_o,
-     VME_IACK_n_i    => VME_IACK_n_i,
-     VME_IACKIN_n_i  => VME_IACKIN_n_i,
-     VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-     VME_DTACK_OE_o  => VME_DTACK_OE_o,
-     VME_DATA_DIR_o  => VME_DATA_DIR_int,
-     VME_DATA_OE_N_o => VME_DATA_OE_N_o,
-     VME_ADDR_DIR_o  => VME_ADDR_DIR_int,
-     VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
-     master_o        => cnx_slave_in (c_MASTER_VME),
-     master_i        => cnx_slave_out(c_MASTER_VME),
-     irq_i           => irq_to_vmecore);
+    (clk_i            => clk_sys_62m5,
+     rst_n_i          => rst_sys_62m5_n,
+     vme_i.as_n       => vme_as_n_i,
+     vme_i.rst_n      => vme_rst_n_i,
+     vme_i.write_n    => vme_write_n_i,
+     vme_i.am         => vme_am_i,
+     vme_i.ds_n       => vme_ds_n_i,
+     vme_i.ga         => vme_ga_i,
+     vme_i.lword_n    => vme_lword_n_b,
+     vme_i.addr       => vme_addr_b,
+     vme_i.data       => vme_data_b,
+     vme_i.iack_n     => vme_iack_n_i,
+     vme_i.iackin_n   => vme_iackin_n_i,
+     vme_o.berr_n     => vme_berr_n,
+     vme_o.dtack_n    => vme_dtack_n_o,
+     vme_o.retry_n    => vme_retry_n_o,
+     vme_o.retry_oe   => vme_retry_oe_o,
+     vme_o.lword_n    => vme_lword_n_b_out,
+     vme_o.data       => vme_data_b_out,
+     vme_o.addr       => vme_addr_b_out,
+     vme_o.irq_n      => vme_irq_n,
+     vme_o.iackout_n  => vme_iackout_n_o,
+     vme_o.dtack_oe   => vme_dtack_oe_o,
+     vme_o.data_dir   => vme_data_dir_int,
+     vme_o.data_oe_n  => vme_data_oe_n_o,
+     vme_o.addr_dir   => vme_addr_dir_int,
+     vme_o.addr_oe_n  => vme_addr_oe_n_o,
+     wb_o             => cnx_slave_in(c_MASTER_VME),
+     wb_i             => vme_wb_in);
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  VME_DATA_b         <= VME_DATA_b_out    when VME_DATA_DIR_int = '1' else (others => 'Z');
-  VME_ADDR_b         <= VME_ADDR_b_out    when VME_ADDR_DIR_int = '1' else (others => 'Z');
-  VME_LWORD_n_b      <= VME_LWORD_n_b_out when VME_ADDR_DIR_int = '1' else 'Z';
-  VME_ADDR_DIR_o     <= VME_ADDR_DIR_int;
-  VME_DATA_DIR_o     <= VME_DATA_DIR_int;
+  vme_berr_o <= not vme_berr_n;
+  vme_irq_o  <= not vme_irq_n;
 
+  -- Drive inject also IRQ to the WB interface.
+  vme_wb_in.ack      <= cnx_slave_out(c_MASTER_VME).ack;
+  vme_wb_in.err      <= cnx_slave_out(c_MASTER_VME).err;
+  vme_wb_in.rty      <= cnx_slave_out(c_MASTER_VME).rty;
+  vme_wb_in.stall    <= cnx_slave_out(c_MASTER_VME).stall;
+  vme_wb_in.dat      <= cnx_slave_out(c_MASTER_VME).dat;
+  vme_wb_in.int      <= irq_to_vmecore;
+
+  -- VME tri-state bufferes
+  vme_data_b         <= vme_data_b_out    when vme_data_dir_int = '1' else (others => 'Z');
+  vme_addr_b         <= vme_addr_b_out    when vme_addr_dir_int = '1' else (others => 'Z');
+  vme_lword_n_b      <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
+
+  vme_addr_dir_o     <= vme_addr_dir_int;
+  vme_data_dir_o     <= vme_data_dir_int;
 
 ---------------------------------------------------------------------------------------------------
 --                                            TDC BOARDS                                         --
 ---------------------------------------------------------------------------------------------------
-
      
    cmp_tdc_mezzanine_1: fmc_tdc_wrapper
     generic map (
       g_simulation          => g_simulation,
       g_with_direct_readout => false )
     port map (
-      clk_sys_i            => clk_62m5_sys,
-      rst_sys_n_i          => rst_n_sys,
+      clk_sys_i            => clk_sys_62m5,
+      rst_sys_n_i          => rst_sys_62m5_n,
       rst_n_a_i            => tdc1_soft_rst_n,
       pll_sclk_o           => tdc1_pll_sclk_o,
       pll_sdi_o            => tdc1_pll_sdi_o,
@@ -981,24 +698,22 @@ begin
       tm_link_up_i         => tm_link_up,
       tm_time_valid_i      => tm_time_valid,
       tm_cycles_i          => tm_cycles,
-      tm_tai_i             => tm_utc,
+      tm_tai_i             => tm_tai,
       tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(0),
       tm_clk_aux_locked_i  => tm_clk_aux_locked(0),
       tm_clk_dmtd_locked_i => '1',
       tm_dac_value_i       => tm_dac_value,
       tm_dac_wr_i          => tm_dac_wr_p(0),
 
-      slave_i        => cnx_master_out(c_SLAVE_TDC0),
-      slave_o        => cnx_master_in(c_SLAVE_TDC0),
+      slave_i              => cnx_master_out(c_SLAVE_TDC0),
+      slave_o              => cnx_master_in(c_SLAVE_TDC0),
 
       irq_o                => tdc1_irq,
       clk_125m_tdc_o       => tdc1_125m_clk);
 
 
-  tdc1_scl_b   <= '0' when (tdc1_scl_oen = '0' or wrc_scl_out = '0') else 'Z';
-  tdc1_sda_b   <= '0' when (tdc1_sda_oen = '0' or wrc_sda_out = '0') else 'Z';
-  wrc_scl_in   <= tdc1_scl_b;
-  wrc_sda_in   <= tdc1_sda_b;
+  tdc1_scl_b   <= '0' when (tdc1_scl_oen = '0') else 'Z';
+  tdc1_sda_b   <= '0' when (tdc1_sda_oen = '0') else 'Z';
   tdc1_scl_in  <= tdc1_scl_b;
   tdc1_sda_in  <= tdc1_sda_b;
 
@@ -1007,8 +722,8 @@ begin
       g_simulation          => g_simulation,
       g_with_direct_readout => false )
     port map (
-      clk_sys_i            => clk_62m5_sys,
-      rst_sys_n_i          => rst_n_sys,
+      clk_sys_i            => clk_sys_62m5,
+      rst_sys_n_i          => rst_sys_62m5_n,
       rst_n_a_i            => tdc2_soft_rst_n,
       pll_sclk_o           => tdc2_pll_sclk_o,
       pll_sdi_o            => tdc2_pll_sdi_o,
@@ -1060,15 +775,15 @@ begin
       tm_link_up_i         => tm_link_up,
       tm_time_valid_i      => tm_time_valid,
       tm_cycles_i          => tm_cycles,
-      tm_tai_i             => tm_utc,
+      tm_tai_i             => tm_tai,
       tm_clk_aux_lock_en_o => tm_clk_aux_lock_en(1),
       tm_clk_aux_locked_i  => tm_clk_aux_locked(1),
       tm_clk_dmtd_locked_i => '1',
       tm_dac_value_i       => tm_dac_value,
       tm_dac_wr_i          => tm_dac_wr_p(1),
 
-      slave_i        => cnx_master_out(c_SLAVE_TDC1),
-      slave_o        => cnx_master_in(c_SLAVE_TDC1),
+      slave_i              => cnx_master_out(c_SLAVE_TDC1),
+      slave_o              => cnx_master_in(c_SLAVE_TDC1),
 
       irq_o                => tdc2_irq,
       clk_125m_tdc_o       => tdc2_125m_clk);
@@ -1091,8 +806,8 @@ begin
      g_num_interrupts      => 2,
      g_init_vectors        => c_VIC_VECTOR_TABLE)
   port map
-    (clk_sys_i             => clk_62m5_sys,
-     rst_n_i               => rst_n_sys,
+    (clk_sys_i             => clk_sys_62m5,
+     rst_n_i               => rst_sys_62m5_n,
      slave_i               => cnx_master_out(c_SLAVE_VIC),
      slave_o               => cnx_master_in(c_SLAVE_VIC),
      irqs_i(0)             => tdc1_irq,
@@ -1106,8 +821,8 @@ begin
 -- Also added software resets for the clks_rsts_manager units
   cmp_carrier_info : carrier_info
   port map
-    (rst_n_i                           => rst_n_sys,
-     clk_sys_i                         => clk_62m5_sys,
+    (rst_n_i                           => rst_sys_62m5_n,
+     clk_sys_i                         => clk_sys_62m5,
      wb_adr_i                          => cnx_master_out(c_SLAVE_SVEC_INFO).adr(3 downto 2),
      wb_dat_i                          => cnx_master_out(c_SLAVE_SVEC_INFO).dat,
      wb_dat_o                          => cnx_master_in(c_SLAVE_SVEC_INFO).dat,
@@ -1122,7 +837,9 @@ begin
      carrier_info_carrier_type_i       => c_CARRIER_TYPE,
      carrier_info_stat_fmc_pres_i      => tdc1_prsntm2c_n_i,
      carrier_info_stat_p2l_pll_lck_i   => '0',
-     carrier_info_stat_sys_pll_lck_i   => sys_locked,
+     -- SVEC board wrapper releases rst_sys_62m5_n only when system clock pll is
+     -- locked. Therefore we report here '1' - pll locked
+     carrier_info_stat_sys_pll_lck_i   => '1',
      carrier_info_stat_ddr3_cal_done_i => '0',
 
      carrier_info_stat_reserved_i(27 downto 1)   => (others => '1'),
@@ -1153,8 +870,8 @@ begin
      g_CLK_FREQ      => 62500000,  -- in Hz
      g_REFRESH_RATE  => 250)       -- in Hz
   port map
-    (rst_n_i         => rst_n_sys,
-     clk_i           => clk_62m5_sys,
+    (rst_n_i         => rst_sys_62m5_n,
+     clk_i           => clk_sys_62m5,
      led_intensity_i => "1100100", -- in %
      led_state_i     => led_state,
      column_o        => fp_led_column_o,
@@ -1167,9 +884,9 @@ begin
   -- fp led number  :  | 5 | 6 | 7 | 8 | 1 | 2 | 3 | 4 |
 
   -- LED 1: White Rabbit act
-  led_state(7  downto  6) <= c_LED_RED   when wrabbit_led_red      = '1' else c_LED_OFF;
+  led_state(7  downto  6) <= c_LED_RED   when wr_led_act           = '1' else c_LED_OFF;
   -- LED 2: White Rabbit link
-  led_state(5  downto  4) <= c_LED_GREEN when wrabbit_led_green    = '1' else c_LED_OFF;
+  led_state(5  downto  4) <= c_LED_GREEN when wr_led_link          = '1' else c_LED_OFF;
   -- LED 3: TDC1 empty flag
   led_state(3  downto  2) <= c_LED_GREEN when led_tdc1_ef          = '1' else c_LED_OFF;
   -- LED 4: TDC2 empty flag
@@ -1188,8 +905,8 @@ begin
   generic map
     (g_width    => 5000000)
   port map
-    (clk_i      => clk_62m5_sys,
-     rst_n_i    => rst_n_sys,
+    (clk_i      => clk_sys_62m5,
+     rst_n_i    => rst_sys_62m5_n,
      pulse_i    => cnx_slave_in(c_MASTER_VME).cyc,
      extended_o => led_vme_access);
 
@@ -1198,8 +915,8 @@ begin
   generic map
     (g_width    => 5000000)
   port map
-    (clk_i      => clk_62m5_sys,
-     rst_n_i    => rst_n_sys,
+    (clk_i      => clk_sys_62m5,
+     rst_n_i    => rst_sys_62m5_n,
      pulse_i    => tdc1_ef,
      extended_o => led_tdc1_ef);
   --  --  --  --  --  --  --
@@ -1210,13 +927,16 @@ begin
   generic map
     (g_width    => 5000000)
   port map
-    (clk_i      => clk_62m5_sys,
-     rst_n_i    => rst_n_sys,
+    (clk_i      => clk_sys_62m5,
+     rst_n_i    => rst_sys_62m5_n,
      pulse_i    => tdc2_ef,
      extended_o => led_tdc2_ef);
   --  --  --  --  --  --  --
   tdc2_ef <= not(tdc2_ef1_i) or not(tdc2_ef2_i);
 
+  fp_term_en_o    <= (others => '0');
+  fp_gpio1_a2b_o  <= '1';
+
 
 end rtl;
 ----------------------------------------------------------------------------------------------------