diff --git a/hdl/rtl/Manifest.py b/hdl/rtl/Manifest.py
index 19dff9dec7a57acb11e39e1186527ed13957f54e..995c9b00bcc039fd67b156a15971ae52d2cb2d2d 100644
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
@@ -3,7 +3,6 @@ files = [
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
-"circular_buffer.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
@@ -12,7 +11,6 @@ files = [
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
-"irq_generator.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
@@ -23,5 +21,8 @@ files = [
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
+"timestamp_fifo.vhd",
+"timestamp_fifo_wb.vhd",
+"timestamp_fifo_wbgen2_pkg.vhd"
];
diff --git a/hdl/rtl/circular_buffer.vhd b/hdl/rtl/circular_buffer.vhd
deleted file mode 100644
index c57061c4af4301288996d3e5d04e2ba3be6dfbb5..0000000000000000000000000000000000000000
--- a/hdl/rtl/circular_buffer.vhd
+++ /dev/null
@@ -1,320 +0,0 @@
---_________________________________________________________________________________________________
--- |
--- |TDC core| |
--- |
--- CERN,BE/CO-HT |
---________________________________________________________________________________________________|
-
----------------------------------------------------------------------------------------------------
--- |
--- circular_buffer |
--- |
----------------------------------------------------------------------------------------------------
--- File circular_buffer.vhd |
--- |
--- Description Dual port RAM circular buffer for timestamp storage; contains the RAM block and |
--- the WISHBONE slave interfaces: |
--- o The data_formatting unit is writing 128-bit long timestamps, using a WISHBONE |
--- classic interface. The unit implements a WISHBONE classic slave. |
--- As figure 1 indicates, from this side the memory is of size: 255 * 128. |
--- o The GN4124/VME core is reading 32-bit words. Readings take place using |
--- pipelined WISHBONE interface. For the PCi-e interface, Direct Memory Access can|
--- take place on this side. The unit implements the WISHBONE pipelined slave. |
--- As figure 1 indicates, from this side the memory is of size: 1024 * 32. |
--- |
--- Note also that in principle the data_formatting unit is only writing in the RAM |
--- and the GN4124/VME core is only reading from it. |
--- |
--- |
--- RAM as seen from the RAM as seen from the |
--- data_formatting unit GN4124/VME core |
--- ____________________________________________________________ _______________ |
--- 0 | 128 bits | 0 | 32 bits | |
--- |____________________________________________________________| |_______________| |
--- 1 | 128 bits | 1 | 32 bits | |
--- |____________________________________________________________| |_______________| |
--- . | 128 bits | 2 | 32 bits | |
--- |____________________________________________________________| <==> |_______________| |
--- . | 128 bits | 3 | 32 bits | |
--- |____________________________________________________________| |_______________| |
--- | 128 bits | 4 | 32 bits | |
--- 255|____________________________________________________________| |_______________| |
--- . | 32 bits | |
--- |_______________| |
--- . | 32 bits | |
--- |_______________| |
--- . | 32 bits | |
--- |_______________| |
--- . | 32 bits | |
--- |_______________| |
--- 1021 | 32 bits | |
--- |_______________| |
--- 1022 | 32 bits | |
--- |_______________| |
--- 1023 | 32 bits | |
--- |_______________| |
--- Figuure 1: RAM configuration |
--- |
--- |
--- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
--- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
--- Date 04/2012 |
--- Version v0.11 |
--- Depends on |
--- |
----------------- |
--- Last changes |
--- 10/2011 v0.1 GP First version |
--- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
--- |
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- GNU LESSER GENERAL PUBLIC LICENSE |
--- ------------------------------------ |
--- This source file is free software; you can redistribute it and/or modify it under the terms of |
--- the GNU Lesser General Public License as published by the Free Software Foundation; either |
--- version 2.1 of the License, or (at your option) any later version. |
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
--- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
--- See the GNU Lesser General Public License for more details. |
--- You should have received a copy of the GNU Lesser General Public License along with this |
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
----------------------------------------------------------------------------------------------------
-
-
-
---=================================================================================================
--- Libraries & Packages
---=================================================================================================
-
--- Standard library
-library IEEE;
-use IEEE.std_logic_1164.all; -- std_logic definitions
-use IEEE.NUMERIC_STD.all; -- conversion functions
--- Specific library
-library work;
-use work.tdc_core_pkg.all; -- definitions of types, constants, entities
-use work.genram_pkg.all; -- for the RAM
-
---=================================================================================================
--- Entity declaration for circular_buffer
---=================================================================================================
-
-entity circular_buffer is
- port
- -- INPUTS
- -- Signal from the clk_rst_manager
- (clk_tdc_i : in std_logic; -- 125 MHz clock; same for both ports
- clk_sys_i : in std_logic;
-
- rst_n_sys_i : in std_logic;
-
- -- Signals from the data_formatting unit (WISHBONE classic): timestamps writing
- tstamp_wr_rst_i : in std_logic; -- timestamp writing WISHBONE reset
- tstamp_wr_stb_i : in std_logic; -- timestamp writing WISHBONE strobe
- tstamp_wr_cyc_i : in std_logic; -- timestamp writing WISHBONE cycle
- tstamp_wr_we_i : in std_logic; -- timestamp writing WISHBONE write enable
- tstamp_wr_adr_i : in std_logic_vector(7 downto 0); -- adr 8 bits long 2^8 = 255
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0); -- timestamp 128 bits long
-
- -- Signals from the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
- tdc_mem_wb_rst_i : in std_logic; -- timestamp reading WISHBONE reset
- tdc_mem_wb_stb_i : in std_logic; -- timestamp reading WISHBONE strobe
- tdc_mem_wb_cyc_i : in std_logic; -- timestamp reading WISHBONE cycle
- tdc_mem_wb_we_i : in std_logic; -- timestamp reading WISHBONE write enable; not used
- tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0); -- adr 10 bits long 2^10 = 1024
- tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0); -- not used
-
- -- OUTPUTS
- -- Signals to the data_formatting unit (WISHBONE classic): timestamps writing
- tstamp_wr_ack_p_o : out std_logic; -- timestamp writing WISHBONE classic acknowledge
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- not used
-
- -- Signals to the GN4124/VME core unit (WISHBONE pipelined): timestamps reading
- tdc_mem_wb_ack_o : out std_logic; -- timestamp reading WISHBONE pipelined acknowledge
- tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0); -- 32 bit words
- tdc_mem_wb_stall_o : out std_logic); -- timestamp reading WISHBONE pipelined stall
-
-end circular_buffer;
-
---=================================================================================================
--- architecture declaration
---=================================================================================================
-architecture rtl of circular_buffer is
-
- type t_wb_wr is (IDLE, MEM_ACCESS, MEM_ACCESS_AND_ACKNOWLEDGE, ACKNOWLEDGE);
- type t_rd_data_array is array(0 to 3) of std_logic_vector(31 downto 0);
-
- signal tstamp_rd_wb_st, nxt_tstamp_rd_wb_st : t_wb_wr;
- signal tstamp_wr_ack_p : std_logic;
- signal tstamp_rd_we, tstamp_wr_we : std_logic_vector(3 downto 0);
- signal mb_data : t_rd_data_array;
- signal adr_d0 : std_logic_vector(1 downto 0);
-
---=================================================================================================
--- architecture begin
---=================================================================================================
-begin
-
----------------------------------------------------------------------------------------------------
--- TIMESTAMP WRITINGS WISHBONE CLASSIC ACK --
----------------------------------------------------------------------------------------------------
- -- WISHBONE classic interface compatible slave
- classic_interface : process (clk_tdc_i)
- begin
- if rising_edge (clk_tdc_i) then
- if tstamp_wr_rst_i = '1' then
- tstamp_wr_ack_p <= '0';
-
- elsif tstamp_wr_stb_i = '1' and tstamp_wr_cyc_i = '1' and tstamp_wr_ack_p = '0' then
- tstamp_wr_ack_p <= '1'; -- a new 1 clk-wide ack is given for each stb
- else
- tstamp_wr_ack_p <= '0';
- end if;
- end if;
- end process;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- tstamp_wr_ack_p_o <= tstamp_wr_ack_p;
-
-
----------------------------------------------------------------------------------------------------
--- TIMESTAMP READINGS WISHBONE PIPELINE ACK --
----------------------------------------------------------------------------------------------------
--- FSM for the generation of the pipelined WISHBONE ACK signal.
--- Note that the first output from the memory comes 2 clk cycles after the address setting.
-
--- CLK : --|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--- STB : _____|-----------------------------------|_________________
--- CYC : _____|-----------------------------------|_________________
--- ADR : <ADR0><ADR1><ADR2><ADR3><ADR4><ADR5>
--- ACK : _________________|-----------------------------------|_____
--- DATO: <DAT0><DAT1><DAT2><DAT3><DAT4><DAT5>
-
- WB_pipe_ack_fsm_seq : process (clk_sys_i)
- begin
- if rising_edge (clk_sys_i) then
- if tdc_mem_wb_rst_i = '1' then
- tstamp_rd_wb_st <= IDLE;
- else
- tstamp_rd_wb_st <= nxt_tstamp_rd_wb_st;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------------------------------
- WB_pipe_ack_fsm_comb : process (tstamp_rd_wb_st, tdc_mem_wb_stb_i, tdc_mem_wb_cyc_i)
- begin
- case tstamp_rd_wb_st is
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when IDLE =>
- -----------------------------------------------
- tdc_mem_wb_ack_o <= '0';
- -----------------------------------------------
-
- if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
- nxt_tstamp_rd_wb_st <= MEM_ACCESS;
- else
- nxt_tstamp_rd_wb_st <= IDLE;
- end if;
-
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when MEM_ACCESS =>
-
- -----------------------------------------------
- tdc_mem_wb_ack_o <= '0';
- -----------------------------------------------
-
- if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
- nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
- else
- nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
- end if;
-
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when MEM_ACCESS_AND_ACKNOWLEDGE =>
- -----------------------------------------------
- tdc_mem_wb_ack_o <= '1';
- -----------------------------------------------
-
- if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
- nxt_tstamp_rd_wb_st <= MEM_ACCESS_AND_ACKNOWLEDGE;
- else
- nxt_tstamp_rd_wb_st <= ACKNOWLEDGE;
- end if;
-
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when ACKNOWLEDGE =>
- -----------------------------------------------
- tdc_mem_wb_ack_o <= '1';
- -----------------------------------------------
-
- if tdc_mem_wb_stb_i = '1' and tdc_mem_wb_cyc_i = '1' then
- nxt_tstamp_rd_wb_st <= MEM_ACCESS;
- else
- nxt_tstamp_rd_wb_st <= IDLE;
- end if;
-
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when others =>
- -----------------------------------------------
- tdc_mem_wb_ack_o <= '0';
- -----------------------------------------------
-
- nxt_tstamp_rd_wb_st <= IDLE;
- end case;
- end process;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- tdc_mem_wb_stall_o <= '0';
-
- gen_mem_blocks : for i in 0 to 3 generate
-
- memory_block : generic_dpram
- generic map (
- g_data_width => 32,
- g_size => 256,
- g_with_byte_enable => false,
- g_addr_conflict_resolution => "write_first",
- g_dual_clock => true)
- port map (
- rst_n_i => rst_n_sys_i,
- clka_i => clk_tdc_i,
- wea_i => tstamp_wr_we(0),
- aa_i => tstamp_wr_adr_i(7 downto 0),
- da_i => tstamp_wr_dat_i(32*i + 31 downto 32*i),
- clkb_i => clk_sys_i,
- web_i => '0',
- ab_i => tdc_mem_wb_adr_i(9 downto 2),
- db_i => tdc_mem_wb_dat_i,
- qb_o => mb_data(i));
-
--- tstamp_rd_we(i) <= '1' when unsigned(tdc_mem_wb_adr_i(1 downto 0)) = i else '0';
-
- process(clk_sys_i)
- begin
- if rising_edge(clk_sys_i) then
- adr_d0 <= tdc_mem_wb_adr_i(1 downto 0);
- end if;
- end process;
-
- tdc_mem_wb_dat_o <= mb_data(to_integer(unsigned(adr_d0)));
-
- end generate gen_mem_blocks;
-
- tstamp_wr_we(0) <= tstamp_wr_we_i and tstamp_wr_cyc_i and tstamp_wr_stb_i;
-
-
-end architecture rtl;
---=================================================================================================
--- architecture end
---=================================================================================================
----------------------------------------------------------------------------------------------------
--- E N D O F F I L E
----------------------------------------------------------------------------------------------------
diff --git a/hdl/rtl/data_formatting.vhd b/hdl/rtl/data_formatting.vhd
index 8886f768cd6e8cf814bc68f03425240e824a5c5a..812ef0f8fbfe2897260afccd3f93ae1a5bf730a0 100644
--- a/hdl/rtl/data_formatting.vhd
+++ b/hdl/rtl/data_formatting.vhd
@@ -61,11 +61,11 @@
-- Standard library
library IEEE;
-use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
-use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
+use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
+use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
-use work.tdc_core_pkg.all; -- definitions of types, constants, entities
+use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
@@ -73,28 +73,21 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
entity data_formatting is
port
- -- INPUTS
- -- Signal from the clk_rst_manager
- (clk_i : in std_logic; -- 125 MHz clk
- rst_i : in std_logic; -- general reset
-
- -- Signals from the circular_buffer unit: WISHBONE classic
- tstamp_wr_wb_ack_i : in std_logic; -- tstamp writing WISHBONE acknowledge
+ -- INPUTS
+ -- Signal from the clk_rst_manager
+ (clk_i : in std_logic; -- 125 MHz clk
+ rst_i : in std_logic; -- general reset
-- Signals from the data_engine unit
- acam_tstamp1_ok_p_i : in std_logic; -- tstamp1 valid indicator
- acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
- -- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
- acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
- acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
- -- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
-
- -- Signals from the reg_ctrl unit
- dacapo_c_rst_p_i : in std_logic; -- instruction from GN4124/VME to clear dacapo flag
- deactivate_chan_i : in std_logic_vector(4 downto 0); -- instruction from GN4124/VME to stop registering tstamps from a specific channel
-
- -- Signals from the one_hz_gen unit
- utc_i : in std_logic_vector(31 downto 0); -- local UTC time
+ acam_tstamp1_ok_p_i : in std_logic; -- tstamp1 valid indicator
+ acam_tstamp1_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
+ -- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO1
+ acam_tstamp2_ok_p_i : in std_logic; -- tstamp2 valid indicator
+ acam_tstamp2_i : in std_logic_vector(31 downto 0); -- 32 bits tstamp to be treated and stored;
+ -- includes ef1 & ef2 & 0 & 0 & 28 bits tstamp from FIFO2
+
+-- Signals from the one_hz_gen unit
+ utc_i : in std_logic_vector(31 downto 0); -- local UTC time
-- Signals from the start_retrig_ctrl unit
roll_over_incr_recent_i : in std_logic;
@@ -103,26 +96,15 @@ entity data_formatting is
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
-- Signal from the WRabbit core or the one_hz_generator unit
- utc_p_i : in std_logic;
+ utc_p_i : in std_logic;
- -- OUTPUTS
- -- Signals to the circular_buffer unit: WISHBONE classic
- tstamp_wr_wb_cyc_o : out std_logic; -- tstamp writing WISHBONE cycle
- tstamp_wr_wb_stb_o : out std_logic; -- tstamp writing WISHBONE strobe
- tstamp_wr_wb_we_o : out std_logic; -- tstamp writing WISHBONE write enable
- tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0); -- WISHBONE adr to write to
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0); -- tstamp to write
+ -- OUTPUTS
- -- Signal to the irq_generator unit
- tstamp_wr_p_o : out std_logic; -- pulse upon storage of a new tstamp
- acam_channel_o : out std_logic_vector(2 downto 0); --
+ timestamp_o : out std_logic_vector(127 downto 0);
+ timestamp_valid_o : out std_logic
- -- Signal to the reg_ctrl unit
- wr_index_o : out std_logic_vector(31 downto 0)); -- index of last byte written
- -- note that the index is provided
- -- #bytes, as the GN4124/VME expects
- -- (not in #128-bits-words)
+ );
end data_formatting;
@@ -131,7 +113,6 @@ end data_formatting;
--=================================================================================================
architecture rtl of data_formatting is
- constant c_MULTIPLY_BY_SIXTEEN : std_logic_vector(3 downto 0) := "0000";
-- ACAM timestamp fields
signal acam_channel : std_logic_vector(2 downto 0);
signal acam_slope : std_logic;
@@ -145,15 +126,10 @@ architecture rtl of data_formatting is
-- final timestamp fields
signal full_timestamp : std_logic_vector(127 downto 0);
signal metadata, utc, coarse_time, fine_time : std_logic_vector(31 downto 0);
- -- circular buffer timestamp writings WISHBONE interface
- signal tstamp_wr_cyc, tstamp_wr_stb, tstamp_wr_we : std_logic;
- -- circular buffer counters
- signal dacapo_counter : unsigned(19 downto 0);
- signal wr_index : unsigned(7 downto 0);
-- coarse time calculations
signal tstamp_on_first_retrig_case1 : std_logic;
signal tstamp_on_first_retrig_case2 : std_logic;
- signal coarse_zero : std_logic; -- for debug
+ signal coarse_zero : std_logic; -- for debug
signal un_previous_clk_i_cycles_offset : unsigned(31 downto 0);
signal un_previous_retrig_nb_offset : unsigned(31 downto 0);
signal un_previous_roll_over_nb : unsigned(31 downto 0);
@@ -167,130 +143,19 @@ architecture rtl of data_formatting is
-- architecture begin
--=================================================================================================
begin
-
----------------------------------------------------------------------------------------------------
--- WISHBONE STB, CYC, WE, ADR --
----------------------------------------------------------------------------------------------------
--- WISHBONE_master_signals: Generation of the WISHBONE classic signals STB, CYC, WE that initiate
--- writes to the circular_buffer memory. Upon acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i activation
--- and according to the value of the deactivate_chan_i register, the process activates the
--- STB, CYC, WE signals and waits for an ACK; as soon as the ACK arrives, the tstamps are
--- written in the memory and the STB, CYC and WE are deactivated; then a new acam_tstamp1_ok_p_i or
--- acam_tstamp2_ok_p_i pulse is awaited to initiate a new write cycle.
--- Reminder: timestamps (acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i pulses) can arrive at maximum
--- every 4 clk_i cycles (31.25 MHz).
-
--- clk_i : __|-|__|-|__|-|__|-|__|-|__|-|__|-|__|-|__|-|__|-|__|-|__ ...
--- acam_tstamp1_ok_p : ____________|----|______________|----|___________________ ...
--- tstamp_wr_wb_dat : _________________< one tstamp >< another tstamp > ...
--- tstamp_wr_wb_adr : address 0 >< address 1 >< address 2...
--- tstamp_wr_stb : _________________|--------|_________|---------|__________ ...
--- tstamp_wr_ack : ______________________|---|______________|----|__________ ...
-
- WISHBONE_master_signals: process (clk_i)
- begin
- if rising_edge (clk_i) then
- if rst_i = '1' then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
-
- elsif acam_tstamp1_ok_p_i = '1' then
- if deactivate_chan_i = "00000" then
- tstamp_wr_stb <= '1';
- tstamp_wr_cyc <= '1';
- tstamp_wr_we <= '1';
- else
- if deactivate_chan_i = "00001" and acam_tstamp1_i(27 downto 26) = "00" then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- elsif deactivate_chan_i = "00010" and acam_tstamp1_i(27 downto 26) = "01" then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- elsif deactivate_chan_i = "00100" and acam_tstamp1_i(27 downto 26) = "10" then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- elsif deactivate_chan_i = "01000" and acam_tstamp1_i(27 downto 26) = "11" then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- else
- tstamp_wr_stb <= '1';
- tstamp_wr_cyc <= '1';
- tstamp_wr_we <= '1';
- end if;
- end if;
- elsif acam_tstamp2_ok_p_i = '1' then
- if deactivate_chan_i = "10000" then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- else
- tstamp_wr_stb <= '1';
- tstamp_wr_cyc <= '1';
- tstamp_wr_we <= '1';
- end if;
- elsif tstamp_wr_wb_ack_i = '1' then
- tstamp_wr_stb <= '0';
- tstamp_wr_cyc <= '0';
- tstamp_wr_we <= '0';
- end if;
- end if;
- end process;
-
--- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--- tstamp_wr_wb_adr: the process keeps track of the place in the memory the next timestamp is to be
--- written; wr_index indicates which one is the next address to write to.
--- The index is also used by the GN4124 host to configure the DMA coherently (DMALENR register)
- tstamp_wr_wb_adr: process (clk_i)
+ p_gen_timestamp_valid : process (clk_i)
begin
if rising_edge (clk_i) then
- if rst_i ='1' or dacapo_c_rst_p_i = '1' then
- wr_index <= (others => '0');
-
- elsif tstamp_wr_cyc = '1' and tstamp_wr_stb = '1' and tstamp_wr_we = '1' and tstamp_wr_wb_ack_i = '1' then
-
- if wr_index = c_CIRCULAR_BUFF_SIZE - 1 then
- wr_index <= (others => '0'); -- when memory completed, restart from the beginning
- else
- wr_index <= wr_index + 1; -- otherwise write to the next one
- end if;
-
- end if;
- end if;
- end process;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- tstamp_wr_p_o <= tstamp_wr_cyc and tstamp_wr_stb and tstamp_wr_we and tstamp_wr_wb_ack_i;
- tstamp_wr_wb_adr_o <= std_logic_vector(wr_index);
- wr_index_o <= std_logic_vector(dacapo_counter) & std_logic_vector(wr_index) & c_MULTIPLY_BY_SIXTEEN;
- -- "& c_MULTIPLY_BY_SIXTEEN" for the conversion to the number of 8-bits-words
- -- for the configuration of the DMA
-
----------------------------------------------------------------------------------------------------
--- Da Capo flag --
----------------------------------------------------------------------------------------------------
--- dacapo_counter_update: the Da Capo counter indicates the number of times the circular buffer
--- has been written completely; it can be cleared by the GN4124/VME host.
- dacapo_counter_update: process (clk_i)
- begin
- if rising_edge (clk_i) then
- if rst_i ='1' or dacapo_c_rst_p_i = '1' then
- dacapo_counter <= (others => '0');
-
- elsif tstamp_wr_cyc = '1' and tstamp_wr_stb = '1' and tstamp_wr_we = '1' and
- tstamp_wr_wb_ack_i = '1' and wr_index = c_CIRCULAR_BUFF_SIZE - 1 then
- dacapo_counter <= dacapo_counter + 1;
+ if rst_i = '1' then
+ timestamp_valid_o <= '0';
+ else
+ timestamp_valid_o <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
end if;
end if;
end process;
-
---------------------------------------------------------------------------------------------------
-- Final Timestamp Formatting --
---------------------------------------------------------------------------------------------------
@@ -322,10 +187,10 @@ begin
-- [127:96] Metadata for each timestamp: Slope(rising or falling tstamp), Channel
- tstamp_formatting: process (clk_i) -- ACAM data handling DFF #2 (DFF #1 refers to the registering of the acam_tstamp1/2_ok_p)
- begin
+ tstamp_formatting : process (clk_i) -- ACAM data handling DFF #2 (DFF #1 refers to the registering of the acam_tstamp1/2_ok_p)
+ begin
if rising_edge (clk_i) then
- if rst_i ='1' then
+ if rst_i = '1' then
acam_channel <= (others => '0');
acam_fine_timestamp <= (others => '0');
acam_slope <= '0';
@@ -337,7 +202,7 @@ begin
acam_slope <= acam_tstamp1_i(17);
acam_start_nb <= unsigned(acam_tstamp1_i(25 downto 18))-1;
- elsif acam_tstamp2_ok_p_i ='1' then
+ elsif acam_tstamp2_ok_p_i = '1' then
acam_channel <= "1" & acam_tstamp2_i(27 downto 26);
acam_fine_timestamp <= acam_tstamp2_i(16 downto 0);
acam_slope <= acam_tstamp2_i(17);
@@ -347,8 +212,8 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- reg_info_of_previous_sec: process (clk_i)
- begin
+ reg_info_of_previous_sec : process (clk_i)
+ begin
if rising_edge (clk_i) then
if rst_i = '1' then
un_previous_clk_i_cycles_offset <= (others => '0');
@@ -400,37 +265,37 @@ begin
-- Eva: have to calculate better the amount of tstamps that could have been accumulated before the rollover changes;
-- the current value we put "192" is not well studied for all cases!!
- coarse_time_intermed_calcul: process (clk_i) -- ACAM data handling DFF #3; at the next cycle (#4) the data is written in memory
- begin
+ coarse_time_intermed_calcul : process (clk_i) -- ACAM data handling DFF #3; at the next cycle (#4) the data is written in memory
+ begin
if rising_edge (clk_i) then
- if rst_i ='1' then
- un_clk_i_cycles_offset <= (others => '0');
- un_retrig_nb_offset <= (others => '0');
- un_retrig_from_roll_over <= (others => '0');
- utc <= (others => '0');
- coarse_zero <= '0';
+ if rst_i = '1' then
+ un_clk_i_cycles_offset <= (others => '0');
+ un_retrig_nb_offset <= (others => '0');
+ un_retrig_from_roll_over <= (others => '0');
+ utc <= (others => '0');
+ coarse_zero <= '0';
else
-- ACAM tstamp arrived on the same retgigger after a new second
- if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
- (un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0) ) then
+ if (un_acam_start_nb+un_current_retrig_from_roll_over = un_current_retrig_nb_offset) or
+ (un_acam_start_nb = un_current_retrig_nb_offset-1 and un_acam_fine_time > 6318 and (un_current_retrig_from_roll_over = 0)) then
- coarse_zero <= '1';
- un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
- un_retrig_nb_offset <= un_previous_retrig_nb_offset;
- utc <= previous_utc;
- un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
+ coarse_zero <= '1';
+ un_clk_i_cycles_offset <= un_previous_clk_i_cycles_offset;
+ un_retrig_nb_offset <= un_previous_retrig_nb_offset;
+ utc <= previous_utc;
+ un_retrig_from_roll_over <= shift_left(un_previous_roll_over_nb, 8);
else
- un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
- un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
- utc <= utc_i;
- coarse_zero <= '0';
+ un_clk_i_cycles_offset <= unsigned(clk_i_cycles_offset_i);
+ un_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
+ utc <= utc_i;
+ coarse_zero <= '0';
if roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 then
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i)-1, 8);
else
un_retrig_from_roll_over <= shift_left(unsigned(roll_over_nb_i), 8);
end if;
- end if;
+ end if;
end if;
end if;
end process;
@@ -438,49 +303,40 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- the number of internal start retriggers actually occurred is calculated by subtracting the offset number
-- already present when the one_hz_pulse arrives, and adding the start nb provided by the ACAM.
- un_nb_of_retrig <= un_retrig_from_roll_over - (un_retrig_nb_offset) + un_acam_start_nb;
+ un_nb_of_retrig <= un_retrig_from_roll_over - (un_retrig_nb_offset) + un_acam_start_nb;
-- finally, the coarse time is obtained by multiplying by the number of clk_i cycles in an internal
-- start retrigger period and adding the number of clk_i cycles still to be discounted when the
-- one_hz_pulse arrives.
- un_nb_of_cycles <= shift_left(un_nb_of_retrig, c_ACAM_RETRIG_PERIOD_SHIFT) + un_clk_i_cycles_offset;
+ un_nb_of_cycles <= shift_left(un_nb_of_retrig, c_ACAM_RETRIG_PERIOD_SHIFT) + un_clk_i_cycles_offset;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- coarse time: expressed as the number of 125 MHz clock cycles since the last one_hz_pulse.
-- Since the clk_i and the pulse are derived from the same PLL, any offset between them is constant
-- and will cancel when subtracting timestamps.
- coarse_time <= std_logic_vector(un_nb_of_cycles);-- when coarse_zero = '0' else std_logic_vector(64-unsigned(clk_i_cycles_offset_i));
+ coarse_time <= std_logic_vector(un_nb_of_cycles); -- when coarse_zero = '0' else std_logic_vector(64-unsigned(clk_i_cycles_offset_i));
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- fine time: directly provided by ACAM as a number of BINs since the last internal retrigger
- fine_time <= x"000" & "000" & acam_fine_timestamp;
+ fine_time <= x"000" & "000" & acam_fine_timestamp;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- metadata: information about the timestamp
- metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- for debug
- coarse_zero & std_logic_vector(un_retrig_nb_offset(7 downto 0)) & -- for debug
- std_logic_vector(roll_over_nb_i(2 downto 0)) &
- std_logic_vector(un_clk_i_cycles_offset(6 downto 0)) & -- for debug
- acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits used for slope and acam_channel
+ metadata <= std_logic_vector(acam_start_nb(7 downto 0)) & -- for debug
+ coarse_zero & std_logic_vector(un_retrig_nb_offset(7 downto 0)) & -- for debug
+ std_logic_vector(roll_over_nb_i(2 downto 0)) &
+ std_logic_vector(un_clk_i_cycles_offset(6 downto 0)) & -- for debug
+ acam_slope & roll_over_incr_recent_i & acam_channel; -- 5 LSbits used for slope and acam_channel
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata;
- tstamp_wr_dat_o <= full_timestamp;
-
+ timestamp_o <= full_timestamp;
----------------------------------------------------------------------------------------------------
--- Outputs --
----------------------------------------------------------------------------------------------------
- tstamp_wr_wb_cyc_o <= tstamp_wr_cyc;
- tstamp_wr_wb_stb_o <= tstamp_wr_stb;
- tstamp_wr_wb_we_o <= tstamp_wr_we;
- acam_channel_o <= acam_channel;
-
-
+
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
-----------------------------------------------------------------------------------------------------
\ No newline at end of file
+----------------------------------------------------------------------------------------------------
diff --git a/hdl/rtl/fmc_tdc_core.vhd b/hdl/rtl/fmc_tdc_core.vhd
index 384eb79bd57af0baca7dfcd55d39217c6e906d44..9ca83ce69b2014a7c744282f9fc25be548e712cb 100644
--- a/hdl/rtl/fmc_tdc_core.vhd
+++ b/hdl/rtl/fmc_tdc_core.vhd
@@ -206,11 +206,9 @@ entity fmc_tdc_core is
tdc_in_fpga_3_i : in std_logic; -- TDC input Ch.3, not used
tdc_in_fpga_4_i : in std_logic; -- TDC input Ch.4, not used
tdc_in_fpga_5_i : in std_logic; -- TDC input Ch.5, not used
- -- Interrupts
- irq_tstamp_p_o : out std_logic; -- if amount of tstamps > tstamps_threshold
- irq_time_p_o : out std_logic; -- if 0 < amount of tstamps < tstamps_threshold and time > time_threshold
- irq_acam_err_p_o : out std_logic; -- if ACAM err_flag_i is activated
- -- White Rabbit control and status registers
+
+
+-- White Rabbit control and status registers
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
-- White Rabbit timing
@@ -223,13 +221,12 @@ entity fmc_tdc_core is
cfg_slave_i: in t_wishbone_slave_in;
cfg_slave_o: out t_wishbone_slave_out;
- -- WISHBONE bus interface with the GN4124/VME core for the retrieval
- -- of the timestamps from the TDC core memory (clk_sys)
- mem_slave_i: in t_wishbone_slave_in;
- mem_slave_o: out t_wishbone_slave_out;
+ timestamp_o : out std_logic_vector(127 downto 0);
+ timestamp_stb_o : out std_logic;
- direct_timestamp_o : out std_logic_vector(127 downto 0);
- direct_timestamp_stb_o : out std_logic
+ channel_enable_o : out std_logic_vector(4 downto 0);
+ irq_threshold_o : out std_logic_vector(9 downto 0);
+ irq_timeout_o : out std_logic_vector(9 downto 0)
);
end fmc_tdc_core;
@@ -252,15 +249,15 @@ architecture rtl of fmc_tdc_core is
signal activate_acq_p, deactivate_acq_p, load_acam_config : std_logic;
signal read_acam_config, read_acam_status, read_ififo1 : std_logic;
signal read_ififo2, read_start01, reset_acam, load_utc : std_logic;
- signal clear_dacapo_counter, roll_over_incr_recent : std_logic;
+ signal roll_over_incr_recent : std_logic;
signal deactivate_chan : std_logic_vector(4 downto 0);
signal pulse_delay, window_delay, clk_period : std_logic_vector(g_width-1 downto 0);
signal starting_utc, acam_inputs_en : std_logic_vector(g_width-1 downto 0);
signal acam_ififo1, acam_ififo2, acam_start01 : std_logic_vector(g_width-1 downto 0);
signal irq_tstamp_threshold, irq_time_threshold : std_logic_vector(g_width-1 downto 0);
- signal local_utc, wr_index : std_logic_vector(g_width-1 downto 0);
+ signal local_utc : std_logic_vector(g_width-1 downto 0);
signal acam_config, acam_config_rdbk : config_vector;
- signal tstamp_wr_p, start_from_fpga, state_active_p : std_logic;
+ signal start_from_fpga, state_active_p : std_logic;
-- retrigger control
signal clk_i_cycles_offset, roll_over_nb, retrig_nb_offset: std_logic_vector(g_width-1 downto 0);
signal local_utc_p : std_logic;
@@ -268,11 +265,7 @@ architecture rtl of fmc_tdc_core is
-- UTC
signal utc_p : std_logic;
signal utc, wrabbit_ctrl_reg : std_logic_vector(g_width-1 downto 0);
- -- circular buffer
- signal circ_buff_class_adr : std_logic_vector(7 downto 0);
- signal circ_buff_class_stb, circ_buff_class_cyc : std_logic;
- signal circ_buff_class_we, circ_buff_class_ack : std_logic;
- signal circ_buff_class_data_wr, circ_buff_class_data_rd : std_logic_vector(4*g_width-1 downto 0);
+
-- LEDs
signal acam_channel : std_logic_vector(5 downto 0);
signal tdc_in_fpga_1, tdc_in_fpga_2, tdc_in_fpga_3 : std_logic_vector(1 downto 0);
@@ -280,7 +273,8 @@ architecture rtl of fmc_tdc_core is
signal acam_tstamp_channel : std_logic_vector(2 downto 0);
signal rst_sys: std_logic;
-
+ signal timestamp_valid : std_logic;
+ signal timestamp : std_logic_vector(127 downto 0);
--=================================================================================================
@@ -317,8 +311,6 @@ begin
acam_rdbk_start01_p_o => read_start01,
acam_rst_p_o => reset_acam,
load_utc_p_o => load_utc,
- dacapo_c_rst_p_o => clear_dacapo_counter,
- deactivate_chan_o => deactivate_chan,
acam_config_rdbk_i => acam_config_rdbk,
acam_ififo1_i => acam_ififo1,
acam_ififo2_i => acam_ififo2,
@@ -326,7 +318,6 @@ begin
local_utc_i => utc,
irq_code_i => x"00000000",
core_status_i => x"00000000",
- wr_index_i => wr_index,
wrabbit_status_reg_i => wrabbit_status_reg_i,
wrabbit_ctrl_reg_o => wrabbit_ctrl_reg,
acam_config_o => acam_config,
@@ -339,6 +330,10 @@ begin
dac_word_o => dac_word_o,
one_hz_phase_o => pulse_delay);
+ irq_threshold_o <=irq_tstamp_threshold(9 downto 0);
+ irq_timeout_o <= irq_time_threshold(9 downto 0);
+
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
@@ -502,27 +497,19 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
port map
(clk_i => clk_tdc_i,
rst_i => rst_tdc_i,
- tstamp_wr_wb_ack_i => circ_buff_class_ack,
- tstamp_wr_wb_adr_o => circ_buff_class_adr,
- tstamp_wr_wb_cyc_o => circ_buff_class_cyc,
- tstamp_wr_dat_o => circ_buff_class_data_wr,
- tstamp_wr_wb_stb_o => circ_buff_class_stb,
- tstamp_wr_wb_we_o => circ_buff_class_we,
acam_tstamp1_i => acam_tstamp1,
acam_tstamp1_ok_p_i => acam_tstamp1_ok_p,
acam_tstamp2_i => acam_tstamp2,
acam_tstamp2_ok_p_i => acam_tstamp2_ok_p,
- dacapo_c_rst_p_i => clear_dacapo_counter,
- deactivate_chan_i => deactivate_chan,
roll_over_incr_recent_i => roll_over_incr_recent,
clk_i_cycles_offset_i => clk_i_cycles_offset,
roll_over_nb_i => roll_over_nb,
retrig_nb_offset_i => retrig_nb_offset,
utc_p_i => utc_p,
utc_i => utc,
- tstamp_wr_p_o => tstamp_wr_p,
- acam_channel_o => acam_tstamp_channel,
- wr_index_o => wr_index);
+ timestamp_o => timestamp,
+ timestamp_valid_o => timestamp_valid
+ );
---------------------------------------------------------------------------------------------------
@@ -531,55 +518,8 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
utc <= wrabbit_tai_i when wrabbit_synched_i = '1' else local_utc;
utc_p <= wrabbit_tai_p_i when wrabbit_synched_i = '1' else local_utc_p;
- direct_timestamp_stb_o <= circ_buff_class_cyc and circ_buff_class_stb and circ_buff_class_ack;
- direct_timestamp_o <= circ_buff_class_data_wr;
-
----------------------------------------------------------------------------------------------------
--- INTERRUPTS GENERATOR --
----------------------------------------------------------------------------------------------------
- interrupts_generator: irq_generator
- generic map
- (g_width => 32)
- port map
- (clk_i => clk_tdc_i,
- rst_i => rst_tdc_i,
- irq_tstamp_threshold_i => irq_tstamp_threshold,
- irq_time_threshold_i => irq_time_threshold,
- acam_errflag_r_edge_p_i => acam_errflag_r_edge_p,
- activate_acq_p_i => activate_acq_p,
- deactivate_acq_p_i => deactivate_acq_p,
- tstamp_wr_p_i => tstamp_wr_p,
- irq_tstamp_p_o => irq_tstamp_p_o,
- irq_time_p_o => irq_time_p_o,
- irq_acam_err_p_o => irq_acam_err_p_o);
-
-
----------------------------------------------------------------------------------------------------
--- CIRCULAR BUFFER --
----------------------------------------------------------------------------------------------------
- circular_buffer_block: circular_buffer
- port map
- (clk_tdc_i => clk_tdc_i,
- clk_sys_i => clk_sys_i,
- rst_n_sys_i => rst_n_sys_i,
- tstamp_wr_rst_i => rst_tdc_i,
- tstamp_wr_adr_i => circ_buff_class_adr,
- tstamp_wr_cyc_i => circ_buff_class_cyc,
- tstamp_wr_dat_i => circ_buff_class_data_wr,
- tstamp_wr_stb_i => circ_buff_class_stb,
- tstamp_wr_we_i => circ_buff_class_we,
- tstamp_wr_ack_p_o => circ_buff_class_ack,
- tstamp_wr_dat_o => circ_buff_class_data_rd,
- tdc_mem_wb_rst_i => rst_sys,
- tdc_mem_wb_adr_i => mem_slave_i.adr,
- tdc_mem_wb_cyc_i => mem_slave_i.cyc,
- tdc_mem_wb_dat_i => mem_slave_i.dat,
- tdc_mem_wb_stb_i => mem_slave_i.stb,
- tdc_mem_wb_we_i => mem_slave_i.we,
- tdc_mem_wb_ack_o => mem_slave_o.ack,
- tdc_mem_wb_dat_o => mem_slave_o.dat,
- tdc_mem_wb_stall_o => mem_slave_o.stall);
-
+ timestamp_stb_o <= timestamp_valid;
+ timestamp_o <= timestamp;
---------------------------------------------------------------------------------------------------
-- TDC LEDs --
@@ -594,7 +534,7 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
utc_p_i => local_utc_p,
acam_inputs_en_i => acam_inputs_en,
acam_channel_i => acam_channel,
- tstamp_wr_p_i => tstamp_wr_p,
+ tstamp_wr_p_i => timestamp_valid,
tdc_led_status_o => tdc_led_status_o,
tdc_led_trig1_o => tdc_led_trig1_o,
tdc_led_trig2_o => tdc_led_trig2_o,
@@ -608,6 +548,8 @@ clk_period <= f_pick(g_simulation, c_SIM_CLK_PERIOD, c_SYN_CLK_PERIOD);
-- ACAM start_dis, not used --
---------------------------------------------------------------------------------------------------
start_dis_o <= '0';
+
+ channel_enable_o <= acam_inputs_en(4 downto 0);
end rtl;
----------------------------------------------------------------------------------------------------
diff --git a/hdl/rtl/fmc_tdc_mezzanine.vhd b/hdl/rtl/fmc_tdc_mezzanine.vhd
index 0088391b2eb61a55ec8a993116cb64f2a5bc70ab..0fb8fb1dbc09c243222b11731701512e473836fa 100644
--- a/hdl/rtl/fmc_tdc_mezzanine.vhd
+++ b/hdl/rtl/fmc_tdc_mezzanine.vhd
@@ -115,81 +115,81 @@ entity fmc_tdc_mezzanine is
(
-- System clock & reset (Wishbone)
- clk_sys_i : in std_logic; -- 62.5 MHz clock
- rst_sys_n_i : in std_logic; -- reset for 62.5 MHz logic
-
- -- TDC 125 MHz reference & Reset (FMC)
- clk_tdc_i : in std_logic; -- 125 MHz clock
- rst_tdc_i : in std_logic; -- reset for 125 MHz logic
-
- acam_refclk_r_edge_p_i : in std_logic;
- send_dac_word_p_o : out std_logic;
- dac_word_o : out std_logic_vector(23 downto 0);
- -- Interface with ACAM
- start_from_fpga_o : out std_logic;
- err_flag_i : in std_logic;
- int_flag_i : in std_logic;
- start_dis_o : out std_logic;
- stop_dis_o : out std_logic;
- data_bus_io : inout std_logic_vector(27 downto 0);
- address_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic;
- oe_n_o : out std_logic;
- rd_n_o : out std_logic;
- wr_n_o : out std_logic;
- ef1_i : in std_logic;
- ef2_i : in std_logic;
- -- Channels termination
- enable_inputs_o : out std_logic;
- term_en_1_o : out std_logic;
- term_en_2_o : out std_logic;
- term_en_3_o : out std_logic;
- term_en_4_o : out std_logic;
- term_en_5_o : out std_logic;
- -- TDC board LEDs
- tdc_led_status_o : out std_logic;
- tdc_led_trig1_o : out std_logic;
- tdc_led_trig2_o : out std_logic;
- tdc_led_trig3_o : out std_logic;
- tdc_led_trig4_o : out std_logic;
- tdc_led_trig5_o : out std_logic;
- -- Input pulses arriving also to the FPGA, currently not treated
- tdc_in_fpga_1_i : in std_logic;
- tdc_in_fpga_2_i : in std_logic;
- tdc_in_fpga_3_i : in std_logic;
- tdc_in_fpga_4_i : in std_logic;
- tdc_in_fpga_5_i : in std_logic;
- -- White Rabbit core
- wrabbit_link_up_i : in std_logic;
- wrabbit_time_valid_i : in std_logic;
- wrabbit_cycles_i : in std_logic_vector(27 downto 0);
- wrabbit_utc_i : in std_logic_vector(31 downto 0);
- wrabbit_clk_aux_lock_en_o : out std_logic;
- wrabbit_clk_aux_locked_i : in std_logic;
- wrabbit_clk_dmtd_locked_i : in std_logic;
- wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
- wrabbit_dac_wr_p_i : in std_logic;
-
- -- WISHBONE interface with the GN4124/VME_core (clk_sys)
- -- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
-
- slave_i: in t_wishbone_slave_in;
- slave_o: out t_wishbone_slave_out;
-
- wb_irq_o : out std_logic;
-
- -- I2C EEPROM interface
- i2c_scl_o : out std_logic;
- i2c_scl_oen_o : out std_logic;
- i2c_scl_i : in std_logic;
- i2c_sda_oen_o : out std_logic;
- i2c_sda_o : out std_logic;
- i2c_sda_i : in std_logic;
- -- 1-Wire interface
- onewire_b : inout std_logic;
- direct_timestamp_o : out std_logic_vector(127 downto 0);
- direct_timestamp_stb_o : out std_logic
-);
+ clk_sys_i : in std_logic; -- 62.5 MHz clock
+ rst_sys_n_i : in std_logic; -- reset for 62.5 MHz logic
+
+ -- TDC 125 MHz reference & Reset (FMC)
+ clk_tdc_i : in std_logic; -- 125 MHz clock
+ rst_tdc_i : in std_logic; -- reset for 125 MHz logic
+
+ acam_refclk_r_edge_p_i : in std_logic;
+ send_dac_word_p_o : out std_logic;
+ dac_word_o : out std_logic_vector(23 downto 0);
+ -- Interface with ACAM
+ start_from_fpga_o : out std_logic;
+ err_flag_i : in std_logic;
+ int_flag_i : in std_logic;
+ start_dis_o : out std_logic;
+ stop_dis_o : out std_logic;
+ data_bus_io : inout std_logic_vector(27 downto 0);
+ address_o : out std_logic_vector(3 downto 0);
+ cs_n_o : out std_logic;
+ oe_n_o : out std_logic;
+ rd_n_o : out std_logic;
+ wr_n_o : out std_logic;
+ ef1_i : in std_logic;
+ ef2_i : in std_logic;
+ -- Channels termination
+ enable_inputs_o : out std_logic;
+ term_en_1_o : out std_logic;
+ term_en_2_o : out std_logic;
+ term_en_3_o : out std_logic;
+ term_en_4_o : out std_logic;
+ term_en_5_o : out std_logic;
+ -- TDC board LEDs
+ tdc_led_status_o : out std_logic;
+ tdc_led_trig1_o : out std_logic;
+ tdc_led_trig2_o : out std_logic;
+ tdc_led_trig3_o : out std_logic;
+ tdc_led_trig4_o : out std_logic;
+ tdc_led_trig5_o : out std_logic;
+ -- Input pulses arriving also to the FPGA, currently not treated
+ tdc_in_fpga_1_i : in std_logic;
+ tdc_in_fpga_2_i : in std_logic;
+ tdc_in_fpga_3_i : in std_logic;
+ tdc_in_fpga_4_i : in std_logic;
+ tdc_in_fpga_5_i : in std_logic;
+ -- White Rabbit core
+ wrabbit_link_up_i : in std_logic;
+ wrabbit_time_valid_i : in std_logic;
+ wrabbit_cycles_i : in std_logic_vector(27 downto 0);
+ wrabbit_utc_i : in std_logic_vector(31 downto 0);
+ wrabbit_clk_aux_lock_en_o : out std_logic;
+ wrabbit_clk_aux_locked_i : in std_logic;
+ wrabbit_clk_dmtd_locked_i : in std_logic;
+ wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
+ wrabbit_dac_wr_p_i : in std_logic;
+
+ -- WISHBONE interface with the GN4124/VME_core (clk_sys)
+ -- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
+
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+
+ wb_irq_o : out std_logic;
+
+ -- I2C EEPROM interface
+ i2c_scl_o : out std_logic;
+ i2c_scl_oen_o : out std_logic;
+ i2c_scl_i : in std_logic;
+ i2c_sda_oen_o : out std_logic;
+ i2c_sda_o : out std_logic;
+ i2c_sda_i : in std_logic;
+ -- 1-Wire interface
+ onewire_b : inout std_logic;
+ direct_timestamp_o : out std_logic_vector(127 downto 0);
+ direct_timestamp_stb_o : out std_logic
+ );
end fmc_tdc_mezzanine;
@@ -198,45 +198,69 @@ end fmc_tdc_mezzanine;
--=================================================================================================
architecture rtl of fmc_tdc_mezzanine is
+ component timestamp_fifo is
+ generic (
+ g_channel : integer);
+ port (
+ clk_sys_i : in std_logic;
+ clk_tdc_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ rst_tdc_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ irq_o : out std_logic;
+ enable_i : in std_logic;
+ tick_i : in std_logic;
+ irq_threshold_i : in std_logic_vector(9 downto 0);
+ irq_timeout_i : in std_logic_vector(9 downto 0);
+ timestamp_i : in std_logic_vector(127 downto 0);
+ timestamp_valid_i : in std_logic);
+ end component timestamp_fifo;
+
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
- constant c_NUM_WB_MASTERS : integer := 5;
+ constant c_NUM_WB_MASTERS : integer := 9;
constant c_WB_SLAVE_TDC_ONEWIRE : integer := 0; -- TDC mezzanine board UnidueID&Thermometer 1-wire
constant c_WB_SLAVE_TDC_CORE_CONFIG : integer := 1; -- TDC core configuration registers
constant c_WB_SLAVE_TDC_EIC : integer := 2; -- TDC interrupts
constant c_WB_SLAVE_TDC_I2C : integer := 3; -- TDC mezzanine board system EEPROM I2C
- constant c_WB_SLAVE_TSTAMP_MEM : integer := 4; -- Access to TDC core memory for timestamps retrieval
+ constant c_WB_SLAVE_TDC_FIFO0 : integer := 4; -- Access to TDC core FIFO for timestamps retrieval
-- Slave port on the wishbone crossbar
- constant c_NUM_WB_SLAVES : integer := 1;
+ constant c_NUM_WB_SLAVES : integer := 1;
-- Wishbone master(s)
- constant c_WB_MASTER : integer := 0;
+ constant c_WB_MASTER : integer := 0;
-- sdb header address
- constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
+ constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- WISHBONE crossbar layout
- constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
+ constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
(0 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_TDC_CONFIG_SDB_DEVICE, x"00002000"),
2 => f_sdb_embed_device(c_TDC_EIC_DEVICE, x"00003000"),
3 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00004000"),
- 4 => f_sdb_embed_device(c_TDC_MEM_SDB_DEVICE, x"00005000"));
+ 4 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005000"),
+ 5 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005100"),
+ 6 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005200"),
+ 7 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005300"),
+ 8 => f_sdb_embed_device(c_TDC_FIFO_SDB_DEVICE, x"00005400")
+ );
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- resets
- signal general_rst_n, rst_ref_0_n: std_logic;
+ signal general_rst_n, rst_ref_0_n : std_logic;
-- Wishbone buse(s) from crossbar master port(s)
- signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
- signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
+ signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+ signal cnx_master_in : t_wishbone_master_in_array (c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE addresses
signal tdc_core_wb_adr : std_logic_vector(31 downto 0);
@@ -248,31 +272,33 @@ architecture rtl of fmc_tdc_mezzanine is
signal sys_scl_oe_n, sys_sda_in : std_logic;
signal sys_sda_out, sys_sda_oe_n : std_logic;
-- IRQ
- signal irq_tstamp_p, irq_time_p : std_logic;
- signal irq_acam_err_p : std_logic;
- signal irq_tstamp_p_sys, irq_time_p_sys : std_logic;
- signal irq_acam_err_p_sys : std_logic;
- -- WRabbit
- signal reg_to_wr, reg_from_wr : std_logic_vector(31 downto 0);
- signal wrabbit_utc_p : std_logic;
- signal wrabbit_synched : std_logic;
+ signal irq_tstamp : std_logic;
+ signal reg_to_wr, reg_from_wr : std_logic_vector(31 downto 0);
+ signal wrabbit_utc_p : std_logic;
+ signal wrabbit_synched : std_logic;
- signal irq_tstamp_sreg : std_logic_vector(7 downto 0);
+ signal irq_channel : std_logic_vector(4 downto 0);
+ signal timestamp : std_logic_vector(127 downto 0);
+ signal timestamp_stb : std_logic;
+ signal channel_enable : std_logic_vector(4 downto 0);
+ signal irq_threshold, irq_timeout : std_logic_vector(9 downto 0);
+ signal tick_1ms : std_logic;
+ signal counter_1ms : unsigned(17 downto 0);
+
+ function f_wb_shift_address_word (w : t_wishbone_master_out) return t_wishbone_master_out is
+ variable r : t_wishbone_master_out;
+ begin
+ r.adr := "00" & w.adr(31 downto 2);
+ r.dat := w.dat;
+ r.cyc := w.cyc;
+ r.stb := w.stb;
+ r.we := w.we;
+ r.sel := w.sel;
+ return r;
+ end f_wb_shift_address_word;
-function f_wb_shift_address_word ( w: t_wishbone_master_out ) return t_wishbone_master_out is
- variable r : t_wishbone_master_out;
-begin
- r.adr := "00" & w.adr(31 downto 2);
- r.dat := w.dat;
- r.cyc := w.cyc;
- r.stb := w.stb;
- r.we := w.we;
- r.sel := w.sel;
- return r;
-end f_wb_shift_address_word;
-
--=================================================================================================
-- architecture begin
--=================================================================================================
@@ -280,141 +306,145 @@ begin
rst_ref_0_n <= not(rst_tdc_i);
----------------------------------------------------------------------------------------------------
--- CSR WISHBONE CROSSBAR --
----------------------------------------------------------------------------------------------------
--- CSR wishbone address decoder
--- 0x0000 -> SDB descriptor
--- 0x1000 -> TDC mezzanine board 1-Wire
--- 0x2000 -> TDC core registers
--- 0x3000 -> TDC core interrupt controller (EIC)
--- 0x4000 -> TDC mezzanine board I2C eeprom
--- 0x5000 -> TDC core circular buffer
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sdb_crossbar : xwb_sdb_crossbar
generic map
- (g_num_masters => c_NUM_WB_SLAVES,
- g_num_slaves => c_NUM_WB_MASTERS,
- g_registered => true,
- g_wraparound => true,
- g_layout => c_INTERCONNECT_LAYOUT,
- g_sdb_addr => c_SDB_ADDRESS)
+ (g_num_masters => c_NUM_WB_SLAVES,
+ g_num_slaves => c_NUM_WB_MASTERS,
+ g_registered => true,
+ g_wraparound => true,
+ g_layout => c_INTERCONNECT_LAYOUT,
+ g_sdb_addr => c_SDB_ADDRESS)
port map
- (clk_sys_i => clk_sys_i,
- rst_n_i => rst_sys_n_i,
- slave_i(0) => slave_i,
- slave_o(0) => slave_o,
- master_i => cnx_master_in,
- master_o => cnx_master_out);
-
-
+ (clk_sys_i => clk_sys_i,
+ rst_n_i => rst_sys_n_i,
+ slave_i(0) => slave_i,
+ slave_o(0) => slave_o,
+ master_i => cnx_master_in,
+ master_o => cnx_master_out);
+
+
---------------------------------------------------------------------------------------------------
-- TDC CORE --
---------------------------------------------------------------------------------------------------
- cmp_tdc_core: fmc_tdc_core
- generic map
- (g_span => g_span,
- g_width => g_width,
- g_simulation => g_simulation)
- port map
- (-- clks, rst
- clk_tdc_i => clk_tdc_i,
- rst_tdc_i => rst_tdc_i,
- clk_sys_i => clk_sys_i,
- rst_n_sys_i => rst_sys_n_i,
- acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
- -- DAC configuration
- send_dac_word_p_o => send_dac_word_p_o,
- dac_word_o => dac_word_o,
- -- ACAM
- start_from_fpga_o => start_from_fpga_o,
- err_flag_i => err_flag_i,
- int_flag_i => int_flag_i,
- start_dis_o => start_dis_o,
- stop_dis_o => stop_dis_o,
- data_bus_io => data_bus_io,
- address_o => address_o,
- cs_n_o => cs_n_o,
- oe_n_o => oe_n_o,
- rd_n_o => rd_n_o,
- wr_n_o => wr_n_o,
- ef1_i => ef1_i,
- ef2_i => ef2_i,
- -- Input channels enable
- enable_inputs_o => enable_inputs_o,
- term_en_1_o => term_en_1_o,
- term_en_2_o => term_en_2_o,
- term_en_3_o => term_en_3_o,
- term_en_4_o => term_en_4_o,
- term_en_5_o => term_en_5_o,
- -- Input channels to FPGA (not used currently)
- tdc_in_fpga_1_i => tdc_in_fpga_1_i,
- tdc_in_fpga_2_i => tdc_in_fpga_2_i,
- tdc_in_fpga_3_i => tdc_in_fpga_3_i,
- tdc_in_fpga_4_i => tdc_in_fpga_4_i,
- tdc_in_fpga_5_i => tdc_in_fpga_5_i,
- -- TDC board LEDs
- tdc_led_status_o => tdc_led_status_o,
- tdc_led_trig1_o => tdc_led_trig1_o,
- tdc_led_trig2_o => tdc_led_trig2_o,
- tdc_led_trig3_o => tdc_led_trig3_o,
- tdc_led_trig4_o => tdc_led_trig4_o,
- tdc_led_trig5_o => tdc_led_trig5_o,
- -- Interrupts
- irq_tstamp_p_o => irq_tstamp_p,
- irq_time_p_o => irq_time_p,
- irq_acam_err_p_o => irq_acam_err_p,
- -- WR stuff
- wrabbit_tai_i => wrabbit_utc_i,
- wrabbit_tai_p_i => wrabbit_utc_p,
- wrabbit_synched_i => wrabbit_synched,
- wrabbit_status_reg_i => reg_from_wr,
- wrabbit_ctrl_reg_o => reg_to_wr,
- -- WISHBONE CSR for core configuration
-
- cfg_slave_i => f_wb_shift_address_word(cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG)),
- cfg_slave_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG),
-
- mem_slave_i => f_wb_shift_address_word(cnx_master_out(c_WB_SLAVE_TSTAMP_MEM)),
- mem_slave_o => cnx_master_in(c_WB_SLAVE_TSTAMP_MEM),
-
- direct_timestamp_o => direct_timestamp_o,
- direct_timestamp_stb_o => direct_timestamp_stb_o);
-
-
- p_extend_irq : process(clk_tdc_i)
+ cmp_tdc_core : fmc_tdc_core
+ generic map
+ (g_span => g_span,
+ g_width => g_width,
+ g_simulation => g_simulation)
+ port map
+ ( -- clks, rst
+ clk_tdc_i => clk_tdc_i,
+ rst_tdc_i => rst_tdc_i,
+ clk_sys_i => clk_sys_i,
+ rst_n_sys_i => rst_sys_n_i,
+ acam_refclk_r_edge_p_i => acam_refclk_r_edge_p_i,
+ -- DAC configuration
+ send_dac_word_p_o => send_dac_word_p_o,
+ dac_word_o => dac_word_o,
+ -- ACAM
+ start_from_fpga_o => start_from_fpga_o,
+ err_flag_i => err_flag_i,
+ int_flag_i => int_flag_i,
+ start_dis_o => start_dis_o,
+ stop_dis_o => stop_dis_o,
+ data_bus_io => data_bus_io,
+ address_o => address_o,
+ cs_n_o => cs_n_o,
+ oe_n_o => oe_n_o,
+ rd_n_o => rd_n_o,
+ wr_n_o => wr_n_o,
+ ef1_i => ef1_i,
+ ef2_i => ef2_i,
+ -- Input channels enable
+ enable_inputs_o => enable_inputs_o,
+ term_en_1_o => term_en_1_o,
+ term_en_2_o => term_en_2_o,
+ term_en_3_o => term_en_3_o,
+ term_en_4_o => term_en_4_o,
+ term_en_5_o => term_en_5_o,
+ -- Input channels to FPGA (not used currently)
+ tdc_in_fpga_1_i => tdc_in_fpga_1_i,
+ tdc_in_fpga_2_i => tdc_in_fpga_2_i,
+ tdc_in_fpga_3_i => tdc_in_fpga_3_i,
+ tdc_in_fpga_4_i => tdc_in_fpga_4_i,
+ tdc_in_fpga_5_i => tdc_in_fpga_5_i,
+ -- TDC board LEDs
+ tdc_led_status_o => tdc_led_status_o,
+ tdc_led_trig1_o => tdc_led_trig1_o,
+ tdc_led_trig2_o => tdc_led_trig2_o,
+ tdc_led_trig3_o => tdc_led_trig3_o,
+ tdc_led_trig4_o => tdc_led_trig4_o,
+ tdc_led_trig5_o => tdc_led_trig5_o,
+
+ -- WR stuff
+ wrabbit_tai_i => wrabbit_utc_i,
+ wrabbit_tai_p_i => wrabbit_utc_p,
+ wrabbit_synched_i => wrabbit_synched,
+ wrabbit_status_reg_i => reg_from_wr,
+ wrabbit_ctrl_reg_o => reg_to_wr,
+ -- WISHBONE CSR for core configuration
+
+ cfg_slave_i => f_wb_shift_address_word(cnx_master_out(c_WB_SLAVE_TDC_CORE_CONFIG)),
+ cfg_slave_o => cnx_master_in(c_WB_SLAVE_TDC_CORE_CONFIG),
+
+ timestamp_o => timestamp,
+ timestamp_stb_o => timestamp_stb,
+
+ irq_threshold_o => irq_threshold,
+ irq_timeout_o => irq_timeout,
+ channel_enable_o => channel_enable
+ );
+
+ gen_fifos : for i in 0 to 4 generate
+ U_TheFifo : timestamp_fifo
+ generic map (
+ g_channel => i)
+ port map (
+ clk_sys_i => clk_sys_i,
+ clk_tdc_i => clk_tdc_i,
+ rst_n_sys_i => rst_sys_n_i,
+ rst_tdc_i => rst_tdc_i,
+ slave_i => cnx_master_out(c_WB_SLAVE_TDC_FIFO0 + i),
+ slave_o => cnx_master_in(c_WB_SLAVE_TDC_FIFO0 + i),
+ irq_o => irq_channel(i),
+ enable_i => channel_enable(i),
+ tick_i => tick_1ms,
+ irq_threshold_i => irq_threshold,
+ irq_timeout_i => irq_timeout,
+ timestamp_i => timestamp,
+ timestamp_valid_i => timestamp_stb);
+
+ end generate gen_fifos;
+
+ irq_tstamp <= '1' when unsigned(irq_channel) /= 0 else '0';
+
+
+ p_gen_1ms_tick : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_tdc_i = '1' then
- irq_tstamp_sreg <= (others => '0');
+ tick_1ms <= '0';
+ counter_1ms <= (others => '0');
else
- if(irq_tstamp_p = '1')then
- irq_tstamp_sreg <= (others => '1');
+ if counter_1ms = (125000000 / 1000) then
+ tick_1ms <= '1';
+ counter_1ms <= (others => '0');
else
- irq_tstamp_sreg <= '0' & irq_tstamp_sreg(7 downto 1);
+ tick_1ms <= '0';
+ counter_1ms <= counter_1ms + 1;
end if;
end if;
end if;
end process;
-
- u_sync_irq_line : gc_sync_ffs
- port map (
- clk_i => clk_sys_i,
- rst_n_i => rst_sys_n_i,
- data_i => irq_tstamp_sreg(0),
- ppulse_o => irq_tstamp_p_sys);
-
-
---------------------------------------------------------------------------------------------------
-- WHITE RABBIT STUFF --
-- only synthesized if g_with_wrabbit_core is TRUE --
---------------------------------------------------------------------------------------------------
- cmp_wrabbit_synch: wrabbit_sync
- generic map
- (g_simulation => g_simulation,
- g_with_wrabbit_core => g_with_wrabbit_core)
- port map
+ cmp_wrabbit_synch : wrabbit_sync
+ generic map
+ (g_simulation => g_simulation,
+ g_with_wrabbit_core => g_with_wrabbit_core)
+ port map
(clk_sys_i => clk_sys_i,
rst_n_sys_i => rst_sys_n_i,
clk_ref_i => clk_tdc_i,
@@ -425,27 +455,27 @@ begin
wrabbit_time_valid_i => wrabbit_time_valid_i,
wrabbit_clk_aux_lock_en_o => wrabbit_clk_aux_lock_en_o,
wrabbit_clk_aux_locked_i => wrabbit_clk_aux_locked_i,
- wrabbit_clk_dmtd_locked_i => '1', -- FIXME
+ wrabbit_clk_dmtd_locked_i => '1', -- FIXME
wrabbit_synched_o => wrabbit_synched,
- wrabbit_reg_i => reg_to_wr, -- synced to 125MHz mezzanine
- wrabbit_reg_o => reg_from_wr); -- synced to 125MHz mezzanine
+ wrabbit_reg_i => reg_to_wr, -- synced to 125MHz mezzanine
+ wrabbit_reg_o => reg_from_wr); -- synced to 125MHz mezzanine
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
wrabbit_one_hz_pulse : process(clk_tdc_i)
begin
if rising_edge(clk_tdc_i) then
if rst_ref_0_n = '0' then
- wrabbit_utc_p <= '0';
+ wrabbit_utc_p <= '0';
else
if wrabbit_clk_aux_locked_i = '1' and g_with_wrabbit_core then
- if unsigned(wrabbit_cycles_i) = (unsigned(c_SYN_CLK_PERIOD)-3) then -- so that the end of the pulse
- -- comes exactly upon the UTC change
+ if unsigned(wrabbit_cycles_i) = (unsigned(c_SYN_CLK_PERIOD)-3) then -- so that the end of the pulse
+ -- comes exactly upon the UTC change
wrabbit_utc_p <= '1';
else
wrabbit_utc_p <= '0';
end if;
else
- wrabbit_utc_p <= '0';
+ wrabbit_utc_p <= '0';
end if;
end if;
end if;
@@ -456,24 +486,24 @@ begin
-- TDC Mezzanine Board UniqueID&Thermometer OneWire --
---------------------------------------------------------------------------------------------------
cmp_fmc_onewire : xwb_onewire_master
- generic map
+ generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0")
- port map
- (clk_sys_i => clk_sys_i,
- rst_n_i => rst_sys_n_i,
- slave_i => cnx_master_out(c_WB_SLAVE_TDC_ONEWIRE),
- slave_o => cnx_master_in(c_WB_SLAVE_TDC_ONEWIRE),
- desc_o => open,
- owr_pwren_o => open,
- owr_en_o => mezz_owr_en,
- owr_i => mezz_owr_i);
+ port map
+ (clk_sys_i => clk_sys_i,
+ rst_n_i => rst_sys_n_i,
+ slave_i => cnx_master_out(c_WB_SLAVE_TDC_ONEWIRE),
+ slave_o => cnx_master_in(c_WB_SLAVE_TDC_ONEWIRE),
+ desc_o => open,
+ owr_pwren_o => open,
+ owr_en_o => mezz_owr_en,
+ owr_i => mezz_owr_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- onewire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
- mezz_owr_i(0) <= onewire_b;
+ onewire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
+ mezz_owr_i(0) <= onewire_b;
---------------------------------------------------------------------------------------------------
@@ -484,7 +514,7 @@ begin
-- 1 -> number of seconds passed reached threshold and number of accumulated tstamps > 0
-- 2 -> ACAM error
cmp_tdc_eic : tdc_eic
- port map
+ port map
(clk_sys_i => clk_sys_i,
rst_n_i => rst_sys_n_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TDC_EIC).adr(3 downto 2),
@@ -497,13 +527,10 @@ begin
wb_ack_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_TDC_EIC).stall,
wb_int_o => wb_irq_o,
- irq_tdc_tstamps_i => irq_tstamp_p_sys,
- irq_tdc_time_i => irq_time_p_sys,
- irq_tdc_acam_err_i => irq_acam_err_p_sys);
+ irq_tdc_tstamps_i => irq_tstamp,
+ irq_tdc_time_i => '0',
+ irq_tdc_acam_err_i => '0');
- irq_time_p_sys <= '0'; -- we don't need these in the driver
- irq_acam_err_p_sys <= '0';
-
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TDC_EIC).err <= '0';
@@ -514,28 +541,28 @@ begin
---------------------------------------------------------------------------------------------------
-- TDC Mezzanine Board EEPROM I2C --
---------------------------------------------------------------------------------------------------
- cmp_I2C_master : xwb_i2c_master
- generic map
- (g_interface_mode => PIPELINED,
- g_address_granularity => BYTE)
- port map
- (clk_sys_i => clk_sys_i,
- rst_n_i => rst_sys_n_i,
- slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
- slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
- desc_o => open,
- scl_pad_i(0) => i2c_scl_i,
- scl_pad_o(0) => sys_scl_out,
+ cmp_I2C_master : xwb_i2c_master
+ generic map
+ (g_interface_mode => PIPELINED,
+ g_address_granularity => BYTE)
+ port map
+ (clk_sys_i => clk_sys_i,
+ rst_n_i => rst_sys_n_i,
+ slave_i => cnx_master_out(c_WB_SLAVE_TDC_I2C),
+ slave_o => cnx_master_in(c_WB_SLAVE_TDC_I2C),
+ desc_o => open,
+ scl_pad_i(0) => i2c_scl_i,
+ scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => i2c_sda_i,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- i2c_sda_oen_o <= sys_sda_oe_n;
- i2c_sda_o <= sys_sda_out;
- i2c_scl_oen_o <= sys_scl_oe_n;
- i2c_scl_o <= sys_scl_out;
+ i2c_sda_oen_o <= sys_sda_oe_n;
+ i2c_sda_o <= sys_sda_out;
+ i2c_scl_oen_o <= sys_scl_oe_n;
+ i2c_scl_o <= sys_scl_out;
end rtl;
diff --git a/hdl/rtl/irq_generator.vhd b/hdl/rtl/irq_generator.vhd
deleted file mode 100644
index e2c546c7621e670ac293017524243472c499e616..0000000000000000000000000000000000000000
--- a/hdl/rtl/irq_generator.vhd
+++ /dev/null
@@ -1,299 +0,0 @@
---_________________________________________________________________________________________________
--- |
--- |TDC core| |
--- |
--- CERN,BE/CO-HT |
---________________________________________________________________________________________________|
-
----------------------------------------------------------------------------------------------------
--- |
--- irq_generator |
--- |
----------------------------------------------------------------------------------------------------
--- File irq_generator.vhd |
--- |
--- Description Interrupts generator: the unit generates three interrupts: |
--- |
--- o irq_tstamp_p_o is a 1-clk_i-long pulse generated when the amount of |
--- timestamps written in the circular_buffer, since the last interrupt or since |
--- the startup of the acquisition, exceeds the GN4124/VME settable threshold |
--- irq_tstamp_threshold. |
--- |
--- o irq_time_p_o is a 1-clk_i-long pulse generated when some timestamps have been |
--- written in the circular_buffer (>=1 timestamp) and the amount of time passed |
--- since the last interrupt or since the acquisition startup, exceeds the |
--- GN4124/VME settable threshold irq_time_threshold. The threshold is in ms. |
--- |
--- o irq_acam_err_p_o is a 1-clk_i-long pulse generated when the ACAM Hit FIFOS are|
--- full (according to ACAM configuration register 11) |
--- |
--- |
--- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
--- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
--- Date 08/2013 |
--- Version v1 |
--- Depends on |
--- |
----------------- |
--- Last changes |
--- 05/2012 v0.1 EG First version |
--- 04/2013 v0.2 EG line 170 added "irq_time_threshold_i > 0"; if the user doesn t want the |
--- time interrupts he sets the irq_time_threshold reg to zero; same goes |
--- for number-of-tstamps interrupts, users sets to zero to disable them |
--- 08/2013 v1 EG time irq concept in milliseconds rather than seconds |
--- |
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- GNU LESSER GENERAL PUBLIC LICENSE |
--- ------------------------------------ |
--- This source file is free software; you can redistribute it and/or modify it under the terms of |
--- the GNU Lesser General Public License as published by the Free Software Foundation; either |
--- version 2.1 of the License, or (at your option) any later version. |
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
--- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
--- See the GNU Lesser General Public License for more details. |
--- You should have received a copy of the GNU Lesser General Public License along with this |
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
----------------------------------------------------------------------------------------------------
-
-
---=================================================================================================
--- Libraries & Packages
---=================================================================================================
-
--- Standard library
-library IEEE;
-use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
-use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
--- Specific library
-library work;
-use work.tdc_core_pkg.all; -- definitions of types, constants, entities
-
-
---=================================================================================================
--- Entity declaration for irq_generator
---=================================================================================================
-entity irq_generator is
- generic
- (g_width : integer := 32);
- port
- -- INPUTS
- -- Signal from the clks_rsts_manager
- (clk_i : in std_logic; -- 125 MHz clk
- rst_i : in std_logic; -- global reset
-
- irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
- irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0); -- GN4124/VME settable threshold
-
- -- Signal from the acam_timecontrol_interface
- acam_errflag_r_edge_p_i : in std_logic; -- ACAM ErrFlag rising edge; through the ACAM config reg 11
- -- the ERRflag is configured to follow the full flags of the
- -- Hit FIFOs; this would translate to data loss
- -- Signal from the reg_ctrl unit
- activate_acq_p_i : in std_logic; -- activates tstamps acquisition from ACAM
- deactivate_acq_p_i : in std_logic; -- deactivates tstamps acquisition
-
- -- Signals from the data_formatting unit
- tstamp_wr_p_i : in std_logic; -- pulse upon storage of a new timestamp
-
-
- -- OUTPUTS
- -- Signals to the wb_irq_controller
- irq_tstamp_p_o : out std_logic; -- active if amount of tstamps > tstamps_threshold
- irq_time_p_o : out std_logic; -- active if amount of tstamps < tstamps_threshold but time > time_threshold
- irq_acam_err_p_o : out std_logic); -- active if ACAM err_flag_i is active
-
-end irq_generator;
-
---=================================================================================================
--- architecture declaration
---=================================================================================================
-architecture rtl of irq_generator is
-
- constant ZERO : std_logic_vector (8 downto 0):= "000000000";
- type t_irq_st is (IDLE, TSTAMP_AND_TIME_COUNTING, RAISE_IRQ_TSTAMP, RAISE_IRQ_TIME);
- signal irq_st, nxt_irq_st : t_irq_st;
- signal tstamps_c_rst, time_c_rst : std_logic;
- signal tstamps_c_en, time_c_en : std_logic;
- signal tstamps_c_incr_en, time_c_incr_en : std_logic;
- signal tstamps_c : std_logic_vector(8 downto 0);
- signal time_c : std_logic_vector(g_width-1 downto 0);
- signal one_ms_passed_p : std_logic;
-
-
---=================================================================================================
--- architecture begin
---=================================================================================================
-begin
-
-
--- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-
----------------------------------------------------------------------------------------------------
--- INTERRUPTS GENERATOR FSM --
----------------------------------------------------------------------------------------------------
-
- IRQ_generator_seq: process (clk_i)
- begin
- if rising_edge (clk_i) then
- if rst_i ='1' then
- irq_st <= IDLE;
- else
- irq_st <= nxt_irq_st;
- end if;
- end if;
- end process;
-
----------------------------------------------------------------------------------------------------
- IRQ_generator_comb: process (irq_st, activate_acq_p_i, deactivate_acq_p_i, tstamps_c,
- irq_tstamp_threshold_i, irq_time_threshold_i, time_c)
- begin
- case irq_st is
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when IDLE =>
- -----------------------------------------------
- irq_tstamp_p_o <= '0';
- irq_time_p_o <= '0';
- tstamps_c_rst <= '1';
- time_c_rst <= '1';
- tstamps_c_en <= '0';
- time_c_en <= '0';
- -----------------------------------------------
- if activate_acq_p_i = '1' then
- nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
- else
- nxt_irq_st <= IDLE;
- end if;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when TSTAMP_AND_TIME_COUNTING =>
- -----------------------------------------------
- irq_tstamp_p_o <= '0';
- irq_time_p_o <= '0';
- tstamps_c_rst <= '0';
- time_c_rst <= '0';
- tstamps_c_en <= '1';
- time_c_en <= '1';
- -----------------------------------------------
- if deactivate_acq_p_i = '1' then
- nxt_irq_st <= IDLE;
- elsif tstamps_c > ZERO and tstamps_c >= irq_tstamp_threshold_i(8 downto 0) then -- not >= ZERO!!
- nxt_irq_st <= RAISE_IRQ_TSTAMP;
- elsif unsigned(irq_time_threshold_i) > 0 and time_c >= irq_time_threshold_i and tstamps_c > ZERO then
- nxt_irq_st <= RAISE_IRQ_TIME;
- else
- nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
- end if;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when RAISE_IRQ_TSTAMP =>
- -----------------------------------------------
- irq_tstamp_p_o <= '1';
- irq_time_p_o <= '0';
- tstamps_c_rst <= '1';
- time_c_rst <= '1';
- tstamps_c_en <= '0';
- time_c_en <= '0';
- -----------------------------------------------
- if deactivate_acq_p_i = '1' then
- nxt_irq_st <= IDLE;
- else
- nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
- end if;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when RAISE_IRQ_TIME =>
- -----------------------------------------------
- irq_tstamp_p_o <= '0';
- irq_time_p_o <= '1';
- tstamps_c_rst <= '1';
- time_c_rst <= '1';
- tstamps_c_en <= '0';
- time_c_en <= '0';
- -----------------------------------------------
- if deactivate_acq_p_i = '1' then
- nxt_irq_st <= IDLE;
- else
- nxt_irq_st <= TSTAMP_AND_TIME_COUNTING;
- end if;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- when others =>
- -----------------------------------------------
- irq_tstamp_p_o <= '0';
- irq_time_p_o <= '0';
- tstamps_c_rst <= '1';
- time_c_rst <= '1';
- tstamps_c_en <= '0';
- time_c_en <= '0';
- -----------------------------------------------
- nxt_irq_st <= IDLE;
- end case;
- end process;
-
-
----------------------------------------------------------------------------------------------------
--- TIMESTAMPS COUNTER --
----------------------------------------------------------------------------------------------------
--- Incremental counter counting the amount of timestamps written since the last interrupt or the
--- last reset. The counter counts up to 255.
- tstamps_counter: incr_counter
- generic map
- (width => 9) -- 9 digits, counting up to 255
- port map
- (clk_i => clk_i,
- rst_i => tstamps_c_rst,
- counter_top_i => "100000000",
- counter_incr_en_i => tstamps_c_incr_en,
- counter_is_full_o => open,
- -------------------------------------------
- counter_o => tstamps_c);
- -------------------------------------------
- tstamps_c_incr_en <= tstamps_c_en and tstamp_wr_p_i;
-
-
----------------------------------------------------------------------------------------------------
--- TIME COUNTER --
----------------------------------------------------------------------------------------------------
--- Incremental counter counting the time in milliseconds since the last interrupt or the last reset.
- time_counter: incr_counter
- generic map
- (width => g_width)
- port map
- (clk_i => clk_i,
- rst_i => time_c_rst,
- counter_top_i => x"FFFFFFFF",
- counter_incr_en_i => time_c_incr_en,
- counter_is_full_o => open,
- -------------------------------------------
- counter_o => time_c);
- -------------------------------------------
- time_c_incr_en <= time_c_en and one_ms_passed_p;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- millisec_counter: free_counter
- generic map
- (width => g_width)
- port map
- (clk_i => clk_i,
- rst_i => rst_i,
- counter_en_i => '1',
- counter_top_i => x"0001E848", -- 125'000 clk_i cycles = 1 ms
- -------------------------------------------
- counter_is_zero_o => one_ms_passed_p,
- counter_o => open);
- -------------------------------------------
-
-
----------------------------------------------------------------------------------------------------
--- ACAM ErrFlag IRQ --
----------------------------------------------------------------------------------------------------
- irq_acam_err_p_o <= acam_errflag_r_edge_p_i;
-
-
-end rtl;
-----------------------------------------------------------------------------------------------------
--- architecture ends
-----------------------------------------------------------------------------------------------------
\ No newline at end of file
diff --git a/hdl/rtl/reg_ctrl.vhd b/hdl/rtl/reg_ctrl.vhd
index fd375a95e70fc8470c17a05b3a0e07d2572dda75..595eb43a1a931c4ef91984c79a68af74fbee8bbc 100644
--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -84,9 +84,8 @@ entity reg_ctrl is
(g_span : integer := 32;
g_width : integer := 32);
port
- -- INPUTS
- -- Signals from the clks_rsts_manager unit
- (clk_sys_i : in std_logic;
+ (
+ clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic; -- global reset, synched to clk_sys
clk_tdc_i : in std_logic;
@@ -101,9 +100,6 @@ entity reg_ctrl is
acam_ififo2_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 9; for debug reasons only
acam_start01_i : in std_logic_vector(g_width-1 downto 0); -- keeps value read back from ACAM reg 10; for debug reasons only
- -- Signals from the data_formatting unit
- wr_index_i : in std_logic_vector(g_width-1 downto 0); -- index of the last circular_buffer adr written
-
-- Signals from the one_hz_gen unit
local_utc_i : in std_logic_vector(g_width-1 downto 0); -- local utc time
@@ -130,10 +126,6 @@ entity reg_ctrl is
acam_rdbk_ififo2_p_o : out std_logic; -- enables reading of ACAM reg 9
acam_rdbk_start01_p_o : out std_logic; -- enables reading of ACAM reg 10
- -- Signal to the data_formatting unit
- dacapo_c_rst_p_o : out std_logic; -- clears the dacapo counter
- deactivate_chan_o : out std_logic_vector(4 downto 0); -- stops registering timestamps from a specific channel
-
-- Signals to the clks_resets_manager unit
send_dac_word_p_o : out std_logic; -- initiates the reconfiguration of the DAC
dac_word_o : out std_logic_vector(23 downto 0);
@@ -171,7 +163,7 @@ architecture rtl of reg_ctrl is
signal dac_word : std_logic_vector(23 downto 0);
signal pulse_extender_en : std_logic;
signal pulse_extender_c : std_logic_vector(2 downto 0);
- signal dat_out, wrabbit_ctrl_reg, deactivate_chan : std_logic_vector(g_span-1 downto 0);
+ signal dat_out, wrabbit_ctrl_reg : std_logic_vector(g_span-1 downto 0);
signal ack_out_pipe0, ack_out_pipe1 : std_logic;
@@ -356,7 +348,6 @@ begin
start_phase <= (others =>'0');
one_hz_phase <= (others =>'0');
wrabbit_ctrl_reg <= (others =>'0');
- deactivate_chan <= (others =>'0');
irq_tstamp_threshold <= x"00000001"; -- default 256 timestamps: full memory
irq_time_threshold <= x"00000001"; -- default 200 ms
dac_word <= c_DEFAULT_DAC_WORD; -- default DAC Vout = 1.65
@@ -395,9 +386,6 @@ begin
wrabbit_ctrl_reg <= wb_in.dat;
end if;
- if reg_adr = c_DEACT_CHAN_ADR then
- deactivate_chan <= wb_in.dat;
- end if;
end if;
end if;
@@ -411,7 +399,6 @@ begin
irq_time_threshold_o <= irq_time_threshold;
dac_word_o <= dac_word;
wrabbit_ctrl_reg_o <= wrabbit_ctrl_reg;
- deactivate_chan_o <= deactivate_chan(4 downto 0);
---------------------------------------------------------------------------------------------------
-- Reception of TDC core Control Register --
@@ -453,7 +440,6 @@ begin
acam_rdbk_start01_p_o <= ctrl_reg(7);
acam_rst_p_o <= ctrl_reg(8);
load_utc_p_o <= ctrl_reg(9);
- dacapo_c_rst_p_o <= ctrl_reg(10) or ctrl_reg(1); -- dacapo register reset when the acquisition is deactivated
send_dac_word_p <= ctrl_reg(11);
-- ctrl_reg bits 12 to 31 not used for the moment!
@@ -545,12 +531,12 @@ begin
-- regs written locally by the TDC core units
local_utc_i when c_LOCAL_UTC_ADR,
irq_code_i when c_IRQ_CODE_ADR,
- wr_index_i when c_WR_INDEX_ADR,
+ x"00000000" when c_WR_INDEX_ADR,
core_status_i when c_CORE_STATUS_ADR,
-- White Rabbit regs
wrabbit_status_reg_i when c_WRABBIT_STATUS_ADR,
wrabbit_ctrl_reg when c_WRABBIT_CTRL_ADR,
- deactivate_chan when c_DEACT_CHAN_ADR,
+ x"00000000" when c_DEACT_CHAN_ADR,
-- others
x"00000000" when others;
diff --git a/hdl/rtl/tdc_core_pkg.vhd b/hdl/rtl/tdc_core_pkg.vhd
index 08cc307097be344493cc3a13ebdde6550154603a..c8237c5fe75f1a86d9d3a33f07563629e42258f2 100644
--- a/hdl/rtl/tdc_core_pkg.vhd
+++ b/hdl/rtl/tdc_core_pkg.vhd
@@ -170,7 +170,7 @@ package tdc_core_pkg is
date => x"20130429",
name => "WB-TDC-Core-Config ")));
- constant c_TDC_MEM_SDB_DEVICE : t_sdb_device :=
+ constant c_TDC_FIFO_SDB_DEVICE : t_sdb_device :=
(abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
@@ -178,13 +178,13 @@ package tdc_core_pkg is
wbd_width => x"4", -- 32-bit port granularity
sdb_component =>
(addr_first => x"0000000000000000",
- addr_last => x"0000000000000FFF",
+ addr_last => x"00000000000000FF",
product =>
(vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000601", -- "WB-TDC-Mem " | md5sum | cut -c1-8
+ device_id => x"00000622", -- "WB-TDC-Mem " | md5sum | cut -c1-8
version => x"00000001",
- date => x"20121116",
- name => "WB-TDC-Mem ")));
+ date => x"20150415",
+ name => "WB-TDC-TsFIFO ")));
---------------------------------------------------------------------------------------------------
@@ -432,12 +432,11 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-
component fmc_tdc_core is
- generic
- (g_span : integer := 32;
- g_width : integer := 32;
- g_simulation : boolean := FALSE);
+ generic (
+ g_span : integer;
+ g_width : integer;
+ g_simulation : boolean);
port (
clk_sys_i : in std_logic;
rst_n_sys_i : in std_logic;
@@ -476,9 +475,6 @@ package tdc_core_pkg is
tdc_in_fpga_3_i : in std_logic;
tdc_in_fpga_4_i : in std_logic;
tdc_in_fpga_5_i : in std_logic;
- irq_tstamp_p_o : out std_logic;
- irq_time_p_o : out std_logic;
- irq_acam_err_p_o : out std_logic;
wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
wrabbit_synched_i : in std_logic;
@@ -486,10 +482,11 @@ package tdc_core_pkg is
wrabbit_tai_i : in std_logic_vector(31 downto 0);
cfg_slave_i : in t_wishbone_slave_in;
cfg_slave_o : out t_wishbone_slave_out;
- mem_slave_i : in t_wishbone_slave_in;
- mem_slave_o : out t_wishbone_slave_out;
- direct_timestamp_o : out std_logic_vector(127 downto 0);
- direct_timestamp_stb_o : out std_logic);
+ timestamp_o : out std_logic_vector(127 downto 0);
+ timestamp_stb_o : out std_logic;
+ channel_enable_o : out std_logic_vector(4 downto 0);
+ irq_threshold_o : out std_logic_vector(9 downto 0);
+ irq_timeout_o : out std_logic_vector(9 downto 0));
end component fmc_tdc_core;
---------------------------------------------------------------------------------------------------
@@ -647,60 +644,46 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
-
-
- component reg_ctrl
- generic
- (g_span : integer := 32;
- g_width : integer := 32);
- port
- (clk_sys_i : in std_logic;
- rst_n_sys_i : in std_logic; -- global reset, synched to clk_sys_i
-
- clk_tdc_i : in std_logic;
- rst_tdc_i : in std_logic;
-
- slave_i: in t_wishbone_slave_in; -- WB interface (clk_sys domain)
- slave_o: out t_wishbone_slave_out;
-
-
- acam_config_rdbk_i : in config_vector;
- acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
- acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
- acam_start01_i : in std_logic_vector(g_width-1 downto 0);
- local_utc_i : in std_logic_vector(g_width-1 downto 0);
- irq_code_i : in std_logic_vector(g_width-1 downto 0);
- wr_index_i : in std_logic_vector(g_width-1 downto 0);
- core_status_i : in std_logic_vector(g_width-1 downto 0);
- wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
- ----------------------------------------------------------------------
-
- activate_acq_p_o : out std_logic;
- deactivate_acq_p_o : out std_logic;
- deactivate_chan_o : out std_logic_vector(4 downto 0);
- acam_wr_config_p_o : out std_logic;
- acam_rdbk_config_p_o : out std_logic;
- acam_rdbk_status_p_o : out std_logic;
- acam_rdbk_ififo1_p_o : out std_logic;
- acam_rdbk_ififo2_p_o : out std_logic;
- acam_rdbk_start01_p_o : out std_logic;
- acam_rst_p_o : out std_logic;
- load_utc_p_o : out std_logic;
- irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
- irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
- send_dac_word_p_o : out std_logic;
- dac_word_o : out std_logic_vector(23 downto 0);
- dacapo_c_rst_p_o : out std_logic;
- acam_config_o : out config_vector;
- starting_utc_o : out std_logic_vector(g_width-1 downto 0);
- acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0);
- start_phase_o : out std_logic_vector(g_width-1 downto 0);
- one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
- wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
+ component reg_ctrl is
+ generic (
+ g_span : integer := 32;
+ g_width : integer := 32);
+ port (
+ clk_sys_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ clk_tdc_i : in std_logic;
+ rst_tdc_i : in std_logic;
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+ acam_config_rdbk_i : in config_vector;
+ acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
+ acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
+ acam_start01_i : in std_logic_vector(g_width-1 downto 0);
+ local_utc_i : in std_logic_vector(g_width-1 downto 0);
+ core_status_i : in std_logic_vector(g_width-1 downto 0);
+ irq_code_i : in std_logic_vector(g_width-1 downto 0);
+ wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
+ acam_config_o : out config_vector;
+ activate_acq_p_o : out std_logic;
+ deactivate_acq_p_o : out std_logic;
+ acam_wr_config_p_o : out std_logic;
+ acam_rdbk_config_p_o : out std_logic;
+ acam_rst_p_o : out std_logic;
+ acam_rdbk_status_p_o : out std_logic;
+ acam_rdbk_ififo1_p_o : out std_logic;
+ acam_rdbk_ififo2_p_o : out std_logic;
+ acam_rdbk_start01_p_o : out std_logic;
+ send_dac_word_p_o : out std_logic;
+ dac_word_o : out std_logic_vector(23 downto 0);
+ load_utc_p_o : out std_logic;
+ starting_utc_o : out std_logic_vector(g_width-1 downto 0);
+ irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
+ irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
+ one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
+ acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0);
+ wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
+ start_phase_o : out std_logic_vector(g_width-1 downto 0));
+ end component reg_ctrl;
---------------------------------------------------------------------------------------------------
component acam_timecontrol_interface
port
@@ -721,58 +704,26 @@ package tdc_core_pkg is
acam_intflag_f_edge_p_o : out std_logic);
----------------------------------------------------------------------
end component;
+
+ component data_formatting is
+ port (
+ clk_i : in std_logic;
+ rst_i : in std_logic;
+ acam_tstamp1_ok_p_i : in std_logic;
+ acam_tstamp1_i : in std_logic_vector(31 downto 0);
+ acam_tstamp2_ok_p_i : in std_logic;
+ acam_tstamp2_i : in std_logic_vector(31 downto 0);
+ utc_i : in std_logic_vector(31 downto 0);
+ roll_over_incr_recent_i : in std_logic;
+ clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
+ roll_over_nb_i : in std_logic_vector(31 downto 0);
+ retrig_nb_offset_i : in std_logic_vector(31 downto 0);
+ utc_p_i : in std_logic;
+ timestamp_o : out std_logic_vector(127 downto 0);
+ timestamp_valid_o : out std_logic);
+ end component data_formatting;
----------------------------------------------------------------------------------------------------
- component data_formatting
- port
- (tstamp_wr_wb_ack_i : in std_logic;
- acam_tstamp1_i : in std_logic_vector(31 downto 0);
- acam_tstamp1_ok_p_i : in std_logic;
- acam_tstamp2_i : in std_logic_vector(31 downto 0);
- acam_tstamp2_ok_p_i : in std_logic;
- clk_i : in std_logic;
- dacapo_c_rst_p_i : in std_logic;
- deactivate_chan_i : in std_logic_vector(4 downto 0);
- rst_i : in std_logic;
- roll_over_incr_recent_i : in std_logic;
- clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
- roll_over_nb_i : in std_logic_vector(31 downto 0);
- utc_i : in std_logic_vector(31 downto 0);
- retrig_nb_offset_i : in std_logic_vector(31 downto 0);
- utc_p_i : in std_logic;
- ----------------------------------------------------------------------
- tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
- tstamp_wr_wb_cyc_o : out std_logic;
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
- tstamp_wr_wb_stb_o : out std_logic;
- tstamp_wr_wb_we_o : out std_logic;
- tstamp_wr_p_o : out std_logic;
- acam_channel_o : out std_logic_vector(2 downto 0);
- wr_index_o : out std_logic_vector(31 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component irq_generator is
- generic
- (g_width : integer := 32);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0);
- irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0);
- activate_acq_p_i : in std_logic;
- deactivate_acq_p_i : in std_logic;
- tstamp_wr_p_i : in std_logic;
- acam_errflag_r_edge_p_i : in std_logic;
- ----------------------------------------------------------------------
- irq_tstamp_p_o : out std_logic;
- irq_acam_err_p_o : out std_logic;
- irq_time_p_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
---------------------------------------------------------------------------------------------------
@@ -914,29 +865,6 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
- component circular_buffer
- port (
- clk_tdc_i : in std_logic;
- clk_sys_i : in std_logic;
- rst_n_sys_i : in std_logic;
- tstamp_wr_rst_i : in std_logic;
- tstamp_wr_stb_i : in std_logic;
- tstamp_wr_cyc_i : in std_logic;
- tstamp_wr_we_i : in std_logic;
- tstamp_wr_adr_i : in std_logic_vector(7 downto 0);
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
- tdc_mem_wb_rst_i : in std_logic;
- tdc_mem_wb_stb_i : in std_logic;
- tdc_mem_wb_cyc_i : in std_logic;
- tdc_mem_wb_we_i : in std_logic;
- tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
- tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
- tstamp_wr_ack_p_o : out std_logic;
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
- tdc_mem_wb_ack_o : out std_logic;
- tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
- tdc_mem_wb_stall_o : out std_logic);
- end component;
component fmc_tdc_wrapper is
generic (
diff --git a/hdl/rtl/timestamp_fifo.vhd b/hdl/rtl/timestamp_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bdabb677f0c965091a498b72c9fb8f076ea30d4b
--- /dev/null
+++ b/hdl/rtl/timestamp_fifo.vhd
@@ -0,0 +1,190 @@
+--_________________________________________________________________________________________________
+-- |
+-- |TDC core| |
+-- |
+-- CERN,BE/CO-HT |
+--________________________________________________________________________________________________|
+
+---------------------------------------------------------------------------------------------------
+-- GNU LESSER GENERAL PUBLIC LICENSE |
+-- ------------------------------------ |
+-- This source file is free software; you can redistribute it and/or modify it under the terms of |
+-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
+-- version 2.1 of the License, or (at your option) any later version. |
+-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
+-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
+-- See the GNU Lesser General Public License for more details. |
+-- You should have received a copy of the GNU Lesser General Public License along with this |
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
+---------------------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.NUMERIC_STD.all;
+
+use work.tsf_wbgen2_pkg.all;
+use work.wishbone_pkg.all;
+use work.gencores_pkg.all;
+
+entity timestamp_fifo is
+ generic (
+ g_channel : integer
+ );
+ port (
+ clk_sys_i : in std_logic;
+ clk_tdc_i : in std_logic;
+ rst_n_sys_i : in std_logic;
+ rst_tdc_i : in std_logic;
+
+ -- WB slave, system clock
+ slave_i : in t_wishbone_slave_in;
+ slave_o : out t_wishbone_slave_out;
+
+ irq_o : out std_logic; -- IRQ line, level high, system clock
+
+ enable_i : in std_logic; -- channel enable, TDC clock
+ tick_i : in std_logic; -- 1ms tick, TDC clock
+
+
+ irq_threshold_i : in std_logic_vector(9 downto 0);
+ irq_timeout_i : in std_logic_vector(9 downto 0);
+
+ timestamp_i : in std_logic_vector(127 downto 0);
+ timestamp_valid_i : in std_logic
+ );
+
+end entity;
+
+architecture rtl of timestamp_fifo is
+
+ component timestamp_fifo_wb is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ clk_tdc_i : in std_logic;
+ regs_i : in t_tsf_in_registers;
+ regs_o : out t_tsf_out_registers);
+ end component timestamp_fifo_wb;
+
+ signal tmr_timeout : unsigned(9 downto 0);
+ signal buf_irq_int : std_logic;
+ signal buf_count : unsigned(9 downto 0);
+
+ signal last_ts : std_logic_vector(127 downto 0);
+ signal regs_in : t_tsf_in_registers;
+ signal regs_out : t_tsf_out_registers;
+ signal channel_id : std_logic_vector(2 downto 0);
+
+ signal ts_match : std_logic;
+begin
+
+ U_WB_Slave : timestamp_fifo_wb
+ port map (
+ rst_n_i => rst_n_sys_i,
+ clk_sys_i => clk_sys_i,
+ wb_adr_i => slave_i.adr(5 downto 2),
+ wb_dat_i => slave_i.dat,
+ wb_dat_o => slave_o.dat,
+ wb_cyc_i => slave_i.cyc,
+ wb_sel_i => slave_i.sel,
+ wb_stb_i => slave_i.stb,
+ wb_we_i => slave_i.we,
+ wb_ack_o => slave_o.ack,
+ wb_stall_o => slave_o.stall,
+ clk_tdc_i => clk_tdc_i,
+ regs_i => regs_in,
+ regs_o => regs_out);
+
+ buf_count <= unsigned(regs_out.fifo_wr_usedw_o);
+
+ ts_match <= '1' when timestamp_valid_i = '1' and unsigned(timestamp_i(98 downto 96)) = g_channel else '0';
+
+ p_fifo_write : process(clk_tdc_i)
+ begin
+ if rising_edge(clk_tdc_i) then
+ if rst_tdc_i = '1' then
+ regs_in.fifo_wr_req_i <= '0';
+ else
+ if(enable_i = '1' and regs_out.fifo_wr_full_o = '0' and ts_match = '1') then
+ regs_in.fifo_wr_req_i <= '1';
+ else
+ regs_in.fifo_wr_req_i <= '0';
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_latch_last_timestamp : process(clk_tdc_i)
+ begin
+ if rising_edge(clk_tdc_i) then
+ if rst_tdc_i = '1' then
+ regs_in.ltsctl_valid_i <= '0';
+ else
+ if (enable_i = '1' and ts_match = '1') then
+ regs_in.ltsctl_valid_i <= '1';
+ last_ts <= timestamp_i;
+ elsif (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then
+ regs_in.ltsctl_valid_i <= '0';
+ end if;
+
+ if (regs_out.ltsctl_valid_o = '0' and regs_out.ltsctl_valid_load_o = '1') then
+ regs_in.lts0_i <= last_ts(127 downto 96);
+ regs_in.lts1_i <= last_ts(95 downto 64);
+ regs_in.lts2_i <= last_ts(63 downto 32);
+ regs_in.lts3_i <= last_ts(31 downto 0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ p_coalesce_irq : process(clk_tdc_i)
+ begin
+ if rising_edge(clk_tdc_i) then
+ if rst_tdc_i = '1' or enable_i = '0' then
+ buf_irq_int <= '0';
+ else
+ if(buf_count = 0) then
+ buf_irq_int <= '0';
+ tmr_timeout <= (others => '0');
+ else
+ -- Simple interrupt coalescing :
+
+ -- Case 1: There is some data in the buffer
+ -- (but not exceeding the threshold) - assert the IRQ line after a
+ -- certain timeout.
+ if(buf_irq_int = '0') then
+ if(tmr_timeout = unsigned(irq_timeout_i(9 downto 0))) then
+ buf_irq_int <= '1';
+ tmr_timeout <= (others => '0');
+ elsif(tick_i = '1') then
+ tmr_timeout <= tmr_timeout + 1;
+ end if;
+ end if;
+
+ -- Case 2: amount of data exceeded the threshold - assert the IRQ
+ -- line immediately.
+ if(buf_count > unsigned(irq_threshold_i(9 downto 0))) then
+ buf_irq_int <= '1';
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ U_Sync_IRQ : gc_sync_ffs
+ port map (
+ clk_i => clk_sys_i,
+ rst_n_i => rst_n_sys_i,
+ data_i => buf_irq_int,
+ synced_o => irq_o);
+
+end rtl;
diff --git a/hdl/rtl/timestamp_fifo_wb.vhd b/hdl/rtl/timestamp_fifo_wb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8aee1f1d7e7e6593940e1a7cc82fae3c8fcd48eb
--- /dev/null
+++ b/hdl/rtl/timestamp_fifo_wb.vhd
@@ -0,0 +1,646 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for Timestamp FIFO
+---------------------------------------------------------------------------------------
+-- File : timestamp_fifo_wb.vhd
+-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
+-- Created : Tue Apr 14 16:47:08 2015
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+use work.tsf_wbgen2_pkg.all;
+
+
+entity timestamp_fifo_wb is
+ port (
+ rst_n_i : in std_logic;
+ clk_sys_i : in std_logic;
+ wb_adr_i : in std_logic_vector(3 downto 0);
+ wb_dat_i : in std_logic_vector(31 downto 0);
+ wb_dat_o : out std_logic_vector(31 downto 0);
+ wb_cyc_i : in std_logic;
+ wb_sel_i : in std_logic_vector(3 downto 0);
+ wb_stb_i : in std_logic;
+ wb_we_i : in std_logic;
+ wb_ack_o : out std_logic;
+ wb_stall_o : out std_logic;
+ clk_tdc_i : in std_logic;
+ regs_i : in t_tsf_in_registers;
+ regs_o : out t_tsf_out_registers
+ );
+end timestamp_fifo_wb;
+
+architecture syn of timestamp_fifo_wb is
+
+signal tsf_fifo_rst_n : std_logic ;
+signal tsf_fifo_in_int : std_logic_vector(127 downto 0);
+signal tsf_fifo_out_int : std_logic_vector(127 downto 0);
+signal tsf_fifo_rdreq_int : std_logic ;
+signal tsf_fifo_rdreq_int_d0 : std_logic ;
+signal tsf_lts0_int : std_logic_vector(31 downto 0);
+signal tsf_lts0_lwb : std_logic ;
+signal tsf_lts0_lwb_delay : std_logic ;
+signal tsf_lts0_lwb_in_progress : std_logic ;
+signal tsf_lts0_lwb_s0 : std_logic ;
+signal tsf_lts0_lwb_s1 : std_logic ;
+signal tsf_lts0_lwb_s2 : std_logic ;
+signal tsf_lts1_int : std_logic_vector(31 downto 0);
+signal tsf_lts1_lwb : std_logic ;
+signal tsf_lts1_lwb_delay : std_logic ;
+signal tsf_lts1_lwb_in_progress : std_logic ;
+signal tsf_lts1_lwb_s0 : std_logic ;
+signal tsf_lts1_lwb_s1 : std_logic ;
+signal tsf_lts1_lwb_s2 : std_logic ;
+signal tsf_lts2_int : std_logic_vector(31 downto 0);
+signal tsf_lts2_lwb : std_logic ;
+signal tsf_lts2_lwb_delay : std_logic ;
+signal tsf_lts2_lwb_in_progress : std_logic ;
+signal tsf_lts2_lwb_s0 : std_logic ;
+signal tsf_lts2_lwb_s1 : std_logic ;
+signal tsf_lts2_lwb_s2 : std_logic ;
+signal tsf_lts3_int : std_logic_vector(31 downto 0);
+signal tsf_lts3_lwb : std_logic ;
+signal tsf_lts3_lwb_delay : std_logic ;
+signal tsf_lts3_lwb_in_progress : std_logic ;
+signal tsf_lts3_lwb_s0 : std_logic ;
+signal tsf_lts3_lwb_s1 : std_logic ;
+signal tsf_lts3_lwb_s2 : std_logic ;
+signal tsf_ltsctl_valid_int_read : std_logic ;
+signal tsf_ltsctl_valid_int_write : std_logic ;
+signal tsf_ltsctl_valid_lw : std_logic ;
+signal tsf_ltsctl_valid_lw_delay : std_logic ;
+signal tsf_ltsctl_valid_lw_read_in_progress : std_logic ;
+signal tsf_ltsctl_valid_lw_s0 : std_logic ;
+signal tsf_ltsctl_valid_lw_s1 : std_logic ;
+signal tsf_ltsctl_valid_lw_s2 : std_logic ;
+signal tsf_ltsctl_valid_rwsel : std_logic ;
+signal tsf_fifo_full_int : std_logic ;
+signal tsf_fifo_empty_int : std_logic ;
+signal tsf_fifo_usedw_int : std_logic_vector(9 downto 0);
+signal ack_sreg : std_logic_vector(9 downto 0);
+signal rddata_reg : std_logic_vector(31 downto 0);
+signal wrdata_reg : std_logic_vector(31 downto 0);
+signal bwsel_reg : std_logic_vector(3 downto 0);
+signal rwaddr_reg : std_logic_vector(3 downto 0);
+signal ack_in_progress : std_logic ;
+signal wr_int : std_logic ;
+signal rd_int : std_logic ;
+signal allones : std_logic_vector(31 downto 0);
+signal allzeros : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+ wrdata_reg <= wb_dat_i;
+ bwsel_reg <= wb_sel_i;
+ rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+ wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+ allones <= (others => '1');
+ allzeros <= (others => '0');
+--
+-- Main register bank access process.
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ ack_sreg <= "0000000000";
+ ack_in_progress <= '0';
+ rddata_reg <= "00000000000000000000000000000000";
+ tsf_lts0_lwb <= '0';
+ tsf_lts0_lwb_delay <= '0';
+ tsf_lts0_lwb_in_progress <= '0';
+ tsf_lts1_lwb <= '0';
+ tsf_lts1_lwb_delay <= '0';
+ tsf_lts1_lwb_in_progress <= '0';
+ tsf_lts2_lwb <= '0';
+ tsf_lts2_lwb_delay <= '0';
+ tsf_lts2_lwb_in_progress <= '0';
+ tsf_lts3_lwb <= '0';
+ tsf_lts3_lwb_delay <= '0';
+ tsf_lts3_lwb_in_progress <= '0';
+ tsf_ltsctl_valid_lw <= '0';
+ tsf_ltsctl_valid_lw_delay <= '0';
+ tsf_ltsctl_valid_lw_read_in_progress <= '0';
+ tsf_ltsctl_valid_rwsel <= '0';
+ tsf_ltsctl_valid_int_write <= '0';
+ tsf_fifo_rdreq_int <= '0';
+ elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+ ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+ ack_sreg(9) <= '0';
+ if (ack_in_progress = '1') then
+ if (ack_sreg(0) = '1') then
+ ack_in_progress <= '0';
+ else
+ tsf_lts0_lwb <= tsf_lts0_lwb_delay;
+ tsf_lts0_lwb_delay <= '0';
+ if ((ack_sreg(1) = '1') and (tsf_lts0_lwb_in_progress = '1')) then
+ rddata_reg(31 downto 0) <= tsf_lts0_int;
+ tsf_lts0_lwb_in_progress <= '0';
+ end if;
+ tsf_lts1_lwb <= tsf_lts1_lwb_delay;
+ tsf_lts1_lwb_delay <= '0';
+ if ((ack_sreg(1) = '1') and (tsf_lts1_lwb_in_progress = '1')) then
+ rddata_reg(31 downto 0) <= tsf_lts1_int;
+ tsf_lts1_lwb_in_progress <= '0';
+ end if;
+ tsf_lts2_lwb <= tsf_lts2_lwb_delay;
+ tsf_lts2_lwb_delay <= '0';
+ if ((ack_sreg(1) = '1') and (tsf_lts2_lwb_in_progress = '1')) then
+ rddata_reg(31 downto 0) <= tsf_lts2_int;
+ tsf_lts2_lwb_in_progress <= '0';
+ end if;
+ tsf_lts3_lwb <= tsf_lts3_lwb_delay;
+ tsf_lts3_lwb_delay <= '0';
+ if ((ack_sreg(1) = '1') and (tsf_lts3_lwb_in_progress = '1')) then
+ rddata_reg(31 downto 0) <= tsf_lts3_int;
+ tsf_lts3_lwb_in_progress <= '0';
+ end if;
+ tsf_ltsctl_valid_lw <= tsf_ltsctl_valid_lw_delay;
+ tsf_ltsctl_valid_lw_delay <= '0';
+ if ((ack_sreg(1) = '1') and (tsf_ltsctl_valid_lw_read_in_progress = '1')) then
+ rddata_reg(0) <= tsf_ltsctl_valid_int_read;
+ tsf_ltsctl_valid_lw_read_in_progress <= '0';
+ end if;
+ end if;
+ else
+ if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+ case rwaddr_reg(3 downto 0) is
+ when "0000" =>
+ if (wb_we_i = '1') then
+ end if;
+ if (wb_we_i = '0') then
+ tsf_lts0_lwb <= '1';
+ tsf_lts0_lwb_delay <= '1';
+ tsf_lts0_lwb_in_progress <= '1';
+ end if;
+ ack_sreg(5) <= '1';
+ ack_in_progress <= '1';
+ when "0001" =>
+ if (wb_we_i = '1') then
+ end if;
+ if (wb_we_i = '0') then
+ tsf_lts1_lwb <= '1';
+ tsf_lts1_lwb_delay <= '1';
+ tsf_lts1_lwb_in_progress <= '1';
+ end if;
+ ack_sreg(5) <= '1';
+ ack_in_progress <= '1';
+ when "0010" =>
+ if (wb_we_i = '1') then
+ end if;
+ if (wb_we_i = '0') then
+ tsf_lts2_lwb <= '1';
+ tsf_lts2_lwb_delay <= '1';
+ tsf_lts2_lwb_in_progress <= '1';
+ end if;
+ ack_sreg(5) <= '1';
+ ack_in_progress <= '1';
+ when "0011" =>
+ if (wb_we_i = '1') then
+ end if;
+ if (wb_we_i = '0') then
+ tsf_lts3_lwb <= '1';
+ tsf_lts3_lwb_delay <= '1';
+ tsf_lts3_lwb_in_progress <= '1';
+ end if;
+ ack_sreg(5) <= '1';
+ ack_in_progress <= '1';
+ when "0100" =>
+ if (wb_we_i = '1') then
+ tsf_ltsctl_valid_int_write <= wrdata_reg(0);
+ tsf_ltsctl_valid_lw <= '1';
+ tsf_ltsctl_valid_lw_delay <= '1';
+ tsf_ltsctl_valid_lw_read_in_progress <= '0';
+ tsf_ltsctl_valid_rwsel <= '1';
+ end if;
+ if (wb_we_i = '0') then
+ rddata_reg(0) <= 'X';
+ tsf_ltsctl_valid_lw <= '1';
+ tsf_ltsctl_valid_lw_delay <= '1';
+ tsf_ltsctl_valid_lw_read_in_progress <= '1';
+ tsf_ltsctl_valid_rwsel <= '0';
+ end if;
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(5) <= '1';
+ ack_in_progress <= '1';
+ when "0101" =>
+ if (wb_we_i = '1') then
+ end if;
+ if (tsf_fifo_rdreq_int_d0 = '0') then
+ tsf_fifo_rdreq_int <= not tsf_fifo_rdreq_int;
+ else
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ when "0110" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "0111" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1000" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1001" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(0) <= 'X';
+ rddata_reg(1) <= 'X';
+ rddata_reg(2) <= 'X';
+ rddata_reg(3) <= 'X';
+ rddata_reg(4) <= 'X';
+ rddata_reg(5) <= 'X';
+ rddata_reg(6) <= 'X';
+ rddata_reg(7) <= 'X';
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when "1010" =>
+ if (wb_we_i = '1') then
+ end if;
+ rddata_reg(16) <= tsf_fifo_full_int;
+ rddata_reg(17) <= tsf_fifo_empty_int;
+ rddata_reg(9 downto 0) <= tsf_fifo_usedw_int;
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
+ ack_sreg(0) <= '1';
+ ack_in_progress <= '1';
+ when others =>
+-- prevent the slave from hanging the bus on invalid address
+ ack_in_progress <= '1';
+ ack_sreg(0) <= '1';
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+-- Drive the data output bus
+ wb_dat_o <= rddata_reg;
+-- extra code for reg/fifo/mem: Timestamp FIFO
+ tsf_fifo_in_int(127 downto 0) <= regs_i.fifo_value_i;
+ tsf_fifo_rst_n <= rst_n_i;
+ tsf_fifo_INST : wbgen2_fifo_async
+ generic map (
+ g_size => 1024,
+ g_width => 128,
+ g_usedw_size => 10
+ )
+ port map (
+ wr_req_i => regs_i.fifo_wr_req_i,
+ wr_full_o => regs_o.fifo_wr_full_o,
+ wr_empty_o => regs_o.fifo_wr_empty_o,
+ wr_usedw_o => regs_o.fifo_wr_usedw_o,
+ rd_full_o => tsf_fifo_full_int,
+ rd_empty_o => tsf_fifo_empty_int,
+ rd_usedw_o => tsf_fifo_usedw_int,
+ rd_req_i => tsf_fifo_rdreq_int,
+ rst_n_i => tsf_fifo_rst_n,
+ wr_clk_i => clk_tdc_i,
+ rd_clk_i => clk_sys_i,
+ wr_data_i => tsf_fifo_in_int,
+ rd_data_o => tsf_fifo_out_int
+ );
+
+-- Last Timestamp Word 0
+-- asynchronous std_logic_vector register : Last Timestamp Word 0 (type RO/WO, clk_tdc_i <-> clk_sys_i)
+ process (clk_tdc_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_lts0_lwb_s0 <= '0';
+ tsf_lts0_lwb_s1 <= '0';
+ tsf_lts0_lwb_s2 <= '0';
+ tsf_lts0_int <= "00000000000000000000000000000000";
+ elsif rising_edge(clk_tdc_i) then
+ tsf_lts0_lwb_s0 <= tsf_lts0_lwb;
+ tsf_lts0_lwb_s1 <= tsf_lts0_lwb_s0;
+ tsf_lts0_lwb_s2 <= tsf_lts0_lwb_s1;
+ if ((tsf_lts0_lwb_s1 = '1') and (tsf_lts0_lwb_s2 = '0')) then
+ tsf_lts0_int <= regs_i.lts0_i;
+ end if;
+ end if;
+ end process;
+
+
+-- Last Timestamp Word 1
+-- asynchronous std_logic_vector register : Last Timestamp Word 1 (type RO/WO, clk_tdc_i <-> clk_sys_i)
+ process (clk_tdc_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_lts1_lwb_s0 <= '0';
+ tsf_lts1_lwb_s1 <= '0';
+ tsf_lts1_lwb_s2 <= '0';
+ tsf_lts1_int <= "00000000000000000000000000000000";
+ elsif rising_edge(clk_tdc_i) then
+ tsf_lts1_lwb_s0 <= tsf_lts1_lwb;
+ tsf_lts1_lwb_s1 <= tsf_lts1_lwb_s0;
+ tsf_lts1_lwb_s2 <= tsf_lts1_lwb_s1;
+ if ((tsf_lts1_lwb_s1 = '1') and (tsf_lts1_lwb_s2 = '0')) then
+ tsf_lts1_int <= regs_i.lts1_i;
+ end if;
+ end if;
+ end process;
+
+
+-- Last Timestamp Word 2
+-- asynchronous std_logic_vector register : Last Timestamp Word 2 (type RO/WO, clk_tdc_i <-> clk_sys_i)
+ process (clk_tdc_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_lts2_lwb_s0 <= '0';
+ tsf_lts2_lwb_s1 <= '0';
+ tsf_lts2_lwb_s2 <= '0';
+ tsf_lts2_int <= "00000000000000000000000000000000";
+ elsif rising_edge(clk_tdc_i) then
+ tsf_lts2_lwb_s0 <= tsf_lts2_lwb;
+ tsf_lts2_lwb_s1 <= tsf_lts2_lwb_s0;
+ tsf_lts2_lwb_s2 <= tsf_lts2_lwb_s1;
+ if ((tsf_lts2_lwb_s1 = '1') and (tsf_lts2_lwb_s2 = '0')) then
+ tsf_lts2_int <= regs_i.lts2_i;
+ end if;
+ end if;
+ end process;
+
+
+-- Last Timestamp Word 3
+-- asynchronous std_logic_vector register : Last Timestamp Word 3 (type RO/WO, clk_tdc_i <-> clk_sys_i)
+ process (clk_tdc_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_lts3_lwb_s0 <= '0';
+ tsf_lts3_lwb_s1 <= '0';
+ tsf_lts3_lwb_s2 <= '0';
+ tsf_lts3_int <= "00000000000000000000000000000000";
+ elsif rising_edge(clk_tdc_i) then
+ tsf_lts3_lwb_s0 <= tsf_lts3_lwb;
+ tsf_lts3_lwb_s1 <= tsf_lts3_lwb_s0;
+ tsf_lts3_lwb_s2 <= tsf_lts3_lwb_s1;
+ if ((tsf_lts3_lwb_s1 = '1') and (tsf_lts3_lwb_s2 = '0')) then
+ tsf_lts3_int <= regs_i.lts3_i;
+ end if;
+ end if;
+ end process;
+
+
+-- Last Timestamp Valid
+-- asynchronous BIT register : Last Timestamp Valid (type RW/WO, clk_tdc_i <-> clk_sys_i)
+ process (clk_tdc_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_ltsctl_valid_lw_s0 <= '0';
+ tsf_ltsctl_valid_lw_s1 <= '0';
+ tsf_ltsctl_valid_lw_s2 <= '0';
+ tsf_ltsctl_valid_int_read <= '0';
+ regs_o.ltsctl_valid_load_o <= '0';
+ regs_o.ltsctl_valid_o <= '0';
+ elsif rising_edge(clk_tdc_i) then
+ tsf_ltsctl_valid_lw_s0 <= tsf_ltsctl_valid_lw;
+ tsf_ltsctl_valid_lw_s1 <= tsf_ltsctl_valid_lw_s0;
+ tsf_ltsctl_valid_lw_s2 <= tsf_ltsctl_valid_lw_s1;
+ if ((tsf_ltsctl_valid_lw_s2 = '0') and (tsf_ltsctl_valid_lw_s1 = '1')) then
+ if (tsf_ltsctl_valid_rwsel = '1') then
+ regs_o.ltsctl_valid_o <= tsf_ltsctl_valid_int_write;
+ regs_o.ltsctl_valid_load_o <= '1';
+ else
+ regs_o.ltsctl_valid_load_o <= '0';
+ tsf_ltsctl_valid_int_read <= regs_i.ltsctl_valid_i;
+ end if;
+ else
+ regs_o.ltsctl_valid_load_o <= '0';
+ end if;
+ end if;
+ end process;
+
+
+-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 0
+ process (clk_sys_i, rst_n_i)
+ begin
+ if (rst_n_i = '0') then
+ tsf_fifo_rdreq_int_d0 <= '0';
+ elsif rising_edge(clk_sys_i) then
+ tsf_fifo_rdreq_int_d0 <= tsf_fifo_rdreq_int;
+ end if;
+ end process;
+
+
+-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 1
+-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 2
+-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 3
+-- extra code for reg/fifo/mem: FIFO 'Timestamp FIFO' data output register 4
+ rwaddr_reg <= wb_adr_i;
+ wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+ wb_ack_o <= ack_sreg(0);
+end syn;
diff --git a/hdl/rtl/timestamp_fifo_wb.wb b/hdl/rtl/timestamp_fifo_wb.wb
new file mode 100644
index 0000000000000000000000000000000000000000..c007c361183bd942f3282e34b866ba36b445550e
--- /dev/null
+++ b/hdl/rtl/timestamp_fifo_wb.wb
@@ -0,0 +1,102 @@
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+ name = "Timestamp FIFO";
+ prefix="tsf";
+
+ hdl_entity="timestamp_fifo_wb";
+
+ -- TXTSU shared FIFO
+
+ fifo_reg {
+ size = 1024; -- or more. We'll see :)
+ direction = CORE_TO_BUS;
+ prefix = "fifo";
+ name = "Timestamp FIFO";
+ clock = "clk_tdc_i";
+
+ flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
+ flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
+
+ field {
+ name = "The timestamp";
+ prefix = "value";
+ type = SLV;
+ size = 128;
+ };
+ };
+
+
+ reg {
+ name = "Last Timestamp Word 0";
+ prefix = "LTS0";
+
+ field {
+ name = "Last Timestamp Word 0";
+ clock = "clk_tdc_i";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+
+ };
+ };
+ reg {
+ name = "Last Timestamp Word 1";
+ prefix = "LTS1";
+
+ field {
+ name = "Last Timestamp Word 1";
+ clock = "clk_tdc_i";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "Last Timestamp Word 2";
+ prefix = "LTS2";
+
+ field {
+ name = "Last Timestamp Word 2";
+ clock = "clk_tdc_i";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+
+ };
+ };
+
+ reg {
+ name = "Last Timestamp Word 3";
+ prefix = "LTS3";
+
+ field {
+ name = "Last Timestamp Word 3";
+ clock = "clk_tdc_i";
+ type = SLV;
+ size = 32;
+ access_bus = READ_ONLY;
+ access_dev = WRITE_ONLY;
+ };
+ };
+
+ reg {
+ name = "Last Timestamp Control/Status";
+ prefix = "LTSCTL";
+
+ field {
+ name = "Last Timestamp Valid";
+ clock = "clk_tdc_i";
+ prefix = "VALID";
+ type = BIT;
+ access_bus = READ_WRITE;
+ access_dev = READ_WRITE;
+ load = LOAD_EXT;
+ };
+ };
+
+};
diff --git a/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd b/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c316a0869465ecb8074f864191004d390b5f4d2c
--- /dev/null
+++ b/hdl/rtl/timestamp_fifo_wbgen2_pkg.vhd
@@ -0,0 +1,98 @@
+---------------------------------------------------------------------------------------
+-- Title : Wishbone slave core for Timestamp FIFO
+---------------------------------------------------------------------------------------
+-- File : timestamp_fifo_wbgen2_pkg.vhd
+-- Author : auto-generated by wbgen2 from timestamp_fifo_wb.wb
+-- Created : Tue Apr 14 16:47:08 2015
+-- Standard : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timestamp_fifo_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wbgen2_pkg.all;
+
+package tsf_wbgen2_pkg is
+
+
+ -- Input registers (user design -> WB slave)
+
+ type t_tsf_in_registers is record
+ fifo_wr_req_i : std_logic;
+ fifo_value_i : std_logic_vector(127 downto 0);
+ lts0_i : std_logic_vector(31 downto 0);
+ lts1_i : std_logic_vector(31 downto 0);
+ lts2_i : std_logic_vector(31 downto 0);
+ lts3_i : std_logic_vector(31 downto 0);
+ ltsctl_valid_i : std_logic;
+ end record;
+
+ constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
+ fifo_wr_req_i => '0',
+ fifo_value_i => (others => '0'),
+ lts0_i => (others => '0'),
+ lts1_i => (others => '0'),
+ lts2_i => (others => '0'),
+ lts3_i => (others => '0'),
+ ltsctl_valid_i => '0'
+ );
+
+ -- Output registers (WB slave -> user design)
+
+ type t_tsf_out_registers is record
+ fifo_wr_full_o : std_logic;
+ fifo_wr_empty_o : std_logic;
+ fifo_wr_usedw_o : std_logic_vector(9 downto 0);
+ ltsctl_valid_o : std_logic;
+ ltsctl_valid_load_o : std_logic;
+ end record;
+
+ constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
+ fifo_wr_full_o => '0',
+ fifo_wr_empty_o => '0',
+ fifo_wr_usedw_o => (others => '0'),
+ ltsctl_valid_o => '0',
+ ltsctl_valid_load_o => '0'
+ );
+ function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
+ function f_x_to_zero (x:std_logic) return std_logic;
+ function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body tsf_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if;
+end loop;
+return tmp;
+end function;
+function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
+variable tmp: t_tsf_in_registers;
+begin
+tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
+tmp.fifo_value_i := f_x_to_zero(left.fifo_value_i) or f_x_to_zero(right.fifo_value_i);
+tmp.lts0_i := f_x_to_zero(left.lts0_i) or f_x_to_zero(right.lts0_i);
+tmp.lts1_i := f_x_to_zero(left.lts1_i) or f_x_to_zero(right.lts1_i);
+tmp.lts2_i := f_x_to_zero(left.lts2_i) or f_x_to_zero(right.lts2_i);
+tmp.lts3_i := f_x_to_zero(left.lts3_i) or f_x_to_zero(right.lts3_i);
+tmp.ltsctl_valid_i := f_x_to_zero(left.ltsctl_valid_i) or f_x_to_zero(right.ltsctl_valid_i);
+return tmp;
+end function;
+end package body;
diff --git a/hdl/syn/svec/wr_svec_tdc.xise b/hdl/syn/svec/wr_svec_tdc.xise
index e6da13c89165396165af8d6f52e67885a6d70f4f..edef1afe1a0957a5af83975320a06fea88965c1b 100644
--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
@@ -1,1144 +1,1142 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<?xml version="1.0" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
- </autoManagedFiles>
-
- <properties>
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- <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
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- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
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- <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-27T11:49:48" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
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- <libraries/>
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- <files>
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- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
- </file>
- <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
- </file>
- <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
- </file>
- <file xil_pn:name="../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
- </file>
- <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
- </file>
- <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
- </file>
- <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
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+ <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_svec_tdc|rtl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/svec/wr_svec_tdc.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_svec_tdc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
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+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="svec_top_fmc_tdc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
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+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
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+ <file xil_pn:name="../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
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+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="185"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="186"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="187"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="188"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="189"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="190"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="193"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="194"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="195"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="196"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="197"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="200"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="201"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="202"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="203"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="204"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_ts_counter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="207"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="208"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="209"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="210"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="213"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="216"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="217"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/wr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="222"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="223"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="224"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="225"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="226"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="227"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="228"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="229"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="230"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="231"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="232"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="233"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="234"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="235"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="236"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="237"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="238"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="239"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="240"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="241"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="242"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="243"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="244"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="245"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="246"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="247"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="248"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="249"/>
+</file>
+ <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="250"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="251"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="252"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="253"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="254"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="255"/>
+</file>
+ <file xil_pn:name="../../top/svec/wr_svec_tdc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="256"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="257"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="258"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="259"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="260"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="261"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="262"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="263"/>
+</file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="264"/>
+</file>
+</files>
+ <bindings/>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
diff --git a/hdl/testbench/svec/main.sv b/hdl/testbench/svec/main.sv
index 1e02bf17fd7819c5e443c47525879aea4d425eb2..56f7dfd867920244f3a60937268337a54990150d 100644
--- a/hdl/testbench/svec/main.sv
+++ b/hdl/testbench/svec/main.sv
@@ -1,6 +1,78 @@
`include "simdrv_defs.svh"
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
+`include "../../rtl/timestamp_fifo_regs.vh"
+
+module fake_acam(
+ input [3:0] addr,
+ output reg [27:0] data,
+ input wr,
+ input rd,
+ output reg ef1,
+ output reg ef2
+ );
+
+ typedef struct {
+ int channel;
+ time ts;
+ } acam_fifo_entry;
+
+ acam_fifo_entry fifo1[$], fifo2[$];
+
+ task pulse(int channel, time ts);
+
+ acam_fifo_entry ent;
+
+ ent.channel = channel % 4;
+ ent.ts = ts;
+
+ if (channel >= 0 && channel <= 3)
+ fifo1.push_back(ent);
+ else
+ fifo2.push_back(ent);
+
+ #100ns;
+ if(fifo1.size())
+ ef1 = 0;
+ if(fifo2.size())
+ ef2 = 0;
+
+ endtask // pulse
+
+ initial begin
+ ef1 = 1;
+ ef2 = 1;
+ data = 28'bz;
+
+ end
+
+
+ always@(negedge rd) begin
+ if (addr == 8) begin
+ acam_fifo_entry ent;
+ ent=fifo1.pop_front();
+ data <= ent.ts | (ent.channel << 26);
+
+ end else if (addr == 9) begin
+ acam_fifo_entry ent;
+ ent=fifo2.pop_front();
+ data <= ent.ts | (ent.channel << 26);
+
+ end else
+ data <= 28'bz;
+
+ #10ns;
+
+ ef1 <= (fifo1.size() ? 0 : 1);
+ ef2 <= (fifo2.size() ? 0 : 1);
+
+
+ end
+
+
+
+endmodule
+
module main;
@@ -19,20 +91,6 @@ module main;
`DECLARE_VME_BUFFERS(VME.slave);
- reg tdc_ef1 = 1;
- reg tdc_pulse = 0;
- wire tdc_rd_n;
-
-
- always@(posedge tdc_pulse) begin
- #100ns;
- tdc_ef1 <= 0;
- while(tdc_rd_n != 0)
- #1ns;
- #10ns;
- tdc_ef1 <= 1;
- end
-
reg clk_acam = 0;
reg clk_62m5 = 0;
@@ -43,6 +101,10 @@ module main;
always@(posedge clk_62m5)
clk_acam <= ~clk_acam;
+ wire [3:0] tdc_addr;
+
+ wire [27:0] tdc_data;
+
wr_svec_tdc #(
.g_with_wr_phy(0),
@@ -65,20 +127,24 @@ module main;
.por_n_i(rst_n),
.tdc1_ef1_i(tdc_ef1),
- .tdc1_ef2_i(1'b1),
+ .tdc1_ef2_i(tdc_ef2),
.tdc1_err_flag_i(1'b0),
.tdc1_int_flag_i(1'b0),
.tdc1_rd_n_o(tdc_rd_n),
- .tdc1_in_fpga_1_i(tdc_pulse),
- .tdc1_in_fpga_2_i(1'b0),
- .tdc1_in_fpga_3_i(1'b0),
- .tdc1_in_fpga_4_i(1'b0),
- .tdc1_in_fpga_5_i(1'b0),
- .tdc1_data_bus_io(28'hcafebab),
+ .tdc1_data_bus_io(tdc_data),
+ .tdc1_address_o(tdc_addr),
-
`WIRE_VME_PINS(8)
);
+
+ fake_acam ACAM(
+ .addr(tdc_addr),
+ .data(tdc_data),
+ .wr(1'b0),
+ .rd(tdc_rd_n),
+ .ef1(tdc_ef1),
+ .ef2(tdc_ef2)
+ );
@@ -139,30 +205,60 @@ module main;
$display("Un-reset FMCs...");
- acc.write('hc2000c, 'h3);
+ acc.write('hc0100c, 'h3);
#500us;
- acc.read('hc40000, d);
+ acc.read('hc10000, d);
$display("TDC SDB ID : %x", d);
- acc.write('hc510a0, 1234); // set UTC
- acc.write('hc510fc, 1<<9); // load UTC
+ acc.write('hc120a0, 1234); // set UTC
+ acc.write('hc120fc, 1<<9); // load UTC
- acc.write('hc52004, 'hf); // enable EIC irq
+ acc.write('hc13004, 'hf); // enable EIC irq
- acc.write('hc51084, 'h1f); // enable all ACAM inputs
- acc.write('hc510fc, (1<<0)); // start acquisition
+ acc.write('hc12084, 'h1f); // enable all ACAM inputs
+ acc.write('hc120fc, (1<<0)); // start acquisition
+
+ acc.write('hc120fc, (1<<0)); // start acquisition
+ acc.write('hc12090, 2); // thr = 2 ts
+ acc.write('hc12094, 10); // thr = 10 ms
+
+
-
#300us;
- forever begin
- tdc_pulse <= 1;
- #1000ns;
- tdc_pulse <= 0;
- #10ns;
- end
+ fork
+ forever begin
+ acc.read('hc15000 + `ADDR_TSF_LTSCTL, d);
+ if(d&1) begin
+ uint64_t t0,t1,t2,t3;
+
+ acc.write('hc15000 + `ADDR_TSF_LTSCTL, 0);
+ acc.read('hc15000 + `ADDR_TSF_LTS0, t0);
+ acc.read('hc15000 + `ADDR_TSF_LTS1, t1);
+ acc.read('hc15000 + `ADDR_TSF_LTS2, t2);
+ acc.read('hc15000 + `ADDR_TSF_LTS3, t3);
+
+ $display("Last: %08x %08x %08x %08x",t0,t1,t2,t3);
+
+ end
+
+
+
+ end
+
+
+ forever begin
+ $display("Pulse!");
+
+ ACAM.pulse(0, 0);
+ ACAM.pulse(1, 0);
+ ACAM.pulse(2, 0);
+ #10us;
+ end
+ join
+
diff --git a/hdl/testbench/svec/wave.do b/hdl/testbench/svec/wave.do
index f4cc133292b614d13f2c7f590f6d4072ed7f3c39..8d6ffe3c7cab1bc9fed3166212768f3055ed7962 100644
--- a/hdl/testbench/svec/wave.do
+++ b/hdl/testbench/svec/wave.do
@@ -18,697 +18,225 @@ add wave -noupdate -expand -group VME /main/VME/irq_n
add wave -noupdate -expand -group VME /main/VME/iackin_n
add wave -noupdate -expand -group VME /main/VME/iackout_n
add wave -noupdate -expand -group VME /main/VME/iack_n
-add wave -noupdate -group Top /main/DUT/por_n_i
-add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_i
-add wave -noupdate -group Top /main/DUT/clk_125m_pllref_p_i
-add wave -noupdate -group Top /main/DUT/clk_125m_pllref_n_i
-add wave -noupdate -group Top /main/DUT/clk_125m_gtp_p_i
-add wave -noupdate -group Top /main/DUT/clk_125m_gtp_n_i
-add wave -noupdate -group Top /main/DUT/sfp_txp_o
-add wave -noupdate -group Top /main/DUT/sfp_txn_o
-add wave -noupdate -group Top /main/DUT/sfp_rxp_i
-add wave -noupdate -group Top /main/DUT/sfp_rxn_i
-add wave -noupdate -group Top /main/DUT/sfp_mod_def0_b
-add wave -noupdate -group Top /main/DUT/sfp_mod_def1_b
-add wave -noupdate -group Top /main/DUT/sfp_mod_def2_b
-add wave -noupdate -group Top /main/DUT/sfp_rate_select_b
-add wave -noupdate -group Top /main/DUT/sfp_tx_fault_i
-add wave -noupdate -group Top /main/DUT/sfp_tx_disable_o
-add wave -noupdate -group Top /main/DUT/sfp_los_i
-add wave -noupdate -group Top /main/DUT/pll20dac_din_o
-add wave -noupdate -group Top /main/DUT/pll20dac_sclk_o
-add wave -noupdate -group Top /main/DUT/pll20dac_sync_n_o
-add wave -noupdate -group Top /main/DUT/pll25dac_din_o
-add wave -noupdate -group Top /main/DUT/pll25dac_sclk_o
-add wave -noupdate -group Top /main/DUT/pll25dac_sync_n_o
-add wave -noupdate -group Top /main/DUT/uart_rxd_i
-add wave -noupdate -group Top /main/DUT/uart_txd_o
-add wave -noupdate -group Top /main/DUT/carrier_onewire_b
-add wave -noupdate -group Top /main/DUT/pcb_ver_i
-add wave -noupdate -group Top /main/DUT/tdc1_prsntm2c_n_i
-add wave -noupdate -group Top /main/DUT/tdc2_prsntm2c_n_i
-add wave -noupdate -group Top /main/DUT/fp_led_line_oen_o
-add wave -noupdate -group Top /main/DUT/fp_led_line_o
-add wave -noupdate -group Top /main/DUT/fp_led_column_o
-add wave -noupdate -group Top /main/DUT/VME_AS_n_i
-add wave -noupdate -group Top /main/DUT/VME_RST_n_i
-add wave -noupdate -group Top /main/DUT/VME_WRITE_n_i
-add wave -noupdate -group Top /main/DUT/VME_AM_i
-add wave -noupdate -group Top /main/DUT/VME_DS_n_i
-add wave -noupdate -group Top /main/DUT/VME_GA_i
-add wave -noupdate -group Top /main/DUT/VME_BERR_o
-add wave -noupdate -group Top /main/DUT/VME_DTACK_n_o
-add wave -noupdate -group Top /main/DUT/VME_RETRY_n_o
-add wave -noupdate -group Top /main/DUT/VME_RETRY_OE_o
-add wave -noupdate -group Top /main/DUT/VME_LWORD_n_b
-add wave -noupdate -group Top /main/DUT/VME_ADDR_b
-add wave -noupdate -group Top /main/DUT/VME_DATA_b
-add wave -noupdate -group Top /main/DUT/VME_BBSY_n_i
-add wave -noupdate -group Top /main/DUT/VME_IRQ_n_o
-add wave -noupdate -group Top /main/DUT/VME_IACK_n_i
-add wave -noupdate -group Top /main/DUT/VME_IACKIN_n_i
-add wave -noupdate -group Top /main/DUT/VME_IACKOUT_n_o
-add wave -noupdate -group Top /main/DUT/VME_DTACK_OE_o
-add wave -noupdate -group Top /main/DUT/VME_DATA_DIR_o
-add wave -noupdate -group Top /main/DUT/VME_DATA_OE_N_o
-add wave -noupdate -group Top /main/DUT/VME_ADDR_DIR_o
-add wave -noupdate -group Top /main/DUT/VME_ADDR_OE_N_o
-add wave -noupdate -group Top /main/DUT/tdc1_pll_sclk_o
-add wave -noupdate -group Top /main/DUT/tdc1_pll_sdi_o
-add wave -noupdate -group Top /main/DUT/tdc1_pll_cs_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_pll_dac_sync_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_pll_sdo_i
-add wave -noupdate -group Top /main/DUT/tdc1_pll_status_i
-add wave -noupdate -group Top /main/DUT/tdc1_125m_clk_p_i
-add wave -noupdate -group Top /main/DUT/tdc1_125m_clk_n_i
-add wave -noupdate -group Top /main/DUT/tdc1_acam_refclk_p_i
-add wave -noupdate -group Top /main/DUT/tdc1_acam_refclk_n_i
-add wave -noupdate -group Top /main/DUT/tdc1_start_from_fpga_o
-add wave -noupdate -group Top /main/DUT/tdc1_err_flag_i
-add wave -noupdate -group Top /main/DUT/tdc1_int_flag_i
-add wave -noupdate -group Top /main/DUT/tdc1_start_dis_o
-add wave -noupdate -group Top /main/DUT/tdc1_stop_dis_o
-add wave -noupdate -group Top /main/DUT/tdc1_data_bus_io
-add wave -noupdate -group Top /main/DUT/tdc1_address_o
-add wave -noupdate -group Top /main/DUT/tdc1_cs_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_oe_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_rd_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_wr_n_o
-add wave -noupdate -group Top /main/DUT/tdc1_ef1_i
-add wave -noupdate -group Top /main/DUT/tdc1_ef2_i
-add wave -noupdate -group Top /main/DUT/tdc1_enable_inputs_o
-add wave -noupdate -group Top /main/DUT/tdc1_term_en_1_o
-add wave -noupdate -group Top /main/DUT/tdc1_term_en_2_o
-add wave -noupdate -group Top /main/DUT/tdc1_term_en_3_o
-add wave -noupdate -group Top /main/DUT/tdc1_term_en_4_o
-add wave -noupdate -group Top /main/DUT/tdc1_term_en_5_o
-add wave -noupdate -group Top /main/DUT/tdc1_onewire_b
-add wave -noupdate -group Top /main/DUT/tdc1_scl_b
-add wave -noupdate -group Top /main/DUT/tdc1_sda_b
-add wave -noupdate -group Top /main/DUT/tdc1_led_status_o
-add wave -noupdate -group Top /main/DUT/tdc1_led_trig1_o
-add wave -noupdate -group Top /main/DUT/tdc1_led_trig2_o
-add wave -noupdate -group Top /main/DUT/tdc1_led_trig3_o
-add wave -noupdate -group Top /main/DUT/tdc1_led_trig4_o
-add wave -noupdate -group Top /main/DUT/tdc1_led_trig5_o
-add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_1_i
-add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_2_i
-add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_3_i
-add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_4_i
-add wave -noupdate -group Top /main/DUT/tdc1_in_fpga_5_i
-add wave -noupdate -group Top /main/DUT/tdc2_pll_sclk_o
-add wave -noupdate -group Top /main/DUT/tdc2_pll_sdi_o
-add wave -noupdate -group Top /main/DUT/tdc2_pll_cs_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_pll_dac_sync_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_pll_sdo_i
-add wave -noupdate -group Top /main/DUT/tdc2_pll_status_i
-add wave -noupdate -group Top /main/DUT/tdc2_125m_clk_p_i
-add wave -noupdate -group Top /main/DUT/tdc2_125m_clk_n_i
-add wave -noupdate -group Top /main/DUT/tdc2_acam_refclk_p_i
-add wave -noupdate -group Top /main/DUT/tdc2_acam_refclk_n_i
-add wave -noupdate -group Top /main/DUT/tdc2_start_from_fpga_o
-add wave -noupdate -group Top /main/DUT/tdc2_err_flag_i
-add wave -noupdate -group Top /main/DUT/tdc2_int_flag_i
-add wave -noupdate -group Top /main/DUT/tdc2_start_dis_o
-add wave -noupdate -group Top /main/DUT/tdc2_stop_dis_o
-add wave -noupdate -group Top /main/DUT/tdc2_data_bus_io
-add wave -noupdate -group Top /main/DUT/tdc2_address_o
-add wave -noupdate -group Top /main/DUT/tdc2_cs_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_oe_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_rd_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_wr_n_o
-add wave -noupdate -group Top /main/DUT/tdc2_ef1_i
-add wave -noupdate -group Top /main/DUT/tdc2_ef2_i
-add wave -noupdate -group Top /main/DUT/tdc2_enable_inputs_o
-add wave -noupdate -group Top /main/DUT/tdc2_term_en_1_o
-add wave -noupdate -group Top /main/DUT/tdc2_term_en_2_o
-add wave -noupdate -group Top /main/DUT/tdc2_term_en_3_o
-add wave -noupdate -group Top /main/DUT/tdc2_term_en_4_o
-add wave -noupdate -group Top /main/DUT/tdc2_term_en_5_o
-add wave -noupdate -group Top /main/DUT/tdc2_onewire_b
-add wave -noupdate -group Top /main/DUT/tdc2_scl_b
-add wave -noupdate -group Top /main/DUT/tdc2_sda_b
-add wave -noupdate -group Top /main/DUT/tdc2_led_status_o
-add wave -noupdate -group Top /main/DUT/tdc2_led_trig1_o
-add wave -noupdate -group Top /main/DUT/tdc2_led_trig2_o
-add wave -noupdate -group Top /main/DUT/tdc2_led_trig3_o
-add wave -noupdate -group Top /main/DUT/tdc2_led_trig4_o
-add wave -noupdate -group Top /main/DUT/tdc2_led_trig5_o
-add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_1_i
-add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_2_i
-add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_3_i
-add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_4_i
-add wave -noupdate -group Top /main/DUT/tdc2_in_fpga_5_i
-add wave -noupdate -group Top /main/DUT/clk_20m_vcxo_buf
-add wave -noupdate -group Top /main/DUT/clk_20m_vcxo
-add wave -noupdate -group Top /main/DUT/clk_62m5_sys
-add wave -noupdate -group Top /main/DUT/pllout_clk_sys
-add wave -noupdate -group Top /main/DUT/pllout_clk_sys_fb
-add wave -noupdate -group Top /main/DUT/sys_locked
-add wave -noupdate -group Top /main/DUT/tdc1_125m_clk
-add wave -noupdate -group Top /main/DUT/tdc1_send_dac_word_p
-add wave -noupdate -group Top /main/DUT/tdc1_dac_word
-add wave -noupdate -group Top /main/DUT/tdc2_125m_clk
-add wave -noupdate -group Top /main/DUT/tdc2_send_dac_word_p
-add wave -noupdate -group Top /main/DUT/tdc2_dac_word
-add wave -noupdate -group Top /main/DUT/pllout_clk_dmtd
-add wave -noupdate -group Top /main/DUT/pllout_clk_fb_dmtd
-add wave -noupdate -group Top /main/DUT/pllout_clk_fb_pllref
-add wave -noupdate -group Top /main/DUT/clk_125m_pllref
-add wave -noupdate -group Top /main/DUT/clk_125m_gtp
-add wave -noupdate -group Top /main/DUT/clk_dmtd
-add wave -noupdate -group Top /main/DUT/por_rst_n_a
-add wave -noupdate -group Top /main/DUT/powerup_rst_cnt
-add wave -noupdate -group Top /main/DUT/rst_n_sys
-add wave -noupdate -group Top /main/DUT/tdc1_soft_rst_n
-add wave -noupdate -group Top /main/DUT/tdc2_soft_rst_n
-add wave -noupdate -group Top /main/DUT/carrier_info_fmc_rst
-add wave -noupdate -group Top /main/DUT/carrier_info_stat_reserv
-add wave -noupdate -group Top /main/DUT/VME_DATA_b_out
-add wave -noupdate -group Top /main/DUT/VME_ADDR_b_out
-add wave -noupdate -group Top /main/DUT/VME_LWORD_n_b_out
-add wave -noupdate -group Top /main/DUT/VME_DATA_DIR_int
-add wave -noupdate -group Top /main/DUT/VME_ADDR_DIR_int
-add wave -noupdate -group Top /main/DUT/tm_link_up
-add wave -noupdate -group Top /main/DUT/tm_time_valid
-add wave -noupdate -group Top /main/DUT/tm_utc
-add wave -noupdate -group Top /main/DUT/tm_cycles
-add wave -noupdate -group Top /main/DUT/tm_clk_aux_lock_en
-add wave -noupdate -group Top /main/DUT/tm_clk_aux_locked
-add wave -noupdate -group Top /main/DUT/tm_dac_value
-add wave -noupdate -group Top /main/DUT/tm_dac_wr_p
-add wave -noupdate -group Top /main/DUT/phy_tx_data
-add wave -noupdate -group Top /main/DUT/phy_rx_data
-add wave -noupdate -group Top /main/DUT/phy_tx_k
-add wave -noupdate -group Top /main/DUT/phy_tx_disparity
-add wave -noupdate -group Top /main/DUT/phy_rx_k
-add wave -noupdate -group Top /main/DUT/phy_tx_enc_err
-add wave -noupdate -group Top /main/DUT/phy_rx_rbclk
-add wave -noupdate -group Top /main/DUT/phy_rx_enc_err
-add wave -noupdate -group Top /main/DUT/phy_rst
-add wave -noupdate -group Top /main/DUT/phy_loopen
-add wave -noupdate -group Top /main/DUT/phy_rx_bitslide
-add wave -noupdate -group Top /main/DUT/dac_hpll_load_p1
-add wave -noupdate -group Top /main/DUT/dac_dpll_load_p1
-add wave -noupdate -group Top /main/DUT/dac_hpll_data
-add wave -noupdate -group Top /main/DUT/dac_dpll_data
-add wave -noupdate -group Top /main/DUT/wrc_scl_out
-add wave -noupdate -group Top /main/DUT/wrc_scl_in
-add wave -noupdate -group Top /main/DUT/wrc_sda_out
-add wave -noupdate -group Top /main/DUT/wrc_sda_in
-add wave -noupdate -group Top /main/DUT/sfp_scl_out
-add wave -noupdate -group Top /main/DUT/sfp_scl_in
-add wave -noupdate -group Top /main/DUT/sfp_sda_out
-add wave -noupdate -group Top /main/DUT/sfp_sda_in
-add wave -noupdate -group Top /main/DUT/wrc_owr_en
-add wave -noupdate -group Top /main/DUT/wrc_owr_in
-add wave -noupdate -group Top /main/DUT/cnx_master_out
-add wave -noupdate -group Top /main/DUT/cnx_master_in
-add wave -noupdate -group Top /main/DUT/cnx_slave_out
-add wave -noupdate -group Top /main/DUT/cnx_slave_in
-add wave -noupdate -group Top /main/DUT/irq_to_vmecore
-add wave -noupdate -group Top /main/DUT/tdc1_irq
-add wave -noupdate -group Top /main/DUT/tdc2_irq
-add wave -noupdate -group Top /main/DUT/tdc1_scl_oen
-add wave -noupdate -group Top /main/DUT/tdc1_scl_in
-add wave -noupdate -group Top /main/DUT/tdc1_sda_oen
-add wave -noupdate -group Top /main/DUT/tdc1_sda_in
-add wave -noupdate -group Top /main/DUT/tdc2_scl_oen
-add wave -noupdate -group Top /main/DUT/tdc2_scl_in
-add wave -noupdate -group Top /main/DUT/tdc2_sda_oen
-add wave -noupdate -group Top /main/DUT/tdc2_sda_in
-add wave -noupdate -group Top /main/DUT/carrier_owr_en
-add wave -noupdate -group Top /main/DUT/carrier_owr_i
-add wave -noupdate -group Top /main/DUT/led_state
-add wave -noupdate -group Top /main/DUT/tdc1_ef
-add wave -noupdate -group Top /main/DUT/tdc2_ef
-add wave -noupdate -group Top /main/DUT/led_tdc1_ef
-add wave -noupdate -group Top /main/DUT/led_tdc2_ef
-add wave -noupdate -group Top /main/DUT/led_vme_access
-add wave -noupdate -group Top /main/DUT/led_clk_62m5_divider
-add wave -noupdate -group Top /main/DUT/led_clk_62m5_aux
-add wave -noupdate -group Top /main/DUT/led_clk_62m5
-add wave -noupdate -group Top /main/DUT/wrabbit_led_red
-add wave -noupdate -group Top /main/DUT/wrabbit_led_green
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_sys_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_sys_n_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_n_a_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sclk_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdi_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_cs_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_dac_sync_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdo_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_status_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_clk_125m_p_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_clk_125m_n_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_p_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_n_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/start_from_fpga_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/err_flag_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/int_flag_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/start_dis_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/stop_dis_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/data_bus_io
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/address_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cs_n_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/oe_n_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rd_n_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/wr_n_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/ef1_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/ef2_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/enable_inputs_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_1_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_2_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_3_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_4_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/term_en_5_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_status_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig1_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig2_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig3_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig4_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_led_trig5_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_1_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_2_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_3_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_4_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_in_fpga_5_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_scl_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_sda_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_scl_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_sda_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/mezz_one_wire_b
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_link_up_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_time_valid_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_cycles_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_tai_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_aux_lock_en_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_aux_locked_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_clk_dmtd_locked_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_dac_value_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tm_dac_wr_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/slave_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/slave_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_slave_i
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_slave_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/irq_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_125m_tdc_o
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/clk_125m_mezz
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_125m_mezz_n
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/rst_125m_mezz
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/acam_refclk_r_edge_p
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/send_dac_word_p
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/dac_word
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sclk
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_sdi
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/pll_dac_sync
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/fmc_eic_irq
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/fmc_eic_irq_synch
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_scl_out
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_scl_oen
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_sda_out
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/tdc_sda_oen
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_timestamp
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/direct_timestamp_wr
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cnx_master_in
-add wave -noupdate -group Mezz1Wrapper /main/DUT/cmp_tdc_mezzanine_1/cnx_master_out
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/clk_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/rst_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/activate_acq_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/deactivate_acq_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_wr_config_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rst_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_config_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_status_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo1_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_ififo2_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_rdbk_start01_p_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef1_meta_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ef2_meta_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ack_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/start_from_fpga_i
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/state_active_p_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_dat_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo1_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_ififo2_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp1_ok_p_o
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_tstamp2_ok_p_o
-add wave -noupdate -group DataEngine1 -height 16 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/nxt_engine_st
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_cyc
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_stb
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_we
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_adr
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/config_adr_c
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/reset_word
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_reg4
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_full_p
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_en
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c_rst
-add wave -noupdate -group DataEngine1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_engine_block/time_c
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/clk_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_refclk_r_edge_p_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/utc_p_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/state_active_p_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/activate_acq_p_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/deactivate_acq_p_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_i
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_from_fpga_o
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/stop_dis_o
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_r_edge_p_o
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_errflag_f_edge_p_o
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p_o
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/int_flag_synch
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/err_flag_synch
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/acam_intflag_f_edge_p
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/start_pulse
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_utc
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/rst_n
-add wave -noupdate -group acam-timing1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_timing_block/wait_for_state_active
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/clk_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/rst_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/acam_refclk_r_edge_p_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/clk_period_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/load_utc_p_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/starting_utc_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/pulse_delay_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/local_utc
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/one_hz_p_pre
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/one_hz_p_post
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/onesec_counter_en
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_one_second_block/total_delay
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_sys_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wr_index_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dacapo_c_rst_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
-add wave -noupdate -group 1s-1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_tdc
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_sys_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_sys_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clk_tdc_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_tdc_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/slave_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_rdbk_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo1_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_ififo2_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_start01_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wr_index_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/local_utc_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/core_status_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_code_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_status_reg_i
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/activate_acq_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_acq_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_wr_config_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_config_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rst_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_status_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo1_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_ififo2_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_rdbk_start01_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dacapo_c_rst_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/load_utc_p_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase_o
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/starting_utc
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_inputs_en
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/start_phase
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ctrl_reg
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/one_hz_phase
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_time_threshold
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/clear_ctrl_reg
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/send_dac_word_p
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_en
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/pulse_extender_c
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/deactivate_chan
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe0
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/ack_out_pipe1
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb0
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb1
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb2
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_comb3
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe0
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe1
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe2
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dat_out_pipe3
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/cyc_in_progress
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_in
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wb_out
-add wave -noupdate -expand -group Regs1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reg_control_block/rst_n_tdc
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/clk_tdc_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/clk_sys_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/rst_n_sys_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_rst_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_stb_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_cyc_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_we_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_adr_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_dat_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_rst_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_stb_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_cyc_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_we_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_adr_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_dat_i
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_ack_p_o
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_dat_o
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_ack_o
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_dat_o
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tdc_mem_wb_stall_o
-add wave -noupdate -expand -group CircBuf1 -height 16 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_rd_wb_st
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/nxt_tstamp_rd_wb_st
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_ack_p
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_rd_we
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/tstamp_wr_we
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/mb_data
-add wave -noupdate -expand -group CircBuf1 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/adr_d0
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_p_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_p_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_acam_err_p_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/mem_slave_i
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/mem_slave_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/direct_timestamp_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/direct_timestamp_stb_o
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clear_dacapo_counter
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_index
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tstamp_wr_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_adr
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_stb
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_cyc
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_we
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_ack
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_data_wr
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/circ_buff_class_data_rd
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/CONTROL
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/CLK
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG0
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG1
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG2
-add wave -noupdate -group TDC1Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/TRIG3
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/clk_sys_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/rst_sys_n_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/clk_tdc_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/rst_tdc_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/acam_refclk_r_edge_p_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/send_dac_word_p_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/dac_word_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/start_from_fpga_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/err_flag_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/int_flag_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/start_dis_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/stop_dis_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/data_bus_io
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/address_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cs_n_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/oe_n_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/rd_n_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wr_n_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/ef1_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/ef2_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/enable_inputs_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/term_en_1_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/term_en_2_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/term_en_3_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/term_en_4_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/term_en_5_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_status_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_trig1_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_trig2_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_trig3_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_trig4_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_led_trig5_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_in_fpga_1_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_in_fpga_2_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_in_fpga_3_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_in_fpga_4_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_in_fpga_5_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_link_up_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_time_valid_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_cycles_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_utc_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_dac_value_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_dac_wr_p_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/slave_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/slave_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wb_irq_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_scl_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_scl_oen_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_scl_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_sda_oen_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_sda_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/i2c_sda_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/onewire_b
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/direct_timestamp_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/direct_timestamp_stb_o
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/general_rst_n
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/rst_ref_0_n
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cnx_master_out
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cnx_master_in
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_core_wb_adr
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tdc_mem_wb_adr
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/mezz_owr_en
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/mezz_owr_i
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_scl_in
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_scl_out
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_scl_oe_n
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_sda_in
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_sda_out
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/sys_sda_oe_n
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_tstamp
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/reg_to_wr
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/reg_from_wr
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_utc_p
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/wrabbit_synched
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_channel
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/timestamp
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/timestamp_stb
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/channel_enable
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_threshold
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/irq_timeout
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/tick_1ms
+add wave -noupdate -group Mezzanine /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/counter_1ms
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
+add wave -noupdate -group Fifo0 /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/address_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef1_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/ef2_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_adr
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_stb
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_we
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_ack
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/read_start01
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/reset_acam
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/load_utc
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/window_delay
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_period
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/starting_utc
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_start01
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/state_active_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc_p
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/utc
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_channel
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/rst_sys
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
+add wave -noupdate -expand -group Core /main/DUT/cmp_tdc_mezzanine_1/cmp_tdc_mezz/cmp_tdc_core/timestamp
TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {943109721 ps} 0}
+WaveRestoreCursors {{Cursor 1} {936185162 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -723,4 +251,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
-WaveRestoreZoom {919925540 ps} {1035495170 ps}
+WaveRestoreZoom {890208852 ps} {1005778482 ps}