From 5765c94d3f0b118adcc9bfea880aca75ecef6001 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tomasz=20W=C5=82ostowski?= <tomasz.wlostowski@cern.ch>
Date: Tue, 19 May 2015 10:04:55 +0200
Subject: [PATCH] hdl: SPEC top level with refurbished TDC core
---
hdl/ip_cores/gn4124-core | 2 +-
hdl/ip_cores/vme64x-core | 2 +-
hdl/syn/spec/Manifest.py | 14 +
hdl/syn/spec/no_wrabbit/spec_tdc.par | 325 -
hdl/syn/spec/no_wrabbit/spec_tdc.twr | 1782 --
hdl/syn/spec/no_wrabbit/spec_tdc.xise | 1393 --
hdl/syn/spec/no_wrabbit/spec_tdc_map.map | 176 -
hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp | 973 -
hdl/syn/spec/no_wrabbit/wrc.ram | 19518 ----------------
hdl/syn/spec/with_wrabbit/wr_spec_tdc.par | 491 -
hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr | 4485 ----
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map | 222 -
hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp | 1042 -
hdl/syn/spec/with_wrabbit/wrc.ram | 19518 ----------------
.../spec/{with_wrabbit => }/wr_spec_tdc.xise | 1919 +-
.../spec_top_fmc_tdc/spec_top_fmc_tdc.xise | 1393 --
hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram | 19518 ----------------
.../{spec => spec.old}/acam_data_model.vhd | 0
.../{spec => spec.old}/acam_fifo_model.vhd | 0
.../{spec => spec.old}/acam_model.vhd | 0
.../{spec => spec.old}/acam_timing_model.vhd | 0
.../gnum_model/cmd_router.vhd | 0
.../gnum_model/cmd_router1.vhd | 0
.../gnum_model/gennum_tb.tar | Bin
.../gnum_model/gn412x_bfm.vhd | 0
.../gnum_model/mem_model.vhd | 0
.../gnum_model/textutil.vhd | 0
.../{spec => spec.old}/gnum_model/util.vhd | 0
.../{spec => spec.old}/start_stop_gen.vhd | 0
hdl/testbench/{spec => spec.old}/tb_tdc.vhd | 0
hdl/testbench/spec/Manifest.py | 13 +
hdl/testbench/spec/main.sv | 254 +
hdl/testbench/spec/run.do | 8 +
hdl/testbench/spec/wave.do | 565 +
hdl/testbench/spec/wrc-simulation.ram | 1000 +
hdl/testbench/svec/Manifest.py | 6 +-
hdl/top/spec/Manifest.py | 14 +
hdl/top/spec/build_wb.sh | 3 -
hdl/top/spec/spec_reset_gen.vhd | 55 -
hdl/top/spec/tdc_core_pkg.vhd | 1067 -
hdl/top/spec/wr_spec_tdc.ucf | 274 +-
hdl/top/spec/wr_spec_tdc.vhd | 1197 +-
hdl/top/svec/wr_svec_tdc.vhd | 55 +-
43 files changed, 3429 insertions(+), 73855 deletions(-)
create mode 100644 hdl/syn/spec/Manifest.py
delete mode 100644 hdl/syn/spec/no_wrabbit/spec_tdc.par
delete mode 100644 hdl/syn/spec/no_wrabbit/spec_tdc.twr
delete mode 100644 hdl/syn/spec/no_wrabbit/spec_tdc.xise
delete mode 100644 hdl/syn/spec/no_wrabbit/spec_tdc_map.map
delete mode 100644 hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp
delete mode 100644 hdl/syn/spec/no_wrabbit/wrc.ram
delete mode 100644 hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
delete mode 100644 hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
delete mode 100644 hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
delete mode 100644 hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp
delete mode 100644 hdl/syn/spec/with_wrabbit/wrc.ram
rename hdl/syn/spec/{with_wrabbit => }/wr_spec_tdc.xise (52%)
delete mode 100644 hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
delete mode 100644 hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram
rename hdl/testbench/{spec => spec.old}/acam_data_model.vhd (100%)
rename hdl/testbench/{spec => spec.old}/acam_fifo_model.vhd (100%)
rename hdl/testbench/{spec => spec.old}/acam_model.vhd (100%)
rename hdl/testbench/{spec => spec.old}/acam_timing_model.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/cmd_router.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/cmd_router1.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/gennum_tb.tar (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/gn412x_bfm.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/mem_model.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/textutil.vhd (100%)
rename hdl/testbench/{spec => spec.old}/gnum_model/util.vhd (100%)
rename hdl/testbench/{spec => spec.old}/start_stop_gen.vhd (100%)
rename hdl/testbench/{spec => spec.old}/tb_tdc.vhd (100%)
create mode 100644 hdl/testbench/spec/Manifest.py
create mode 100644 hdl/testbench/spec/main.sv
create mode 100644 hdl/testbench/spec/run.do
create mode 100644 hdl/testbench/spec/wave.do
create mode 100644 hdl/testbench/spec/wrc-simulation.ram
create mode 100644 hdl/top/spec/Manifest.py
delete mode 100755 hdl/top/spec/build_wb.sh
delete mode 100644 hdl/top/spec/spec_reset_gen.vhd
delete mode 100644 hdl/top/spec/tdc_core_pkg.vhd
diff --git a/hdl/ip_cores/gn4124-core b/hdl/ip_cores/gn4124-core
index e0dcb3f..ffea547 160000
--- a/hdl/ip_cores/gn4124-core
+++ b/hdl/ip_cores/gn4124-core
@@ -1 +1 @@
-Subproject commit e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab
+Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
diff --git a/hdl/ip_cores/vme64x-core b/hdl/ip_cores/vme64x-core
index e98eb58..d8ae986 160000
--- a/hdl/ip_cores/vme64x-core
+++ b/hdl/ip_cores/vme64x-core
@@ -1 +1 @@
-Subproject commit e98eb58ca8757be8fdf4117d0d1d1c8bb2e238bc
+Subproject commit d8ae98675b15a5dc6bf5cc9e7e3fcbdd266187f7
diff --git a/hdl/syn/spec/Manifest.py b/hdl/syn/spec/Manifest.py
new file mode 100644
index 0000000..0fd9423
--- /dev/null
+++ b/hdl/syn/spec/Manifest.py
@@ -0,0 +1,14 @@
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_top = "wr_spec_tdc"
+syn_project = "wr_spec_tdc.xise"
+syn_tool = "ise"
+top_module = "wr_spec_tdc"
+
+modules = { "local" : [ "../../top/spec" ] }
diff --git a/hdl/syn/spec/no_wrabbit/spec_tdc.par b/hdl/syn/spec/no_wrabbit/spec_tdc.par
deleted file mode 100644
index be585c8..0000000
--- a/hdl/syn/spec/no_wrabbit/spec_tdc.par
+++ /dev/null
@@ -1,325 +0,0 @@
-Release 13.4 par O.87xd (nt)
-Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-
-PCBE13136:: Tue Jul 08 10:29:26 2014
-
-par -w -intstyle ise -ol high -xe c -mt off spec_tdc_map.ncd spec_tdc.ncd
-spec_tdc.pcf
-
-
-Constraints file: spec_tdc.pcf.
-Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
- "spec_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
-INFO:Par:338 -
- Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
- not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
- speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
- design even if the time specs can not be met. If you are looking for the best possible design speed available from a
- long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
- speed improvements have shrunk to the point that the time specs are not expected to be met.
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version: "PRODUCTION 1.21 2012-01-07".
-
-
-
-Device Utilization Summary:
-
-Slice Logic Utilization:
- Number of Slice Registers: 3,584 out of 54,576 6%
- Number used as Flip Flops: 3,559
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 23
- Number of Slice LUTs: 3,881 out of 27,288 14%
- Number used as logic: 3,781 out of 27,288 13%
- Number using O6 output only: 2,251
- Number using O5 output only: 328
- Number using O5 and O6: 1,202
- Number used as ROM: 0
- Number used as Memory: 2 out of 6,408 1%
- Number used as Dual Port RAM: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 2
- Number using O6 output only: 2
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used exclusively as route-thrus: 98
- Number with same-slice register load: 53
- Number with same-slice carry load: 45
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 1,510 out of 6,822 22%
- Nummber of MUXCYs used: 1,284 out of 13,644 9%
- Number of LUT Flip Flop pairs used: 4,827
- Number with an unused Flip Flop: 1,538 out of 4,827 31%
- Number with an unused LUT: 946 out of 4,827 19%
- Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
- Number of slice register sites lost
- to control set restrictions: 0 out of 54,576 0%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 134 out of 296 45%
- Number of LOCed IOBs: 134 out of 134 100%
- IOB Flip Flops: 55
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 11 out of 116 9%
- Number of RAMB8BWERs: 0 out of 232 0%
- Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
- Number used as BUFIO2s: 1
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 3 out of 16 18%
- Number used as BUFGs: 3
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
- Number used as ILOGIC2s: 40
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
- Number used as OLOGIC2s: 15
- Number used as OSERDES2s: 20
- Number of BSCANs: 0 out of 4 0%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 0 out of 58 0%
- Number of GTPA1_DUALs: 0 out of 2 0%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 1 out of 4 25%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-
-Overall effort level (-ol): High
-Router effort level (-rl): High
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
- Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis. REAL time: 11 secs
-Finished initial Timing Analysis. REAL time: 11 secs
-
-WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal p_wr_req_i<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
-Starting Router
-
-
-Phase 1 : 24084 unrouted; REAL time: 13 secs
-
-Phase 2 : 20731 unrouted; REAL time: 16 secs
-
-Phase 3 : 8906 unrouted; REAL time: 27 secs
-
-Phase 4 : 8912 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 30 secs
-
-Updating file: spec_tdc.ncd with current fully routed design.
-
-Phase 5 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 6 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 7 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 8 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 9 : 0 unrouted; (Setup:0, Hold:1608, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 47 secs
-
-Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
-Total REAL time to Router completion: 49 secs
-Total CPU time to Router completion: 46 secs
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-| clk_125m | BUFGMUX_X3Y7| No | 944 | 0.551 | 1.762 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/sys_ | | | | | |
-| clk | BUFGMUX_X3Y13| No | 235 | 0.518 | 1.729 |
-+---------------------+--------------+------+------+------------+-------------+
-|clk_20m_vcxo_buf_BUF | | | | | |
-| G | BUFGMUX_X2Y3| No | 26 | 0.519 | 1.737 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/io_c | | | | | |
-| lk | Local| | 41 | 0.064 | 1.562 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_tdc_mezz/cmp_tdc | | | | | |
-|_core/data_engine_bl | | | | | |
-|ock/engine_st[3]_PWR | | | | | |
-| _227_o_Mux_41_o | Local| | 2 | 0.000 | 0.469 |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-* The fanout is the number of component pins not the individual BEL loads,
-for example SLICE loads not FF loads.
-
-Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
-
-Number of Timing Constraints that were not applied: 8
-
-Asterisk (*) preceding a constraint indicates it was not met.
- This may be due to a setup or hold violation.
-
-----------------------------------------------------------------------------------------------------------
- Constraint | Check | Worst Case | Best Case | Timing | Timing
- | | Slack | Achievable | Errors | Score
-----------------------------------------------------------------------------------------------------------
- TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
- _clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.395ns| | 0| 0
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.248ns| 4.752ns| 0| 0
- 1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.043ns| | 0| 0
- core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
- S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
- PHASE 1.25 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
- PERIOD TIMEGRP "cmp_gn4124_core_ | | | | |
- cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH | | | | |
- 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
- = PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
- e_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i | | | | |
- HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
- 1 = PERIOD TIMEGRP "cmp_gn4124_co | | | | |
- re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
- p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
- 1.25 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
- p_i" 5 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
- n_i" 5 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
- clk_125m_p_i" 8 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | SETUP | 44.742ns| 5.258ns| 0| 0
- 0m_vcxo_i" 50 ns HIGH 50% | HOLD | 0.369ns| | 0| 0
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
- s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
- 4_core_cmp_clk_in_rx_pllout_xs_int" | | | | |
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl | | | | |
- k / 2 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
- s_int_0 = PERIOD TIMEGRP "cmp_gn4 | | | | |
- 124_core_cmp_clk_in_rx_pllout_xs_int_0" | | | | |
- TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
- P_clk_0 / 2 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Review Timing Report for more details on the following derived constraints.
-To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
-or "Run Timing Analysis" from Timing Analyzer (timingan).
-Derived Constraints for TS_p2l_clk_p_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_n_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.752ns| 0| 0| 0| 5842|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.752ns| 0| 0| 0| 5842|
-| buf_P_clk_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.752ns| N/A| 0| 0| 5842| 0|
-| _rx_pllout_x1_0 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-All constraints were met.
-INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
- constraint is not analyzed due to the following: No paths covered by this
- constraint; Other constraints intersect with this constraint; or This
- constraint was disabled by a Path Tracing Control. Please run the Timespec
- Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-
-Total REAL time to PAR completion: 53 secs
-Total CPU time to PAR completion: 48 secs
-
-Peak Memory Usage: 333 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - No errors found.
-
-Number of error messages: 0
-Number of warning messages: 7
-Number of info messages: 2
-
-Writing design to file spec_tdc.ncd
-
-
-
-PAR done!
diff --git a/hdl/syn/spec/no_wrabbit/spec_tdc.twr b/hdl/syn/spec/no_wrabbit/spec_tdc.twr
deleted file mode 100644
index fd42af7..0000000
--- a/hdl/syn/spec/no_wrabbit/spec_tdc.twr
+++ /dev/null
@@ -1,1782 +0,0 @@
---------------------------------------------------------------------------------
-Release 13.4 Trace (nt)
-Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-
-C:\EDA\Xilinx\v13_4\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s
-3 -n 3 -fastpaths -xml spec_tdc.twx spec_tdc.ncd -o spec_tdc.twr spec_tdc.pcf
-
-Design file: spec_tdc.ncd
-Physical constraint file: spec_tdc.pcf
-Device,package,speed: xc6slx45t,fgg484,C,-3 (PRODUCTION 1.21 2012-01-07)
-Report level: verbose report
-
-Environment Variable Effect
--------------------- ------
-NONE No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
- information, see the TSI report. Please consult the Xilinx Command Line
- Tools User Guide for information on generating a TSI report.
-INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
-
-================================================================================
-Timing constraint: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 869 paths analyzed, 297 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 5.258ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/pll_status_synch_0 (ILOGIC_X24Y0.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 44.742ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/pll_status_synch_0 (FF)
- Requirement: 50.000ns
- Data Path Delay: 5.650ns (Levels of Logic = 0)
- Clock Path Skew: 0.427ns (0.909 - 0.482)
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc_clks_rsts_mgment/pll_status_synch_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y45.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc_clks_rsts_mgment/rst_in_synch_1
- ILOGIC_X24Y0.SR net (fanout=24) 4.469 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- ILOGIC_X24Y0.CLK0 Tisrck 0.734 cmp_tdc_clks_rsts_mgment/pll_status_synch<0>
- cmp_tdc_clks_rsts_mgment/pll_status_synch_0
- ------------------------------------------------- ---------------------------
- Total 5.650ns (1.181ns logic, 4.469ns route)
- (20.9% logic, 79.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/dac_word_11 (SLICE_X31Y34.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 45.065ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/dac_word_11 (FF)
- Requirement: 50.000ns
- Data Path Delay: 4.888ns (Levels of Logic = 0)
- Clock Path Skew: -0.012ns (0.243 - 0.255)
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc_clks_rsts_mgment/dac_word_11
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y45.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc_clks_rsts_mgment/rst_in_synch_1
- SLICE_X31Y34.SR net (fanout=24) 4.016 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- SLICE_X31Y34.CLK Tsrck 0.425 cmp_tdc_clks_rsts_mgment/dac_word<11>
- cmp_tdc_clks_rsts_mgment/dac_word_11
- ------------------------------------------------- ---------------------------
- Total 4.888ns (0.872ns logic, 4.016ns route)
- (17.8% logic, 82.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/dac_word_10 (SLICE_X31Y34.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 45.068ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/dac_word_10 (FF)
- Requirement: 50.000ns
- Data Path Delay: 4.885ns (Levels of Logic = 0)
- Clock Path Skew: -0.012ns (0.243 - 0.255)
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 0.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/rst_in_synch_1 to cmp_tdc_clks_rsts_mgment/dac_word_10
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y45.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- cmp_tdc_clks_rsts_mgment/rst_in_synch_1
- SLICE_X31Y34.SR net (fanout=24) 4.016 cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
- SLICE_X31Y34.CLK Tsrck 0.422 cmp_tdc_clks_rsts_mgment/dac_word<11>
- cmp_tdc_clks_rsts_mgment/dac_word_10
- ------------------------------------------------- ---------------------------
- Total 4.885ns (0.869ns logic, 4.016ns route)
- (17.8% logic, 82.2% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/rst_cnt_7 (SLICE_X44Y34.CE), 9 paths
---------------------------------------------------------------------------------
-Slack (hold path): 0.369ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.369ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_7 to cmp_tdc_clks_rsts_mgment/rst_cnt_7
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.DQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- SLICE_X45Y34.C6 net (fanout=3) 0.029 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.108 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- ------------------------------------------------- ---------------------------
- Total 0.369ns (0.282ns logic, 0.087ns route)
- (76.4% logic, 23.6% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.592ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.592ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_6 to cmp_tdc_clks_rsts_mgment/rst_cnt_7
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.CQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- SLICE_X45Y34.C3 net (fanout=3) 0.252 cmp_tdc_clks_rsts_mgment/rst_cnt<6>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.108 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- ------------------------------------------------- ---------------------------
- Total 0.592ns (0.282ns logic, 0.310ns route)
- (47.6% logic, 52.4% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.691ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.691ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_5 to cmp_tdc_clks_rsts_mgment/rst_cnt_7
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.BQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- SLICE_X45Y34.C1 net (fanout=3) 0.351 cmp_tdc_clks_rsts_mgment/rst_cnt<5>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.108 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- ------------------------------------------------- ---------------------------
- Total 0.691ns (0.282ns logic, 0.409ns route)
- (40.8% logic, 59.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/rst_cnt_6 (SLICE_X44Y34.CE), 9 paths
---------------------------------------------------------------------------------
-Slack (hold path): 0.373ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.373ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_7 to cmp_tdc_clks_rsts_mgment/rst_cnt_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.DQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- SLICE_X45Y34.C6 net (fanout=3) 0.029 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.104 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- ------------------------------------------------- ---------------------------
- Total 0.373ns (0.286ns logic, 0.087ns route)
- (76.7% logic, 23.3% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.596ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.596ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_6 to cmp_tdc_clks_rsts_mgment/rst_cnt_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.CQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- SLICE_X45Y34.C3 net (fanout=3) 0.252 cmp_tdc_clks_rsts_mgment/rst_cnt<6>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.104 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- ------------------------------------------------- ---------------------------
- Total 0.596ns (0.286ns logic, 0.310ns route)
- (48.0% logic, 52.0% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.695ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.695ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_5 to cmp_tdc_clks_rsts_mgment/rst_cnt_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.BQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- SLICE_X45Y34.C1 net (fanout=3) 0.351 cmp_tdc_clks_rsts_mgment/rst_cnt<5>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.104 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- ------------------------------------------------- ---------------------------
- Total 0.695ns (0.286ns logic, 0.409ns route)
- (41.2% logic, 58.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/rst_cnt_5 (SLICE_X44Y34.CE), 9 paths
---------------------------------------------------------------------------------
-Slack (hold path): 0.375ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_7 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.375ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_7 to cmp_tdc_clks_rsts_mgment/rst_cnt_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.DQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_7
- SLICE_X45Y34.C6 net (fanout=3) 0.029 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.102 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- ------------------------------------------------- ---------------------------
- Total 0.375ns (0.288ns logic, 0.087ns route)
- (76.8% logic, 23.2% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.598ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_6 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.598ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_6 to cmp_tdc_clks_rsts_mgment/rst_cnt_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.CQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_6
- SLICE_X45Y34.C3 net (fanout=3) 0.252 cmp_tdc_clks_rsts_mgment/rst_cnt<6>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.102 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- ------------------------------------------------- ---------------------------
- Total 0.598ns (0.288ns logic, 0.310ns route)
- (48.2% logic, 51.8% route)
-
---------------------------------------------------------------------------------
-Slack (hold path): 0.697ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/rst_cnt_5 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.697ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Destination Clock: clk_20m_vcxo_buf_BUFG rising at 50.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clks_rsts_mgment/rst_cnt_5 to cmp_tdc_clks_rsts_mgment/rst_cnt_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y34.BQ Tcko 0.234 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- SLICE_X45Y34.C1 net (fanout=3) 0.351 cmp_tdc_clks_rsts_mgment/rst_cnt<5>
- SLICE_X45Y34.C Tilo 0.156 cmp_tdc_clks_rsts_mgment/rst
- cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CE net (fanout=2) 0.058 cmp_tdc_clks_rsts_mgment/_n0398_inv
- SLICE_X44Y34.CLK Tckce (-Th) 0.102 cmp_tdc_clks_rsts_mgment/rst_cnt<7>
- cmp_tdc_clks_rsts_mgment/rst_cnt_5
- ------------------------------------------------- ---------------------------
- Total 0.697ns (0.288ns logic, 0.409ns route)
- (41.3% logic, 58.7% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 48.270ns (period - min period limit)
- Period: 50.000ns
- Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
- Physical resource: clk_20m_vcxo_buf_BUFG/I0
- Logical resource: clk_20m_vcxo_buf_BUFG/I0
- Location pin: BUFGMUX_X2Y3.I0
- Clock network: clk_20m_vcxo_buf
---------------------------------------------------------------------------------
-Slack: 48.940ns (period - (min high pulse limit / (high pulse / period)))
- Period: 50.000ns
- High pulse: 25.000ns
- High pulse limit: 0.530ns (Tispwh)
- Physical resource: cmp_tdc_clks_rsts_mgment/pll_status_synch<0>/SR
- Logical resource: cmp_tdc_clks_rsts_mgment/pll_status_synch_0/SR
- Location pin: ILOGIC_X24Y0.SR
- Clock network: cmp_tdc_clks_rsts_mgment/rst_in_synch<1>
---------------------------------------------------------------------------------
-Slack: 48.941ns (period - min period limit)
- Period: 50.000ns
- Min period limit: 1.059ns (944.287MHz) (Tickper)
- Physical resource: cmp_tdc_clks_rsts_mgment/pll_status_synch<0>/CLK0
- Logical resource: cmp_tdc_clks_rsts_mgment/pll_status_synch_0/CLK0
- Location pin: ILOGIC_X24Y0.CLK0
- Clock network: clk_20m_vcxo_buf_BUFG
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_clk_125m_p_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.124ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_clk_125m_p_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X1Y8.CLKA
- Clock network: clk_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X1Y8.CLKB
- Clock network: clk_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y6.CLKA
- Clock network: clk_125m
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 386083 paths analyzed, 13172 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.949ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12 (SLICE_X15Y8.D1), 2311 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.051ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.898ns (Levels of Logic = 6)
- Clock Path Skew: -0.016ns (0.231 - 0.247)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y8.DMUX Tshcko 0.461 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb<3>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4
- SLICE_X22Y10.B3 net (fanout=5) 1.445 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb<4>
- SLICE_X22Y10.B Tilo 0.203 N348
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i_GND_606_o_AND_1805_o_SW0
- SLICE_X22Y10.D1 net (fanout=4) 0.493 N186
- SLICE_X22Y10.D Tilo 0.203 N348
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i_GND_606_o_AND_1805_o_SW1
- SLICE_X22Y13.B3 net (fanout=9) 0.729 N348
- SLICE_X22Y13.B Tilo 0.203 N496
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<10>_SW1_SW1
- SLICE_X26Y14.C4 net (fanout=1) 0.698 N496
- SLICE_X26Y14.CMUX Topcc 0.396 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.D1 net (fanout=18) 1.688 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT31
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- ------------------------------------------------- ---------------------------
- Total 7.898ns (2.047ns logic, 5.851ns route)
- (25.9% logic, 74.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.079ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.872ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.231 - 0.245)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y8.AQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<7>
- cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4
- SLICE_X20Y9.A1 net (fanout=7) 1.240 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<4>
- SLICE_X20Y9.COUT Topcya 0.395 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_lut<4>_INV_0
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.COUT Tbyp 0.076 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CMUX Tcinc 0.272 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- SLICE_X18Y12.D3 net (fanout=3) 0.522 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/GND_606_o_GND_606_o_sub_57_OUT<14>
- SLICE_X18Y12.D Tilo 0.203 N303
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>_SW1
- SLICE_X26Y13.D1 net (fanout=1) 1.135 N303
- SLICE_X26Y13.COUT Topcyd 0.261 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CMUX Tcinc 0.284 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.D1 net (fanout=18) 1.688 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT31
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- ------------------------------------------------- ---------------------------
- Total 7.872ns (2.480ns logic, 5.392ns route)
- (31.5% logic, 68.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.085ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.866ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.231 - 0.245)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y8.AQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<7>
- cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4
- SLICE_X20Y9.A1 net (fanout=7) 1.240 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<4>
- SLICE_X20Y9.COUT Topcya 0.395 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_lut<4>_INV_0
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.COUT Tbyp 0.076 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.DMUX Tcind 0.272 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- SLICE_X18Y12.D4 net (fanout=3) 0.516 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/GND_606_o_GND_606_o_sub_57_OUT<15>
- SLICE_X18Y12.D Tilo 0.203 N303
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>_SW1
- SLICE_X26Y13.D1 net (fanout=1) 1.135 N303
- SLICE_X26Y13.COUT Topcyd 0.261 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CMUX Tcinc 0.284 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.D1 net (fanout=18) 1.688 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT31
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_12
- ------------------------------------------------- ---------------------------
- Total 7.866ns (2.480ns logic, 5.386ns route)
- (31.5% logic, 68.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8 (SLICE_X15Y8.A2), 2311 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.076ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.873ns (Levels of Logic = 6)
- Clock Path Skew: -0.016ns (0.231 - 0.247)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y8.DMUX Tshcko 0.461 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb<3>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb_4
- SLICE_X22Y10.B3 net (fanout=5) 1.445 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/acam_start_nb<4>
- SLICE_X22Y10.B Tilo 0.203 N348
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i_GND_606_o_AND_1805_o_SW0
- SLICE_X22Y10.D1 net (fanout=4) 0.493 N186
- SLICE_X22Y10.D Tilo 0.203 N348
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/roll_over_incr_recent_i_GND_606_o_AND_1805_o_SW1
- SLICE_X22Y13.B3 net (fanout=9) 0.729 N348
- SLICE_X22Y13.B Tilo 0.203 N496
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<10>_SW1_SW1
- SLICE_X26Y14.C4 net (fanout=1) 0.698 N496
- SLICE_X26Y14.CMUX Topcc 0.396 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.A2 net (fanout=18) 1.663 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT171
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- ------------------------------------------------- ---------------------------
- Total 7.873ns (2.047ns logic, 5.826ns route)
- (26.0% logic, 74.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.104ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.847ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.231 - 0.245)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y8.AQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<7>
- cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4
- SLICE_X20Y9.A1 net (fanout=7) 1.240 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<4>
- SLICE_X20Y9.COUT Topcya 0.395 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_lut<4>_INV_0
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.COUT Tbyp 0.076 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CMUX Tcinc 0.272 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- SLICE_X18Y12.D3 net (fanout=3) 0.522 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/GND_606_o_GND_606_o_sub_57_OUT<14>
- SLICE_X18Y12.D Tilo 0.203 N303
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>_SW1
- SLICE_X26Y13.D1 net (fanout=1) 1.135 N303
- SLICE_X26Y13.COUT Topcyd 0.261 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CMUX Tcinc 0.284 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.A2 net (fanout=18) 1.663 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT171
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- ------------------------------------------------- ---------------------------
- Total 7.847ns (2.480ns logic, 5.367ns route)
- (31.6% logic, 68.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.110ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.841ns (Levels of Logic = 8)
- Clock Path Skew: -0.014ns (0.231 - 0.245)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y8.AQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<7>
- cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_4
- SLICE_X20Y9.A1 net (fanout=7) 1.240 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<4>
- SLICE_X20Y9.COUT Topcya 0.395 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_lut<4>_INV_0
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<7>
- SLICE_X20Y10.COUT Tbyp 0.076 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<11>
- SLICE_X20Y11.DMUX Tcind 0.272 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Msub_GND_606_o_GND_606_o_sub_57_OUT<23:0>_cy<15>
- SLICE_X18Y12.D4 net (fanout=3) 0.516 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/GND_606_o_GND_606_o_sub_57_OUT<15>
- SLICE_X18Y12.D Tilo 0.203 N303
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>_SW1
- SLICE_X26Y13.D1 net (fanout=1) 1.135 N303
- SLICE_X26Y13.COUT Topcyd 0.261 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_lut<7>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CIN net (fanout=1) 0.003 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<7>
- SLICE_X26Y14.CMUX Tcinc 0.284 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mcompar_un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o_cy<10>
- SLICE_X23Y10.A6 net (fanout=65) 0.798 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_current_retrig_nb_offset[31]_equal_60_o
- SLICE_X23Y10.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<10>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o16_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy_cy
- SLICE_X15Y8.A2 net (fanout=18) 1.663 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_acam_start_nb[31]_un_acam_start_nb[31]_OR_1036_o
- SLICE_X15Y8.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over<12>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Mmux_roll_over_nb_i[23]_un_previous_roll_over_nb[23]_mux_70_OUT171
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_retrig_from_roll_over_8
- ------------------------------------------------- ---------------------------
- Total 7.841ns (2.480ns logic, 5.361ns route)
- (31.6% logic, 68.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (SLICE_X3Y31.A4), 362 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.105ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1_1 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.845ns (Levels of Logic = 6)
- Clock Path Skew: -0.015ns (0.486 - 0.501)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1_1 to cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X6Y36.AQ Tcko 0.447 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1_1
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1_1
- SLICE_X5Y34.B2 net (fanout=3) 1.191 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1_1
- SLICE_X5Y34.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_config_rdbk_5<31>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0786<7>11
- SLICE_X6Y34.C1 net (fanout=66) 0.709 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0786<7>1
- SLICE_X6Y34.C Tilo 0.204 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_3_2
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20423211
- SLICE_X5Y37.D1 net (fanout=6) 0.912 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out2042321
- SLICE_X5Y37.D Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20413
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20413
- SLICE_X3Y38.A3 net (fanout=1) 0.820 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20413
- SLICE_X3Y38.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20418
- SLICE_X3Y31.B3 net (fanout=1) 1.127 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20418
- SLICE_X3Y31.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.A4 net (fanout=1) 1.077 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20426
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- ------------------------------------------------- ---------------------------
- Total 7.845ns (2.009ns logic, 5.836ns route)
- (25.6% logic, 74.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.280ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.665ns (Levels of Logic = 6)
- Clock Path Skew: -0.020ns (0.486 - 0.506)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1 to cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X6Y33.BQ Tcko 0.447 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0<2>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_1
- SLICE_X9Y39.B1 net (fanout=180) 1.654 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0<1>
- SLICE_X9Y39.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_7_1
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0579<7>21
- SLICE_X4Y39.C2 net (fanout=1) 0.869 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0579<7>2
- SLICE_X4Y39.C Tilo 0.205 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out2042171
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20421711
- SLICE_X3Y38.B5 net (fanout=6) 0.741 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out2042171
- SLICE_X3Y38.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- SLICE_X3Y38.A5 net (fanout=1) 0.187 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- SLICE_X3Y38.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20417
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20418
- SLICE_X3Y31.B3 net (fanout=1) 1.127 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20418
- SLICE_X3Y31.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.A4 net (fanout=1) 1.077 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20426
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- ------------------------------------------------- ---------------------------
- Total 7.665ns (2.010ns logic, 5.655ns route)
- (26.2% logic, 73.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.407ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.543ns (Levels of Logic = 5)
- Clock Path Skew: -0.015ns (0.486 - 0.501)
- Source Clock: clk_125m rising at 0.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5 to cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X7Y36.BQ Tcko 0.391 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0<7>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_5
- SLICE_X7Y38.A5 net (fanout=21) 0.740 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0<5>
- SLICE_X7Y38.A Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/reg_adr_pipe0_6_1
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0570<7>11_1
- SLICE_X10Y39.A2 net (fanout=9) 1.094 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/_n0570<7>11
- SLICE_X10Y39.A Tilo 0.203 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/acam_config_3<15>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out11111
- SLICE_X13Y31.B4 net (fanout=32) 1.514 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out1111
- SLICE_X13Y31.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/irq_tstamp_threshold<29>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out2049
- SLICE_X3Y31.B5 net (fanout=1) 1.425 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20410
- SLICE_X3Y31.B Tilo 0.259 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.A4 net (fanout=1) 1.077 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20419
- SLICE_X3Y31.CLK Tas 0.322 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o<25>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/Mmux_dat_out20426
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/tdc_config_wb_dat_o_24
- ------------------------------------------------- ---------------------------
- Total 7.543ns (1.693ns logic, 5.850ns route)
- (22.4% logic, 77.6% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_x_2 (SLICE_X41Y61.CX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.395ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_xm_2 (FF)
- Destination: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_x_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.397ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.042 - 0.040)
- Source Clock: clk_125m rising at 8.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_xm_2 to cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_x_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X40Y61.CQ Tcko 0.200 cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_xm<3>
- cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_xm_2
- SLICE_X41Y61.CX net (fanout=1) 0.138 cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_xm<2>
- SLICE_X41Y61.CLK Tckdi (-Th) -0.059 cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_x<3>
- cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/rcb_gray_x_2
- ------------------------------------------------- ---------------------------
- Total 0.397ns (0.259ns logic, 0.138ns route)
- (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2 (SLICE_X20Y43.B5), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.399ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1 (FF)
- Destination: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.399ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m rising at 8.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1 to cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X20Y43.BQ Tcko 0.200 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_1
- SLICE_X20Y43.B5 net (fanout=5) 0.078 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
- SLICE_X20Y43.CLK Tah (-Th) -0.121 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt<1>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/Mmux_dcnt[2]_GND_675_o_mux_8_OUT31
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/byte_ctrl/dcnt_2
- ------------------------------------------------- ---------------------------
- Total 0.399ns (0.321ns logic, 0.078ns route)
- (80.5% logic, 19.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_16 (SLICE_X17Y11.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.401ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_16 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_16 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.403ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.040 - 0.038)
- Source Clock: clk_125m rising at 8.000ns
- Destination Clock: clk_125m rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_16 to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_16
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y11.AQ Tcko 0.200 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<19>
- cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c_16
- SLICE_X17Y11.AX net (fanout=7) 0.144 cmp_tdc_mezz/cmp_tdc_core/start_retrigger_block/roll_over_c<16>
- SLICE_X17Y11.CLK Tckdi (-Th) -0.059 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb<17>
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/un_previous_roll_over_nb_16
- ------------------------------------------------- ---------------------------
- Total 0.403ns (0.259ns logic, 0.144ns route)
- (64.3% logic, 35.7% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X1Y8.CLKA
- Clock network: clk_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB)
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKB
- Location pin: RAMB16_X1Y8.CLKB
- Clock network: clk_125m
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y6.CLKA
- Clock network: clk_125m
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_p_i" 5 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_p_i" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.075ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Location pin: BUFIO2_X4Y21.I
- Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_n_i" 5 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_n_i" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.075ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Location pin: BUFIO2_X4Y21.I
- Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.575ns (period - min period limit)
- Period: 2.500ns
- Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Location pin: PLL_ADV_X0Y2.CLKOUT0
- Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
- Period: 5.000ns
- Low pulse: 2.500ns
- Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
- Period: 5.000ns
- High pulse: 2.500ns
- High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.575ns (period - min period limit)
- Period: 2.500ns
- Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Location pin: PLL_ADV_X0Y2.CLKOUT0
- Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
- Period: 5.000ns
- Low pulse: 2.500ns
- Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
- Period: 5.000ns
- High pulse: 2.500ns
- High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk / 2 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.124ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Location pin: RAMB16_X2Y44.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Location pin: RAMB16_X2Y50.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Location pin: RAMB16_X2Y30.CLKB
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 / 2 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 5842 paths analyzed, 2324 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 4.752ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int (SLICE_X34Y109.A5), 170 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.248ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7 (FF)
- Destination: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.665ns (Levels of Logic = 5)
- Clock Path Skew: -0.012ns (0.242 - 0.254)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X39Y107.DQ Tcko 0.391 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<7>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7
- SLICE_X39Y109.A6 net (fanout=8) 0.703 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<7>
- SLICE_X39Y109.A Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<9>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110_SW0
- SLICE_X39Y108.C5 net (fanout=1) 0.885 N0
- SLICE_X39Y108.C Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<8>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.B2 net (fanout=1) 0.794 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.B Tilo 0.205 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full1
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full11
- SLICE_X34Y109.B4 net (fanout=1) 0.455 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full1
- SLICE_X34Y109.B Tilo 0.203 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full13
- SLICE_X34Y109.A5 net (fanout=1) 0.222 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full12
- SLICE_X34Y109.CLK Tas 0.289 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full15
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- ------------------------------------------------- ---------------------------
- Total 4.665ns (1.606ns logic, 3.059ns route)
- (34.4% logic, 65.6% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.322ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_8 (FF)
- Destination: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.589ns (Levels of Logic = 5)
- Clock Path Skew: -0.014ns (0.242 - 0.256)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_8 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X39Y108.AQ Tcko 0.391 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<8>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_8
- SLICE_X39Y109.A2 net (fanout=9) 0.627 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<8>
- SLICE_X39Y109.A Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<9>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110_SW0
- SLICE_X39Y108.C5 net (fanout=1) 0.885 N0
- SLICE_X39Y108.C Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<8>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.B2 net (fanout=1) 0.794 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.B Tilo 0.205 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full1
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full11
- SLICE_X34Y109.B4 net (fanout=1) 0.455 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full1
- SLICE_X34Y109.B Tilo 0.203 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full13
- SLICE_X34Y109.A5 net (fanout=1) 0.222 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full12
- SLICE_X34Y109.CLK Tas 0.289 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full15
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- ------------------------------------------------- ---------------------------
- Total 4.589ns (1.606ns logic, 2.983ns route)
- (35.0% logic, 65.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.325ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7 (FF)
- Destination: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.588ns (Levels of Logic = 5)
- Clock Path Skew: -0.012ns (0.242 - 0.254)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7 to cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X39Y107.DQ Tcko 0.391 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<7>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x_7
- SLICE_X39Y109.A6 net (fanout=8) 0.703 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<7>
- SLICE_X39Y109.A Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<9>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110_SW0
- SLICE_X39Y108.C5 net (fanout=1) 0.885 N0
- SLICE_X39Y108.C Tilo 0.259 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/rcb_gray_x<8>
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.B2 net (fanout=1) 0.794 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full110
- SLICE_X36Y109.BMUX Tilo 0.251 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full1
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full12
- SLICE_X34Y109.B6 net (fanout=1) 0.332 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full11
- SLICE_X34Y109.B Tilo 0.203 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full13
- SLICE_X34Y109.A5 net (fanout=1) 0.222 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full12
- SLICE_X34Y109.CLK Tas 0.289 cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mmux_going_full15
- cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/full_int
- ------------------------------------------------- ---------------------------
- Total 4.588ns (1.652ns logic, 2.936ns route)
- (36.0% logic, 64.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29 (SLICE_X49Y98.B5), 4 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.656ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_des/p2l_valid_o (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29 (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.221ns (Levels of Logic = 2)
- Clock Path Skew: -0.048ns (0.460 - 0.508)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_des/p2l_valid_o to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y77.AMUX Tshcko 0.461 cmp_gn4124_core/cmp_p2l_des/p2l_data_t2<3>
- cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
- SLICE_X47Y91.C5 net (fanout=13) 1.865 cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.B5 net (fanout=30) 1.314 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2111
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- ------------------------------------------------- ---------------------------
- Total 4.221ns (1.042ns logic, 3.179ns route)
- (24.7% logic, 75.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.782ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_decode32/target_mrd (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29 (FF)
- Requirement: 5.000ns
- Data Path Delay: 3.120ns (Levels of Logic = 2)
- Clock Path Skew: -0.023ns (0.460 - 0.483)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/target_mrd to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y93.AMUX Tshcko 0.461 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- cmp_gn4124_core/cmp_p2l_decode32/target_mrd
- SLICE_X47Y91.C1 net (fanout=34) 0.764 cmp_gn4124_core/cmp_p2l_decode32/target_mrd
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.B5 net (fanout=30) 1.314 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2111
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- ------------------------------------------------- ---------------------------
- Total 3.120ns (1.042ns logic, 2.078ns route)
- (33.4% logic, 66.6% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.921ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_decode32/target_mwr (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29 (FF)
- Requirement: 5.000ns
- Data Path Delay: 2.981ns (Levels of Logic = 2)
- Clock Path Skew: -0.023ns (0.460 - 0.483)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/target_mwr to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y93.AQ Tcko 0.391 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- SLICE_X47Y91.C2 net (fanout=66) 0.695 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.B5 net (fanout=30) 1.314 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2111
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_29
- ------------------------------------------------- ---------------------------
- Total 2.981ns (0.972ns logic, 2.009ns route)
- (32.6% logic, 67.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30 (SLICE_X49Y98.C5), 4 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.683ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_des/p2l_valid_o (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30 (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.194ns (Levels of Logic = 2)
- Clock Path Skew: -0.048ns (0.460 - 0.508)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_des/p2l_valid_o to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y77.AMUX Tshcko 0.461 cmp_gn4124_core/cmp_p2l_des/p2l_data_t2<3>
- cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
- SLICE_X47Y91.C5 net (fanout=13) 1.865 cmp_gn4124_core/cmp_p2l_des/p2l_valid_o
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.C5 net (fanout=30) 1.287 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2311
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- ------------------------------------------------- ---------------------------
- Total 4.194ns (1.042ns logic, 3.152ns route)
- (24.8% logic, 75.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.809ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_decode32/target_mrd (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30 (FF)
- Requirement: 5.000ns
- Data Path Delay: 3.093ns (Levels of Logic = 2)
- Clock Path Skew: -0.023ns (0.460 - 0.483)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/target_mrd to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y93.AMUX Tshcko 0.461 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- cmp_gn4124_core/cmp_p2l_decode32/target_mrd
- SLICE_X47Y91.C1 net (fanout=34) 0.764 cmp_gn4124_core/cmp_p2l_decode32/target_mrd
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.C5 net (fanout=30) 1.287 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2311
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- ------------------------------------------------- ---------------------------
- Total 3.093ns (1.042ns logic, 2.051ns route)
- (33.7% logic, 66.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.948ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_p2l_decode32/target_mwr (FF)
- Destination: cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30 (FF)
- Requirement: 5.000ns
- Data Path Delay: 2.954ns (Levels of Logic = 2)
- Clock Path Skew: -0.023ns (0.460 - 0.483)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_p2l_decode32/target_mwr to cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y93.AQ Tcko 0.391 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- SLICE_X47Y91.C2 net (fanout=66) 0.695 cmp_gn4124_core/cmp_p2l_decode32/target_mwr
- SLICE_X47Y91.C Tilo 0.259 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<3>
- cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o1
- SLICE_X49Y98.C5 net (fanout=30) 1.287 cmp_gn4124_core/cmp_p2l_decode32/GND_180_o_p2l_addr_cycle_MUX_418_o
- SLICE_X49Y98.CLK Tas 0.322 cmp_gn4124_core/cmp_p2l_decode32/p2l_addr<31>
- cmp_gn4124_core/cmp_p2l_decode32/mux2311
- cmp_gn4124_core/cmp_p2l_decode32/p2l_addr_30
- ------------------------------------------------- ---------------------------
- Total 2.954ns (0.972ns logic, 1.982ns route)
- (32.9% logic, 67.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m (OLOGIC_X27Y48.D1), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.043ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.052ns (Levels of Logic = 0)
- Clock Path Skew: 0.009ns (0.253 - 0.244)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X53Y49.BMUX Tshcko 0.434 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<11>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_9
- OLOGIC_X27Y48.D1 net (fanout=1) 0.931 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<9>
- OLOGIC_X27Y48.CLKDIV Tosckd_D (-Th) 1.313 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.052ns (-0.879ns logic, 0.931ns route)
- (-1690.4% logic, 1790.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m (OLOGIC_X27Y47.D2), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.077ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.097ns (Levels of Logic = 0)
- Clock Path Skew: 0.020ns (0.258 - 0.238)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y52.CMUX Tshcko 0.460 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<27>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_26
- OLOGIC_X27Y47.D2 net (fanout=1) 0.959 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<26>
- OLOGIC_X27Y47.CLKDIV Tosckd_D (-Th) 1.322 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[10].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.097ns (-0.862ns logic, 0.959ns route)
- (-888.7% logic, 988.7% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (OLOGIC_X27Y50.D2), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.085ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.093ns (Levels of Logic = 0)
- Clock Path Skew: 0.008ns (0.246 - 0.238)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y52.AMUX Tshcko 0.460 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<27>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24
- OLOGIC_X27Y50.D2 net (fanout=1) 0.955 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<24>
- OLOGIC_X27Y50.CLKDIV Tosckd_D (-Th) 1.322 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.093ns (-0.862ns logic, 0.955ns route)
- (-926.9% logic, 1026.9% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Location pin: RAMB16_X2Y44.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Location pin: RAMB16_X2Y50.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Location pin: RAMB16_X2Y30.CLKB
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Derived Constraints for TS_p2l_clk_p_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_n_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 4.752ns| 0| 0| 0| 5842|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.752ns| 0| 0| 0| 5842|
-| buf_P_clk_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.752ns| N/A| 0| 0| 5842| 0|
-| _rx_pllout_x1_0 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-All constraints were met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Clock to Setup on destination clock clk_20m_vcxo_i
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 5.258| | | |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock p2l_clk_n_i
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-p2l_clk_n_i | 4.752| | | |
-p2l_clk_p_i | 4.752| | | |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock p2l_clk_p_i
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-p2l_clk_n_i | 4.752| | | |
-p2l_clk_p_i | 4.752| | | |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock tdc_clk_125m_n_i
-----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc_clk_125m_n_i| 7.949| | | |
-tdc_clk_125m_p_i| 7.949| | | |
-----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock tdc_clk_125m_p_i
-----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-tdc_clk_125m_n_i| 7.949| | | |
-tdc_clk_125m_p_i| 7.949| | | |
-----------------+---------+---------+---------+---------+
-
-
-Timing summary:
----------------
-
-Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
-
-Constraints cover 392794 paths, 0 nets, and 19799 connections
-
-Design statistics:
- Minimum period: 7.949ns{1} (Maximum frequency: 125.802MHz)
-
-
-------------------------------------Footnotes-----------------------------------
-1) The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Tue Jul 08 10:30:36 2014
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings
-
-Peak Memory Usage: 224 MB
-
-
-
diff --git a/hdl/syn/spec/no_wrabbit/spec_tdc.xise b/hdl/syn/spec/no_wrabbit/spec_tdc.xise
deleted file mode 100644
index 605f2b1..0000000
--- a/hdl/syn/spec/no_wrabbit/spec_tdc.xise
+++ /dev/null
@@ -1,1393 +0,0 @@
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-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
-
- <files>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
- </file>
- <file xil_pn:name="../../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
- </file>
- <file xil_pn:name="../../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
- </file>
- <file xil_pn:name="../../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
- </file>
- <file xil_pn:name="../../../rtl/circular_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
- </file>
- <file xil_pn:name="../../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
- </file>
- <file xil_pn:name="../../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
- </file>
- <file xil_pn:name="../../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
- </file>
- <file xil_pn:name="../../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
- </file>
- <file xil_pn:name="../../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
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- <file xil_pn:name="../../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
- </file>
- <file xil_pn:name="../../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
- </file>
- <file xil_pn:name="../../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
- </file>
- <file xil_pn:name="../../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
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- <file xil_pn:name="../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
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- <file xil_pn:name="../../../ip_cores/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../top/spec/no_wrabbit/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../top/spec/no_wrabbit/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../top/spec/no_wrabbit/spec_tdc.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../top/spec/no_wrabbit/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
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- <file xil_pn:name="../../../top/spec/no_wrabbit/spec_tdc.ucf" xil_pn:type="FILE_UCF">
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-
- <properties>
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- <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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- <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
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- <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_tdc_map.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="spec_tdc_timesim.vhd" xil_pn:valueState="default"/>
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- <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
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- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
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- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-27T11:49:48" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7FBE502A282B40C7A2410990D68F770C" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/spec_tdc" xil_pn:name="../../../top/spec/no_wrabbit/spec_tdc.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- <file xil_pn:name="../../../ip_cores/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_lm32/src/lm32_functions.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
- </autoManagedFiles>
-
-</project>
diff --git a/hdl/syn/spec/no_wrabbit/spec_tdc_map.map b/hdl/syn/spec/no_wrabbit/spec_tdc_map.map
deleted file mode 100644
index d5d3f83..0000000
--- a/hdl/syn/spec/no_wrabbit/spec_tdc_map.map
+++ /dev/null
@@ -1,176 +0,0 @@
-Release 13.4 Map O.87xd (nt)
-Xilinx Map Application Log File for Design 'spec_tdc'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
-high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
-off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
-Target Device : xc6slx45t
-Target Package : fgg484
-Target Speed : -3
-Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Tue Jul 08 10:27:13 2014
-
-Mapping design into LUTs...
-Running directed packing...
-Running delay-based LUT packing...
-Updating timing models...
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
- (.mrp).
-Running timing-driven placement...
-Total REAL time at the beginning of Placer: 21 secs
-Total CPU time at the beginning of Placer: 17 secs
-
-Phase 1.1 Initial Placement Analysis
-Phase 1.1 Initial Placement Analysis (Checksum:de9a1ea9) REAL time: 37 secs
-
-Phase 2.7 Design Feasibility Check
-Phase 2.7 Design Feasibility Check (Checksum:de9a1ea9) REAL time: 38 secs
-
-Phase 3.31 Local Placement Optimization
-Phase 3.31 Local Placement Optimization (Checksum:de9a1ea9) REAL time: 38 secs
-
-Phase 4.2 Initial Placement for Architecture Specific Features
-
-Phase 4.2 Initial Placement for Architecture Specific Features
-(Checksum:46e77852) REAL time: 1 mins 9 secs
-
-Phase 5.36 Local Placement Optimization
-Phase 5.36 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 9 secs
-
-Phase 6.30 Global Clock Region Assignment
-Phase 6.30 Global Clock Region Assignment (Checksum:46e77852) REAL time: 1 mins 9 secs
-
-Phase 7.3 Local Placement Optimization
-Phase 7.3 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
-
-Phase 8.5 Local Placement Optimization
-Phase 8.5 Local Placement Optimization (Checksum:46e77852) REAL time: 1 mins 10 secs
-
-Phase 9.8 Global Placement
-..................................
-........................................................
-........................................................
-..........................
-Phase 9.8 Global Placement (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
-
-Phase 10.5 Local Placement Optimization
-Phase 10.5 Local Placement Optimization (Checksum:a3a2a52d) REAL time: 1 mins 42 secs
-
-Phase 11.18 Placement Optimization
-Phase 11.18 Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
-
-Phase 12.5 Local Placement Optimization
-Phase 12.5 Local Placement Optimization (Checksum:8078f7ee) REAL time: 1 mins 58 secs
-
-Phase 13.34 Placement Validation
-Phase 13.34 Placement Validation (Checksum:d7bfac99) REAL time: 1 mins 59 secs
-
-Total REAL time to Placer completion: 2 mins 6 secs
-Total CPU time to Placer completion: 1 mins 47 secs
-Running post-placement packing...
-Writing output files...
-WARNING:PhysDesignRules:372 - Gated clock. Clock net
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
- is sourced by a combinatorial pin. This is not good design practice. Use the
- CE pin to control the loading of data into the flip-flop.
-
-Design Summary
---------------
-
-Design Summary:
-Number of errors: 0
-Number of warnings: 1
-Slice Logic Utilization:
- Number of Slice Registers: 3,584 out of 54,576 6%
- Number used as Flip Flops: 3,559
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 23
- Number of Slice LUTs: 3,881 out of 27,288 14%
- Number used as logic: 3,781 out of 27,288 13%
- Number using O6 output only: 2,251
- Number using O5 output only: 328
- Number using O5 and O6: 1,202
- Number used as ROM: 0
- Number used as Memory: 2 out of 6,408 1%
- Number used as Dual Port RAM: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 2
- Number using O6 output only: 2
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used exclusively as route-thrus: 98
- Number with same-slice register load: 53
- Number with same-slice carry load: 45
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 1,510 out of 6,822 22%
- Nummber of MUXCYs used: 1,284 out of 13,644 9%
- Number of LUT Flip Flop pairs used: 4,827
- Number with an unused Flip Flop: 1,538 out of 4,827 31%
- Number with an unused LUT: 946 out of 4,827 19%
- Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
- Number of unique control sets: 129
- Number of slice register sites lost
- to control set restrictions: 309 out of 54,576 1%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 134 out of 296 45%
- Number of LOCed IOBs: 134 out of 134 100%
- IOB Flip Flops: 55
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 11 out of 116 9%
- Number of RAMB8BWERs: 0 out of 232 0%
- Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
- Number used as BUFIO2s: 1
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 3 out of 16 18%
- Number used as BUFGs: 3
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
- Number used as ILOGIC2s: 40
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
- Number used as OLOGIC2s: 15
- Number used as OSERDES2s: 20
- Number of BSCANs: 0 out of 4 0%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 0 out of 58 0%
- Number of GTPA1_DUALs: 0 out of 2 0%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 1 out of 4 25%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-Average Fanout of Non-Clock Nets: 3.70
-
-Peak Memory Usage: 355 MB
-Total REAL time to MAP completion: 2 mins 11 secs
-Total CPU time to MAP completion: 1 mins 52 secs
-
-Mapping completed.
-See MAP report file "spec_tdc_map.mrp" for details.
diff --git a/hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp b/hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp
deleted file mode 100644
index 629f311..0000000
--- a/hdl/syn/spec/no_wrabbit/spec_tdc_map.mrp
+++ /dev/null
@@ -1,973 +0,0 @@
-Release 13.4 Map O.87xd (nt)
-Xilinx Mapping Report File for Design 'spec_tdc'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
-high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
-off -pr b -lc off -power off -o spec_tdc_map.ncd spec_tdc.ngd spec_tdc.pcf
-Target Device : xc6slx45t
-Target Package : fgg484
-Target Speed : -3
-Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Tue Jul 08 10:27:13 2014
-
-Design Summary
---------------
-Number of errors: 0
-Number of warnings: 1
-Slice Logic Utilization:
- Number of Slice Registers: 3,584 out of 54,576 6%
- Number used as Flip Flops: 3,559
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 23
- Number of Slice LUTs: 3,881 out of 27,288 14%
- Number used as logic: 3,781 out of 27,288 13%
- Number using O6 output only: 2,251
- Number using O5 output only: 328
- Number using O5 and O6: 1,202
- Number used as ROM: 0
- Number used as Memory: 2 out of 6,408 1%
- Number used as Dual Port RAM: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 2
- Number using O6 output only: 2
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used exclusively as route-thrus: 98
- Number with same-slice register load: 53
- Number with same-slice carry load: 45
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 1,510 out of 6,822 22%
- Nummber of MUXCYs used: 1,284 out of 13,644 9%
- Number of LUT Flip Flop pairs used: 4,827
- Number with an unused Flip Flop: 1,538 out of 4,827 31%
- Number with an unused LUT: 946 out of 4,827 19%
- Number of fully used LUT-FF pairs: 2,343 out of 4,827 48%
- Number of unique control sets: 129
- Number of slice register sites lost
- to control set restrictions: 309 out of 54,576 1%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 134 out of 296 45%
- Number of LOCed IOBs: 134 out of 134 100%
- IOB Flip Flops: 55
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 11 out of 116 9%
- Number of RAMB8BWERs: 0 out of 232 0%
- Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
- Number used as BUFIO2s: 1
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 3 out of 16 18%
- Number used as BUFGs: 3
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 60 out of 376 15%
- Number used as ILOGIC2s: 40
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 35 out of 376 9%
- Number used as OLOGIC2s: 15
- Number used as OSERDES2s: 20
- Number of BSCANs: 0 out of 4 0%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 0 out of 58 0%
- Number of GTPA1_DUALs: 0 out of 2 0%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 1 out of 4 25%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-Average Fanout of Non-Clock Nets: 3.70
-
-Peak Memory Usage: 355 MB
-Total REAL time to MAP completion: 2 mins 11 secs
-Total CPU time to MAP completion: 1 mins 52 secs
-
-Table of Contents
------------------
-Section 1 - Errors
-Section 2 - Warnings
-Section 3 - Informational
-Section 4 - Removed Logic Summary
-Section 5 - Removed Logic
-Section 6 - IOB Properties
-Section 7 - RPMs
-Section 8 - Guide Report
-Section 9 - Area Group and Partition Summary
-Section 10 - Timing Report
-Section 11 - Configuration String Information
-Section 12 - Control Set Information
-Section 13 - Utilization by Hierarchy
-
-Section 1 - Errors
-------------------
-
-Section 2 - Warnings
---------------------
-WARNING:PhysDesignRules:372 - Gated clock. Clock net
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_227_o_Mux_41_o
- is sourced by a combinatorial pin. This is not good design practice. Use the
- CE pin to control the loading of data into the flip-flop.
-
-Section 3 - Informational
--------------------------
-INFO:LIT:243 - Logical network button1_i has no load.
-INFO:LIT:395 - The above info message is repeated 142 more times for the
- following (max. 5 shown):
- button2_i,
- tdc_in_fpga_1_i,
- tdc_in_fpga_2_i,
- tdc_in_fpga_3_i,
- tdc_in_fpga_4_i
- To see the details of these info messages, please use the -detail switch.
-INFO:MapLib:562 - No environment variables are currently set.
-INFO:LIT:244 - All of the single ended outputs in this design are using slew
- rate limited output drivers. The delay on speed critical single ended outputs
- can be dramatically reduced by designating them as fast outputs.
-INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
- 0.000 to 85.000 Celsius)
-INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
- 1.260 Volts)
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
- Command Line Tools User Guide for information on generating a TSI report.
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
- (.mrp).
-INFO:Pack:1650 - Map created a placed design.
-
-Section 4 - Removed Logic Summary
----------------------------------
- 60 block(s) removed
- 3 block(s) optimized away
- 169 signal(s) removed
-
-Section 5 - Removed Logic
--------------------------
-
-The trimmed logic report below shows the logic removed from your design due to
-sourceless or loadless signals, and VCC or ground connections. If the removal
-of a signal or symbol results in the subsequent removal of an additional signal
-or symbol, the message explaining that second removal will be indented. This
-indentation will be repeated as a chain of related logic is removed.
-
-To quickly locate the original cause for the removal of a chain of logic, look
-above the place where that logic is listed in the trimming report, then locate
-the lines that are least indented (begin at the leftmost edge).
-
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
-been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
-(BUF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0364_inv1" (ROM)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
-(ROM) removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
-sourceless and has been removed.
-
-Optimized Block(s):
-TYPE BLOCK
-GND XST_GND
-VCC XST_VCC
-GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
-
-To enable printing of redundant blocks removed and signals merged, set the
-detailed map report option and rerun map.
-
-Section 6 - IOB Properties
---------------------------
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
-| | | | | Term | Strength | Rate | | | Delay |
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
-| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
-| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
-| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| led_green_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| led_red_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_sys_scl_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_sys_sda_b | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
-| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
-| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
-| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
-| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
-| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
-| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
-| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
-| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-Section 7 - RPMs
-----------------
-
-Section 8 - Guide Report
-------------------------
-Guide not run on this design.
-
-Section 9 - Area Group and Partition Summary
---------------------------------------------
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-Area Group Information
-----------------------
-
- No area groups were found in this design.
-
-----------------------
-
-Section 10 - Timing Report
---------------------------
-A logic-level (pre-route) timing report can be generated by using Xilinx static
-timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
-mapped NCD and PCF files. Please note that this timing report will be generated
-using estimated delay information. For accurate numbers, please generate a
-timing report with the post Place and Route NCD file.
-
-For more information about the Timing Analyzer, consult the Xilinx Timing
-Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
-Command Line Tools User Guide "TRACE" chapter.
-
-Section 11 - Configuration String Details
------------------------------------------
-Use the "-detail" map option to print out Configuration Strings
-
-Section 12 - Control Set Information
-------------------------------------
-Use the "-detail" map option to print out Control Set Information.
-
-Section 13 - Utilization by Hierarchy
--------------------------------------
-Use the "-detail" map option to print out the Utilization by Hierarchy section.
diff --git a/hdl/syn/spec/no_wrabbit/wrc.ram b/hdl/syn/spec/no_wrabbit/wrc.ram
deleted file mode 100644
index ab26e0f..0000000
--- a/hdl/syn/spec/no_wrabbit/wrc.ram
+++ /dev/null
@@ -1,19518 +0,0 @@
-write 0 98000000
-write 1 D0000000
-write 2 D0200000
-write 3 78010000
-write 4 38210000
-write 5 D0E10000
-write 6 F800003A
-write 7 34000000
-write 8 00000000
-write 9 00000000
-write a 00000000
-write b 00000000
-write c 00000000
-write d 00000000
-write e 00000000
-write f 00000000
-write 10 00000000
-write 11 00000000
-write 12 00000000
-write 13 00000000
-write 14 00000000
-write 15 00000000
-write 16 00000000
-write 17 00000000
-write 18 00000000
-write 19 00000000
-write 1a 00000000
-write 1b 00000000
-write 1c 00000000
-write 1d 00000000
-write 1e 00000000
-write 1f 00000000
-write 20 00000000
-write 21 00000000
-write 22 00000000
-write 23 00000000
-write 24 00000000
-write 25 00000000
-write 26 00000000
-write 27 00000000
-write 28 00000000
-write 29 00000000
-write 2a 00000000
-write 2b 00000000
-write 2c 00000000
-write 2d 00000000
-write 2e 00000000
-write 2f 00000000
-write 30 5B9D0000
-write 31 F8000020
-write 32 34010002
-write 33 F8003A00
-write 34 E0000030
-write 35 34000000
-write 36 34000000
-write 37 34000000
-write 38 00000000
-write 39 00000000
-write 3a 00000000
-write 3b 00000000
-write 3c 00000000
-write 3d 00000000
-write 3e 00000000
-write 3f 00000000
-write 40 98000000
-write 41 781C0001
-write 42 3B9C5FFC
-write 43 781A0001
-write 44 3B5AB060
-write 45 78010001
-write 46 382130F8
-write 47 34020000
-write 48 78030001
-write 49 3863516C
-write 4a C8611800
-write 4b F8003EB1
-write 4c 34010000
-write 4d 34020000
-write 4e 34030000
-write 4f F800004D
-write 50 E0000000
-write 51 379CFFC4
-write 52 5B810004
-write 53 5B820008
-write 54 5B83000C
-write 55 5B840010
-write 56 5B850014
-write 57 5B860018
-write 58 5B87001C
-write 59 5B880020
-write 5a 5B890024
-write 5b 5B8A0028
-write 5c 5B9E0034
-write 5d 5B9F0038
-write 5e 2B81003C
-write 5f 5B810030
-write 60 BB800800
-write 61 3421003C
-write 62 5B81002C
-write 63 C3A00000
-write 64 2B810004
-write 65 2B820008
-write 66 2B83000C
-write 67 2B840010
-write 68 2B850014
-write 69 2B860018
-write 6a 2B87001C
-write 6b 2B880020
-write 6c 2B890024
-write 6d 2B8A0028
-write 6e 2B9D0030
-write 6f 2B9E0034
-write 70 2B9F0038
-write 71 2B9C002C
-write 72 34000000
-write 73 C3C00000
-write 74 90001000
-write 75 3401FFFE
-write 76 A0410800
-write 77 D0010000
-write 78 90201000
-write 79 3401FFFE
-write 7a A0410800
-write 7b D0210000
-write 7c C3A00000
-write 7d 90001000
-write 7e 3401FFFE
-write 7f A0410800
-write 80 D0010000
-write 81 90201000
-write 82 38420001
-write 83 D0220000
-write 84 38210001
-write 85 D0010000
-write 86 C3A00000
-write 87 379CFFE0
-write 88 5B9D0004
-write 89 5B83000C
-write 8a 78030001
-write 8b 5B820008
-write 8c 5B840010
-write 8d 5B850014
-write 8e 5B860018
-write 8f 5B87001C
-write 90 5B880020
-write 91 386330F8
-write 92 28630000
-write 93 5C600006
-write 94 20210020
-write 95 44230004
-write 96 B8400800
-write 97 3782000C
-write 98 F8002692
-write 99 2B9D0004
-write 9a 379C0020
-write 9b C3A00000
-write 9c 379CFFBC
-write 9d 5B8B003C
-write 9e 5B8C0038
-write 9f 5B8D0034
-write a0 5B8E0030
-write a1 5B8F002C
-write a2 5B900028
-write a3 5B910024
-write a4 5B920020
-write a5 5B93001C
-write a6 5B940018
-write a7 5B950014
-write a8 5B960010
-write a9 5B97000C
-write aa 5B980008
-write ab 5B9D0004
-write ac 78030001
-write ad 386322C0
-write ae 78010001
-write af 28620000
-write b0 382130F8
-write b1 58200000
-write b2 78010001
-write b3 38215800
-write b4 58220000
-write b5 F8002E3D
-write b6 F8003581
-write b7 F8003577
-write b8 78010001
-write b9 382100F0
-write ba F8002692
-write bb 34010001
-write bc F8002D4B
-write bd F800335E
-write be 78010001
-write bf 382150B8
-write c0 58200000
-write c1 F8003284
-write c2 34010000
-write c3 F8002A70
-write c4 34020050
-write c5 34010000
-write c6 F8003006
-write c7 34010008
-write c8 33810040
-write c9 34010030
-write ca 33810042
-write cb 37820040
-write cc 34010000
-write cd 33800041
-write ce F8003217
-write cf 3402FFFF
-write d0 5C220010
-write d1 78010001
-write d2 3821010C
-write d3 F8002679
-write d4 34010011
-write d5 33810040
-write d6 34010022
-write d7 33810041
-write d8 34010033
-write d9 33810042
-write da 34010044
-write db 33810043
-write dc 34010055
-write dd 33810044
-write de 34010066
-write df 33810045
-write e0 43830040
-write e1 43840041
-write e2 43850042
-write e3 43860043
-write e4 43870044
-write e5 43880045
-write e6 78020001
-write e7 38420130
-write e8 34010000
-write e9 FBFFFF9E
-write ea 37810040
-write eb F8002782
-write ec 34020001
-write ed 34010001
-write ee F800279E
-write ef F8002AE3
-write f0 F8002C62
-write f1 F800042A
-write f2 78020001
-write f3 38422854
-write f4 34010002
-write f5 F8002F18
-write f6 F8002410
-write f7 F8001E73
-write f8 34010003
-write f9 F8000476
-write fa F8000433
-write fb F8001F45
-write fc 78010001
-write fd 382122C0
-write fe 28360000
-write ff 780F0001
-write 100 78120001
-write 101 780B0001
-write 102 78110001
-write 103 780C0001
-write 104 780D0001
-write 105 78100001
-write 106 39EF2858
-write 107 34180004
-write 108 3A520164
-write 109 396B5150
-write 10a 340E0002
-write 10b 3A310158
-write 10c 34170001
-write 10d 34150003
-write 10e 398C30F8
-write 10f 3414001B
-write 110 39AD5800
-write 111 3A100170
-write 112 34010000
-write 113 F80027AB
-write 114 29E40000
-write 115 7C230000
-write 116 B8209800
-write 117 64810000
-write 118 A0610800
-write 119 44200008
-write 11a 34010000
-write 11b BA201000
-write 11c FBFFFF6B
-write 11d 29610000
-write 11e 34030001
-write 11f 582E0004
-write 120 E000000D
-write 121 66620000
-write 122 7C840000
-write 123 A0441000
-write 124 FC621800
-write 125 CB031800
-write 126 44410007
-write 127 34010000
-write 128 BA401000
-write 129 FBFFFF5E
-write 12a 29610000
-write 12b 34030002
-write 12c 582E0008
-write 12d 59F30000
-write 12e 446E0004
-write 12f 5C75000B
-write 130 F8002571
-write 131 E0000009
-write 132 F80003F7
-write 133 5C350007
-write 134 34010002
-write 135 34020000
-write 136 34030001
-write 137 F80039DB
-write 138 34010000
-write 139 F8002CC2
-write 13a 29810000
-write 13b 5C370003
-write 13c F8000067
-write 13d E0000004
-write 13e 5C2E0008
-write 13f 34010000
-write 140 F80001EB
-write 141 F800351C
-write 142 5C340005
-write 143 F8001E27
-write 144 59800000
-write 145 E0000002
-write 146 F8001E2E
-write 147 F80004AD
-write 148 F8003B9D
-write 149 E0000005
-write 14a BA000800
-write 14b F8002601
-write 14c 340103E8
-write 14d F8002CD1
-write 14e 29A10000
-write 14f 5C36FFFB
-write 150 E3FFFFC2
-write 151 379CFFF4
-write 152 5B9D0004
-write 153 5B810008
-write 154 5B82000C
-write 155 B8401800
-write 156 4820000C
-write 157 5C200005
-write 158 78020001
-write 159 384222C4
-write 15a 28410000
-write 15b 54610007
-write 15c 78010001
-write 15d 78020001
-write 15e 38420184
-write 15f 38213108
-write 160 F80025DE
-write 161 E000000D
-write 162 78030001
-write 163 386322C8
-write 164 28620000
-write 165 37810008
-write 166 F8001D43
-write 167 2B83000C
-write 168 B8202000
-write 169 78020001
-write 16a 78010001
-write 16b 38213108
-write 16c 38420188
-write 16d F80025D1
-write 16e 78010001
-write 16f 38213108
-write 170 2B9D0004
-write 171 379C000C
-write 172 C3A00000
-write 173 379CFFF8
-write 174 5B8B0008
-write 175 5B9D0004
-write 176 78010001
-write 177 3821285C
-write 178 780B0001
-write 179 28210000
-write 17a 396B2E88
-write 17b E0000004
-write 17c 28230000
-write 17d 44430004
-write 17e 356B000C
-write 17f 29620000
-write 180 5C40FFFC
-write 181 78020001
-write 182 34010004
-write 183 38420190
-write 184 F800230E
-write 185 29630004
-write 186 78020001
-write 187 34010007
-write 188 384201A0
-write 189 F8002309
-write 18a 78010001
-write 18b 38213370
-write 18c 28210000
-write 18d 44200007
-write 18e 78010001
-write 18f 3821285C
-write 190 28210000
-write 191 28220000
-write 192 34010009
-write 193 44410007
-write 194 78020001
-write 195 34010001
-write 196 384201A4
-write 197 F80022FB
-write 198 34010000
-write 199 E0000006
-write 19a 78020001
-write 19b 34010004
-write 19c 384201BC
-write 19d F80022F5
-write 19e 34010001
-write 19f 2B9D0004
-write 1a0 2B8B0008
-write 1a1 379C0008
-write 1a2 C3A00000
-write 1a3 379CFF88
-write 1a4 5B8B0010
-write 1a5 5B8C000C
-write 1a6 5B8D0008
-write 1a7 5B9D0004
-write 1a8 780B0001
-write 1a9 F8002C70
-write 1aa 396B3104
-write 1ab 29620000
-write 1ac C8220800
-write 1ad 340203E7
-write 1ae 50410177
-write 1af F8002C6A
-write 1b0 59610000
-write 1b1 F8002327
-write 1b2 78040001
-write 1b3 34010001
-write 1b4 34020001
-write 1b5 34030004
-write 1b6 388401D8
-write 1b7 F80022FA
-write 1b8 78040001
-write 1b9 388401F8
-write 1ba 34030087
-write 1bb 34010002
-write 1bc 34020001
-write 1bd F80022F4
-write 1be 37810068
-write 1bf 37820070
-write 1c0 F8002C0B
-write 1c1 78020001
-write 1c2 34010004
-write 1c3 38420204
-write 1c4 F80022CE
-write 1c5 2B82006C
-write 1c6 2B810068
-write 1c7 F8002240
-write 1c8 78020001
-write 1c9 B8201800
-write 1ca 384201A0
-write 1cb 34010007
-write 1cc F80022C6
-write 1cd 34020000
-write 1ce 37810014
-write 1cf F8000209
-write 1d0 78040001
-write 1d1 34010004
-write 1d2 34020001
-write 1d3 34030004
-write 1d4 38840224
-write 1d5 F80022DC
-write 1d6 78040001
-write 1d7 78050001
-write 1d8 34010006
-write 1d9 34020001
-write 1da 34030007
-write 1db 38840234
-write 1dc 38A5023C
-write 1dd F80022D4
-write 1de 2B81002C
-write 1df 44200005
-write 1e0 78020001
-write 1e1 34010002
-write 1e2 38420244
-write 1e3 E0000004
-write 1e4 78020001
-write 1e5 34010001
-write 1e6 38420250
-write 1e7 F80022AB
-write 1e8 2B81002C
-write 1e9 44200139
-write 1ea 37810078
-write 1eb 37820074
-write 1ec F8002B5F
-write 1ed 2B830074
-write 1ee 2B840078
-write 1ef 78020001
-write 1f0 34010087
-write 1f1 3842025C
-write 1f2 780B0001
-write 1f3 F800229F
-write 1f4 396B285C
-write 1f5 29610000
-write 1f6 28210448
-write 1f7 28210010
-write 1f8 282C0008
-write 1f9 5D800037
-write 1fa 78020001
-write 1fb 34010001
-write 1fc 38420278
-write 1fd F8002295
-write 1fe FBFFFF75
-write 1ff 442C0126
-write 200 78020001
-write 201 34010087
-write 202 38420280
-write 203 F800228F
-write 204 29610000
-write 205 2821001C
-write 206 28240010
-write 207 28830004
-write 208 4460000B
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-write 4c35 00011C58
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diff --git a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.par b/hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
deleted file mode 100644
index 706ab8c..0000000
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.par
+++ /dev/null
@@ -1,491 +0,0 @@
-Release 13.4 par O.87xd (nt)
-Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-
-PCBE13136:: Tue Jul 08 11:06:17 2014
-
-par -w -intstyle ise -ol high -xe c -mt off wr_spec_tdc_map.ncd wr_spec_tdc.ncd
-wr_spec_tdc.pcf
-
-
-Constraints file: wr_spec_tdc.pcf.
-Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\v13_4\ISE_DS\ISE\.
- "wr_spec_tdc" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
-INFO:Par:338 -
- Extra Effort Level "c"ontinue is not a runtime optimized effort level. It is intended to be used for designs that are
- not meeting timing but where the designer wants the tools to continue iterating on the design until no further design
- speed improvements are possible. This can result in very long runtimes since the tools will continue improving the
- design even if the time specs can not be met. If you are looking for the best possible design speed available from a
- long but reasonable runtime use Extra Effort Level "n"ormal. It will stop iterating on the design when the design
- speed improvements have shrunk to the point that the time specs are not expected to be met.
-
-Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
-
-
-Device speed data version: "PRODUCTION 1.21 2012-01-07".
-
-
-
-Device Utilization Summary:
-
-Slice Logic Utilization:
- Number of Slice Registers: 8,192 out of 54,576 15%
- Number used as Flip Flops: 8,166
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 24
- Number of Slice LUTs: 10,646 out of 27,288 39%
- Number used as logic: 10,382 out of 27,288 38%
- Number using O6 output only: 7,374
- Number using O5 output only: 777
- Number using O5 and O6: 2,231
- Number used as ROM: 0
- Number used as Memory: 67 out of 6,408 1%
- Number used as Dual Port RAM: 24
- Number using O6 output only: 24
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 43
- Number using O6 output only: 22
- Number using O5 output only: 0
- Number using O5 and O6: 21
- Number used exclusively as route-thrus: 197
- Number with same-slice register load: 122
- Number with same-slice carry load: 75
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 4,050 out of 6,822 59%
- Nummber of MUXCYs used: 2,388 out of 13,644 17%
- Number of LUT Flip Flop pairs used: 12,451
- Number with an unused Flip Flop: 4,848 out of 12,451 38%
- Number with an unused LUT: 1,805 out of 12,451 14%
- Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
- Number of slice register sites lost
- to control set restrictions: 0 out of 54,576 0%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 152 out of 296 51%
- Number of LOCed IOBs: 152 out of 152 100%
- IOB Flip Flops: 57
- Number of bonded IPADs: 4 out of 16 25%
- Number of LOCed IPADs: 4 out of 4 100%
- Number of bonded OPADs: 2 out of 8 25%
- Number of LOCed OPADs: 2 out of 2 100%
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 62 out of 116 53%
- Number of RAMB8BWERs: 9 out of 232 3%
- Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
- Number used as BUFIO2s: 3
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 7 out of 16 43%
- Number used as BUFGs: 7
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
- Number used as ILOGIC2s: 41
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
- Number used as OLOGIC2s: 16
- Number used as OSERDES2s: 20
- Number of BSCANs: 1 out of 4 25%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 3 out of 58 5%
- Number of GTPA1_DUALs: 1 out of 2 50%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 3 out of 4 75%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-
-Overall effort level (-ol): High
-Router effort level (-rl): High
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
- Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis. REAL time: 20 secs
-Finished initial Timing Analysis. REAL time: 20 secs
-
-WARNING:Par:288 - The signal sfp_rate_select_b_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal sfp_tx_fault_i_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal tdc_in_fpga_1_i_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal button2_i_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal p_wr_req_i<0>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal p_wr_req_i<1>_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal pll_sdo_i_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal sfp_los_i_IBUF has no load. PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O has no load.
- PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O has no load.
- PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O has no load.
- PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O has no load.
- PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O has no load.
- PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O has no load.
- PAR will not attempt to route this signal.
-Starting Router
-
-
-Phase 1 : 70638 unrouted; REAL time: 22 secs
-
-Phase 2 : 62023 unrouted; REAL time: 26 secs
-
-Phase 3 : 32684 unrouted; REAL time: 54 secs
-
-Phase 4 : 32741 unrouted; (Setup:0, Hold:72789, Component Switching Limit:0) REAL time: 58 secs
-
-Updating file: wr_spec_tdc.ncd with current fully routed design.
-
-Phase 5 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
-
-Phase 6 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
-
-Phase 7 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
-
-Phase 8 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
-
-Phase 9 : 0 unrouted; (Setup:0, Hold:70704, Component Switching Limit:0) REAL time: 2 mins 1 secs
-
-Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 3 secs
-
-Phase 11 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 7 secs
-Total REAL time to Router completion: 2 mins 7 secs
-Total CPU time to Router completion: 2 mins 11 secs
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-| clk_62m5_sys | BUFGMUX_X3Y13| No | 1643 | 0.529 | 1.740 |
-+---------------------+--------------+------+------+------------+-------------+
-| clk_125m_mezz | BUFGMUX_X3Y7| No | 727 | 0.551 | 1.762 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/sys_ | | | | | |
-| clk | BUFGMUX_X2Y4| No | 247 | 0.522 | 1.733 |
-+---------------------+--------------+------+------+------------+-------------+
-| phy_rx_rbclk | BUFGMUX_X3Y8| No | 153 | 0.077 | 1.290 |
-+---------------------+--------------+------+------+------------+-------------+
-|clk_125m_pllref_BUFG | | | | | |
-| | BUFGMUX_X2Y1| No | 152 | 0.065 | 1.281 |
-+---------------------+--------------+------+------+------------+-------------+
-| clk_dmtd | BUFGMUX_X2Y2| No | 88 | 0.032 | 1.245 |
-+---------------------+--------------+------+------+------------+-------------+
-|U_WR_CORE/WRPC/LM32_ | | | | | |
-|CORE/gen_profile_med | | | | | |
-|ium_icache_debug.U_W | | | | | |
-| rapped_LM32/jtck | Local| | 9 | 3.112 | 6.373 |
-+---------------------+--------------+------+------+------------+-------------+
-|U_Buf_CLK_GTP_ML_IBU | | | | | |
-| F2 | Local| | 1 | 0.000 | 0.002 |
-+---------------------+--------------+------+------+------------+-------------+
-|U_Buf_CLK_GTP_ML_IBU | | | | | |
-| F1 | Local| | 1 | 0.000 | 0.002 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_gn4124_core/io_c | | | | | |
-| lk | Local| | 41 | 0.064 | 1.562 |
-+---------------------+--------------+------+------+------------+-------------+
-| clk_125m_gtp | Local| | 1 | 0.000 | 1.256 |
-+---------------------+--------------+------+------+------------+-------------+
-|cmp_tdc_mezz/cmp_tdc | | | | | |
-|_core/data_engine_bl | | | | | |
-|ock/engine_st[3]_PWR | | | | | |
-| _441_o_Mux_41_o | Local| | 1 | 0.000 | 0.972 |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-* The fanout is the number of component pins not the individual BEL loads,
-for example SLICE loads not FF loads.
-
-Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
-
-Number of Timing Constraints that were not applied: 17
-
-Asterisk (*) preceding a constraint indicates it was not met.
- This may be due to a setup or hold violation.
-
-----------------------------------------------------------------------------------------------------------
- Constraint | Check | Worst Case | Best Case | Timing | Timing
- | | Slack | Achievable | Errors | Score
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.050ns| 4.950ns| 0| 0
- 1_1 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.115ns| | 0| 0
- core_cmp_clk_in_rx_pllout_x1_1" T | | | | |
- S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | | | | |
- PHASE 1.25 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc | SETUP | 0.051ns| 7.949ns| 0| 0
- _clk_125m_n_i" 8 ns HIGH 50% | HOLD | 0.421ns| | 0| 0
-----------------------------------------------------------------------------------------------------------
- TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP " | SETUP | 0.169ns| 7.831ns| 0| 0
- U_GTP_ch1_rx_divclk" TS_U_GTP_ch1 | HOLD | 0.322ns| | 0| 0
- _gtp_clkout_int_1_ HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_tr | SETUP | 0.169ns| 1.831ns| 0| 0
- ig" TO TIMEGRP "FFS" 2 ns DATAPAT | HOLD | 0.704ns| | 0| 0
- HONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_s | SETUP | 0.181ns| 9.819ns| 0| 0
- ys" TO TIMEGRP "U_GTP_ch1_rx_divclk" | HOLD | 0.448ns| | 0| 0
- 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_ = MAXDELAY FROM TIMEGRP "skew_limit" | SETUP | 0.557ns| 1.443ns| 0| 0
- TO TIMEGRP "FFS" 2 ns DATAPATHONLY | HOLD | 0.434ns| | 0| 0
-----------------------------------------------------------------------------------------------------------
- TS_clk_125m_pllref_n_i = PERIOD TIMEGRP " | SETUP | 0.774ns| 6.711ns| 0| 0
- clk_125m_pllref_n_i" 8 ns HIGH 50% | HOLD | 0.393ns| | 0| 0
-----------------------------------------------------------------------------------------------------------
- TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_ | SETUP | 0.861ns| 9.139ns| 0| 0
- rx_divclk" TO TIMEGRP "clk_62m5_sys" | HOLD | 0.344ns| | 0| 0
- 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_pllout_clk_sys = PERIOD TIMEGRP "pllou | SETUP | 1.200ns| 14.800ns| 0| 0
- t_clk_sys" TS_clk_20m_vcxo_i / 3.125 | HOLD | 0.039ns| | 0| 0
- HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
- = PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
- e_cmp_clk_in_buf_P_clk_1" TS_cmp_ | | | | |
- gn4124_core_cmp_clk_in_P_clk HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
- = PERIOD TIMEGRP "cmp_gn4124_cor | | | | |
- e_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i | | | | |
- HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
- PERIOD TIMEGRP "cmp_gn4124_core_ | | | | |
- cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH | | | | |
- 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_clk_125m_pllref_p_i = PERIOD TIMEGRP " | MINPERIOD | 1.750ns| 6.250ns| 0| 0
- clk_125m_pllref_p_i" 8 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
- 1_0 = PERIOD TIMEGRP "cmp_gn4124_ | | | | |
- core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
- S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
- PHASE 1.25 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | MINPERIOD | 1.876ns| 3.124ns| 0| 0
- 1 = PERIOD TIMEGRP "cmp_gn4124_co | | | | |
- re_cmp_clk_in_rx_pllout_x1" TS_cm | | | | |
- p_gn4124_core_cmp_clk_in_buf_P_clk PHASE | | | | |
- 1.25 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_2 | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
- 0m_vcxo_i" 50 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP | SETUP | 3.332ns| 6.668ns| 0| 0
- "clk_62m5_sys" TO TIMEGRP "clk_1 | HOLD | 0.491ns| | 0| 0
- 25m_pllref_n_i" 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
- p_i" 5 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_P_clk = PER | MINPERIOD | 4.075ns| 0.925ns| 0| 0
- IOD TIMEGRP "cmp_gn4124_core/cmp_ | | | | |
- clk_in/P_clk" 5 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_ | MINPERIOD | 4.075ns| 0.925ns| 0| 0
- n_i" 5 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- ts_ignore_crossclock = MAXDELAY FROM TIME | SETUP | 4.274ns| 5.726ns| 0| 0
- GRP "clk_62m5_sys" TO TIMEGRP "td | HOLD | 0.456ns| | 0| 0
- c_clk_125m_p_i" 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
- _125m_gtp_p_i" 8 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk | MINPERIOD | 4.875ns| 3.125ns| 0| 0
- _125m_gtp_n_i" 8 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_ | MINPERIOD | 4.876ns| 3.124ns| 0| 0
- clk_125m_p_i" 8 ns HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllo | SETUP | 5.919ns| 10.081ns| 0| 0
- ut_clk_dmtd" TS_clk_20m_vcxo_i / | HOLD | 0.014ns| | 0| 0
- 3.125 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP | SETUP | 6.013ns| 3.987ns| 0| 0
- "clk_125m_pllref_p_i" TO TIMEGRP | HOLD | 0.448ns| | 0| 0
- "clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- ts_ignore_crossclock2 = MAXDELAY FROM TIM | SETUP | 6.783ns| 3.217ns| 0| 0
- EGRP "tdc_clk_125m_p_i" TO TIMEGRP | HOLD | 0.367ns| | 0| 0
- "clk_62m5_sys" 10 ns DATAPATHONLY | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD T | MINPERIOD | 7.075ns| 0.925ns| 0| 0
- IMEGRP "U_GTP/ch1_gtp_clkout_int<1>" | | | | |
- 125 MHz HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
- s_int = PERIOD TIMEGRP "cmp_gn412 | | | | |
- 4_core_cmp_clk_in_rx_pllout_xs_int" | | | | |
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_cl | | | | |
- k / 2 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
- s_int_0 = PERIOD TIMEGRP "cmp_gn4 | | | | |
- 124_core_cmp_clk_in_rx_pllout_xs_int_0" | | | | |
- TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
- P_clk_0 / 2 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
- TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | N/A | N/A| N/A| N/A| N/A
- s_int_1 = PERIOD TIMEGRP "cmp_gn4 | | | | |
- 124_core_cmp_clk_in_rx_pllout_xs_int_1" | | | | |
- TS_cmp_gn4124_core_cmp_clk_in_buf_ | | | | |
- P_clk_1 / 2 HIGH 50% | | | | |
-----------------------------------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Review Timing Report for more details on the following derived constraints.
-To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
-or "Run Timing Analysis" from Timing Analyzer (timingan).
-Derived Constraints for TS_clk_20m_vcxo_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.250ns| 0| 0| 0| 1682593|
-| TS_pllout_clk_dmtd | 16.000ns| 10.081ns| N/A| 0| 0| 9425| 0|
-| TS_pllout_clk_sys | 16.000ns| 14.800ns| N/A| 0| 0| 1673168| 0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_p_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_n_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1_0 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_cmp_gn4124_core_cmp_clk_in_P_clk
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.950ns| 0| 0| 0| 5838|
-|_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.950ns| 0| 0| 0| 5838|
-| buf_P_clk_1 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_1 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.950ns| N/A| 0| 0| 5838| 0|
-| _rx_pllout_x1_1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_U_GTP_ch1_gtp_clkout_int_1_
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.831ns| 0| 0| 0| 20096|
-| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.831ns| N/A| 0| 0| 20096| 0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-All constraints were met.
-INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
- constraint is not analyzed due to the following: No paths covered by this
- constraint; Other constraints intersect with this constraint; or This
- constraint was disabled by a Path Tracing Control. Please run the Timespec
- Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-WARNING:Par:283 - There are 16 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-
-Total REAL time to PAR completion: 2 mins 13 secs
-Total CPU time to PAR completion: 2 mins 17 secs
-
-Peak Memory Usage: 458 MB
-
-Placer: Placement generated during map.
-Routing: Completed - No errors found.
-Timing: Completed - No errors found.
-
-Number of error messages: 0
-Number of warning messages: 18
-Number of info messages: 2
-
-Writing design to file wr_spec_tdc.ncd
-
-
-
-PAR done!
diff --git a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr b/hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
deleted file mode 100644
index b8a1b26..0000000
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.twr
+++ /dev/null
@@ -1,4485 +0,0 @@
---------------------------------------------------------------------------------
-Release 13.4 Trace (nt)
-Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
-
-C:\EDA\Xilinx\v13_4\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s
-3 -n 3 -fastpaths -xml wr_spec_tdc.twx wr_spec_tdc.ncd -o wr_spec_tdc.twr
-wr_spec_tdc.pcf
-
-Design file: wr_spec_tdc.ncd
-Physical constraint file: wr_spec_tdc.pcf
-Device,package,speed: xc6slx45t,fgg484,C,-3 (PRODUCTION 1.21 2012-01-07)
-Report level: verbose report
-
-Environment Variable Effect
--------------------- ------
-NONE No environment variables were set
---------------------------------------------------------------------------------
-
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more
- information, see the TSI report. Please consult the Xilinx Command Line
- Tools User Guide for information on generating a TSI report.
-INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
-
-================================================================================
-Timing constraint: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 20.000ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_20m_vcxo_i = PERIOD TIMEGRP "clk_20m_vcxo_i" 50 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 2.630ns (max period limit - period)
- Period: 50.000ns
- Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN)
- Physical resource: cmp_dmtd_clk_pll/PLL_ADV/CLKIN1
- Logical resource: cmp_dmtd_clk_pll/PLL_ADV/CLKIN1
- Location pin: PLL_ADV_X0Y3.CLKIN2
- Clock network: cmp_dmtd_clk_pll/PLL_ADV_ML_NEW_DIVCLK
---------------------------------------------------------------------------------
-Slack: 2.630ns (max period limit - period)
- Period: 50.000ns
- Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKFB)
- Physical resource: cmp_dmtd_clk_pll/PLL_ADV/CLKFBOUT
- Logical resource: cmp_dmtd_clk_pll/PLL_ADV/CLKFBOUT
- Location pin: PLL_ADV_X0Y3.CLKFBOUT
- Clock network: pllout_clk_fb_dmtd
---------------------------------------------------------------------------------
-Slack: 2.630ns (max period limit - period)
- Period: 50.000ns
- Max period limit: 52.630ns (19.001MHz) (Tpllper_CLKIN)
- Physical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Logical resource: cmp_sys_clk_pll/PLL_ADV/CLKIN1
- Location pin: PLL_ADV_X0Y1.CLKIN2
- Clock network: clk_20m_vcxo
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_clk_125m_pllref_p_i = PERIOD TIMEGRP
-"clk_125m_pllref_p_i" 8 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 6.250ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_125m_pllref_p_i = PERIOD TIMEGRP "clk_125m_pllref_p_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.750ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK20
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-Slack: 1.750ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK21
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-Slack: 4.875ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.125ns (320.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK0
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_clk_125m_pllref_n_i = PERIOD TIMEGRP
-"clk_125m_pllref_n_i" 8 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 9018 paths analyzed, 1707 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 6.711ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_1 (SLICE_X32Y74.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.774ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_1 (FF)
- Requirement: 4.000ns
- Data Path Delay: 3.170ns (Levels of Logic = 1)
- Clock Path Skew: -0.021ns (0.237 - 0.258)
- Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
- Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y78.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D6 net (fanout=7) 0.975 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
- SLICE_X32Y74.SR net (fanout=30) 1.034 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- SLICE_X32Y74.CLK Tsrck 0.455 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_1
- ------------------------------------------------- ---------------------------
- Total 3.170ns (1.161ns logic, 2.009ns route)
- (36.6% logic, 63.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_0 (SLICE_X32Y74.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.785ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_0 (FF)
- Requirement: 4.000ns
- Data Path Delay: 3.159ns (Levels of Logic = 1)
- Clock Path Skew: -0.021ns (0.237 - 0.258)
- Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
- Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y78.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D6 net (fanout=7) 0.975 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
- SLICE_X32Y74.SR net (fanout=30) 1.034 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- SLICE_X32Y74.CLK Tsrck 0.444 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_0
- ------------------------------------------------- ---------------------------
- Total 3.159ns (1.150ns logic, 2.009ns route)
- (36.4% logic, 63.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_2 (SLICE_X32Y74.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.808ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_2 (FF)
- Requirement: 4.000ns
- Data Path Delay: 3.136ns (Levels of Logic = 1)
- Clock Path Skew: -0.021ns (0.237 - 0.258)
- Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
- Destination Clock: clk_125m_pllref_BUFG falling at 4.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y78.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D6 net (fanout=7) 0.975 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/sync_reset_refclk/sync2
- SLICE_X39Y71.D Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv1_INV_0
- SLICE_X32Y74.SR net (fanout=30) 1.034 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_synced_refclk_inv
- SLICE_X32Y74.CLK Tsrck 0.421 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_f_2
- ------------------------------------------------- ---------------------------
- Total 3.136ns (1.127ns logic, 2.009ns route)
- (35.9% logic, 64.1% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_clk_125m_pllref_n_i = PERIOD TIMEGRP "clk_125m_pllref_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point U_GTP/ch1_disp_pipe_1 (SLICE_X37Y107.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.393ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_GTP/ch1_disp_pipe_0 (FF)
- Destination: U_GTP/ch1_disp_pipe_1 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.393ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_GTP/ch1_disp_pipe_0 to U_GTP/ch1_disp_pipe_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X37Y107.AQ Tcko 0.198 U_GTP/ch1_disp_pipe<1>
- U_GTP/ch1_disp_pipe_0
- SLICE_X37Y107.BX net (fanout=1) 0.136 U_GTP/ch1_disp_pipe<0>
- SLICE_X37Y107.CLK Tckdi (-Th) -0.059 U_GTP/ch1_disp_pipe<1>
- U_GTP/ch1_disp_pipe_1
- ------------------------------------------------- ---------------------------
- Total 0.393ns (0.257ns logic, 0.136ns route)
- (65.4% logic, 34.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_x_2 (SLICE_X29Y101.CX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.395ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_x_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.397ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.036 - 0.034)
- Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_x_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X28Y101.CQ Tcko 0.200 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_2
- SLICE_X29Y101.CX net (fanout=1) 0.138 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm<2>
- SLICE_X29Y101.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_x<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_x_2
- ------------------------------------------------- ---------------------------
- Total 0.397ns (0.259ns logic, 0.138ns route)
- (65.2% logic, 34.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_3 (SLICE_X16Y68.A4), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.419ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_4 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_3 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.419ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_4 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X16Y68.CQ Tcko 0.200 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay<4>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_4
- SLICE_X16Y68.A4 net (fanout=1) 0.098 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay<4>
- SLICE_X16Y68.CLK Tah (-Th) -0.121 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay<4>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/Mmux_GND_233_o_PWR_136_o_mux_11_OUT41
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/tx_sync_delay_3
- ------------------------------------------------- ---------------------------
- Total 0.419ns (0.321ns logic, 0.098ns route)
- (76.6% logic, 23.4% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_125m_pllref_n_i = PERIOD TIMEGRP "clk_125m_pllref_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.750ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK20
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK20
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-Slack: 1.750ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 6.250ns (160.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK21
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK21
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-Slack: 4.875ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.125ns (320.000MHz) (Tgtpcper_TXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/TXUSRCLK0
- Location pin: GTPA1_DUAL_X1Y0.TXUSRCLK0
- Clock network: clk_125m_pllref_BUFG
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk_125m_gtp_n_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.125ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_125m_gtp_n_i = PERIOD TIMEGRP "clk_125m_gtp_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.875ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.125ns (320.000MHz) (Tgtpcper_CLKIN)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Location pin: GTPA1_DUAL_X1Y0.CLKINEAST1
- Clock network: clk_125m_gtp
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk_125m_gtp_p_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.125ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_clk_125m_gtp_p_i = PERIOD TIMEGRP "clk_125m_gtp_p_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.875ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.125ns (320.000MHz) (Tgtpcper_CLKIN)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/CLK01
- Location pin: GTPA1_DUAL_X1Y0.CLKINEAST1
- Clock network: clk_125m_gtp
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_clk_125m_p_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.124ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TStdc_clk_125m_p_i = PERIOD TIMEGRP "tdc_clk_125m_p_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKBRDCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKBRDCLK
- Location pin: RAMB8_X3Y20.CLKBRDCLK
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKBRDCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKBRDCLK
- Location pin: RAMB8_X3Y23.CLKBRDCLK
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y48.CLKA
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns
-HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 460627 paths analyzed, 10037 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.949ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_2 (ILOGIC_X4Y3.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.051ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_2 (FF)
- Requirement: 8.000ns
- Data Path Delay: 8.334ns (Levels of Logic = 0)
- Clock Path Skew: 0.420ns (0.931 - 0.511)
- Source Clock: clk_125m_mezz rising at 0.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 to cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y48.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- cmp_tdc_clks_rsts_mgment/internal_rst_synch_1
- ILOGIC_X4Y3.SR net (fanout=699) 7.153 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- ILOGIC_X4Y3.CLK0 Tisrck 0.734 N1121
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_2
- ------------------------------------------------- ---------------------------
- Total 8.334ns (1.181ns logic, 7.153ns route)
- (14.2% logic, 85.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_4 (ILOGIC_X4Y1.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.063ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_4 (FF)
- Requirement: 8.000ns
- Data Path Delay: 8.322ns (Levels of Logic = 0)
- Clock Path Skew: 0.420ns (0.931 - 0.511)
- Source Clock: clk_125m_mezz rising at 0.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 to cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y48.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- cmp_tdc_clks_rsts_mgment/internal_rst_synch_1
- ILOGIC_X4Y1.SR net (fanout=699) 7.141 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- ILOGIC_X4Y1.CLK0 Tisrck 0.734 N1119
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_4
- ------------------------------------------------- ---------------------------
- Total 8.322ns (1.181ns logic, 7.141ns route)
- (14.2% logic, 85.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_6 (ILOGIC_X4Y0.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.063ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_6 (FF)
- Requirement: 8.000ns
- Data Path Delay: 8.322ns (Levels of Logic = 0)
- Clock Path Skew: 0.420ns (0.931 - 0.511)
- Source Clock: clk_125m_mezz rising at 0.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_clks_rsts_mgment/internal_rst_synch_1 to cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_6
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y48.AQ Tcko 0.447 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- cmp_tdc_clks_rsts_mgment/internal_rst_synch_1
- ILOGIC_X4Y0.SR net (fanout=699) 7.141 cmp_tdc_clks_rsts_mgment/internal_rst_synch<1>
- ILOGIC_X4Y0.CLK0 Tisrck 0.734 N1117
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/acam_start01_o_6
- ------------------------------------------------- ---------------------------
- Total 8.322ns (1.181ns logic, 7.141ns route)
- (14.2% logic, 85.8% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc (SLICE_X40Y57.D6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.421ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc (FF)
- Destination: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.421ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising at 8.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc to cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X40Y57.DQ Tcko 0.200 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- SLICE_X40Y57.D6 net (fanout=24) 0.031 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- SLICE_X40Y57.CLK Tah (-Th) -0.190 cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc_rstpot
- cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/tstamp_wr_cyc
- ------------------------------------------------- ---------------------------
- Total 0.421ns (0.390ns logic, 0.031ns route)
- (92.6% logic, 7.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0 (SLICE_X54Y56.A6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.421ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0 (FF)
- Destination: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.421ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising at 8.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0 to cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X54Y56.AQ Tcko 0.200 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<3>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0
- SLICE_X54Y56.A6 net (fanout=3) 0.031 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<0>
- SLICE_X54Y56.CLK Tah (-Th) -0.190 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<3>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/Mmux_prer[15]_PWR_513_o_mux_6_OUT17
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_0
- ------------------------------------------------- ---------------------------
- Total 0.421ns (0.390ns logic, 0.031ns route)
- (92.6% logic, 7.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8 (SLICE_X54Y58.A6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.421ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8 (FF)
- Destination: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.421ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising at 8.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8 to cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X54Y58.AQ Tcko 0.200 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<12>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8
- SLICE_X54Y58.A6 net (fanout=4) 0.031 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<8>
- SLICE_X54Y58.CLK Tah (-Th) -0.190 cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer<12>
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/Mmux_prer[15]_PWR_513_o_mux_6_OUT151
- cmp_tdc_mezz/cmp_I2C_master/U_Wrapped_I2C/Wrapped_I2C/prer_8
- ------------------------------------------------- ---------------------------
- Total 0.421ns (0.390ns logic, 0.031ns route)
- (92.6% logic, 7.4% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_tdc_clk_125m_n_i = PERIOD TIMEGRP "tdc_clk_125m_n_i" 8 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKBRDCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKBRDCLK
- Location pin: RAMB8_X3Y20.CLKBRDCLK
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKBRDCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKBRDCLK
- Location pin: RAMB8_X3Y23.CLKBRDCLK
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Logical resource: cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram/CLKA
- Location pin: RAMB16_X2Y48.CLKA
- Clock network: clk_125m_mezz
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_p_i" 5 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clk_p_i = PERIOD TIMEGRP "p2l_clk_p_i" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.075ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Location pin: BUFIO2_X4Y21.I
- Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_n_i" 5 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_p2l_clk_n_i = PERIOD TIMEGRP "p2l_clk_n_i" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.075ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Location pin: BUFIO2_X4Y21.I
- Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD TIMEGRP
-"cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD TIMEGRP
- "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 4.075ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Logical resource: cmp_gn4124_core/cmp_clk_in/P_clk_bufio2_inst/I
- Location pin: BUFIO2_X4Y21.I
- Clock network: cmp_gn4124_core/cmp_clk_in/P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: ts_ignore_crossclock = MAXDELAY FROM TIMEGRP "clk_62m5_sys"
-TO TIMEGRP "tdc_clk_125m_p_i" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 13 paths analyzed, 13 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 5.726ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (SLICE_X7Y108.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 4.274ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.726ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X7Y108.SR net (fanout=469) 3.875 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X7Y108.CLK Trck 0.267 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- ------------------------------------------------- ---------------------------
- Total 5.726ns (0.973ns logic, 4.753ns route)
- (17.0% logic, 83.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_locked_0 (SLICE_X37Y56.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 5.702ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 (FF)
- Destination: cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_locked_0 (FF)
- Requirement: 10.000ns
- Data Path Delay: 4.298ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 to cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_locked_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y90.BQ Tcko 0.391 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1
- SLICE_X37Y56.AX net (fanout=5) 3.844 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<1>
- SLICE_X37Y56.CLK Tdick 0.063 cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_locked<1>
- cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_locked_0
- ------------------------------------------------- ---------------------------
- Total 4.298ns (0.454ns logic, 3.844ns route)
- (10.6% logic, 89.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/wrabbit_utc_p (SLICE_X28Y62.A2), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.287ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 (FF)
- Destination: cmp_tdc_mezz/wrabbit_utc_p (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.713ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1 to cmp_tdc_mezz/wrabbit_utc_p
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y90.BQ Tcko 0.391 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int_1
- SLICE_X28Y62.A2 net (fanout=5) 2.981 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_occr_out_lock_int<1>
- SLICE_X28Y62.CLK Tas 0.341 cmp_tdc_mezz/wrabbit_utc_p
- cmp_tdc_mezz/wrabbit_utc_p_rstpot
- cmp_tdc_mezz/wrabbit_utc_p
- ------------------------------------------------- ---------------------------
- Total 3.713ns (0.732ns logic, 2.981ns route)
- (19.7% logic, 80.3% route)
-
---------------------------------------------------------------------------------
-Hold Paths: ts_ignore_crossclock = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "tdc_clk_125m_p_i" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X48Y40.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.456ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/mfifo/w_idx_gray_0 (FF)
- Destination: cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.456ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/mfifo/w_idx_gray_0 to cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X51Y41.AQ Tcko 0.198 cmp_tdc_clk_crossing/mfifo/w_idx_gray<2>
- cmp_tdc_clk_crossing/mfifo/w_idx_gray_0
- SLICE_X48Y40.AX net (fanout=2) 0.328 cmp_tdc_clk_crossing/mfifo/w_idx_gray<0>
- SLICE_X48Y40.CLK Tdh (-Th) 0.070 cmp_tdc_clk_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_0
- ------------------------------------------------- ---------------------------
- Total 0.456ns (0.128ns logic, 0.328ns route)
- (28.1% logic, 71.9% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X48Y40.DI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.456ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/mfifo/w_idx_gray_1 (FF)
- Destination: cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_1 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.456ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/mfifo/w_idx_gray_1 to cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X51Y41.CQ Tcko 0.198 cmp_tdc_clk_crossing/mfifo/w_idx_gray<2>
- cmp_tdc_clk_crossing/mfifo/w_idx_gray_1
- SLICE_X48Y40.DI net (fanout=2) 0.225 cmp_tdc_clk_crossing/mfifo/w_idx_gray<1>
- SLICE_X48Y40.CLK Tdh (-Th) -0.033 cmp_tdc_clk_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_1
- ------------------------------------------------- ---------------------------
- Total 0.456ns (0.231ns logic, 0.225ns route)
- (50.7% logic, 49.3% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (SLICE_X48Y40.CI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.470ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/mfifo/w_idx_gray_2 (FF)
- Destination: cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.470ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_mezz rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/mfifo/w_idx_gray_2 to cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X51Y41.DQ Tcko 0.198 cmp_tdc_clk_crossing/mfifo/w_idx_gray<2>
- cmp_tdc_clk_crossing/mfifo/w_idx_gray_2
- SLICE_X48Y40.CI net (fanout=2) 0.222 cmp_tdc_clk_crossing/mfifo/w_idx_gray<2>
- SLICE_X48Y40.CLK Tdh (-Th) -0.050 cmp_tdc_clk_crossing/mfifo/w_idx_shift_r_3<1>
- cmp_tdc_clk_crossing/mfifo/Mshreg_w_idx_shift_r_3_2
- ------------------------------------------------- ---------------------------
- Total 0.470ns (0.248ns logic, 0.222ns route)
- (52.8% logic, 47.2% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: ts_ignore_crossclock2 = MAXDELAY FROM TIMEGRP
-"tdc_clk_125m_p_i" TO TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 40 paths analyzed, 38 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 3.217ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_mezz/cmp_wrabbit_synch/wrabbit_en_sync_0 (SLICE_X35Y49.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.783ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_0 (FF)
- Destination: cmp_tdc_mezz/cmp_wrabbit_synch/wrabbit_en_sync_0 (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.217ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_0 to cmp_tdc_mezz/cmp_wrabbit_synch/wrabbit_en_sync_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y31.AQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg<3>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg_0
- SLICE_X35Y49.AX net (fanout=3) 2.746 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/wrabbit_ctrl_reg<0>
- SLICE_X35Y49.CLK Tdick 0.063 cmp_tdc_mezz/cmp_wrabbit_synch/wrabbit_en_sync<1>
- cmp_tdc_mezz/cmp_wrabbit_synch/wrabbit_en_sync_0
- ------------------------------------------------- ---------------------------
- Total 3.217ns (0.471ns logic, 2.746ns route)
- (14.6% logic, 85.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg_1 (SLICE_X23Y87.C6), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.951ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_lock_en_1 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg_1 (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.049ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_lock_en_1 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X26Y59.DQ Tcko 0.447 cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_lock_en<1>
- cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_lock_en_1
- SLICE_X23Y87.D6 net (fanout=2) 1.903 cmp_tdc_mezz/cmp_wrabbit_synch/clk_aux_lock_en<1>
- SLICE_X23Y87.D Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg<1>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/Mmux_rwaddr_reg[4]_rddata_reg[31]_wide_mux_8_OUT143
- SLICE_X23Y87.C6 net (fanout=1) 0.118 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rwaddr_reg[4]_rddata_reg[31]_wide_mux_8_OUT<1>
- SLICE_X23Y87.CLK Tas 0.322 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg<1>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg_1_dpot
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/rddata_reg_1
- ------------------------------------------------- ---------------------------
- Total 3.049ns (1.028ns logic, 2.021ns route)
- (33.7% logic, 66.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clks_rsts_mgment/dac_word_18 (SLICE_X44Y28.B1), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 7.886ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_18 (FF)
- Destination: cmp_tdc_clks_rsts_mgment/dac_word_18 (FF)
- Requirement: 10.000ns
- Data Path Delay: 2.114ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_18 to cmp_tdc_clks_rsts_mgment/dac_word_18
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X36Y32.DQ Tcko 0.408 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word<18>
- cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word_18
- SLICE_X44Y28.B1 net (fanout=2) 1.417 cmp_tdc_mezz/cmp_tdc_core/reg_control_block/dac_word<18>
- SLICE_X44Y28.CLK Tas 0.289 cmp_tdc_clks_rsts_mgment/dac_word<23>
- cmp_tdc_clks_rsts_mgment/Mmux_dac_word[23]_dac_word_i[23]_mux_15_OUT101
- cmp_tdc_clks_rsts_mgment/dac_word_18
- ------------------------------------------------- ---------------------------
- Total 2.114ns (0.697ns logic, 1.417ns route)
- (33.0% logic, 67.0% route)
-
---------------------------------------------------------------------------------
-Hold Paths: ts_ignore_crossclock2 = MAXDELAY FROM TIMEGRP "tdc_clk_125m_p_i" TO TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (SLICE_X56Y40.CI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.367ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/sfifo/w_idx_bnry_4 (FF)
- Destination: cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_4 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.367ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/sfifo/w_idx_bnry_4 to cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y41.BQ Tcko 0.198 cmp_tdc_clk_crossing/sfifo/w_idx_bnry<2>
- cmp_tdc_clk_crossing/sfifo/w_idx_bnry_4
- SLICE_X56Y40.CI net (fanout=2) 0.119 cmp_tdc_clk_crossing/sfifo/w_idx_bnry<4>
- SLICE_X56Y40.CLK Tdh (-Th) -0.050 cmp_tdc_clk_crossing/sfifo/r_idx_shift_a_3<1>
- cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_4
- ------------------------------------------------- ---------------------------
- Total 0.367ns (0.248ns logic, 0.119ns route)
- (67.6% logic, 32.4% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_0 (SLICE_X56Y40.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.420ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/sfifo/w_idx_gray_0 (FF)
- Destination: cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.420ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/sfifo/w_idx_gray_0 to cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y41.CMUX Tshcko 0.244 cmp_tdc_clk_crossing/sfifo/w_idx_bnry<2>
- cmp_tdc_clk_crossing/sfifo/w_idx_gray_0
- SLICE_X56Y40.DX net (fanout=1) 0.276 cmp_tdc_clk_crossing/sfifo/w_idx_gray<0>
- SLICE_X56Y40.CLK Tdh (-Th) 0.100 cmp_tdc_clk_crossing/sfifo/r_idx_shift_a_3<1>
- cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_0
- ------------------------------------------------- ---------------------------
- Total 0.420ns (0.144ns logic, 0.276ns route)
- (34.3% logic, 65.7% route)
---------------------------------------------------------------------------------
-
-Paths for end point cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_1 (SLICE_X56Y40.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.444ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_tdc_clk_crossing/sfifo/w_idx_gray_1 (FF)
- Destination: cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_1 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.444ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: cmp_tdc_clk_crossing/sfifo/w_idx_gray_1 to cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X58Y41.AQ Tcko 0.200 cmp_tdc_clk_crossing/sfifo/w_idx_gray<2>
- cmp_tdc_clk_crossing/sfifo/w_idx_gray_1
- SLICE_X56Y40.BX net (fanout=1) 0.324 cmp_tdc_clk_crossing/sfifo/w_idx_gray<1>
- SLICE_X56Y40.CLK Tdh (-Th) 0.080 cmp_tdc_clk_crossing/sfifo/r_idx_shift_a_3<1>
- cmp_tdc_clk_crossing/sfifo/Mshreg_w_idx_shift_r_3_1
- ------------------------------------------------- ---------------------------
- Total 0.444ns (0.120ns logic, 0.324ns route)
- (27.0% logic, 73.0% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO
-TIMEGRP "clk_125m_pllref_n_i" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 1097 paths analyzed, 291 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 6.668ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_GTP/Mshreg_ch1_rst_synced (SLICE_X56Y105.AI), 3 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 3.332ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_GTP/Mshreg_ch1_rst_synced (FF)
- Requirement: 10.000ns
- Data Path Delay: 6.668ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_GTP/Mshreg_ch1_rst_synced
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X39Y80.A5 net (fanout=66) 2.746 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X39Y80.AMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/rst_n_i_link_timer_restart_OR_241_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/serdes_rst_o1
- SLICE_X56Y105.AI net (fanout=3) 3.124 phy_rst
- SLICE_X56Y105.CLK Tds 0.038 U_GTP/ch1_rst_synced
- U_GTP/Mshreg_ch1_rst_synced
- ------------------------------------------------- ---------------------------
- Total 6.668ns (0.798ns logic, 5.870ns route)
- (12.0% logic, 88.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 3.968ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_pdown_int (FF)
- Destination: U_GTP/Mshreg_ch1_rst_synced (FF)
- Requirement: 10.000ns
- Data Path Delay: 6.032ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_pdown_int to U_GTP/Mshreg_ch1_rst_synced
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X26Y67.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_pdown_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_pdown_int
- SLICE_X39Y80.A3 net (fanout=4) 2.110 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_pdown_int
- SLICE_X39Y80.AMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/rst_n_i_link_timer_restart_OR_241_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/serdes_rst_o1
- SLICE_X56Y105.AI net (fanout=3) 3.124 phy_rst
- SLICE_X56Y105.CLK Tds 0.038 U_GTP/ch1_rst_synced
- U_GTP/Mshreg_ch1_rst_synced
- ------------------------------------------------- ---------------------------
- Total 6.032ns (0.798ns logic, 5.234ns route)
- (13.2% logic, 86.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 5.264ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_reset_o (FF)
- Destination: U_GTP/Mshreg_ch1_rst_synced (FF)
- Requirement: 10.000ns
- Data Path Delay: 4.736ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_reset_o to U_GTP/Mshreg_ch1_rst_synced
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y82.AQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_reset_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_reset_o
- SLICE_X39Y80.A2 net (fanout=5) 0.814 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_mcr_reset_o
- SLICE_X39Y80.AMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/rst_n_i_link_timer_restart_OR_241_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/serdes_rst_o1
- SLICE_X56Y105.AI net (fanout=3) 3.124 phy_rst
- SLICE_X56Y105.CLK Tds 0.038 U_GTP/ch1_rst_synced
- U_GTP/Mshreg_ch1_rst_synced
- ------------------------------------------------- ---------------------------
- Total 4.736ns (0.798ns logic, 3.938ns route)
- (16.8% logic, 83.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1 (SLICE_X22Y48.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 3.525ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1 (FF)
- Requirement: 10.000ns
- Data Path Delay: 6.475ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X22Y48.SR net (fanout=469) 4.666 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X22Y48.CLK Trck 0.225 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1
- ------------------------------------------------- ---------------------------
- Total 6.475ns (0.931ns logic, 5.544ns route)
- (14.4% logic, 85.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync0 (SLICE_X22Y48.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 3.533ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync0 (FF)
- Requirement: 10.000ns
- Data Path Delay: 6.467ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X22Y48.SR net (fanout=469) 4.666 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X22Y48.CLK Trck 0.217 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync1
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_escr_tm_valid_sync0
- ------------------------------------------------- ---------------------------
- Total 6.467ns (0.923ns logic, 5.544ns route)
- (14.3% logic, 85.7% route)
-
---------------------------------------------------------------------------------
-Hold Paths: ts_ignore_xclock1 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "clk_125m_pllref_n_i" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_4 (SLICE_X26Y102.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.491ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_4 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_4 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.491ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_4 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X26Y101.CQ Tcko 0.234 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray<6>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_4
- SLICE_X26Y102.AX net (fanout=1) 0.216 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray<4>
- SLICE_X26Y102.CLK Tckdi (-Th) -0.041 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm<6>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_4
- ------------------------------------------------- ---------------------------
- Total 0.491ns (0.275ns logic, 0.216ns route)
- (56.0% logic, 44.0% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_5 (SLICE_X26Y102.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.529ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_5 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_5 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.529ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_5 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X26Y101.DMUX Tshcko 0.266 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray<6>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_5
- SLICE_X26Y102.BX net (fanout=1) 0.222 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray<5>
- SLICE_X26Y102.CLK Tckdi (-Th) -0.041 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm<6>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_gray_xm_5
- ------------------------------------------------- ---------------------------
- Total 0.529ns (0.307ns logic, 0.222ns route)
- (58.0% logic, 42.0% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/cntr_utc_14 (SLICE_X33Y56.D6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.548ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_utc_14 (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/cntr_utc_14 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.548ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_utc_14 to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/cntr_utc_14
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X31Y56.CQ Tcko 0.198 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_utc<15>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_utc_14
- SLICE_X33Y56.D6 net (fanout=3) 0.135 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_utc<14>
- SLICE_X33Y56.CLK Tah (-Th) -0.215 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/cntr_utc<14>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Mmux_cntr_utc[39]_adj_utc[39]_mux_34_OUT61
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/cntr_utc_14
- ------------------------------------------------- ---------------------------
- Total 0.548ns (0.413ns logic, 0.135ns route)
- (75.4% logic, 24.6% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP
-"clk_125m_pllref_p_i" TO TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 247 paths analyzed, 212 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 3.987ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_4 (SLICE_X22Y96.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.013ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_4 (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.987ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y78.DQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- SLICE_X31Y92.B4 net (fanout=3) 1.439 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- SLICE_X31Y92.BMUX Tilo 0.313 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/tags_masked_1<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/rst_n_i_inv1
- SLICE_X22Y96.SR net (fanout=9) 1.560 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/rst_n_i_inv
- SLICE_X22Y96.CLK Trck 0.228 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin<5>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_4
- ------------------------------------------------- ---------------------------
- Total 3.987ns (0.988ns logic, 2.999ns route)
- (24.8% logic, 75.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_5 (SLICE_X22Y96.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 6.024ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_5 (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.976ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y78.DQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- SLICE_X31Y92.B4 net (fanout=3) 1.439 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_sync_power_down/sync2
- SLICE_X31Y92.BMUX Tilo 0.313 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/tags_masked_1<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/rst_n_i_inv1
- SLICE_X22Y96.SR net (fanout=9) 1.560 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/rst_n_i_inv
- SLICE_X22Y96.CLK Trck 0.217 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin<5>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_PCS/U_TX_FIFO/U_Inferred_FIFO/wcb_bin_5
- ------------------------------------------------- ---------------------------
- Total 3.976ns (0.977ns logic, 2.999ns route)
- (24.6% logic, 75.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5 (SLICE_X15Y58.D4), 3 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 6.099ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utchi_int_5 (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5 (FF)
- Requirement: 10.000ns
- Data Path Delay: 3.901ns (Levels of Logic = 3)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utchi_int_5 to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X25Y60.BQ Tcko 0.391 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utchi_int<7>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utchi_int_5
- SLICE_X25Y57.C4 net (fanout=1) 0.881 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utchi_int<5>
- SLICE_X25Y57.CMUX Tilo 0.313 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_nsec<8>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT342_SW0
- SLICE_X25Y57.A5 net (fanout=1) 0.744 N2174
- SLICE_X25Y57.A Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_nsec<8>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT342
- SLICE_X15Y58.D4 net (fanout=1) 0.991 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT341
- SLICE_X15Y58.CLK Tas 0.322 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg<5>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT343
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- ------------------------------------------------- ---------------------------
- Total 3.901ns (1.285ns logic, 2.616ns route)
- (32.9% logic, 67.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.090ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_nsec_int_5 (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5 (FF)
- Requirement: 10.000ns
- Data Path Delay: 2.910ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_nsec_int_5 to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y58.BQ Tcko 0.408 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_nsec_int<7>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_nsec_int_5
- SLICE_X25Y57.A4 net (fanout=1) 0.930 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_nsec_int<5>
- SLICE_X25Y57.A Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_nsec<8>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT342
- SLICE_X15Y58.D4 net (fanout=1) 0.991 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT341
- SLICE_X15Y58.CLK Tas 0.322 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg<5>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT343
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- ------------------------------------------------- ---------------------------
- Total 2.910ns (0.989ns logic, 1.921ns route)
- (34.0% logic, 66.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 7.374ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utclo_int_5 (FF)
- Destination: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5 (FF)
- Requirement: 10.000ns
- Data Path Delay: 2.626ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utclo_int_5 to U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y55.BQ Tcko 0.408 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utclo_int<7>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utclo_int_5
- SLICE_X25Y57.A1 net (fanout=1) 0.646 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/ppsg_cntr_utclo_int<5>
- SLICE_X25Y57.A Tilo 0.259 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/adj_nsec<8>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT342
- SLICE_X15Y58.D4 net (fanout=1) 0.991 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT341
- SLICE_X15Y58.CLK Tas 0.322 U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg<5>
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/Mmux_rddata_reg[31]_rddata_reg[31]_mux_48_OUT343
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/Uwb_slave/rddata_reg_5
- ------------------------------------------------- ---------------------------
- Total 2.626ns (0.989ns logic, 1.637ns route)
- (37.7% logic, 62.3% route)
-
---------------------------------------------------------------------------------
-Hold Paths: ts_ignore_xclock2 = MAXDELAY FROM TIMEGRP "clk_125m_pllref_p_i" TO TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_11 (SLICE_X16Y76.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.448ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_11 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_11 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.448ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_11 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_11
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X17Y74.DQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<11>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_11
- SLICE_X16Y76.DX net (fanout=1) 0.202 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<11>
- SLICE_X16Y76.CLK Tckdi (-Th) -0.048 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o<11>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_11
- ------------------------------------------------- ---------------------------
- Total 0.448ns (0.246ns logic, 0.202ns route)
- (54.9% logic, 45.1% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_9 (SLICE_X16Y76.BX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.457ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_9 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_9 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.457ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_9 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_9
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X17Y74.BQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<11>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_9
- SLICE_X16Y76.BX net (fanout=1) 0.211 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<9>
- SLICE_X16Y76.CLK Tckdi (-Th) -0.048 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o<11>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_9
- ------------------------------------------------- ---------------------------
- Total 0.457ns (0.246ns logic, 0.211ns route)
- (53.8% logic, 46.2% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_27 (SLICE_X16Y75.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.506ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_27 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_27 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.506ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_27 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_27
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X17Y75.DQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<27>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r_27
- SLICE_X16Y75.DX net (fanout=1) 0.260 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/cntr_tx_r<27>
- SLICE_X16Y75.CLK Tckdi (-Th) -0.048 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o<27>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/txts_timestamp_o_27
- ------------------------------------------------- ---------------------------
- Total 0.506ns (0.246ns logic, 0.260ns route)
- (48.6% logic, 51.4% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP
-"U_GTP_ch1_rx_divclk" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 192 paths analyzed, 119 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 9.819ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/d_p_d0 (SLICE_X51Y10.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.181ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/d_p_d0 (FF)
- Requirement: 10.000ns
- Data Path Delay: 9.819ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/d_p_d0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X51Y10.SR net (fanout=469) 7.968 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X51Y10.CLK Trck 0.267 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/d_p_d0
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/d_p_d0
- ------------------------------------------------- ---------------------------
- Total 9.819ns (0.973ns logic, 8.846ns route)
- (9.9% logic, 90.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext (SLICE_X50Y10.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.216ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext (FF)
- Requirement: 10.000ns
- Data Path Delay: 9.784ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X50Y10.SR net (fanout=469) 7.968 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X50Y10.CLK Trck 0.232 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext
- ------------------------------------------------- ---------------------------
- Total 9.784ns (0.938ns logic, 8.846ns route)
- (9.6% logic, 90.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/ready (SLICE_X50Y10.SR), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.264ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/PERIPH/rst_net_n_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/ready (FF)
- Requirement: 10.000ns
- Data Path Delay: 9.736ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/PERIPH/rst_net_n_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/ready
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X18Y89.AQ Tcko 0.447 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A6 net (fanout=66) 0.878 U_WR_CORE/WRPC/PERIPH/rst_net_n_o
- SLICE_X31Y89.A Tilo 0.259 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/rst_n_i_inv1_INV_0
- SLICE_X50Y10.SR net (fanout=469) 7.968 U_WR_CORE/WRPC/MINI_NIC/U_Wrapped_Minic/U_WB_Slave/eic_irq_controller_inst/rst_n_i_inv
- SLICE_X50Y10.CLK Trck 0.184 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/in_ext
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_Sync_Done/ready
- ------------------------------------------------- ---------------------------
- Total 9.736ns (0.890ns logic, 8.846ns route)
- (9.1% logic, 90.9% route)
-
---------------------------------------------------------------------------------
-Hold Paths: ts_x3 = MAXDELAY FROM TIMEGRP "clk_62m5_sys" TO TIMEGRP "U_GTP_ch1_rx_divclk" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb_s0 (SLICE_X5Y87.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.448ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb_s0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.448ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb_s0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X4Y86.AQ Tcko 0.200 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb
- SLICE_X5Y87.AX net (fanout=1) 0.189 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb
- SLICE_X5Y87.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb_s2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_MDIO_WB/mdio_wr_spec_bslide_lwb_s0
- ------------------------------------------------- ---------------------------
- Total 0.448ns (0.259ns logic, 0.189ns route)
- (57.8% logic, 42.2% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_0 (SLICE_X59Y27.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.471ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_0 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.471ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_0 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X58Y25.AQ Tcko 0.200 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray<2>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_0
- SLICE_X59Y27.AX net (fanout=2) 0.212 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray<0>
- SLICE_X59Y27.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_0
- ------------------------------------------------- ---------------------------
- Total 0.471ns (0.259ns logic, 0.212ns route)
- (55.0% logic, 45.0% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_3 (SLICE_X59Y27.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.490ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_3 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_3 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.490ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_62m5_sys rising
- Destination Clock: phy_rx_rbclk rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_3 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y27.AQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray<4>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_3
- SLICE_X59Y27.DX net (fanout=2) 0.233 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray<3>
- SLICE_X59Y27.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/rcb_gray_xm_3
- ------------------------------------------------- ---------------------------
- Total 0.490ns (0.257ns logic, 0.233ns route)
- (52.4% logic, 47.6% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_rx_divclk" TO
-TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 141 paths analyzed, 47 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 9.139ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i (SLICE_X25Y95.A5), 5 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 0.861ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_error (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i (FF)
- Requirement: 10.000ns
- Data Path Delay: 9.139ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_error to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X55Y47.CMUX Tshcko 0.461 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_ready
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_error
- SLICE_X57Y37.D2 net (fanout=10) 2.099 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_error
- SLICE_X57Y37.DMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_pending<2>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/pcs_fab_o_dvalid1
- SLICE_X25Y95.A5 net (fanout=12) 5.944 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rxpcs_fab_dvalid
- SLICE_X25Y95.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i_glue_set
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- ------------------------------------------------- ---------------------------
- Total 9.139ns (1.096ns logic, 8.043ns route)
- (12.0% logic, 88.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 1.111ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_wr_toggle (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i (FF)
- Requirement: 10.000ns
- Data Path Delay: 8.889ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_wr_toggle to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X54Y47.CQ Tcko 0.408 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_wr_toggle
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_wr_toggle
- SLICE_X57Y37.D5 net (fanout=39) 1.902 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_wr_toggle
- SLICE_X57Y37.DMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_pending<2>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/pcs_fab_o_dvalid1
- SLICE_X25Y95.A5 net (fanout=12) 5.944 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rxpcs_fab_dvalid
- SLICE_X25Y95.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i_glue_set
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- ------------------------------------------------- ---------------------------
- Total 8.889ns (1.043ns logic, 7.846ns route)
- (11.7% logic, 88.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 1.458ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_sof (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i (FF)
- Requirement: 10.000ns
- Data Path Delay: 8.542ns (Levels of Logic = 2)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_sof to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X59Y53.CMUX Tshcko 0.461 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/an_idle_cntr<1>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_sof
- SLICE_X57Y37.D4 net (fanout=15) 1.502 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/fifo_sof
- SLICE_X57Y37.DMUX Tilo 0.313 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_pending<2>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/pcs_fab_o_dvalid1
- SLICE_X25Y95.A5 net (fanout=12) 5.944 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/rxpcs_fab_dvalid
- SLICE_X25Y95.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i_glue_set
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/regs_towb_ep_dsr_lact_i
- ------------------------------------------------- ---------------------------
- Total 8.542ns (1.096ns logic, 7.446ns route)
- (12.8% logic, 87.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (SLICE_X36Y70.C1), 16 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 4.667ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.333ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y53.CQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1
- SLICE_X49Y53.B4 net (fanout=1) 0.971 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<1>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.C1 net (fanout=6) 1.276 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.412 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_G
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.333ns (1.580ns logic, 3.753ns route)
- (29.6% logic, 70.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 4.734ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.266ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y53.DQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0
- SLICE_X49Y53.B1 net (fanout=1) 0.904 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.C1 net (fanout=6) 1.276 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.412 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_G
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.266ns (1.580ns logic, 3.686ns route)
- (30.0% logic, 70.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 4.863ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.137ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y53.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4
- SLICE_X49Y53.B3 net (fanout=1) 0.831 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<4>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.C1 net (fanout=6) 1.276 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.412 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_G
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.137ns (1.524ns logic, 3.613ns route)
- (29.7% logic, 70.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (SLICE_X36Y70.D5), 16 paths
---------------------------------------------------------------------------------
-Slack (setup paths): 4.742ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.258ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y53.CQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_1
- SLICE_X49Y53.B4 net (fanout=1) 0.971 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<1>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.D5 net (fanout=6) 1.206 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.407 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_F
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.258ns (1.575ns logic, 3.683ns route)
- (30.0% logic, 70.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 4.809ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.191ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X52Y53.DQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_0
- SLICE_X49Y53.B1 net (fanout=1) 0.904 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<0>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.D5 net (fanout=6) 1.206 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.407 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_F
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.191ns (1.575ns logic, 3.616ns route)
- (30.3% logic, 69.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup paths): 4.938ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3 (FF)
- Requirement: 10.000ns
- Data Path Delay: 5.062ns (Levels of Logic = 4)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y53.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val_4
- SLICE_X49Y53.B3 net (fanout=1) 0.831 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<4>
- SLICE_X49Y53.B Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X49Y53.A5 net (fanout=1) 0.187 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>
- SLICE_X49Y53.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/lcr_final_val<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>2
- SLICE_X48Y69.A6 net (fanout=1) 1.319 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>1
- SLICE_X48Y69.A Tilo 0.203 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o<15>3
- SLICE_X36Y70.D5 net (fanout=6) 1.206 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/GND_113_o_an_rx_val_i[15]_equal_15_o
- SLICE_X36Y70.CLK Tas 0.407 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23_F
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3-In23
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/U_AUTONEGOTIATION/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 5.062ns (1.519ns logic, 3.543ns route)
- (30.0% logic, 70.0% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_x4 = MAXDELAY FROM TIMEGRP "U_GTP_ch1_rx_divclk" TO TIMEGRP "clk_62m5_sys" 10 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_8_0 (SLICE_X48Y17.DI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.344ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_5 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_8_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.344ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_5 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_8_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y17.BQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o<7>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_5
- SLICE_X48Y17.DI net (fanout=1) 0.113 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o<5>
- SLICE_X48Y17.CLK Tdh (-Th) -0.033 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/sreg_match_class<5>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_8_0
- ------------------------------------------------- ---------------------------
- Total 0.344ns (0.231ns logic, 0.113ns route)
- (67.2% logic, 32.8% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_xm_0 (SLICE_X59Y29.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.394ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_0 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_xm_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.394ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_0 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_xm_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X58Y29.AQ Tcko 0.200 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray<5>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_0
- SLICE_X59Y29.AX net (fanout=1) 0.135 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray<0>
- SLICE_X59Y29.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_xm<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Rx_Clock_Align_FIFO/U_FIFO/U_Inferred_FIFO/wcb_gray_xm_0
- ------------------------------------------------- ---------------------------
- Total 0.394ns (0.259ns logic, 0.135ns route)
- (65.7% logic, 34.3% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_5_0 (SLICE_X48Y18.CI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.454ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_5_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.454ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_62m5_sys rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_5_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y18.CQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o_2
- SLICE_X48Y18.CI net (fanout=1) 0.206 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/pclass_o<2>
- SLICE_X48Y18.CLK Tdh (-Th) -0.050 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_Gen_Status/sreg_is_hp
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/U_match_buffer/Mshreg_q_o_5_0
- ------------------------------------------------- ---------------------------
- Total 0.454ns (0.248ns logic, 0.206ns route)
- (54.6% logic, 45.4% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD TIMEGRP
-"U_GTP/ch1_gtp_clkout_int<1>" 125 MHz HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 0.925ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD TIMEGRP "U_GTP/ch1_gtp_clkout_int<1>"
- 125 MHz HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 7.075ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 0.925ns (1081.081MHz) (Tbufper_I)
- Physical resource: U_GTP/gen_with_channel1.U_Rbclk_buf_ch1/I
- Logical resource: U_GTP/gen_with_channel1.U_Rbclk_buf_ch1/I
- Location pin: BUFIO2_X4Y27.I
- Clock network: U_GTP/ch1_gtp_clkout_int<1>
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_ = MAXDELAY FROM TIMEGRP "skew_limit" TO TIMEGRP "FFS" 2
-ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 6 paths analyzed, 6 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 1.443ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0 (SLICE_X4Y110.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.557ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0 (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.443ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_dmtd rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X1Y110.AQ Tcko 0.391 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- SLICE_X4Y110.AX net (fanout=2) 0.916 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- SLICE_X4Y110.CLK Tdick 0.136 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0
- ------------------------------------------------- ---------------------------
- Total 1.443ns (0.527ns logic, 0.916ns route)
- (36.5% logic, 63.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0 (SLICE_X2Y107.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.886ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0 (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.114ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising
- Destination Clock: clk_dmtd rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X2Y109.DQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X2Y107.AX net (fanout=2) 0.581 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X2Y107.CLK Tdick 0.086 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0
- ------------------------------------------------- ---------------------------
- Total 1.114ns (0.533ns logic, 0.581ns route)
- (47.8% logic, 52.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in (SLICE_X2Y109.D5), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.912ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.088ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: clk_125m_pllref_BUFG rising at 0.000ns
- Destination Clock: clk_125m_pllref_BUFG rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X2Y109.DQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X2Y109.D5 net (fanout=2) 0.368 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X2Y109.CLK Tas 0.273 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in_INV_203_o1_INV_0
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in
- ------------------------------------------------- ---------------------------
- Total 1.088ns (0.720ns logic, 0.368ns route)
- (66.2% logic, 33.8% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_ = MAXDELAY FROM TIMEGRP "skew_limit" TO TIMEGRP "FFS" 2 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in (SLICE_X1Y110.A6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.434ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.434ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising at 8.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X1Y110.AQ Tcko 0.198 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- SLICE_X1Y110.A6 net (fanout=2) 0.021 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- SLICE_X1Y110.CLK Tah (-Th) -0.215 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in_INV_203_o1_INV_0
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in
- ------------------------------------------------- ---------------------------
- Total 0.434ns (0.413ns logic, 0.021ns route)
- (95.2% logic, 4.8% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (SLICE_X7Y108.A6), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.436ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.436ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising at 8.000ns
- Destination Clock: clk_125m_mezz rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X7Y108.AQ Tcko 0.198 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X7Y108.A6 net (fanout=2) 0.023 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X7Y108.CLK Tah (-Th) -0.215 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in_INV_203_o1_INV_0
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- ------------------------------------------------- ---------------------------
- Total 0.436ns (0.413ns logic, 0.023ns route)
- (94.7% logic, 5.3% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0 (SLICE_X4Y108.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.460ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.460ns (Levels of Logic = 0)
- Positive Clock Path Skew: 0.000ns
- Source Clock: clk_125m_mezz rising
- Destination Clock: clk_dmtd rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X7Y108.AQ Tcko 0.198 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X4Y108.AX net (fanout=2) 0.214 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in
- SLICE_X4Y108.CLK Tckdi (-Th) -0.048 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0
- ------------------------------------------------- ---------------------------
- Total 0.460ns (0.246ns logic, 0.214ns route)
- (53.5% logic, 46.5% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_trig" TO TIMEGRP
-"FFS" 2 ns DATAPATHONLY;
-For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).
-
- 3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors)
- Maximum delay is 1.831ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0 (SLICE_X46Y68.DX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.169ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0 (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.831ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_125m_pllref_BUFG falling
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D3 net (fanout=2) 0.483 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a1
- SLICE_X46Y68.DX net (fanout=2) 0.562 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- SLICE_X46Y68.CLK Tdick 0.136 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- ------------------------------------------------- ---------------------------
- Total 1.831ns (0.786ns logic, 1.045ns route)
- (42.9% logic, 57.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0 (SLICE_X47Y69.AX), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.265ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0 (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.735ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D3 net (fanout=2) 0.483 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a1
- SLICE_X47Y69.AX net (fanout=2) 0.539 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- SLICE_X47Y69.CLK Tdick 0.063 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync1
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0
- ------------------------------------------------- ---------------------------
- Total 1.735ns (0.713ns logic, 1.022ns route)
- (41.1% logic, 58.9% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (SLICE_X47Y70.C1), 1 path
---------------------------------------------------------------------------------
-Slack (setup paths): 0.609ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Requirement: 2.000ns
- Data Path Delay: 1.391ns (Levels of Logic = 1)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y70.C1 net (fanout=2) 0.678 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y70.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o_rstpot
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- ------------------------------------------------- ---------------------------
- Total 1.391ns (0.713ns logic, 0.678ns route)
- (51.3% logic, 48.7% route)
-
---------------------------------------------------------------------------------
-Hold Paths: TS_RXTS = MAXDELAY FROM TIMEGRP "rx_ts_trig" TO TIMEGRP "FFS" 2 ns DATAPATHONLY;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (SLICE_X47Y70.C1), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.704ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.704ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising at 8.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y70.C1 net (fanout=2) 0.291 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y70.CLK Tah (-Th) -0.215 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o_rstpot
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- ------------------------------------------------- ---------------------------
- Total 0.704ns (0.413ns logic, 0.291ns route)
- (58.7% logic, 41.3% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0 (SLICE_X47Y69.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.971ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.971ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_125m_pllref_BUFG rising
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D3 net (fanout=2) 0.274 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D Tilo 0.156 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a1
- SLICE_X47Y69.AX net (fanout=2) 0.284 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- SLICE_X47Y69.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync1
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_r/sync0
- ------------------------------------------------- ---------------------------
- Total 0.971ns (0.413ns logic, 0.558ns route)
- (42.5% logic, 57.5% route)
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0 (SLICE_X46Y68.DX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.973ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.973ns (Levels of Logic = 1)
- Positive Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising
- Destination Clock: clk_125m_pllref_BUFG falling
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X47Y70.CQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D3 net (fanout=2) 0.274 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o
- SLICE_X47Y71.D Tilo 0.156 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a1
- SLICE_X46Y68.DX net (fanout=2) 0.297 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/rx_trigger_a
- SLICE_X46Y68.CLK Tckdi (-Th) -0.048 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_EP_TSU/sync_ffs_rx_f/sync0
- ------------------------------------------------- ---------------------------
- Total 0.973ns (0.402ns logic, 0.571ns route)
- (41.3% logic, 58.7% route)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllout_clk_dmtd"
-TS_clk_20m_vcxo_i / 3.125 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 9425 paths analyzed, 1520 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 10.081ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2 (SLICE_X31Y100.CE), 36 paths
---------------------------------------------------------------------------------
-Slack (setup path): 5.919ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.886ns (Levels of Logic = 2)
- Clock Path Skew: -1.436ns (3.534 - 4.970)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X8Y96.AQ Tcko 0.408 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<15>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12
- SLICE_X0Y104.A1 net (fanout=4) 2.157 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<12>
- SLICE_X0Y104.BMUX Topab 0.469 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<4>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.340 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- ------------------------------------------------- ---------------------------
- Total 7.886ns (1.476ns logic, 6.410ns route)
- (18.7% logic, 81.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.035ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.755ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.AQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8
- SLICE_X0Y103.C3 net (fanout=4) 1.857 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<8>
- SLICE_X0Y103.COUT Topcyc 0.295 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.340 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- ------------------------------------------------- ---------------------------
- Total 7.755ns (1.563ns logic, 6.192ns route)
- (20.2% logic, 79.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.107ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.683ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.DQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11
- SLICE_X0Y103.D3 net (fanout=4) 1.820 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- SLICE_X0Y103.COUT Topcyd 0.260 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.340 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_2
- ------------------------------------------------- ---------------------------
- Total 7.683ns (1.528ns logic, 6.155ns route)
- (19.9% logic, 80.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1 (SLICE_X31Y100.CE), 36 paths
---------------------------------------------------------------------------------
-Slack (setup path): 5.935ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.870ns (Levels of Logic = 2)
- Clock Path Skew: -1.436ns (3.534 - 4.970)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X8Y96.AQ Tcko 0.408 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<15>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12
- SLICE_X0Y104.A1 net (fanout=4) 2.157 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<12>
- SLICE_X0Y104.BMUX Topab 0.469 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<4>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.324 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- ------------------------------------------------- ---------------------------
- Total 7.870ns (1.460ns logic, 6.410ns route)
- (18.6% logic, 81.4% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.051ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.739ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.AQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8
- SLICE_X0Y103.C3 net (fanout=4) 1.857 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<8>
- SLICE_X0Y103.COUT Topcyc 0.295 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.324 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- ------------------------------------------------- ---------------------------
- Total 7.739ns (1.547ns logic, 6.192ns route)
- (20.0% logic, 80.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.123ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.667ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.DQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11
- SLICE_X0Y103.D3 net (fanout=4) 1.820 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- SLICE_X0Y103.COUT Topcyd 0.260 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.324 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_1
- ------------------------------------------------- ---------------------------
- Total 7.667ns (1.512ns logic, 6.155ns route)
- (19.7% logic, 80.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3 (SLICE_X31Y100.CE), 36 paths
---------------------------------------------------------------------------------
-Slack (setup path): 5.943ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.862ns (Levels of Logic = 2)
- Clock Path Skew: -1.436ns (3.534 - 4.970)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X8Y96.AQ Tcko 0.408 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<15>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_12
- SLICE_X0Y104.A1 net (fanout=4) 2.157 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<12>
- SLICE_X0Y104.BMUX Topab 0.469 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<4>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.316 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- ------------------------------------------------- ---------------------------
- Total 7.862ns (1.452ns logic, 6.410ns route)
- (18.5% logic, 81.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.059ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.731ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.AQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_8
- SLICE_X0Y103.C3 net (fanout=4) 1.857 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<8>
- SLICE_X0Y103.COUT Topcyc 0.295 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.316 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- ------------------------------------------------- ---------------------------
- Total 7.731ns (1.539ns logic, 6.192ns route)
- (19.9% logic, 80.1% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 6.131ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 7.659ns (Levels of Logic = 3)
- Clock Path Skew: -1.451ns (3.534 - 4.985)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y95.DQ Tcko 0.447 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int_11
- SLICE_X0Y103.D3 net (fanout=4) 1.820 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/U_WB_SLAVE/spll_deglitch_thr_int<11>
- SLICE_X0Y103.COUT Topcyd 0.260 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_lut<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.CIN net (fanout=1) 0.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<3>
- SLICE_X0Y104.BMUX Tcinb 0.222 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/Mcompar_stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o_cy<5>
- SLICE_X23Y104.A3 net (fanout=19) 2.864 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/stab_cntr[15]_deglitch_threshold_i[15]_equal_14_o
- SLICE_X23Y104.A Tilo 0.259 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv1
- SLICE_X31Y100.CE net (fanout=6) 1.389 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/_n0153_inv
- SLICE_X31Y100.CLK Tceck 0.316 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o<3>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/tag_o_3
- ------------------------------------------------- ---------------------------
- Total 7.659ns (1.504ns logic, 6.155ns route)
- (19.6% logic, 80.4% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllout_clk_dmtd" TS_clk_20m_vcxo_i /
- 3.125 HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/d_in2out_0 (SLICE_X9Y102.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.014ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/in_ext (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/d_in2out_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.655ns (Levels of Logic = 0)
- Clock Path Skew: -0.118ns (2.184 - 2.302)
- Source Clock: clk_62m5_sys rising at 16.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/in_ext to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/d_in2out_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X8Y103.DQ Tcko 0.200 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/in_ext
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/in_ext
- SLICE_X9Y102.AX net (fanout=3) 0.396 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/in_ext
- SLICE_X9Y102.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/q_p_o
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/U_Sync_Start_Pulse/d_in2out_0
- ------------------------------------------------- ---------------------------
- Total 0.655ns (0.259ns logic, 0.396ns route)
- (39.5% logic, 60.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_in2out_0 (SLICE_X7Y105.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.209ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/in_ext (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_in2out_0 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.842ns (Levels of Logic = 0)
- Clock Path Skew: -0.126ns (2.184 - 2.310)
- Source Clock: clk_62m5_sys rising at 16.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/in_ext to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_in2out_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X5Y100.BQ Tcko 0.198 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_p_d0
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/in_ext
- SLICE_X7Y105.AX net (fanout=3) 0.585 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/in_ext
- SLICE_X7Y105.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_in2out<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_in2out_0
- ------------------------------------------------- ---------------------------
- Total 0.842ns (0.257ns logic, 0.585ns route)
- (30.5% logic, 69.5% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_8 (SLICE_X37Y96.AX), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.392ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_8 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_8 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.394ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.044 - 0.042)
- Source Clock: clk_dmtd rising at 16.000ns
- Destination Clock: clk_dmtd rising at 16.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_8 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_8
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X36Y96.AQ Tcko 0.200 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_8
- SLICE_X37Y96.AX net (fanout=2) 0.135 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int<8>
- SLICE_X37Y96.CLK Tckdi (-Th) -0.059 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o<11>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_8
- ------------------------------------------------- ---------------------------
- Total 0.394ns (0.259ns logic, 0.135ns route)
- (65.7% logic, 34.3% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_pllout_clk_dmtd = PERIOD TIMEGRP "pllout_clk_dmtd" TS_clk_20m_vcxo_i /
- 3.125 HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 14.270ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 1.730ns (578.035MHz) (Tbcper_I)
- Physical resource: cmp_clk_dmtd_buf/I0
- Logical resource: cmp_clk_dmtd_buf/I0
- Location pin: BUFGMUX_X2Y2.I0
- Clock network: pllout_clk_dmtd
---------------------------------------------------------------------------------
-Slack: 15.000ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 1.000ns (1000.000MHz) (Tcp)
- Physical resource: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2/CLK
- Logical resource: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/Mshreg_sync2/CLK
- Location pin: SLICE_X10Y106.CLK
- Clock network: clk_dmtd
---------------------------------------------------------------------------------
-Slack: 15.570ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 0.430ns (2325.581MHz) (Tcp)
- Physical resource: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/free_cntr<3>/CLK
- Logical resource: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/free_cntr_0/CK
- Location pin: SLICE_X20Y87.CLK
- Clock network: clk_dmtd
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_pllout_clk_sys = PERIOD TIMEGRP "pllout_clk_sys"
-TS_clk_20m_vcxo_i / 3.125 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 1673168 paths analyzed, 25653 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 14.800ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0 (SLICE_X12Y75.CE), 29 paths
---------------------------------------------------------------------------------
-Slack (setup path): 1.200ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.650ns (Levels of Logic = 4)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D6 net (fanout=5) 4.262 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.335 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- ------------------------------------------------- ---------------------------
- Total 14.650ns (1.708ns logic, 12.942ns route)
- (11.7% logic, 88.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.789ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.061ns (Levels of Logic = 3)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C3 net (fanout=5) 4.787 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.335 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- ------------------------------------------------- ---------------------------
- Total 14.061ns (1.449ns logic, 12.612ns route)
- (10.3% logic, 89.7% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 2.935ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_WBP_Mux/mux (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0 (FF)
- Requirement: 16.000ns
- Data Path Delay: 12.945ns (Levels of Logic = 5)
- Clock Path Skew: -0.006ns (0.502 - 0.508)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_WBP_Mux/mux to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y81.CMUX Tshcko 0.455 rst_sys_n
- U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A5 net (fanout=17) 1.713 U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_cyc_d0
- U_WR_CORE/WRPC/U_WBP_Mux/Mmux_ep_src_o_cyc11
- SLICE_X31Y91.D3 net (fanout=5) 0.521 U_WR_CORE/WRPC/ep_snk_in_cyc
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.335 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_0
- ------------------------------------------------- ---------------------------
- Total 12.945ns (2.031ns logic, 10.914ns route)
- (15.7% logic, 84.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3 (SLICE_X12Y75.CE), 29 paths
---------------------------------------------------------------------------------
-Slack (setup path): 1.220ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.630ns (Levels of Logic = 4)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D6 net (fanout=5) 4.262 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.315 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- ------------------------------------------------- ---------------------------
- Total 14.630ns (1.688ns logic, 12.942ns route)
- (11.5% logic, 88.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.809ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.041ns (Levels of Logic = 3)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C3 net (fanout=5) 4.787 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.315 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- ------------------------------------------------- ---------------------------
- Total 14.041ns (1.429ns logic, 12.612ns route)
- (10.2% logic, 89.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 2.955ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_WBP_Mux/mux (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3 (FF)
- Requirement: 16.000ns
- Data Path Delay: 12.925ns (Levels of Logic = 5)
- Clock Path Skew: -0.006ns (0.502 - 0.508)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_WBP_Mux/mux to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y81.CMUX Tshcko 0.455 rst_sys_n
- U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A5 net (fanout=17) 1.713 U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_cyc_d0
- U_WR_CORE/WRPC/U_WBP_Mux/Mmux_ep_src_o_cyc11
- SLICE_X31Y91.D3 net (fanout=5) 0.521 U_WR_CORE/WRPC/ep_snk_in_cyc
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.315 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_3
- ------------------------------------------------- ---------------------------
- Total 12.925ns (2.011ns logic, 10.914ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2 (SLICE_X12Y75.CE), 29 paths
---------------------------------------------------------------------------------
-Slack (setup path): 1.221ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.629ns (Levels of Logic = 4)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D6 net (fanout=5) 4.262 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.314 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- ------------------------------------------------- ---------------------------
- Total 14.629ns (1.687ns logic, 12.942ns route)
- (11.5% logic, 88.5% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.810ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 14.040ns (Levels of Logic = 3)
- Clock Path Skew: -0.036ns (0.594 - 0.630)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X19Y50.AQ Tcko 0.391 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C3 net (fanout=5) 4.787 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_WB_SLAVE/ep_ecr_tx_en_int
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.314 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- ------------------------------------------------- ---------------------------
- Total 14.040ns (1.428ns logic, 12.612ns route)
- (10.2% logic, 89.8% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 2.956ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_WBP_Mux/mux (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2 (FF)
- Requirement: 16.000ns
- Data Path Delay: 12.924ns (Levels of Logic = 5)
- Clock Path Skew: -0.006ns (0.502 - 0.508)
- Source Clock: clk_62m5_sys rising at 0.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.114ns
-
- Clock Uncertainty: 0.114ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.217ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_WBP_Mux/mux to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X24Y81.CMUX Tshcko 0.455 rst_sys_n
- U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A5 net (fanout=17) 1.713 U_WR_CORE/WRPC/U_WBP_Mux/mux
- SLICE_X31Y93.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_cyc_d0
- U_WR_CORE/WRPC/U_WBP_Mux/Mmux_ep_src_o_cyc11
- SLICE_X31Y91.D3 net (fanout=5) 0.521 U_WR_CORE/WRPC/ep_snk_in_cyc
- SLICE_X31Y91.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_out_ack
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/state_FSM_FFd2-In131
- SLICE_X33Y95.C5 net (fanout=9) 0.855 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/snk_valid
- SLICE_X33Y95.C Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n1001_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o1
- SLICE_X41Y72.D5 net (fanout=13) 2.514 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/regs_i_ecr_tx_en_o_error_p1_OR_275_o
- SLICE_X41Y72.D Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now1
- SLICE_X32Y87.A1 net (fanout=6) 2.467 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/abort_now
- SLICE_X32Y87.A Tilo 0.205 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CE net (fanout=15) 2.844 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/_n0565_inv
- SLICE_X12Y75.CLK Tceck 0.314 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o<3>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Tx_Framer/txtsu_ts_value_o_2
- ------------------------------------------------- ---------------------------
- Total 12.924ns (2.010ns logic, 10.914ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_pllout_clk_sys = PERIOD TIMEGRP "pllout_clk_sys" TS_clk_20m_vcxo_i / 3.125
- HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2 (SLICE_X4Y102.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.039ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 2.223ns (Levels of Logic = 1)
- Clock Path Skew: 1.425ns (4.961 - 3.536)
- Source Clock: clk_dmtd rising at 16.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Minimum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y106.AQ Tcko 0.421 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D5 net (fanout=10) 0.359 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D Tilo 0.191 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv1_INV_0
- SLICE_X4Y102.SR net (fanout=15) 1.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- SLICE_X4Y102.CLK Tremck (-Th) -0.170 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2
- ------------------------------------------------- ---------------------------
- Total 2.223ns (0.782ns logic, 1.441ns route)
- (35.2% logic, 64.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_1 (SLICE_X4Y102.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.052ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_1 (FF)
- Requirement: 0.000ns
- Data Path Delay: 2.236ns (Levels of Logic = 1)
- Clock Path Skew: 1.425ns (4.961 - 3.536)
- Source Clock: clk_dmtd rising at 16.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Minimum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_1
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y106.AQ Tcko 0.421 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D5 net (fanout=10) 0.359 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D Tilo 0.191 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv1_INV_0
- SLICE_X4Y102.SR net (fanout=15) 1.082 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- SLICE_X4Y102.CLK Tremck (-Th) -0.183 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_1
- ------------------------------------------------- ---------------------------
- Total 2.236ns (0.795ns logic, 1.441ns route)
- (35.6% logic, 64.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2 (SLICE_X4Y103.SR), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.052ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 2.234ns (Levels of Logic = 1)
- Clock Path Skew: 1.423ns (4.959 - 3.536)
- Source Clock: clk_dmtd rising at 16.000ns
- Destination Clock: clk_62m5_sys rising at 16.000ns
- Clock Uncertainty: 0.759ns
-
- Clock Uncertainty: 0.759ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.435ns
- Phase Error (PE): 0.538ns
-
- Minimum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2 to U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X10Y106.AQ Tcko 0.421 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D5 net (fanout=10) 0.359 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/sync_ffs_rst2/sync2
- SLICE_X10Y105.D Tilo 0.191 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv1_INV_0
- SLICE_X4Y103.SR net (fanout=15) 1.093 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Resync_Pulse/rst_n_i_inv
- SLICE_X4Y103.CLK Tremck (-Th) -0.170 U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in<2>
- U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/U_Sync_Start_Pulse/d_out2in_2
- ------------------------------------------------- ---------------------------
- Total 2.234ns (0.782ns logic, 1.452ns route)
- (35.0% logic, 65.0% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_pllout_clk_sys = PERIOD TIMEGRP "pllout_clk_sys" TS_clk_20m_vcxo_i / 3.125
- HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKAWRCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram1/CLKAWRCLK
- Location pin: RAMB8_X3Y20.CLKAWRCLK
- Clock network: clk_62m5_sys
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKAWRCLK
- Logical resource: cmp_tdc_clk_crossing/mfifo/ram/Mram_ram2/CLKAWRCLK
- Location pin: RAMB8_X3Y23.CLKAWRCLK
- Clock network: clk_62m5_sys
---------------------------------------------------------------------------------
-Slack: 12.876ns (period - min period limit)
- Period: 16.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer.U_Rx_Buffer/BUF_FIFO/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram/CLKA
- Logical resource: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_rx_buffer.U_Rx_Buffer/BUF_FIFO/U_Inferred_FIFO/U_FIFO_Ram/gen_single_clk.U_RAM_SC/Mram_ram/CLKA
- Location pin: RAMB16_X3Y16.CLKA
- Clock network: clk_62m5_sys
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk" TS_p2l_clk_p_i HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.575ns (period - min period limit)
- Period: 2.500ns
- Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Location pin: PLL_ADV_X0Y2.CLKOUT0
- Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
- Period: 5.000ns
- Low pulse: 2.500ns
- Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
- Period: 5.000ns
- High pulse: 2.500ns
- High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_0" TS_p2l_clk_n_i HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.575ns (period - min period limit)
- Period: 2.500ns
- Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Location pin: PLL_ADV_X0Y2.CLKOUT0
- Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
- Period: 5.000ns
- Low pulse: 2.500ns
- Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
- Period: 5.000ns
- High pulse: 2.500ns
- High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_1"
-TS_cmp_gn4124_core_cmp_clk_in_P_clk HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 2.800ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_buf_P_clk_1"
- TS_cmp_gn4124_core_cmp_clk_in_P_clk HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.575ns (period - min period limit)
- Period: 2.500ns
- Min period limit: 0.925ns (1081.081MHz) (Tpllper_CLKOUT(Foutmax))
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKOUT0
- Location pin: PLL_ADV_X0Y2.CLKOUT0
- Clock network: cmp_gn4124_core/cmp_clk_in/rx_pllout_xs_int
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min low pulse limit / (low pulse / period)))
- Period: 5.000ns
- Low pulse: 2.500ns
- Low pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-Slack: 2.200ns (period - (min high pulse limit / (high pulse / period)))
- Period: 5.000ns
- High pulse: 2.500ns
- High pulse limit: 1.400ns (Tdcmpw_CLKIN_200_250)
- Physical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Logical resource: cmp_gn4124_core/cmp_clk_in/rx_pll_adv_inst/CLKIN1
- Location pin: PLL_ADV_X0Y2.CLKIN1
- Clock network: cmp_gn4124_core/cmp_clk_in/buf_P_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP
-"U_GTP_ch1_rx_divclk" TS_U_GTP_ch1_gtp_clkout_int_1_ HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 20096 paths analyzed, 1911 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 7.831ns.
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4 (SLICE_X56Y80.SR), 2 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.169ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.742ns (Levels of Logic = 1)
- Clock Path Skew: -0.054ns (0.552 - 0.606)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y62.CQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- SLICE_X57Y53.A3 net (fanout=7) 2.234 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- SLICE_X57Y53.A Tilo 0.259 N103
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/reset_synced_rxclk_mdio_mcr_pdown_synced_OR_224_o1
- SLICE_X56Y80.SR net (fanout=23) 4.360 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/en_i_0
- SLICE_X56Y80.CLK Tsrck 0.442 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4
- ------------------------------------------------- ---------------------------
- Total 7.742ns (1.148ns logic, 6.594ns route)
- (14.8% logic, 85.2% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.624ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.287ns (Levels of Logic = 1)
- Clock Path Skew: -0.054ns (0.552 - 0.606)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y62.BQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2
- SLICE_X57Y53.A4 net (fanout=9) 1.779 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2
- SLICE_X57Y53.A Tilo 0.259 N103
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/reset_synced_rxclk_mdio_mcr_pdown_synced_OR_224_o1
- SLICE_X56Y80.SR net (fanout=23) 4.360 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/en_i_0
- SLICE_X56Y80.CLK Tsrck 0.442 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd4
- ------------------------------------------------- ---------------------------
- Total 7.287ns (1.148ns logic, 6.139ns route)
- (15.8% logic, 84.2% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3 (SLICE_X56Y80.SR), 2 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.180ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.731ns (Levels of Logic = 1)
- Clock Path Skew: -0.054ns (0.552 - 0.606)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y62.CQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- SLICE_X57Y53.A3 net (fanout=7) 2.234 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- SLICE_X57Y53.A Tilo 0.259 N103
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/reset_synced_rxclk_mdio_mcr_pdown_synced_OR_224_o1
- SLICE_X56Y80.SR net (fanout=23) 4.360 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/en_i_0
- SLICE_X56Y80.CLK Tsrck 0.431 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 7.731ns (1.137ns logic, 6.594ns route)
- (14.7% logic, 85.3% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 0.635ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3 (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.276ns (Levels of Logic = 1)
- Clock Path Skew: -0.054ns (0.552 - 0.606)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X44Y62.BQ Tcko 0.447 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_rx_reset/sync2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2
- SLICE_X57Y53.A4 net (fanout=9) 1.779 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_sync_power_down/sync2
- SLICE_X57Y53.A Tilo 0.259 N103
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/reset_synced_rxclk_mdio_mcr_pdown_synced_OR_224_o1
- SLICE_X56Y80.SR net (fanout=23) 4.360 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/en_i_0
- SLICE_X56Y80.CLK Tsrck 0.431 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/U_SYNC_DET/state_FSM_FFd3
- ------------------------------------------------- ---------------------------
- Total 7.276ns (1.137ns logic, 6.139ns route)
- (15.6% logic, 84.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend (SLICE_X57Y55.C4), 6 paths
---------------------------------------------------------------------------------
-Slack (setup path): 0.302ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_GTP/ch1_rx_data_o_4 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend (FF)
- Requirement: 8.000ns
- Data Path Delay: 7.657ns (Levels of Logic = 2)
- Clock Path Skew: -0.006ns (0.565 - 0.571)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_GTP/ch1_rx_data_o_4 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y104.CQ Tcko 0.447 U_GTP/ch1_rx_data_o<6>
- U_GTP/ch1_rx_data_o_4
- SLICE_X57Y63.A3 net (fanout=10) 5.287 U_GTP/ch1_rx_data_o<4>
- SLICE_X57Y63.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_epd
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o11
- SLICE_X57Y55.C4 net (fanout=2) 1.342 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o1
- SLICE_X57Y55.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_preamble_char
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/Mmux_GND_109_o_PWR_78_o_MUX_875_o11
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- ------------------------------------------------- ---------------------------
- Total 7.657ns (1.028ns logic, 6.629ns route)
- (13.4% logic, 86.6% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.290ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_GTP/ch1_rx_data_o_5 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend (FF)
- Requirement: 8.000ns
- Data Path Delay: 6.669ns (Levels of Logic = 2)
- Clock Path Skew: -0.006ns (0.565 - 0.571)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_GTP/ch1_rx_data_o_5 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y104.CMUX Tshcko 0.488 U_GTP/ch1_rx_data_o<6>
- U_GTP/ch1_rx_data_o_5
- SLICE_X57Y63.A2 net (fanout=8) 4.258 U_GTP/ch1_rx_data_o<5>
- SLICE_X57Y63.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_epd
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o11
- SLICE_X57Y55.C4 net (fanout=2) 1.342 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o1
- SLICE_X57Y55.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_preamble_char
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/Mmux_GND_109_o_PWR_78_o_MUX_875_o11
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- ------------------------------------------------- ---------------------------
- Total 6.669ns (1.069ns logic, 5.600ns route)
- (16.0% logic, 84.0% route)
-
---------------------------------------------------------------------------------
-Slack (setup path): 1.335ns (requirement - (data path - clock path skew + uncertainty))
- Source: U_GTP/ch1_rx_data_o_6 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend (FF)
- Requirement: 8.000ns
- Data Path Delay: 6.624ns (Levels of Logic = 2)
- Clock Path Skew: -0.006ns (0.565 - 0.571)
- Source Clock: phy_rx_rbclk rising at 0.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.035ns
-
- Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Total Input Jitter (TIJ): 0.000ns
- Discrete Jitter (DJ): 0.000ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: U_GTP/ch1_rx_data_o_6 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X48Y104.DQ Tcko 0.447 U_GTP/ch1_rx_data_o<6>
- U_GTP/ch1_rx_data_o_6
- SLICE_X57Y63.A5 net (fanout=7) 4.254 U_GTP/ch1_rx_data_o<6>
- SLICE_X57Y63.A Tilo 0.259 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_epd
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o11
- SLICE_X57Y55.C4 net (fanout=2) 1.342 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/PWR_78_o_phy_rx_k_i_AND_203_o1
- SLICE_X57Y55.CLK Tas 0.322 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_preamble_char
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/Mmux_GND_109_o_PWR_78_o_MUX_875_o11
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/d_is_extend
- ------------------------------------------------- ---------------------------
- Total 6.624ns (1.028ns logic, 5.596ns route)
- (15.5% logic, 84.5% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP "U_GTP_ch1_rx_divclk"
- TS_U_GTP_ch1_gtp_clkout_int_1_ HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point U_GTP/gen_with_channel1.U_sync_oen_ch1/Mshreg_sync2 (SLICE_X38Y102.BI), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.322ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_GTP/gen_with_channel1.U_sync_oen_ch1/sync0 (FF)
- Destination: U_GTP/gen_with_channel1.U_sync_oen_ch1/Mshreg_sync2 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.322ns (Levels of Logic = 0)
- Clock Path Skew: 0.000ns
- Source Clock: phy_rx_rbclk rising at 8.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_GTP/gen_with_channel1.U_sync_oen_ch1/sync0 to U_GTP/gen_with_channel1.U_sync_oen_ch1/Mshreg_sync2
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X38Y102.AQ Tcko 0.234 U_GTP/gen_with_channel1.U_sync_oen_ch1/sync2
- U_GTP/gen_with_channel1.U_sync_oen_ch1/sync0
- SLICE_X38Y102.BI net (fanout=1) 0.059 U_GTP/gen_with_channel1.U_sync_oen_ch1/sync0
- SLICE_X38Y102.CLK Tdh (-Th) -0.029 U_GTP/gen_with_channel1.U_sync_oen_ch1/sync2
- U_GTP/gen_with_channel1.U_sync_oen_ch1/Mshreg_sync2
- ------------------------------------------------- ---------------------------
- Total 0.322ns (0.263ns logic, 0.059ns route)
- (81.7% logic, 18.3% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_23 (SLICE_X48Y12.CE), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.362ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_23 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.361ns (Levels of Logic = 0)
- Clock Path Skew: -0.001ns (0.041 - 0.042)
- Source Clock: phy_rx_rbclk rising at 8.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_23
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y15.AQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- SLICE_X48Y12.CE net (fanout=19) 0.271 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- SLICE_X48Y12.CLK Tckce (-Th) 0.108 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs<23>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_23
- ------------------------------------------------- ---------------------------
- Total 0.361ns (0.090ns logic, 0.271ns route)
- (24.9% logic, 75.1% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_7 (SLICE_X48Y12.CE), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.366ns (requirement - (clock path skew + uncertainty - data path))
- Source: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2 (FF)
- Destination: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_7 (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.365ns (Levels of Logic = 0)
- Clock Path Skew: -0.001ns (0.041 - 0.042)
- Source Clock: phy_rx_rbclk rising at 8.000ns
- Destination Clock: phy_rx_rbclk rising at 8.000ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Fast Process Corner: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2 to U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_7
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X49Y15.AQ Tcko 0.198 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- SLICE_X48Y12.CE net (fanout=19) 0.271 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/stage2
- SLICE_X48Y12.CLK Tckce (-Th) 0.104 U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs<23>
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/regs_7
- ------------------------------------------------- ---------------------------
- Total 0.365ns (0.094ns logic, 0.271ns route)
- (25.8% logic, 74.2% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_U_GTP_ch1_rx_divclk = PERIOD TIMEGRP "U_GTP_ch1_rx_divclk"
- TS_U_GTP_ch1_gtp_clkout_int_1_ HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.750ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 6.250ns (160.000MHz) (Tgtpcper_RXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/RXUSRCLK21
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/RXUSRCLK21
- Location pin: GTPA1_DUAL_X1Y0.RXUSRCLK21
- Clock network: phy_rx_rbclk
---------------------------------------------------------------------------------
-Slack: 4.875ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.125ns (320.000MHz) (Tgtpcper_RXUSRCLK)
- Physical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/RXUSRCLK1
- Logical resource: U_GTP/U_GTP_TILE_INST/gtpa1_dual_i/RXUSRCLK1
- Location pin: GTPA1_DUAL_X1Y0.RXUSRCLK1
- Clock network: phy_rx_rbclk
---------------------------------------------------------------------------------
-Slack: 4.876ns (period - min period limit)
- Period: 8.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_backlog_ram/gen_single_clk.U_RAM_SC/Mram_ram/CLKAWRCLK
- Logical resource: U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter.U_packet_filter/U_backlog_ram/gen_single_clk.U_RAM_SC/Mram_ram/CLKAWRCLK
- Location pin: RAMB8_X2Y13.CLKAWRCLK
- Clock network: phy_rx_rbclk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk / 2 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.124ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Location pin: RAMB16_X2Y16.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Location pin: RAMB16_X3Y18.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Location pin: RAMB16_X2Y46.CLKB
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_0"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 / 2 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
- Minimum period is 3.124ns.
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_0"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Location pin: RAMB16_X2Y16.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Location pin: RAMB16_X3Y18.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Location pin: RAMB16_X2Y46.CLKB
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_1 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_xs_int_1"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 / 2 HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 component switching limit errors)
---------------------------------------------------------------------------------
-
-================================================================================
-Timing constraint: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1 = PERIOD
-TIMEGRP "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1"
-TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 PHASE 1.25 ns HIGH 50%;
-For more information, see Period Analysis in the Timing Closure User Guide (UG612).
-
- 5838 paths analyzed, 2324 endpoints analyzed, 0 failing endpoints
- 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
- Minimum period is 4.950ns.
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o (SLICE_X54Y55.D5), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.050ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.861ns (Levels of Logic = 1)
- Clock Path Skew: -0.014ns (0.564 - 0.578)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X51Y92.AQ Tcko 0.391 cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1
- cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1
- SLICE_X54Y55.D5 net (fanout=76) 4.063 cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd1
- SLICE_X54Y55.CLK Tas 0.407 cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o_rstpot_F
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o_rstpot
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- ------------------------------------------------- ---------------------------
- Total 4.861ns (0.798ns logic, 4.063ns route)
- (16.4% logic, 83.6% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o (SLICE_X54Y55.D6), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.104ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.804ns (Levels of Logic = 1)
- Clock Path Skew: -0.017ns (0.564 - 0.581)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3 to cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X51Y94.AQ Tcko 0.391 cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
- cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
- SLICE_X54Y55.D6 net (fanout=62) 4.006 cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_current_state_FSM_FFd3
- SLICE_X54Y55.CLK Tas 0.407 cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o_rstpot_F
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o_rstpot
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_valid_o
- ------------------------------------------------- ---------------------------
- Total 4.804ns (0.798ns logic, 4.006ns route)
- (16.6% logic, 83.4% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0 (SLICE_X55Y63.A3), 1 path
---------------------------------------------------------------------------------
-Slack (setup path): 0.107ns (requirement - (data path - clock path skew + uncertainty))
- Source: cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_0 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0 (FF)
- Requirement: 5.000ns
- Data Path Delay: 4.811ns (Levels of Logic = 1)
- Clock Path Skew: -0.007ns (0.576 - 0.583)
- Source Clock: cmp_gn4124_core/sys_clk rising at 1.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.075ns
-
- Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
- Total System Jitter (TSJ): 0.070ns
- Discrete Jitter (DJ): 0.132ns
- Phase Error (PE): 0.000ns
-
- Maximum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_0 to cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X53Y96.AMUX Tshcko 0.461 cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<6>
- cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o_0
- SLICE_X55Y63.A3 net (fanout=1) 4.028 cmp_gn4124_core/cmp_l2p_dma_master/ldm_arb_data_o<0>
- SLICE_X55Y63.CLK Tas 0.322 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<3>
- cmp_gn4124_core/cmp_l2p_arbiter/Mmux_GND_600_o_wbm_arb_data_i[31]_mux_2_OUT110
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t_0
- ------------------------------------------------- ---------------------------
- Total 4.811ns (0.783ns logic, 4.028ns route)
- (16.3% logic, 83.7% route)
-
---------------------------------------------------------------------------------
-
-Hold Paths: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (OLOGIC_X27Y50.D2), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.115ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.117ns (Levels of Logic = 0)
- Clock Path Skew: 0.002ns (0.246 - 0.244)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X59Y63.AMUX Tshcko 0.434 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<27>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_24
- OLOGIC_X27Y50.D2 net (fanout=1) 1.005 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<24>
- OLOGIC_X27Y50.CLKDIV Tosckd_D (-Th) 1.322 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.117ns (-0.888ns logic, 1.005ns route)
- (-759.0% logic, 859.0% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (OLOGIC_X27Y50.D1), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.163ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.185ns (Levels of Logic = 0)
- Clock Path Skew: 0.022ns (0.596 - 0.574)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X57Y67.AQ Tcko 0.368 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<10>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_8
- OLOGIC_X27Y50.D1 net (fanout=1) 1.130 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<8>
- OLOGIC_X27Y50.CLKDIV Tosckd_D (-Th) 1.313 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[8].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.185ns (-0.945ns logic, 1.130ns route)
- (-510.8% logic, 610.8% route)
-
---------------------------------------------------------------------------------
-
-Paths for end point cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m (OLOGIC_X27Y48.D2), 1 path
---------------------------------------------------------------------------------
-Slack (hold path): 0.173ns (requirement - (clock path skew + uncertainty - data path))
- Source: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25 (FF)
- Destination: cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m (FF)
- Requirement: 0.000ns
- Data Path Delay: 0.182ns (Levels of Logic = 0)
- Clock Path Skew: 0.009ns (0.253 - 0.244)
- Source Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Destination Clock: cmp_gn4124_core/sys_clk rising at 6.250ns
- Clock Uncertainty: 0.000ns
-
- Minimum Data Path at Slow Process Corner: cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25 to cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- Location Delay type Delay(ns) Physical Resource
- Logical Resource(s)
- ------------------------------------------------- -------------------
- SLICE_X59Y63.BMUX Tshcko 0.434 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_t<27>
- cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o_25
- OLOGIC_X27Y48.D2 net (fanout=1) 1.070 cmp_gn4124_core/cmp_l2p_arbiter/arb_ser_data_o<25>
- OLOGIC_X27Y48.CLKDIV Tosckd_D (-Th) 1.322 cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- cmp_gn4124_core/cmp_l2p_ser/cmp_data_out/loop0[9].loop3.oserdes_m
- ------------------------------------------------- ---------------------------
- Total 0.182ns (-0.888ns logic, 1.070ns route)
- (-487.9% logic, 587.9% route)
-
---------------------------------------------------------------------------------
-
-Component Switching Limit Checks: TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1 = PERIOD TIMEGRP
- "cmp_gn4124_core_cmp_clk_in_rx_pllout_x1_1"
- TS_cmp_gn4124_core_cmp_clk_in_buf_P_clk_1 PHASE 1.25 ns HIGH 50%;
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1/CLKA
- Location pin: RAMB16_X2Y16.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKA(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2/CLKA
- Location pin: RAMB16_X3Y18.CLKA
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-Slack: 1.876ns (period - min period limit)
- Period: 5.000ns
- Min period limit: 3.124ns (320.102MHz) (Trper_CLKB(Fmax))
- Physical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Logical resource: cmp_gn4124_core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem/CLKB
- Location pin: RAMB16_X2Y46.CLKB
- Clock network: cmp_gn4124_core/sys_clk
---------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Derived Constraints for TS_clk_20m_vcxo_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_clk_20m_vcxo_i | 50.000ns| 20.000ns| 46.250ns| 0| 0| 0| 1682593|
-| TS_pllout_clk_dmtd | 16.000ns| 10.081ns| N/A| 0| 0| 9425| 0|
-| TS_pllout_clk_sys | 16.000ns| 14.800ns| N/A| 0| 0| 1673168| 0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_p_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_p_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_p2l_clk_n_i
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_p2l_clk_n_i | 5.000ns| 0.925ns| 3.124ns| 0| 0| 0| 0|
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 3.124ns| 0| 0| 0| 0|
-| buf_P_clk_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_0 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 3.124ns| N/A| 0| 0| 0| 0|
-| _rx_pllout_x1_0 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_cmp_gn4124_core_cmp_clk_in_P_clk
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_cmp_gn4124_core_cmp_clk_in_P| 5.000ns| 0.925ns| 4.950ns| 0| 0| 0| 5838|
-|_clk | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.950ns| 0| 0| 0| 5838|
-| buf_P_clk_1 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
-| _rx_pllout_xs_int_1 | | | | | | | |
-| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.950ns| N/A| 0| 0| 5838| 0|
-| _rx_pllout_x1_1 | | | | | | | |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS_U_GTP_ch1_gtp_clkout_int_1_
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-| | Period | Actual Period | Timing Errors | Paths Analyzed |
-| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS_U_GTP_ch1_gtp_clkout_int_1_ | 8.000ns| 0.925ns| 7.831ns| 0| 0| 0| 20096|
-| TS_U_GTP_ch1_rx_divclk | 8.000ns| 7.831ns| N/A| 0| 0| 20096| 0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-All constraints were met.
-
-
-Data Sheet report:
------------------
-All values displayed in nanoseconds (ns)
-
-Clock to Setup on destination clock clk_20m_vcxo_i
--------------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 14.800| | | |
-clk_125m_pllref_n_i| 3.987| 1.587| | |
-clk_125m_pllref_p_i| 3.987| 1.587| | |
-tdc_clk_125m_n_i | 3.217| | | |
-tdc_clk_125m_p_i | 3.217| | | |
--------------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock clk_125m_pllref_n_i
--------------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 6.668| | | |
-clk_125m_pllref_n_i| 6.711| | 3.226| 1.495|
-clk_125m_pllref_p_i| 6.711| | 3.226| 1.495|
--------------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock clk_125m_pllref_p_i
--------------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 6.668| | | |
-clk_125m_pllref_n_i| 6.711| | 3.226| 1.495|
-clk_125m_pllref_p_i| 6.711| | 3.226| 1.495|
--------------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock p2l_clk_n_i
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-p2l_clk_n_i | 4.950| | | |
-p2l_clk_p_i | 4.950| | | |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock p2l_clk_p_i
----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
-p2l_clk_n_i | 4.950| | | |
-p2l_clk_p_i | 4.950| | | |
----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock tdc_clk_125m_n_i
-----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 5.726| | | |
-tdc_clk_125m_n_i| 7.949| | | |
-tdc_clk_125m_p_i| 7.949| | | |
-----------------+---------+---------+---------+---------+
-
-Clock to Setup on destination clock tdc_clk_125m_p_i
-----------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
-Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-----------------+---------+---------+---------+---------+
-clk_20m_vcxo_i | 5.726| | | |
-tdc_clk_125m_n_i| 7.949| | | |
-tdc_clk_125m_p_i| 7.949| | | |
-----------------+---------+---------+---------+---------+
-
-
-Timing summary:
----------------
-
-Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
-
-Constraints cover 2179911 paths, 0 nets, and 62686 connections
-
-Design statistics:
- Minimum period: 20.000ns{1} (Maximum frequency: 50.000MHz)
- Maximum path delay from/to any node: 9.819ns
-
-
-------------------------------------Footnotes-----------------------------------
-1) The minimum period statistic assumes all single cycle delays.
-
-Analysis completed Tue Jul 08 11:09:03 2014
---------------------------------------------------------------------------------
-
-Trace Settings:
--------------------------
-Trace Settings
-
-Peak Memory Usage: 322 MB
-
-
-
diff --git a/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map b/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
deleted file mode 100644
index ba0bc14..0000000
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.map
+++ /dev/null
@@ -1,222 +0,0 @@
-Release 13.4 Map O.87xd (nt)
-Xilinx Map Application Log File for Design 'wr_spec_tdc'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
-high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
-off -pr b -lc off -power off -o wr_spec_tdc_map.ncd wr_spec_tdc.ngd
-wr_spec_tdc.pcf
-Target Device : xc6slx45t
-Target Package : fgg484
-Target Speed : -3
-Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Tue Jul 08 10:59:56 2014
-
-Mapping design into LUTs...
-Running directed packing...
-Running delay-based LUT packing...
-Updating timing models...
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
- (.mrp).
-Running timing-driven placement...
-Total REAL time at the beginning of Placer: 44 secs
-Total CPU time at the beginning of Placer: 39 secs
-
-Phase 1.1 Initial Placement Analysis
-Phase 1.1 Initial Placement Analysis (Checksum:2f07b54b) REAL time: 48 secs
-
-Phase 2.7 Design Feasibility Check
-Phase 2.7 Design Feasibility Check (Checksum:2f07b54b) REAL time: 49 secs
-
-Phase 3.31 Local Placement Optimization
-Phase 3.31 Local Placement Optimization (Checksum:ed3fb313) REAL time: 49 secs
-
-Phase 4.2 Initial Placement for Architecture Specific Features
-
-Phase 4.2 Initial Placement for Architecture Specific Features
-(Checksum:2d826acd) REAL time: 1 mins 38 secs
-
-Phase 5.36 Local Placement Optimization
-Phase 5.36 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
-
-Phase 6.30 Global Clock Region Assignment
-Phase 6.30 Global Clock Region Assignment (Checksum:2d826acd) REAL time: 1 mins 38 secs
-
-Phase 7.3 Local Placement Optimization
-Phase 7.3 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
-
-Phase 8.5 Local Placement Optimization
-Phase 8.5 Local Placement Optimization (Checksum:2d826acd) REAL time: 1 mins 38 secs
-
-Phase 9.8 Global Placement
-........................
-..................................................................................................
-.................................................................................
-..................................................................................................................................
-..............................
-Phase 9.8 Global Placement (Checksum:9fd444c4) REAL time: 5 mins
-
-Phase 10.5 Local Placement Optimization
-Phase 10.5 Local Placement Optimization (Checksum:9fd444c4) REAL time: 5 mins 1 secs
-
-Phase 11.18 Placement Optimization
-Phase 11.18 Placement Optimization (Checksum:887f371b) REAL time: 5 mins 47 secs
-
-Phase 12.5 Local Placement Optimization
-Phase 12.5 Local Placement Optimization (Checksum:887f371b) REAL time: 5 mins 48 secs
-
-Phase 13.34 Placement Validation
-Phase 13.34 Placement Validation (Checksum:27e1a814) REAL time: 5 mins 48 secs
-
-Total REAL time to Placer completion: 6 mins 7 secs
-Total CPU time to Placer completion: 6 mins 1 secs
-Running post-placement packing...
-Writing output files...
-WARNING:PhysDesignRules:372 - Gated clock. Clock net
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
- is sourced by a combinatorial pin. This is not good design practice. Use the
- CE pin to control the loading of data into the flip-flop.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
- .U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
- READ_FIRST mode has certain restrictions. Make sure that there is no address
- collision. A read/write on one port and a write operation from the other port
- at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
- wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
- bits wide, A13-7 including A5 cannot be the same. Violating this restriction
- may result in the incorrect operation of the BRAM.
-WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
- (RAMB8BWER). 9K Block RAM initialization data, both user defined and
- default, may be incorrect and should not be used. For more information,
- please reference Xilinx Answer Record 39999.
-
-Design Summary
---------------
-
-Design Summary:
-Number of errors: 0
-Number of warnings: 9
-Slice Logic Utilization:
- Number of Slice Registers: 8,192 out of 54,576 15%
- Number used as Flip Flops: 8,166
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 24
- Number of Slice LUTs: 10,646 out of 27,288 39%
- Number used as logic: 10,382 out of 27,288 38%
- Number using O6 output only: 7,374
- Number using O5 output only: 777
- Number using O5 and O6: 2,231
- Number used as ROM: 0
- Number used as Memory: 67 out of 6,408 1%
- Number used as Dual Port RAM: 24
- Number using O6 output only: 24
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 43
- Number using O6 output only: 22
- Number using O5 output only: 0
- Number using O5 and O6: 21
- Number used exclusively as route-thrus: 197
- Number with same-slice register load: 122
- Number with same-slice carry load: 75
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 4,050 out of 6,822 59%
- Nummber of MUXCYs used: 2,388 out of 13,644 17%
- Number of LUT Flip Flop pairs used: 12,451
- Number with an unused Flip Flop: 4,848 out of 12,451 38%
- Number with an unused LUT: 1,805 out of 12,451 14%
- Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
- Number of unique control sets: 372
- Number of slice register sites lost
- to control set restrictions: 992 out of 54,576 1%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 152 out of 296 51%
- Number of LOCed IOBs: 152 out of 152 100%
- IOB Flip Flops: 57
- Number of bonded IPADs: 4 out of 16 25%
- Number of LOCed IPADs: 4 out of 4 100%
- Number of bonded OPADs: 2 out of 8 25%
- Number of LOCed OPADs: 2 out of 2 100%
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 62 out of 116 53%
- Number of RAMB8BWERs: 9 out of 232 3%
- Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
- Number used as BUFIO2s: 3
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 7 out of 16 43%
- Number used as BUFGs: 7
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
- Number used as ILOGIC2s: 41
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
- Number used as OLOGIC2s: 16
- Number used as OSERDES2s: 20
- Number of BSCANs: 1 out of 4 25%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 3 out of 58 5%
- Number of GTPA1_DUALs: 1 out of 2 50%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 3 out of 4 75%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-Average Fanout of Non-Clock Nets: 3.59
-
-Peak Memory Usage: 476 MB
-Total REAL time to MAP completion: 6 mins 19 secs
-Total CPU time to MAP completion: 6 mins 12 secs
-
-Mapping completed.
-See MAP report file "wr_spec_tdc_map.mrp" for details.
diff --git a/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp b/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp
deleted file mode 100644
index a76b7ce..0000000
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc_map.mrp
+++ /dev/null
@@ -1,1042 +0,0 @@
-Release 13.4 Map O.87xd (nt)
-Xilinx Mapping Report File for Design 'wr_spec_tdc'
-
-Design Information
-------------------
-Command Line : map -intstyle ise -p xc6slx45t-fgg484-3 -w -logic_opt off -ol
-high -xe c -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir
-off -pr b -lc off -power off -o wr_spec_tdc_map.ncd wr_spec_tdc.ngd
-wr_spec_tdc.pcf
-Target Device : xc6slx45t
-Target Package : fgg484
-Target Speed : -3
-Mapper Version : spartan6 -- $Revision: 1.55 $
-Mapped Date : Tue Jul 08 10:59:56 2014
-
-Design Summary
---------------
-Number of errors: 0
-Number of warnings: 9
-Slice Logic Utilization:
- Number of Slice Registers: 8,192 out of 54,576 15%
- Number used as Flip Flops: 8,166
- Number used as Latches: 2
- Number used as Latch-thrus: 0
- Number used as AND/OR logics: 24
- Number of Slice LUTs: 10,646 out of 27,288 39%
- Number used as logic: 10,382 out of 27,288 38%
- Number using O6 output only: 7,374
- Number using O5 output only: 777
- Number using O5 and O6: 2,231
- Number used as ROM: 0
- Number used as Memory: 67 out of 6,408 1%
- Number used as Dual Port RAM: 24
- Number using O6 output only: 24
- Number using O5 output only: 0
- Number using O5 and O6: 0
- Number used as Single Port RAM: 0
- Number used as Shift Register: 43
- Number using O6 output only: 22
- Number using O5 output only: 0
- Number using O5 and O6: 21
- Number used exclusively as route-thrus: 197
- Number with same-slice register load: 122
- Number with same-slice carry load: 75
- Number with other load: 0
-
-Slice Logic Distribution:
- Number of occupied Slices: 4,050 out of 6,822 59%
- Nummber of MUXCYs used: 2,388 out of 13,644 17%
- Number of LUT Flip Flop pairs used: 12,451
- Number with an unused Flip Flop: 4,848 out of 12,451 38%
- Number with an unused LUT: 1,805 out of 12,451 14%
- Number of fully used LUT-FF pairs: 5,798 out of 12,451 46%
- Number of unique control sets: 372
- Number of slice register sites lost
- to control set restrictions: 992 out of 54,576 1%
-
- A LUT Flip Flop pair for this architecture represents one LUT paired with
- one Flip Flop within a slice. A control set is a unique combination of
- clock, reset, set, and enable signals for a registered element.
- The Slice Logic Distribution report is not meaningful if the design is
- over-mapped for a non-slice resource or if Placement fails.
-
-IO Utilization:
- Number of bonded IOBs: 152 out of 296 51%
- Number of LOCed IOBs: 152 out of 152 100%
- IOB Flip Flops: 57
- Number of bonded IPADs: 4 out of 16 25%
- Number of LOCed IPADs: 4 out of 4 100%
- Number of bonded OPADs: 2 out of 8 25%
- Number of LOCed OPADs: 2 out of 2 100%
-
-Specific Feature Utilization:
- Number of RAMB16BWERs: 62 out of 116 53%
- Number of RAMB8BWERs: 9 out of 232 3%
- Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
- Number used as BUFIO2s: 3
- Number used as BUFIO2_2CLKs: 0
- Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
- Number used as BUFIO2FBs: 1
- Number used as BUFIO2FB_2CLKs: 0
- Number of BUFG/BUFGMUXs: 7 out of 16 43%
- Number used as BUFGs: 7
- Number used as BUFGMUX: 0
- Number of DCM/DCM_CLKGENs: 0 out of 8 0%
- Number of ILOGIC2/ISERDES2s: 61 out of 376 16%
- Number used as ILOGIC2s: 41
- Number used as ISERDES2s: 20
- Number of IODELAY2/IODRP2/IODRP2_MCBs: 2 out of 376 1%
- Number used as IODELAY2s: 2
- Number used as IODRP2s: 0
- Number used as IODRP2_MCBs: 0
- Number of OLOGIC2/OSERDES2s: 36 out of 376 9%
- Number used as OLOGIC2s: 16
- Number used as OSERDES2s: 20
- Number of BSCANs: 1 out of 4 25%
- Number of BUFHs: 0 out of 256 0%
- Number of BUFPLLs: 1 out of 8 12%
- Number of BUFPLL_MCBs: 0 out of 4 0%
- Number of DSP48A1s: 3 out of 58 5%
- Number of GTPA1_DUALs: 1 out of 2 50%
- Number of ICAPs: 0 out of 1 0%
- Number of MCBs: 0 out of 2 0%
- Number of PCIE_A1s: 0 out of 1 0%
- Number of PCILOGICSEs: 0 out of 2 0%
- Number of PLL_ADVs: 3 out of 4 75%
- Number of PMVs: 0 out of 1 0%
- Number of STARTUPs: 0 out of 1 0%
- Number of SUSPEND_SYNCs: 0 out of 1 0%
-
-Average Fanout of Non-Clock Nets: 3.59
-
-Peak Memory Usage: 476 MB
-Total REAL time to MAP completion: 6 mins 19 secs
-Total CPU time to MAP completion: 6 mins 12 secs
-
-Table of Contents
------------------
-Section 1 - Errors
-Section 2 - Warnings
-Section 3 - Informational
-Section 4 - Removed Logic Summary
-Section 5 - Removed Logic
-Section 6 - IOB Properties
-Section 7 - RPMs
-Section 8 - Guide Report
-Section 9 - Area Group and Partition Summary
-Section 10 - Timing Report
-Section 11 - Configuration String Information
-Section 12 - Control Set Information
-Section 13 - Utilization by Hierarchy
-
-Section 1 - Errors
-------------------
-
-Section 2 - Warnings
---------------------
-WARNING:PhysDesignRules:372 - Gated clock. Clock net
- cmp_tdc_mezz/cmp_tdc_core/data_engine_block/engine_st[3]_PWR_441_o_Mux_41_o
- is sourced by a combinatorial pin. This is not good design practice. Use the
- CE pin to control the loading of data into the flip-flop.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem6_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem1_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem2_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem5_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem4_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
- <U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_TX_P
- CS/U_TX_FIFO/U_Inferred_FIFO/Mram_mem3_RAMD_O> is incomplete. The signal does
- not drive any load pins in the design.
-WARNING:PhysDesignRules:2212 - Async clocking for BRAM (comp
- U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_Rx_Path/gen_with_packet_filter
- .U_packet_filter/U_microcode_ram/gen_dual_clk.U_RAM_DC/Mram_ram) port(s) with
- READ_FIRST mode has certain restrictions. Make sure that there is no address
- collision. A read/write on one port and a write operation from the other port
- at the same address is not allowed. RAMB16BWER, when both ports are 18 bits
- wide or smaller, A13-6 including A4 cannot be same. When any one port is 36
- bits wide, A13-7 including A5 cannot be the same. Violating this restriction
- may result in the incorrect operation of the BRAM.
-WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
- (RAMB8BWER). 9K Block RAM initialization data, both user defined and
- default, may be incorrect and should not be used. For more information,
- please reference Xilinx Answer Record 39999.
-
-Section 3 - Informational
--------------------------
-INFO:LIT:243 - Logical network tdc_in_fpga_2_i has no load.
-INFO:LIT:395 - The above info message is repeated 144 more times for the
- following (max. 5 shown):
- tdc_in_fpga_3_i,
- tdc_in_fpga_4_i,
- tdc_in_fpga_5_i,
- carrier_scl_b,
- carrier_sda_b
- To see the details of these info messages, please use the -detail switch.
-INFO:MapLib:562 - No environment variables are currently set.
-INFO:LIT:244 - All of the single ended outputs in this design are using slew
- rate limited output drivers. The delay on speed critical single ended outputs
- can be dramatically reduced by designating them as fast outputs.
-INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
- 0.000 to 85.000 Celsius)
-INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
- 1.260 Volts)
-INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
- Command Line Tools User Guide for information on generating a TSI report.
-INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
- (.mrp).
-INFO:Pack:1650 - Map created a placed design.
-
-Section 4 - Removed Logic Summary
----------------------------------
- 60 block(s) removed
- 3 block(s) optimized away
- 169 signal(s) removed
-
-Section 5 - Removed Logic
--------------------------
-
-The trimmed logic report below shows the logic removed from your design due to
-sourceless or loadless signals, and VCC or ground connections. If the removal
-of a signal or symbol results in the subsequent removal of an additional signal
-or symbol, the message explaining that second removal will be indented. This
-indentation will be repeated as a chain of related logic is removed.
-
-To quickly locate the original cause for the removal of a chain of logic, look
-above the place where that logic is listed in the trimming report, then locate
-the lines that are least indented (begin at the leftmost edge).
-
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master" (FF)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/cal_data_master_rstpot"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" is loadless and has
-been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/enable_rstpot" (ROM)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<5>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_5" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter5" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<5>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<4>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<3>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<2>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<1>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<0>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>_inv1_INV_0"
-(BUF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<8>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_8" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter8" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<8>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<7>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<6>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_cy<5>"
-(MUX) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<5>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<6>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<6>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_6" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter6" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<6>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<7>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<7>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_7" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter7" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<7>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<0>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<0>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_0" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<0>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<1>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<1>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_1" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter1" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<1>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<2>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<2>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_2" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter2" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<2>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<3>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<3>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_3" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter3" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<3>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_lut<4>"
-(ROM) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter<4>" is loadless and
-has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/counter_4" (FF) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter4" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/Mcount_counter_xor<4>"
-(XOR) removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" is loadless
-and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4" (FF)
-removed.
- The signal "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/state_FSM_FFd4-In" is
-loadless and has been removed.
- Loadless block "cmp_gn4124_core/cmp_p2l_des/cmp_data_in/_n0363_inv1" (ROM)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[10].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[11].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[12].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[13].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[14].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[15].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[1].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[2].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[3].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[4].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[5].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[6].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[7].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[8].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_data_in/loop0[9].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_dframe_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_gn4124_core/cmp_p2l_des/cmp_valid_in/loop0[0].loop3.iodelay_m" (IODELAY2)
-removed.
-Loadless block
-"cmp_tdc_mezz/cmp_tdc_core/data_formatting_block/Madd_un_nb_of_retrig_Madd25"
-(ROM) removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(127)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(126)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(125)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(124)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(123)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(122)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(121)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(120)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(119)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(118)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(117)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(116)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(115)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(114)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(113)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(112)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(111)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(110)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(109)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(108)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(107)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(106)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(105)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(104)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(103)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(102)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(101)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(100)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(99)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(98)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(97)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(96)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(95)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(94)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(93)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(92)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(91)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(90)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(89)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(88)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(87)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(86)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(85)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(84)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(83)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(82)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(81)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(80)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(79)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(78)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(77)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(76)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(75)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(74)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(73)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(72)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(71)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(70)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(69)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(68)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(67)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(66)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(65)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(64)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(63)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(62)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(61)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(60)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(59)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(58)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(57)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(56)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(55)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(54)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(53)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(52)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(51)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(50)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(49)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(48)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(47)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(46)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(45)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(44)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(43)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(42)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(41)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(40)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(39)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(38)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(37)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(36)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(35)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(34)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(33)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(32)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(31)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(30)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(29)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(28)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(27)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(26)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(25)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(24)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(23)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(22)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(21)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(20)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(19)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(18)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(17)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(16)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(15)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(14)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(13)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(12)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(11)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(10)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(9)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(8)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(7)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(6)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(5)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(4)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(3)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(2)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(1)" is
-sourceless and has been removed.
-The signal
-"cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/douta(0)" is
-sourceless and has been removed.
-
-Optimized Block(s):
-TYPE BLOCK
-GND XST_GND
-VCC XST_VCC
-GND cmp_tdc_mezz/cmp_tdc_core/circular_buffer_block/memory_block/XST_GND
-
-To enable printing of redundant blocks removed and signals merged, set the
-detailed map report option and rerun map.
-
-Section 6 - IOB Properties
---------------------------
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
-| | | | | Term | Strength | Rate | | | Delay |
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-| acam_refclk_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| acam_refclk_p_i | IOB | INPUT | LVDS_25 | TRUE | | | IFF | | |
-| address_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| address_o<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| button1_i | IOB | INPUT | LVCMOS18 | | | | | | |
-| button2_i | IOB | INPUT | LVCMOS18 | | | | | | |
-| carrier_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| clk_125m_gtp_n_i | IPAD | INPUT | | | | | | | |
-| clk_125m_gtp_p_i | IPAD | INPUT | | | | | | | |
-| clk_125m_pllref_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| clk_125m_pllref_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| clk_20m_vcxo_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| cs_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| dac_cs1_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| dac_cs2_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| dac_din_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| dac_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| data_bus_io<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<16> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<17> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<18> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<19> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<20> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<21> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<22> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<23> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<24> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<25> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<26> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| data_bus_io<27> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | IFF | | |
-| ef1_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| ef2_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| enable_inputs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| err_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| int_flag_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| irq_p_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| l2p_clk_n_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
-| l2p_clk_p_o | IOB | OUTPUT | DIFF_SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<0> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<1> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<2> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<3> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<4> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<5> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<6> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<7> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<8> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<9> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<10> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<11> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<12> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<13> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<14> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_data_o<15> | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_dframe_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l2p_edb_o | IOB | OUTPUT | SSTL18_I | | | | OFF | | |
-| l2p_rdy_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| l2p_valid_o | IOB | OUTPUT | SSTL18_I | | | | OSERDES | | |
-| l_wr_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| l_wr_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| led_green | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| led_red | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_onewire_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_sys_scl_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| mezz_sys_sda_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| oe_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| p2l_clk_n_i | IOB | INPUT | DIFF_SSTL18_I | | | | | | |
-| p2l_clk_p_i | IOB | INPUT | DIFF_SSTL18_I | | | | ISERDES | | VARIABLE |
-| p2l_data_i<0> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<1> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<2> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<3> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<4> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<5> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<6> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<7> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<8> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<9> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<10> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<11> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<12> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<13> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<14> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_data_i<15> | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_dframe_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p2l_rdy_o | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p2l_valid_i | IOB | INPUT | SSTL18_I | | | | ISERDES | | |
-| p_rd_d_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| p_rd_d_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| p_wr_rdy_o<0> | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p_wr_rdy_o<1> | IOB | OUTPUT | SSTL18_I | | | | | | |
-| p_wr_req_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
-| p_wr_req_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
-| pcb_ver_i<0> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<1> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<2> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pcb_ver_i<3> | IOB | INPUT | LVCMOS15 | | | | | | |
-| pll_cs_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_dac_sync_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sclk_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sdi_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| pll_sdo_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| pll_status_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| prsnt_m2c_n_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| rd_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| rst_n_a_i | IOB | INPUT | LVCMOS18 | | | | | | |
-| rx_error_o | IOB | OUTPUT | SSTL18_I | | | | | | |
-| sfp_los_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| sfp_mod_def0_b | IOB | INPUT | LVCMOS25 | | | | | | |
-| sfp_mod_def1_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| sfp_mod_def2_b | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
-| sfp_rate_select_b | IOB | INPUT | LVCMOS25 | | | | | | |
-| sfp_rxn_i | IPAD | INPUT | | | | | | | |
-| sfp_rxp_i | IPAD | INPUT | | | | | | | |
-| sfp_tx_disable_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| sfp_tx_fault_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| sfp_txn_o | OPAD | OUTPUT | | | | | | | |
-| sfp_txp_o | OPAD | OUTPUT | | | | | | | |
-| start_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| start_from_fpga_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| stop_dis_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| tdc_clk_125m_n_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| tdc_clk_125m_p_i | IOB | INPUT | LVDS_25 | TRUE | | | | | |
-| tdc_in_fpga_1_i | IOB | INPUT | LVCMOS25 | | | | | | |
-| tdc_led_status_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
-| tdc_led_trig1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tdc_led_trig5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_1_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_2_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_3_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_4_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| term_en_5_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| tx_error_i | IOB | INPUT | SSTL18_I | | | | IFF | | |
-| uart_rxd_i | IOB | INPUT | LVCMOS25 | | | | IFF | | |
-| uart_txd_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-| vc_rdy_i<0> | IOB | INPUT | SSTL18_I | | | | | | |
-| vc_rdy_i<1> | IOB | INPUT | SSTL18_I | | | | | | |
-| wr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | OFF | | |
-+---------------------------------------------------------------------------------------------------------------------------------------------------------+
-
-Section 7 - RPMs
-----------------
-
-Section 8 - Guide Report
-------------------------
-Guide not run on this design.
-
-Section 9 - Area Group and Partition Summary
---------------------------------------------
-
-Partition Implementation Status
--------------------------------
-
- No Partitions were found in this design.
-
--------------------------------
-
-Area Group Information
-----------------------
-
- No area groups were found in this design.
-
-----------------------
-
-Section 10 - Timing Report
---------------------------
-A logic-level (pre-route) timing report can be generated by using Xilinx static
-timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
-mapped NCD and PCF files. Please note that this timing report will be generated
-using estimated delay information. For accurate numbers, please generate a
-timing report with the post Place and Route NCD file.
-
-For more information about the Timing Analyzer, consult the Xilinx Timing
-Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
-Command Line Tools User Guide "TRACE" chapter.
-
-Section 11 - Configuration String Details
------------------------------------------
-Use the "-detail" map option to print out Configuration Strings
-
-Section 12 - Control Set Information
-------------------------------------
-Use the "-detail" map option to print out Control Set Information.
-
-Section 13 - Utilization by Hierarchy
--------------------------------------
-Use the "-detail" map option to print out the Utilization by Hierarchy section.
diff --git a/hdl/syn/spec/with_wrabbit/wrc.ram b/hdl/syn/spec/with_wrabbit/wrc.ram
deleted file mode 100644
index ab26e0f..0000000
--- a/hdl/syn/spec/with_wrabbit/wrc.ram
+++ /dev/null
@@ -1,19518 +0,0 @@
-write 0 98000000
-write 1 D0000000
-write 2 D0200000
-write 3 78010000
-write 4 38210000
-write 5 D0E10000
-write 6 F800003A
-write 7 34000000
-write 8 00000000
-write 9 00000000
-write a 00000000
-write b 00000000
-write c 00000000
-write d 00000000
-write e 00000000
-write f 00000000
-write 10 00000000
-write 11 00000000
-write 12 00000000
-write 13 00000000
-write 14 00000000
-write 15 00000000
-write 16 00000000
-write 17 00000000
-write 18 00000000
-write 19 00000000
-write 1a 00000000
-write 1b 00000000
-write 1c 00000000
-write 1d 00000000
-write 1e 00000000
-write 1f 00000000
-write 20 00000000
-write 21 00000000
-write 22 00000000
-write 23 00000000
-write 24 00000000
-write 25 00000000
-write 26 00000000
-write 27 00000000
-write 28 00000000
-write 29 00000000
-write 2a 00000000
-write 2b 00000000
-write 2c 00000000
-write 2d 00000000
-write 2e 00000000
-write 2f 00000000
-write 30 5B9D0000
-write 31 F8000020
-write 32 34010002
-write 33 F8003A00
-write 34 E0000030
-write 35 34000000
-write 36 34000000
-write 37 34000000
-write 38 00000000
-write 39 00000000
-write 3a 00000000
-write 3b 00000000
-write 3c 00000000
-write 3d 00000000
-write 3e 00000000
-write 3f 00000000
-write 40 98000000
-write 41 781C0001
-write 42 3B9C5FFC
-write 43 781A0001
-write 44 3B5AB060
-write 45 78010001
-write 46 382130F8
-write 47 34020000
-write 48 78030001
-write 49 3863516C
-write 4a C8611800
-write 4b F8003EB1
-write 4c 34010000
-write 4d 34020000
-write 4e 34030000
-write 4f F800004D
-write 50 E0000000
-write 51 379CFFC4
-write 52 5B810004
-write 53 5B820008
-write 54 5B83000C
-write 55 5B840010
-write 56 5B850014
-write 57 5B860018
-write 58 5B87001C
-write 59 5B880020
-write 5a 5B890024
-write 5b 5B8A0028
-write 5c 5B9E0034
-write 5d 5B9F0038
-write 5e 2B81003C
-write 5f 5B810030
-write 60 BB800800
-write 61 3421003C
-write 62 5B81002C
-write 63 C3A00000
-write 64 2B810004
-write 65 2B820008
-write 66 2B83000C
-write 67 2B840010
-write 68 2B850014
-write 69 2B860018
-write 6a 2B87001C
-write 6b 2B880020
-write 6c 2B890024
-write 6d 2B8A0028
-write 6e 2B9D0030
-write 6f 2B9E0034
-write 70 2B9F0038
-write 71 2B9C002C
-write 72 34000000
-write 73 C3C00000
-write 74 90001000
-write 75 3401FFFE
-write 76 A0410800
-write 77 D0010000
-write 78 90201000
-write 79 3401FFFE
-write 7a A0410800
-write 7b D0210000
-write 7c C3A00000
-write 7d 90001000
-write 7e 3401FFFE
-write 7f A0410800
-write 80 D0010000
-write 81 90201000
-write 82 38420001
-write 83 D0220000
-write 84 38210001
-write 85 D0010000
-write 86 C3A00000
-write 87 379CFFE0
-write 88 5B9D0004
-write 89 5B83000C
-write 8a 78030001
-write 8b 5B820008
-write 8c 5B840010
-write 8d 5B850014
-write 8e 5B860018
-write 8f 5B87001C
-write 90 5B880020
-write 91 386330F8
-write 92 28630000
-write 93 5C600006
-write 94 20210020
-write 95 44230004
-write 96 B8400800
-write 97 3782000C
-write 98 F8002692
-write 99 2B9D0004
-write 9a 379C0020
-write 9b C3A00000
-write 9c 379CFFBC
-write 9d 5B8B003C
-write 9e 5B8C0038
-write 9f 5B8D0034
-write a0 5B8E0030
-write a1 5B8F002C
-write a2 5B900028
-write a3 5B910024
-write a4 5B920020
-write a5 5B93001C
-write a6 5B940018
-write a7 5B950014
-write a8 5B960010
-write a9 5B97000C
-write aa 5B980008
-write ab 5B9D0004
-write ac 78030001
-write ad 386322C0
-write ae 78010001
-write af 28620000
-write b0 382130F8
-write b1 58200000
-write b2 78010001
-write b3 38215800
-write b4 58220000
-write b5 F8002E3D
-write b6 F8003581
-write b7 F8003577
-write b8 78010001
-write b9 382100F0
-write ba F8002692
-write bb 34010001
-write bc F8002D4B
-write bd F800335E
-write be 78010001
-write bf 382150B8
-write c0 58200000
-write c1 F8003284
-write c2 34010000
-write c3 F8002A70
-write c4 34020050
-write c5 34010000
-write c6 F8003006
-write c7 34010008
-write c8 33810040
-write c9 34010030
-write ca 33810042
-write cb 37820040
-write cc 34010000
-write cd 33800041
-write ce F8003217
-write cf 3402FFFF
-write d0 5C220010
-write d1 78010001
-write d2 3821010C
-write d3 F8002679
-write d4 34010011
-write d5 33810040
-write d6 34010022
-write d7 33810041
-write d8 34010033
-write d9 33810042
-write da 34010044
-write db 33810043
-write dc 34010055
-write dd 33810044
-write de 34010066
-write df 33810045
-write e0 43830040
-write e1 43840041
-write e2 43850042
-write e3 43860043
-write e4 43870044
-write e5 43880045
-write e6 78020001
-write e7 38420130
-write e8 34010000
-write e9 FBFFFF9E
-write ea 37810040
-write eb F8002782
-write ec 34020001
-write ed 34010001
-write ee F800279E
-write ef F8002AE3
-write f0 F8002C62
-write f1 F800042A
-write f2 78020001
-write f3 38422854
-write f4 34010002
-write f5 F8002F18
-write f6 F8002410
-write f7 F8001E73
-write f8 34010003
-write f9 F8000476
-write fa F8000433
-write fb F8001F45
-write fc 78010001
-write fd 382122C0
-write fe 28360000
-write ff 780F0001
-write 100 78120001
-write 101 780B0001
-write 102 78110001
-write 103 780C0001
-write 104 780D0001
-write 105 78100001
-write 106 39EF2858
-write 107 34180004
-write 108 3A520164
-write 109 396B5150
-write 10a 340E0002
-write 10b 3A310158
-write 10c 34170001
-write 10d 34150003
-write 10e 398C30F8
-write 10f 3414001B
-write 110 39AD5800
-write 111 3A100170
-write 112 34010000
-write 113 F80027AB
-write 114 29E40000
-write 115 7C230000
-write 116 B8209800
-write 117 64810000
-write 118 A0610800
-write 119 44200008
-write 11a 34010000
-write 11b BA201000
-write 11c FBFFFF6B
-write 11d 29610000
-write 11e 34030001
-write 11f 582E0004
-write 120 E000000D
-write 121 66620000
-write 122 7C840000
-write 123 A0441000
-write 124 FC621800
-write 125 CB031800
-write 126 44410007
-write 127 34010000
-write 128 BA401000
-write 129 FBFFFF5E
-write 12a 29610000
-write 12b 34030002
-write 12c 582E0008
-write 12d 59F30000
-write 12e 446E0004
-write 12f 5C75000B
-write 130 F8002571
-write 131 E0000009
-write 132 F80003F7
-write 133 5C350007
-write 134 34010002
-write 135 34020000
-write 136 34030001
-write 137 F80039DB
-write 138 34010000
-write 139 F8002CC2
-write 13a 29810000
-write 13b 5C370003
-write 13c F8000067
-write 13d E0000004
-write 13e 5C2E0008
-write 13f 34010000
-write 140 F80001EB
-write 141 F800351C
-write 142 5C340005
-write 143 F8001E27
-write 144 59800000
-write 145 E0000002
-write 146 F8001E2E
-write 147 F80004AD
-write 148 F8003B9D
-write 149 E0000005
-write 14a BA000800
-write 14b F8002601
-write 14c 340103E8
-write 14d F8002CD1
-write 14e 29A10000
-write 14f 5C36FFFB
-write 150 E3FFFFC2
-write 151 379CFFF4
-write 152 5B9D0004
-write 153 5B810008
-write 154 5B82000C
-write 155 B8401800
-write 156 4820000C
-write 157 5C200005
-write 158 78020001
-write 159 384222C4
-write 15a 28410000
-write 15b 54610007
-write 15c 78010001
-write 15d 78020001
-write 15e 38420184
-write 15f 38213108
-write 160 F80025DE
-write 161 E000000D
-write 162 78030001
-write 163 386322C8
-write 164 28620000
-write 165 37810008
-write 166 F8001D43
-write 167 2B83000C
-write 168 B8202000
-write 169 78020001
-write 16a 78010001
-write 16b 38213108
-write 16c 38420188
-write 16d F80025D1
-write 16e 78010001
-write 16f 38213108
-write 170 2B9D0004
-write 171 379C000C
-write 172 C3A00000
-write 173 379CFFF8
-write 174 5B8B0008
-write 175 5B9D0004
-write 176 78010001
-write 177 3821285C
-write 178 780B0001
-write 179 28210000
-write 17a 396B2E88
-write 17b E0000004
-write 17c 28230000
-write 17d 44430004
-write 17e 356B000C
-write 17f 29620000
-write 180 5C40FFFC
-write 181 78020001
-write 182 34010004
-write 183 38420190
-write 184 F800230E
-write 185 29630004
-write 186 78020001
-write 187 34010007
-write 188 384201A0
-write 189 F8002309
-write 18a 78010001
-write 18b 38213370
-write 18c 28210000
-write 18d 44200007
-write 18e 78010001
-write 18f 3821285C
-write 190 28210000
-write 191 28220000
-write 192 34010009
-write 193 44410007
-write 194 78020001
-write 195 34010001
-write 196 384201A4
-write 197 F80022FB
-write 198 34010000
-write 199 E0000006
-write 19a 78020001
-write 19b 34010004
-write 19c 384201BC
-write 19d F80022F5
-write 19e 34010001
-write 19f 2B9D0004
-write 1a0 2B8B0008
-write 1a1 379C0008
-write 1a2 C3A00000
-write 1a3 379CFF88
-write 1a4 5B8B0010
-write 1a5 5B8C000C
-write 1a6 5B8D0008
-write 1a7 5B9D0004
-write 1a8 780B0001
-write 1a9 F8002C70
-write 1aa 396B3104
-write 1ab 29620000
-write 1ac C8220800
-write 1ad 340203E7
-write 1ae 50410177
-write 1af F8002C6A
-write 1b0 59610000
-write 1b1 F8002327
-write 1b2 78040001
-write 1b3 34010001
-write 1b4 34020001
-write 1b5 34030004
-write 1b6 388401D8
-write 1b7 F80022FA
-write 1b8 78040001
-write 1b9 388401F8
-write 1ba 34030087
-write 1bb 34010002
-write 1bc 34020001
-write 1bd F80022F4
-write 1be 37810068
-write 1bf 37820070
-write 1c0 F8002C0B
-write 1c1 78020001
-write 1c2 34010004
-write 1c3 38420204
-write 1c4 F80022CE
-write 1c5 2B82006C
-write 1c6 2B810068
-write 1c7 F8002240
-write 1c8 78020001
-write 1c9 B8201800
-write 1ca 384201A0
-write 1cb 34010007
-write 1cc F80022C6
-write 1cd 34020000
-write 1ce 37810014
-write 1cf F8000209
-write 1d0 78040001
-write 1d1 34010004
-write 1d2 34020001
-write 1d3 34030004
-write 1d4 38840224
-write 1d5 F80022DC
-write 1d6 78040001
-write 1d7 78050001
-write 1d8 34010006
-write 1d9 34020001
-write 1da 34030007
-write 1db 38840234
-write 1dc 38A5023C
-write 1dd F80022D4
-write 1de 2B81002C
-write 1df 44200005
-write 1e0 78020001
-write 1e1 34010002
-write 1e2 38420244
-write 1e3 E0000004
-write 1e4 78020001
-write 1e5 34010001
-write 1e6 38420250
-write 1e7 F80022AB
-write 1e8 2B81002C
-write 1e9 44200139
-write 1ea 37810078
-write 1eb 37820074
-write 1ec F8002B5F
-write 1ed 2B830074
-write 1ee 2B840078
-write 1ef 78020001
-write 1f0 34010087
-write 1f1 3842025C
-write 1f2 780B0001
-write 1f3 F800229F
-write 1f4 396B285C
-write 1f5 29610000
-write 1f6 28210448
-write 1f7 28210010
-write 1f8 282C0008
-write 1f9 5D800037
-write 1fa 78020001
-write 1fb 34010001
-write 1fc 38420278
-write 1fd F8002295
-write 1fe FBFFFF75
-write 1ff 442C0126
-write 200 78020001
-write 201 34010087
-write 202 38420280
-write 203 F800228F
-write 204 29610000
-write 205 2821001C
-write 206 28240010
-write 207 28830004
-write 208 4460000B
-write 209 78020001
-write 20a 384202A0
-write 20b 28840008
-write 20c 4C030003
-write 20d 34010007
-write 20e E0000003
-write 20f 34010007
-write 210 C8042000
-write 211 F8002281
-write 212 E0000113
-write 213 28830008
-write 214 780C0001
-write 215 398C02AC
-write 216 B9801000
-write 217 34010007
-write 218 F800227A
-write 219 78020001
-write 21a 34010087
-write 21b 384202B4
-write 21c F8002276
-write 21d 29610000
-write 21e B9801000
-write 21f 2821001C
-write 220 28230010
-write 221 34010007
-write 222 2863001C
-write 223 F800226F
-write 224 78020001
-write 225 34010087
-write 226 384202D4
-write 227 F800226B
-write 228 29610000
-write 229 B9801000
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diff --git a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise b/hdl/syn/spec/wr_spec_tdc.xise
similarity index 52%
rename from hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
rename to hdl/syn/spec/wr_spec_tdc.xise
index 33c1ae0..dd18a61 100644
--- a/hdl/syn/spec/with_wrabbit/wr_spec_tdc.xise
+++ b/hdl/syn/spec/wr_spec_tdc.xise
@@ -9,1041 +9,20 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
- <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+ <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
- <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="../../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
- </file>
- <file xil_pn:name="../../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
- </file>
- <file xil_pn:name="../../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
- </file>
- <file xil_pn:name="../../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
- </file>
- <file xil_pn:name="../../../rtl/circular_buffer.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
- </file>
- <file xil_pn:name="../../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
- </file>
- <file xil_pn:name="../../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
- </file>
- <file xil_pn:name="../../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
- </file>
- <file xil_pn:name="../../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
- </file>
- <file xil_pn:name="../../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
- </file>
- <file xil_pn:name="../../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
- </file>
- <file xil_pn:name="../../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
- </file>
- <file xil_pn:name="../../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
- </file>
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- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="334"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="335"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="336"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="337"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="338"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="143"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="339"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="340"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="341"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
- </file>
- <file xil_pn:name="../../../ip_cores/gnum_core/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="342"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
- </file>
- <file xil_pn:name="../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../../../ip_cores/wrabbit/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="314"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
- </file>
- <file xil_pn:name="../../../top/spec/with_wrabbit/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="332"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
- </file>
- <file xil_pn:name="../../../top/spec/with_wrabbit/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="333"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
- </file>
- <file xil_pn:name="../../../top/spec/with_wrabbit/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="264"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
- </file>
- <file xil_pn:name="../../../top/spec/with_wrabbit/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="265"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
- </file>
- <file xil_pn:name="../../../top/spec/with_wrabbit/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
- </file>
- </files>
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
+ </autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
@@ -1070,16 +49,12 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
- <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -1106,12 +81,11 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -1119,19 +93,18 @@
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -1160,7 +133,7 @@
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|wr_spec_tdc|rtl" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Implementation Top File" xil_pn:value="../../../top/spec/with_wrabbit/wr_spec_tdc.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="../../top/spec/wr_spec_tdc.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/wr_spec_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -1168,7 +141,7 @@
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
@@ -1206,7 +179,6 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
@@ -1226,7 +198,7 @@
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="wr_spec_tdc" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -1236,19 +208,17 @@
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wr_spec_tdc_map.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="wr_spec_tdc_timesim.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wr_spec_tdc_synthesis.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wr_spec_tdc_translate.vhd" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="wr_spec_tdc_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="wr_spec_tdc_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="wr_spec_tdc_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="wr_spec_tdc_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -1257,14 +227,14 @@
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="wr_spec_tdc" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -1278,8 +248,6 @@
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -1297,7 +265,7 @@
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -1341,7 +309,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
@@ -1350,13 +318,13 @@
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="wr_spec_tdc" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
@@ -1364,29 +332,810 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-27T11:49:48" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7FBE502A282B40C7A2410990D68F770C" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-05-19T01:04:18" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E64FCD639D6940CF1E77C64A85A19F94" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
+ <libraries/>
+
+ <files>
+ <file xil_pn:name="../../top/spec/wr_spec_tdc.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="156"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../top/spec/wr_spec_tdc.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="167"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram_mixed.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/timestamp_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
+ </file>
+ <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="137"/>
+ </file>
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
+ </file>
+ <file xil_pn:name="../../rtl/wrabbit_sync.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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+ <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
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+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_path.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="132"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="138"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+ </file>
+ <file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_gpio_channel.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+ </file>
+ <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="126"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
+ </file>
+ <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="124"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="142"/>
+ </file>
+ <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_framer.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ </files>
+
<bindings>
- <binding xil_pn:location="/wr_spec_tdc" xil_pn:name="../../../top/spec/with_wrabbit/wr_spec_tdc.ucf"/>
+ <binding xil_pn:location="/wr_spec_tdc" xil_pn:name="../../top/spec/wr_spec_tdc.ucf"/>
</bindings>
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- <file xil_pn:name="../../../ip_cores/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_lm32/src/lm32_functions.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../ip_cores/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
- </autoManagedFiles>
+ <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
diff --git a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise b/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
deleted file mode 100644
index f665c7c..0000000
--- a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/spec_top_fmc_tdc.xise
+++ /dev/null
@@ -1,1393 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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-
- <header>
- <!-- ISE source project file created by Project Navigator. -->
- <!-- -->
- <!-- This file contains project source information including a list of -->
- <!-- project source files, project and process properties. This file, -->
- <!-- along with the project source files, is sufficient to open and -->
- <!-- implement in ISE Project Navigator. -->
- <!-- -->
- <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
- </header>
-
- <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/>
-
- <files>
- <file xil_pn:name="../../../../rtl/tdc_eic.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
- </file>
- <file xil_pn:name="../../../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
- </file>
- <file xil_pn:name="../../../../rtl/acam_timecontrol_interface.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
- </file>
- <file xil_pn:name="../../../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
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- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
- </file>
- <file xil_pn:name="../../../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
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- <file xil_pn:name="../../../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
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- <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
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- <file xil_pn:name="../../../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
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- <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Output File Name" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="default"/>
- <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
- <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
- <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Continue on Impossible" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spec_top_fmc_tdc_map.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="spec_top_fmc_tdc_timesim.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_fmc_tdc_synthesis.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_fmc_tdc_translate.vhd" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
- <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
- <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="default"/>
- <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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- <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
- <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
- <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
- <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
- <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
- <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
- <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
- <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
- <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
- <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
- <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
- <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
- <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
- <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
- <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
- <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
- <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
- <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
- <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
- <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
- <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
- <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
- <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
- <!-- -->
- <!-- The following properties are for internal use only. These should not be modified.-->
- <!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_DesignName" xil_pn:value="spec_top_fmc_tdc" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
- <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-27T11:49:48" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7FBE502A282B40C7A2410990D68F770C" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
- <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
- </properties>
-
- <bindings>
- <binding xil_pn:location="/spec_top_fmc_tdc" xil_pn:name="../../../../top/spec/spec_top_fmc_tdc.ucf"/>
- </bindings>
-
- <libraries/>
-
- <autoManagedFiles>
- <!-- The following files are identified by `include statements in verilog -->
- <!-- source files and are automatically managed by Project Navigator. -->
- <!-- -->
- <!-- Do not hand-edit this section, as it will be overwritten when the -->
- <!-- project is analyzed based on files automatically identified as -->
- <!-- include files. -->
- <file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../../ip_cores/wishbone/wb_lm32/src/lm32_functions.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../../ip_cores/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
- <file xil_pn:name="../../../../ip_cores/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
- </autoManagedFiles>
-
-</project>
diff --git a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram b/hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram
deleted file mode 100644
index ab26e0f..0000000
--- a/hdl/syn/spec/xilinx/spec_top_fmc_tdc/wrc.ram
+++ /dev/null
@@ -1,19518 +0,0 @@
-write 0 98000000
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-write 4 38210000
-write 5 D0E10000
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-write 13 00000000
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-write 16 00000000
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-write 1f 00000000
-write 20 00000000
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-write 26 00000000
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-write 29 00000000
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-write 2e 00000000
-write 2f 00000000
-write 30 5B9D0000
-write 31 F8000020
-write 32 34010002
-write 33 F8003A00
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-write 35 34000000
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-write 3e 00000000
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-write 4b7a 00000000
-write 4b7b 00000000
-write 4b7c 00000000
-write 4b7d 00000000
-write 4b7e 00000000
-write 4b7f 00000000
-write 4b80 00000000
-write 4b81 00000000
-write 4b82 00000000
-write 4b83 00000000
-write 4b84 00000000
-write 4b85 00000000
-write 4b86 00000000
-write 4b87 00000000
-write 4b88 00000000
-write 4b89 00001DA0
-write 4b8a 00001DD4
-write 4b8b 00001E54
-write 4b8c 00001E5C
-write 4b8d 00001EB4
-write 4b8e 00001EE0
-write 4b8f 00001F38
-write 4b90 00001F5C
-write 4b91 00002004
-write 4b92 0000200C
-write 4b93 00002014
-write 4b94 00002078
-write 4b95 00002094
-write 4b96 00001E80
-write 4b97 00001A68
-write 4b98 000019EC
-write 4b99 00001990
-write 4b9a 00001938
-write 4b9b 00000000
-write 4b9c 00000000
-write 4b9d 00001908
-write 4b9e 00001CE8
-write 4b9f 00001CC8
-write 4ba0 00001BF8
-write 4ba1 00001AE8
-write 4ba2 00000001
-write 4ba3 00010D10
-write 4ba4 00004BFC
-write 4ba5 00000002
-write 4ba6 00010D20
-write 4ba7 00004DC0
-write 4ba8 00000003
-write 4ba9 00010D28
-write 4baa 00004E7C
-write 4bab 00000004
-write 4bac 00010D34
-write 4bad 00004E8C
-write 4bae 00000006
-write 4baf 000122B8
-write 4bb0 00005030
-write 4bb1 00000008
-write 4bb2 00010D40
-write 4bb3 00005278
-write 4bb4 00000009
-write 4bb5 00010D50
-write 4bb6 000052EC
-write 4bb7 00000064
-write 4bb8 00010D58
-write 4bb9 00002D7C
-write 4bba 00000066
-write 4bbb 00010D70
-write 4bbc 00002F18
-write 4bbd 00000065
-write 4bbe 00010D84
-write 4bbf 00003064
-write 4bc0 00000067
-write 4bc1 00010D9C
-write 4bc2 00003158
-write 4bc3 00000068
-write 4bc4 00010DB4
-write 4bc5 000032A8
-write 4bc6 00000069
-write 4bc7 00010DC4
-write 4bc8 000035A4
-write 4bc9 0000006A
-write 4bca 00010DD4
-write 4bcb 00003704
-write 4bcc 0000006B
-write 4bcd 00010DE8
-write 4bce 0000388C
-write 4bcf 00000000
-write 4bd0 00000000
-write 4bd1 00000000
-write 4bd2 000028B8
-write 4bd3 0000292C
-write 4bd4 00000000
-write 4bd5 000029D8
-write 4bd6 00002C14
-write 4bd7 00002BF8
-write 4bd8 00002B28
-write 4bd9 000029F4
-write 4bda 00002A40
-write 4bdb 00002AB0
-write 4bdc 00002AEC
-write 4bdd 00002D40
-write 4bde 00002D1C
-write 4bdf 00000001
-write 4be0 00011384
-write 4be1 0001138C
-write 4be2 00011398
-write 4be3 000113A4
-write 4be4 00000000
-write 4be5 00000000
-write 4be6 00000000
-write 4be7 00000000
-write 4be8 000113C8
-write 4be9 000113B0
-write 4bea 000113BC
-write 4beb 000113D4
-write 4bec 000113E0
-write 4bed 000113EC
-write 4bee 00000000
-write 4bef 00000000
-write 4bf0 00011778
-write 4bf1 00011788
-write 4bf2 00011794
-write 4bf3 000117A8
-write 4bf4 000117BC
-write 4bf5 000117CC
-write 4bf6 000117D8
-write 4bf7 000117E4
-write 4bf8 BBFEF060
-write 4bf9 00000000
-write 4bfa 00000000
-write 4bfb 00000000
-write 4bfc 00000000
-write 4bfd 00000000
-write 4bfe 00000000
-write 4bff 00000000
-write 4c00 00000000
-write 4c01 00000000
-write 4c02 00000000
-write 4c03 00000000
-write 4c04 00000000
-write 4c05 00000001
-write 4c06 0000000A
-write 4c07 03E80006
-write 4c08 01008080
-write 4c09 00000000
-write 4c0a 00000000
-write 4c0b 00000000
-write 4c0c 00000000
-write 4c0d 00000000
-write 4c0e 00000000
-write 4c0f 00000000
-write 4c10 00000004
-write 4c11 00000008
-write 4c12 00000100
-write 4c13 00000200
-write 4c14 0000CFD4
-write 4c15 0000D008
-write 4c16 0000D038
-write 4c17 FFFFFFFF
-write 4c18 00012738
-write 4c19 000118F0
-write 4c1a 000081C0
-write 4c1b 00011938
-write 4c1c 00008268
-write 4c1d 00011A60
-write 4c1e 000084B0
-write 4c1f 00011900
-write 4c20 00008838
-write 4c21 00011A78
-write 4c22 000088B8
-write 4c23 00011A80
-write 4c24 00008918
-write 4c25 00011AF4
-write 4c26 000089B4
-write 4c27 00011B30
-write 4c28 00008A98
-write 4c29 00011B38
-write 4c2a 00008BF4
-write 4c2b 00011B3C
-write 4c2c 00008C0C
-write 4c2d 00011B80
-write 4c2e 00008C88
-write 4c2f 000118F4
-write 4c30 00008DA0
-write 4c31 00011C10
-write 4c32 00008EBC
-write 4c33 00011C38
-write 4c34 00008F68
-write 4c35 00011C58
-write 4c36 00008FD4
-write 4c37 00012070
-write 4c38 0000D284
-write 4c39 00012074
-write 4c3a 0000D188
-write 4c3b 00012078
-write 4c3c 0000D08C
-write 4c3d 0000D08C
diff --git a/hdl/testbench/spec/acam_data_model.vhd b/hdl/testbench/spec.old/acam_data_model.vhd
similarity index 100%
rename from hdl/testbench/spec/acam_data_model.vhd
rename to hdl/testbench/spec.old/acam_data_model.vhd
diff --git a/hdl/testbench/spec/acam_fifo_model.vhd b/hdl/testbench/spec.old/acam_fifo_model.vhd
similarity index 100%
rename from hdl/testbench/spec/acam_fifo_model.vhd
rename to hdl/testbench/spec.old/acam_fifo_model.vhd
diff --git a/hdl/testbench/spec/acam_model.vhd b/hdl/testbench/spec.old/acam_model.vhd
similarity index 100%
rename from hdl/testbench/spec/acam_model.vhd
rename to hdl/testbench/spec.old/acam_model.vhd
diff --git a/hdl/testbench/spec/acam_timing_model.vhd b/hdl/testbench/spec.old/acam_timing_model.vhd
similarity index 100%
rename from hdl/testbench/spec/acam_timing_model.vhd
rename to hdl/testbench/spec.old/acam_timing_model.vhd
diff --git a/hdl/testbench/spec/gnum_model/cmd_router.vhd b/hdl/testbench/spec.old/gnum_model/cmd_router.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/cmd_router.vhd
rename to hdl/testbench/spec.old/gnum_model/cmd_router.vhd
diff --git a/hdl/testbench/spec/gnum_model/cmd_router1.vhd b/hdl/testbench/spec.old/gnum_model/cmd_router1.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/cmd_router1.vhd
rename to hdl/testbench/spec.old/gnum_model/cmd_router1.vhd
diff --git a/hdl/testbench/spec/gnum_model/gennum_tb.tar b/hdl/testbench/spec.old/gnum_model/gennum_tb.tar
similarity index 100%
rename from hdl/testbench/spec/gnum_model/gennum_tb.tar
rename to hdl/testbench/spec.old/gnum_model/gennum_tb.tar
diff --git a/hdl/testbench/spec/gnum_model/gn412x_bfm.vhd b/hdl/testbench/spec.old/gnum_model/gn412x_bfm.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/gn412x_bfm.vhd
rename to hdl/testbench/spec.old/gnum_model/gn412x_bfm.vhd
diff --git a/hdl/testbench/spec/gnum_model/mem_model.vhd b/hdl/testbench/spec.old/gnum_model/mem_model.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/mem_model.vhd
rename to hdl/testbench/spec.old/gnum_model/mem_model.vhd
diff --git a/hdl/testbench/spec/gnum_model/textutil.vhd b/hdl/testbench/spec.old/gnum_model/textutil.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/textutil.vhd
rename to hdl/testbench/spec.old/gnum_model/textutil.vhd
diff --git a/hdl/testbench/spec/gnum_model/util.vhd b/hdl/testbench/spec.old/gnum_model/util.vhd
similarity index 100%
rename from hdl/testbench/spec/gnum_model/util.vhd
rename to hdl/testbench/spec.old/gnum_model/util.vhd
diff --git a/hdl/testbench/spec/start_stop_gen.vhd b/hdl/testbench/spec.old/start_stop_gen.vhd
similarity index 100%
rename from hdl/testbench/spec/start_stop_gen.vhd
rename to hdl/testbench/spec.old/start_stop_gen.vhd
diff --git a/hdl/testbench/spec/tb_tdc.vhd b/hdl/testbench/spec.old/tb_tdc.vhd
similarity index 100%
rename from hdl/testbench/spec/tb_tdc.vhd
rename to hdl/testbench/spec.old/tb_tdc.vhd
diff --git a/hdl/testbench/spec/Manifest.py b/hdl/testbench/spec/Manifest.py
new file mode 100644
index 0000000..e729076
--- /dev/null
+++ b/hdl/testbench/spec/Manifest.py
@@ -0,0 +1,13 @@
+sim_tool = "modelsim"
+top_module="main"
+syn_device="xc6slx45t"
+
+action = "simulation"
+target = "xilinx"
+fetchto = "../../ip_cores"
+include_dirs=[ "../../sim", "../include", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ]
+
+files = [ "main.sv" ]
+
+modules = { "local" : [ "../../top/spec", "../../ip_cores/gn4124-core/hdl/gn4124core/sim/gn4124_bfm" ] }
+
diff --git a/hdl/testbench/spec/main.sv b/hdl/testbench/spec/main.sv
new file mode 100644
index 0000000..8a0de8a
--- /dev/null
+++ b/hdl/testbench/spec/main.sv
@@ -0,0 +1,254 @@
+`include "simdrv_defs.svh"
+`include "gn4124_bfm.svh"
+`include "timestamp_fifo_regs.vh"
+
+module fake_acam(
+ input [3:0] addr,
+ output reg [27:0] data,
+ input wr,
+ input rd,
+ output reg ef1,
+ output reg ef2
+ );
+
+ typedef struct {
+ int channel;
+ time ts;
+ } acam_fifo_entry;
+
+ acam_fifo_entry fifo1[$], fifo2[$];
+
+ task pulse(int channel, time ts);
+
+ acam_fifo_entry ent;
+
+ ent.channel = channel % 4;
+ ent.ts = ts;
+
+ if (channel >= 0 && channel <= 3)
+ fifo1.push_back(ent);
+ else
+ fifo2.push_back(ent);
+
+ #100ns;
+ if(fifo1.size())
+ ef1 = 0;
+ if(fifo2.size())
+ ef2 = 0;
+
+ endtask // pulse
+
+ initial begin
+ ef1 = 1;
+ ef2 = 1;
+ data = 28'bz;
+
+ end
+
+
+ always@(negedge rd) begin
+ if (addr == 8) begin
+ acam_fifo_entry ent;
+ ent=fifo1.pop_front();
+ data <= ent.ts | (ent.channel << 26) | (1<<17);
+
+ end else if (addr == 9) begin
+ acam_fifo_entry ent;
+ ent=fifo2.pop_front();
+ data <= ent.ts | (ent.channel << 26) | (1<<17);
+
+ end else
+ data <= 28'bz;
+
+ #10ns;
+
+ ef1 <= (fifo1.size() ? 0 : 1);
+ ef2 <= (fifo2.size() ? 0 : 1);
+
+
+ end
+
+
+
+endmodule
+
+
+module main;
+
+ reg rst_n = 0;
+ reg clk_125m = 0, clk_20m = 0;
+
+ always #4ns clk_125m <= ~clk_125m;
+ always #25ns clk_20m <= ~clk_20m;
+
+ initial begin
+ repeat(20) @(posedge clk_125m);
+ rst_n = 1;
+ end
+
+
+ reg clk_acam = 0;
+ reg clk_62m5 = 0;
+
+ always@(posedge clk_125m)
+ clk_62m5 <= ~clk_62m5;
+
+ always@(posedge clk_62m5)
+ clk_acam <= ~clk_acam;
+
+ wire [3:0] tdc_addr;
+
+ wire [27:0] tdc_data;
+
+
+ IGN4124PCIMaster I_Gennum ();
+
+
+ wr_spec_tdc #(
+ .g_with_wr_phy(0),
+ .g_simulation(1)
+ ) DUT (
+ .clk_125m_pllref_p_i(clk_125m),
+ .clk_125m_pllref_n_i(~clk_125m),
+ .clk_125m_gtp_p_i(clk_125m),
+ .clk_125m_gtp_n_i(~clk_125m),
+
+
+ .tdc_clk_125m_p_i(clk_125m),
+ .tdc_clk_125m_n_i(~clk_125m),
+
+ .acam_refclk_p_i(clk_acam),
+ .acam_refclk_n_i(~clk_acam),
+
+ .clk_20m_vcxo_i(clk_20m),
+ .pll_status_i(1'b1),
+ .ef1_i(tdc_ef1),
+ .ef2_i(tdc_ef2),
+ .err_flag_i(1'b0),
+ .int_flag_i(1'b0),
+ .rd_n_o(tdc_rd_n),
+ .data_bus_io(tdc_data),
+ .address_o(tdc_addr),
+
+ `GENNUM_WIRE_SPEC_PINS(I_Gennum)
+
+
+ );
+
+ fake_acam ACAM(
+ .addr(tdc_addr),
+ .data(tdc_data),
+ .wr(1'b0),
+ .rd(tdc_rd_n),
+ .ef1(tdc_ef1),
+ .ef2(tdc_ef2)
+ );
+
+
+
+
+
+
+
+ reg force_irq = 0;
+
+ initial begin
+
+ CBusAccessor acc;
+ const uint64_t tdc1_base = 'h40000;
+ uint64_t d;
+ acc = I_Gennum.get_accessor();
+
+
+ #100us;
+
+ $display("Accessor: %x", acc);
+
+ $display("Un-reset FMCs...");
+
+ acc.write('h02000c, 'h3);
+
+ #500us;
+
+ acc.read('h040000, d);
+ $display("TDC SDB ID : %x", d);
+
+
+ acc.write('h420a0, 1234); // set UTC
+ acc.write('h420fc, 1<<9); // load UTC
+
+ acc.write('h43004, 'hf); // enable EIC irq
+
+ acc.write('h42084, 'h1f0000); // enable all ACAM inputs
+ acc.write('h420fc, (1<<0)); // start acquisition
+
+ acc.write('h420fc, (1<<0)); // start acquisition
+ acc.write('h42090, 2); // thr = 2 ts
+ acc.write('h42094, 10); // thr = 10 ms
+
+
+
+ #300us;
+ fork
+ forever begin
+ acc.read('h45000 + `ADDR_TSF_CSR, d);
+
+ $display("TSF CSR %x", d);
+
+ if(d&1) begin
+ uint64_t t0,t1,t2,t3;
+
+ acc.write('h45000 + `ADDR_TSF_CSR, 0);
+ acc.read('h45000 + `ADDR_TSF_LTS0, t0);
+ acc.read('h45000 + `ADDR_TSF_LTS1, t1);
+ acc.read('h45000 + `ADDR_TSF_LTS2, t2);
+ acc.read('h45000 + `ADDR_TSF_LTS3, t3);
+
+ $display("Last: %08x %08x %08x %08x",t0,t1,t2,t3);
+
+ end
+
+
+ acc.read('h45000 + `ADDR_TSF_FIFO_CSR, d);
+// $display("FIFO CSR %x", d);
+
+/* -----\/----- EXCLUDED -----\/-----
+ if(!(d&`TSF_FIFO_CSR_EMPTY)) begin
+ uint64_t t0,t1,t2,t3;
+
+ acc.read('hc15000 + `ADDR_TSF_FIFO_R0, t0);
+ acc.read('hc15000 + `ADDR_TSF_FIFO_R1, t1);
+ acc.read('hc15000 + `ADDR_TSF_FIFO_R2, t2);
+ acc.read('hc15000 + `ADDR_TSF_FIFO_R3, t3);
+
+ $display("Fifo: %08x %08x %08x %08x",t0,t1,t2,t3);
+ end
+ -----/\----- EXCLUDED -----/\----- */
+
+ end
+
+
+ forever begin
+ $display("Pulse!");
+
+ ACAM.pulse(0, 0);
+ ACAM.pulse(1, 0);
+ ACAM.pulse(2, 0);
+ #10us;
+ end
+ join
+
+
+
+
+
+ end
+
+
+
+
+endmodule // main
+
+
+
+
diff --git a/hdl/testbench/spec/run.do b/hdl/testbench/spec/run.do
new file mode 100644
index 0000000..660b144
--- /dev/null
+++ b/hdl/testbench/spec/run.do
@@ -0,0 +1,8 @@
+vsim -t 1ps -L unisim work.main -voptargs=+acc
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+do wave.do
+radix -hexadecimal
+run 1ms
\ No newline at end of file
diff --git a/hdl/testbench/spec/wave.do b/hdl/testbench/spec/wave.do
new file mode 100644
index 0000000..69cb0c5
--- /dev/null
+++ b/hdl/testbench/spec/wave.do
@@ -0,0 +1,565 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n_a_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/status_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_p_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_clk_n_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_data_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dframe_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_valid_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_req_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rx_error_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/vc_rdy_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_p_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_clk_n_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_data_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dframe_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_valid_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/irq_p_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_clk_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_adr_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_sel_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stb_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_we_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_cyc_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_dat_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_ack_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_reg_stall_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_clk_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_sel_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stb_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_we_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_cyc_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_dat_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_ack_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_stall_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_err_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_rty_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_int_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_clk_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_adr_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_sel_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stb_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_we_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_cyc_o
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_dat_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ack_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_stall_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_err_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_rty_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_int_i
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/sys_clk
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/io_clk
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/serdes_strobe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_pll_locked
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_reg
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst_n
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/rst
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_dframe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/des_pd_data
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_wr_rdy
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_wbm
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_rdy_pdm
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_start
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_length
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_cid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_last
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_hdr_stat
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mrd
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_target_mwr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpld
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_master_cpln
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d_last
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_d
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_be
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_addr_start
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_dframe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ser_data
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy_t2
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l_wr_rdy
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy_t2
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p_rd_d_rdy
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy_t2
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_rdy
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_edb_t2
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t2
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error_t
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/tx_error
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_dframe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_data
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/wbm_arb_req
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_wbm_gnt
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_req
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_ldm_gnt
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_dframe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/ldm_arb_data
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_dframe
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_data
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/pdm_arb_req
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/arb_pdm_gnt
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_carrier_addr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_h
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_host_addr_l
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_len
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_l2p
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_p2l
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_start_next
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_done
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_error
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_done
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_l2p_error
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_done
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_p2l_error
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_byte_swap
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_ctrl_abort
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_carrier_addr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_h
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_host_addr_l
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_len
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_l
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_next_h
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_attrib
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/next_item_valid
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/dma_irq
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/csr_adr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_adr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_s2m
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_dat_m2s
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_sel
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_cyc
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stb
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_we
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_ack
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/l2p_dma_stall
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_adr
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_s2m
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_dat_m2s
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_sel
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_cyc
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stb
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_we
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_ack
+add wave -noupdate -expand -group Gennum /main/DUT/cmp_gn4124_core/p2l_dma_stall
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_sys_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_sys_n_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/clk_tdc_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_tdc_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/acam_refclk_r_edge_p_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/send_dac_word_p_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/dac_word_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_from_fpga_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/err_flag_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/int_flag_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/start_dis_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/stop_dis_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/data_bus_io
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/address_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cs_n_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/oe_n_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rd_n_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wr_n_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef1_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/ef2_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/enable_inputs_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_1_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_2_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_3_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_4_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/term_en_5_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_status_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig1_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig2_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig3_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig4_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_led_trig5_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_1_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_2_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_3_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_4_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_in_fpga_5_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_link_up_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_time_valid_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_cycles_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_lock_en_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_aux_locked_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_clk_dmtd_locked_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_value_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_dac_wr_p_i
+add wave -noupdate -expand -group Mezz -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/slave_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wb_irq_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_oen_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_scl_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_oen_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/i2c_sda_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/onewire_b
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/direct_timestamp_stb_o
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/general_rst_n
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/rst_ref_0_n
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_out
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cnx_master_in
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_core_wb_adr
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tdc_mem_wb_adr
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_en
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/mezz_owr_i
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_in
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_out
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_scl_oe_n
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_in
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_out
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/sys_sda_oe_n
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_tstamp
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_to_wr
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/reg_from_wr
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_utc_p
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/wrabbit_synched
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_channel
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/timestamp_stb
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/channel_enable
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_threshold
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/irq_timeout
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/tick_1ms
+add wave -noupdate -expand -group Mezz /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/counter_1ms
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_sys_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_n_sys_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_tdc_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_tdc_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_refclk_r_edge_p_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/send_dac_word_p_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/dac_word_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/err_flag_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/int_flag_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_dis_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/stop_dis_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/data_bus_io
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/address_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cs_n_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/oe_n_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rd_n_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wr_n_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/ef1_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/ef2_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/enable_inputs_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_1_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_2_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_3_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_4_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/term_en_5_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_status_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig1_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig2_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig3_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig4_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_led_trig5_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_status_reg_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_synched_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_p_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_tai_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_i
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/cfg_slave_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_stb_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/channel_enable_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_threshold_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_timeout_o
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_adr
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_cyc
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_stb
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_we
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_ack
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_dat_r
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acm_dat_w
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef1
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef2
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef1_meta
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ef2_meta
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_f_edge_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_errflag_r_edge_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_intflag_f_edge_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp1_ok_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp2_ok_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/activate_acq_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/deactivate_acq_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/load_acam_config
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_acam_config
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_acam_status
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_ififo1
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_ififo2
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/read_start01
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/reset_acam
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/load_utc
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/roll_over_incr_recent
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/deactivate_chan
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/pulse_delay
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/window_delay
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_period
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/starting_utc
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_inputs_en
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ififo1
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_ififo2
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_start01
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_tstamp_threshold
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/irq_time_threshold
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/local_utc
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_config
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_config_rdbk
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/start_from_fpga
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/state_active_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/clk_i_cycles_offset
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/roll_over_nb
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/retrig_nb_offset
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/local_utc_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/current_retrig_nb
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc_p
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/utc
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/wrabbit_ctrl_reg
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_channel
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_1
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_2
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_3
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_4
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/tdc_in_fpga_5
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/acam_tstamp_channel
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/rst_sys
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp_valid
+add wave -noupdate -group Core /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/cmp_tdc_core/timestamp
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_sys_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/clk_tdc_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_n_sys_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/rst_tdc_i
+add wave -noupdate -expand -group FIFO0 -expand /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/slave_o
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_o
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/enable_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tick_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_threshold_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/irq_timeout_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_valid_i
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/tmr_timeout
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_irq_int
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/buf_count
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/last_ts
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_in
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/regs_out
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/channel_id
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/ts_match
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/seq_counter
+add wave -noupdate -expand -group FIFO0 /main/DUT/cmp_tdc_mezzanine/cmp_tdc_mezz/gen_fifos(0)/U_TheFifo/timestamp_with_seq
+add wave -noupdate /main/DUT/clk_125m_pllref_p_i
+add wave -noupdate /main/DUT/clk_125m_pllref_n_i
+add wave -noupdate /main/DUT/clk_125m_gtp_n_i
+add wave -noupdate /main/DUT/clk_125m_gtp_p_i
+add wave -noupdate /main/DUT/clk_20m_vcxo_i
+add wave -noupdate /main/DUT/dac_sclk_o
+add wave -noupdate /main/DUT/dac_din_o
+add wave -noupdate /main/DUT/dac_cs1_n_o
+add wave -noupdate /main/DUT/dac_cs2_n_o
+add wave -noupdate /main/DUT/sfp_txp_o
+add wave -noupdate /main/DUT/sfp_txn_o
+add wave -noupdate /main/DUT/sfp_rxp_i
+add wave -noupdate /main/DUT/sfp_rxn_i
+add wave -noupdate /main/DUT/sfp_mod_def0_b
+add wave -noupdate /main/DUT/sfp_mod_def1_b
+add wave -noupdate /main/DUT/sfp_mod_def2_b
+add wave -noupdate /main/DUT/sfp_rate_select_b
+add wave -noupdate /main/DUT/sfp_tx_fault_i
+add wave -noupdate /main/DUT/sfp_tx_disable_o
+add wave -noupdate /main/DUT/sfp_los_i
+add wave -noupdate /main/DUT/uart_rxd_i
+add wave -noupdate /main/DUT/uart_txd_o
+add wave -noupdate /main/DUT/carrier_scl_b
+add wave -noupdate /main/DUT/carrier_sda_b
+add wave -noupdate /main/DUT/carrier_onewire_b
+add wave -noupdate /main/DUT/button1_i
+add wave -noupdate /main/DUT/button2_i
+add wave -noupdate /main/DUT/l_rst_n
+add wave -noupdate /main/DUT/gpio
+add wave -noupdate /main/DUT/p2l_rdy
+add wave -noupdate /main/DUT/p2l_clkn
+add wave -noupdate /main/DUT/p2l_clkp
+add wave -noupdate /main/DUT/p2l_data
+add wave -noupdate /main/DUT/p2l_dframe
+add wave -noupdate /main/DUT/p2l_valid
+add wave -noupdate /main/DUT/p_wr_req
+add wave -noupdate /main/DUT/p_wr_rdy
+add wave -noupdate /main/DUT/rx_error
+add wave -noupdate /main/DUT/l2p_data
+add wave -noupdate /main/DUT/l2p_dframe
+add wave -noupdate /main/DUT/l2p_valid
+add wave -noupdate /main/DUT/l2p_clkn
+add wave -noupdate /main/DUT/l2p_clkp
+add wave -noupdate /main/DUT/l2p_edb
+add wave -noupdate /main/DUT/l2p_rdy
+add wave -noupdate /main/DUT/l_wr_rdy
+add wave -noupdate /main/DUT/p_rd_d_rdy
+add wave -noupdate /main/DUT/tx_error
+add wave -noupdate /main/DUT/vc_rdy
+add wave -noupdate /main/DUT/pll_sclk_o
+add wave -noupdate /main/DUT/pll_sdi_o
+add wave -noupdate /main/DUT/pll_cs_o
+add wave -noupdate /main/DUT/pll_dac_sync_o
+add wave -noupdate /main/DUT/pll_sdo_i
+add wave -noupdate /main/DUT/pll_status_i
+add wave -noupdate /main/DUT/tdc_clk_125m_p_i
+add wave -noupdate /main/DUT/tdc_clk_125m_n_i
+add wave -noupdate /main/DUT/acam_refclk_p_i
+add wave -noupdate /main/DUT/acam_refclk_n_i
+add wave -noupdate /main/DUT/start_from_fpga_o
+add wave -noupdate /main/DUT/err_flag_i
+add wave -noupdate /main/DUT/int_flag_i
+add wave -noupdate /main/DUT/start_dis_o
+add wave -noupdate /main/DUT/stop_dis_o
+add wave -noupdate /main/DUT/data_bus_io
+add wave -noupdate /main/DUT/address_o
+add wave -noupdate /main/DUT/cs_n_o
+add wave -noupdate /main/DUT/oe_n_o
+add wave -noupdate /main/DUT/rd_n_o
+add wave -noupdate /main/DUT/wr_n_o
+add wave -noupdate /main/DUT/ef1_i
+add wave -noupdate /main/DUT/ef2_i
+add wave -noupdate /main/DUT/enable_inputs_o
+add wave -noupdate /main/DUT/term_en_2_o
+add wave -noupdate /main/DUT/term_en_3_o
+add wave -noupdate /main/DUT/term_en_4_o
+add wave -noupdate /main/DUT/term_en_5_o
+add wave -noupdate /main/DUT/tdc_led_status_o
+add wave -noupdate /main/DUT/tdc_led_trig1_o
+add wave -noupdate /main/DUT/tdc_led_trig2_o
+add wave -noupdate /main/DUT/tdc_led_trig3_o
+add wave -noupdate /main/DUT/tdc_led_trig4_o
+add wave -noupdate /main/DUT/tdc_led_trig5_o
+add wave -noupdate /main/DUT/tdc_in_fpga_1_i
+add wave -noupdate /main/DUT/tdc_in_fpga_2_i
+add wave -noupdate /main/DUT/tdc_in_fpga_3_i
+add wave -noupdate /main/DUT/tdc_in_fpga_4_i
+add wave -noupdate /main/DUT/tdc_in_fpga_5_i
+add wave -noupdate /main/DUT/mezz_sys_scl_b
+add wave -noupdate /main/DUT/mezz_sys_sda_b
+add wave -noupdate /main/DUT/mezz_onewire_b
+add wave -noupdate /main/DUT/led_red
+add wave -noupdate /main/DUT/led_green
+add wave -noupdate /main/DUT/pcb_ver_i
+add wave -noupdate /main/DUT/prsnt_m2c_n_i
+add wave -noupdate /main/DUT/pllout_clk_sys
+add wave -noupdate /main/DUT/pllout_clk_dmtd
+add wave -noupdate /main/DUT/pllout_clk_fb_pllref
+add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
+add wave -noupdate /main/DUT/clk_125m_pllref
+add wave -noupdate /main/DUT/clk_125m_gtp
+add wave -noupdate /main/DUT/clk_dmtd
+add wave -noupdate /main/DUT/clk_20m_vcxo
+add wave -noupdate /main/DUT/clk_20m_vcxo_buf
+add wave -noupdate /main/DUT/clk_62m5_sys
+add wave -noupdate /main/DUT/sys_locked
+add wave -noupdate /main/DUT/rst_n_sys
+add wave -noupdate /main/DUT/cnx_master_out
+add wave -noupdate /main/DUT/cnx_master_in
+add wave -noupdate /main/DUT/cnx_slave_out
+add wave -noupdate /main/DUT/cnx_slave_in
+add wave -noupdate /main/DUT/gn_wb_adr
+add wave -noupdate /main/DUT/gn4124_status
+add wave -noupdate /main/DUT/carrier_owr_en
+add wave -noupdate /main/DUT/carrier_owr_i
+add wave -noupdate /main/DUT/irq_to_gn4124
+add wave -noupdate /main/DUT/tm_link_up
+add wave -noupdate /main/DUT/tm_time_valid
+add wave -noupdate /main/DUT/tm_dac_wr_p
+add wave -noupdate /main/DUT/tm_tai
+add wave -noupdate /main/DUT/tm_cycles
+add wave -noupdate /main/DUT/tm_dac_value
+add wave -noupdate /main/DUT/tm_dac_value_reg
+add wave -noupdate /main/DUT/tm_clk_aux_lock_en
+add wave -noupdate /main/DUT/tm_clk_aux_locked
+add wave -noupdate /main/DUT/phy_tx_data
+add wave -noupdate /main/DUT/phy_rx_data
+add wave -noupdate /main/DUT/phy_tx_k
+add wave -noupdate /main/DUT/phy_tx_disparity
+add wave -noupdate /main/DUT/phy_rx_k
+add wave -noupdate /main/DUT/phy_tx_enc_err
+add wave -noupdate /main/DUT/phy_rx_rbclk
+add wave -noupdate /main/DUT/phy_rx_enc_err
+add wave -noupdate /main/DUT/phy_rst
+add wave -noupdate /main/DUT/phy_loopen
+add wave -noupdate /main/DUT/phy_rx_bitslide
+add wave -noupdate /main/DUT/dac_hpll_load_p1
+add wave -noupdate /main/DUT/dac_dpll_load_p1
+add wave -noupdate /main/DUT/dac_hpll_data
+add wave -noupdate /main/DUT/dac_dpll_data
+add wave -noupdate /main/DUT/wrc_scl_out
+add wave -noupdate /main/DUT/wrc_scl_in
+add wave -noupdate /main/DUT/wrc_sda_out
+add wave -noupdate /main/DUT/wrc_sda_in
+add wave -noupdate /main/DUT/tdc_scl_out
+add wave -noupdate /main/DUT/tdc_scl_in
+add wave -noupdate /main/DUT/tdc_sda_out
+add wave -noupdate /main/DUT/tdc_sda_in
+add wave -noupdate /main/DUT/tdc_scl_oen
+add wave -noupdate /main/DUT/tdc_sda_oen
+add wave -noupdate /main/DUT/sfp_scl_out
+add wave -noupdate /main/DUT/sfp_scl_in
+add wave -noupdate /main/DUT/sfp_sda_out
+add wave -noupdate /main/DUT/sfp_sda_in
+add wave -noupdate /main/DUT/wrc_owr_en
+add wave -noupdate /main/DUT/wrc_owr_in
+add wave -noupdate /main/DUT/tdc0_irq
+add wave -noupdate /main/DUT/tdc0_clk_125m
+add wave -noupdate /main/DUT/tdc0_soft_rst_n
+add wave -noupdate /main/DUT/powerup_rst_cnt
+add wave -noupdate /main/DUT/carrier_info_fmc_rst
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {916212143 ps} 0}
+configure wave -namecolwidth 177
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {3698688 ns}
diff --git a/hdl/testbench/spec/wrc-simulation.ram b/hdl/testbench/spec/wrc-simulation.ram
new file mode 100644
index 0000000..0a52b48
--- /dev/null
+++ b/hdl/testbench/spec/wrc-simulation.ram
@@ -0,0 +1,1000 @@
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diff --git a/hdl/testbench/svec/Manifest.py b/hdl/testbench/svec/Manifest.py
index 0c2a8c1..46c65d0 100644
--- a/hdl/testbench/svec/Manifest.py
+++ b/hdl/testbench/svec/Manifest.py
@@ -1,7 +1,11 @@
+sim_tool = "modelsim"
+top_module="main"
+syn_device="xc6slx150t"
+
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
-vlog_opt="+incdir+../../sim +incdir+../include/vme64x_bfm +incdir+../include "
+include_dirs=[ "../../sim", "../include", "../../ip_cores/vme64x-core/hdl/vme64x-core/sim/vme64x_bfm" ]
files = [ "main.sv" ]
diff --git a/hdl/top/spec/Manifest.py b/hdl/top/spec/Manifest.py
new file mode 100644
index 0000000..c4644d0
--- /dev/null
+++ b/hdl/top/spec/Manifest.py
@@ -0,0 +1,14 @@
+files = ["synthesis_descriptor.vhd",
+"wr_spec_tdc.ucf",
+"wr_spec_tdc.vhd"];
+
+fetchto = "../../ip_cores"
+
+modules = {
+ "local" : [ "../../rtl/",
+ "../../ip_cores/gn4124-core",
+ "../../ip_cores/general-cores",
+ "../../ip_cores/wr-cores"
+ ]
+ }
+
diff --git a/hdl/top/spec/build_wb.sh b/hdl/top/spec/build_wb.sh
deleted file mode 100755
index 352169d..0000000
--- a/hdl/top/spec/build_wb.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-#!/bin/bash
-
-wbgen2 -D 1.html -V fmc_tdc_direct_readout_slave.vhd -H record -p fmc_tdc_direct_readout_slave_pkg.vhd -K regs.vh -s defines -C fmctdc-direct.h fmc_tdc_direct_readout_slave.wb
diff --git a/hdl/top/spec/spec_reset_gen.vhd b/hdl/top/spec/spec_reset_gen.vhd
deleted file mode 100644
index b2a399c..0000000
--- a/hdl/top/spec/spec_reset_gen.vhd
+++ /dev/null
@@ -1,55 +0,0 @@
-library ieee;
-use ieee.STD_LOGIC_1164.all;
-use ieee.NUMERIC_STD.all;
-
-use work.gencores_pkg.all;
-
-entity spec_reset_gen is
-
- port (
- clk_sys_i : in std_logic;
-
- rst_pcie_n_a_i : in std_logic;
- rst_button_n_a_i : in std_logic;
-
- rst_n_o : out std_logic
- );
-
-end spec_reset_gen;
-
-architecture behavioral of spec_reset_gen is
-
- signal powerup_cnt : unsigned(7 downto 0) := x"00";
- signal button_synced_n : std_logic;
- signal pcie_synced_n : std_logic;
- signal powerup_n : std_logic := '0';
-
-begin -- behavioral
-
- U_EdgeDet_PCIe : gc_sync_ffs port map (
- clk_i => clk_sys_i,
- rst_n_i => '1',
- data_i => rst_pcie_n_a_i,
- ppulse_o => pcie_synced_n);
-
- U_Sync_Button : gc_sync_ffs port map (
- clk_i => clk_sys_i,
- rst_n_i => '1',
- data_i => rst_button_n_a_i,
- synced_o => button_synced_n);
-
- p_powerup_reset : process(clk_sys_i)
- begin
- if rising_edge(clk_sys_i) then
- if(powerup_cnt /= x"ff") then
- powerup_cnt <= powerup_cnt + 1;
- powerup_n <= '0';
- else
- powerup_n <= '1';
- end if;
- end if;
- end process;
-
- rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
-
-end behavioral;
diff --git a/hdl/top/spec/tdc_core_pkg.vhd b/hdl/top/spec/tdc_core_pkg.vhd
deleted file mode 100644
index 21a88ff..0000000
--- a/hdl/top/spec/tdc_core_pkg.vhd
+++ /dev/null
@@ -1,1067 +0,0 @@
---_________________________________________________________________________________________________
--- |
--- |TDC core| |
--- |
--- CERN,BE/CO-HT |
---________________________________________________________________________________________________|
-
----------------------------------------------------------------------------------------------------
--- |
--- tdc_core_pkg |
--- |
----------------------------------------------------------------------------------------------------
--- File tdc_core_pkg.vhd |
--- |
--- Description Package containing core wide constants and components |
--- |
--- |
--- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
--- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
--- Date 04/2012 |
--- Version v0.2 |
--- Depends on |
--- |
----------------- |
--- Last changes |
--- 07/2011 v0.1 GP First version |
--- 04/2012 v0.2 EG Revamping; Gathering of all the constants, declarations of all the |
--- units; Comments added, signals renamed |
--- |
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- GNU LESSER GENERAL PUBLIC LICENSE |
--- ------------------------------------ |
--- This source file is free software; you can redistribute it and/or modify it under the terms of |
--- the GNU Lesser General Public License as published by the Free Software Foundation; either |
--- version 2.1 of the License, or (at your option) any later version. |
--- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
--- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
--- See the GNU Lesser General Public License for more details. |
--- You should have received a copy of the GNU Lesser General Public License along with this |
--- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
----------------------------------------------------------------------------------------------------
-
-
-
---=================================================================================================
--- Libraries & Packages
---=================================================================================================
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
-use IEEE.NUMERIC_STD.all; -- conversion functions
-use work.wishbone_pkg.all;
-use work.gencores_pkg.all;
-
-
---=================================================================================================
--- Package declaration for tdc_core_pkg
---=================================================================================================
-package tdc_core_pkg is
-
----------------------------------------------------------------------------------------------------
--- Constant regarding the Mezzanine DAC configuration --
----------------------------------------------------------------------------------------------------
- -- Vout = Vref (DAC_WORD/ 65536); for Vout = 1.65V, with Vref = 2.5V the DAC_WORD = xA8F5
- constant c_DEFAULT_DAC_WORD : std_logic_vector(23 downto 0) := x"00A8F5";
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding the SDB Devices Definitions --
----------------------------------------------------------------------------------------------------
--- Note: All address in sdb and crossbar are BYTE addresses!
-
- -- Devices sdb description
- constant c_ONEWIRE_SDB_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"0000000000000007",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000602", -- "WB-Onewire.Control " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20121116",
- name => "WB-Onewire.Control ")));
-
- constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"000000000000001F",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20121116",
- name => "WB-SPEC.CSR ")));
-
- constant c_TDC_EIC_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"000000000000000F",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000605", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20121116",
- name => "WB-FMC-TDC.EIC ")));
-
-
- constant c_I2C_SDB_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"000000000000001F",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000606", -- "WB-I2C.Control " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20121116",
- name => "WB-I2C.Control ")));
-
- constant c_TDC_EIC_SDB : t_sdb_device := (
- abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component => (
- addr_first => x"0000000000000000",
- addr_last => x"000000000000000F",
- product => (
- vendor_id => x"000000000000CE42", -- CERN
- device_id => x"26ec6086", -- "WB-FMC-TDC.EIC " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20131204",
- name => "WB-FMC-TDC.EIC ")));
-
- constant c_TDC_CONFIG_SDB_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"00000000000000FF",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000604", -- "WB-TDC-Core-Config " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20130429",
- name => "WB-TDC-Core-Config ")));
-
- constant c_TDC_MEM_SDB_DEVICE : t_sdb_device :=
- (abi_class => x"0000", -- undocumented device
- abi_ver_major => x"01",
- abi_ver_minor => x"01",
- wbd_endian => c_sdb_endian_big,
- wbd_width => x"4", -- 32-bit port granularity
- sdb_component =>
- (addr_first => x"0000000000000000",
- addr_last => x"0000000000000FFF",
- product =>
- (vendor_id => x"000000000000CE42", -- CERN
- device_id => x"00000601", -- "WB-TDC-Mem " | md5sum | cut -c1-8
- version => x"00000001",
- date => x"20121116",
- name => "WB-TDC-Mem ")));
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding 1 Hz pulse generation --
----------------------------------------------------------------------------------------------------
-
- -- for synthesis: 1 sec = x"07735940" clk_i cycles (1 clk_i cycle = 8ns)
- constant c_SYN_CLK_PERIOD : std_logic_vector(31 downto 0) := x"07735940";
-
- -- for simulation: 1 msec = x"0001E848" clk_i cycles (1 clk_i cycle = 8ns)
- constant c_SIM_CLK_PERIOD : std_logic_vector(31 downto 0) := x"0001E848";
-
-
----------------------------------------------------------------------------------------------------
--- Vector with the 11 ACAM Configuration Registers --
----------------------------------------------------------------------------------------------------
- subtype config_register is std_logic_vector(31 downto 0);
- type config_vector is array (10 downto 0) of config_register;
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding addressing of the ACAM registers --
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- Addresses of ACAM configuration registers to be written by the PCIe host
- -- corresponds to:
- constant c_ACAM_REG0_ADR : std_logic_vector(7 downto 0) := x"00"; -- address 0x51000 of GN4124 BAR 0
- constant c_ACAM_REG1_ADR : std_logic_vector(7 downto 0) := x"01"; -- address 0x51004 of GN4124 BAR 0
- constant c_ACAM_REG2_ADR : std_logic_vector(7 downto 0) := x"02"; -- address 0x51008 of GN4124 BAR 0
- constant c_ACAM_REG3_ADR : std_logic_vector(7 downto 0) := x"03"; -- address 0x5100C of GN4124 BAR 0
- constant c_ACAM_REG4_ADR : std_logic_vector(7 downto 0) := x"04"; -- address 0x51010 of GN4124 BAR 0
- constant c_ACAM_REG5_ADR : std_logic_vector(7 downto 0) := x"05"; -- address 0x51014 of GN4124 BAR 0
- constant c_ACAM_REG6_ADR : std_logic_vector(7 downto 0) := x"06"; -- address 0x51018 of GN4124 BAR 0
- constant c_ACAM_REG7_ADR : std_logic_vector(7 downto 0) := x"07"; -- address 0x5101C of GN4124 BAR 0
- constant c_ACAM_REG11_ADR : std_logic_vector(7 downto 0) := x"0B"; -- address 0x5102C of GN4124 BAR 0
- constant c_ACAM_REG12_ADR : std_logic_vector(7 downto 0) := x"0C"; -- address 0x51030 of GN4124 BAR 0
- constant c_ACAM_REG14_ADR : std_logic_vector(7 downto 0) := x"0E"; -- address 0x51038 of GN4124 BAR 0
-
-
----------------------------------------------------------------------------------------------------
--- Addresses of ACAM read-only registers, to be written by the ACAM and used within the core to access ACAM timestamps
- constant c_ACAM_REG8_ADR : std_logic_vector(7 downto 0) := x"08"; -- not accessible for writing from PCI-e
- constant c_ACAM_REG9_ADR : std_logic_vector(7 downto 0) := x"09"; -- not accessible for writing from PCI-e
- constant c_ACAM_REG10_ADR : std_logic_vector(7 downto 0) := x"0A"; -- not accessible for writing from PCI-e
-
-
----------------------------------------------------------------------------------------------------
--- Addresses of ACAM configuration readback registers, to be written by the ACAM
- -- corresponds to:
- constant c_ACAM_REG0_RDBK_ADR : std_logic_vector(7 downto 0) := x"10"; -- address 0x51040 of the GN4124 BAR 0
- constant c_ACAM_REG1_RDBK_ADR : std_logic_vector(7 downto 0) := x"11"; -- address 0x51044 of the GN4124 BAR 0
- constant c_ACAM_REG2_RDBK_ADR : std_logic_vector(7 downto 0) := x"12"; -- address 0x51048 of the GN4124 BAR 0
- constant c_ACAM_REG3_RDBK_ADR : std_logic_vector(7 downto 0) := x"13"; -- address 0x5104C of the GN4124 BAR 0
- constant c_ACAM_REG4_RDBK_ADR : std_logic_vector(7 downto 0) := x"14"; -- address 0x51050 of the GN4124 BAR 0
- constant c_ACAM_REG5_RDBK_ADR : std_logic_vector(7 downto 0) := x"15"; -- address 0x51054 of the GN4124 BAR 0
- constant c_ACAM_REG6_RDBK_ADR : std_logic_vector(7 downto 0) := x"16"; -- address 0x51058 of the GN4124 BAR 0
- constant c_ACAM_REG7_RDBK_ADR : std_logic_vector(7 downto 0) := x"17"; -- address 0x5105C of the GN4124 BAR 0
- constant c_ACAM_REG8_RDBK_ADR : std_logic_vector(7 downto 0) := x"18"; -- address 0x51060 of the GN4124 BAR 0
- constant c_ACAM_REG9_RDBK_ADR : std_logic_vector(7 downto 0) := x"19"; -- address 0x51064 of the GN4124 BAR 0
- constant c_ACAM_REG10_RDBK_ADR : std_logic_vector(7 downto 0) := x"1A"; -- address 0x51068 of the GN4124 BAR 0
- constant c_ACAM_REG11_RDBK_ADR : std_logic_vector(7 downto 0) := x"1B"; -- address 0x5106C of the GN4124 BAR 0
- constant c_ACAM_REG12_RDBK_ADR : std_logic_vector(7 downto 0) := x"1C"; -- address 0x51070 of the GN4124 BAR 0
- constant c_ACAM_REG14_RDBK_ADR : std_logic_vector(7 downto 0) := x"1E"; -- address 0x51078 of the GN4124 BAR 0
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding addressing of the TDC core registers --
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
--- Addresses of TDC core Configuration registers to be written by the PCIe host
- -- corresponds to:
- constant c_STARTING_UTC_ADR : std_logic_vector(7 downto 0) := x"20"; -- address 0x51080 of GN4124 BAR 0
- constant c_ACAM_INPUTS_EN_ADR : std_logic_vector(7 downto 0) := x"21"; -- address 0x51084 of GN4124 BAR 0
- constant c_START_PHASE_ADR : std_logic_vector(7 downto 0) := x"22"; -- address 0x51088 of GN4124 BAR 0
- constant c_ONE_HZ_PHASE_ADR : std_logic_vector(7 downto 0) := x"23"; -- address 0x5108C of GN4124 BAR 0
-
- constant c_IRQ_TSTAMP_THRESH_ADR: std_logic_vector(7 downto 0) := x"24"; -- address 0x51090 of GN4124 BAR 0
- constant c_IRQ_TIME_THRESH_ADR : std_logic_vector(7 downto 0) := x"25"; -- address 0x51094 of GN4124 BAR 0
- constant c_DAC_WORD_ADR : std_logic_vector(7 downto 0) := x"26"; -- address 0x51098 of GN4124 BAR 0
-
- constant c_DEACT_CHAN_ADR : std_logic_vector(7 downto 0) := x"27"; -- address 0x5109C of GN4124 BAR 0
-
----------------------------------------------------------------------------------------------------
--- Addresses of TDC core Status registers to be written by the different core units
- -- corresponds to:
- constant c_LOCAL_UTC_ADR : std_logic_vector(7 downto 0) := x"28"; -- address 0x510A0 of GN4124 BAR 0
- constant c_IRQ_CODE_ADR : std_logic_vector(7 downto 0) := x"29"; -- address 0x510A4 of GN4124 BAR 0
- constant c_WR_INDEX_ADR : std_logic_vector(7 downto 0) := x"2A"; -- address 0x510A8 of GN4124 BAR 0
- constant c_CORE_STATUS_ADR : std_logic_vector(7 downto 0) := x"2B"; -- address 0x510AC of GN4124 BAR 0
-
----------------------------------------------------------------------------------------------------
--- Addresses of the White Rabbit control and status registers
-
- constant c_WRABBIT_STATUS_ADR : std_logic_vector(7 downto 0) := x"2C"; -- address 0x510B0 of GN4124 BAR 0
- constant c_WRABBIT_CTRL_ADR : std_logic_vector(7 downto 0) := x"2D"; -- address 0x510B4 of GN4124 BAR 0
-
----------------------------------------------------------------------------------------------------
--- Address of TDC core Control register
- -- corresponds to:
- constant c_CTRL_REG_ADR : std_logic_vector(7 downto 0) := x"3F"; -- address 0x510FC of GN4124 BAR 0
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding ACAM retriggers --
----------------------------------------------------------------------------------------------------
- -- Number of clk_i cycles corresponding to the Acam retrigger period;
- -- through Acam Reg 4 StartTimer the chip is programmed to retrigger every:
- -- (15+1) * acam_ref_clk = (15+1) * 32 ns
- -- x"00000040" * clk_i = 64 * 8 ns
- -- 512 ns
- constant c_ACAM_RETRIG_PERIOD : std_logic_vector(31 downto 0) := x"00000040";
-
- -- Used to multiply by 64, which is the retrigger period in clk_i cycles
- constant c_ACAM_RETRIG_PERIOD_SHIFT : integer := 6;
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding TDC & SPEC LEDs --
----------------------------------------------------------------------------------------------------
-
- constant c_SPEC_LED_PERIOD_SIM : std_logic_vector(31 downto 0) := x"00004E20"; -- 1 ms at 20 MHz
- constant c_SPEC_LED_PERIOD_SYN : std_logic_vector(31 downto 0) := x"01312D00"; -- 1 s at 20 MHz
- constant c_BLINK_LGTH_SYN : std_logic_vector(31 downto 0) := x"00BEBC20"; -- 100 ms at 125 MHz
- constant c_BLINK_LGTH_SIM : std_logic_vector(31 downto 0) := x"000004E2"; -- 10 us at 125 MHz
---c_RESET_WORD
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding the Circular Buffer --
----------------------------------------------------------------------------------------------------
- constant c_CIRCULAR_BUFF_SIZE : unsigned(31 downto 0) := x"00000100";
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding the One-Wire interface --
----------------------------------------------------------------------------------------------------
- constant c_FMC_ONEWIRE_NB : integer := 1;
-
-
----------------------------------------------------------------------------------------------------
--- Constants regarding the Carrier CSR info --
----------------------------------------------------------------------------------------------------
- constant c_CARRIER_TYPE : std_logic_vector(15 downto 0) := X"0001";
-
-
----------------------------------------------------------------------------------------------------
--- Components Declarations --
----------------------------------------------------------------------------------------------------
-
----------------------------------------------------------------------------------------------------
- component fmc_tdc_mezzanine is
- generic
- (g_with_wrabbit_core : boolean := FALSE;
- g_span : integer := 32;
- g_width : integer := 32;
- values_for_simul : boolean := FALSE);
- port
- -- 62.5MHz clock and synchronous reset
- (clk_sys_i : in std_logic;
- rst_sys_n_i : in std_logic;
- -- Signals from the clks_rsts_manager unit
- clk_ref_0_i : in std_logic;
- rst_ref_0_i : in std_logic;
- -- TDC core
- acam_refclk_r_edge_p_i : in std_logic;
- send_dac_word_p_o : out std_logic;
- dac_word_o : out std_logic_vector(23 downto 0);
- start_from_fpga_o : out std_logic;
- err_flag_i : in std_logic;
- int_flag_i : in std_logic;
- start_dis_o : out std_logic;
- stop_dis_o : out std_logic;
- data_bus_io : inout std_logic_vector(27 downto 0);
- address_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic;
- oe_n_o : out std_logic;
- rd_n_o : out std_logic;
- wr_n_o : out std_logic;
- ef1_i : in std_logic;
- ef2_i : in std_logic;
- tdc_in_fpga_1_i : in std_logic;
- tdc_in_fpga_2_i : in std_logic;
- tdc_in_fpga_3_i : in std_logic;
- tdc_in_fpga_4_i : in std_logic;
- tdc_in_fpga_5_i : in std_logic;
- enable_inputs_o : out std_logic;
- term_en_1_o : out std_logic;
- term_en_2_o : out std_logic;
- term_en_3_o : out std_logic;
- term_en_4_o : out std_logic;
- term_en_5_o : out std_logic;
- tdc_led_status_o : out std_logic;
- tdc_led_trig1_o : out std_logic;
- tdc_led_trig2_o : out std_logic;
- tdc_led_trig3_o : out std_logic;
- tdc_led_trig4_o : out std_logic;
- tdc_led_trig5_o : out std_logic;
- -- White Rabbit core
- wrabbit_link_up_i : in std_logic;
- wrabbit_time_valid_i : in std_logic;
- wrabbit_cycles_i : in std_logic_vector(27 downto 0);
- wrabbit_utc_i : in std_logic_vector(31 downto 0);
- wrabbit_clk_aux_lock_en_o : out std_logic;
- wrabbit_clk_aux_locked_i : in std_logic;
- wrabbit_clk_dmtd_locked_i : in std_logic;
- wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
- wrabbit_dac_wr_p_i : in std_logic;
- -- WISHBONE interface with the GN4124/VME_core
- -- for the core configuration | timestamps retrieval | core interrupts | 1Wire | I2C
- wb_tdc_csr_adr_i : in std_logic_vector(31 downto 0);
- wb_tdc_csr_dat_i : in std_logic_vector(31 downto 0);
- wb_tdc_csr_cyc_i : in std_logic;
- wb_tdc_csr_sel_i : in std_logic_vector(3 downto 0);
- wb_tdc_csr_stb_i : in std_logic;
- wb_tdc_csr_we_i : in std_logic;
- wb_tdc_csr_dat_o : out std_logic_vector(31 downto 0);
- wb_tdc_csr_ack_o : out std_logic;
- wb_tdc_csr_stall_o : out std_logic;
- wb_irq_o : out std_logic;
- -- I2C EEPROM interface
- i2c_scl_o : out std_logic;
- i2c_scl_oen_o : out std_logic;
- i2c_scl_i : in std_logic;
- i2c_sda_o : out std_logic;
- i2c_sda_oen_o : out std_logic;
- i2c_sda_i : in std_logic;
- -- 1-wire UniqueID&Thermometer interface
- onewire_b : inout std_logic);
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component fmc_tdc_core
- generic
- (g_span : integer := 32;
- g_width : integer := 32;
- values_for_simul : boolean := FALSE);
- port
- (clk_125m_i : in std_logic;
- rst_i : in std_logic;
- acam_refclk_r_edge_p_i : in std_logic;
- send_dac_word_p_o : out std_logic;
- dac_word_o : out std_logic_vector(23 downto 0);
- start_from_fpga_o : out std_logic;
- err_flag_i : in std_logic;
- int_flag_i : in std_logic;
- start_dis_o : out std_logic;
- stop_dis_o : out std_logic;
- data_bus_io : inout std_logic_vector(27 downto 0);
- address_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic;
- oe_n_o : out std_logic;
- rd_n_o : out std_logic;
- wr_n_o : out std_logic;
- ef1_i : in std_logic;
- ef2_i : in std_logic;
- tdc_in_fpga_1_i : in std_logic;
- tdc_in_fpga_2_i : in std_logic;
- tdc_in_fpga_3_i : in std_logic;
- tdc_in_fpga_4_i : in std_logic;
- tdc_in_fpga_5_i : in std_logic;
- enable_inputs_o : out std_logic;
- term_en_1_o : out std_logic;
- term_en_2_o : out std_logic;
- term_en_3_o : out std_logic;
- term_en_4_o : out std_logic;
- term_en_5_o : out std_logic;
- tdc_led_status_o : out std_logic;
- tdc_led_trig1_o : out std_logic;
- tdc_led_trig2_o : out std_logic;
- tdc_led_trig3_o : out std_logic;
- tdc_led_trig4_o : out std_logic;
- tdc_led_trig5_o : out std_logic;
- wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
- wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0);
- wrabbit_synched_i : in std_logic;
- wrabbit_tai_p_i : in std_logic;
- wrabbit_tai_i : in std_logic_vector(31 downto 0);
- irq_tstamp_p_o : out std_logic;
- irq_time_p_o : out std_logic;
- irq_acam_err_p_o : out std_logic;
- tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
- tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
- tdc_config_wb_stb_i : in std_logic;
- tdc_config_wb_we_i : in std_logic;
- tdc_config_wb_cyc_i : in std_logic;
- tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
- tdc_config_wb_ack_o : out std_logic;
- tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
- tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
- tdc_mem_wb_stb_i : in std_logic;
- tdc_mem_wb_we_i : in std_logic;
- tdc_mem_wb_cyc_i : in std_logic;
- tdc_mem_wb_ack_o : out std_logic;
- tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
- tdc_mem_wb_stall_o : out std_logic);
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component wrabbit_sync is
- generic
- (g_simulation : boolean;
- g_with_wrabbit_core : boolean);
- port
- (clk_sys_i : in std_logic;
- rst_n_sys_i : in std_logic;
- clk_ref_i : in std_logic;
- rst_n_ref_i : in std_logic;
- wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
- wrabbit_dac_wr_p_i : in std_logic;
- wrabbit_link_up_i : in std_logic;
- wrabbit_time_valid_i : in std_logic; -- this is i te clk_ref_0 domain, no??
- wrabbit_clk_aux_lock_en_o : out std_logic;
- wrabbit_clk_aux_locked_i : in std_logic;
- wrabbit_clk_dmtd_locked_i : in std_logic;
- wrabbit_synched_o : out std_logic;
- wrabbit_reg_i : in std_logic_vector(31 downto 0);
- wrabbit_reg_o : out std_logic_vector(31 downto 0));
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component spec_serial_dac -- for White Rabbit
- generic
- (g_num_data_bits : integer;
- g_num_extra_bits : integer;
- g_num_cs_select : integer);
- port
- (clk_i : in std_logic;
- rst_n_i : in std_logic;
- value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
- cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
- load_i : in std_logic;
- sclk_divsel_i : in std_logic_vector(2 downto 0);
- dac_cs_n_o : out std_logic_vector(g_num_cs_select-1 downto 0);
- dac_sclk_o : out std_logic;
- dac_sdata_o : out std_logic;
- xdone_o : out std_logic);
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component xvme64x_core
- port (
- clk_i : in std_logic;
- rst_n_i : in std_logic;
- VME_AS_n_i : in std_logic;
- VME_RST_n_i : in std_logic;
- VME_WRITE_n_i : in std_logic;
- VME_AM_i : in std_logic_vector(5 downto 0);
- VME_DS_n_i : in std_logic_vector(1 downto 0);
- VME_GA_i : in std_logic_vector(5 downto 0);
- VME_BERR_o : out std_logic;
- VME_DTACK_n_o : out std_logic;
- VME_RETRY_n_o : out std_logic;
- VME_RETRY_OE_o : out std_logic;
- VME_LWORD_n_b_i : in std_logic;
- VME_LWORD_n_b_o : out std_logic;
- VME_ADDR_b_i : in std_logic_vector(31 downto 1);
- VME_ADDR_b_o : out std_logic_vector(31 downto 1);
- VME_DATA_b_i : in std_logic_vector(31 downto 0);
- VME_DATA_b_o : out std_logic_vector(31 downto 0);
- VME_IRQ_n_o : out std_logic_vector(6 downto 0);
- VME_IACKIN_n_i : in std_logic;
- VME_IACK_n_i : in std_logic;
- VME_IACKOUT_n_o : out std_logic;
- VME_DTACK_OE_o : out std_logic;
- VME_DATA_DIR_o : out std_logic;
- VME_DATA_OE_N_o : out std_logic;
- VME_ADDR_DIR_o : out std_logic;
- VME_ADDR_OE_N_o : out std_logic;
- master_o : out t_wishbone_master_out;
- master_i : in t_wishbone_master_in;
- irq_i : in std_logic;
- irq_ack_o : out std_logic);
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component decr_counter
- generic
- (width : integer := 32);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- counter_load_i : in std_logic;
- counter_top_i : in std_logic_vector(width-1 downto 0);
- -------------------------------------------------------------
- counter_is_zero_o : out std_logic;
- counter_o : out std_logic_vector(width-1 downto 0));
- -------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component free_counter is
- generic
- (width : integer := 32);
- port
- (clk_i : in std_logic;
- counter_en_i : in std_logic;
- rst_i : in std_logic;
- counter_top_i : in std_logic_vector(width-1 downto 0);
- -------------------------------------------------------------
- counter_is_zero_o : out std_logic;
- counter_o : out std_logic_vector(width-1 downto 0));
- -------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component incr_counter
- generic
- (width : integer := 32);
- port
- (clk_i : in std_logic;
- counter_top_i : in std_logic_vector(width-1 downto 0);
- counter_incr_en_i : in std_logic;
- rst_i : in std_logic;
- -------------------------------------------------------------
- counter_is_full_o : out std_logic;
- counter_o : out std_logic_vector(width-1 downto 0));
- -------------------------------------------------------------
- end component;
----------------------------------------------------------------------------------------------------
-
-
----------------------------------------------------------------------------------------------------
- component start_retrig_ctrl
- generic
- (g_width : integer := 32);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- acam_intflag_f_edge_p_i : in std_logic;
- utc_p_i : in std_logic;
- ----------------------------------------------------------------------
- current_retrig_nb_o : out std_logic_vector(g_width-1 downto 0);
- roll_over_incr_recent_o : out std_logic;
- clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
- roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
- retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component local_pps_gen
- generic
- (g_width : integer := 32);
- port
- (acam_refclk_r_edge_p_i : in std_logic;
- clk_i : in std_logic;
- clk_period_i : in std_logic_vector(g_width-1 downto 0);
- load_utc_p_i : in std_logic;
- pulse_delay_i : in std_logic_vector(g_width-1 downto 0);
- rst_i : in std_logic;
- starting_utc_i : in std_logic_vector(g_width-1 downto 0);
- ----------------------------------------------------------------------
- local_utc_o : out std_logic_vector(g_width-1 downto 0);
- local_utc_p_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component data_engine
- port
- (acam_ack_i : in std_logic;
- acam_dat_i : in std_logic_vector(31 downto 0);
- clk_i : in std_logic;
- rst_i : in std_logic;
- acam_ef1_i : in std_logic;
- acam_ef1_meta_i : in std_logic;
- acam_ef2_i : in std_logic;
- acam_ef2_meta_i : in std_logic;
- activate_acq_p_i : in std_logic;
- deactivate_acq_p_i : in std_logic;
- acam_wr_config_p_i : in std_logic;
- acam_rdbk_config_p_i : in std_logic;
- acam_rdbk_status_p_i : in std_logic;
- acam_rdbk_ififo1_p_i : in std_logic;
- acam_rdbk_ififo2_p_i : in std_logic;
- acam_rdbk_start01_p_i : in std_logic;
- acam_rst_p_i : in std_logic;
- acam_config_i : in config_vector;
- start_from_fpga_i : in std_logic;
- ----------------------------------------------------------------------
- state_active_p_o : out std_logic;
- acam_adr_o : out std_logic_vector(7 downto 0);
- acam_cyc_o : out std_logic;
- acam_dat_o : out std_logic_vector(31 downto 0);
- acam_stb_o : out std_logic;
- acam_we_o : out std_logic;
- acam_config_rdbk_o : out config_vector;
- acam_ififo1_o : out std_logic_vector(31 downto 0);
- acam_ififo2_o : out std_logic_vector(31 downto 0);
- acam_start01_o : out std_logic_vector(31 downto 0);
- acam_tstamp1_o : out std_logic_vector(31 downto 0);
- acam_tstamp1_ok_p_o : out std_logic;
- acam_tstamp2_o : out std_logic_vector(31 downto 0);
- acam_tstamp2_ok_p_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component reg_ctrl
- generic
- (g_span : integer := 32;
- g_width : integer := 32);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- tdc_config_wb_adr_i : in std_logic_vector(g_span-1 downto 0);
- tdc_config_wb_cyc_i : in std_logic;
- tdc_config_wb_dat_i : in std_logic_vector(g_width-1 downto 0);
- tdc_config_wb_stb_i : in std_logic;
- tdc_config_wb_we_i : in std_logic;
- acam_config_rdbk_i : in config_vector;
- acam_ififo1_i : in std_logic_vector(g_width-1 downto 0);
- acam_ififo2_i : in std_logic_vector(g_width-1 downto 0);
- acam_start01_i : in std_logic_vector(g_width-1 downto 0);
- local_utc_i : in std_logic_vector(g_width-1 downto 0);
- irq_code_i : in std_logic_vector(g_width-1 downto 0);
- wr_index_i : in std_logic_vector(g_width-1 downto 0);
- core_status_i : in std_logic_vector(g_width-1 downto 0);
- wrabbit_status_reg_i : in std_logic_vector(g_width-1 downto 0);
- ----------------------------------------------------------------------
- tdc_config_wb_ack_o : out std_logic;
- tdc_config_wb_dat_o : out std_logic_vector(g_width-1 downto 0);
- activate_acq_p_o : out std_logic;
- deactivate_acq_p_o : out std_logic;
- deactivate_chan_o : out std_logic_vector(4 downto 0);
- acam_wr_config_p_o : out std_logic;
- acam_rdbk_config_p_o : out std_logic;
- acam_rdbk_status_p_o : out std_logic;
- acam_rdbk_ififo1_p_o : out std_logic;
- acam_rdbk_ififo2_p_o : out std_logic;
- acam_rdbk_start01_p_o : out std_logic;
- acam_rst_p_o : out std_logic;
- load_utc_p_o : out std_logic;
- irq_tstamp_threshold_o : out std_logic_vector(g_width-1 downto 0);
- irq_time_threshold_o : out std_logic_vector(g_width-1 downto 0);
- send_dac_word_p_o : out std_logic;
- dac_word_o : out std_logic_vector(23 downto 0);
- dacapo_c_rst_p_o : out std_logic;
- acam_config_o : out config_vector;
- starting_utc_o : out std_logic_vector(g_width-1 downto 0);
- acam_inputs_en_o : out std_logic_vector(g_width-1 downto 0);
- start_phase_o : out std_logic_vector(g_width-1 downto 0);
- one_hz_phase_o : out std_logic_vector(g_width-1 downto 0);
- wrabbit_ctrl_reg_o : out std_logic_vector(g_width-1 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component acam_timecontrol_interface
- port
- (err_flag_i : in std_logic;
- int_flag_i : in std_logic;
- acam_refclk_r_edge_p_i : in std_logic;
- utc_p_i : in std_logic;
- clk_i : in std_logic;
- activate_acq_p_i : in std_logic;
- rst_i : in std_logic;
- state_active_p_i : in std_logic;
- deactivate_acq_p_i : in std_logic;
- ----------------------------------------------------------------------
- start_from_fpga_o : out std_logic;
- stop_dis_o : out std_logic;
- acam_errflag_r_edge_p_o : out std_logic;
- acam_errflag_f_edge_p_o : out std_logic;
- acam_intflag_f_edge_p_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component data_formatting
- port
- (tstamp_wr_wb_ack_i : in std_logic;
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
- acam_tstamp1_i : in std_logic_vector(31 downto 0);
- acam_tstamp1_ok_p_i : in std_logic;
- acam_tstamp2_i : in std_logic_vector(31 downto 0);
- acam_tstamp2_ok_p_i : in std_logic;
- clk_i : in std_logic;
- dacapo_c_rst_p_i : in std_logic;
- deactivate_chan_i : in std_logic_vector(4 downto 0);
- rst_i : in std_logic;
- roll_over_incr_recent_i : in std_logic;
- clk_i_cycles_offset_i : in std_logic_vector(31 downto 0);
- roll_over_nb_i : in std_logic_vector(31 downto 0);
- utc_i : in std_logic_vector(31 downto 0);
- retrig_nb_offset_i : in std_logic_vector(31 downto 0);
- utc_p_i : in std_logic;
- ----------------------------------------------------------------------
- tstamp_wr_wb_adr_o : out std_logic_vector(7 downto 0);
- tstamp_wr_wb_cyc_o : out std_logic;
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
- tstamp_wr_wb_stb_o : out std_logic;
- tstamp_wr_wb_we_o : out std_logic;
- tstamp_wr_p_o : out std_logic;
- acam_channel_o : out std_logic_vector(2 downto 0);
- wr_index_o : out std_logic_vector(31 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component irq_generator is
- generic
- (g_width : integer := 32);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- irq_tstamp_threshold_i : in std_logic_vector(g_width-1 downto 0);
- irq_time_threshold_i : in std_logic_vector(g_width-1 downto 0);
- activate_acq_p_i : in std_logic;
- deactivate_acq_p_i : in std_logic;
- tstamp_wr_p_i : in std_logic;
- acam_errflag_r_edge_p_i : in std_logic;
- ----------------------------------------------------------------------
- irq_tstamp_p_o : out std_logic;
- irq_acam_err_p_o : out std_logic;
- irq_time_p_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component tdc_eic
- port
- (rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- wb_adr_i : in std_logic_vector(1 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_dat_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_stall_o : out std_logic;
- wb_int_o : out std_logic;
- irq_tdc_tstamps_i : in std_logic;
- irq_tdc_time_i : in std_logic;
- irq_tdc_acam_err_i : in std_logic);
- end component tdc_eic;
-
-
----------------------------------------------------------------------------------------------------
- component clks_rsts_manager
- generic
- (nb_of_reg : integer := 68);
- port
- (clk_sys_i : in std_logic;
- acam_refclk_p_i : in std_logic;
- acam_refclk_n_i : in std_logic;
- tdc_125m_clk_p_i : in std_logic;
- tdc_125m_clk_n_i : in std_logic;
- rst_n_i : in std_logic;
- pll_status_i : in std_logic;
- pll_sdo_i : in std_logic;
- send_dac_word_p_i : in std_logic;
- dac_word_i : in std_logic_vector(23 downto 0);
- wrabbit_dac_wr_p_i : in std_logic;
- wrabbit_dac_value_i : in std_logic_vector(23 downto 0);
- ----------------------------------------------------------------------
- tdc_125m_clk_o : out std_logic;
- internal_rst_o : out std_logic;
- acam_refclk_r_edge_p_o : out std_logic;
- pll_cs_n_o : out std_logic;
- pll_dac_sync_n_o : out std_logic;
- pll_sdi_o : out std_logic;
- pll_sclk_o : out std_logic;
- pll_status_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component carrier_info
- port
- (rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- wb_adr_i : in std_logic_vector(1 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_dat_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_stall_o : out std_logic;
- carrier_info_carrier_pcb_rev_i : in std_logic_vector(3 downto 0);
- carrier_info_carrier_reserved_i : in std_logic_vector(11 downto 0);
- carrier_info_carrier_type_i : in std_logic_vector(15 downto 0);
- carrier_info_stat_fmc_pres_i : in std_logic;
- carrier_info_stat_p2l_pll_lck_i : in std_logic;
- carrier_info_stat_sys_pll_lck_i : in std_logic;
- carrier_info_stat_ddr3_cal_done_i : in std_logic;
- carrier_info_stat_reserved_i : in std_logic_vector(27 downto 0);
- carrier_info_ctrl_led_green_o : out std_logic;
- carrier_info_ctrl_led_red_o : out std_logic;
- carrier_info_ctrl_dac_clr_n_o : out std_logic;
- carrier_info_ctrl_reserved_o : out std_logic_vector(28 downto 0);
- carrier_info_rst_fmc0_n_o : out std_logic;
- carrier_info_rst_fmc0_n_i : in std_logic;
- carrier_info_rst_fmc0_n_load_o : out std_logic;
- carrier_info_rst_reserved_o : out std_logic_vector(30 downto 0));
- end component carrier_info;
-
-
----------------------------------------------------------------------------------------------------
- component leds_manager is
- generic
- (g_width : integer := 32;
- values_for_simul : boolean := FALSE);
- port
- (clk_i : in std_logic;
- rst_i : in std_logic;
- utc_p_i : in std_logic;
- acam_inputs_en_i : in std_logic_vector(g_width-1 downto 0);
- acam_channel_i : in std_logic_vector(5 downto 0);
- tstamp_wr_p_i : in std_logic;
- ----------------------------------------------------------------------
- tdc_led_status_o : out std_logic;
- tdc_led_trig1_o : out std_logic;
- tdc_led_trig2_o : out std_logic;
- tdc_led_trig3_o : out std_logic;
- tdc_led_trig4_o : out std_logic;
- tdc_led_trig5_o : out std_logic);
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component acam_databus_interface
- port
- (ef1_i : in std_logic;
- ef2_i : in std_logic;
- data_bus_io : inout std_logic_vector(27 downto 0);
- clk_i : in std_logic;
- rst_i : in std_logic;
- adr_i : in std_logic_vector(7 downto 0);
- cyc_i : in std_logic;
- dat_i : in std_logic_vector(31 downto 0);
- stb_i : in std_logic;
- we_i : in std_logic;
- ----------------------------------------------------------------------
- adr_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic;
- oe_n_o : out std_logic;
- rd_n_o : out std_logic;
- wr_n_o : out std_logic;
- ack_o : out std_logic;
- ef1_o : out std_logic;
- ef1_meta_o : out std_logic;
- ef2_o : out std_logic;
- ef2_meta_o : out std_logic;
- dat_o : out std_logic_vector(31 downto 0));
- ----------------------------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component circular_buffer
- port
- (clk_i : in std_logic;
- tstamp_wr_rst_i : in std_logic;
- tstamp_wr_stb_i : in std_logic;
- tstamp_wr_cyc_i : in std_logic;
- tstamp_wr_we_i : in std_logic;
- tstamp_wr_adr_i : in std_logic_vector(7 downto 0);
- tstamp_wr_dat_i : in std_logic_vector(127 downto 0);
- tdc_mem_wb_rst_i : in std_logic;
- tdc_mem_wb_stb_i : in std_logic;
- tdc_mem_wb_cyc_i : in std_logic;
- tdc_mem_wb_we_i : in std_logic;
- tdc_mem_wb_adr_i : in std_logic_vector(31 downto 0);
- tdc_mem_wb_dat_i : in std_logic_vector(31 downto 0);
- --------------------------------------------------
- tstamp_wr_ack_p_o : out std_logic;
- tstamp_wr_dat_o : out std_logic_vector(127 downto 0);
- tdc_mem_wb_ack_o : out std_logic;
- tdc_mem_wb_dat_o : out std_logic_vector(31 downto 0);
- tdc_mem_wb_stall_o : out std_logic);
- --------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component blk_mem_circ_buff_v6_4
- port
- (clka : in std_logic;
- addra : in std_logic_vector(7 downto 0);
- dina : in std_logic_vector(127 downto 0);
- ena : in std_logic;
- wea : in std_logic_vector(0 downto 0);
- clkb : in std_logic;
- addrb : in std_logic_vector(9 downto 0);
- dinb : in std_logic_vector(31 downto 0);
- enb : in std_logic;
- web : in std_logic_vector(0 downto 0);
- --------------------------------------------------
- douta : out std_logic_vector(127 downto 0);
- doutb : out std_logic_vector(31 downto 0));
- --------------------------------------------------
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component spec_reset_gen is
- port
- (clk_sys_i : in std_logic;
- rst_pcie_n_a_i : in std_logic;
- rst_button_n_a_i : in std_logic;
- rst_n_o : out std_logic);
- end component;
-
-
----------------------------------------------------------------------------------------------------
- component dma_eic
- port
- (rst_n_i : in std_logic;
- clk_sys_i : in std_logic;
- wb_adr_i : in std_logic_vector(1 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_dat_o : out std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- wb_ack_o : out std_logic;
- wb_stall_o : out std_logic;
- wb_int_o : out std_logic;
- irq_dma_done_i : in std_logic;
- irq_dma_error_i : in std_logic);
- end component dma_eic;
-
-
----------------------------------------------------------------------------------------------------
- component irq_controller
- port
- (clk_i : in std_logic;
- rst_n_i : in std_logic;
- irq_src_p_i : in std_logic_vector(31 downto 0);
- wb_adr_i : in std_logic_vector(1 downto 0);
- wb_dat_i : in std_logic_vector(31 downto 0);
- wb_cyc_i : in std_logic;
- wb_sel_i : in std_logic_vector(3 downto 0);
- wb_stb_i : in std_logic;
- wb_we_i : in std_logic;
- ----------------------------------------------------------------------
- wb_dat_o : out std_logic_vector(31 downto 0);
- wb_ack_o : out std_logic;
- irq_p_o : out std_logic);
- end component irq_controller;
-
-
-end tdc_core_pkg;
---=================================================================================================
--- package body
---=================================================================================================
-package body tdc_core_pkg is
-
-end tdc_core_pkg;
---=================================================================================================
--- package end
---=================================================================================================
----------------------------------------------------------------------------------------------------
--- E N D O F F I L E
----------------------------------------------------------------------------------------------------
-
diff --git a/hdl/top/spec/wr_spec_tdc.ucf b/hdl/top/spec/wr_spec_tdc.ucf
index 2a0ccd6..5320a18 100644
--- a/hdl/top/spec/wr_spec_tdc.ucf
+++ b/hdl/top/spec/wr_spec_tdc.ucf
@@ -35,15 +35,139 @@ NET "tdc_clk_125m_n_i" IOSTANDARD = "LVDS_25";
NET "tdc_clk_125m_n_i" TNM_NET = "tdc_clk_125m_n_i";
TIMESPEC TS_tdc_clk_125m_n_i = PERIOD "tdc_clk_125m_n_i" 8 ns HIGH 50%;
-NET "p2l_clk_n_i" LOC = M19;
-NET "p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
-NET "p2l_clk_p_i" LOC = M20;
-NET "p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
-
-NET "p2l_clk_p_i" TNM_NET = "p2l_clk_p_i";
-TIMESPEC TS_p2l_clk_p_i = PERIOD "p2l_clk_p_i" 5 ns HIGH 50%;
-NET "p2l_clk_n_i" TNM_NET = "p2l_clk_n_i";
-TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
+#####################################################################
+### Gennum ports
+#####################################################################
+NET "L_RST_N" LOC = N20;
+NET "L_RST_N" IOSTANDARD = "LVCMOS18";
+
+NET "GPIO[1]" LOC = U16;
+NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
+NET "GPIO[0]" LOC = AB19;
+NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
+
+NET "P2L_RDY" LOC = J16;
+NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
+
+NET "P2L_CLKN" LOC = M19;
+NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
+NET "P2L_CLKP" LOC = M20;
+NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
+NET "P2L_DATA[0]" LOC = K20;
+NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[1]" LOC = H22;
+NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[2]" LOC = H21;
+NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[3]" LOC = L17;
+NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[4]" LOC = K17;
+NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[5]" LOC = G22;
+NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[6]" LOC = G20;
+NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[7]" LOC = K18;
+NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[8]" LOC = K19;
+NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[9]" LOC = H20;
+NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[10]" LOC = J19;
+NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[11]" LOC = E22;
+NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[12]" LOC = E20;
+NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[13]" LOC = F22;
+NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[14]" LOC = F21;
+NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
+NET "P2L_DATA[15]" LOC = H19;
+NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
+
+
+NET "P2L_DFRAME" LOC = J22;
+NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
+
+NET "P2L_VALID" LOC = L19;
+NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
+
+NET "P_WR_REQ[0]" LOC = M22;
+NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
+NET "P_WR_REQ[1]" LOC = M21;
+NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
+
+NET "P_WR_RDY[0]" LOC = L15;
+NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "P_WR_RDY[1]" LOC = K16;
+NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
+
+NET "RX_ERROR" LOC = J17;
+NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
+
+
+
+NET "L2P_DATA[0]" LOC = P16;
+NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[1]" LOC = P21;
+NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[2]" LOC = P18;
+NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[3]" LOC = T20;
+NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[4]" LOC = V21;
+NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[5]" LOC = V19;
+NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[6]" LOC = W22;
+NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[7]" LOC = Y22;
+NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[8]" LOC = P22;
+NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[9]" LOC = R22;
+NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[10]" LOC = T21;
+NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[11]" LOC = T19;
+NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[12]" LOC = V22;
+NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[13]" LOC = V20;
+NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[14]" LOC = W20;
+NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DATA[15]" LOC = Y21;
+NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
+NET "L2P_DFRAME" LOC = U22;
+NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
+NET "L2P_VALID" LOC = T18;
+NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
+NET "L2P_CLKN" LOC = K22;
+NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
+NET "L2P_CLKP" LOC = K21;
+NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
+NET "L2P_EDB" LOC = U20;
+NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
+
+
+NET "L2P_RDY" LOC = U19;
+NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
+NET "L_WR_RDY[0]" LOC = R20;
+NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "L_WR_RDY[1]" LOC = T22;
+NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
+NET "P_RD_D_RDY[0]" LOC = N16;
+NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "P_RD_D_RDY[1]" LOC = P19;
+NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
+NET "TX_ERROR" LOC = M17;
+NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
+NET "VC_RDY[0]" LOC = B21;
+NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "VC_RDY[1]" LOC = B22;
+NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# FMC slot
@@ -192,125 +316,6 @@ NET "mezz_sys_sda_b" IOSTANDARD = "LVCMOS25";
NET "carrier_onewire_b" LOC = D4;
NET "carrier_onewire_b" IOSTANDARD = "LVCMOS25";
-#----------------------------------------
-# GN4124 interface
-#----------------------------------------
-NET "rst_n_a_i" LOC = N20;
-NET "rst_n_a_i" IOSTANDARD = "LVCMOS18";
-NET "l2p_clk_n_o" LOC = K22;
-NET "l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
-NET "l2p_clk_p_o" LOC = K21;
-NET "l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
-NET "l2p_dframe_o" LOC = U22;
-NET "l2p_dframe_o" IOSTANDARD = "SSTL18_I";
-NET "l2p_edb_o" LOC = U20;
-NET "l2p_edb_o" IOSTANDARD = "SSTL18_I";
-NET "l2p_rdy_i" LOC = U19;
-NET "l2p_rdy_i" IOSTANDARD = "SSTL18_I";
-NET "l2p_valid_o" LOC = T18;
-NET "l2p_valid_o" IOSTANDARD = "SSTL18_I";
-NET "l_wr_rdy_i[0]" LOC = R20;
-NET "l_wr_rdy_i[0]" IOSTANDARD = "SSTL18_I";
-NET "l_wr_rdy_i[1]" LOC = T22;
-NET "l_wr_rdy_i[1]" IOSTANDARD = "SSTL18_I";
-#NET "L_CLKN" LOC = N19;
-#NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
-#NET "L_CLKP" LOC = P20;
-#NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
-NET "p2l_dframe_i" LOC = J22;
-NET "p2l_dframe_i" IOSTANDARD = "SSTL18_I";
-NET "p2l_rdy_o" LOC = J16;
-NET "p2l_rdy_o" IOSTANDARD = "SSTL18_I";
-NET "p2l_valid_i" LOC = L19;
-NET "p2l_valid_i" IOSTANDARD = "SSTL18_I";
-NET "p_rd_d_rdy_i[0]" LOC = N16;
-NET "p_rd_d_rdy_i[0]" IOSTANDARD = "SSTL18_I";
-NET "p_rd_d_rdy_i[1]" LOC = P19;
-NET "p_rd_d_rdy_i[1]" IOSTANDARD = "SSTL18_I";
-NET "p_wr_rdy_o[0]" LOC = L15;
-NET "p_wr_rdy_o[0]" IOSTANDARD = "SSTL18_I";
-NET "p_wr_rdy_o[1]" LOC = K16;
-NET "p_wr_rdy_o[1]" IOSTANDARD = "SSTL18_I";
-NET "p_wr_req_i[0]" LOC = M22;
-NET "p_wr_req_i[0]" IOSTANDARD = "SSTL18_I";
-NET "p_wr_req_i[1]" LOC = M21;
-NET "p_wr_req_i[1]" IOSTANDARD = "SSTL18_I";
-NET "rx_error_o" LOC = J17;
-NET "rx_error_o" IOSTANDARD = "SSTL18_I";
-NET "tx_error_i" LOC = M17;
-NET "tx_error_i" IOSTANDARD = "SSTL18_I";
-NET "vc_rdy_i[0]" LOC = B21;
-NET "vc_rdy_i[0]" IOSTANDARD = "SSTL18_I";
-NET "vc_rdy_i[1]" LOC = B22;
-NET "vc_rdy_i[1]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[0]" LOC = P16;
-NET "l2p_data_o[0]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[1]" LOC = P21;
-NET "l2p_data_o[1]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[2]" LOC = P18;
-NET "l2p_data_o[2]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[3]" LOC = T20;
-NET "l2p_data_o[3]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[4]" LOC = V21;
-NET "l2p_data_o[4]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[5]" LOC = V19;
-NET "l2p_data_o[5]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[6]" LOC = W22;
-NET "l2p_data_o[6]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[7]" LOC = Y22;
-NET "l2p_data_o[7]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[8]" LOC = P22;
-NET "l2p_data_o[8]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[9]" LOC = R22;
-NET "l2p_data_o[9]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[10]" LOC = T21;
-NET "l2p_data_o[10]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[11]" LOC = T19;
-NET "l2p_data_o[11]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[12]" LOC = V22;
-NET "l2p_data_o[12]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[13]" LOC = V20;
-NET "l2p_data_o[13]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[14]" LOC = W20;
-NET "l2p_data_o[14]" IOSTANDARD = "SSTL18_I";
-NET "l2p_data_o[15]" LOC = Y21;
-NET "l2p_data_o[15]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[0]" LOC = K20;
-NET "p2l_data_i[0]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[1]" LOC = H22;
-NET "p2l_data_i[1]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[2]" LOC = H21;
-NET "p2l_data_i[2]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[3]" LOC = L17;
-NET "p2l_data_i[3]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[4]" LOC = K17;
-NET "p2l_data_i[4]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[5]" LOC = G22;
-NET "p2l_data_i[5]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[6]" LOC = G20;
-NET "p2l_data_i[6]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[7]" LOC = K18;
-NET "p2l_data_i[7]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[8]" LOC = K19;
-NET "p2l_data_i[8]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[9]" LOC = H20;
-NET "p2l_data_i[9]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[10]" LOC = J19;
-NET "p2l_data_i[10]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[11]" LOC = E22;
-NET "p2l_data_i[11]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[12]" LOC = E20;
-NET "p2l_data_i[12]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[13]" LOC = F22;
-NET "p2l_data_i[13]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[14]" LOC = F21;
-NET "p2l_data_i[14]" IOSTANDARD = "SSTL18_I";
-NET "p2l_data_i[15]" LOC = H19;
-NET "p2l_data_i[15]" IOSTANDARD = "SSTL18_I";
-
-NET "irq_p_o" LOC = U16;
-NET "irq_p_o" IOSTANDARD = "LVCMOS25";
-
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
@@ -326,7 +331,6 @@ NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC Presence
#----------------------------------------
-
NET "prsnt_m2c_n_i" LOC = AB14;
NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
@@ -394,14 +398,12 @@ NET "uart_txd_o" IOSTANDARD=LVCMOS25;
#----------------------------------------
# False Path
#----------------------------------------
-
# GN4124
-NET "rst_n_a_i" TIG;
+NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
-PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk_62m5_sys" TNM_NET = clk_62m5_sys;
TIMESPEC ts_ignore_crossclock = FROM "clk_62m5_sys" TO "tdc_clk_125m_p_i" 10ns DATAPATHONLY;
@@ -412,9 +414,6 @@ TIMESPEC ts_ignore_xclock2 = FROM "clk_125m_pllref_p_i" TO "clk_62m5_sys" 10ns D
TIMESPEC ts_x3 = FROM "clk_62m5_sys" TO "U_GTP_ch1_rx_divclk" 10ns DATAPATHONLY;
TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
-PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
-NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
-TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 125 MHz HIGH 50%;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
@@ -424,3 +423,8 @@ TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO "FFS" 2 ns DATAPATHONLY;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/05/19
+NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>;
+TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
+NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
+TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
diff --git a/hdl/top/spec/wr_spec_tdc.vhd b/hdl/top/spec/wr_spec_tdc.vhd
index 2c44b79..614ac7e 100644
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -40,9 +40,6 @@
-- the FPGA startup, using the 62.5MHz clock. The clks_rsts_manager is keeping the |
-- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
--- For the TDC mezzanine core, the crossing from the 125 MHz world to the 62.5 MHz |
--- world takes place through the dedicated clock_crossing module. |
--- |
-- ___________________________________________________________________________ |
-- | | |
-- | ____________________________ ___ _____ | |
@@ -50,14 +47,14 @@
-- |------|------| WRabbit core, PHY, DAC | <----------> | | | | | |
-- \/ | |____________________________| | | | | | |
-- ________ | 62.5MHz | | | | | |
--- | | | ___________________ | | | | | |
--- | DAC |<->| | clks rsts manager | | | | G | | |
--- | PLL | |___________________| | | | | | |
--- | | | ____________________________ _______ | S | | N | | |
--- | | | | | | clk | | | | | | |
--- | ACAM |<->| | TDC mezzanine |-| cross |<--> | | | 4 | | |
--- |________| | |--|____________________________| |_______| | D | | | | |
--- TDC mezz | | 125MHz 62.5MHz | | | 1 | | |
+-- | | | | | | | | |
+-- | DAC |<->| | | | G | | |
+-- | PLL | | | | | | |
+-- | | | ____________________________ | S | | N | | |
+-- | | | | | | | | | | |
+-- | ACAM |<->|------| TDC wrapper |<------------> | | | 4 | | |
+-- |________| | |--|____________________________| | D | | | | |
+-- TDC mezz | | 62.5MHz | | | 1 | | |
-- | | ____________________________ | | | | | |
-- | |->| | | B | | 2 | | |
-- | | Vector Interrupt Controller| <----------> | | <--> | | | |
@@ -140,140 +137,149 @@ use UNISIM.vcomponents.all;
--=================================================================================================
entity wr_spec_tdc is
generic
- (g_span : integer := 32; -- address span in bus interfaces
- g_width : integer := 32; -- data width in bus interfaces
- values_for_simul : boolean := FALSE); -- this generic is set to TRUE
- -- when instantiated in a test-bench
+ (g_with_wr_phy : boolean := true;
+ g_simulation : boolean := false); -- this generic is set to TRUE
+ -- when instantiated in a test-bench
port
- (-- SPEC carrier
- clk_125m_pllref_p_i: in std_logic; -- 125 MHz PLL reference
- clk_125m_pllref_n_i: in std_logic;
-
- clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
- clk_125m_gtp_p_i : in std_logic;
-
- clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
-
- dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
- dac_din_o : out std_logic;
- dac_cs1_n_o : out std_logic;
- dac_cs2_n_o : out std_logic;
-
- sfp_txp_o : out std_logic; -- SFP
- sfp_txn_o : out std_logic;
- sfp_rxp_i : in std_logic := '0';
- sfp_rxn_i : in std_logic := '1';
- sfp_mod_def0_b : in std_logic; -- SFP detect pin
- sfp_mod_def1_b : inout std_logic; -- SFP scl
- sfp_mod_def2_b : inout std_logic; -- SFP sda
- sfp_rate_select_b : inout std_logic := '0';
- sfp_tx_fault_i : in std_logic := '0';
- sfp_tx_disable_o : out std_logic;
- sfp_los_i : in std_logic := '0';
-
- uart_rxd_i : in std_logic := '1'; -- UART
- uart_txd_o : out std_logic;
-
- carrier_scl_b : inout std_logic; -- SPEC EEPROM
- carrier_sda_b : inout std_logic;
-
- carrier_onewire_b : inout std_logic; -- SPEC 1-wire
-
- button1_i : in std_logic := '1';
- button2_i : in std_logic := '1';
-
- -- Interface with GN4124
- rst_n_a_i : in std_logic;
- -- P2L Direction
- p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
- p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
- p2l_data_i : in std_logic_vector(15 downto 0);-- Parallel receive data
- p2l_dframe_i : in std_logic; -- Receive Frame
- p2l_valid_i : in std_logic; -- Receive Data Valid
- p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
- p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
- p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
- rx_error_o : out std_logic; -- Receive Error
- vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
- -- L2P Direction
- l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
- l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
- l2p_data_o : out std_logic_vector(15 downto 0);-- Parallel transmit data
- l2p_dframe_o : out std_logic; -- Transmit Data Frame
- l2p_valid_o : out std_logic; -- Transmit Data Valid
- l2p_edb_o : out std_logic; -- Packet termination and discard
- l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
- l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
- p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
- tx_error_i : in std_logic; -- Transmit Error
- irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 8
- irq_aux_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO 9, aux signal
-
- -- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
- pll_sclk_o : out std_logic; -- SPI clock
- pll_sdi_o : out std_logic; -- data line for PLL and DAC
- pll_cs_o : out std_logic; -- PLL chip select
- pll_dac_sync_o : out std_logic; -- DAC chip select
- pll_sdo_i : in std_logic; -- not used for the moment
- pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
- tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
- tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
- acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
- acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
-
- -- Timing interface with the ACAM on TDC mezzanine
- start_from_fpga_o : out std_logic; -- start signal
- err_flag_i : in std_logic; -- error flag
- int_flag_i : in std_logic; -- interrupt flag
- start_dis_o : out std_logic; -- start disable, not used
- stop_dis_o : out std_logic; -- stop disable, not used
- -- Data interface with the ACAM on TDC mezzanine
- data_bus_io : inout std_logic_vector(27 downto 0);
- address_o : out std_logic_vector(3 downto 0);
- cs_n_o : out std_logic; -- chip select for ACAM
- oe_n_o : out std_logic; -- output enable for ACAM
- rd_n_o : out std_logic; -- read signal for ACAM
- wr_n_o : out std_logic; -- write signal for ACAM
- ef1_i : in std_logic; -- empty flag iFIFO1
- ef2_i : in std_logic; -- empty flag iFIFO2
-
- -- Enable of input Logic on TDC mezzanine
- enable_inputs_o : out std_logic; -- enables all 5 inputs
- term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
- term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
- term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
- term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
- term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
-
- -- LEDs on TDC mezzanine
- tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
- tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
- tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
- tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
- tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
- tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
-
- -- Input Logic on TDC mezzanine (not used currently)
- tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
- tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
- tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
- tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
- tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
-
- -- I2C EEPROM interface on TDC mezzanine
- mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
- mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
-
- -- 1-wire interface on TDC mezzanine
- mezz_onewire_b : inout std_logic;
-
- -- font panel leds
- led_red : out std_logic;
- led_green : out std_logic;
-
- -- Carrier other signals
- pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
- prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
+ ( -- SPEC carrier
+ clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
+ clk_125m_pllref_n_i : in std_logic;
+
+ clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTP reference
+ clk_125m_gtp_p_i : in std_logic;
+
+ clk_20m_vcxo_i : in std_logic; -- 20 MHz VCXO
+
+ dac_sclk_o : out std_logic; -- PLL VCXO DAC Drive
+ dac_din_o : out std_logic;
+ dac_cs1_n_o : out std_logic;
+ dac_cs2_n_o : out std_logic;
+
+ sfp_txp_o : out std_logic; -- SFP
+ sfp_txn_o : out std_logic;
+ sfp_rxp_i : in std_logic := '0';
+ sfp_rxn_i : in std_logic := '1';
+ sfp_mod_def0_b : in std_logic; -- SFP detect pin
+ sfp_mod_def1_b : inout std_logic; -- SFP scl
+ sfp_mod_def2_b : inout std_logic; -- SFP sda
+ sfp_rate_select_b : inout std_logic := '0';
+ sfp_tx_fault_i : in std_logic := '0';
+ sfp_tx_disable_o : out std_logic;
+ sfp_los_i : in std_logic := '0';
+
+ uart_rxd_i : in std_logic := '1'; -- UART
+ uart_txd_o : out std_logic;
+
+ carrier_scl_b : inout std_logic; -- SPEC EEPROM
+ carrier_sda_b : inout std_logic;
+
+ carrier_onewire_b : inout std_logic; -- SPEC 1-wire
+
+ button1_i : in std_logic := '1';
+ button2_i : in std_logic := '1';
+
+ ------------------------------------------------------------------------
+ -- GN4124 PCI bridge pins
+ ------------------------------------------------------------------------
+
+ l_rst_n : in std_logic; -- reset from gn4124 (rstout18_n)
+
+ -- general purpose interface
+ gpio : inout std_logic_vector(1 downto 0); -- gpio[0] -> gn4124 gpio8
+ -- gpio[1] -> gn4124 gpio9
+ -- pcie to local [inbound data] - rx
+ p2l_rdy : out std_logic; -- rx buffer full flag
+ p2l_clkn : in std_logic; -- receiver source synchronous clock-
+ p2l_clkp : in std_logic; -- receiver source synchronous clock+
+ p2l_data : in std_logic_vector(15 downto 0); -- parallel receive data
+ p2l_dframe : in std_logic; -- receive frame
+ p2l_valid : in std_logic; -- receive data valid
+
+ -- inbound buffer request/status
+ p_wr_req : in std_logic_vector(1 downto 0); -- pcie write request
+ p_wr_rdy : out std_logic_vector(1 downto 0); -- pcie write ready
+ rx_error : out std_logic; -- receive error
+
+ -- local to parallel [outbound data] - tx
+ l2p_data : out std_logic_vector(15 downto 0); -- parallel transmit data
+ l2p_dframe : out std_logic; -- transmit data frame
+ l2p_valid : out std_logic; -- transmit data valid
+ l2p_clkn : out std_logic; -- transmitter source synchronous clock-
+ l2p_clkp : out std_logic; -- transmitter source synchronous clock+
+ l2p_edb : out std_logic; -- packet termination and discard
+
+ -- outbound buffer status
+ l2p_rdy : in std_logic; -- tx buffer full flag
+ l_wr_rdy : in std_logic_vector(1 downto 0); -- local-to-pcie write
+ p_rd_d_rdy : in std_logic_vector(1 downto 0); -- pcie-to-local read response data ready
+ tx_error : in std_logic; -- transmit error
+ vc_rdy : in std_logic_vector(1 downto 0); -- channel ready
+
+ -- Interface with the PLL AD9516 and DAC AD5662 on TDC mezzanine
+ pll_sclk_o : out std_logic; -- SPI clock
+ pll_sdi_o : out std_logic; -- data line for PLL and DAC
+ pll_cs_o : out std_logic; -- PLL chip select
+ pll_dac_sync_o : out std_logic; -- DAC chip select
+ pll_sdo_i : in std_logic; -- not used for the moment
+ pll_status_i : in std_logic; -- PLL Digital Lock Detect, active high
+ tdc_clk_125m_p_i : in std_logic; -- 125 MHz differential clock: system clock
+ tdc_clk_125m_n_i : in std_logic; -- 125 MHz differential clock: system clock
+ acam_refclk_p_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
+ acam_refclk_n_i : in std_logic; -- 31.25 MHz differential clock: ACAM ref clock
+
+ -- Timing interface with the ACAM on TDC mezzanine
+ start_from_fpga_o : out std_logic; -- start signal
+ err_flag_i : in std_logic; -- error flag
+ int_flag_i : in std_logic; -- interrupt flag
+ start_dis_o : out std_logic; -- start disable, not used
+ stop_dis_o : out std_logic; -- stop disable, not used
+ -- Data interface with the ACAM on TDC mezzanine
+ data_bus_io : inout std_logic_vector(27 downto 0);
+ address_o : out std_logic_vector(3 downto 0);
+ cs_n_o : out std_logic; -- chip select for ACAM
+ oe_n_o : out std_logic; -- output enable for ACAM
+ rd_n_o : out std_logic; -- read signal for ACAM
+ wr_n_o : out std_logic; -- write signal for ACAM
+ ef1_i : in std_logic; -- empty flag iFIFO1
+ ef2_i : in std_logic; -- empty flag iFIFO2
+
+ -- Enable of input Logic on TDC mezzanine
+ enable_inputs_o : out std_logic; -- enables all 5 inputs
+ term_en_1_o : out std_logic; -- Ch.1 termination enable of 50 Ohm termination
+ term_en_2_o : out std_logic; -- Ch.2 termination enable of 50 Ohm termination
+ term_en_3_o : out std_logic; -- Ch.3 termination enable of 50 Ohm termination
+ term_en_4_o : out std_logic; -- Ch.4 termination enable of 50 Ohm termination
+ term_en_5_o : out std_logic; -- Ch.5 termination enable of 50 Ohm termination
+
+ -- LEDs on TDC mezzanine
+ tdc_led_status_o : out std_logic; -- amber led on front pannel, division of 125 MHz tdc_clk
+ tdc_led_trig1_o : out std_logic; -- amber led on front pannel, Ch.1 enable
+ tdc_led_trig2_o : out std_logic; -- amber led on front pannel, Ch.2 enable
+ tdc_led_trig3_o : out std_logic; -- amber led on front pannel, Ch.3 enable
+ tdc_led_trig4_o : out std_logic; -- amber led on front pannel, Ch.4 enable
+ tdc_led_trig5_o : out std_logic; -- amber led on front pannel, Ch.5 enable
+
+ -- Input Logic on TDC mezzanine (not used currently)
+ tdc_in_fpga_1_i : in std_logic; -- Ch.1 for ACAM, also received by FPGA
+ tdc_in_fpga_2_i : in std_logic; -- Ch.2 for ACAM, also received by FPGA
+ tdc_in_fpga_3_i : in std_logic; -- Ch.3 for ACAM, also received by FPGA
+ tdc_in_fpga_4_i : in std_logic; -- Ch.4 for ACAM, also received by FPGA
+ tdc_in_fpga_5_i : in std_logic; -- Ch.5 for ACAM, also received by FPGA
+
+ -- I2C EEPROM interface on TDC mezzanine
+ mezz_sys_scl_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C clock
+ mezz_sys_sda_b : inout std_logic := '1'; -- Mezzanine system EEPROM I2C data
+
+ -- 1-wire interface on TDC mezzanine
+ mezz_onewire_b : inout std_logic;
+
+ -- font panel leds
+ led_red : out std_logic;
+ led_green : out std_logic;
+
+ -- Carrier other signals
+ pcb_ver_i : in std_logic_vector(3 downto 0); -- PCB version
+ prsnt_m2c_n_i : in std_logic); -- Mezzanine presence (active low)
end wr_spec_tdc;
@@ -282,132 +288,130 @@ end wr_spec_tdc;
--=================================================================================================
architecture rtl of wr_spec_tdc is
+
+ function f_bool2int (x : boolean) return integer is
+ begin
+ if(x) then
+ return 1;
+ else
+ return 0;
+ end if;
+ end f_bool2int;
+
+
---------------------------------------------------------------------------------------------------
-- SDB CONSTANTS --
---------------------------------------------------------------------------------------------------
- -- Note: All address in sdb and crossbar are BYTE addresses!
+
+ constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
+ (abi_class => x"0000", -- undocumented device
+ abi_ver_major => x"01",
+ abi_ver_minor => x"01",
+ wbd_endian => c_sdb_endian_big,
+ wbd_width => x"4", -- 32-bit port granularity
+ sdb_component =>
+ (addr_first => x"0000000000000000",
+ addr_last => x"000000000000001F",
+ product =>
+ (vendor_id => x"000000000000CE42", -- CERN
+ device_id => x"00000603", -- "WB-SPEC.CSR " | md5sum | cut -c1-8
+ version => x"00000001",
+ date => x"20121116",
+ name => "WB-SPEC.CSR ")));
+
+-- Note: All address in sdb and crossbar are BYTE addresses!
-- Master ports on the wishbone crossbar
- constant c_NUM_WB_MASTERS : integer := 4;
- constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
- constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
- constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
- constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
+ constant c_NUM_WB_MASTERS : integer := 4;
+ constant c_WB_SLAVE_SPEC_INFO : integer := 0; -- Info on SPEC control and status registers
+ constant c_WB_SLAVE_VIC : integer := 1; -- Interrupt controller
+ constant c_WB_SLAVE_TDC : integer := 2; -- TDC core configuration
+ constant c_SLAVE_WRCORE : integer := 3; -- White Rabbit PTP core
-- SDB header address
- constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
+ constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Slave port on the wishbone crossbar
- constant c_NUM_WB_SLAVES : integer := 1;
- constant c_MASTER_GENNUM : integer := 0;
-
- constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0001FFFF", x"00000000");
- constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+ constant c_NUM_WB_SLAVES : integer := 1;
+ constant c_MASTER_GENNUM : integer := 0;
- constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
- (0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
- 1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
- 2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
- 3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
- 4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
- 5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
+ constant c_FMC_TDC_SDB_BRIDGE : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0000FFFF", x"00000000");
+ constant c_WRCORE_BRIDGE_SDB : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
+ constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) :=
+ (0 => f_sdb_embed_device (c_SPEC_INFO_SDB_DEVICE, x"00020000"),
+ 1 => f_sdb_embed_device (c_xwb_vic_sdb, x"00030000"), -- c_xwb_vic_sdb described in the wishbone_pkg
+ 2 => f_sdb_embed_bridge (c_FMC_TDC_SDB_BRIDGE, x"00040000"),
+ 3 => f_sdb_embed_bridge (c_WRCORE_BRIDGE_SDB, x"00080000"),
+ 4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
+ 5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
+
---------------------------------------------------------------------------------------------------
-- VIC CONSTANT --
---------------------------------------------------------------------------------------------------
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 0) :=
- (0 => x"00052000");
-
+ (0 => x"00043000");
---------------------------------------------------------------------------------------------------
-- Signals --
---------------------------------------------------------------------------------------------------
-- WRabbit clocks
- signal pllout_clk_sys, pllout_clk_dmtd : std_logic;
- signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd : std_logic;
- signal clk_125m_pllref, clk_125m_gtp : std_logic;
- signal clk_dmtd : std_logic;
- attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
- attribute buffer_type of clk_125m_pllref : signal is "BUFG";
+ signal pllout_clk_sys, pllout_clk_dmtd : std_logic;
+ signal pllout_clk_fb_pllref, pllout_clk_fb_dmtd : std_logic;
+ signal clk_125m_pllref, clk_125m_gtp : std_logic;
+ signal clk_dmtd : std_logic;
+ attribute buffer_type : string; --" {bufgdll | ibufg | bufgp | ibuf | bufr | none}";
+ attribute buffer_type of clk_125m_pllref : signal is "BUFG";
-- TDC core clocks and resets
- signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
- signal clk_62m5_sys, sys_locked : std_logic;
- signal clk_125m_mezz, pll_mezz_status : std_logic;
- signal rst_125m_mezz_n, rst_125m_mezz : std_logic;
- signal acam_refclk_r_edge_p : std_logic;
- signal rst_sys, rst_sys_n : std_logic;
+ signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
+ signal clk_62m5_sys, sys_locked : std_logic;
+ signal rst_n_sys : std_logic;
-- DAC configuration through PCIe/VME
- signal send_dac_word_p : std_logic;
- signal dac_word : std_logic_vector(23 downto 0);
-- WISHBONE from crossbar master port
- signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
- signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+ signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+ signal cnx_master_in : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
-- WISHBONE to crossbar slave port
- signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
- signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
- signal tdc_slave_in : t_wishbone_slave_in;
- signal tdc_slave_out : t_wishbone_slave_out;
- signal gn_wb_adr : std_logic_vector(31 downto 0);
+ signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+ signal cnx_slave_in : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+ signal gn_wb_adr : std_logic_vector(31 downto 0);
-- Carrier CSR info
- signal gn4124_status : std_logic_vector(31 downto 0);
+ signal gn4124_status : std_logic_vector(31 downto 0);
-- Carrier 1-wire
- signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
+ signal carrier_owr_en, carrier_owr_i : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
-- VIC
- signal fmc_eic_irq, irq_to_gn4124 : std_logic;
- signal fmc_eic_irq_synch : std_logic_vector (1 downto 0);
+ signal irq_to_gn4124 : std_logic;
-- WRabbit time
- signal tm_link_up, tm_time_valid, tm_dac_wr_p : std_logic;
- signal tm_utc : std_logic_vector(39 downto 0);
- signal tm_cycles : std_logic_vector(27 downto 0);
- signal tm_dac_value, tm_dac_value_reg : std_logic_vector(23 downto 0);
- signal tm_clk_aux_lock_en, tm_clk_aux_locked : std_logic;
+ signal tm_link_up, tm_time_valid, tm_dac_wr_p : std_logic;
+ signal tm_tai : std_logic_vector(39 downto 0);
+ signal tm_cycles : std_logic_vector(27 downto 0);
+ signal tm_dac_value, tm_dac_value_reg : std_logic_vector(23 downto 0);
+ signal tm_clk_aux_lock_en, tm_clk_aux_locked : std_logic;
-- WRabbit PHY
- signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
- signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
- signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
- signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
- signal phy_rx_bitslide : std_logic_vector(3 downto 0);
+ signal phy_tx_data, phy_rx_data : std_logic_vector(7 downto 0);
+ signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
+ signal phy_tx_enc_err, phy_rx_rbclk : std_logic;
+ signal phy_rx_enc_err, phy_rst, phy_loopen : std_logic;
+ signal phy_rx_bitslide : std_logic_vector(3 downto 0);
-- DAC configuration through WRabbit
- signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
- signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
+ signal dac_hpll_load_p1, dac_dpll_load_p1 : std_logic;
+ signal dac_hpll_data, dac_dpll_data : std_logic_vector(15 downto 0);
-- EEPROM on mezzanine
- signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in: std_logic;
- signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in: std_logic;
- signal tdc_scl_oen, tdc_sda_oen : std_logic;
+ signal wrc_scl_out, wrc_scl_in, wrc_sda_out, wrc_sda_in : std_logic;
+ signal tdc_scl_out, tdc_scl_in, tdc_sda_out, tdc_sda_in : std_logic;
+ signal tdc_scl_oen, tdc_sda_oen : std_logic;
-- SFP EEPROM on mezzanine
- signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in: std_logic;
+ signal sfp_scl_out, sfp_scl_in, sfp_sda_out, sfp_sda_in : std_logic;
-- Carrier 1-Wire
- signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
+ signal wrc_owr_en, wrc_owr_in : std_logic_vector(1 downto 0);
-- aux
- signal pll_sclk, pll_sdi, pll_dac_sync, pll_cs : std_logic;
----------------------------------------------------------------------------------------------------
--- Chipscope --
----------------------------------------------------------------------------------------------------
- -- -- Chipscope
- -- component chipscope_ila
- -- port (
- -- CONTROL : inout std_logic_vector(35 downto 0);
- -- CLK : in std_logic;
- -- TRIG0 : in std_logic_vector(31 downto 0);
- -- TRIG1 : in std_logic_vector(31 downto 0);
- -- TRIG2 : in std_logic_vector(31 downto 0);
- -- TRIG3 : in std_logic_vector(31 downto 0));
- -- end component;
-
- -- component chipscope_icon
- -- port (
- -- CONTROL0 : inout std_logic_vector (35 downto 0));
- -- end component;
-
- -- signal CONTROL : std_logic_vector(35 downto 0);
- -- signal CLK : std_logic;
- -- signal TRIG0 : std_logic_vector(31 downto 0);
- -- signal TRIG1 : std_logic_vector(31 downto 0);
- -- signal TRIG2 : std_logic_vector(31 downto 0);
- -- signal TRIG3 : std_logic_vector(31 downto 0);
+ signal tdc0_irq: std_logic;
+ signal tdc0_clk_125m : std_logic;
+ signal tdc0_soft_rst_n: std_logic;
+ signal powerup_rst_cnt : unsigned(7 downto 0) := "00000000";
+ signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
--=================================================================================================
-- architecture begin
@@ -418,30 +422,28 @@ begin
-- 62.5 MHz system clock --
---------------------------------------------------------------------------------------------------
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_vcxo_ibuf : IBUFG
- port map
+ port map
(O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_clk_vcxo_gbuf : BUFG
- port map
+ port map
(O => clk_20m_vcxo,
I => clk_20m_vcxo_buf);
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sys_clk_pll : PLL_BASE
- generic map
+ generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
+ CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 16, -- not used
+ CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
@@ -449,117 +451,42 @@ begin
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
- port map
- (CLKFBOUT => pllout_clk_fb_pllref,
- CLKOUT0 => pllout_clk_sys,
- CLKOUT1 => open,
- CLKOUT2 => open,
- CLKOUT3 => open,
- CLKOUT4 => open,
- CLKOUT5 => open,
- LOCKED => sys_locked,
- RST => '0',
- CLKFBIN => pllout_clk_fb_pllref,
- CLKIN => clk_20m_vcxo);
-
+ port map
+ (CLKFBOUT => pllout_clk_fb_pllref,
+ CLKOUT0 => pllout_clk_sys,
+ CLKOUT1 => open,
+ CLKOUT2 => open,
+ CLKOUT3 => open,
+ CLKOUT4 => open,
+ CLKOUT5 => open,
+ LOCKED => sys_locked,
+ RST => '0',
+ CLKFBIN => pllout_clk_fb_pllref,
+ CLKIN => clk_20m_vcxo);
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_sys_buf : BUFG
- port map
+ port map
(O => clk_62m5_sys,
- I => pllout_clk_sys);
-
-
----------------------------------------------------------------------------------------------------
--- Reset for 62.5 MHz clk domain --
----------------------------------------------------------------------------------------------------
-
- U_Reset_Generator : spec_reset_gen
- port map
- (clk_sys_i => clk_62m5_sys,
- rst_pcie_n_a_i => rst_n_a_i,
- rst_button_n_a_i => button1_i,
- rst_n_o => rst_sys_n);
- -- -- -- -- -- -- -- -- -- --
- rst_sys <= not rst_sys_n;
-
+ I => pllout_clk_sys);
----------------------------------------------------------------------------------------------------
--- 125 MHz clk and Reset for TDC core --
----------------------------------------------------------------------------------------------------
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- cmp_tdc_clks_rsts_mgment : clks_rsts_manager
- generic map
- (nb_of_reg => 68)
- port map
- (clk_sys_i => clk_62m5_sys,
- acam_refclk_p_i => acam_refclk_p_i,
- acam_refclk_n_i => acam_refclk_n_i,
- tdc_125m_clk_p_i => tdc_clk_125m_p_i,
- tdc_125m_clk_n_i => tdc_clk_125m_n_i,
- rst_n_i => rst_n_a_i,
- pll_sdo_i => pll_sdo_i,
- pll_status_i => pll_status_i,
- send_dac_word_p_i => send_dac_word_p,
- dac_word_i => dac_word,
- acam_refclk_r_edge_p_o => acam_refclk_r_edge_p,
- wrabbit_dac_value_i => tm_dac_value,
- wrabbit_dac_wr_p_i => tm_dac_wr_p,
- internal_rst_o => rst_125m_mezz,
- pll_cs_n_o => pll_cs,
- pll_dac_sync_n_o => pll_dac_sync,
- pll_sdi_o => pll_sdi,
- pll_sclk_o => pll_sclk,
- tdc_125m_clk_o => clk_125m_mezz,
- pll_status_o => pll_mezz_status);
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- rst_125m_mezz_n <= not rst_125m_mezz;
- pll_dac_sync_o <= pll_dac_sync;
- pll_sdi_o <= pll_sdi;
- pll_sclk_o <= pll_sclk;
- pll_cs_o <= pll_cs;
-
- -- chipscope_ila_1 : chipscope_ila
- -- port map (
- -- CONTROL => CONTROL,
- -- CLK => clk_62m5_sys,
- -- TRIG0 => TRIG0,
- -- TRIG1 => TRIG1,
- -- TRIG2 => TRIG2,
- -- TRIG3 => TRIG3);
-
- -- chipscope_icon_1 : chipscope_icon
- -- port map (
- -- CONTROL0 => CONTROL);
-
- -- TRIG0(23 downto 0) <= tm_dac_value;
- -- TRIG0(24) <= tm_dac_wr_p;
- -- TRIG0(25) <= pll_dac_sync;
- -- TRIG0(26) <= pll_sdi;
- -- TRIG0(27) <= pll_sclk;
- -- TRIG0(28) <= pll_sdo_i;
- -- TRIG0(29) <= pll_status_i;
- -- TRIG0(30) <= pll_cs;
- -- TRIG0(31) <= tm_clk_aux_lock_en;
-
---------------------------------------------------------------------------------------------------
-- 62.5 MHz DMTD clock --
---------------------------------------------------------------------------------------------------
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_dmtd_clk_pll : PLL_BASE
- generic map
+ generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
+ CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 16, -- not used
+ CLKOUT1_DIVIDE => 16, -- not used
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
@@ -567,50 +494,78 @@ begin
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
- port map
- (CLKFBOUT => pllout_clk_fb_dmtd,
- CLKOUT0 => pllout_clk_dmtd,
- CLKOUT1 => open,
- CLKOUT2 => open,
- CLKOUT3 => open,
- CLKOUT4 => open,
- CLKOUT5 => open,
- LOCKED => open,
- RST => '0',
- CLKFBIN => pllout_clk_fb_dmtd,
- CLKIN => clk_20m_vcxo_buf);
+ port map
+ (CLKFBOUT => pllout_clk_fb_dmtd,
+ CLKOUT0 => pllout_clk_dmtd,
+ CLKOUT1 => open,
+ CLKOUT2 => open,
+ CLKOUT3 => open,
+ CLKOUT4 => open,
+ CLKOUT5 => open,
+ LOCKED => open,
+ RST => '0',
+ CLKFBIN => pllout_clk_fb_dmtd,
+ CLKIN => clk_20m_vcxo_buf);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_dmtd_buf : BUFG
- port map
+ port map
(O => clk_dmtd,
I => pllout_clk_dmtd);
-
---------------------------------------------------------------------------------------------------
-- 125 MHz clk for White Rabbit core --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_PLL : IBUFGDS
- generic map
+ generic map
(DIFF_TERM => true,
- IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
- port map
- (O => clk_125m_pllref, -- Buffer output
+ IBUF_LOW_PWR => true) -- Low power (TRUE) vs. performance (FALSE) setting for referenced
+ port map
+ (O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
- IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
+ IB => clk_125m_pllref_n_i); -- Diff_n buffer input (connect directly to top-level port)
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_Buf_CLK_GTP : IBUFDS
- generic map
- (DIFF_TERM => true,
+ generic map
+ (DIFF_TERM => true,
IBUF_LOW_PWR => false)
- port map
+ port map
(O => clk_125m_gtp,
I => clk_125m_gtp_p_i,
IB => clk_125m_gtp_n_i);
+---------------------------------------------------------------------------------------------------
+-- 62.5 MHz Reset --
+---------------------------------------------------------------------------------------------------
+-- SPEC power-up reset in the clk_62m5_sys domain: rst_n_sys is asserted asynchronously upon VME
+-- reset or SVEC AFPGA power-on reset. If none of these signals is asserted at startup, the process
+-- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
+-- the reset.
+
+ p_powerup_reset : process(clk_62m5_sys,l_rst_n)
+ begin
+ if(l_rst_n = '0') then
+ rst_n_sys <= '0';
+ elsif rising_edge(clk_62m5_sys) then
+ if sys_locked = '1' then
+ if(powerup_rst_cnt = "11111111") then
+ rst_n_sys <= '1';
+ else
+ rst_n_sys <= '0';
+ powerup_rst_cnt <= powerup_rst_cnt + 1;
+ end if;
+ else
+ rst_n_sys <= '0';
+ powerup_rst_cnt <= "00000000";
+ end if;
+ end if;
+ end process;
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
---------------------------------------------------------------------------------------------------
-- White Rabbit Core + PHY --
@@ -618,86 +573,87 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
- generic map
- (g_simulation => 0,
+ generic map
+ (g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
g_aux_clks => 1,
g_ep_rxbuf_size => 1024,
- g_dpram_initf => "wrc.ram",
+ g_dpram_initf => "none",
g_dpram_size => 90112/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false)
- port map
- (clk_sys_i => clk_62m5_sys,
- clk_dmtd_i => clk_dmtd,
- clk_ref_i => clk_125m_pllref,
- clk_aux_i(0) => clk_125m_mezz,
- rst_n_i => rst_sys_n,
+ port map
+ (clk_sys_i => clk_62m5_sys,
+ clk_dmtd_i => clk_dmtd,
+ clk_ref_i => clk_125m_pllref,
+ clk_aux_i(0) => tdc0_clk_125m,
+ rst_n_i => rst_n_sys,
-- DAC
- dac_hpll_load_p1_o => dac_hpll_load_p1,
- dac_hpll_data_o => dac_hpll_data,
- dac_dpll_load_p1_o => dac_dpll_load_p1,
- dac_dpll_data_o => dac_dpll_data,
+ dac_hpll_load_p1_o => dac_hpll_load_p1,
+ dac_hpll_data_o => dac_hpll_data,
+ dac_dpll_load_p1_o => dac_dpll_load_p1,
+ dac_dpll_data_o => dac_dpll_data,
-- PHY
- phy_ref_clk_i => clk_125m_pllref,
- phy_tx_data_o => phy_tx_data,
- phy_tx_k_o => phy_tx_k,
- phy_tx_disparity_i => phy_tx_disparity,
- phy_tx_enc_err_i => phy_tx_enc_err,
- phy_rx_data_i => phy_rx_data,
- phy_rx_rbclk_i => phy_rx_rbclk,
- phy_rx_k_i => phy_rx_k,
- phy_rx_enc_err_i => phy_rx_enc_err,
- phy_rx_bitslide_i => phy_rx_bitslide,
- phy_rst_o => phy_rst,
- phy_loopen_o => phy_loopen,
+ phy_ref_clk_i => clk_125m_pllref,
+ phy_tx_data_o => phy_tx_data,
+ phy_tx_k_o => phy_tx_k,
+ phy_tx_disparity_i => phy_tx_disparity,
+ phy_tx_enc_err_i => phy_tx_enc_err,
+ phy_rx_data_i => phy_rx_data,
+ phy_rx_rbclk_i => phy_rx_rbclk,
+ phy_rx_k_i => phy_rx_k,
+ phy_rx_enc_err_i => phy_rx_enc_err,
+ phy_rx_bitslide_i => phy_rx_bitslide,
+ phy_rst_o => phy_rst,
+ phy_loopen_o => phy_loopen,
-- SPEC LEDs
- led_act_o => LED_RED,
- led_link_o => LED_GREEN,
+ led_act_o => LED_RED,
+ led_link_o => LED_GREEN,
-- SFP
- scl_o => wrc_scl_out,
- scl_i => wrc_scl_in,
- sda_o => wrc_sda_out,
- sda_i => wrc_sda_in,
- sfp_scl_o => sfp_scl_out,
- sfp_scl_i => sfp_scl_in,
- sfp_sda_o => sfp_sda_out,
- sfp_sda_i => sfp_sda_in,
- sfp_det_i => sfp_mod_def0_b,
- uart_rxd_i => uart_rxd_i,
- uart_txd_o => uart_txd_o,
+ scl_o => wrc_scl_out,
+ scl_i => wrc_scl_in,
+ sda_o => wrc_sda_out,
+ sda_i => wrc_sda_in,
+ sfp_scl_o => sfp_scl_out,
+ sfp_scl_i => sfp_scl_in,
+ sfp_sda_o => sfp_sda_out,
+ sfp_sda_i => sfp_sda_in,
+ sfp_det_i => sfp_mod_def0_b,
+ uart_rxd_i => uart_rxd_i,
+ uart_txd_o => uart_txd_o,
-- 1-wire
- owr_en_o => wrc_owr_en,
- owr_i => wrc_owr_in,
+ owr_en_o => wrc_owr_en,
+ owr_i => wrc_owr_in,
-- WISHBONE
- slave_i => cnx_master_out(c_SLAVE_WRCORE),
- slave_o => cnx_master_in(c_SLAVE_WRCORE),
+ slave_i => cnx_master_out(c_SLAVE_WRCORE),
+ slave_o => cnx_master_in(c_SLAVE_WRCORE),
-- Timimg info for TDC core
- tm_link_up_o => tm_link_up,
- tm_dac_value_o => tm_dac_value,
- tm_dac_wr_o(0) => tm_dac_wr_p,
- tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
- tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
- tm_time_valid_o => tm_time_valid,
- tm_tai_o => tm_utc,
- tm_cycles_o => tm_cycles,
+ tm_link_up_o => tm_link_up,
+ tm_dac_value_o => tm_dac_value,
+ tm_dac_wr_o(0) => tm_dac_wr_p,
+ tm_clk_aux_lock_en_i(0) => tm_clk_aux_lock_en,
+ tm_clk_aux_locked_o(0) => tm_clk_aux_locked,
+ tm_time_valid_o => tm_time_valid,
+ tm_tai_o => tm_tai,
+ tm_cycles_o => tm_cycles,
-- not used
- btn1_i => '1',
- btn2_i => '1',
- pps_p_o => open,
+ btn1_i => '1',
+ btn2_i => '1',
+ pps_p_o => open,
-- aux reset
- rst_aux_n_o => open);
+ rst_aux_n_o => open);
+gen_with_wr_phy: if g_with_wr_phy generate
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_GTP : wr_gtp_phy_spartan6
- generic map
- (g_simulation => 0,
- g_enable_ch0 => 0,
- g_enable_ch1 => 1)
- port map
+ generic map
+ (g_simulation => 0,
+ g_enable_ch0 => 0,
+ g_enable_ch1 => 1)
+ port map
(gtp_clk_i => clk_125m_gtp,
ch0_ref_clk_i => clk_125m_pllref,
ch0_tx_data_i => x"00",
@@ -722,7 +678,7 @@ begin
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
- ch1_loopen_i => '0', -- phy_loopen,
+ ch1_loopen_i => '0', -- phy_loopen,
pad_txn0_o => open,
pad_txp0_o => open,
pad_rxn0_i => '0',
@@ -732,47 +688,26 @@ begin
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
+
+ end generate gen_with_wr_phy;
+
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_DAC_ARB : spec_serial_dac_arb
- generic map
+ generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
- port map
- (clk_i => clk_62m5_sys,
- rst_n_i => rst_sys_n,
- val1_i => dac_dpll_data,
- load1_i => dac_dpll_load_p1,
- val2_i => dac_hpll_data,
- load2_i => dac_hpll_load_p1,
- dac_cs_n_o(0) => dac_cs1_n_o,
- dac_cs_n_o(1) => dac_cs2_n_o,
+ port map
+ (clk_i => clk_62m5_sys,
+ rst_n_i => rst_n_sys,
+ val1_i => dac_dpll_data,
+ load1_i => dac_dpll_load_p1,
+ val2_i => dac_hpll_data,
+ load2_i => dac_hpll_load_p1,
+ dac_cs_n_o(0) => dac_cs1_n_o,
+ dac_cs_n_o(1) => dac_cs2_n_o,
-- dac_clr_n_o => open,
- dac_sclk_o => dac_sclk_o,
- dac_din_o => dac_din_o);
- -- -- -- -- -- --
- sfp_tx_disable_o <= '0';
- -- dac_clr_n_o <= '1';
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Tristates for TDC mezzanine EEPROM
- mezz_sys_scl_b <= tdc_scl_out when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
- mezz_sys_sda_b <= tdc_sda_out when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
- wrc_scl_in <= mezz_sys_scl_b;
- wrc_sda_in <= mezz_sys_sda_b;
- tdc_scl_in <= mezz_sys_scl_b;
- tdc_sda_in <= mezz_sys_sda_b;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Tristates for SFP EEPROM
- sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
- sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
- sfp_scl_in <= sfp_mod_def1_b;
- sfp_sda_in <= sfp_mod_def2_b;
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
- wrc_owr_in(0) <= carrier_onewire_b;
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ dac_sclk_o => dac_sclk_o,
+ dac_din_o => dac_din_o);
---------------------------------------------------------------------------------------------------
@@ -789,58 +724,66 @@ begin
-- 0x13000 -> TDC Mezzanine I2C master
-- 0x14000 -> TDC core timestamps retrieval from memory
cmp_sdb_crossbar : xwb_sdb_crossbar
- generic map
+ generic map
(g_num_masters => c_NUM_WB_SLAVES,
g_num_slaves => c_NUM_WB_MASTERS,
g_registered => true,
g_wraparound => true,
g_layout => c_INTERCONNECT_LAYOUT,
g_sdb_addr => c_SDB_ADDRESS)
- port map
- (clk_sys_i => clk_62m5_sys,
- rst_n_i => rst_sys_n,
- slave_i => cnx_slave_in,
- slave_o => cnx_slave_out,
- master_i => cnx_master_in,
- master_o => cnx_master_out);
+ port map
+ (clk_sys_i => clk_62m5_sys,
+ rst_n_i => rst_n_sys,
+ slave_i => cnx_slave_in,
+ slave_o => cnx_slave_out,
+ master_i => cnx_master_in,
+ master_o => cnx_master_out);
---------------------------------------------------------------------------------------------------
-- GN4124 CORE --
---------------------------------------------------------------------------------------------------
- cmp_gn4124_core: gn4124_core
- port map
- (rst_n_a_i => rst_n_a_i,
+ cmp_gn4124_core : gn4124_core
+ port map
+ (rst_n_a_i => l_rst_n,
status_o => gn4124_status,
- -- P2L Direction Source Sync DDR related signals
- p2l_clk_p_i => p2l_clk_p_i,
- p2l_clk_n_i => p2l_clk_n_i,
- p2l_data_i => p2l_data_i,
- p2l_dframe_i => p2l_dframe_i,
- p2l_valid_i => p2l_valid_i,
- -- P2L Control
- p2l_rdy_o => p2l_rdy_o,
- p_wr_req_i => p_wr_req_i,
- p_wr_rdy_o => p_wr_rdy_o,
- rx_error_o => rx_error_o,
- -- L2P Direction Source Sync DDR related signals
- l2p_clk_p_o => l2p_clk_p_o,
- l2p_clk_n_o => l2p_clk_n_o,
- l2p_data_o => l2p_data_o ,
- l2p_dframe_o => l2p_dframe_o,
- l2p_valid_o => l2p_valid_o,
- l2p_edb_o => l2p_edb_o,
- -- L2P Control
- l2p_rdy_i => l2p_rdy_i,
- l_wr_rdy_i => l_wr_rdy_i,
- p_rd_d_rdy_i => p_rd_d_rdy_i,
- tx_error_i => tx_error_i,
- vc_rdy_i => vc_rdy_i,
- -- Interrupt interface
- dma_irq_o => open,
- irq_p_i => irq_to_gn4124,
- irq_p_o => irq_p_o,
- -- CSR WISHBONE interface (master pipelined)
+ ---------------------------------------------------------
+ -- P2L Direction
+ --
+ -- Source Sync DDR related signals
+ p2l_clk_p_i => P2L_CLKp,
+ p2l_clk_n_i => P2L_CLKn,
+ p2l_data_i => P2L_DATA,
+ p2l_dframe_i => P2L_DFRAME,
+ p2l_valid_i => P2L_VALID,
+ -- P2L Control
+ p2l_rdy_o => P2L_RDY,
+ p_wr_req_i => P_WR_REQ,
+ p_wr_rdy_o => P_WR_RDY,
+ rx_error_o => RX_ERROR,
+ vc_rdy_i => VC_RDY,
+
+ ---------------------------------------------------------
+ -- L2P Direction
+ --
+ -- Source Sync DDR related signals
+ l2p_clk_p_o => L2P_CLKp,
+ l2p_clk_n_o => L2P_CLKn,
+ l2p_data_o => L2P_DATA,
+ l2p_dframe_o => L2P_DFRAME,
+ l2p_valid_o => L2P_VALID,
+ -- L2P Control
+ l2p_edb_o => L2P_EDB,
+ l2p_rdy_i => L2P_RDY,
+ l_wr_rdy_i => L_WR_RDY,
+ p_rd_d_rdy_i => P_RD_D_RDY,
+ tx_error_i => TX_ERROR,
+
+ dma_irq_o => open,
+ irq_p_i => '0',
+ irq_p_o => open,
+
+ -- CSR WISHBONE interface (master pipelined)
csr_clk_i => clk_62m5_sys,
csr_adr_o => gn_wb_adr,
csr_dat_o => cnx_slave_in(c_MASTER_GENNUM).dat,
@@ -851,7 +794,10 @@ begin
csr_dat_i => cnx_slave_out(c_MASTER_GENNUM).dat,
csr_ack_i => cnx_slave_out(c_MASTER_GENNUM).ack,
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
- -- DMA: not used
+ csr_err_i => '0',
+ csr_rty_i => '0',
+ csr_int_i => '0',
+ -- DMA: not used
dma_clk_i => clk_62m5_sys,
dma_adr_o => open,
dma_cyc_o => open,
@@ -862,6 +808,9 @@ begin
dma_ack_i => '1',
dma_dat_i => (others => '0'),
dma_stall_i => '0',
+ dma_err_i => '0',
+ dma_rty_i => '0',
+ dma_int_i => '0',
dma_reg_clk_i => clk_62m5_sys,
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
@@ -877,171 +826,102 @@ begin
-- Convert 32-bit word address into byte address for crossbar
cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";
+ cmp_tdc_mezzanine : fmc_tdc_wrapper
+ generic map (
+ g_simulation => g_simulation,
+ g_with_direct_readout => false)
+ port map (
+ clk_sys_i => clk_62m5_sys,
+ rst_sys_n_i => rst_n_sys,
+ rst_n_a_i => tdc0_soft_rst_n,
+ pll_sclk_o => pll_sclk_o,
+ pll_sdi_o => pll_sdi_o,
+ pll_cs_o => pll_cs_o,
+ pll_dac_sync_o => pll_dac_sync_o,
+ pll_sdo_i => pll_sdo_i,
+ pll_status_i => pll_status_i,
+ tdc_clk_125m_p_i => tdc_clk_125m_p_i,
+ tdc_clk_125m_n_i => tdc_clk_125m_n_i,
+ acam_refclk_p_i => acam_refclk_p_i,
+ acam_refclk_n_i => acam_refclk_n_i,
+ start_from_fpga_o => start_from_fpga_o,
+ err_flag_i => err_flag_i,
+ int_flag_i => int_flag_i,
+ start_dis_o => start_dis_o,
+ stop_dis_o => stop_dis_o,
+ data_bus_io => data_bus_io,
+ address_o => address_o,
+ cs_n_o => cs_n_o,
+ oe_n_o => oe_n_o,
+ rd_n_o => rd_n_o,
+ wr_n_o => wr_n_o,
+ ef1_i => ef1_i,
+ ef2_i => ef2_i,
+ enable_inputs_o => enable_inputs_o,
+ term_en_1_o => term_en_1_o,
+ term_en_2_o => term_en_2_o,
+ term_en_3_o => term_en_3_o,
+ term_en_4_o => term_en_4_o,
+ term_en_5_o => term_en_5_o,
+ tdc_led_status_o => tdc_led_status_o,
+ tdc_led_trig1_o => tdc_led_trig1_o,
+ tdc_led_trig2_o => tdc_led_trig2_o,
+ tdc_led_trig3_o => tdc_led_trig3_o,
+ tdc_led_trig4_o => tdc_led_trig4_o,
+ tdc_led_trig5_o => tdc_led_trig5_o,
+ tdc_in_fpga_1_i => tdc_in_fpga_1_i,
+ tdc_in_fpga_2_i => tdc_in_fpga_2_i,
+ tdc_in_fpga_3_i => tdc_in_fpga_3_i,
+ tdc_in_fpga_4_i => tdc_in_fpga_4_i,
+ tdc_in_fpga_5_i => tdc_in_fpga_5_i,
+ mezz_scl_o => tdc_scl_oen,
+ mezz_sda_o => tdc_sda_oen,
+ mezz_scl_i => tdc_scl_in,
+ mezz_sda_i => tdc_sda_in,
+ mezz_one_wire_b => mezz_onewire_b,
+ tm_link_up_i => tm_link_up,
+ tm_time_valid_i => tm_time_valid,
+ tm_cycles_i => tm_cycles,
+ tm_tai_i => tm_tai,
+ tm_clk_aux_lock_en_o => tm_clk_aux_lock_en,
+ tm_clk_aux_locked_i => tm_clk_aux_locked,
+ tm_clk_dmtd_locked_i => '1',
+ tm_dac_value_i => tm_dac_value,
+ tm_dac_wr_i => tm_dac_wr_p,
+ slave_i => cnx_master_out(c_WB_SLAVE_TDC),
+ slave_o => cnx_master_in(c_WB_SLAVE_TDC),
+ irq_o => tdc0_irq,
+ clk_125m_tdc_o => tdc0_clk_125m);
----------------------------------------------------------------------------------------------------
--- TDC BOARD --
----------------------------------------------------------------------------------------------------
- cmp_tdc_mezz : fmc_tdc_mezzanine
- generic map
- (g_with_wrabbit_core => TRUE,
- g_span => g_span,
- g_width => g_width,
- values_for_simul => FALSE)
- port map
- -- 62M5 clk and reset
- (clk_sys_i => clk_62m5_sys,
- rst_sys_n_i => rst_sys_n,
- -- 125M clk and reset
- clk_ref_0_i => clk_125m_mezz,
- rst_ref_0_i => rst_125m_mezz,
- -- Configuration of the DAC on the TDC mezzanine, non White Rabbit
- acam_refclk_r_edge_p_i => acam_refclk_r_edge_p,
- send_dac_word_p_o => send_dac_word_p,
- dac_word_o => dac_word,
- -- ACAM interface
- start_from_fpga_o => start_from_fpga_o,
- err_flag_i => err_flag_i,
- int_flag_i => int_flag_i,
- start_dis_o => start_dis_o,
- stop_dis_o => stop_dis_o,
- data_bus_io => data_bus_io,
- address_o => address_o,
- cs_n_o => cs_n_o,
- oe_n_o => oe_n_o,
- rd_n_o => rd_n_o,
- wr_n_o => wr_n_o,
- ef1_i => ef1_i,
- ef2_i => ef2_i,
- -- Input channels enable
- enable_inputs_o => enable_inputs_o,
- term_en_1_o => term_en_1_o,
- term_en_2_o => term_en_2_o,
- term_en_3_o => term_en_3_o,
- term_en_4_o => term_en_4_o,
- term_en_5_o => term_en_5_o,
- -- LEDs on TDC mezzanine
- tdc_led_status_o => tdc_led_status_o,
- tdc_led_trig1_o => tdc_led_trig1_o,
- tdc_led_trig2_o => tdc_led_trig2_o,
- tdc_led_trig3_o => tdc_led_trig3_o,
- tdc_led_trig4_o => tdc_led_trig4_o,
- tdc_led_trig5_o => tdc_led_trig5_o,
- -- Input channels to FPGA (not used)
- tdc_in_fpga_1_i => tdc_in_fpga_1_i,
- tdc_in_fpga_2_i => tdc_in_fpga_2_i,
- tdc_in_fpga_3_i => tdc_in_fpga_3_i,
- tdc_in_fpga_4_i => tdc_in_fpga_4_i,
- tdc_in_fpga_5_i => tdc_in_fpga_5_i,
- -- WISHBONE interface with the GN4124 core
- wb_tdc_csr_adr_i => tdc_slave_in.adr,
- wb_tdc_csr_dat_i => tdc_slave_in.dat,
- wb_tdc_csr_stb_i => tdc_slave_in.stb,
- wb_tdc_csr_we_i => tdc_slave_in.we,
- wb_tdc_csr_cyc_i => tdc_slave_in.cyc,
- wb_tdc_csr_sel_i => tdc_slave_in.sel,
- wb_tdc_csr_dat_o => tdc_slave_out.dat,
- wb_tdc_csr_ack_o => tdc_slave_out.ack,
- wb_tdc_csr_stall_o => tdc_slave_out.stall,
- -- White Rabbit
- wrabbit_link_up_i => tm_link_up,
- wrabbit_time_valid_i => tm_time_valid,
- wrabbit_cycles_i => tm_cycles,
- wrabbit_utc_i => tm_utc(31 downto 0),
- wrabbit_clk_aux_lock_en_o => tm_clk_aux_lock_en,
- wrabbit_clk_aux_locked_i => tm_clk_aux_locked,
- wrabbit_clk_dmtd_locked_i => '1', -- FIXME: fan out real signal from the WRCore
- wrabbit_dac_value_i => tm_dac_value_reg,
- wrabbit_dac_wr_p_i => tm_dac_wr_p,
- -- Interrupt line from EIC
- wb_irq_o => fmc_eic_irq,
- -- EEPROM I2C on TDC mezzanine
- i2c_scl_oen_o => tdc_scl_oen,
- i2c_scl_i => tdc_scl_in,
- i2c_sda_oen_o => tdc_sda_oen,
- i2c_sda_i => tdc_sda_in,
- i2c_scl_o => tdc_scl_out,
- i2c_sda_o => tdc_sda_out,
- -- 1-Wire on TDC mezzanine
- onewire_b => mezz_onewire_b);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Domains crossing: clk_125m_mezz <-> clk_62m5_sys
- cmp_tdc_clk_crossing : xwb_clock_crossing
- port map
- (slave_clk_i => clk_62m5_sys, -- Slave control port: GNUM interface at 62.5 MHz
- slave_rst_n_i => rst_sys_n,
- slave_i => cnx_master_out(c_WB_SLAVE_TDC),
- slave_o => cnx_master_in(c_WB_SLAVE_TDC),
- master_clk_i => clk_125m_mezz, -- Master reader port: TDC core at 125 MHz
- master_rst_n_i => rst_125m_mezz_n,
- master_i => tdc_slave_out,
- master_o => tdc_slave_in);
-
-
+
---------------------------------------------------------------------------------------------------
-- VIC --
---------------------------------------------------------------------------------------------------
cmp_vic : xwb_vic
- generic map
+ generic map
(g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_interrupts => 1,
g_init_vectors => c_VIC_VECTOR_TABLE)
- port map
+ port map
(clk_sys_i => clk_62m5_sys,
- rst_n_i => rst_sys_n,
+ rst_n_i => rst_n_sys,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
- irqs_i(0) => fmc_eic_irq_synch(1),
+ irqs_i(0) => tdc0_irq,
irq_master_o => irq_to_gn4124);
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- Domains crossing: synchronization of the wb_ird_o from 125MHz to 62.5MHz
- irq_pulse_synchronizer: process (clk_62m5_sys)
- begin
- if rising_edge (clk_62m5_sys) then
- if rst_sys_n = '0' then
- fmc_eic_irq_synch <= (others => '0');
- else
- fmc_eic_irq_synch <= fmc_eic_irq_synch(0) & fmc_eic_irq;
- end if;
- end if;
- end process;
-
-
----------------------------------------------------------------------------------------------------
--- Carrier 1-wire MASTER DS18B20 (thermometer + unique ID) --
----------------------------------------------------------------------------------------------------
- -- cmp_carrier_onewire : xwb_onewire_master
- -- generic map
- -- (g_interface_mode => CLASSIC,
- -- g_address_granularity => BYTE,
- -- g_num_ports => 1,
- -- g_ow_btp_normal => "5.0",
- -- g_ow_btp_overdrive => "1.0")
- -- port map
- -- (clk_sys_i => clk_62m5_sys,
- -- rst_n_i => rst_sys_n,
- -- slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
- -- slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
- -- desc_o => open,
- -- owr_pwren_o => open,
- -- owr_en_o => carrier_owr_en,
- -- owr_i => carrier_owr_i);
-
- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
- -- carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
- -- carrier_owr_i(0) <= carrier_onewire_b;
-
-
+ gpio(0) <= irq_to_gn4124;
+ gpio(1) <= '0';
+
---------------------------------------------------------------------------------------------------
-- Carrier CSR information --
---------------------------------------------------------------------------------------------------
-- Information on carrier type, mezzanine presence, pcb version
cmp_carrier_info : carrier_info
- port map
- (rst_n_i => rst_sys_n,
+ port map
+ (rst_n_i => rst_n_sys,
clk_sys_i => clk_62m5_sys,
wb_adr_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
wb_dat_i => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
@@ -1057,9 +937,10 @@ begin
carrier_info_carrier_type_i => c_CARRIER_TYPE,
carrier_info_stat_fmc_pres_i => prsnt_m2c_n_i,
carrier_info_stat_p2l_pll_lck_i => gn4124_status(0),
- carrier_info_stat_sys_pll_lck_i => pll_mezz_status,
+ carrier_info_stat_sys_pll_lck_i => sys_locked,
carrier_info_stat_ddr3_cal_done_i => '0',
- carrier_info_stat_reserved_i => x"000000" & "000" & sys_locked,
+ carrier_info_stat_reserved_i => x"0000000",
+
carrier_info_ctrl_led_green_o => open,
carrier_info_ctrl_led_red_o => open,
carrier_info_ctrl_dac_clr_n_o => open,
@@ -1067,16 +948,42 @@ begin
carrier_info_rst_fmc0_n_o => open,
carrier_info_rst_fmc0_n_i => '1',
carrier_info_rst_fmc0_n_load_o => open,
- carrier_info_rst_reserved_o => open);
+ carrier_info_rst_reserved_o => carrier_info_fmc_rst);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Unused wishbone signals
- cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
- cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
- cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
+ cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
+ cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
+ cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
+
+
+ -- -- -- -- -- --
+ sfp_tx_disable_o <= '0';
+ -- dac_clr_n_o <= '1';
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Tristates for TDC mezzanine EEPROM
+ mezz_sys_scl_b <= '0' when (tdc_scl_oen = '0') else '0' when (wrc_scl_out = '0') else 'Z';
+ mezz_sys_sda_b <= '0' when (tdc_sda_oen = '0') else '0' when (wrc_sda_out = '0') else 'Z';
+ wrc_scl_in <= mezz_sys_scl_b;
+ wrc_sda_in <= mezz_sys_sda_b;
+ tdc_scl_in <= mezz_sys_scl_b;
+ tdc_sda_in <= mezz_sys_sda_b;
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ -- Tristates for SFP EEPROM
+ sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+ sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+ sfp_scl_in <= sfp_mod_def1_b;
+ sfp_sda_in <= sfp_mod_def2_b;
+
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
+ carrier_onewire_b <= '0' when wrc_owr_en(0) = '1' else 'Z';
+ wrc_owr_in(0) <= carrier_onewire_b;
+ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
-----------------------------------------------------------------------------------------------------
\ No newline at end of file
+----------------------------------------------------------------------------------------------------
diff --git a/hdl/top/svec/wr_svec_tdc.vhd b/hdl/top/svec/wr_svec_tdc.vhd
index ed93206..5e22e70 100644
--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -25,18 +25,14 @@
-- All these cores communicate with the VME core through the WISHBONE. |
-- The SDB crossbar is mapping the different slaves into the WISHBONE address space. |
-- |
--- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores however operate at|
--- 125 MHz (like this the TDC core can keep up to speed with the maximum speed the |
--- ACAM can be receiving timestamps). The crossing from the 62.5 MHz world to the |
--- 125 MHz world takes place through dedicated clock_crossing modules. |
+-- The speed for the VME core is 62.5 MHz. The TDC mezzanine cores
+-- internally operate at 125 MHz, but the wishbone bus works still
+-- at system-wide 62.5 MHz clock.
-- |
-- The 62.5 MHz clock comes from an internal Xilinx FPGA PLL, using the 20MHz VCXO of|
-- the SVEC board. |
-- |
-- The 125 MHz clock for each TDC mezzanine comes from the PLL located on it. |
--- A clks_rsts_manager unit is responsible for automatically configuring the PLL upon|
--- the FPGA startup, using the 62.5 MHz clock. The clks_rsts_manager is keeping the |
--- the TDC mezzanine core under reset until the respective PLL gets locked. |
-- |
-- Upon powering up of the FPGA as well as after a VME reset, the whole logic gets |
-- reset (FMC1 125 MHz, FMC2 125 MHz and 62.5 MHz). This also triggers a |
@@ -53,23 +49,23 @@
-- | | |____________________________| \ | | | |
-- | 62.5MHz \ | | | |
-- | | ____________________________ \| | _____ | |
--- | | | ____________ _______ | | | | | | |
--- | |---|->| | | clk | | | | | | | |
--- | | | | TDC mezz 1 | | cross | | | | | | | |
--- FMC1 | | | |____________| |_______| |\ | | | | | |
--- | | | FMC1 125MHz | \ | | | | | |
--- | | | ___________________ | \ | | | | | |
--- | |---|--->|_clks_rsts_manager_| | \ | | | | | |
+-- | | | | | | | | | |
+-- | |---| | | | | | | |
+-- | | | | | | | | | |
+-- FMC1 | | | TDC mezzanine 1 |\ | | | | | |
+-- | | | wrapper | \ | | | | | |
+-- | | | | \ | | | | | |
+-- | |---| | \ | | | | | |
-- | | |____________________________| \| | | | | |
-- | | | | | | | |
-- | | ____________________________ | | | | | |
--- | | | ____________ _______ | | | | | | |
--- | | | | | | clk | | | | | | | |
--- | |---|->| TDC mezz 2 | | cross | | | S | | V | | |
--- FMC2 | | | |____________| |_______| | ---- | | | | | |
--- | | | FMC2 125MHz | | | | | | |
--- | | | ___________________ | | | | | | |
--- | |---|--->|_clks_rsts_manager_| | | | | | | |
+-- | | | | | | | | | |
+-- | | | | | | | | | |
+-- | |---| | | S | | V | | |
+-- FMC2 | | | TDC mezzanine 2 | ---- | | | | | |
+-- | | | wrapper | | | | | | |
+-- | | | | | | | | | |
+-- | |---| | | | | | | |
-- | |____________________________| | D | <--> | M | | |
-- | | | | | | |
-- | ____________________________ | | | | | |
@@ -137,10 +133,8 @@ use work.synthesis_descriptor.all;
-- Entity declaration for top_tdc
--=================================================================================================
entity wr_svec_tdc is
- generic
- (g_span : integer := 32; -- address span in bus interfaces
- g_width : integer := 32; -- data width in bus interfaces
- g_simulation : boolean := false;
+ generic (
+ g_simulation : boolean := false;
g_with_wr_phy : boolean := true);
port
(-- SVEC carrier
@@ -324,6 +318,15 @@ end wr_svec_tdc;
--=================================================================================================
architecture rtl of wr_svec_tdc is
+ function f_bool2int (x : boolean) return integer is
+ begin
+ if(x) then
+ return 1;
+ else
+ return 0;
+ end if;
+ end f_bool2int;
+
component spec_serial_dac is
generic (
g_num_data_bits : integer;
@@ -664,7 +667,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
U_WR_CORE : xwr_core
generic map
- (g_simulation => 0,
+ (g_simulation => f_bool2int(g_simulation),
g_phys_uart => true,
g_virtual_uart => true,
g_with_external_clock_input => false,
--
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