diff --git a/.gitignore b/.gitignore
index 58989e196d1c7343c61031ac974af6250c238c24..ddd5c2fbd77836173646e9a3a3c373544cebb9d2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,5 +7,9 @@ modelsim.ini
 *.vstf
 work
 *.bak
-syn/*
-transcript
\ No newline at end of file
+hdl/syn/*
+transcript
+work/
+NullFile
+*.orig
+*.html
\ No newline at end of file
diff --git a/hdl/ip_cores/general-cores b/hdl/ip_cores/general-cores
index 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980..96295346bb6742b03b43930a4e8a5c73028f4572 160000
--- a/hdl/ip_cores/general-cores
+++ b/hdl/ip_cores/general-cores
@@ -1 +1 @@
-Subproject commit 29db1b2af734d9a9e530cb4dbeb2ec56f9f38980
+Subproject commit 96295346bb6742b03b43930a4e8a5c73028f4572
diff --git a/hdl/ip_cores/gn4124-core b/hdl/ip_cores/gn4124-core
index 7082c5833a2569b24ad69d5f94269eaeff1c7af3..9c9bffc908e371ea298cdc52d9b12abb35e05dc3 160000
--- a/hdl/ip_cores/gn4124-core
+++ b/hdl/ip_cores/gn4124-core
@@ -1 +1 @@
-Subproject commit 7082c5833a2569b24ad69d5f94269eaeff1c7af3
+Subproject commit 9c9bffc908e371ea298cdc52d9b12abb35e05dc3
diff --git a/hdl/ip_cores/wr-cores b/hdl/ip_cores/wr-cores
index 598a2f6ccbf1ac937ff589c0797cd2a487306efe..bcd1f0a3be98c58d2648b788d2f15fdcb3ed820a 160000
--- a/hdl/ip_cores/wr-cores
+++ b/hdl/ip_cores/wr-cores
@@ -1 +1 @@
-Subproject commit 598a2f6ccbf1ac937ff589c0797cd2a487306efe
+Subproject commit bcd1f0a3be98c58d2648b788d2f15fdcb3ed820a
diff --git a/hdl/syn/svec/Manifest.py b/hdl/syn/svec/Manifest.py
index f45df84961f65504340e5a559c341d6f1320d28c..dce428519a3dab75f1380b8cfc66df8ad70a3fb8 100644
--- a/hdl/syn/svec/Manifest.py
+++ b/hdl/syn/svec/Manifest.py
@@ -8,5 +8,6 @@ syn_grade = "-3"
 syn_package = "fgg900"
 syn_top = "wr_svec_tdc"
 syn_project = "wr_svec_tdc.xise"
+syn_tool = "ise"
 
 modules = { "local" : [ "../../top/svec" ] }
diff --git a/hdl/syn/svec/wr_svec_tdc.xise b/hdl/syn/svec/wr_svec_tdc.xise
index 5b5107ba5aadebd1bf6649585c9f3cbab1dde70c..947adc59aa6f8d6aad6010d3d9c644e8494c4706 100644
--- a/hdl/syn/svec/wr_svec_tdc.xise
+++ b/hdl/syn/svec/wr_svec_tdc.xise
@@ -36,7 +36,7 @@
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
     <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -182,7 +182,7 @@
     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="High" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
@@ -236,7 +236,7 @@
     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
@@ -352,801 +352,968 @@
   <libraries/>
 
   <files>
-    <file xil_pn:name="../../top/svec/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/chipscope/chipscope_icon.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/tdc_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
+    <file xil_pn:name="../../top/svec/wr_svec_tdc.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/acam_databus_interface.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+    <file xil_pn:name="../../top/svec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="166"/>
     </file>
-    <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
     </file>
-    <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="149"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
     </file>
-    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
     </file>
-    <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_mezzanine.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="147"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="172"/>
     </file>
-    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
-    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
     </file>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
     </file>
-    <file xil_pn:name="../../rtl/wrabbit_sync.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="130"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="171"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_wrapper.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="176"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo_wb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/timestamp_fifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/xwrc_platform_xilinx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../top/svec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_kintex7.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tdp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="165"/>
+    <file xil_pn:name="../../rtl/clks_rsts_manager.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
+    <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
+    <file xil_pn:name="../../rtl/reg_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_ac_wbm_auto_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="155"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="139"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
     </file>
-    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_flags.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_piso_fifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_queue_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
+    </file>
+    <file xil_pn:name="../../rtl/data_engine.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
+    </file>
+    <file xil_pn:name="../../rtl/local_pps_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_data.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_channel.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_tag_channel.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../rtl/data_formatting.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="123"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
+    </file>
+    <file xil_pn:name="../../rtl/start_retrig_ctrl.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/xwr_streamers.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="148"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/xwr_endpoint.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="144"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="154"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../rtl/fmc_tdc_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="131"/>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
+    </file>
+    <file xil_pn:name="../../rtl/leds_manager.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
     </file>
     <file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/xwr_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
     </file>
-    <file xil_pn:name="../../top/svec/wr_svec_tdc.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="151"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/wrf_loopback.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../rtl/fmc_tdc_direct_readout.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="127"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtx_wrapper_gtx.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/whiterabbitgtp_wrapper_tile.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="150"/>
+    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
     </file>
-    <file xil_pn:name="../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="125"/>
+    </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
+    </file>
   </files>
 
-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/wr_svec_tdc" xil_pn:name="../../top/svec/wr_svec_tdc.ucf"/>
+  </bindings>
 
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
diff --git a/hdl/top/spec/synthesis_descriptor.vhd b/hdl/top/spec/synthesis_descriptor.vhd
index e2aa0d1d10aa9bc25a5597fa0b00e51228ae4cc0..6e3abf13183115566c4191e9d47ef727507fcbcd 100644
--- a/hdl/top/spec/synthesis_descriptor.vhd
+++ b/hdl/top/spec/synthesis_descriptor.vhd
@@ -1,57 +1,57 @@
--------------------------------------------------------------------------------
--- Title      : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
--- Project    : TDC FMC (fmc-tdc-1ns-5cha)
--------------------------------------------------------------------------------
--- File       : synthesis_descriptor.vhd
--- Author     : Evangelia Gousiou
--- Company    : CERN
--- Created    : 2013-04-16
--- Last update: 2013-04-16
--- Platform   : FPGA-generic
--- Standard   : VHDL'93
--------------------------------------------------------------------------------
--- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
--- Contains synthesis & source repository information.
--- Warning: this file is modified whenever a synthesis is executed.
--------------------------------------------------------------------------------
---
--- Copyright (c) 2013 CERN / BE-CO-HT
---
--- This source file is free software; you can redistribute it   
--- and/or modify it under the terms of the GNU Lesser General   
--- Public License as published by the Free Software Foundation; 
--- either version 2.1 of the License, or (at your option) any   
--- later version.                                               
---
--- This source is distributed in the hope that it will be       
--- useful, but WITHOUT ANY WARRANTY; without even the implied   
--- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
--- PURPOSE.  See the GNU Lesser General Public License for more 
--- details.                                                     
---
--- You should have received a copy of the GNU Lesser General    
--- Public License along with this source; if not, download it   
--- from http://www.gnu.org/licenses/lgpl-2.1.html
---
--------------------------------------------------------------------------------
-library ieee;
-use ieee.STD_LOGIC_1164.all;
-use work.wishbone_pkg.all;
-
-package synthesis_descriptor is
-  
-constant c_sdb_synthesis_info : t_sdb_synthesis :=
-  (
-    syn_module_name => "wr_spec_tdc     ",
-    syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
-    syn_tool_name => "ISE     ",
-    syn_tool_version => x"00000147",
-    syn_date => x"20150522",
-    syn_username => "twlostow       ");
-
-constant c_sdb_repo_url : t_sdb_repo_url :=
-  (
-    repo_url => "http://svn.ohwr.org/fmc-tdc                                    " 
-  );
-
-end package synthesis_descriptor;
+-------------------------------------------------------------------------------
+-- Title      : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
+-- Project    : TDC FMC (fmc-tdc-1ns-5cha)
+-------------------------------------------------------------------------------
+-- File       : synthesis_descriptor.vhd
+-- Author     : Evangelia Gousiou
+-- Company    : CERN
+-- Created    : 2013-04-16
+-- Last update: 2017-09-20
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
+-- Contains synthesis & source repository information.
+-- Warning: this file is modified whenever a synthesis is executed.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use work.wishbone_pkg.all;
+
+package synthesis_descriptor is
+  
+  constant c_sdb_synthesis_info : t_sdb_synthesis :=
+    (
+      syn_module_name  => "wr_spec_tdc     ",
+      syn_commit_id    => "5765c94d3f0b118adcc9bfea880aca75",
+      syn_tool_name    => "ISE     ",
+      syn_tool_version => x"00000147",
+      syn_date         => x"20170920",
+      syn_username     => "twlostow       ");
+
+  constant c_sdb_repo_url : t_sdb_repo_url :=
+    (
+      repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git    "
+      );
+
+end package synthesis_descriptor;
diff --git a/hdl/top/spec/wr_spec_tdc.ucf b/hdl/top/spec/wr_spec_tdc.ucf
index 5320a1808a4395c4c5ca2db1dce1a965017d385e..40356b77fbc92803d65f7ce461214b9e27fbe50e 100644
--- a/hdl/top/spec/wr_spec_tdc.ucf
+++ b/hdl/top/spec/wr_spec_tdc.ucf
@@ -416,9 +416,6 @@ TIMESPEC TS_x4 = FROM "U_GTP_ch1_rx_divclk" TO "clk_62m5_sys" 10ns DATAPATHONLY;
 
 
 ##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
-INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
-TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 2 ns DATAPATHONLY;
 
 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/08
 INST "U_WR_CORE/WRPC/U_Endpoint/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = rx_ts_trig;
@@ -428,3 +425,8 @@ NET "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = gen_with_wr_phy.U_GT
 TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_phy.U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
 NET "cmp_gn4124_core/cmp_clk_in/feedback" TNM_NET = cmp_gn4124_core/cmp_clk_in/feedback;
 TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_feedback = PERIOD "cmp_gn4124_core/cmp_clk_in/feedback" 5 ns HIGH 50%;
+
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
diff --git a/hdl/top/spec/wr_spec_tdc.vhd b/hdl/top/spec/wr_spec_tdc.vhd
index 8913af0523c86ae9a91646d69a94f28231f0a18a..0deaff63ea8421cb7d78b4187bdf1ffba2a45d6b 100644
--- a/hdl/top/spec/wr_spec_tdc.vhd
+++ b/hdl/top/spec/wr_spec_tdc.vhd
@@ -181,9 +181,9 @@ entity wr_spec_tdc is
       ------------------------------------------------------------------------
       -- GN4124 PCI bridge pins
       ------------------------------------------------------------------------
-      
+
       l_rst_n : in std_logic;           -- reset from gn4124 (rstout18_n)
-      
+
       -- general purpose interface
       gpio       : inout std_logic_vector(1 downto 0);  -- gpio[0] -> gn4124 gpio8
                                         -- gpio[1] -> gn4124 gpio9
@@ -303,21 +303,21 @@ architecture rtl of wr_spec_tdc is
 --                                         SDB CONSTANTS                                         --
 ---------------------------------------------------------------------------------------------------
 
-    constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
-    (abi_class     => x"0000",               -- undocumented device
+  constant c_SPEC_INFO_SDB_DEVICE : t_sdb_device :=
+    (abi_class     => x"0000",          -- undocumented device
      abi_ver_major => x"01",
      abi_ver_minor => x"01",
      wbd_endian    => c_sdb_endian_big,
-     wbd_width     => x"4",                  -- 32-bit port granularity
+     wbd_width     => x"4",             -- 32-bit port granularity
      sdb_component =>
-       (addr_first  => x"0000000000000000",
-        addr_last   => x"000000000000001F",
-        product     =>
-          (vendor_id => x"000000000000CE42", -- CERN
-           device_id => x"00000603",         -- "WB-SPEC.CSR        " | md5sum | cut -c1-8
-           version   => x"00000001",
-           date      => x"20121116",
-           name      => "WB-SPEC.CSR        ")));
+     (addr_first   => x"0000000000000000",
+      addr_last    => x"000000000000001F",
+      product =>
+      (vendor_id   => x"000000000000CE42",  -- CERN
+       device_id   => x"00000603",  -- "WB-SPEC.CSR        " | md5sum | cut -c1-8
+       version     => x"00000001",
+       date        => x"20121116",
+       name        => "WB-SPEC.CSR        ")));
 
 -- Note: All address in sdb and crossbar are BYTE addresses!
 
@@ -346,7 +346,7 @@ architecture rtl of wr_spec_tdc is
      4 => f_sdb_embed_repo_url (c_SDB_REPO_URL),
      5 => f_sdb_embed_synthesis (c_sdb_synthesis_info));
 
-  
+
 ---------------------------------------------------------------------------------------------------
 --                                         VIC CONSTANT                                          --
 ---------------------------------------------------------------------------------------------------
@@ -366,7 +366,7 @@ architecture rtl of wr_spec_tdc is
   -- TDC core clocks and resets
   signal clk_20m_vcxo, clk_20m_vcxo_buf                   : std_logic;
   signal clk_62m5_sys, sys_locked                         : std_logic;
-  signal rst_n_sys                               : std_logic;
+  signal rst_n_sys                                        : std_logic;
   -- DAC configuration through PCIe/VME
   -- WISHBONE from crossbar master port
   signal cnx_master_out                                   : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
@@ -380,7 +380,7 @@ architecture rtl of wr_spec_tdc is
   -- Carrier 1-wire
   signal carrier_owr_en, carrier_owr_i                    : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
   -- VIC
-  signal irq_to_gn4124                       : std_logic;
+  signal irq_to_gn4124                                    : std_logic;
   -- WRabbit time
   signal tm_link_up, tm_time_valid, tm_dac_wr_p           : std_logic;
   signal tm_tai                                           : std_logic_vector(39 downto 0);
@@ -389,8 +389,8 @@ architecture rtl of wr_spec_tdc is
   signal tm_clk_aux_lock_en, tm_clk_aux_locked            : std_logic;
   -- WRabbit PHY
   signal phy_tx_data, phy_rx_data                         : std_logic_vector(7 downto 0);
-  signal phy_tx_k, phy_tx_disparity, phy_rx_k             : std_logic;
-  signal phy_tx_enc_err, phy_rx_rbclk                     : std_logic;
+  signal phy_tx_k,  phy_rx_k             : std_logic_vector(0 downto 0);
+  signal phy_tx_enc_err, phy_rx_rbclk, phy_tx_disparity                     : std_logic;
   signal phy_rx_enc_err, phy_rst, phy_loopen              : std_logic;
   signal phy_rx_bitslide                                  : std_logic_vector(3 downto 0);
   -- DAC configuration through WRabbit
@@ -406,12 +406,12 @@ architecture rtl of wr_spec_tdc is
   signal wrc_owr_en, wrc_owr_in                           : std_logic_vector(1 downto 0);
   -- aux
 
-  signal tdc0_irq: std_logic;
-  signal tdc0_clk_125m : std_logic;
-  signal tdc0_soft_rst_n: std_logic;
+  signal tdc0_irq        : std_logic;
+  signal tdc0_clk_125m   : std_logic;
+  signal tdc0_soft_rst_n : std_logic;
 
-  signal powerup_rst_cnt                      : unsigned(7 downto 0) := "00000000";
-  signal carrier_info_fmc_rst                 : std_logic_vector(30 downto 0);
+  signal powerup_rst_cnt      : unsigned(7 downto 0) := "00000000";
+  signal carrier_info_fmc_rst : std_logic_vector(30 downto 0);
 
 --=================================================================================================
 --                                       architecture begin
@@ -545,27 +545,27 @@ begin
 -- waits for the system clock PLL to lock + additional 256 clk_62m5_sys cycles before de-asserting
 -- the reset.
 
-  p_powerup_reset : process(clk_62m5_sys,l_rst_n)
+  p_powerup_reset : process(clk_62m5_sys, l_rst_n)
   begin
     if(l_rst_n = '0') then
-      rst_n_sys           <= '0';
+      rst_n_sys <= '0';
     elsif rising_edge(clk_62m5_sys) then
       if sys_locked = '1' then
         if(powerup_rst_cnt = "11111111") then
-          rst_n_sys       <= '1';
+          rst_n_sys <= '1';
         else
           rst_n_sys       <= '0';
           powerup_rst_cnt <= powerup_rst_cnt + 1;
         end if;
       else
-        rst_n_sys         <= '0';
-        powerup_rst_cnt   <= "00000000";
+        rst_n_sys       <= '0';
+        powerup_rst_cnt <= "00000000";
       end if;
     end if;
   end process;
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  tdc0_soft_rst_n             <= carrier_info_fmc_rst(0) and rst_n_sys;
+  tdc0_soft_rst_n <= carrier_info_fmc_rst(0) and rst_n_sys;
 
 ---------------------------------------------------------------------------------------------------
 --                                  White Rabbit Core + PHY                                      --
@@ -578,13 +578,16 @@ begin
      g_phys_uart                 => true,
      g_virtual_uart              => true,
      g_with_external_clock_input => false,
+     g_board_name                => "SPEC",
      g_aux_clks                  => 1,
      g_ep_rxbuf_size             => 1024,
-     g_dpram_initf => "wrc.ram",
-     g_dpram_size                => 90112/4,
+     g_dpram_initf               => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
+     g_dpram_size                => 131072/4,
      g_interface_mode            => PIPELINED,
      g_address_granularity       => BYTE,
-     g_softpll_enable_debugger   => false)
+     g_softpll_enable_debugger   => false,
+     g_pcs_16bit                 => false,
+     g_records_for_phy           => false)
     port map
     (clk_sys_i               => clk_62m5_sys,
      clk_dmtd_i              => clk_dmtd,
@@ -646,51 +649,51 @@ begin
      -- aux reset
      rst_aux_n_o             => open);
 
-gen_with_wr_phy:  if g_with_wr_phy generate
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  U_GTP : wr_gtp_phy_spartan6
-    generic map
-    (g_simulation => 0,
-     g_enable_ch0 => 0,
-     g_enable_ch1 => 1)
-    port map
-    (gtp_clk_i          => clk_125m_gtp,
-     ch0_ref_clk_i      => clk_125m_pllref,
-     ch0_tx_data_i      => x"00",
-     ch0_tx_k_i         => '0',
-     ch0_tx_disparity_o => open,
-     ch0_tx_enc_err_o   => open,
-     ch0_rx_rbclk_o     => open,
-     ch0_rx_data_o      => open,
-     ch0_rx_k_o         => open,
-     ch0_rx_enc_err_o   => open,
-     ch0_rx_bitslide_o  => open,
-     ch0_rst_i          => '1',
-     ch0_loopen_i       => '0',
-     ch1_ref_clk_i      => clk_125m_pllref,
-     ch1_tx_data_i      => phy_tx_data,
-     ch1_tx_k_i         => phy_tx_k,
-     ch1_tx_disparity_o => phy_tx_disparity,
-     ch1_tx_enc_err_o   => phy_tx_enc_err,
-     ch1_rx_data_o      => phy_rx_data,
-     ch1_rx_rbclk_o     => phy_rx_rbclk,
-     ch1_rx_k_o         => phy_rx_k,
-     ch1_rx_enc_err_o   => phy_rx_enc_err,
-     ch1_rx_bitslide_o  => phy_rx_bitslide,
-     ch1_rst_i          => phy_rst,
-     ch1_loopen_i       => '0',         -- phy_loopen,
-     pad_txn0_o         => open,
-     pad_txp0_o         => open,
-     pad_rxn0_i         => '0',
-     pad_rxp0_i         => '0',
-     pad_txn1_o         => sfp_txn_o,
-     pad_txp1_o         => sfp_txp_o,
-     pad_rxn1_i         => sfp_rxn_i,
-     pad_rxp1_i         => sfp_rxp_i);
+  gen_with_wr_phy : if g_with_wr_phy generate
+    --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+    U_GTP : wr_gtp_phy_spartan6
+      generic map
+      (g_simulation => 0,
+       g_enable_ch0 => 0,
+       g_enable_ch1 => 1)
+      port map
+      (gtp_clk_i          => clk_125m_gtp,
+       ch0_ref_clk_i      => clk_125m_pllref,
+       ch0_tx_data_i      => x"00",
+       ch0_tx_k_i         => '0',
+       ch0_tx_disparity_o => open,
+       ch0_tx_enc_err_o   => open,
+       ch0_rx_rbclk_o     => open,
+       ch0_rx_data_o      => open,
+       ch0_rx_k_o         => open,
+       ch0_rx_enc_err_o   => open,
+       ch0_rx_bitslide_o  => open,
+       ch0_rst_i          => '1',
+       ch0_loopen_i       => '0',
+       ch1_ref_clk_i      => clk_125m_pllref,
+       ch1_tx_data_i      => phy_tx_data,
+       ch1_tx_k_i         => phy_tx_k(0),
+       ch1_tx_disparity_o => phy_tx_disparity,
+       ch1_tx_enc_err_o   => phy_tx_enc_err,
+       ch1_rx_data_o      => phy_rx_data,
+       ch1_rx_rbclk_o     => phy_rx_rbclk,
+       ch1_rx_k_o         => phy_rx_k(0),
+       ch1_rx_enc_err_o   => phy_rx_enc_err,
+       ch1_rx_bitslide_o  => phy_rx_bitslide,
+       ch1_rst_i          => phy_rst,
+       ch1_loopen_i       => '0',       -- phy_loopen,
+       pad_txn0_o         => open,
+       pad_txp0_o         => open,
+       pad_rxn0_i         => '0',
+       pad_rxp0_i         => '0',
+       pad_txn1_o         => sfp_txn_o,
+       pad_txp1_o         => sfp_txp_o,
+       pad_rxn1_i         => sfp_rxn_i,
+       pad_rxp1_i         => sfp_rxp_i);
 
 
   end generate gen_with_wr_phy;
-  
+
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   U_DAC_ARB : spec_serial_dac_arb
     generic map
@@ -745,39 +748,39 @@ gen_with_wr_phy:  if g_with_wr_phy generate
 ---------------------------------------------------------------------------------------------------
   cmp_gn4124_core : gn4124_core
     port map
-    (rst_n_a_i       => l_rst_n,
-     status_o        => gn4124_status,
-      ---------------------------------------------------------
-      -- P2L Direction
-      --
-      -- Source Sync DDR related signals
-      p2l_clk_p_i  => P2L_CLKp,
-      p2l_clk_n_i  => P2L_CLKn,
-      p2l_data_i   => P2L_DATA,
-      p2l_dframe_i => P2L_DFRAME,
-      p2l_valid_i  => P2L_VALID,
-      -- P2L Control
-      p2l_rdy_o    => P2L_RDY,
-      p_wr_req_i   => P_WR_REQ,
-      p_wr_rdy_o   => P_WR_RDY,
-      rx_error_o   => RX_ERROR,
-      vc_rdy_i     => VC_RDY,
-
-      ---------------------------------------------------------
-      -- L2P Direction
-      --
-      -- Source Sync DDR related signals
-      l2p_clk_p_o  => L2P_CLKp,
-      l2p_clk_n_o  => L2P_CLKn,
-      l2p_data_o   => L2P_DATA,
-      l2p_dframe_o => L2P_DFRAME,
-      l2p_valid_o  => L2P_VALID,
-      -- L2P Control
-      l2p_edb_o    => L2P_EDB,
-      l2p_rdy_i    => L2P_RDY,
-      l_wr_rdy_i   => L_WR_RDY,
-      p_rd_d_rdy_i => P_RD_D_RDY,
-      tx_error_i   => TX_ERROR,
+    (rst_n_a_i    => l_rst_n,
+     status_o     => gn4124_status,
+     ---------------------------------------------------------
+     -- P2L Direction
+     --
+     -- Source Sync DDR related signals
+     p2l_clk_p_i  => P2L_CLKp,
+     p2l_clk_n_i  => P2L_CLKn,
+     p2l_data_i   => P2L_DATA,
+     p2l_dframe_i => P2L_DFRAME,
+     p2l_valid_i  => P2L_VALID,
+     -- P2L Control
+     p2l_rdy_o    => P2L_RDY,
+     p_wr_req_i   => P_WR_REQ,
+     p_wr_rdy_o   => P_WR_RDY,
+     rx_error_o   => RX_ERROR,
+     vc_rdy_i     => VC_RDY,
+
+     ---------------------------------------------------------
+     -- L2P Direction
+     --
+     -- Source Sync DDR related signals
+     l2p_clk_p_o  => L2P_CLKp,
+     l2p_clk_n_o  => L2P_CLKn,
+     l2p_data_o   => L2P_DATA,
+     l2p_dframe_o => L2P_DFRAME,
+     l2p_valid_o  => L2P_VALID,
+     -- L2P Control
+     l2p_edb_o    => L2P_EDB,
+     l2p_rdy_i    => L2P_RDY,
+     l_wr_rdy_i   => L_WR_RDY,
+     p_rd_d_rdy_i => P_RD_D_RDY,
+     tx_error_i   => TX_ERROR,
 
      dma_irq_o => open,
      irq_p_i   => '0',
@@ -794,9 +797,9 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      csr_dat_i       => cnx_slave_out(c_MASTER_GENNUM).dat,
      csr_ack_i       => cnx_slave_out(c_MASTER_GENNUM).ack,
      csr_stall_i     => cnx_slave_out(c_MASTER_GENNUM).stall,
-     csr_err_i => '0',
-     csr_rty_i => '0',
-     csr_int_i => '0',
+     csr_err_i       => '0',
+     csr_rty_i       => '0',
+     csr_int_i       => '0',
      -- DMA: not used
      dma_clk_i       => clk_62m5_sys,
      dma_adr_o       => open,
@@ -808,9 +811,9 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      dma_ack_i       => '1',
      dma_dat_i       => (others => '0'),
      dma_stall_i     => '0',
-     dma_err_i => '0',
-     dma_rty_i => '0',
-     dma_int_i => '0',
+     dma_err_i       => '0',
+     dma_rty_i       => '0',
+     dma_int_i       => '0',
      dma_reg_clk_i   => clk_62m5_sys,
      dma_reg_adr_i   => (others => '0'),
      dma_reg_dat_i   => (others => '0'),
@@ -893,7 +896,7 @@ gen_with_wr_phy:  if g_with_wr_phy generate
       irq_o                => tdc0_irq,
       clk_125m_tdc_o       => tdc0_clk_125m);
 
-  
+
 ---------------------------------------------------------------------------------------------------
 --                                              VIC                                              --
 ---------------------------------------------------------------------------------------------------
@@ -913,7 +916,7 @@ gen_with_wr_phy:  if g_with_wr_phy generate
 
   gpio(0) <= irq_to_gn4124;
   gpio(1) <= '0';
-  
+
 ---------------------------------------------------------------------------------------------------
 --                                    Carrier CSR information                                    --
 ---------------------------------------------------------------------------------------------------
@@ -940,15 +943,15 @@ gen_with_wr_phy:  if g_with_wr_phy generate
      carrier_info_stat_sys_pll_lck_i   => sys_locked,
      carrier_info_stat_ddr3_cal_done_i => '0',
      carrier_info_stat_reserved_i      => x"0000000",
-     
-     carrier_info_ctrl_led_green_o     => open,
-     carrier_info_ctrl_led_red_o       => open,
-     carrier_info_ctrl_dac_clr_n_o     => open,
-     carrier_info_ctrl_reserved_o      => open,
-     carrier_info_rst_fmc0_n_o         => open,
-     carrier_info_rst_fmc0_n_i         => '1',
-     carrier_info_rst_fmc0_n_load_o    => open,
-     carrier_info_rst_reserved_o       => carrier_info_fmc_rst);
+
+     carrier_info_ctrl_led_green_o  => open,
+     carrier_info_ctrl_led_red_o    => open,
+     carrier_info_ctrl_dac_clr_n_o  => open,
+     carrier_info_ctrl_reserved_o   => open,
+     carrier_info_rst_fmc0_n_o      => open,
+     carrier_info_rst_fmc0_n_i      => '1',
+     carrier_info_rst_fmc0_n_load_o => open,
+     carrier_info_rst_reserved_o    => carrier_info_fmc_rst);
 
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   -- Unused wishbone signals
@@ -957,7 +960,7 @@ gen_with_wr_phy:  if g_with_wr_phy generate
   cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';
 
 
-    --  --  --  --  --  --
+  --  --  --  --  --  --
   sfp_tx_disable_o <= '0';
   -- dac_clr_n_o   <= '1';
 
diff --git a/hdl/top/svec/synthesis_descriptor.vhd b/hdl/top/svec/synthesis_descriptor.vhd
index 13b68c29369d2ae035bb62eba969e3ea98368c21..1e070dc8da0a3de3dcfde8373ac18fdb76fafebb 100644
--- a/hdl/top/svec/synthesis_descriptor.vhd
+++ b/hdl/top/svec/synthesis_descriptor.vhd
@@ -6,7 +6,7 @@
 -- Author     : Evangelia Gousiou
 -- Company    : CERN
 -- Created    : 2013-04-16
--- Last update: 2015-04-08
+-- Last update: 2015-05-27
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -46,12 +46,12 @@ constant c_sdb_synthesis_info : t_sdb_synthesis :=
     syn_commit_id => "5765c94d3f0b118adcc9bfea880aca75",
     syn_tool_name => "ISE     ",
     syn_tool_version => x"00000147",
-    syn_date => x"20150522",
+    syn_date => x"20150527",
     syn_username => "twlostow       ");
 
 constant c_sdb_repo_url : t_sdb_repo_url :=
   (
-    repo_url => "http://svn.ohwr.org/fmc-tdc                                    " 
+    repo_url => "git://ohwr.org/fmc-projects/fmc-tdc/fmc-tdc-1ns-5cha-gw.git    "
   );
 
 end package synthesis_descriptor;
diff --git a/hdl/top/svec/wr_svec_tdc.ucf b/hdl/top/svec/wr_svec_tdc.ucf
index 8e916aab13f79416114b25936487f7d201de6f56..50107a2ac151b227c1ba52d3182d10ced49f93df 100644
--- a/hdl/top/svec/wr_svec_tdc.ucf
+++ b/hdl/top/svec/wr_svec_tdc.ucf
@@ -661,29 +661,6 @@ TIMESPEC TS_gen_with_wr_phy_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "gen_with_wr_ph
 
 # PlanAhead Generated miscellaneous constraints 
 
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[1].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d0" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d1" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d2" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_i_d3" KEEP = "TRUE";
-NET "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[2].gen_output_pd_ddmtd.DMTD_FB/clk_in" KEEP = "TRUE";
-
-# PlanAhead Generated IO constraints 
-
 NET "tdc1_address_o[3]" SLEW = FAST;
 NET "tdc1_address_o[2]" SLEW = FAST;
 NET "tdc1_address_o[1]" SLEW = FAST;
@@ -748,3 +725,8 @@ NET "tdc2_data_bus_io[3]" SLEW = FAST;
 NET "tdc2_data_bus_io[2]" SLEW = FAST;
 NET "tdc2_data_bus_io[1]" SLEW = FAST;
 NET "tdc2_data_bus_io[0]" SLEW = FAST;
+
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
+INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
+
+TIMESPEC TS_skew_limit = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
\ No newline at end of file
diff --git a/hdl/top/svec/wr_svec_tdc.vhd b/hdl/top/svec/wr_svec_tdc.vhd
index 2735555c8a2cfe6ec241cbba52d1795119b69508..676506ecf0e0aee11b9c6bc88d765276ed00de1e 100644
--- a/hdl/top/svec/wr_svec_tdc.vhd
+++ b/hdl/top/svec/wr_svec_tdc.vhd
@@ -459,8 +459,8 @@ architecture rtl of wr_svec_tdc is
   signal tm_dac_wr_p                          : std_logic_vector(1 downto 0);
   -- White Rabbit PHY
   signal phy_tx_data, phy_rx_data             : std_logic_vector(7 downto 0);
-  signal phy_tx_k, phy_tx_disparity, phy_rx_k : std_logic;
-  signal phy_tx_enc_err, phy_rx_rbclk         : std_logic;
+  signal phy_tx_k,  phy_rx_k : std_logic_vector(0 downto 0);
+  signal phy_tx_enc_err, phy_rx_rbclk,phy_tx_disparity         : std_logic;
   signal phy_rx_enc_err, phy_rst, phy_loopen  : std_logic;
   signal phy_rx_bitslide                      : std_logic_vector(3 downto 0);
   -- White Rabbit serial DAC
@@ -667,17 +667,20 @@ begin
   --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
   U_WR_CORE : xwr_core
   generic map
-    (g_simulation                => f_bool2int(g_simulation),
+     (g_simulation                => f_bool2int(g_simulation),
      g_phys_uart                 => true,
      g_virtual_uart              => true,
      g_with_external_clock_input => false,
+     g_board_name                => "SVEC",
      g_aux_clks                  => 2,
      g_ep_rxbuf_size             => 1024,
-     g_dpram_initf               => "wrc.ram",
-     g_dpram_size                => 90112/4,
+     g_dpram_initf               => "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram",
+     g_dpram_size                => 131072/4,
      g_interface_mode            => PIPELINED,
      g_address_granularity       => BYTE,
-     g_softpll_enable_debugger   => false)
+     g_softpll_enable_debugger   => false,
+     g_pcs_16bit                 => false,
+     g_records_for_phy           => false)
   port map
     (clk_sys_i                   => clk_62m5_sys,
      clk_dmtd_i                  => clk_dmtd,
@@ -764,12 +767,12 @@ begin
      ch0_loopen_i       => '0',
      ch1_ref_clk_i      => clk_125m_pllref,
      ch1_tx_data_i      => phy_tx_data,
-     ch1_tx_k_i         => phy_tx_k,
+     ch1_tx_k_i         => phy_tx_k(0),
      ch1_tx_disparity_o => phy_tx_disparity,
      ch1_tx_enc_err_o   => phy_tx_enc_err,
      ch1_rx_data_o      => phy_rx_data,
      ch1_rx_rbclk_o     => phy_rx_rbclk,
-     ch1_rx_k_o         => phy_rx_k,
+     ch1_rx_k_o         => phy_rx_k(0),
      ch1_rx_enc_err_o   => phy_rx_enc_err,
      ch1_rx_bitslide_o  => phy_rx_bitslide,
      ch1_rst_i          => phy_rst,