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FMC-PROFINET
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Fix ERTEC reset circuit (Clock-Reset sheet)
#93
· opened
Jul 30, 2021
by
Grzegorz Daniluk
v2.0
critical
CLOSED
2
updated
Feb 21, 2024
fix missing ERTEC JTAG connections
0 of 2 tasks completed
#92
· opened
Jul 30, 2021
by
Grzegorz Daniluk
v2.0
critical
CLOSED
1
updated
Feb 21, 2024
[L7] create void opening in the Chassis polygon
#82
· opened
Mar 22, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
0
updated
May 06, 2021
Flash.SchDoc both flash chips have the same enable signals and DQ0..15, this will not work
#81
· opened
Mar 19, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Mar 19, 2021
Not enough reference planes in the board stack-up
#78
· opened
Mar 18, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
FMC connector: Use separate via for each power pin
#71
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 17, 2021
chassis to board gnd isolation
#70
· opened
Mar 18, 2021
by
Paul PERONNARD
critical
Layout Review V1.0
CLOSED
3
updated
May 11, 2021
Provide clean return path by providing each GND pin with its own via to GND plane
#69
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
May 16, 2021
Remove GND polygons from signal layers
#68
· opened
Mar 18, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
1
updated
Jun 03, 2021
RJ45 connector wrong pinout
#67
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
1
updated
Mar 19, 2021
Missing magnetics for RJ45 connectors
#66
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
Apr 12, 2021
Memories should be routed in a fly-by topology
#61
· opened
Mar 17, 2021
by
Grzegorz Daniluk
layout-v1.0
critical
CLOSED
2
updated
May 17, 2021
DC/DC layout issues
#60
· opened
Mar 17, 2021
by
Christos Gentsos
layout-v1.0
critical
Layout Review V1.0
CLOSED
3
updated
Jun 03, 2021
PCB: URL and OHL text missing
#51
· opened
Mar 16, 2021
by
Erik van der Bij
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
Frontpanel: shows XXXXX
#50
· opened
Mar 16, 2021
by
Erik van der Bij
layout-v1.0
critical
Layout Review V1.0
CLOSED
2
updated
May 17, 2021
Connect PGND to GND and the feedback networks to AGND for all TLV62130s
#49
· opened
Oct 26, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
0
updated
Nov 18, 2020
C2 capacitor voltage rating a bit marginal
#48
· opened
Oct 26, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
1
updated
Nov 27, 2020
PG signal pulled up to multiple power rails
#47
· opened
Oct 26, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
2
updated
Oct 27, 2020
FMC 1-wire temp. sensor needs to use Vadj for I/O
#44
· opened
Oct 26, 2020
by
Christos Gentsos
sch v1.0
critical
CLOSED
4
updated
Oct 28, 2020
Flash: this flash memory is declared obsolete, we should use another one
#33
· opened
Oct 20, 2020
by
Grzegorz Daniluk
sch v1.0
critical
CLOSED
1
updated
Nov 27, 2020
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