On-board JTAG chain
I don't think the JTAG chain can work as it is in EDA-04348-V1-0 schematics.
Jumper SW1 shorts FMC_TDI signal driven by the carrier and TDO signal driven by the ERTEC.
Also some pull-ups are needed on XTRST and XSRST signals. According to ERTEC 200P-2 manual:
XTRST
Recommended JTAG circuit: 10k pull-down default and 4k7 pull-up assembly option.
You should place a pull-down resistor (1k - 47k) on this signal on target side, although this is not JTAG conform. It ensures the on-chip debug logic is inactive when the debugger is not connected.
XSRST
There might be the need to place a pull-up (1k - 47k) on target side to avoid unintentional resets when the debugger is not connected and probably to strengthen the weak 47k pull-up in the debug cable.
Their suggestion for XTRST is indeed not JTAG conform, since most JTAG debug interfaces have open-drain drivers for reset pins, which can never drive them high (in particular the ones sold by ARM). But on the current version of the schematics, this pin is either pulled low by R55 or shorted to GND by SW2, thus rendering the JTAG interface unusable.
I would suggest to use two SPDT DIP switches instead of jumpers, so that FMC_TDO could either be driven by ERTEC TDO (ERTEC in carrier chain) or FMC_TDI (ERTEC bypassed), and XTRST could either be pulled up (JTAG debug allowed) or grounded (debug disabled).