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FMC PCIe Carrier PFC
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FMC PCIe Carrier PFC
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P3V3_GN4124 is floating
#26
· opened
Sep 21, 2010
by
Pablo Alvarez
bug
1
updated
Feb 12, 2019
24FC64-I/MC(IC28) is not decoupled
#25
· opened
Sep 21, 2010
by
Pablo Alvarez
bug
0
updated
Feb 12, 2019
Add LHC equipment name "CFFIB" on front-panel and PCB
#24
· opened
Oct 12, 2010
by
Erik van der Bij
feature
1
updated
Feb 12, 2019
BOM does not contain precise manufacturer references
#23
· opened
Oct 14, 2010
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
Take into account simplification hints from Gennum Field Application Engineer
#22
· opened
Oct 19, 2010
by
Erik van der Bij
feature
0
updated
Feb 12, 2019
Design out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.
#21
· opened
Nov 02, 2010
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
NUMONYX M25P128-VMF6G difficult to find
#20
· opened
Nov 02, 2010
by
Erik van der Bij
feature
1
updated
Feb 12, 2019
PCB copper planes not equal. Board may warp.
#19
· opened
Nov 08, 2010
by
Erik van der Bij
bug
1
updated
Feb 12, 2019
Serigraphy comment for SCANSTA112
#18
· opened
Nov 11, 2010
by
Projects
bug
0
updated
Feb 12, 2019
LCLK_MODE3 = '1' instead of '0'
#17
· opened
Nov 11, 2010
by
Projects
bug
0
updated
Feb 12, 2019
B3 of the PCIe edge connector should be connected to PRE_P12V_PCIe
#16
· opened
Nov 11, 2010
by
Projects
bug
0
updated
Feb 12, 2019
SPI chip select
#15
· opened
Nov 16, 2010
by
Pablo Alvarez
bug
0
updated
Feb 12, 2019
GN4124 EEPROM size
#14
· opened
Nov 16, 2010
by
Projects
bug
2
updated
Feb 12, 2019
SPI configuration resistor list
#13
· opened
Nov 16, 2010
by
Pablo Alvarez
bug
0
updated
Feb 12, 2019
P_WR_RDY0 and P_WR_RDY1 should be moved to bank 3
#11
· opened
Nov 19, 2010
by
Projects
bug
0
updated
Feb 12, 2019
GN4124 does not accept clipped sinewave as local clock reference
#10
· opened
Dec 03, 2010
by
Pablo Alvarez
bug
1
updated
Feb 12, 2019
choose a rear connector type
#9
· opened
Dec 06, 2010
by
Pablo Alvarez
bug
0
updated
Feb 12, 2019
Board needs cut-out at front for ease of installing FMC
#8
· opened
Dec 07, 2010
by
Erik van der Bij
bug
0
updated
Feb 12, 2019
TDO signal from FMC is connected to 2 FPGA pins.
#7
· opened
Dec 13, 2010
by
Projects
bug
0
updated
Feb 12, 2019
Update note about VADJ in schematics
#6
· opened
Dec 13, 2010
by
Projects
bug
0
updated
Feb 12, 2019
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