FMC PCIe Carrier PFC issueshttps://ohwr.org/project/fmc-pci-carrier/issues2019-02-12T08:40:19Zhttps://ohwr.org/project/fmc-pci-carrier/issues/1QDR pins qdr_a and qdr_d should be moved to improve timing.2019-02-12T08:40:19ZErik van der BijQDR pins qdr_a and qdr_d should be moved to improve timing.On Wed, 2011-05-04 at 12:14 +0200, alessandro.maggione@eurotel.it
wrote:
\> As you'd know we are working on the qdr memory on the fmc pcie
board.
\> I want to report you the qdr memory is working.
\> We had a lot of difficulties due to timing problems; these timing
\> problems are related to the qdr memory pin position: the qdr\_a and
\> qdr\_d signals are placed at two different sides of the device (top
\> left and bottom right).https://ohwr.org/project/fmc-pci-carrier/issues/2Use external termination resistor for QDR2019-02-12T08:40:19ZProjectsUse external termination resistor for QDRWe have difficulties on activating input terminations inside the fpga
(there is a xilinx answer record ar40818 about this) so maybe in the
next pcb would be easier put the termination resistance on the pcb even
for the clock signals: qdr\_k and qdr\_cq.https://ohwr.org/project/fmc-pci-carrier/issues/3QDRII VDDQ could be powered from 1V52019-02-12T08:40:19ZPablo AlvarezQDRII VDDQ could be powered from 1V5VDDQ could be power from 1V5. VDD must arrive before VDDQ. At present
VDD is not power at 1V8 because the 1V5 is generated from a linear
regulator connected to 1V8. Generating the 1V5 from a switching
regulator allow to respect the timing between VDD and VDDQ.https://ohwr.org/project/fmc-pci-carrier/issues/4Replace DS18B20U+ (1-wire thermo + ID) by MCP9801-M/MS2019-02-12T08:40:19ZProjectsReplace DS18B20U+ (1-wire thermo + ID) by MCP9801-M/MSWe don't need the unique ID feature of the DS18B20U+.
GN4124 EEPROM can be used to store board ID data if needed.
Note that GN4124 boot configuration stops when reading 0xFFFF.
Therefore user data can be stored after 0xFFFF
The ALERT pin of MCP9801-M/MS must be connected to the FPGA.
This is to generate the carrier over-heat interrupt.https://ohwr.org/project/fmc-pci-carrier/issues/5AD9516 PLL external clock connected improperly2019-02-12T08:40:20ZTomasz WlostowskiAD9516 PLL external clock connected improperlyTermination resistor R5 for LVDS pins CLK in AD9516 PLL should be after
the capacitors C5, C2.https://ohwr.org/project/fmc-pci-carrier/issues/6Update note about VADJ in schematics2019-02-12T08:40:20ZProjectsUpdate note about VADJ in schematicsThe note refers to 6k2 and 1k6 resistors that don't exist any more.https://ohwr.org/project/fmc-pci-carrier/issues/7TDO signal from FMC is connected to 2 FPGA pins.2019-02-12T08:40:20ZProjectsTDO signal from FMC is connected to 2 FPGA pins.TDO\_FROM\_FMC\_P1V8 is connected to FPGA pins R23 and M6.https://ohwr.org/project/fmc-pci-carrier/issues/8Board needs cut-out at front for ease of installing FMC2019-02-12T08:40:21ZErik van der BijBoard needs cut-out at front for ease of installing FMCThe board needs a cut-out at front for ease of installing FMC cards.
Without it, the PCIe front-panel should be removed for installing an FMC
card.
A prototype with a relatively large cutout has been made, including a
Gerber file for it. See attached file.
### Files
* [PFC3_Board_Shape.pdf](/uploads/b8a5c3be92307c34918032d7b51aefe6/PFC3_Board_Shape.pdf)https://ohwr.org/project/fmc-pci-carrier/issues/9choose a rear connector type2019-02-12T08:40:21ZPablo Alvarezchoose a rear connector typeAnalyze the use of the rear connector and chose a suitable type, for the
PFC and SPEC.
As alternative to eSata there are:
Sata II (3Gbit/s widely used in computers nowadays)
Sata III (6Gbit/s that could become the future standard in computers)
These are not so robust as eSata but for communication between neighbour
boards should be good enough.
For eSata it is hard to find cable shorter than 0.5m, whereas for Sata
it is possible to find 0.2m cables.https://ohwr.org/project/fmc-pci-carrier/issues/10GN4124 does not accept clipped sinewave as local clock reference2019-02-12T08:40:21ZPablo AlvarezGN4124 does not accept clipped sinewave as local clock referenceThe GN4124 does not seem to accept a clipped sinewave as reference.
Probably the voltage excursion provided by the oscillator is too low
(only 0.8Vpk-pk). This issue could be fixed with a CMOS/TTL oscillator
or by generating the local clock from the PCIe reference clock.https://ohwr.org/project/fmc-pci-carrier/issues/11P_WR_RDY0 and P_WR_RDY1 should be moved to bank 32019-02-12T08:40:21ZProjectsP_WR_RDY0 and P_WR_RDY1 should be moved to bank 3Control/status signals for DDS and PLL can be move away from bank 3 and
P\_WR\_RDY0/1 can be placed in the same bank as other GN4124 related
signals.
This will avoid Timing warning during FPGA routing.https://ohwr.org/project/fmc-pci-carrier/issues/13SPI configuration resistor list2019-02-12T08:40:22ZPablo AlvarezSPI configuration resistor listDescription
The default configuration should be changed to:
M1 and M0:
R268 off , R267 on, R60 on, R64 off
SPI\_Q
R274 mountedhttps://ohwr.org/project/fmc-pci-carrier/issues/14GN4124 EEPROM size2019-02-12T08:40:23ZProjectsGN4124 EEPROM sizeI2C EEPROM for GN4124 configuration must be smaller than 2Kb.
Internal address must be done on 8 bits max. -\> one I2C frame.https://ohwr.org/project/fmc-pci-carrier/issues/15SPI chip select2019-02-12T08:40:23ZPablo AlvarezSPI chip selectSPI\_CS should be connected to CSO\_B\_2. Now it is DDS\_SDIO that is
connected in its place. This signals should be swappedhttps://ohwr.org/project/fmc-pci-carrier/issues/16B3 of the PCIe edge connector should be connected to PRE_P12V_PCIe2019-02-12T08:40:23ZProjectsB3 of the PCIe edge connector should be connected to PRE_P12V_PCIehttps://ohwr.org/project/fmc-pci-carrier/issues/17LCLK_MODE3 = '1' instead of '0'2019-02-12T08:40:23ZProjectsLCLK_MODE3 = '1' instead of '0'Mount R190 and don't mount R183.https://ohwr.org/project/fmc-pci-carrier/issues/18Serigraphy comment for SCANSTA1122019-02-12T08:40:24ZProjectsSerigraphy comment for SCANSTA112Serigraphy is "SCANSTA112 bypassed if R116 is ON", should be "SCANSTA112
bypassed if R116 is OFF".https://ohwr.org/project/fmc-pci-carrier/issues/19PCB copper planes not equal. Board may warp.2019-02-12T08:40:24ZErik van der BijPCB copper planes not equal. Board may warp.As the copper planes of are not homogenous, the V1 version of the PCB
may warp. This may pose problems with the assembly. Verify if this
problem is serious enough to improve on a V2 version of the PCB.https://ohwr.org/project/fmc-pci-carrier/issues/20NUMONYX M25P128-VMF6G difficult to find2019-02-12T08:40:24ZErik van der BijNUMONYX M25P128-VMF6G difficult to findThe NUMONYX M25P128-VMF6G memory is hard to purchase. Find alternative
and update design files.Pablo AlvarezPablo Alvarezhttps://ohwr.org/project/fmc-pci-carrier/issues/21Design out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.2019-02-12T08:40:25ZErik van der BijDesign out RAKON IVT3205CR 25.0 MHz as too difficult to obtain.Find replacement for Rakon oscillator and update design.Pablo AlvarezPablo Alvarez