- Wherever possible place inputs coming from the left side, outputs going to the right side.
- Add wires for pins that have only a net label (so it is clear that they are connected).
* Discuss with the users possibility of disabling the standalone interface, it will free up a lot of FMC pins.
Accepted by QPS and Survey groups. Standalone mode is disabled, a number
of FPGA GPIO pins have been connected to the FMC
* There is an idea to develop nanoFIP gateware with serial (SPI?) interface instead of Wishbone/standalone.
Still in planning.
- Check Microsemi note about RC termination for the clock signal.
RC termination recommended by Microsemi AN
[Clock Network] applies to oscillators with high edge rate. With the
the rise and fall time values of 10 ns, the oscillator and the
connecting copper are considered a lumped circuit for connection lengths
below 26 cm (as described by "High-Speed Digital Design: the Handbook of
Black Magic", Eq 1.4). Since it is a very likely case, the RC
termination is not necessary. Other designs built on the same component
set have been proven to work correctly without the RC
JTAG, power, LEDs
+ Add a jumper shorting FPGA_TDI and FPGA_TDO to bypass the FPGA TAP in the FMC JTAG daisy-chain.
+ Use one-shot trigger circuit with BC817 and a single NOT gate instead of NMOS/PMOS. Use the same type of NOT gate to invert one of the signals. If it is confirmed that there will be a new gateware revision, then drive the LEDs directly from the nanoFIP FPGA.
Done, LEDs can be optionally driven by the FPGA (selectable by soldering
+ Add a diode for the power-on-reset circuit (see FGClite). Add a note about the RC constant.
- Add a note explaining pull-downs on the JTAG connector.
- Check Microsemi note about capacitors for VJTAG and VPUMP.
Microsemi ProASIC3E FPGA Fabric User
Guide suggests 10 nF and
330 nF for VPUMP, there no recommendations for VJTAG decoupling
capacitors. VPUMP capacitors have been changed to 470 nF and 10 nF (470
nF is used in place of 330 nF to keep the parts count
- Check whether it is necessary to connect Vpump to the JTAG connector (pin 7).
(Table 4 notes) says the voltage is provided by FlashPro4/3/3x
programmer if there is only one device on the target board, which is the
! Missing connection on pin 8 of IC2.
* Check if LHC4913 comes in a different package, consider using it.
Contacted Philippe Farthouat, who wrote that STM manufactures
which is electrically identical and qualified for space applications,
but comes at much higher price. LHC4913 in its original package cannot
be used to board space scarcity, therefore the design kept TPS749A which
- Move the substation address pull-ups references so they do not touch the resistor boxes.
! *GND on the DB9 connector is not connected.*
+ Add resistors to enable FielDrive test modes (not mounted by default).
FMC connector (LPC)
- Unique ID reading works correctly in DS18B20U under radiation. Temperature readings are incorrect at times, but this can be fixed in software. Consider mounting the IC by default.
As the part does not behave fully correctly under radiation, it is not
mounted by default but there is a footprint left to mount it. The user
has to be aware of the potential problems and explicitly request the
part to be mounted.
Changes requested after the review (implemented)
Connect hardware revision pins both to FMC and FPGA, so they might
be used as GPIOs if necessary