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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:05:16 02/21/2014 
-- Design Name: 
-- Module Name:    Gauss_Gen1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.math_real.all;
  use IEEE.std_logic_unsigned.ALL;
  use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;

 entity Gauss_Gen1 is
  generic(nn:natural:=1; --power of the binomial distribution <16
  m:REAL:=0.0	 -- mean output value
	);
   port(
	CLK : in STD_LOGIC;
	RST : in STD_LOGIC;
	RAISE_X  : out std_logic
	);
   end Gauss_Gen1;
	
 architecture Model of Gauss_Gen1 is
     	type arri is array (0 to 15) of integer;
      	type arrr is array (0 to 15) of real;
			signal temporal:STD_LOGIC;
         signal counter : real range 0.0 to 2.0 := 0.0;
			signal DATA_OUT1: real := 0.0;
			signal DATA_OUT2: real :=0.0;
			signal reg_clk1: real :=0.0;
			signal reg_clk2: real :=0.0;
			signal clk_out : std_logic;

 begin
 SFR:process(clk,rst)
  variable s1:arri:=(3,33,333,3,4,5,6,7,8,9,11,22,33,others=>11);
  variable s2:arri:=(5,55,555,50,6,7,8,9,5,6,7,21,33,others=>22);
  variable r:arrr:=(others=>0.0);
  variable s:real:=0.0;
  variable mu:real:=1.0;
  variable sigma:real:=1.0;
  variable tempdiv:REAL:= 0.0;
  variable tempdiv1:REAL:= 0.0;
  variable s3:real:=0.0;
  constant max_div:REAL:= 4.0 * sigma;

      	begin 
           if rst='1' then
				  DATA_OUT1 <= 0.0;
				  DATA_OUT2 <= 0.0;
				  temporal <= '0';
              counter <= 0.0;
				  RAISE_X <= '0';
				  elsif  clk='1' and clk'event then
 		s:=0.0;
 ----------- for Gaussian Distribution ---------------------     
 
			for i in 0 to nn-1 loop    -- nn noise generators
                   UNIFORM (s1(i),s2(i),r(i));
                   s:=r(i)*r(i);
						 tempdiv := sigma * r(i) * sqrt(-2.0 * log(s)/s);
       	end loop; 
			
			if (tempdiv > max_div) then 
			DATA_OUT1 <= mu + max_div;
			elsif (tempdiv < - max_div) then
			DATA_OUT1 <= mu - max_div;
			else
			DATA_OUT1 <= mu + tempdiv;
			end if;
			
------------ for Poisson distribution----------------------	
	
			for j in 0 to nn-1 loop    									-- nn noise generators
                   UNIFORM (s1(j),s2(j),r(j));
                   s3:=r(j);
						 tempdiv1 := -log(s3)/mu;
       	end loop;  
			          DATA_OUT2 <= tempdiv1;
						 
	------------- for the clock divider circuit -------------
	
			if (counter = 2.0) then    
         --temporal <= NOT(temporal);
         counter <= 0.0;
         else
         counter <= counter + 1.0; 
         end if;
			    
      
		  --clk_out <= temporal;
		
		--------------------------------------------------------
		
		reg_clk1 <= counter - DATA_OUT2;
		reg_clk2 <= counter - DATA_OUT1;
		
		if (reg_clk1 > 1.0)then
		RAISE_X <= '1';
		else
		RAISE_X <= '0';
		end if;
		end if;
		end process;  
		
  end Model;