Reduced size of figures and uniformed their size. Minor tidying up in first chapters

d8cf419c · Paolo Baesso · 83377c72 · d8cf419c · d8cf419c · d8cf419c
Commit d8cf419c authored Apr 16, 2019 by Paolo Baesso
10 changed files
--- a/Documentation/Images/View1r.png
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--- a/Documentation/Images/View2r.png
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--- a/Documentation/Images/View2rr.png
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--- a/Documentation/Images/View3r.png
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--- a/Documentation/Images/View4r.png
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--- a/Documentation/Images/View5r.png
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--- a/Documentation/Images/View6r.png
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--- a/Documentation/Main_TLU.pdf
+++ b/Documentation/Main_TLU.pdf
--- a/Documentation/ch_TLU_Hardware.tex
+++ b/Documentation/ch_TLU_Hardware.tex
@@ -51,7 +51,7 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
 In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
 \subsubsection{SFP cage}
-\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the Si5345 to provide a clock reference.
+\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream or to issue timing signals over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the on-board clock chip to be used as a clock reference.
 \section{Clock LEMO}
 The board hosts a two-pin LEMO connector that can be used to provide a reference clock to the clock generator (see section~\ref{ch:clock}) or to output the clock from the \gls{tlu} to the external world, for instance to use it as a reference for another \gls{tlu}. The signal level is 3.3~V \gls{lvds}.\\

--- a/Documentation/ch_TLU_Preparation.tex
+++ b/Documentation/ch_TLU_Preparation.tex