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AIDA-2020 TLU
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Documentation/Glossary/AIDAGlossary.tex
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......@@ -40,7 +40,8 @@
\newacronym{ide}{IDE}{Integrated Development Environment}
\newacronym{ifd}{IFD}{Image File Directory}
\newacronym{ir}{IR}{Infra-red}
\newacronym{ipbus}{IPBus}{Software and firmware that provide a reliable high-performance control link for particle physics electronics, by implementing a simple A32/D32 control protocol for reading and modifying memory-mapped resources within FPGA-based hardware devices. See \url{https://ipbus.web.cern.ch/}}
%\newacronym{ipbus}{IPBus}{Software and firmware that provide a reliable high-performance control link for particle physics electronics, by implementing a simple A32/D32 control protocol for reading and modifying memory-mapped resources within FPGA-based hardware devices. See \url{https://ipbus.web.cern.ch/}}
\newacronym{ipbus}{IPBus}{IPBus}
% J
\newacronym{jtag}{JTAG}{Joint Test Action Group}
......
Documentation/Main_TLU.tex
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......@@ -21,7 +21,7 @@
\usepackage{sidecap} %caption on side of figure. Needed for AIDA-2020 acknowledgment
%\usepackage[hidelinks]{hyperref}
%\usepackage{xcolor}
\usepackage{longtable} % multi-page tables
\usepackage{subcaption}
\usepackage{pdflscape} %Landscape pages
\usepackage{pdfpages} %Insert pdf in document
......@@ -125,7 +125,7 @@
}
\makeatother
\author{Paolo Baesso\\David Cussans}
\title{AIDA Trigger logic unit (TLU v1E)}
\title{AIDA Trigger logic unit (TLU v1E-F)}
\date{\today}
\loadglsentries{./Glossary/AIDAGlossary.tex}
%\makeglossaries
......
Documentation/ch_TLU_IPBusRegs.tex
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\chapter{IPBus Registers}\label{ch:ipbusregs}
%
%\begin{table}[]
%\centering
%\caption{My caption}
%\label{my-label}
%\begin{tabular}{|l|l|r|l|l|l|l|l|}
%\hline
%\textbf{NODE} & \textbf{SUBNODE} & \multicolumn{1}{l|}{\textbf{ADDRESS}} & \textbf{MASK} & \textbf{PERMISSION} & \textbf{DESCRIPTION} & \textbf{MODE} & \textbf{SIZE} \\ \hline
%ID & TLU & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{version} & & 0x1 & & r & firmware version & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{DUTInterfaces} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x1000}} & \textbf{} & \textbf{} & \textbf{DUT Interfaces control registers} & \textbf{} & \textbf{} \\
% & DUTMaskW & 0x0 & & w & & & \\
% & IgnoreDUTBusyW & 0x1 & & w & & & \\
% & IgnoreShutterVetoW & 0x2 & & w & & & \\
% & DUTInterfaceModeW & 0x3 & & w & & & \\
% & DUTInterfaceModeModifierW & 0x4 & & w & & & \\
% & DUTInterfaceModeR & 0xB & & r & & & \\
% & DUTInterfaceModeModifierR & 0xC & & r & & & \\
% & DUTMaskR & 0x8 & & r & & & \\
% & IgnoreDUTBusyR & 0x9 & & r & & & \\
% & IgnoreShutterVetoR & 0xA & & r & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{Shutter} & & \multicolumn{1}{l|}{\textbf{0x2000}} & \textbf{} & \textbf{} & \textbf{Shutter/T0 control} & \textbf{} & \\
% & ShutterStateW & 0x0 & & w & & & \\
% & PulseT0 & 0x1 & & w & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{i2c\_master} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x3000}} & \textbf{} & \textbf{} & \textbf{I2C Master interface} & \textbf{} & \textbf{} \\
% & i2c\_pre\_lo & 0x0 & 0xFF & r/w & & & \\
% & i2c\_pre\_hi & 0x1 & 0xFF & r/w & & & \\
% & i2c\_ctrl & 0x2 & 0xFF & r/w & & & \\
% & i2c\_rxtx & 0x3 & 0xFF & r/w & & & \\
% & i2c\_cmdstatus & 0x4 & 0xFF & r/w & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{eventBuffer} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x4000}} & \textbf{} & \textbf{} & \textbf{Event buffer} & \textbf{} & \textbf{} \\
% & EventFifoData & 0x0 & & r & & non-incremental & 3200 \\
% & EventFifoFillLevel & 0x1 & & r & & & \\
% & EventFifoCSR & 0x2 & & r/w & & & \\
% & EventFifoFillLevelFlags & 0x3 & & r & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{Event\_Formatter} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x5000}} & \textbf{} & \textbf{} & \textbf{Event formatter configuration} & \textbf{} & \textbf{} \\
% & Enable\_Record\_Data & 0x0 & & r/w & & & \\
% & ResetTimestampW & 0x1 & & w & & & \\
% & CurrentTimestampLR & 0x2 & & r & & & \\
% & CurrentTimestampHR & 0x3 & & r & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{triggerInputs} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x6000}} & \textbf{} & \textbf{} & \textbf{Inputs configuration} & \textbf{} & \textbf{} \\
% & SerdesRstW & 0x0 & & w & & & \\
% & SerdesRstR & 0x8 & & r & & & \\
% & ThrCount0R & 0x9 & & r & & & \\
% & ThrCount1R & 0xA & & r & & & \\
% & ThrCount2R & 0xB & & r & & & \\
% & ThrCount3R & 0xC & & r & & & \\
% & ThrCount4R & 0xD & & r & & & \\
% & ThrCount5R & 0xE & & r & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{triggerLogic} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x7000}} & \textbf{} & \textbf{} & \textbf{Trigger logic configuration} & \textbf{} & \textbf{} \\
% & PostVetoTriggersR & 0x10 & & r & & & \\
% & PreVetoTriggersR & 0x11 & & r & & & \\
% & InternalTriggerIntervalW & 0x02 & & w & & & \\
% & InternalTriggerIntervalR & 0x12 & & r & & & \\
% & TriggerVetoW & 0x04 & & w & & & \\
% & TriggerVetoR & 0x14 & & r & & & \\
% & ExternalTriggerVetoR & 0x15 & & r & & & \\
% & PulseStretchW & 0x06 & & w & & & \\
% & PulseStretchR & 0x16 & & r & & & \\
% & PulseDelayW & 0x07 & & w & & & \\
% & PulseDelayR & 0x17 & & r & & & \\
% & TriggerHoldOffW & 0x08 & & w & & & \\
% & TriggerHoldOffR & 0x18 & & r & & & \\
% & AuxTriggerCountR & 0x19 & & r & & & \\
% & TriggerPattern\_lowW & 0x0A & & w & & & \\
% & TriggerPattern\_lowR & 0x1A & & r & & & \\
% & TriggerPattern\_highW & 0x0B & & w & & & \\
% & TriggerPattern\_highR & 0x1B & & r & & & \\
% & & \multicolumn{1}{l|}{} & & & & & \\ \hline
%\textbf{logic\_clocks} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x8000}} & \textbf{} & \textbf{} & \textbf{Clocks configuration} & \textbf{} & \textbf{} \\
% & LogicClocksCSR & 0x0 & & r/w & & & \\
% & LogicRst & 0x1 & & w & & & \\ \hline
%\end{tabular}
%\end{table}
\begin{table}
\centering
\footnotesize
\caption{IPBus register}
\label{tab:ipbusreg}
\begin{scriptsize}
\begin{tabular}{|l|l|r|l|l|}
%\begin{longtable}{|l|l|r|l|l|}
\hline
\textbf{NODE} & \textbf{SUBNODE} & \multicolumn{1}{l|}{\textbf{ADDRESS}} & \textbf{MASK} & \textbf{PERMISSION} \\ \hline
\textbf{version} & & 0x1 & & r \\ \hline
......@@ -127,7 +48,7 @@
& CurrentTimestampHR & 0x3 & & r \\ \hline
\textbf{triggerInputs} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x6000}} & \textbf{} & \textbf{} \\
& SerdesRstW & 0x0 & & w \\
& InvertEdgeW & 0x1 & w \\
& InvertEdgeW & 0x1 & & w \\
& SerdesRstR & 0x8 & & r \\
& ThrCount0R & 0x9 & & r \\
& ThrCount1R & 0xA & & r \\
......@@ -158,6 +79,8 @@
& LogicClocksCSR & 0x0 & & r/w \\
& LogicRst & 0x1 & & w \\ \hline
\end{tabular}
\end{scriptsize}
%\end{longtable}
\end{table}
\begin{description}\label{ch:IPBus_DUT}
......
Documentation/ch_TLU_Preparation.tex
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......@@ -36,7 +36,7 @@ When used for within AIDA-2020 specifications, the hardware generates a low-jitt
The \gls{tlu} accepts asynchronous trigger signals from up to six external sources, such as beam-scintillators, and generate synchronous signals (including global trigger or control signals) to send to up to four \gls{dut}. The logic function used to generate the trigger can be defined by the user among all the possible logic combinations of the inputs.\\
Depending on the chosen mode of operation, the \gls{tlu} can accept busy signals or other veto signals from \gls{dut}s and react accordingly, for instance avoiding any further trigger until all the busy signals have been de-asserted.\\
Whenever a global trigger is generated by the unit, a 48-bit coarse time-stamp is attached to it. This time stamp is based on the internal 40~MHz clock. The unit also records a fine-grain time stamp with 1.56~ns resolution for each signal involved in the trigger decision.\\
The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus} which provides a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.\\
The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus} protocol which provides a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.\\
The \gls{tlu} is shipped with an \gls{fpga} board already programmed with the latest version of the firmware needed to operate the unit. New features and bug fixes are continuously being implemented by the developing team and it is possible to flash the unit with a new firmware as described in section~\ref{ch:flashFPGA}.\\
The internal electronics of the \gls{tlu} require 12~V to operate and will dissipate about 12 W during normal operation.\\
Power should be provided using the socket located on the back panel. See section~\ref{ch:backpanelintro} and \ref{ch:rackmountpanel} for details on compatible connectors.\\
......
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