In the old versions of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hwDUT} for further details. \\
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\chapter{DUT Signals}\label{ch:DUTsignals}
In the older, EUDET, version of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has the ability to switch each LVDS pair between input and output. The function and direction of each LVDS pair depends on the interface mode chosen. Table \ref{tab:DUTInterfaceModes} lists the different interface modes and section~\ref{sec:InterfaceModes} describes them in more detail. See chapter~\ref{ch:hwDUT} for details of how LVDS pairs are mapped onto physical \gls{hdmi} pins.
%separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hw\gls{dut}} for further details. \\
There are four different handshake modes, described below:
\subsection{Trigger/Busy (EUDET) Mode}
This mode is designed to allow the \gls{tlu} and \gls{dut} clocks to be asynchronous and to have any frequency relationship. After the \gls{tlu} detects an input trigger the TRIGGER signal to the \gls{dut} is asserted and the \gls{tlu} vetoes further triggers. The \gls{dut} responds by asserting the BUSY line to the \gls{tlu}. The \gls{tlu} detects that the BUSY line has been asserted and responds by de-asserting the trigger line. Finally the \gls{dut} responds by de-asserting the BUSY line. When the \gls{tlu} detects that the BUSY has been de-asserted it re-enables triggers. Figure \ref{fig:eudet-trigger-busy} shows signal timing for this interface mode.
\subsection{Trigger/Busy Handshake With Trigger Number}
This interface mode is an extension of the Trigger/Busy handshake. After the \gls{dut} detects that the \gls{tlu} has de-asserted the TRIGGER line it can cause the \gls{tlu} to clock out the current trigger number by toggling the DUT-Clock line. Figure ~\ref{fig:eudet-trigger-busy-trignumber} shows the signal timing for this interface mode.
\caption{Trigger/Busy Interface Mode With Trigger Number }
\label{fig:eudet-trigger-busy-trignumber}
\end{figure}
\subsection{Synchronous (AIDA) Mode}
In synchronous mode (also known as AIDA mode) the \gls{tlu} sends a clock (by default 40MHz) to the \gls{dut}. When the \gls{tlu} produces a trigger the trigger line from \gls{tlu} to \gls{dut} is asserted for one cycle of the clock. In order to synchronize time-stamps between \gls{tlu} to \gls{dut} a single cycle timestamp reset signal is issued at the start of each run. The \gls{dut} can veto triggers at any point by asserting the BUSY line. Figure~\ref{fig:aida-handshake} shows the signal timing for this interface mode.
This is a modification of the synchronous/AIDA mode. Immediately after the TLU issues a trigger it clocks out the trigger number (least significant bit first) on the Sync/T0 line. Figure~\ref{fig:aida-handshake-with-trigger} shows the signal timing for this interface mode.
An optional ``shutter'' can be enabled. When the shutter is ``closed'' triggers are vetoed and no triggers are sent. When the shutter is ``open'' triggers can be generated and sent to active DUTs.
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@@ -11,8 +11,8 @@ Figure \ref{fig:shutter_timing} illustrates the timing of the shutter. Behaviour
\begin{table}
\begin{tabular}{lp{\0.6\linewidth}}
Register Name & Function \\\hline
ControlRW & Bit-0 controls if shutter pulses are active. 1 = active. Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
ShutterSelectRW & Selects which input is used to trigger shutter sequence.range = 0-5)\\
ControlRW & Bit-0 controls if shutter pulses are active. (bit-0 = 1). Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
ShutterSelectRW & Selects which input is used to trigger shutter sequence.()range = 0-5)\\
InternalShutterPeriodRW & Internal sequence period (when using internal sequence). Units of clock cycles.\\
ShutterOnTimeRW & Time between start of sequence and shutter asserted( t1) \\
ShutterVetoOffTimeRW & time between start of sequence and veto being de-asserted (t2)\\
@@ -13,7 +13,8 @@ The connectors operate with 3.3~V \gls{lvds} signals and are bi-directional, i.e
The input part of the transceiver is configured to be always on. This means that signals going \emph{into} the \gls{tlu} are always routed to the logic (\gls{fpga}). By contrast, the output transceivers have to be enabled and are off by default: signal sent from the logic to the \gls{dut}s cannot reach the devices unless the corresponding enable signal is active.
\end{alertinfo}
Table~\ref{tab:HDMIpins} shows the pin naming and the corresponding output enable signal. The clock pairs have two different enable signals to select the clock source (see section~\ref{ch:clock} for more details). In general only one of the clock sources should be active at any time.\\
The enable signals can be configured by programming two \gls{gpio} bus expanders via \gls{i2c} interface as described in section~\ref{ch:i2c}.
The enable signals can be configured by programming two \gls{gpio} bus expanders via \gls{i2c} interface as described in section~\ref{ch:i2c}. Figure \ref{fig:hdmi-pins} illustrates the position of each pin within the \gls{hdmi} connector.
\begin{table}[]
\centering
\caption{HDMI pin connections.}
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@@ -43,11 +44,20 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
\caption{Internal configuration of the HDMI pins for the DUTs. The path from the DUT to the FPGA is always active. The path from the FPGA to the DUT can be enabled or disabled by the user.}\label{fig:LVDSTransceiver}
\end{figure}\\
\end{figure}
In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
The six inputs on the \gls{tlu} can be used to generate a global trigger that is then issued to all the \gls{dut}s.\\
Each input has a programmable voltage discriminator that can be configured in the range [-1.3 : 1.3]~V.\\
All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V.
All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V. The discriminators are followed by edge-finding and TDC logic. The output of the edge finding logic is fed into logic to stretch and delay the pulses by a controllable amount. The stretched and delayed trigger pulses are fed into a look-up table that generates the triggers. Figure~\ref{fig:aida-tlu-trigger-path} illustrates the path of the trigger signals through the TLU.
The TLU has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6=64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words (indicated as \gls{msb} and \gls{lsb} word) and the rules to generate the trigger can be specified by the user by writing in the two 32-bit registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
