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AIDA-2020 TLU
Commit cc369c2a authored by David Cussans's avatar David Cussans
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-cAdded david cussans as an author. Added edge select and shutter control… 

-cAdded david cussans as an author. Added edge select and shutter control registers. Added ipbus to glossary
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Documentation/Glossary/AIDAGlossary.tex
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......@@ -40,6 +40,7 @@
\newacronym{ide}{IDE}{Integrated Development Environment}
\newacronym{ifd}{IFD}{Image File Directory}
\newacronym{ir}{IR}{Infra-red}
\newacronym{ipbus}{IPBus}{Software and firmware that provide a reliable high-performance control link for particle physics electronics, by implementing a simple A32/D32 control protocol for reading and modifying memory-mapped resources within FPGA-based hardware devices. See \url{https://ipbus.web.cern.ch/}}
% J
\newacronym{jtag}{JTAG}{Joint Test Action Group}
......
Documentation/Main_TLU.tex
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......@@ -124,7 +124,7 @@
\cleardoublepage
}
\makeatother
\author{Paolo Baesso}
\author{Paolo Baesso\\David Cussans}
\title{AIDA Trigger logic unit (TLU v1E)}
\date{\today}
\loadglsentries{./Glossary/AIDAGlossary.tex}
......@@ -135,8 +135,9 @@
\makeindex
\begin{document}
\def\brd{FMC\_TLU\_v1E }
\def\oldbrd{FMC\_TLU\_v1C }
\def\brd{FMC\_TLU\_v1F }
\def\oldbrd{FMC\_TLU\_v1E }
\def\oldoldbrd{FMC\_TLU\_v1C }
\let\cleardoublepage\clearpage
......@@ -146,15 +147,15 @@
\null\vfill
\begin{flushleft}
\textit{Documentation for \brd.}\newline
\textit{Documentation for \oldbrd and \brd.}\newline
\newline
Paolo Baesso - \monthname, \the\year
\newline paolo.baesso@bristol.ac.uk
Paolo Baesso, David Cussans - \monthname, \the\year
\newline david.cussans@bristol.ac.uk
\newline
\newline An up-to-date version of this document can be found at:
\newline \href{https://ohwr.org/project/fmc-mtlu}{https://ohwr.org/project/fmc-mtlu}
\newline
\newline Please report any error or omission to the author.
\newline Please report any errors or omissions to the authors.
\bigskip
\end{flushleft}
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Documentation/ch_TLU_IPBusRegs.tex
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......@@ -102,8 +102,13 @@
& IgnoreDUTBusyR & 0x9 & & r \\
& IgnoreShutterVetoR & 0xA & & r \\ \hline
\textbf{Shutter} & & \multicolumn{1}{l|}{\textbf{0x2000}} & \textbf{} & \textbf{} \\
& ShutterStateW & 0x0 & & w \\
& PulseT0 & 0x1 & & w \\ \hline
& ControlRW & 0x0 & & rw \\
& ShutterSelectRW & 0x1 & & rw \\
& InternalShutterPeriodRW & 0x2 & & rw \\
& ShutterOnTimeRW & 0x3 & & rw \\
& ShutterVetoOffTimeRW & 0x4 & & rw \\
& ShutterOffTimeRW & 0x5 & & rw \\
& RunActiveRW & 0x6 & & rw \\ \hline
\textbf{i2c\_master} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x3000}} & \textbf{} & \textbf{} \\
& i2c\_pre\_lo & 0x0 & 0xFF & r/w \\
& i2c\_pre\_hi & 0x1 & 0xFF & r/w \\
......@@ -122,6 +127,7 @@
& CurrentTimestampHR & 0x3 & & r \\ \hline
\textbf{triggerInputs} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x6000}} & \textbf{} & \textbf{} \\
& SerdesRstW & 0x0 & & w \\
& InvertEdgeW & 0x1 & w \\
& SerdesRstR & 0x8 & & r \\
& ThrCount0R & 0x9 & & r \\
& ThrCount1R & 0xA & & r \\
......@@ -177,9 +183,15 @@
\begin{description}
\item[------------------------]
\item[SHUTTER]
\item[ShutterStateW] The \gls{lsb} of this register is propagated to the \gls{dut}s as shutter signal. This is the signal that the \gls{dut}s receive on the \verb|cont| line.
\item[PulseT0] Writing to this register will cause the firmware to generate a T0 signal.
\item[SHUTTER]These registers control the signal that the \gls{dut}s receive on the \verb|cont| line. A shutter on/off (active/inactive) signal can either be produced from an internal timer or triggered from one of the trigger inputs (N.B. Any trigger input used to control the shutter will still be connected to the trigger logic. Set the trigger mask accordingly)
\item[ControlRW] The \gls{lsb} of this register controls if shutter pulses are active. 1 = active.
\item[ControlRW] Bit-0 controls if shutter pulses are active. 1 = active
\item[ShutterSelectRW] Selects which input is used to trigger shutter
\item[InternalShutterPeriodRW] Internal trig generator period ( units = number of strobe pulses)
\item[ShutterOnTimeRW] Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)
\item[ShutterVetoOffTimeRW] time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)
\item[ShutterOffTimeRW] time between input trigger and time at which shutter de-asserted and veto reasserted(T3) ( units = number of strobe pulses)
\item[RunActiveRW] Writing '1' to Bit-0 of this register raises the internal run\_active signal and and causes sync line to pulse for one clock cycle (i.e. issues a start of run T0 signal.
\end{description}
\begin{description}
......@@ -227,6 +239,7 @@
\item bit 1: set this bit to reset the input trigger counters
\item bit 2: \verb|s_calibrate_delay|
\end{itemize}
\item[InvertEdgeW] Bottom 6 bits control what counts as leading edge of pulse. Set bit to 0 to trigger on low voltage to high voltage (e.g. TTL pulses). Set bit to 1 to trigger on high voltage to low voltage (e.g. NIM pulses, PMT pulses)
\item[SerdesRstR] Read register for the SerDes control.
\item[ThrCount0R] Read register. Returns the number of pulses above threshold for the trigger input.
\item[ThrCount1R] Read register. Returns the number of pulses above threshold for the trigger input.
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Documentation/ch_TLU_triggerInputs.tex
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......@@ -182,7 +182,7 @@ We can now define the trigger logic to be used to assert a valid trigger: we onl
\end{itemize}
\section{Stretch and delay}
The trigger logic is designed to detect edge transitions at the trigger inputs and produce a pulse for each transition detected.\\
The trigger logic is designed to detect edge transitions\footnote{By default transitions from low voltage to high voltage are detected (e.g. the leading edge of TTL pulses). The bottom 6 bits of \gls{ipbus} register InvertEdgeW can be used to select triggering on high voltage to low voltage transitions (e.g. NIM pulses, PMT pulses)} at the trigger inputs and produce a pulse for each transition detected.\\
The pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
Each pulse can be stretched and delayed in integer numbers of clock cycles (25~ns by default) to compensate for differences in cable length. Two separate 5-bit registers are used for the task: the value written in the registers will stretch/delay the pulse by a corresponding number of clock cycles.\\
Diagram~\ref{Fig:trigger_stretchdelay} shows the effect of the delay and stretch words on the trigger logic.
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