Commit a34cf55f authored by David Cussans's avatar David Cussans

Merge branch 'master' of ssh://ohwr.org:7999/project/fmc-mtlu

parents f5024dde c7846bc1
......@@ -151,6 +151,9 @@
Paolo Baesso - \monthname, \the\year
\newline paolo.baesso@bristol.ac.uk
\newline
\newline An up-to-date version of this document can be found at:
\newline \href{https://ohwr.org/project/fmc-mtlu}{https://ohwr.org/project/fmc-mtlu}
\newline
\newline Please report any error or omission to the author.
\bigskip
......
......@@ -41,7 +41,7 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[CLOCK\_CFG\_FILE] \verb|[string, "./../user/eudet/misc/fmctlu_clock_config.txt"]| Name of the text file used to store the configuration values of the Si5345. The file can be generate using the Clockbuilder Pro software provided by \href{https://www.silabs.com/products/development-tools/software/clock}{SiLabs}.
\end{description}
\section{CONF file}
\section{CONF file}\label{ch:configFile}
\begin{description}
\item[confid] \verb|[string, "0"]| Does not serve any purpose in the code but can be useful to identify configuration settings used in a specific run. EUDAQ will store this information in the run data.
\item[verbose] \verb|[int, 0]| Defines the level of output messages from the \gls{tlu}. 0= only errors (minimum), 1= warning (default), 2= info, 3= all.
......@@ -75,9 +75,13 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[in1\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 1.
\item[in1\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in2\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 2.
\item[in2\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in2\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 2.
\item[in3\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 3.
\item[in3\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in3\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 3.
\item[in4\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 4.
\item[in4\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 4.
\item[in5\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 5.
\item[in5\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 5.
\item[trigMaskHi] \verb|[unsigned int32, 0]| This word represents the most significative bits of the 64-bits used to determine the trigger mask.\\
A detailed explanation of how to determine the correct word is provided in section~\ref{ch:triggerLogic}.
\item[trigMaskLo] \verb|[unsigned int32, 0]| This word represents the least significative bits of the 64-bits used to determine the trigger mask.\\
......@@ -92,4 +96,10 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[DUTIgnoreShutterVeto] \verb|[unsigned int, 0x1]| Set bit to 1 to tell the \gls{dut} to ignore the shutter signal.
\item[EnableRecordData] \verb|[boolean, true]| if set to 1, enable the data recording in the \gls{tlu}.
\item[InternalTriggerFreq] \verb|[unsigned int, 0]| Defines the rate of the trigger generated internally by the \gls{tlu}, in Hz: if 0, the internal triggers are disabled. Any other value activates the internal trigger generator with frequency equal to the parameter. Values above 160~MHz are coerced to 160~MHz.
\item[EnableShutterMode] \verb|[unsigned int, 0]| If set to 1, enables the use of the shutter mode described in section~\ref{ch:shutter}. Set to 0 to disable the shutter mode.
\item[ShutterSource] \verb|[unsigned int, 0]| Defines which of the six LEMO inputs is to be used to trigger the shutter sequence. The input should not be also used as part of the trigger validation.
\item[InternalShutterInterval] \verb|[unsigned int, 0]| Determines the period, in 25~ns clock cycles, of the internal shutter trigger. This can be used for debugging purposes. Set to 0 to disable this feature.
\item[ShutterOnTime] \verb|[unsigned int, 0]| Time between start of sequence and shutter asserted (t$_{1}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units, i.e. a value of 3 corresponds to 75~ns.
\item[ShutterVetoOffTime] \verb|[unsigned int, 0]| Time between start of sequence and veto being de-asserted (t$_{2}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units.
\item[ShutterOffTime] \verb|[unsigned int, 0]| Time between start of sequence and time at which shutter de-asserted and veto reasserted (t$_{3}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units.
\end{description}
\ No newline at end of file
\chapter{Shutter}\label{ch:shutter}
An optional ``shutter'' can be enabled. When the shutter is ``closed'' triggers are vetoed and no triggers are sent. When the shutter is ``open'' triggers can be generated and sent to active DUTs.
The shutter cycle can either be started by an external signal or synchronized by a counter clocked by the system clock.
The external signal, if used, must be connected to one of the trigger inputs. An appropriate threshold should be set and the input used for synchronizing the shutter should not be used in the trigger mask.
Figure \ref{fig:shutter_timing} illustrates the timing of the shutter. Behaviour of the shutter is controlled by the IPBus registers described in table \ref{tab:shutter_registers}.
\begin{table}
\begin{tabular}{lp{\0.6\linewidth}}
Register Name & Function \\ \hline
ControlRW & Bit-0 controls if shutter pulses are active. (bit-0 = 1). Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
ShutterSelectRW & Selects which input is used to trigger shutter sequence.()range = 0-5)\\
InternalShutterPeriodRW & Internal sequence period (when using internal sequence). Units of clock cycles.\\
ShutterOnTimeRW & Time between start of sequence and shutter asserted( t1) \\
ShutterVetoOffTimeRW & time between start of sequence and veto being de-asserted (t2)\\
ShutterOffTimeRW & Time between start of sequence and time at which shutter de-asserted and veto reasserted (t3) \\
\end{tabular}
\caption{IPBus registers controlling behaviour of shutter.}
\label{tab:shutter_registers}
\end{table}
An optional ``shutter'' can be enabled to synchronize the acquisition window to a signal, such as the spill signal from a beam line.\\
When the shutter is ``closed'' triggers are vetoed and no triggers are sent. When the shutter is ``open'' triggers can be generated and sent to active \gls{dut}s.\\
The shutter cycle can either be started by an external signal or synchronized by a counter clocked by the system clock (i.e. internally-generated shutter, which can be used to debug hardware).\\
The external signal, if used, must be connected to one of the six LEMO trigger inputs.\\
\begin{alertinfo}{If the external signal is used, an appropriate threshold should be set to the corresponding input. The input used for synchronizing the shutter should not be used in the trigger mask.}
\end{alertinfo}
Figure~\ref{fig:shutter_timing} illustrates the timing of the shutter sequence.\\
When the shutter is open, the \gls{tlu} will assert the \verb|CONT| line (see table~\ref{tab:HDMIpins}), indicating to the \gls{dut} that the sequence is active.\\
Behaviour of the shutter is controlled by the IPBus registers described in table~\ref{tab:shutter_registers}. If using EUDAQ, the registers can be written by including the corresponding steering parameters.
In this case, the easiest way to avoid potential conflict between the shutter signal and the trigger input is to connect the shutter input to LEMO 6 and then setting \verb|trigMaskHi= 0x0|. This means that the corresponding input is never involved in a valid active word. See section~\ref{ch:triggerLogic} for details.\\
The parameters should be included in the config file described in section~\ref{ch:configFile}.
>>>>>>> c7846bc11e8e9e621b1c031e28f70eb3380ed01a
\begin{figure}
\centering
\includegraphics[width=.95\textwidth]{./Images/aida-tlu-sitra-shutter-timing_02.pdf}
\caption{Shutter Timing}
\includegraphics[width=.99\textwidth]{./Images/aida-tlu-sitra-shutter-timing_02.pdf}
\caption{Shutter Timing: the E$_{min}$ signal is fed to one of the trigger inputs and initiates the shutter sequence; after a programmable delay t$_{1}$ the \gls{tlu} asserts the \emph{shutter} signal. The unit will start to issue trigger signals to the \gls{dut} once a programmable time t$_{2}$ has elapsed. The window between t$_{1}$ and t$_{2}$ can be used to ensure the \gls{dut} is configured and ready to accept triggers. The unit will issue triggers until the end of the shutter window, determined by t$_{3}$.}
\label{fig:shutter_timing}
\end{figure}
%\begin{table}
% \begin{tabular}{lp{\0.6\linewidth}}
% Register Name & Function \\ \hline
% ControlRW & Bit-0 controls if shutter pulses are active. 1 = active. Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
% ShutterSelectRW & Selects which input is used to trigger shutter sequence.range = 0-5)\\
% InternalShutterPeriodRW & Internal sequence period (when using internal sequence). Units of clock cycles.\\
% ShutterOnTimeRW & Time between start of sequence and shutter asserted( t1) \\
% ShutterVetoOffTimeRW & time between start of sequence and veto being de-asserted (t2)\\
% ShutterOffTimeRW & Time between start of sequence and time at which shutter de-asserted and veto reasserted(t3)\\
% \end{tabular}
% \caption{IPBus registers controlling behaviour of shutter.}
% \label{tab:shutter_registers}
%\end{table}
\begin{landscape}
\begin{table}[]
\begin{tabular}{llll}
\textbf{\begin{tabular}[c]{@{}l@{}}CONFIGURATION\\ PARAMETER\end{tabular}} & \textbf{FUNCTION} & \multicolumn{1}{c}{\textbf{NOTE}} & \textbf{\begin{tabular}[c]{@{}l@{}}REGISTER \\ NAME\end{tabular}} \\ \hline
EnableShutterMode & \begin{tabular}[c]{@{}l@{}}If 1, shutter mode is enabled.\\ If 0, shutter mode is disabled.\end{tabular} & & ControlRW \\ \hline
ShutterSource & Selects which input is used to trigger shutter sequence. & Range 0:5 & ShutterSelectRW \\ \hline
InternalShutterInterval & \begin{tabular}[c]{@{}l@{}}Internal shutter period when using internal sequence.\\ Set to 0 to not use internal shutter generator.\end{tabular} & \begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular} & InternalShutterPeriodRW \\ \hline
ShutterOnTime & Time between start of sequence and shutter asserted (t$_{1}$). & \begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular} & ShutterOnTimeRW \\ \hline
ShutterVetoOffTime & Time between start of sequence and veto being de-asserted (t$_{2}$). & \begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular} & ShutterVetoOffTimeRW \\ \hline
ShutterOffTime & \begin{tabular}[c]{@{}l@{}}Time between start of sequence and time at which\\ shutter de-asserted and veto reasserted (t$_{3}$).\end{tabular} & \begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular} & ShutterOffTimeRW \\ \hline
\end{tabular}
\caption{Configuration parameters and corresponding IPBus registers controlling behaviour of shutter.}
\label{tab:shutter_registers}
\end{table}
\end{landscape}
......@@ -17,8 +17,6 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
\begin{table}[]
\centering
\caption{HDMI pin connections.}
\label{tab:HDMIpins}
\begin{tabular}{|l|l|l|}
\hline
\textbf{HDMI PIN} & \textbf{HDMI Signal Name} & \textbf{Enable Signal Name} \\ \hline
......@@ -43,6 +41,8 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
18 & n.c. & \\ \hline
19 & n.c. & \\ \hline
\end{tabular}
\caption{HDMI pin connections.}
\label{tab:HDMIpins}
\end{table}
\begin{figure}
......@@ -61,7 +61,7 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
\subsubsection{SFP cage}
\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the Si5345 to provide a clock reference.
\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream or to issue timing signals over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the on-board clock chip to be used as a clock reference.
\section{Clock LEMO}
The board hosts a two-pin LEMO connector that can be used to provide a reference clock to the clock generator (see section~\ref{ch:clock}) or to output the clock from the \gls{tlu} to the external world, for instance to use it as a reference for another \gls{tlu}. The signal level is 3.3~V \gls{lvds}.\\
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This diff is collapsed.
\chapter{Clock}\label{ch:clock}
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}. A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}.\\
A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourht input is used to provide a zero-delay feedback loop.\\
The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop. Note that it is possible to program the clock chip to generate a different frequency for each of its outputs.\\
The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
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......@@ -4,6 +4,8 @@ This repository is only used to provide the most up-to-date documentation for th
The documentation is provided as a LaTex project. The file [Main_TLU.pdf](./Documentation/Main_TLU.pdf) is a compiled PDF version of the documentation.
For a quick guide on how to setup and start using the TLU, see the manual section **Setup**.
## How to access the TLU software, hardware and firmware files
The **CAD** design files for the TLU can be accessed via a dedicated hardware repository (**https://ohwr.org/project/fmc-mtlu-hw/**).
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