From f57ac4ed4d3d5580f66ab245fb901e6514d32237 Mon Sep 17 00:00:00 2001
From: Paolo Baesso <paolo.baesso@bristol.ac.uk>
Date: Thu, 26 Oct 2017 11:11:57 +0100
Subject: [PATCH] Fixed a bug preventin correct assignment of HDMI line
direction. Addend function to read the status of the outputs for the bus
expanders
---
TLU_v1e/scripts/TLU_v1e.py | 18 +++++++++---------
TLU_v1e/scripts/localIni.ini | 2 +-
packages/PCA9539PW.py | 8 ++++++++
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/TLU_v1e/scripts/TLU_v1e.py b/TLU_v1e/scripts/TLU_v1e.py
index 4ca93963..e79a7939 100644
--- a/TLU_v1e/scripts/TLU_v1e.py
+++ b/TLU_v1e/scripts/TLU_v1e.py
@@ -84,11 +84,11 @@ class TLU:
self.IC6=PCA9539PW(self.TLU_I2C, exp1_addr)
self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(0, 0x77)# If output, set to XX
+ self.IC6.setOutputs(0, 0xFF)# If output, set to XX
self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
- self.IC6.setOutputs(1, 0x77)# If output, set to XX
+ self.IC6.setOutputs(1, 0xFF)# If output, set to XX
#self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2_Addr"), 16)
@@ -119,13 +119,13 @@ class TLU:
print " Setting DUT:", dutN, "to", enable
if (verbose > 1):
print "\tBank", bank, "Nibble", nibble
- res= self.IC6.getIOReg(bank)
+ res= self.IC6.getOutputs(bank)
oldStatus= res[0]
mask= 0xF << 4*nibble
newStatus= oldStatus & (~mask)
if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
newStatus |= mask
- self.IC6.setIOReg(bank, newStatus)
+ self.IC6.setOutputs(bank, newStatus)
if verbose:
print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
@@ -145,13 +145,13 @@ class TLU:
print " Setting DUT:", dutN, "pins status to", hex(enable)
if (verbose > 1):
print "\tBank", bank, "Nibble", nibble
- res= self.IC6.getIOReg(bank)
+ res= self.IC6.getOutputs(bank)
oldStatus= res[0]
mask= 0xF << 4*nibble
newnibble= (enable & 0xF) << 4*nibble # bits we want to change are marked with 1
newStatus= (oldStatus & (~mask)) | (newnibble & mask)
- self.IC6.setIOReg(bank, newStatus)
+ self.IC6.setOutputs(bank, newStatus)
if (verbose > 0):
self.getDUTOutpus(dutN, verbose)
@@ -175,7 +175,7 @@ class TLU:
maskLow= 1 << (1* dutN) #CLK FROM FPGA
maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
mask= maskLow | maskHigh
- res= self.IC7.getIOReg(bank)
+ res= self.IC7.getOutputs(bank)
oldStatus= res[0]
newStatus= oldStatus & ~mask #set both bits to zero
outStat= ""
@@ -191,7 +191,7 @@ class TLU:
print " Setting DUT:", dutN, "clock source to", outStat
if (verbose > 1):
print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
- self.IC7.setIOReg(bank, newStatus)
+ self.IC7.setOutputs(bank, newStatus)
return newStatus
def enableClkLEMO(self, enable= False, verbose= False):
@@ -233,7 +233,7 @@ class TLU:
return -1
bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
- res= self.IC6.getIOReg(bank)
+ res= self.IC6.getOutputs(bank)
dut_status= res[0]
dut_lines= ["CONT", "SPARE", "TRIG", "BUSY"]
dut_status= 0x0F & (dut_status >> (4*nibble))
diff --git a/TLU_v1e/scripts/localIni.ini b/TLU_v1e/scripts/localIni.ini
index 80fb9451..45920564 100644
--- a/TLU_v1e/scripts/localIni.ini
+++ b/TLU_v1e/scripts/localIni.ini
@@ -1,6 +1,6 @@
[Producer.fmctlu]
initid= 20170703
-verbose = 0
+verbose = 1
ConnectionFile= "file://./../user/eudet/misc/fmctlu_connection.xml"
DeviceName="fmctlu.udp"
TLUmod= "1e"
diff --git a/packages/PCA9539PW.py b/packages/PCA9539PW.py
index c04719ba..723b0ad4 100644
--- a/packages/PCA9539PW.py
+++ b/packages/PCA9539PW.py
@@ -84,3 +84,11 @@ class PCA9539PW:
return
values = values & 0xFF
self.writeReg(bank+2, values)
+
+ def getOutputs(self, bank):
+ #Read the state of the outputs (i.e. what value is being written to them)
+ if (bank < 0) | (bank > 1):
+ print "PCA9539PW - ERROR: bank should be 0 or 1"
+ return
+ res= self.readReg(bank+2, 1)
+ return res
--
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