diff --git a/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd b/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
index 9f2dc2405737a8a26ac4412a2b1d91c74fd9114c..c304c7e059d407a0504dfe5d0eac7285e2a22149 100644
--- a/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
+++ b/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
@@ -44,26 +44,26 @@ use work.ipbus_reg_types.all;
ENTITY T0_Shutter_Iface IS
GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits in counter
g_IPBUS_WIDTH : integer := 32; --! Width of IPBus data bus
- g_NUM_TRIG_SOURCES : integer := 4 --! Number of input trigger sources.
+ g_NUM_ACCELERATOR_SIGNALS : integer := 4 --! Number of input trigger sources.
);
PORT
(
-- Input signals
- clock_i: IN STD_LOGIC; --! rising edge active clock
+ clk_4x_i: IN STD_LOGIC; --! rising edge active clock
reset_i: IN STD_LOGIC; --! Active high. syncronous with rising clk
- strobe_i: IN STD_LOGIC; --! one strobe pulse per 4 clock cycles
- trigger_sources_i: IN STD_LOGIC_VECTOR(g_NUM_TRIG_SOURCES-1 downto 0); --! array of possible trigger trigger_sources
+ clk_4x_strobe_i: IN STD_LOGIC; --! one strobe pulse per 4 clock cycles
+ accelerator_signals_i: IN STD_LOGIC_VECTOR(g_NUM_ACCELERATOR_SIGNALS-1 downto 0); --! array of possible trigger trigger_sources
--! IPBus signals
- ipb_clk_i: in std_logic;
- ipb_in: in ipb_wbus;
- ipb_out: out ipb_rbus;
+ ipbus_clk_i: in std_logic;
+ ipbus_i: in ipb_wbus;
+ ipbus_o: out ipb_rbus;
--! Output Signals
shutter_o: OUT STD_LOGIC; --! Shutter signal.
- trigger_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers
- T0_o --! T0 synchronization pulse
+ shutter_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers
+ T0_o: out std_logic --! T0 synchronization pulse
);
END T0_Shutter_Iface;
@@ -98,12 +98,12 @@ begin
generic map (
g_COUNTER_WIDTH => g_COUNTER_WIDTH ,
g_IPBUS_WIDTH => g_IPBUS_WIDTH ,
- g_NUM_TRIG_SOURCES => g_NUM_TRIG_SOURCES )
+ g_NUM_TRIG_SOURCES => g_NUM_ACCELERATOR_SIGNALS )
port map (
- clock_i => clock_i,
+ clk_4x_i => clk_4x_i,
reset_i => reset_i,
- strobe_i => strobe_i,
- trigger_sources_i => trigger_sources_i,
+ strobe_i => clk_4x_strobe_i,
+ trigger_sources_i => accelerator_signals_i,
trigger_source_select_i => s_trigger_source_select,
threshold_t1_i => s_threshold_t1,
threshold_t2_i => s_threshold_t2,
@@ -112,7 +112,7 @@ begin
internal_cycle_length_i => s_internal_cycle_length,
enable_internal_cycle_i => s_enable_internal_cycle,
shutter_o => shutter_o,
- trigger_veto_o => trigger_veto_o );
+ trigger_veto_o => shutter_veto_o );
cmp_ipbusReg: entity work.ipbus_syncreg_v
generic map(
@@ -120,11 +120,11 @@ begin
N_STAT => c_NUM_STAT_REGS
)
port map (
- clk => ipb_clk_i,
+ clk => ipbus_clk_i,
rst => reset_i,
- ipb_in => ipb_in,
- ipb_out => ipb_out,
- slv_clk => clock_i,
+ ipb_in => ipbus_i,
+ ipb_out => ipbus_o,
+ slv_clk => clk_4x_i,
d => s_ipbus_statusregs,
q=> s_ipbus_controlregs,
qmask => c_ipbus_qmask,
@@ -146,7 +146,7 @@ begin
-- pulse, so put this logic in parallel.
--------------------
ipbus_generateT0: process (ipbus_clk_i)
- begin -- process ipb_clk_i
+ begin -- process ipbus_clk_i
if rising_edge(ipbus_clk_i) then
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
@@ -161,8 +161,8 @@ begin
--! Retime T0 generated by IPBus onto clk_4x and align with strobe
cmp_T0_retime: entity work.stretchPulse4x
port map (
- clk_4x_i => clock_i,
- clk_4x_strobe_i => strobe_i,
+ clk_4x_i => clk_4x_i,
+ clk_4x_strobe_i => clk_4x_strobe_i,
pulse_i => s_T0_ipbus,
pulse_o => T0_o);
diff --git a/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd b/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
index d8edf6f459fdecc51be672637b193a9f24f62b5c..e45f4ce166b5c76ab8f585fe4de95995c21c0db2 100644
--- a/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
+++ b/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
@@ -23,7 +23,7 @@ use work.ipbus.ALL;
entity top_tlu_v1e is
generic(
- constant FW_VERSION : unsigned(31 downto 0):= X"1e000008"; -- Firmware revision. Remember to change this as needed.
+ constant FW_VERSION : unsigned(31 downto 0):= X"1e00000f"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
@@ -141,6 +141,7 @@ architecture rtl of top_tlu_v1e is
SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Rising edge of trigger inputs
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
+ signal shutter_veto_o : std_logic; --! Goes high when triggers should be vetoed by shutter
signal ctrl, stat: ipb_reg_v(0 downto 0);
--My signals
--SIGNAL busy_toggle_o : std_logic_vector(g_NUM_DUTS-1 downto 0);
@@ -189,6 +190,7 @@ architecture rtl of top_tlu_v1e is
T0_o : OUT std_logic;
accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 DOWNTO 0);
ipbus_o : OUT ipb_rbus;
+ shutter_veto_o: out std_logic;
shutter_o : OUT std_logic
);
END COMPONENT T0_Shutter_Iface;
@@ -405,7 +407,7 @@ begin
-- ModuleWare code(v1.12) for instance 'I19' of 'merge'
--gpio_hdr <= dout1 & dout & s_shutter & T0_o;
-- ModuleWare code(v1.12) for instance 'I8' of 'sor'
- overall_veto <= buffer_full_o OR veto_o;
+ overall_veto <= buffer_full_o OR veto_o or shutter_veto_o;
-- ModuleWare code(v1.12) for instance 'I16' of 'sor'
s_triggerLogic_reset <= logic_reset OR T0_o;
@@ -611,6 +613,7 @@ begin
accelerator_signals_i => triggers,
T0_o => T0_o,
shutter_o => s_shutter,
+ shutter_veto_o => shutter_veto_o,
ipbus_clk_i => clk_ipb,
ipbus_i => ipbww(N_SLV_SHUTTER),
ipbus_o => ipbrr(N_SLV_SHUTTER)