diff --git a/AIDA_tlu/.gitignore b/AIDA_tlu/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..3eae03feb73291bbfad3cbe4f903c79fb49f7cb7
--- /dev/null
+++ b/AIDA_tlu/.gitignore
@@ -0,0 +1,74 @@
+/TLU_v1e/work/TLU_v1e.runs/*
+/EUDETdummy/work/*
+/TLU_v1e/work/*
+/TLU_v1c/work/*
+/Enclustra_Example/*
+/Enclustra_tests/
+/TLU_v1e/scripts/datafiles
+/Data/*
+/TLU_v1e/.Xil/
+*.pyc
+.svn/*
+*.jou
+*.str
+*.BKP
+
+## Backup files
+*.py~
+*.md~
+*.sh~
+*.*~
+
+## Core latex/pdflatex auxiliary files:
+*.aux
+*.lof
+*.log
+*.lot
+*.fls
+*.out
+*.toc
+*.fmt
+*.fot
+*.cb
+*.cb2
+
+## Bibliography auxiliary files (bibtex/biblatex/biber):
+*.bbl
+*.bcf
+*.blg
+*-blx.aux
+*-blx.bib
+*.run.xml
+
+## WinEdt project
+*.prj.bak
+
+## Intermediate documents:
+*.dvi
+*.xdv
+*-converted-to.*
+
+## Build tool auxiliary files:
+*.fdb_latexmk
+*.synctex
+*.synctex(busy)
+*.synctex.gz
+*.synctex.gz(busy)
+*.pdfsync
+
+# makeidx
+*.idx
+*.ilg
+*.ind
+*.ist
+
+# glossaries
+*.acn
+*.acr
+*.glg
+*.glo
+*.gls
+*.glsdefs
+
+# xindy
+*.xdy
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+31 Patch Control
+
+0
+0
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+*Main_TLU.tex
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+*O:/LatexFiles/Glossary/myGlossary.tex
+*ch_TLU_Preparation
+*ch_TLU_Hardware
+*ch_TLU_clock
+*DUT_signals
+*ch_TLU_triggerInputs
+*ch_EventBuffer
+*ch_TLU_Functions
+*ch_TLU_IPBusRegs
+*ch_EUDAQParameters
+*ch_EUDAQProducer
+*ch_TLU_Appendix
+<
diff --git a/AIDA_tlu/Documentation/Latex/DUT_signals.tex b/AIDA_tlu/Documentation/Latex/DUT_signals.tex
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index 0000000000000000000000000000000000000000..c773b9139dcbe5247d493b008380c54142539ccd
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/DUT_signals.tex
@@ -0,0 +1,2 @@
+\chapter{DUT signals}\label{ch:DUTsignals}
+In the old versions of the \gls{tlu} the direction of the signals on the \verb|HDMI*| connectors were pre-defined. The new hardware has separate lines for signals going into the \gls{tlu} and signals out of the \gls{tlu}. See section~\ref{ch:hwDUT} for further details.\\ 
\ No newline at end of file
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xml:space="preserve"><tspan>30</tspan></text><text x="146" y="15" text-anchor="middle" xml:space="preserve"><tspan>29</tspan></text><text x="186" y="15" text-anchor="middle" xml:space="preserve"><tspan>28</tspan></text><text x="226" y="15" text-anchor="middle" xml:space="preserve"><tspan>27</tspan></text><text x="266" y="15" text-anchor="middle" xml:space="preserve"><tspan>26</tspan></text><text x="306" y="15" text-anchor="middle" xml:space="preserve"><tspan>25</tspan></text><text x="346" y="15" text-anchor="middle" xml:space="preserve"><tspan>24</tspan></text><text x="386" y="15" text-anchor="middle" xml:space="preserve"><tspan>23</tspan></text><text x="426" y="15" text-anchor="middle" xml:space="preserve"><tspan>22</tspan></text><text x="466" y="15" text-anchor="middle" xml:space="preserve"><tspan>21</tspan></text><text x="506" y="15" text-anchor="middle" xml:space="preserve"><tspan>20</tspan></text><text x="546" y="15" text-anchor="middle" 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xml:space="preserve"><tspan>8</tspan></text><text x="1026" y="15" text-anchor="middle" xml:space="preserve"><tspan>7</tspan></text><text x="1066" y="15" text-anchor="middle" xml:space="preserve"><tspan>6</tspan></text><text x="1106" y="15" text-anchor="middle" xml:space="preserve"><tspan>5</tspan></text><text x="1146" y="15" text-anchor="middle" xml:space="preserve"><tspan>4</tspan></text><text x="1186" y="15" text-anchor="middle" xml:space="preserve"><tspan>3</tspan></text><text x="1226" y="15" text-anchor="middle" xml:space="preserve"><tspan>2</tspan></text><text x="1266" y="15" text-anchor="middle" xml:space="preserve"><tspan>1</tspan></text><text x="1306" y="15" text-anchor="middle" xml:space="preserve"><tspan>0</tspan></text></g></g><g id="wavelane_1_0" transform="translate(0,35)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 0</tspan></text><g id="wavelane_draw_1_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-2" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-2-4" transform="translate(200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(340)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(360)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(380)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(580)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(600)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(620)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(640)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-4" transform="translate(660)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-4-5" transform="translate(680)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(700)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(720)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(740)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(760)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(780)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(800)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(820)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(840)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(860)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(880)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(900)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(920)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(940)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(960)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(980)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1000)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1020)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1040)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1060)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1080)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vm0-5" transform="translate(1320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(1340)"/><text x="126" y="15" text-anchor="middle" xml:space="preserve"><tspan>ev. type [4 bit]</tspan></text><text x="446" y="15" text-anchor="middle" xml:space="preserve"><tspan>trigger data [12 bit]</tspan></text><text x="1006" y="15" text-anchor="middle" xml:space="preserve"><tspan>time stamp (25 ns) [upper 16 bit]</tspan></text></g></g><g id="wavelane_2_0" transform="translate(0,65)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 1</tspan></text><g id="wavelane_draw_2_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-5" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(340)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(360)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(380)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(580)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(600)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(620)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(640)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(660)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(680)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(700)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(720)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(740)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(760)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(780)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(800)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(820)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(840)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(860)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(880)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(900)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(920)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(940)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(960)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(980)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1000)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1020)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1040)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1060)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1080)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-5" transform="translate(1300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vm0-5" transform="translate(1320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(1340)"/><text x="686" y="15" text-anchor="middle" xml:space="preserve"><tspan>time stamp (25 ns) [lower 32 bit]</tspan></text></g></g><g id="wavelane_3_0" transform="translate(0,95)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 2</tspan></text><g id="wavelane_draw_3_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-3" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(340)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(360)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(380)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(580)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(600)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(620)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(640)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(660)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(680)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(700)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(720)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(740)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(760)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(780)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(800)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(820)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(840)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(860)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(880)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(900)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(920)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(940)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(960)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(980)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(1000)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1020)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1040)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1060)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1080)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vm0-3" transform="translate(1320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(1340)"/><text x="206" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 0 [8 bit]</tspan></text><text x="526" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 1 [8 bit]</tspan></text><text x="846" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 2 [8 bit]</tspan></text><text x="1166" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 3 [8 bit]</tspan></text></g></g><g id="wavelane_4_0" transform="translate(0,125)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 3</tspan></text><g id="wavelane_draw_4_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-2" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(340)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(360)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(380)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(580)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(600)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(620)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(640)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(660)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(680)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(700)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(720)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(740)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(760)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(780)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(800)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(820)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(840)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(860)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(880)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(900)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(920)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(940)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(960)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(980)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1000)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1020)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1040)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1060)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1080)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-2" transform="translate(1300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vm0-2" transform="translate(1320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(1340)"/><text x="686" y="15" text-anchor="middle" xml:space="preserve"><tspan>event number [32 bit]</tspan></text></g></g><g id="wavelane_5_0" transform="translate(0,155)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 4</tspan></text><g id="wavelane_draw_5_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-3" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(340)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(360)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(380)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(580)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(600)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(620)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(640)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(660)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(680)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(700)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(720)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(740)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(760)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(780)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(800)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(820)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(840)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(860)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(880)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(900)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(920)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(940)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(960)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(980)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vmv-3-3" transform="translate(1000)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1020)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1040)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1060)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1080)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1180)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1200)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1220)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1240)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1260)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1280)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(1300)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vm0-3" transform="translate(1320)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(1340)"/><text x="206" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 4 [8 bit]</tspan></text><text x="526" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 5 [8 bit]</tspan></text><text x="846" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 6 [8 bit]</tspan></text><text x="1166" y="15" text-anchor="middle" xml:space="preserve"><tspan>Fine TS 7 [8 bit]</tspan></text></g></g><g id="wavelane_6_0" transform="translate(0,185)"><text x="-10" y="15" class="info" text-anchor="end" xml:space="preserve"><tspan>WORD 5</tspan></text><g id="wavelane_draw_6_0" transform="translate(0, 0)"><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(0)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#000" transform="translate(20)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#0mv-3" transform="translate(40)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(60)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(80)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(100)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(120)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(140)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(160)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(180)"/><use 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xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(400)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(420)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(440)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(460)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(480)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(500)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(520)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(540)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(560)"/><use xmlns:xlink="http://www.w3.org/1999/xlink" xlink:href="#vvv-3" transform="translate(580)"/><use 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diff --git a/AIDA_tlu/Documentation/Latex/Main_TLU.pdf b/AIDA_tlu/Documentation/Latex/Main_TLU.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..397057b72d88839753a41c4117c0d14db045cf1f
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diff --git a/AIDA_tlu/Documentation/Latex/Main_TLU.tex b/AIDA_tlu/Documentation/Latex/Main_TLU.tex
new file mode 100644
index 0000000000000000000000000000000000000000..87ef07f31f6b3a47e95a15a102d329bbe2e6535d
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+++ b/AIDA_tlu/Documentation/Latex/Main_TLU.tex
@@ -0,0 +1,211 @@
+\documentclass[10pt,twoside, fleqn]{memoir}
+%\usepackage{createspace}
+%\usepackage[size=pocket,noicc]{createspace}
+%\usepackage[paperwidth=4.25in, paperght=6.875in,bindingoffset=.75in]{geometry}
+\usepackage[T1]{fontenc}
+\usepackage{mathpazo} % USE PALATINO FONT
+%\usepackage{newpxtext,newpxmath}
+\usepackage[latin1]{inputenc}
+%\usepackage[xindy]{imakeidx}
+%\usepackage{imakeidx}
+\usepackage[nomain,acronym,xindy,toc]{glossaries}
+%\usepackage{glossaries} %For acronyms
+\usepackage[british]{babel}
+%\usepackage{tgtermes}
+%\usepackage[framed, numbered, autolinebreaks]{mcode} %MATLAB Snippet code
+\usepackage{listings}
+\usepackage{graphicx}
+\usepackage{glossaries}
+\usepackage{hyperref} % HYPERLINKS
+\usepackage[font=footnotesize]{caption}
+%\usepackage[hidelinks]{hyperref}
+%\usepackage{xcolor}
+
+\usepackage{subcaption}
+\usepackage{pdflscape} %Landscape pages
+\usepackage{pdfpages} %Insert pdf in document
+\usepackage{amsmath}
+\usepackage{amssymb}
+\usepackage{gensymb} %Degree sign
+\usepackage{footnote} %Footnotes in tabulars
+\usepackage{xcolor,framed,marginnote,blindtext}
+\hypersetup{
+    colorlinks,
+    linkcolor={blue!50!black},
+    citecolor={blue!50!black},
+    urlcolor={blue!80!black}
+}% Get rid of that MySpace feeling in hypelinks...
+\usepackage{listings} %Include code
+\usepackage{multirow}
+\usepackage{datetime}
+%\usepackage{svg}
+
+\definecolor{infobackground}{RGB}{217,237,247}
+\definecolor{infoforeground}{RGB}{58,135,173}
+\definecolor{infoborder}{RGB}{188,232,241}
+\usepackage{environ}
+\usepackage{tikz} %TO CREATE BLOCK DIAGRAMS
+\usetikzlibrary{fit,backgrounds,calc}
+%\usepackage{vrsion}
+\colorlet{shadecolor}{blue!10}
+%\usepackage[fleqn]{amsmath}
+\usetikzlibrary{shapes,arrows}
+\usetikzlibrary{positioning}
+
+\setcounter{tocdepth}{2} % DEPTH OF TABLE OF CONTENTS; 2= SUBSECTIONS INCLUDED
+\setcounter{secnumdepth}{2} % SUBSECTIONS ARE NUMBERED
+
+\usepackage[clockwise, figuresright]{rotating}
+\usepackage{longtable}
+\usepackage{tabu}
+
+\NewEnviron{alertinfo}[1]
+{
+    \begin{tikzpicture}
+    \node[inner sep=0pt,
+          draw=infoborder,
+          line width=1.2pt,
+          fill=infobackground] (box) {\parbox[t]{.99\textwidth}
+        {%
+            \begin{minipage}{.15\textwidth}
+                \centering\tikz[scale=3]
+                \node[scale=1]
+                {
+                    \includegraphics[scale=0.04]{./Images/Warning.png}
+                };
+            \end{minipage}%
+           \begin{minipage}{.80\textwidth}
+                \vskip 10pt
+                \textbf{\textcolor{infoforeground}{#1}}\par\smallskip
+                \textcolor{infoforeground}{\BODY}
+                \par\smallskip
+            \end{minipage}\hfill
+        }%
+    };
+
+    \end{tikzpicture}
+}
+
+
+%\usepackage{mathpazo}
+%\usepackage[protrusion=true,expansion=true]{microtype}
+%\usepackage{type1cm}
+%\usepackage{lettrine}
+
+%\checkandfixthelayout
+
+% See the ``Memoir customise'' template for some common customisations
+% Don't forget to read the Memoir manual: memman.pdf
+
+%\title{TITLE OF BOOK}
+%\author{NAME OF AUTHOR}
+%\date{} % Delete this line to display the current date
+
+%% BEGIN TITLE
+
+\makeatletter
+\def\maketitle{%
+  \null
+  \thispagestyle{empty}%
+  \vfill
+  \begin{center}\leavevmode
+    \normalfont
+    {\LARGE\raggedleft \@author\par}%
+    \hrulefill\par
+    {\huge\raggedright \@title\par}%
+    \vskip 1cm
+  {\Large \@date\par}%
+  \end{center}%
+  \vfill
+  \null
+  \cleardoublepage
+  }
+\makeatother
+\author{Paolo Baesso}
+\title{AIDA Trigger logic unit (TLU)}
+\date{\today}
+\loadglsentries{O:/LatexFiles/Glossary/myGlossary.tex}
+%\input{O:/LatexFiles/Glossary/myGlossary.tex}
+%\makeglossaries
+
+
+%%% BEGIN DOCUMENT
+\makeindex
+\begin{document}
+
+\def\brd{FMC\_TLU\_v1E }
+\def\oldbrd{FMC\_TLU\_v1C }
+
+\let\cleardoublepage\clearpage
+
+
+\maketitle
+\frontmatter
+
+\null\vfill
+\begin{flushleft}
+\textit{Board \brd.}\newline
+\newline
+Paolo Baesso - \monthname,   \the\year\newline paolo.baesso@bristol.ac.uk
+\bigskip
+
+\end{flushleft}
+\let\cleardoublepage\clearpage
+
+\newpage
+\tableofcontents
+
+\mainmatter
+\sloppy
+
+\newenvironment{SpecialPar}
+  {\begin{shaded}\noindent}
+  {\end{shaded}}
+
+
+
+%%% INCLUDE CHAPTERS
+
+%\def\conn{\verb|HDMI1|}
+%\def\conn{\verb|HDMI2|}
+%\def\conn{\verb|HDMI3|}
+%\def\conn{\verb|HDMI4|}
+%\include{ch_Introduction}
+
+
+
+
+\include{ch_TLU_Preparation}
+\include{ch_TLU_Hardware}
+\include{ch_TLU_clock}
+\include{DUT_signals}
+\include{ch_TLU_triggerInputs}
+\include{ch_EventBuffer}
+\include{ch_TLU_Functions}
+\include{ch_TLU_IPBusRegs}
+\include{ch_EUDAQParameters}
+\include{ch_EUDAQProducer}
+\include{ch_TLU_Appendix}
+
+%\begin{figure}[h]
+%  \centering
+%  \includegraphics[width=1.62\textwidth, angle=90]{./Images/protoDUNE_fmc_sfp_to_slave_v0-7.pdf}
+%  \caption{Sketch of the connections and signal names between the elements of the board.}\label{fig:Connections}
+%\end{figure}
+
+%\section{Schematic}
+%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A.pdf}
+%%\includepdf[pages={1-},scale=0.99, landscape=true]{./Images/PC053A_TOPLEVEL.pdf}
+
+
+%%% GLOSSARY
+\printglossaries
+%\printglossary[type=\acronymtype]
+\printglossary[type=\acronymtype,title=Abbreviations]
+
+%%% BIBLIOGRAPHY
+%\bibliographystyle{unsrt}
+%\bibliography{./../../Bibliography/myBibliography}
+
+
+\end{document} 
\ No newline at end of file
diff --git a/AIDA_tlu/Documentation/Latex/ch_EUDAQParameters.tex b/AIDA_tlu/Documentation/Latex/ch_EUDAQParameters.tex
new file mode 100644
index 0000000000000000000000000000000000000000..d0a7a8736b58042658d62f84cb4cb96aa817977e
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_EUDAQParameters.tex
@@ -0,0 +1,78 @@
+\chapter{EUDAQ Parameters}\label{ch:EUDAQPar}
+List of parameters that are parsed by the EUDAQ run control \gls{gui} to configure the \gls{tlu}.\\
+The parameters must be included in the INI or CONF file passed to the main window (see~fig.\ref{fig:EUDAQGui}).
+\begin{figure}
+  \centering
+  \includegraphics[width=.90\textwidth]{./Images/RunControlGUI.jpg}
+  \caption{Main user iterface of the EUDAQ framework.}
+  \label{fig:EUDAQGui}
+\end{figure}\\
+Not all parameters are needed; if one of the parameters is not present in the files, the code will generally assume a default value, indicated in brackets in the following document \verb|[type, default]|.
+\section{INI file}
+\begin{description}
+  \item[initid] \verb|[string, "0"]| Does not serve any purpose in the code but can be useful to identify configuration settings used in a specific run. EUDAQ will store this information in the run data.
+  \item[ConnectionFile] \verb|[string, "file://./FMCTLU_connections.xml"]| Name of the xml file used to store the information required to communicate with the hardware, such as its IP address and the location of the address map. The default location indicates a file that must be located in the \texttt{bin} folder.
+  \item[DeviceName] \verb|[string, "fmctlu.udp"]| The name of the type of hardware to be contacted by the IPBus.
+  \item[TLUmod] \verb|[string, "1e"]| Version of the \gls{tlu} hardware. Reserved for future use.
+  \item[nDUTs] \verb|[positive int, 4]| Number of \gls{dut} in the current \gls{tlu}. This is for future upgrades and should not require editing by the user.
+  \item[nTrgIn] \verb|[positive int, 6]| Number of trigger inputs in the current \gls{tlu}. This is for future upgrades and should not require editing by the user.
+  \item[I2C\_COREEXP\_Addr] \verb|[positive int, 0x21]| \gls{i2c} address of the core expander mounted on the Enclustra board. This is not required if a different \gls{fpga} is used. See section~\ref{ch:i2c} for further details.
+  \item[I2C\_CLK\_Addr] \verb|[positive int, 0x68]| \gls{i2c} address of Si5345 clock generator installed on the \gls{tlu}.
+  \item[I2C\_DAC1\_Addr] \verb|[positive int, 0x13]| \gls{i2c} address of \gls{dac} installed on the \gls{tlu}. The \gls{dac} is used to configure the threshold of the trigger inputs.
+  \item[I2C\_DAC2\_Addr] \verb|[positive int, 0x1F]| \gls{i2c} address of \gls{dac} installed on the \gls{tlu}. The \gls{dac} is used to configure the threshold of the trigger inputs.
+  \item[I2C\_ID\_Addr] \verb|[positive int, 0x50]| \gls{i2c} address the unique ID \gls{eeprom} installed on the \gls{tlu}. The chip is used to provide a unique identifier to each kit.
+  \item[I2C\_EXP1\_Addr] \verb|[positive int, 0x74]| \gls{i2c} address the bus expander used to select the direction of the \gls{hdmi} pins on the board.
+  \item[I2C\_EXP2\_Addr] \verb|[positive int, 0x75]| \gls{i2c} address the bus expander used to select the direction of the \gls{hdmi} pins on the board.
+  \item[intRefOn] \verb|[boolean, false]| If true, the \gls{dac}s installed on the \gls{tlu} will use their internal voltage reference rather than the one provide externally.
+  \item[VRefInt] \verb|[float, 2.5]| Value in volts for the internal reference voltage of the \gls{dac}s. The voltage is chosen by the chip manufacturer. This is only used if \verb|intRefOn= true|.
+  \item[VRefExt] \verb|[float, 1.3]| Value in volts for the external reference voltage of the \gls{dac}s. The voltage is determined by a circuit on the \gls{tlu} and the value of this parameter must reflect such voltage. This is only used if \verb|intRefOn= false|.
+  \item[CONFCLOCK] \verb|[boolean, true]| If true, the clock chip Si5345 will be re-configured when the INIT button is pressed (see figure~fig.\ref{fig:EUDAQGui}). The chip is configured via \gls{i2c} interface using a specific text file (see next parameter). After a power cycle, the chip is not configured and must be reconfigured to operate the \gls{tlu} correctly.
+  \item[CLOCK\_CFG\_FILE] \verb|[string, "./../user/eudet/misc/fmctlu_clock_config.txt"]| Name of the text file used to store the configuration values of the Si5345. The file can be generate using the Clockbuilder Pro software provided by \href{https://www.silabs.com/products/development-tools/software/clock}{SiLabs}.
+\end{description}
+
+\section{CONF file}
+\begin{description}
+  \item[confid] \verb|[string, "0"]| Does not serve any purpose in the code but can be useful to identify configuration settings used in a specific run. EUDAQ will store this information in the run data.
+  \item[verbose] \verb|[int, 0]| Defines the level of output messages from the \gls{tlu}. 0 indicates minimum output.
+  \item[HDMI1\_set] \verb|[unsigned int, 0b0001]| Defines the source of the signal on the pins for the \verb|HDMI1| connector. A 1 indicates that each pin pair is an driven by the \gls{tlu}, a 0 that they are left floating (with respect to the \gls{tlu}). This can be used to define the signal direction on each pin pair. The order of the pairs is as follow:\\
+  bit 0= CONT, bit 1= SPARE, bit 2= TRIG, trig 3= BUSY. Note that the direction of the DUTClk pair is defined in a separate parameter.\\
+  Example to configure the connector to work with an EUDET device:\\
+  - in this configuration the BUSY line is driven by the device under test, so it is an input for the \gls{tlu} and should not be driven by it (bit 3= 0)\\
+  - TRIGGER line is an output for the \gls{tlu} so is driven by it (bit 2= 1)\\
+  - SPARE line is used to provide control signals, such as the reset signal to initialize the devices at the start of a run (\texttt{T$_0$}). It should be configured as driven by the \gls{tlu} (bit 1= 1)\\
+  - CONT is used by the \gls{tlu} to issue control commands and should be configured as a signal driven by the \gls{tlu} (bit 0= 1).\\
+  Therefore the value of this parameter would be 0x7 (b1110).
+  \item[HDMI2\_set] \verb|[unsigned int, 0b0001]| Defines the direction of the pins for the \verb|HDMI2| connector.
+  \item[HDMI3\_set] \verb|[unsigned int, 0b0001]| Defines the direction of the pins for the \verb|HDMI3| connector.
+  \item[HDMI4\_set] \verb|[unsigned int, 0b0001]| Defines the direction of the pins for the \verb|HDMI4| connector.
+  \item[HDMI1\_clk] \verb|[unsigned int, 1]| Defines if the DUTClk pair on the \gls{hdmi} connector must be driven by the \gls{tlu} and, if so, what clock source to use. A 0 indicates that the pins are not driven by the \gls{tlu}. 1 indicates that pins will by driven with the clock produced from the on-board clock chip Si5345. 2 indicates that the driving clock is obtained from the \gls{fpga}.\\
+      Example to configure the connector to work with an EUDET device: in this scenario the clock is driven by the \gls{dut} so the parameter should be set to 0.
+      Example to configure the connector to work with an AIDA device: in this scenario the clock is driven by the \gls{tlu} so the parameter should be set to either 1 or 2 (by default 1).
+  \item[HDMI2\_clk] \verb|[unsigned int, 1]| Defines the driving signal on the corresponding \gls{hdmi} connector.
+  \item[HDMI3\_clk] \verb|[unsigned int, 1]| Defines the driving signal on the corresponding \gls{hdmi} connector.
+  \item[HDMI4\_clk] \verb|[unsigned int, 1]| Defines the driving signal on the corresponding \gls{hdmi} connector.
+  \item[LEMOclk] \verb|[boolean, true]| Defines whether a driving clock is to be provided on the differential LEMO connector of the \gls{tlu}. By default (value= 1), the clock is driven from the clock chip. If the value is set to 0 no clock will be driven.
+  \item[in0\_STR] \verb|[unsigned int, 0]| Defines the number of clock cycles used to stretch a pulse once a trigger is detected by the discriminator on input 0. This feature allows the user to modify the pulses that are then fed into the trigger logic within the \gls{tlu}.
+      A minimum lenght of 6.25~ns is provided if the value is 0. Any extra clock cycle extend the pulse by 6.25~ns (160~MHz clock). An example of the effect on the stretch setting is shown in figure~\ref{Fig:exampleExtendedTriggers}.
+  \item[in0\_DEL] \verb|[unsigned int, 0]| Defines the delay, in 160~MHz clock cycles, to be assigned to the discriminated pulse from input 0, in order to process the logic for the trigger. This can be used to compensate for differences in cable lengths for the signals used to create a trigger.
+  \item[in1\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 1.
+  \item[in1\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
+  \item[in2\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 2.
+  \item[in2\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
+  \item[in3\_STR] \verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 3.
+  \item[in3\_DEL] \verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
+  \item[trigMaskHi] \verb|[unsigned int32, 0]| This word represents the most significative bits of the 64-bits used to determine the trigger mask.\\
+        A detailed explanation of how to determine the correct word is provided in section~\ref{ch:triggerLogic}.
+  \item[trigMaskLo] \verb|[unsigned int32, 0]| This word represents the least significative bits of the 64-bits used to determine the trigger mask.\\
+        A detailed explanation of how to determine the correct word is provided in section~\ref{ch:triggerLogic}.
+  \item[DUTMask]  \verb|[unsigned int, 0x1]| This mask indicates which \gls{hdmi} inputs have an AIDA device connected. Each of the lowest four bits correspond to a connector (bit 0= DUT1, bit 1= DUT2, bit 2= DUT3, bit 3= DUT4). If the bit is set to 1 the \gls{tlu} expects a device connected and exchanging signals according to the mode selected (see DUTMaskMode).
+  \item[DUTMaskMode]  \verb|[unsigned int, 0xFF]| Defines the mode of operation of the device connected to a specific \gls{hdmi} port.\\
+        Two bits are needed for each device, so bits 0,1 refer to \gls{hdmi}1, bits 2, 3 refer to \gls{hdmi}2, etc. Currently only the lower bit of each pair is needed to specify if the device is in AIDA mode (\texttt{bX1}) or EUDET mode (\texttt{bx0}).\\
+        Example: to configure device 1 and 2 as EUDET and the rest as AIDA, the parameters should be set to 11-11-x0-x0, i.e. 0xF0 (but 0xFA, 0xF2 and 0xF8 would also work the same).\\
+        See also section~\ref{ch:IPBus_DUT}.
+  \item[DUTMaskModeModifier] \verb|[unsigned int, 0xF]| This mask only affects EUDET mode. Each of the lower 4 bits correspond to a device. If the device is in EUDET mode, it can assert DUTClk to produce a global veto in the triggers. This behaviour occurs if the corresponding bit is set to 1. If the bit is set to 0, asserting the DUTClk from the device will not produce a global veto.
+  \item[DUTIgnoreBusy] \verb|[unsigned int, 0xF]| This mask tells the \gls{tlu} to ignore the BUSY signal from a specific device, either in AIDA or EUDET mode. If the device is in AIDA mode, this means that further triggers will be issued while the device is busy. If the device is in EUDET mode, this means that the \gls{tlu} will not pause while they are in the handshake phase. In turn, this means that the device will likely receive events where the trigger number does not increase sequentially by one.
+  \item[DUTIgnoreShutterVeto] \verb|[unsigned int, 0x1]| Set bit to 1 to tell the \gls{dut} to ignore the shutter signal.
+  \item[EnableRecordData] \verb|[boolean, true]| if set to 1, enable the data recording in the \gls{tlu}.
+  \item[InternalTriggerFreq] \verb|[unsigned int, 0]| Defines the rate of the trigger generated internally by the \gls{tlu}, in Hz: if 0, the internal triggers are disabled. Any other value activates the internal trigger generator with frequency equal to the parameter. Values above 160~MHz are coerced to 160~MHz.
+\end{description} 
\ No newline at end of file
diff --git a/AIDA_tlu/Documentation/Latex/ch_EUDAQProducer.tex b/AIDA_tlu/Documentation/Latex/ch_EUDAQProducer.tex
new file mode 100644
index 0000000000000000000000000000000000000000..8362f12eb571247066f9ddf627e85b96b3150692
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_EUDAQProducer.tex
@@ -0,0 +1,62 @@
+\chapter{EUDAQ Producer}\label{ch:eudaqprod}
+Current structure of a fmctlu producer event:
+\lstset{language=XML}
+\scriptsize 
+\begin{lstlisting}
+<Event>
+  <Type>2149999981</Type>
+  <Extendword>171577627</Extendword>
+  <Description>Ex0Tg</Description>
+  <Flag>0x00000018</Flag>
+  <RunN>0</RunN>
+  <StreamN>0</StreamN>
+  <EventN>0</EventN>
+  <TriggerN>88</TriggerN>
+  <Timestamp>0x0000000000000000  ->  0x0000000000000000</Timestamp>
+  <Timestamp>0  ->  0</Timestamp>
+  <Block_Size>0</Block_Size>
+  <SubEvents>
+    <Size>1</Size>
+    <Event>
+      <Type>2149999981</Type>
+      <Extendword>3634980144</Extendword>
+      <Description>TluRawDataEvent</Description>
+      <Flag>0x00000010</Flag>
+      <RunN>96</RunN>
+      <StreamN>4008428646</StreamN>
+      <EventN>88</EventN>
+      <TriggerN>88</TriggerN>
+      <Timestamp>0x0000000105b44f91  ->  0x0000000105b44faa</Timestamp>
+      <Timestamp>4390670225  ->  4390670250</Timestamp>
+      <Tags>
+        <Tag>PARTICLES=89</Tag>
+        <Tag>SCALER0=93</Tag>
+        <Tag>SCALER1=93</Tag>
+        <Tag>SCALER2=0</Tag>
+        <Tag>SCALER3=0</Tag>
+        <Tag>SCALER4=0</Tag>
+        <Tag>SCALER5=0</Tag>
+        <Tag>TEST=110011</Tag>
+        <Tag>trigger=</Tag>
+      </Tags>
+      <Block_Size>0</Block_Size>
+    </Event>
+  </SubEvents>
+</Event>
+\end{lstlisting}
+\normalsize
+\begin{description}
+  \item[Type] ??
+  \item[ExtendWord] ??
+  \item[Description]
+  \item[Flag] Independent from producer. See the \href{https://github.com/eudaq/eudaq/blob/master/main/lib/core/include/eudaq/Event.hh#L87}{EUDAQ documentation} for details.
+  \item[RunN]
+  \item[StreamN]
+  \item[EventN]
+  \item[TriggerN] Both in the event and subevent this is written byt the producer with \verb|ev->SetTriggerN(trigger_n);|
+  \item[Timestamp] The event timestamp is currently always 0. The subevent timestamps is written by the producer \verb|ev->SetTimestamp(ts_ns, ts_ns+25, false);|. The top line (0x0000000105b44f91, in the example) is coarse time stamp multiplied by 25, so it represents the time in nanoseconds. The bottom one (4390670225) is the same number but written in decimal format instead of hexadecimal.
+  \item[PARTICLES] Number of pre-veto triggers recorded by the \gls{tlu}: the trigger logic can detect a valid trigger condition even when the unit is vetoed. In this case no trigger is issued to the \gls{dut}s but the number of such triggers is stored as number of particles. \verb|ev->SetTag("PARTICLES", std::to_string(pt));|
+  \item[SCALER\#] Number of triggers edges seen by the specific discriminator. \verb|ev->SetTag("SCALER", std::to_string(sl));|
+  \item[???] Event type from \gls{tlu} is missing?
+  \item[???] Input trig, i.e. the actual firing inputs should be in TRIGGER but there seems to be nothing there
+\end{description}
diff --git a/AIDA_tlu/Documentation/Latex/ch_EventBuffer.tex b/AIDA_tlu/Documentation/Latex/ch_EventBuffer.tex
new file mode 100644
index 0000000000000000000000000000000000000000..e67203db04147e0e5369ce17e094997df1120790
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_EventBuffer.tex
@@ -0,0 +1,43 @@
+\section{Event buffer}\label{ch:eventBuffer}
+The event buffer IPBus slave has four registers.
+Writing to \verb|EventFifoCSR| will reset the \gls{fifo}. Reading from either of the register will put their data on the IPBus data line.\\
+Reading from \verb|EventFifoCSR| returns the following:
+\begin{itemize}
+  \item bit 0: \gls{fifo} empty flag
+  \item bit 1: \gls{fifo} almost empty flag
+  \item bit 2: \gls{fifo} almost full flag
+  \item bit 3: \gls{fifo} full flag
+  \item bit 4: \gls{fifo} programmable full flag
+  \item other bits: 0
+\end{itemize}
+
+
+The status register (SerdesRst) is as follows:
+\begin{itemize}
+  \item bit 0: reset the ISERDES
+  \item bit 1: reset the trigger counters
+  \item bit 2: calibrate IDELAY: This seems to be disconnected at the moment.
+  \item bit 3: fixed to 0
+  \item bit 4, 5: status of \verb|thresholdDeserializer(Input0)|. When the IDELAY modules (prompt, delayed) have reached the correct delay, these two bits should read 00.
+  \item bit 6, 7: status of \verb|thresholdDeserializer(Input1)|
+  \item bit 8, 9: status of \verb|thresholdDeserializer(Input2)|
+  \item bit 10, 11: status of \verb|thresholdDeserializer(Input3)|
+  \item bit 12, 13: status of \verb|thresholdDeserializer(Input4)|
+  \item bit 14, 15: status of \verb|thresholdDeserializer(Input5)|
+  \item bit 16, 19: fixed to 0
+  \item bit 20: \verb|s_deserialized_threshold_data(Input0)(7)|
+  \item bit 21: \verb|s_deserialized_threshold_data(Input1)(7)|
+  \item bit 22: \verb|s_deserialized_threshold_data(Input2)(7)|
+  \item bit 23: \verb|s_deserialized_threshold_data(Input3)(7)|
+  \item bit 24: \verb|s_deserialized_threshold_data(Input4)(7)|
+  \item bit 25: \verb|s_deserialized_threshold_data(Input5)(7)|
+  \end{itemize}
+
+9 bits are used to determine trigger edges. 8 are from the deserializers, 1 is added as the LSB and is the MSB from the previous word.
+
+\begin{figure}
+  \centering
+  \includegraphics[width=.95\textwidth]{./Images/fifo_words.pdf}
+  \caption{Event structure}
+  \label{fig:fifo_event}
+\end{figure}
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_Appendix.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_Appendix.tex
new file mode 100644
index 0000000000000000000000000000000000000000..1b46f61b661f4fbbd6ab039f04ce5e15260ce1d4
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_Appendix.tex
@@ -0,0 +1,4 @@
+\chapter{Appendix}\label{ch:appendix}
+\includepdf[link,pages={1}]{./Docs/PM3TopView.pdf}
+\includepdf[link,pages=-, angle=90]{./Docs/Connections.pdf}
+\includepdf[link,pages=-, angle=90]{./Docs/schematics.pdf} 
\ No newline at end of file
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_Functions.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_Functions.tex
new file mode 100644
index 0000000000000000000000000000000000000000..565c73a45ad38ef82ac4390007bc381dcfbbc4d9
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_Functions.tex
@@ -0,0 +1,46 @@
+\chapter{Functions}\label{ch:functions}
+The following is a list of files containing the code for the \gls{tlu}:
+\begin{itemize}
+  \item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.ini|:\newline initialization file for the hardware. The location of the file can be passed to the EUDAQ code in the \gls{gui}.
+  \item \verb|./eudaq2/user/eudet/misc/fmctlu_runcontrol.conf|:\newline configuration file. It contains all the parameters to be loaded in the \gls{tlu} at the beginning of the run. If this file is not found, EUDAQ will use a list of default settings. The location of the file (and its name) can be passed to the EUDAQ code in the \gls{gui}.
+  \item \verb|./eudaq2/user/eudet/misc/fmctlu_connection.xml|:\newline define the IP address and address map of the \gls{tlu}. The one listed is the default location for the file. A different location can be specified with the \verb|ConnectionFile| option in the \emph{conf} file for the \gls{tlu}.
+  \item \verb|./eudaq2/user/eudet/misc/fmctlu_address.xml|:\newline address map for the \gls{tlu}. The location of the file is specified in the \verb|fmctlu_connection.xml| file.
+  \item \verb|./eudaq2/user/eudet/misc/fmctlu_clock_config.txt|:\newline configuration for the Si5345 clock chip. In order for the hardware to work a configuration file must be present. Those listed are the default name and location for the file; a different file can be specified with the \verb|CLOCK_CFG_FILE| option in the \emph{conf} file for the \gls{tlu}.
+  \item \verb|./eudaq2/user/eudet/module/src/FMCTLU_Producer.cc|:\newline eudaq producer for the \gls{tlu}. Contains the methods to initialize, configure, start, stop the \gls{tlu} producer.
+  \item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cc|:\newline Contains the definition of the hardware class for the \gls{tlu} and the methods to set and read from its hardware, such as clock chip, DAC, etc. This lever is abstract with respect to the actual hardware, so that if a future version of the board uses different components it should be possible to re-use this code.
+  \item \verb|./eudaq2/user/eudet/hardware/include/FmctluController.hh|:\newline Headers for the controller.
+  \item \verb|./eudaq2/user/eudet/hardware/src/FmctluController.cxx|:\newline Executable for the controller.
+  \item \verb|./eudaq2/user/eudet/hardware/src/FmctluHardware.cc|:\newline This is the code that deals with the actual hardware on the \gls{tlu}, and contains specific instructions for the chips mounted in the current version. It contains several classes for the ADC, the clock chip, the I/O expanders etc.
+  \item \verb|./eudaq2/user/eudet/hardware/include/FmctluHardware.hh|:\newline Header for the hardware.
+  \item \verb|./eudaq2/user/eudet/hardware/src/FmctluI2c.cc|:\newline core functions used to read and write from \gls{i2c} compatible slaves.
+  \item \verb|./eudaq2/user/eudet/hardware/include/FmctluI2c.hh|:\newline Headers for the \gls{i2c} core.
+\end{itemize}
+
+\section{Functions}
+\begin{description}
+  \item[enableClkLEMO] Enable or disable the output clock to the differential LEMO connector.
+  \item[enableHDMI] Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.\\ In the configuration file use \verb|HDMIx_on = 0| to disable a channel and \verb|HDMI1_on = 1| to enable it (x can be 1, 2, 3, 4).\\
+      NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.\\
+      NOTE: Clock source must be defined separately using SetDutClkSrc (DUTClkSrc in python script).\\
+      NOTE: this is called \verb|DUTOutputs| on the python scripts.
+  \item[GetFW] dsds
+  \item[getSN] dsd
+  \item[I2C\_enable] dsd
+  \item[InitializeClkChip]
+  \item[InitializeDAC]
+  \item[InitializeIOexp]
+  \item[InitializeI2C]
+  \item[PopFrontEvent]
+  \item[ReadRRegister]
+  \item[ReceiveEvents]
+  \item[ResetEventsBuffer]
+  \item[SetDutClkSrc] Set the clock source for a specific \gls{hdmi} connector. The source can be set to 0 (no clock), 1 (Si5345) or 2 (FPGA). In the configuration file use \verb|HDMIx_on = N| to select the source (x can be 1, 2, 3, 4, N is the clock source).\\
+      NOTE: this is called \verb|DUTClkSrc| on python scripts.
+  \item[SetPulseStretchPk] Takes a vector of six numbers, packs them (5-bits each) and sends them to the PulseStretch register.
+  \item[SetThresholdValue]
+  \item[setTrgPattern] Writes two 32-bit words to define the trigger pattern for the inputs. See section~\ref{ch:triggerinputs} for details.
+  \item[SetWRegister]
+  \item[SetUhalLogLevel]
+\end{description}
+
+
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_Hardware.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_Hardware.tex
new file mode 100644
index 0000000000000000000000000000000000000000..b925b9ef0a83052f08165dfabb591b4d756771a7
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_Hardware.tex
@@ -0,0 +1,135 @@
+\chapter{TLU Hardware}\label{ch:hardware}
+Board \brd is an evolution of the miniTLU designed at the \gls{uob}. The board shares a few features with the miniTLU but also introduces several improvements. This chapter illustrates the main features of the board to provide a general view of its capabilities and an understanding of how to operate it in order to communicate with the \gls{dut}s.
+
+\section{Inputs and interfaces}\label{ch:hwDUT}
+\subsubsection{FMC}
+The board must be plugged onto a \gls{fmc} carrier board with an \gls{fpga} in order to function correctly. The connection is achieved using a low pin count \gls{fmc} connector. The list of the pins used and the corresponding signal within the \gls{fpga} are provided in appendix at page~\pageref{ch:appendix}.\\
+
+\subsubsection{Device under test}\label{ch:dut}
+The \gls{dut}s are connected to the \gls{tlu} using standard size \gls{hdmi} connectors\footnote{In the miniTLU hardware there were mini\gls{hdmi} connectors.}.\\
+In the current version of the hardware, up to four \gls{dut}s can be connected to the board. In this document the connectors will be referred to as \verb|HDMI1|, \verb|HDMI2|, \verb|HDMI3| and \verb|HDMI4|.\\
+The connectors expect 3.3~V \gls{lvds} signals and are bi-directional, i.e. any differential pair can be configured to be an output (signal from the TLU to the DUT) or an input (signals from the DUT to the TLU) by using half-duplex line transceivers. Figure~\ref{fig:LVDSTransceiver} illustrates how the differential pairs are connected to the transceivers.
+\begin{alertinfo}{Note}
+    The input part of the transceiver is configured to be always on. This means that signals going \emph{into} the \gls{tlu} are always routed to the logic (\gls{fpga}). By contrast, the output transceivers have to be enabled and are off by default: signal sent from the logic to the \gls{dut}s cannot reach the devices unless the corresponding enable signal is active.
+\end{alertinfo}
+Table~\ref{tab:HDMIpins} shows the pin naming and the corresponding output enable signal. The clock pairs have two different enable signals to select the clock source (see section~\ref{ch:clock} for more details). In general only one of the clock sources should be active at any time.\\
+The enable signals can be configured by programming two \gls{gpio} bus expanders via \gls{i2c} interface as described in section~\ref{ch:i2c}.
+ \begin{table}[]
+    \centering
+    \caption{HDMI pin connections.}
+    \label{tab:HDMIpins}
+    \begin{tabular}{|l|l|l|}
+    \hline
+    \textbf{HDMI PIN} & \textbf{HDMI Signal Name} & \textbf{Enable Signal Name} \\ \hline
+     &  &  \\ \hline
+    1   & \verb|HDMI_CLK| & \begin{tabular}[c]{@{}l@{}}\verb|ENABLE_CLK_TO_DUT|\\ or\\ \verb|ENABLE_DUT_CLK_FROM_FPGA|\end{tabular} \\ \hline
+    2   & \verb|GND|       & -- \\ \hline
+    3   & \verb|HDMI_CLK| * & \begin{tabular}[c]{@{}l@{}}\verb|ENABLE_CLK_TO_DUT|\\ or\\ \verb|ENABLE_DUT_CLK_FROM_FPGA|\end{tabular} \\ \hline
+    4   & \verb|CONT|      & \verb|ENABLE_CONT_FROM_FPGA| \\ \hline
+    5   & \verb|GND|       & -- \\ \hline
+    6   & \verb|CONT*|     & \verb|ENABLE_CONT_FROM_FPGA| \\ \hline
+    7   & \verb|BUSY|      & \verb|ENABLE_BUSY_FROM_FPGA| \\ \hline
+    8   & \verb|GND|       & -- \\ \hline
+    9   & \verb|BUSY*|     & \verb|ENABLE_BUSY_FROM_FPGA| \\ \hline
+    10  & \verb|SPARE|     & \verb|ENABLE_SPARE_FROM_FPGA| \\ \hline
+    11  & \verb|GND|       & -- \\ \hline
+    12  & \verb|SPARE*|    & \verb|ENABLE_SPARE_FROM_FPGA| \\ \hline
+    13  & n.c.      &  \\ \hline
+    14  & \verb|HDMI_POWER| & -- \\ \hline
+    15  & \verb|TRIG|      & \verb|ENABLE_TRIG_FROM_FPGA| \\ \hline
+    16  & \verb|TRIG*|     & \verb|ENABLE_TRIG_FROM_FPGA| \\ \hline
+    17  & \verb|GND|       &  \\ \hline
+    18  & n.c.      &  \\ \hline
+    19  & n.c.      &  \\ \hline
+    \end{tabular}
+\end{table}
+\begin{figure}
+  \centering
+  \includegraphics[width=.80\textwidth]{./Images/LVDS_transceiver.pdf}
+  \caption{Internal configuration of the HDMI pins for the DUTs. The path from the DUT to the FPGA is always active. The path from the FPGA to the DUT can be enabled or disabled by the user.}\label{fig:LVDSTransceiver}
+\end{figure}\\
+In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
+
+\subsubsection{SFP cage}
+\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the Si5345 to provide a clock reference.
+
+\section{Clock LEMO}
+The board hosts a two-pin LEMO connector that can be used to provide a reference clock to the clock generator (see section~\ref{ch:clock}) or to output the clock from the \gls{tlu} to the external world, for instance to use it as a reference for another \gls{tlu}. The signal level is 3.3~V \gls{lvds}.\\
+As for the differential pairs of the \gls{dut}s, the pins of this connector are wired to a transceiver configured to always accept the incoming signals. The outgoing direction must be enabled by using the \verb|ENABLE_CLK_TO_LEMO| signal, which can be configured using the bus expander described in in section~\ref{ch:i2c}.
+
+\section{Trigger inputs}
+Board \brd can accept up to six trigger inputs over the LEMO connectors labelled \verb|IN_1|, \verb|IN_2|, \verb|IN_3|, \verb|IN_4|, \verb|IN_5| and \verb|IN_6|. The \brd uses internal high-speed\footnote{500$\pm$30~ps propagation delay.} discriminators to detect a valid trigger signal. The voltage thresholds can be adjusted independently for each input in a range from -1.3~V to +1.3~V with 40~$\mu$V resolution.\\
+The adjustment is performed by writing to two 16-bit \gls{dac}s via \gls{i2c} interface as described in section~\ref{ch:i2c}.\\
+The \gls{dac}s can either use an internal reference voltage of 2.5~V or an external one of 1.3~V provided by the \gls{tlu}: it is recommended to choose the external one by configuring the appropriate register in the devices.\\
+The correspondence between DAC slave and thresholds is shown in table~\ref{tab:DACOutputs}.
+\begin{table}[]
+\centering
+\caption{DAC outputs and corresponding threshold inputs.}
+\label{tab:DACOutputs}
+\begin{tabular}{|l|c|c|}
+\hline
+                     & \multicolumn{2}{c|}{Output}                                                        \\ \hline
+                     & \multicolumn{1}{l|}{\textbf{DAC2(Ic2)}} & \multicolumn{1}{l|}{\textbf{DAC1 (Ic1)}} \\ \hline
+\textbf{Threshold 0} & 1                                       &                                          \\ \hline
+\textbf{Threshold 1} & 0                                       &                                          \\ \hline
+\textbf{Threshold 2} &                                         & 3                                        \\ \hline
+\textbf{Threshold 3} &                                         & 2                                        \\ \hline
+\textbf{Threshold 4} &                                         & 1                                        \\ \hline
+\textbf{Threshold 5} &                                         & 0                                        \\ \hline
+\end{tabular}
+\end{table}
+
+
+\section{I$^{2}$C slaves}\label{ch:i2c}
+The \gls{i2c} interface on the \brd can be used to configured several features of the board.\\
+Table~\ref{tab:I2C addresses} lists all the valid addresses and the corresponding slave on the board. The Enclustra lines refer to slaves located on the PM3 board; these slaves can be ignored with the exception of the bus expander. The Enclustra expander is used to enable/disable the \gls{i2c} lines going to the \gls{fmc} connector.
+\begin{alertinfo}{Note}
+    After a power cycle the Enclustra expander is configured to disable the \gls{i2c} interface pins. This means that it is impossible to communicate to any \gls{i2c} slave on the \gls{tlu} until the expander has been enabled.\\
+    The interface is enable by setting bit 7 to 0 on register 0x01 of the Enclustra expander.
+\end{alertinfo}
+\begin{table}[]
+    \centering
+    \caption{I$^{2}$C addresses of the TLU. }
+    \label{tab:I2C addresses}
+    \begin{tabular}{|l|l|l|l|}
+    \hline
+    \textbf{CHIP} & \textbf{ID} & \textbf{FUNCTION}        & \textbf{ADDRESS} \\ \hline
+    IC1           & AD5665RBRUZ & DAC1                     & 0x1F             \\ \hline
+    IC2           & AD5665RBRUZ & DAC2                     & 0x13             \\ \hline
+    IC5           & 24AA025E48T & EEPROM                   & 0x50             \\ \hline
+    IC6           & PCA9539PW   & I2C Expander1            & 0x74             \\ \hline
+    IC7           & PCA9539PW   & I2C Expander2            & 0x75             \\ \hline
+    IC8           & ADN2814ACPZ & CDR                      & 0x60             \\ \hline
+    IC8\_9        & Si5345A     & Clock Generator          & 0x68             \\ \hline
+    \multicolumn{4}{|l|}{Enclustra slaves}                                                    \\ \hline
+                  &             & Enclustra Bus Expander   & 0x21             \\ \hline
+                  &             & Enclustra System Monitor & 0x21             \\ \hline
+                  &             & Enclustra EEPROM         & 0x54             \\ \hline
+                  &             & Enclustra slave          & 0x64             \\ \hline
+\end{tabular}
+\end{table}
+Once the interface is enabled it is possible to read and write to the devices listed in the top part of table~\ref{tab:I2C addresses}.\\
+The user should reference the manual of each individual component to determine the register that must be addressed. The rest of this section is meant to provide an overview of the slave functionalities.
+
+\subsubsection{DAC}
+Each \gls{dac} has four outputs that can be configured independently. \verb|DAC1| is used to configure the thresholds of the first four trigger inputs; \verb|DAC2| configures the remaining two thresholds.\\
+The \gls{dac}s should be configured to use the \gls{tlu} voltage reference of 1.3~V. In these conditions, writing a value of 0x00000 to a \gls{dac} output will set the corresponding threshold to -1.3~V while a value of 0xFFFF will set it to +1.3~V.
+
+\subsubsection{EEPROM}
+The \gls{eeprom} located on the board contains a factory-set unique number, used to identify each \brd unequivocally. The number is comprised of six bytes written in as many memory locations.\\
+The identifier is always in the form: \verb|0xD8 80 39 XX XX XX| with the top three bytes indicating the manufacturer and the bottom three unique to each device.
+
+\subsubsection{Bus expander}
+The expanders are used as electronic switched to enable and disable individual lines. Each expander has two 8-bit banks; the values of the bits, as well as their direction (input/output) can be configured via the \gls{i2c} interface. For the purpose of the \gls{tlu}, all the expander pins should be configured as outputs since they must drive the enable signals on the \gls{dut} transceivers.
+
+\subsubsection{Clock and data recovery chip}
+The \gls{cdr} is used in conjunction with the \gls{sfp} cage to recover data and clock from the incoming bit stream. The functionality has not yet been implemented in the firmware so the \gls{i2c} slave can be ignored for now.
+
+\subsubsection{Clock generator}
+The clock for \brd can be generated using various external or internal references (see section~\ref{ch:clock} for further details). In order to reduce any jitter from the clock source and to provide a stable clock, the board hosts a Si5345 clock generator that needs to be configured via \gls{i2c} interface.\\
+The configuration involves writing $\thicksim$380 register values. A configuration file, containing all the register addresses and the corresponding values, can be generated using the ClockBuilder tool available from \href{http://www.enclustra.com/en/home/}{Silicon Labs}.\\
+The registers addresses between 0x026B and 0x0272 contain user-defined values that can be used to identify the configuration version: it is advisable to check those registers and check that they contain the correct code to ensure that the chip is configured according to the \gls{tlu} specifications. As an indication, files generated for the current version of the \gls{tlu} should have a configuration identifier in the form \verb|TLU1E_XX|, where \verb|XX| is a sequential number.\\
+\begin{alertinfo}{TLU Producer}
+    When using the TLU producer to configure hardware, the location of the configuration file can be specified by setting the \texttt{CLOCK\_CFG\_FILE} value in the \emph{conf} file for the producer.\\
+    If no value is specified, the software will look for the configuration file \texttt{../conf/confClk.txt} i.e. if the \texttt{euRun} binary file is located in \texttt{./eudaq/bin}, then the default configuration file should reside in \texttt{./eudaq/conf}. The configuration will produce an error if the file is not found.
+\end{alertinfo}
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_IPBusRegs.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_IPBusRegs.tex
new file mode 100644
index 0000000000000000000000000000000000000000..c8a4b1550231e16fbed5ba117d80e58987c532a4
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_IPBusRegs.tex
@@ -0,0 +1,283 @@
+\chapter{IPBus Registers}\label{ch:ipbusregs}
+%
+%\begin{table}[]
+%\centering
+%\caption{My caption}
+%\label{my-label}
+%\begin{tabular}{|l|l|r|l|l|l|l|l|}
+%\hline
+%\textbf{NODE} & \textbf{SUBNODE} & \multicolumn{1}{l|}{\textbf{ADDRESS}} & \textbf{MASK} & \textbf{PERMISSION} & \textbf{DESCRIPTION} & \textbf{MODE} & \textbf{SIZE} \\ \hline
+%ID & TLU & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{version} &  & 0x1 &  & r & firmware version &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{DUTInterfaces} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x1000}} & \textbf{} & \textbf{} & \textbf{DUT Interfaces control registers} & \textbf{} & \textbf{} \\
+% & DUTMaskW & 0x0 &  & w &  &  &  \\
+% & IgnoreDUTBusyW & 0x1 &  & w &  &  &  \\
+% & IgnoreShutterVetoW & 0x2 &  & w &  &  &  \\
+% & DUTInterfaceModeW & 0x3 &  & w &  &  &  \\
+% & DUTInterfaceModeModifierW & 0x4 &  & w &  &  &  \\
+% & DUTInterfaceModeR & 0xB &  & r &  &  &  \\
+% & DUTInterfaceModeModifierR & 0xC &  & r &  &  &  \\
+% & DUTMaskR & 0x8 &  & r &  &  &  \\
+% & IgnoreDUTBusyR & 0x9 &  & r &  &  &  \\
+% & IgnoreShutterVetoR & 0xA &  & r &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{Shutter} &  & \multicolumn{1}{l|}{\textbf{0x2000}} & \textbf{} & \textbf{} & \textbf{Shutter/T0 control} & \textbf{} &  \\
+% & ShutterStateW & 0x0 &  & w &  &  &  \\
+% & PulseT0 & 0x1 &  & w &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{i2c\_master} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x3000}} & \textbf{} & \textbf{} & \textbf{I2C Master interface} & \textbf{} & \textbf{} \\
+% & i2c\_pre\_lo & 0x0 & 0xFF & r/w &  &  &  \\
+% & i2c\_pre\_hi & 0x1 & 0xFF & r/w &  &  &  \\
+% & i2c\_ctrl & 0x2 & 0xFF & r/w &  &  &  \\
+% & i2c\_rxtx & 0x3 & 0xFF & r/w &  &  &  \\
+% & i2c\_cmdstatus & 0x4 & 0xFF & r/w &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{eventBuffer} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x4000}} & \textbf{} & \textbf{} & \textbf{Event buffer} & \textbf{} & \textbf{} \\
+% & EventFifoData & 0x0 &  & r &  & non-incremental & 3200 \\
+% & EventFifoFillLevel & 0x1 &  & r &  &  &  \\
+% & EventFifoCSR & 0x2 &  & r/w &  &  &  \\
+% & EventFifoFillLevelFlags & 0x3 &  & r &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{Event\_Formatter} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x5000}} & \textbf{} & \textbf{} & \textbf{Event formatter configuration} & \textbf{} & \textbf{} \\
+% & Enable\_Record\_Data & 0x0 &  & r/w &  &  &  \\
+% & ResetTimestampW & 0x1 &  & w &  &  &  \\
+% & CurrentTimestampLR & 0x2 &  & r &  &  &  \\
+% & CurrentTimestampHR & 0x3 &  & r &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{triggerInputs} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x6000}} & \textbf{} & \textbf{} & \textbf{Inputs configuration} & \textbf{} & \textbf{} \\
+% & SerdesRstW & 0x0 &  & w &  &  &  \\
+% & SerdesRstR & 0x8 &  & r &  &  &  \\
+% & ThrCount0R & 0x9 &  & r &  &  &  \\
+% & ThrCount1R & 0xA &  & r &  &  &  \\
+% & ThrCount2R & 0xB &  & r &  &  &  \\
+% & ThrCount3R & 0xC &  & r &  &  &  \\
+% & ThrCount4R & 0xD &  & r &  &  &  \\
+% & ThrCount5R & 0xE &  & r &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{triggerLogic} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x7000}} & \textbf{} & \textbf{} & \textbf{Trigger logic configuration} & \textbf{} & \textbf{} \\
+% & PostVetoTriggersR & 0x10 &  & r &  &  &  \\
+% & PreVetoTriggersR & 0x11 &  & r &  &  &  \\
+% & InternalTriggerIntervalW & 0x02 &  & w &  &  &  \\
+% & InternalTriggerIntervalR & 0x12 &  & r &  &  &  \\
+% & TriggerVetoW & 0x04 &  & w &  &  &  \\
+% & TriggerVetoR & 0x14 &  & r &  &  &  \\
+% & ExternalTriggerVetoR & 0x15 &  & r &  &  &  \\
+% & PulseStretchW & 0x06 &  & w &  &  &  \\
+% & PulseStretchR & 0x16 &  & r &  &  &  \\
+% & PulseDelayW & 0x07 &  & w &  &  &  \\
+% & PulseDelayR & 0x17 &  & r &  &  &  \\
+% & TriggerHoldOffW & 0x08 &  & w &  &  &  \\
+% & TriggerHoldOffR & 0x18 &  & r &  &  &  \\
+% & AuxTriggerCountR & 0x19 &  & r &  &  &  \\
+% & TriggerPattern\_lowW & 0x0A &  & w &  &  &  \\
+% & TriggerPattern\_lowR & 0x1A &  & r &  &  &  \\
+% & TriggerPattern\_highW & 0x0B &  & w &  &  &  \\
+% & TriggerPattern\_highR & 0x1B &  & r &  &  &  \\
+% &  & \multicolumn{1}{l|}{} &  &  &  &  &  \\ \hline
+%\textbf{logic\_clocks} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x8000}} & \textbf{} & \textbf{} & \textbf{Clocks configuration} & \textbf{} & \textbf{} \\
+% & LogicClocksCSR & 0x0 &  & r/w &  &  &  \\
+% & LogicRst & 0x1 &  & w &  &  &  \\ \hline
+%\end{tabular}
+%\end{table}
+
+\begin{table}
+\centering
+\footnotesize
+\caption{IPBus register}
+\label{tab:ipbusreg}
+\begin{tabular}{|l|l|r|l|l|}
+\hline
+\textbf{NODE} & \textbf{SUBNODE} & \multicolumn{1}{l|}{\textbf{ADDRESS}} & \textbf{MASK} & \textbf{PERMISSION} \\ \hline
+\textbf{version} &  & 0x1 &  & r \\ \hline
+\textbf{DUTInterfaces} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x1000}} & \textbf{} & \textbf{} \\
+ & DUTMaskW & 0x0 &  & w \\
+ & IgnoreDUTBusyW & 0x1 &  & w \\
+ & IgnoreShutterVetoW & 0x2 &  & w \\
+ & DUTInterfaceModeW & 0x3 &  & w \\
+ & DUTInterfaceModeModifierW & 0x4 &  & w \\
+ & DUTInterfaceModeR & 0xB &  & r \\
+ & DUTInterfaceModeModifierR & 0xC &  & r \\
+ & DUTMaskR & 0x8 &  & r \\
+ & IgnoreDUTBusyR & 0x9 &  & r \\
+ & IgnoreShutterVetoR & 0xA &  & r \\ \hline
+\textbf{Shutter} &  & \multicolumn{1}{l|}{\textbf{0x2000}} & \textbf{} & \textbf{} \\
+ & ShutterStateW & 0x0 &  & w \\
+ & PulseT0 & 0x1 &  & w \\ \hline
+\textbf{i2c\_master} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x3000}} & \textbf{} & \textbf{} \\
+ & i2c\_pre\_lo & 0x0 & 0xFF & r/w \\
+ & i2c\_pre\_hi & 0x1 & 0xFF & r/w \\
+ & i2c\_ctrl & 0x2 & 0xFF & r/w \\
+ & i2c\_rxtx & 0x3 & 0xFF & r/w \\
+ & i2c\_cmdstatus & 0x4 & 0xFF & r/w \\ \hline
+\textbf{eventBuffer} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x4000}} & \textbf{} & \textbf{} \\
+ & EventFifoData & 0x0 &  & r \\
+ & EventFifoFillLevel & 0x1 &  & r \\
+ & EventFifoCSR & 0x2 &  & r/w \\
+ & EventFifoFillLevelFlags & 0x3 &  & r \\ \hline
+\textbf{Event\_Formatter} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x5000}} & \textbf{} & \textbf{} \\
+ & Enable\_Record\_Data & 0x0 &  & r/w \\
+ & ResetTimestampW & 0x1 &  & w \\
+ & CurrentTimestampLR & 0x2 &  & r \\
+ & CurrentTimestampHR & 0x3 &  & r \\ \hline
+\textbf{triggerInputs} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x6000}} & \textbf{} & \textbf{} \\
+ & SerdesRstW & 0x0 &  & w \\
+ & SerdesRstR & 0x8 &  & r \\
+ & ThrCount0R & 0x9 &  & r \\
+ & ThrCount1R & 0xA &  & r \\
+ & ThrCount2R & 0xB &  & r \\
+ & ThrCount3R & 0xC &  & r \\
+ & ThrCount4R & 0xD &  & r \\
+ & ThrCount5R & 0xE &  & r \\ \hline
+\textbf{triggerLogic} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x7000}} & \textbf{} & \textbf{} \\
+ & PostVetoTriggersR & 0x10 &  & r \\
+ & PreVetoTriggersR & 0x11 &  & r \\
+ & InternalTriggerIntervalW & 0x02 &  & w \\
+ & InternalTriggerIntervalR & 0x12 &  & r \\
+ & TriggerVetoW & 0x04 &  & w \\
+ & TriggerVetoR & 0x14 &  & r \\
+ & ExternalTriggerVetoR & 0x15 &  & r \\
+ & PulseStretchW & 0x06 &  & w \\
+ & PulseStretchR & 0x16 &  & r \\
+ & PulseDelayW & 0x07 &  & w \\
+ & PulseDelayR & 0x17 &  & r \\
+ & TriggerHoldOffW & 0x08 &  & w \\
+ & TriggerHoldOffR & 0x18 &  & r \\
+ & AuxTriggerCountR & 0x19 &  & r \\
+ & TriggerPattern\_lowW & 0x0A &  & w \\
+ & TriggerPattern\_lowR & 0x1A &  & r \\
+ & TriggerPattern\_highW & 0x0B &  & w \\
+ & TriggerPattern\_highR & 0x1B &  & r \\ \hline
+\textbf{logic\_clocks} & \textbf{} & \multicolumn{1}{l|}{\textbf{0x8000}} & \textbf{} & \textbf{} \\
+ & LogicClocksCSR & 0x0 &  & r/w \\
+ & LogicRst & 0x1 &  & w \\ \hline
+\end{tabular}
+\end{table}
+
+\begin{description}\label{ch:IPBus_DUT}
+  \item[version] Returns the current version of firmware used to program the \gls{tlu}
+  \item[------------------------]
+  \item[DUTINTERFACES]
+  \item[DUTMaskW] Writing to this register allows to define which \gls{dut}s are active when in AIDA mode. The lower 4 bits of the register can be used to define the status of the \gls{dut}s: 1 for active, 0 for masked. \verb|hdmi1| is defined by bit 0, \verb|hdmi2| is defined by bit 1, \verb|hdmi3| is defined by bit 2, \verb|hdmi4| is defined by bit 3.
+  \item[IgnoreDUTBusyW] Writing to this register allows to ignore the busy signal from a particular \gls{dut} while in AIDA mode. The lower 4 bits are used to define the status for each device. A 1 indicates that the logic should ignore busy signals from the specific \gls{dut}.
+  \item[IgnoreShutterVetoW] The \gls{lsb} of this register can be written to define whether the \gls{dut} should ignore the shutter veto signal. Normally, when the shutter signal is asserted the \gls{dut} reports busy. If this bit is flag the \gls{dut} will ignore the shutter signal.
+  \item[DUTInterfaceModeW] Write register to define the mode of operation for a \gls{dut}. Two bits per device can be used to define the mode; currently only two modes are available (AIDA, EUDET) but the second but is reserved for additional modes introduced in the future.\\
+      The bit pairs are packed from the \gls{lsb} starting with \verb|hdmi1| (bits 0, 1), \verb|hdmi2| (bits 2, 3), \verb|hdmi3| (bits 4, 5),  \verb|hdmi4| (bits 6, 7).
+      \begin{itemize}
+        \item bit pair \texttt{X0}: EUDET
+        \item bit pair \texttt{X1}: AIDA
+      \end{itemize}
+  \item[DUTInterfaceModeModifierW] Write register. This register only affects the EUDET mode of operation. For each \gls{dut} two bits can be configured although cyrrently only the lower of the pair is considere. The bit packing is done in a manner similar to the DUTInterfaceMode. Set bit high to allow asynchronous veto using \verb|DUT_CLK| when in EUDET mode.
+  \item[DUTInterfaceModeR] Read the content of the DUTInterfaceMode register.
+  \item[DUTInterfaceModeModifierR] Read status of the DUTInterfaceMode register.
+  \item[DUTMaskR] Read the status of the DUTMask register.
+  \item[IgnoreDUTBusyR] Read the status of the IgnoreDUTBusy register.
+  \item[IgnoreShutterVetoR] Read the status of the IgnoreShutterVeto word (only the last bit is meanigful).
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[SHUTTER]
+  \item[ShutterStateW] The \gls{lsb} of this register is propagated to the \gls{dut}s as shutter signal. This is the signal that the \gls{dut}s receive on the \verb|cont| line.
+  \item[PulseT0] Writing to this register will cause the firmware to generate a T0 signal.
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[I2C\_MASTER] This section includes registers used to talk to the \gls{i2c} bus.
+  \item[i2c\_pre\_lo] Lower part of the clock pre-scaler value. The pre-scaler is used to reduce the clock frequency of the bus and make it compatible with the \gls{i2c} slaves on the board.
+  \item[i2c\_pre\_hi] Higher part of the clock pre-scaler value.
+  \item[i2c\_ctrl]
+  \item[i2c\_rxtx]
+  \item[i2c\_cmdstatus]
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[EVENTBUFFER]
+  \item[EventFifoData]      Returns the content of the \gls{fifo}. In the current firmware implementation the memory can hold 8192 words (32-bit).
+  \item[EventFifoFillLevel] Read register. Returns the number of words written in the \gls{fifo}. The lowest 14-bits are the actual data.
+  \item[EventFifoCSR]       Read or write register. When read it returns the status of the \gls{fifo}. Five flags are returned:
+                              \begin{itemize}
+                                \item bit 0: empty. Asserted when the \gls{fifo} is empty.
+                                \item bit 1: almost empty. Asserted when one word remains in the \gls{fifo}.
+                                \item bit 2: almost full. Asserted when the \gls{fifo} can only accept one more word before becoming full.
+                                \item bit 3: full. In the current firmware the \gls{fifo} can hold 8192 words before filling up.
+                                \item bit 4: programmable full. This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold (8181). It is de-asserted when the number of words in the FIFO is less than the negate threshold (8180).
+                              \end{itemize}
+                                When any value is written to this register the \gls{fifo} is reset.
+  \item[EventFifoFillLevelFlags] Does not do anything? REMOVE \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[EVENT\_FORMATTER]
+  \item[Enable\_Record\_Data] Read and write register. When written, \textcolor[rgb]{1.00,0.00,0.00}{CHECK}\\
+                                When read returns the content of the enable record word.
+  \item[ResetTimestampW]        Write register. Writing any value to this register will cause the firmware to produce a retest timestamp signal (high for one clock cycle of clk\_4x\_logic). At the moment it does not seems to be connected to anything. \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+  \item[CurrentTimestampLR] \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+  \item[CurrentTimestampHR] \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[TRIGGERINPUTS]
+  \item[SerdesRstW] Write register for the SerDes control.\begin{itemize}
+                                                            \item bit 0: set this bit to reset the ISERDES
+                                                            \item bit 1: set this bit to reset the input trigger counters
+                                                            \item bit 2: \verb|s_calibrate_delay|
+                                                          \end{itemize}
+  \item[SerdesRstR] Read register for the SerDes control.
+  \item[ThrCount0R] Read register. Returns the number of pulses above threshold for the trigger input.
+  \item[ThrCount1R] Read register. Returns the number of pulses above threshold for the trigger input.
+  \item[ThrCount2R] Read register. Returns the number of pulses above threshold for the trigger input.
+  \item[ThrCount3R] Read register. Returns the number of pulses above threshold for the trigger input.
+  \item[ThrCount4R] Read register. Returns the number of pulses above threshold for the trigger input.
+  \item[ThrCount5R] Read register. Returns the number of pulses above threshold for the trigger input.
+\end{description}
+
+\begin{description}\label{ch:triggerLogicAdd}
+  \item[------------------------]
+  \item[TRIGGERLOGIC]
+  \item[PostVetoTriggersR] Read register. Returns the number of triggers recorded in the \gls{tlu} after the veto is applied. These are the triggers actually sent to the \gls{dut}s.
+  \item[PreVetoTriggersR] Read register. Returns the number of triggers recorded in the \gls{tlu} before the veto is applied. This is used for debugging purposes.
+  \item[InternalTriggerIntervalW] Write the number of clock cycles to be used as period for the internal trigger generator. If this number is smaller than 5 then the triggers are disabled. Otherwise the period is number -2.
+  \item[InternalTriggerIntervalR] Read the value written in InternalTriggerIntervalW.
+  \item[TriggerVetoW] Write register. The value written to the \gls{lsb} of this register is used to generate a veto signal. This can be used to put switch the \gls{tlu} status: if the bit is asserted the logic will not send new triggers to the \gls{dut}s. If the bit is reset the board will process new triggers.
+  \item[TriggerVetoR] Read the content of the TriggerVeto register.
+  \item[ExternalTriggerVetoR] Read register. Bit 0 of this register reports the \verb|veto| status (1 for veto active, 0 for no veto). The veto is active if the \gls{tlu} buffer is full or if one of the \gls{dut}s is sending a veto signal.
+  \item[PulseStretchW] Write the stretch word for the trigger pulses. The original trigger pulses collected at a trigger input can be stretched by $N$ cycles of the 4x clock (160~MHz, 6.25~ns). $N$ is a number between 0 and 31. The stretched pulse is always at least as long as the original input.\\
+      The stretch values can be written in the \verb|conf| file using the parameters \verb|inX_STR| (X= [0 ... 5]).\\
+      The six words for the inputs are packed in a single 32-bit word written to this register according to the format shown in table~\ref{tab:packing}.
+  \item[PulseStretchR] Returns the content of the PulseStretch word.
+  \item[PulseDelayW] Write the delay word for the trigger pulses. The original pulse is delayed by $N$ clycles of the 4x clock (160~MHz, 6.25~ns). $N$ is a number between 0 and 31. The six words for the inputs are packed in a single 32-bit word written to this register according to the format shown in table~\ref{tab:packing}.\\
+      The delay values can be written in the \verb|conf| file using the parameters \verb|inX_DEL| (X= [0 ... 5]).\\
+  \item[PulseDelayR] Returns the content of the PulseDelay word.
+  \item[TriggerHoldOffW] Does not do anything? \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+  \item[TriggerHoldOffR] Read the previous register... \textcolor[rgb]{1.00,0.00,0.00}{CHECK}
+  \item[AuxTriggerCountR] Auxiliary trigger counter. Used for debug.
+  \item[TriggerPattern\_lowW] Write register for the lower 32-bits of the trigger pattern. This pattern is used to select the combinations of trigger signals that produce a valid trigger in the \gls{tlu}. See section~\ref{ch:triggerLogic} for details.
+  \item[TriggerPattern\_lowR] Read register for the lower 32-bits of the trigger pattern. This pattern is used to select the combinations of trigger signals that produce a valid trigger in the \gls{tlu}. See section~\ref{ch:triggerLogic} for details.
+  \item[TriggerPattern\_highW] Write register for the higher 32-bits of the trigger pattern. This pattern is used to select the combinations of trigger signals that produce a valid trigger in the \gls{tlu}. See section~\ref{ch:triggerLogic} for details.
+  \item[TriggerPattern\_highR] Read register for the higher 32-bits of the trigger pattern. This pattern is used to select the combinations of trigger signals that produce a valid trigger in the \gls{tlu}. See section~\ref{ch:triggerLogic} for details.
+\end{description}
+
+\begin{description}
+  \item[------------------------]
+  \item[LOGIC\_CLOCKS]
+  \item[LogicClocksCSR] This is a read/write register. The write function is now obsolete and should be removed. Reading from this register returns the status of the PLL lock: bit 0 is the locked value of the pll (1= locked).
+  \item[LogicRst] Writing a 1 in the LSB of this register will reset the PLL and the clocks used by the \gls{tlu} firmware. It needs to be checked for bugs.
+\end{description}
+
+\begin{sidewaystable}[]
+\footnotesize
+    \caption{Packing scheme for values in registers used to define the pulse stretch and delay.}
+    \label{tab:packing}
+    \begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|}
+    \hline
+    \multicolumn{32}{|c|}{Register value}                                                                                                                                                             \\ \hline
+    31 & 30 & 29   & 28  & 27  & 26  & 25  & 24   & 23  & 22  & 21  & 20  & 19   & 18  & 17  & 16  & 15  & 14   & 13  & 12  & 11  & 10  & 9    & 8   & 7   & 6   & 5   & 4    & 3   & 2   & 1   & 0   \\ \hline
+    x  & x  & \multicolumn{5}{c|}{Input 5} & \multicolumn{5}{c|}{Input 4} & \multicolumn{5}{c|}{Input 3} & \multicolumn{5}{c|}{Input 2} & \multicolumn{5}{c|}{Input 1} & \multicolumn{5}{c|}{Input 0} \\ \hline
+    x  & x  & b4   & b3  & b2  & b1  & b0  & b4   & b3  & b2  & b1  & b0  & b4   & b3  & b2  & b1  & b0  & b4   & b3  & b2  & b1  & b0  & b4   & b3  & b2  & b1  & b0  & b4   & b3  & b2  & b1  & b0  \\ \hline
+    \end{tabular}
+\end{sidewaystable}
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_Preparation.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_Preparation.tex
new file mode 100644
index 0000000000000000000000000000000000000000..421deaa33649722799e42457eaaed05d06837860
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_Preparation.tex
@@ -0,0 +1,57 @@
+\chapter{Introduction}\label{ch:introduction}
+This manual describes the AIDA \gls{tlu} designed for the \href{http://aida2020.web.cern.ch/}{AIDA-2020 project} by David Cussans\footnote{University of Bristol, Particle Physics group} and Paolo Baesso\footnote{University of Bristol, Particle Physics group}.\\
+The unit is designed to be used in High Energy Physics beam-tests and provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope.\\
+The current version of the hardware is an evolution of the \href{https://twiki.cern.ch/twiki/bin/view/MimosaTelescope/TLU}{EUDET-TLU} and the \href{https://www.ohwr.org/projects/fmc-mtlu/wiki}{miniTLU} and is shipped in a metallic case that includes an \gls{fpga} board and the \gls{tlu} \gls{pcb}: the \gls{fpga} is responsible for all the logic functions of the unit, while the \gls{pcb} contains the clock chip, discriminator and interface blocks needed to communicate with other devices.\\
+The current version of the \gls{pcb} is \brd and is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
+
+\section{Overview}
+The AIDA \gls{tlu} provides timing and synchronization signals to test-beam readout hardware.\\
+The hardware can provide an internally generated low-jitter 40~MHz clock or can accept and external clock reference.\\
+It accepts the asynchronous trigger signals from up to six external sources, such as beam-scintillators, and generate synchronous signals (including global trigger or control signals) to send to up to four devices under tests. The logic function used to generate the trigger can be defined by the user among all the possible logic combinations of the inputs.\\
+Depending on the chosen mode of operation, the \gls{tlu} can accept busy signals or other veto signals from \gls{dut}s and react accordingly, for instance avoinding any further trigger until all the busy signals have been de-asserted.\\
+Whenever a global trigger is generated by the unit, a 48-bit time-stamp is attached to it. This time stamp is based on the 40~MHz clock. Additionally ???\\
+The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus}. IPbus is a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.
+
+
+\section{FPGA}
+The \gls{tlu} is shipped with an \gls{fpga} board already programmed with the latest version of the firmware needed to operate the unit.\\
+The firmware developed at University of Bristol is targeted to work with the Enclustra  AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
+At the time of writing this work\footnote{Oct 2017} the AX3 is the only \gls{fpga} for which a firmware has been developed. However, we plan to ship future versions of the \gls{tlu} with a custom made \gls{fpga} designed by Samer Kilani.
+\begin{alertinfo}{Note}
+    If the \gls{fpga} detects a programming cable connected it will not load the firmware from its memory after a power cycle.\\
+    It is recommended to leave the \gls{usb} cable disconnected from the back panel unless there is the intention to re-program the firmware.
+\end{alertinfo}
+
+
+\section{Power}
+The \gls{tlu} requires 12~V to operate. Power can be provided using the circular jack on the back panel of the unit.\\
+During normal operation the current drawn by the unit is about 0.5~A.
+%\section{Preparation}
+%Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
+%
+%Currently, it is recommended to use the following:
+%\begin{itemize}
+% \item MA-PM3-W-R5: Mars PM3 base board
+% \item MA-AX3-35-1I-D8-R3: Marx AX3 module (hosts a Xilinx XC7A35T-1CSG324I )
+% \item MA-PM3-ACC-BASE: Accessory kit, including a \gls{jtag} breakout board to connect Xilinx programming cables. Also includes a 12~V power supply to power the PM3.
+%\end{itemize}
+%
+%\section{I/O voltage setting}
+%The I/O pins of the PM3 can be configured to operate at 2.5~V or 3.3~V; the factory default is 2.5~V but the \brd requires 3.3~V logic. The user should make sure to select the appropriate voltage by operating on DIP-switch CFG-A/S1200 (pin 1 set to ON).\\For reference, a top view of the board is provided in the appendix at page~\pageref{ch:appendix}.\\
+%\begin{alertinfo}{Warning}
+%    Please double check the PM3 board manual for the correct way to change the I/O voltage setting. Enclustra has been changing their hardware recently.
+%\end{alertinfo}
+%
+%\section{Xilinx programming cable}
+%The \gls{jtag} pins on the PM3 are located on the header J800 (20-way, 2.54~mm pitch). The breakout board provided by Enclustra sits on top of the header and connects the pins to a 14-way Molex milli-grid header so that it is possible to plug the Xiling programming cable directly onto it. However, when the \brd is mounted on a base plate as shown in figure~\ref{fig:TLUplate}, the breakout board has to be detached from the PM3 because it interferes with the mounting screws.\\
+%The connection between J800 and the breakout can be achieved by using two standard 20-way \gls{idc} cables as shown in figure~\ref{fig:XilinxCable}.
+%\begin{figure}[h]
+%  \centering
+%  \includegraphics[width=.50\textwidth]{./Images/TLU_plate.jpg}
+%  \caption{\brd and PM3 mounted on a base plate: in this configuration it is not possible to install the breakout board on the PM3 because the mountings screws are in the way.}\label{fig:TLUplate}
+%\end{figure}
+%\begin{figure}
+%  \centering
+%  \includegraphics[width=.80\textwidth]{./Images/XilinxCable.jpg}
+%  \caption{Connecting the Xilinx programming cable to the PM3 in an ugly (but effective) way.}\label{fig:XilinxCable}
+%\end{figure}
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_PreparationOld.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_PreparationOld.tex
new file mode 100644
index 0000000000000000000000000000000000000000..da991d1b8103d817d301154b9daa5c7a9e6b2f1c
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_PreparationOld.tex
@@ -0,0 +1,30 @@
+\chapter{Preparation}\label{ch:preparation}
+Before powering the \gls{tlu} it is necessary to follow a few steps to ensure the board and the \gls{fpga} work correctly.\\
+The \brd is designed to plug onto a carrier \gls{fpga} board like any other \gls{fmc} mezzanine board, although its form factor does not comply with the ANSI-VITA-57-1 standard.\\
+The firmware developed at University of Bristol is targeted to work with the Enclustra  AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3.\\
+Currently, it is recommended to use the following:
+\begin{itemize}
+ \item MA-PM3-W-R5: Mars PM3 base board
+ \item MA-AX3-35-1I-D8-R3: Marx AX3 module (hosts a Xilinx XC7A35T-1CSG324I )
+ \item MA-PM3-ACC-BASE: Accessory kit, including a \gls{jtag} breakout board to connect Xilinx programming cables. Also includes a 12~V power supply to power the PM3.
+\end{itemize}
+
+\section{I/O voltage setting}
+The I/O pins of the PM3 can be configured to operate at 2.5~V or 3.3~V; the factory default is 2.5~V but the \brd requires 3.3~V logic. The user should make sure to select the appropriate voltage by operating on DIP-switch CFG-A/S1200 (pin 1 set to ON).\\For reference, a top view of the board is provided in the appendix at page~\pageref{ch:appendix}.\\
+\begin{alertinfo}{Warning}
+    Please double check the PM3 board manual for the correct way to change the I/O voltage setting. Enclustra has been changing their hardware recently.
+\end{alertinfo}
+
+\section{Xilinx programming cable}
+The \gls{jtag} pins on the PM3 are located on the header J800 (20-way, 2.54~mm pitch). The breakout board provided by Enclustra sits on top of the header and connects the pins to a 14-way Molex milli-grid header so that it is possible to plug the Xiling programming cable directly onto it. However, when the \brd is mounted on a base plate as shown in figure~\ref{fig:TLUplate}, the breakout board has to be detached from the PM3 because it interferes with the mounting screws.\\
+The connection between J800 and the breakout can be achieved by using two standard 20-way \gls{idc} cables as shown in figure~\ref{fig:XilinxCable}.
+\begin{figure}[h]
+  \centering
+  \includegraphics[width=.50\textwidth]{./Images/TLU_plate.jpg}
+  \caption{\brd and PM3 mounted on a base plate: in this configuration it is not possible to install the breakout board on the PM3 because the mountings screws are in the way.}\label{fig:TLUplate}
+\end{figure}
+\begin{figure}
+  \centering
+  \includegraphics[width=.80\textwidth]{./Images/XilinxCable.jpg}
+  \caption{Connecting the Xilinx programming cable to the PM3 in an ugly (but effective) way.}\label{fig:XilinxCable}
+\end{figure}
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_clock.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_clock.tex
new file mode 100644
index 0000000000000000000000000000000000000000..839b395fdf62c01982ef0df9c41cba35903263f7
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_clock.tex
@@ -0,0 +1,27 @@
+\chapter{Clock}\label{ch:clock}
+The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}. A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
+In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourht input is used to provide a zero-delay feedback loop.\\
+The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga},  connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop.\\
+The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
+The firmware uses the clock generated by the Si5345A except for the block \verb|enclustra_ax3_pm3_infra| which relies on a crystal mounted on the Enclustra board to provide the IPBus functionalities (in this way, at power up the board can communicate via IPBus even if the Si5345A is not configured).
+
+\section{Input selection}
+The Si5345 has four inputs that can be selected to provide the clock alignment; the selection can be automatic or user-defined. For further details on this aspect the user should consult the chip documentation.
+
+\begin{table}[]
+\small
+\centering
+\caption{Si5345  Input Selection Configuration.}
+\label{tab:si5345inputs}
+\begin{tabular}{|l|l|l|}
+\hline
+\textbf{Register Name} & \textbf{Hex Address {[}Bit Field{]}} & \textbf{Function}                                                                                                                                                                                                                              \\ \hline
+CLK\_SWITCH\_MODE      & 0x0536{[}1:0{]}                      & \begin{tabular}[c]{@{}l@{}}Selects manual or automatic switching modes.\\ Automatic mode can be revertive or non-revertive.\\ Selections are the following:\\00 Manual\\01 Automatic non-revertive\\02 Automatic revertive\\03 Reserved\end{tabular} \\ \hline
+IN\_SEL\_REGCTRL       & 0x052A {[}0{]}                       & \begin{tabular}[c]{@{}l@{}}0 for pin controlled clock selection\\ 1 for register controlled clock selection\end{tabular}                                                                                                                       \\ \hline
+IN\_SEL                & 0x052A {[}2:1{]}                     & \begin{tabular}[c]{@{}l@{}}0 for IN0\\ 1 for IN1\\ 2 for IN2\\ 3 for IN3 (or FB\_IN)\end{tabular}                                                                                                                                              \\ \hline
+\end{tabular}
+\end{table}
+
+
+\section{Logic clocks registers}\label{ch:logicClock}
+LogicClocksCSR: in the new TLU the selection of the clock source is done by programming the Si5345. As a consequence, there is no reason to write to this register. Reading it back returns the status of the PLL on bit 0, so this should read 0x1. 
\ No newline at end of file
diff --git a/AIDA_tlu/Documentation/Latex/ch_TLU_triggerInputs.tex b/AIDA_tlu/Documentation/Latex/ch_TLU_triggerInputs.tex
new file mode 100644
index 0000000000000000000000000000000000000000..a7605c2d6470aa6ba7f3efc047cefdedde795c56
--- /dev/null
+++ b/AIDA_tlu/Documentation/Latex/ch_TLU_triggerInputs.tex
@@ -0,0 +1,156 @@
+\chapter{Trigger inputs}\label{ch:triggerinputs}
+The six inputs on the \gls{tlu} can be used to generate a global trigger that is then issued to all the \gls{dut}s.\\
+Each input has a programmable voltage discriminator that can be configured in the range [-1.3 : 1.3]~V.\\
+All the inputs are protected by clamping diodes that limit the input voltage in the range [-5 : +5]~V.
+
+\section{Trigger logic}\label{ch:triggerLogic}
+The TLU has six trigger inputs than can be used to generate a valid trigger event. The number of possible different trigger combinations is $2^6= 64$ so a 64-bit word can be used to decide the valid combinations. In the hardware the 64-bit word is split into two 32-bit words (indicated as \gls{msb} and \gls{lsb} word) and the rules to generate the trigger can be specified by the user by writing in the two 32-bit registers \verb|TriggerPattern_highW| and \verb|TriggerPattern_lowW|: the first stores the 32 most significative bits of the trigger word, the latter stores the least significative bits.\\
+The user can select any combination of the trigger inputs and declare it a valid trigger pattern by setting a 1 in the corresponding trigger configuration word.
+Tables~\ref{tab:trigconfigLow} and ~\ref{tab:trigconfigHigh} show an example of how to determine the trigger configuration words: whenever a valid trigger combination is encountered, the user should put a 1 in the corresponding row under the PATTERN column. The pattern thus obtained is the required word to write in the configuration register.\\
+It is important to note that this solution allows the user to set veto pattern as well: for instance if only word 31 from table~\ref{tab:trigconfigLow} were picked, then the \gls{tlu} would only register a trigger when the combination $\overline{I_{5}}$ * $I_{4}$ * $I_{3}$ * $I_{2}$ * $I_{1}$ * $I_{0}$ was presented at its inputs. In other words, in this specific case $I_{5}$ would act as a veto signal and the \gls{tlu} would \textbf{not} produce a global trigger if $I_{5}$=1.
+
+% Please add the following required packages to your document preamble:
+% \usepackage{multirow}
+\begin{table}[]
+\centering
+\caption{Example of configuration word for the least significative bits of the trigger registers: the only valid configuration is represented by $\overline{I_{5}}$ + $I_{4}$ + $I_{3}$ + $I_{2}$ + $I_{1}$ + $I_{0}$, i.e. a trigger is accepted if all the inputs, except $I_{5}$, present a logic 1 at the same time. The user would then write the resulting word 0x80000000 in the TriggerPattern\_lowW register.}
+\label{tab:trigconfigLow}
+\begin{tabular}{|l|l|l|l|l|l|l||c||c|l|r|}
+\hline
+DEC & I5 & I4 & I3 & I2 & I1 & I0 & PATTERN & \multicolumn{1}{l|}{\begin{tabular}[c]{@{}l@{}}CONFIG. \\ WORD\end{tabular}} &                                  & $2^{n}$ \\ \hline
+0  & 0  & 0  & 0  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                & \parbox[t]{2mm}{\multirow{32}{*}{\rotatebox[origin=c]{90}{LOWEST 32-bits}}} & 1                   \\ \cline{1-8} \cline{11-11}
+1  & 0  & 0  & 0  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 2                   \\ \cline{1-8} \cline{11-11}
+2  & 0  & 0  & 0  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 4                   \\ \cline{1-8} \cline{11-11}
+3  & 0  & 0  & 0  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8                   \\ \cline{1-9} \cline{11-11}
+4  & 0  & 0  & 0  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                  &                                  & 16                  \\ \cline{1-8} \cline{11-11}
+5  & 0  & 0  & 0  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 32                  \\ \cline{1-8} \cline{11-11}
+6  & 0  & 0  & 0  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 64                  \\ \cline{1-8} \cline{11-11}
+7  & 0  & 0  & 0  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 128                 \\ \cline{1-9} \cline{11-11}
+8  & 0  & 0  & 1  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                  &                                  & 256                 \\ \cline{1-8} \cline{11-11}
+9  & 0  & 0  & 1  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 512                 \\ \cline{1-8} \cline{11-11}
+10  & 0  & 0  & 1  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 1024                \\ \cline{1-8} \cline{11-11}
+11  & 0  & 0  & 1  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 2048                \\ \cline{1-9} \cline{11-11}
+12  & 0  & 0  & 1  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 4096                \\ \cline{1-8} \cline{11-11}
+13  & 0  & 0  & 1  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8192                \\ \cline{1-8} \cline{11-11}
+14  & 0  & 0  & 1  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 16384               \\ \cline{1-8} \cline{11-11}
+15  & 0  & 0  & 1  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 32768               \\ \cline{1-9} \cline{11-11}
+16  & 0  & 1  & 0  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 65536               \\ \cline{1-8} \cline{11-11}
+17  & 0  & 1  & 0  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 131072              \\ \cline{1-8} \cline{11-11}
+18  & 0  & 1  & 0  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 262144              \\ \cline{1-8} \cline{11-11}
+19  & 0  & 1  & 0  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 524288              \\ \cline{1-9} \cline{11-11}
+20  & 0  & 1  & 0  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 1048576             \\ \cline{1-8} \cline{11-11}
+21  & 0  & 1  & 0  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 2097152             \\ \cline{1-8} \cline{11-11}
+22  & 0  & 1  & 0  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 4194304             \\ \cline{1-8} \cline{11-11}
+23  & 0  & 1  & 0  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8388608             \\ \cline{1-9} \cline{11-11}
+24  & 0  & 1  & 1  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 16777216            \\ \cline{1-8} \cline{11-11}
+25  & 0  & 1  & 1  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 33554432            \\ \cline{1-8} \cline{11-11}
+26  & 0  & 1  & 1  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 67108864            \\ \cline{1-8} \cline{11-11}
+27  & 0  & 1  & 1  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 134217728           \\ \cline{1-9} \cline{11-11}
+28  & 0  & 1  & 1  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{8}}}                                                                 &                                  & 268435456           \\ \cline{1-8} \cline{11-11}
+29  & 0  & 1  & 1  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 536870912           \\ \cline{1-8} \cline{11-11}
+30  & 0  & 1  & 1  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 1073741824          \\ \cline{1-8} \cline{11-11}
+31  & 0  & 1  & 1  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 2147483648          \\ \hline
+\end{tabular}
+\end{table}
+
+
+
+\begin{table}[]
+\centering
+\caption{Example of the most significative word of the register: a valid trigger is obtained when the inputs show the same configuration as row DEC 36, 37, 38, 39, 41, 43 and 63. These configuration are in logic OR with that presented in table~\ref{tab:trigconfigLow}. The resulting configuration word is 0x80000AF0.}
+\label{tab:trigconfigHigh}
+\begin{tabular}{|l|l|l|l|l|l|l||c||c|l|r|}
+\hline
+DEC & I5 & I4 & I3 & I2 & I1 & I0 & PATTERN & \multicolumn{1}{l|}{\begin{tabular}[c]{@{}l@{}}CONFIG. \\ WORD\end{tabular}} &                                  & $2^{n}$ \\ \hline
+32  & 1  & 0  & 0  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                & \parbox[t]{2mm}{\multirow{32}{*}{\rotatebox[origin=c]{90}{HIGHEST 32-bits}}} & 1                   \\ \cline{1-8} \cline{11-11}
+33  & 1  & 0  & 0  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 2                   \\ \cline{1-8} \cline{11-11}
+34  & 1  & 0  & 0  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 4                   \\ \cline{1-8} \cline{11-11}
+35  & 1  & 0  & 0  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8                   \\ \cline{1-9} \cline{11-11}
+36  & 1  & 0  & 0  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{1}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{F}}}                                                                  &                                  & 16                  \\ \cline{1-8} \cline{11-11}
+37  & 1  & 0  & 0  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 32                  \\ \cline{1-8} \cline{11-11}
+38  & 1  & 0  & 0  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 64                  \\ \cline{1-8} \cline{11-11}
+39  & 1  & 0  & 0  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 128                 \\ \cline{1-9} \cline{11-11}
+40  & 1  & 0  & 1  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{A}}}                                                                  &                                  & 256                 \\ \cline{1-8} \cline{11-11}
+41  & 1  & 0  & 1  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 512                 \\ \cline{1-8} \cline{11-11}
+42  & 1  & 0  & 1  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 1024                \\ \cline{1-8} \cline{11-11}
+43  & 1  & 0  & 1  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 2048                \\ \cline{1-9} \cline{11-11}
+44  & 1  & 0  & 1  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 4096                \\ \cline{1-8} \cline{11-11}
+45  & 1  & 0  & 1  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8192                \\ \cline{1-8} \cline{11-11}
+46  & 1  & 0  & 1  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 16384               \\ \cline{1-8} \cline{11-11}
+47  & 1  & 0  & 1  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 32768               \\ \cline{1-9} \cline{11-11}
+48  & 1  & 1  & 0  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 65536               \\ \cline{1-8} \cline{11-11}
+49  & 1  & 1  & 0  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 131072              \\ \cline{1-8} \cline{11-11}
+50  & 1  & 1  & 0  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 262144              \\ \cline{1-8} \cline{11-11}
+51  & 1  & 1  & 0  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 524288              \\ \cline{1-9} \cline{11-11}
+52  & 1  & 1  & 0  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 1048576             \\ \cline{1-8} \cline{11-11}
+53  & 1  & 1  & 0  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 2097152             \\ \cline{1-8} \cline{11-11}
+54  & 1  & 1  & 0  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 4194304             \\ \cline{1-8} \cline{11-11}
+55  & 1  & 1  & 0  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 8388608             \\ \cline{1-9} \cline{11-11}
+56  & 1  & 1  & 1  & 0  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{0}}}                                                                 &                                  & 16777216            \\ \cline{1-8} \cline{11-11}
+57  & 1  & 1  & 1  & 0  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 33554432            \\ \cline{1-8} \cline{11-11}
+58  & 1  & 1  & 1  & 0  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 67108864            \\ \cline{1-8} \cline{11-11}
+59  & 1  & 1  & 1  & 0  & 1  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 134217728           \\ \cline{1-9} \cline{11-11}
+60  & 1  & 1  & 1  & 1  & 0  & 0  & \rotatebox[origin=c]{90}{0}       & \parbox[t]{2mm}{\multirow{4}{*}{\rotatebox[origin=c]{90}{8}}}                                                                 &                                  & 268435456           \\ \cline{1-8} \cline{11-11}
+61  & 1  & 1  & 1  & 1  & 0  & 1  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 536870912           \\ \cline{1-8} \cline{11-11}
+62  & 1  & 1  & 1  & 1  & 1  & 0  & \rotatebox[origin=c]{90}{0}       &                                                                                    &                                  & 1073741824          \\ \cline{1-8} \cline{11-11}
+63  & 1  & 1  & 1  & 1  & 1  & 1  & \rotatebox[origin=c]{90}{1}       &                                                                                    &                                  & 2147483648          \\ \hline
+\end{tabular}
+\end{table}
+\noindent The default configuration in the firmware is Hi=~0xFFFFFFFF, Low=~0xFFFEFFFE, which means that as long as any trigger input fires, a trigger will be generated. These words are loaded in the \gls{fpga} every time the firmware is flushed.\\
+
+\begin{alertinfo}{Trigger logic definition}
+    The user should pay attention to what trigger logic they want to define in order to avoid confusion in the data.\\
+    A ``1'' in the logic table means that the corresponding input must be active to produce a valid trigger. Similarly, a ``0'' indicates that the corresponding input must be inactive (i.e. is a veto, not an ignore). Any change in input configuration will cause the logic to re-assess the trigger status. The following section gives a brief example.\\
+\end{alertinfo}
+
+\begin{alertinfo}{Bit 0 meaning}
+    A 1 in the lowest bit of the \gls{lsb} word indicates that $\overline{I_{5}}$ * $\overline{I_{4}}$ * $\overline{I_{3}}$ * $\overline{I_{2}}$ * $\overline{I_{1}}$ * $\overline{I_{0}}$ is a valid trigger combination, so the \gls{tlu} will produce a trigger when all the inputs are unactive (i.e. even if all the inputs are unplugged). Apart from very specific cases, this is generally not a desired behaviour.
+\end{alertinfo}
+
+\subsubsection{Example}
+In this example we have connected a pulser to two inputs of the \gls{tlu}, namely \verb|IN_1| and \verb|IN_5|. The inputs fire with a small, random delay with respect to each other.\\
+In order to ensure that the signals overlap adequately, we use the \emph{stretch} register (see chapter~\ref{ch:triggerLogic}) to increase the length of the pulses: we extend \emph{in0} to 10 clock cycles and \emph{in4} to 8 clock cycles, where the clock has a frequency of 160~MHz. The resulting signals are shown in figure~\ref{Fig:exampleExtendedTriggers}.
+\begin{figure}
+  \centering
+  \includegraphics[width=.90\textwidth]{./Images/Initial.png}
+  \caption{Input pulses (yellow) and corresponding stretched signals (red). Input 0 is stretched by 10 cycles, input 4 by 8, hence the difference in pulse widths.}
+  \label{Fig:exampleExtendedTriggers}
+\end{figure}\\
+We can now define the trigger logic to be used to assert a valid trigger: we only consider the lower 32-bits of the trigger word and see how different values can produce very different results.
+\begin{itemize}
+    \item Trigger \gls{lsb} word= 0x00020000. This indicates that the only valid trigger combination occurs when both \verb|IN_1| and \verb|IN_5| are high. The valid trigger goes high 1 clock cycle after this condition is met and remains high up to 1 clock cycle after the condition is no longer valid. This is illustrated in figure~\ref{Fig:exampleTrig00020000}.
+        \begin{figure}
+            \centering
+            \includegraphics[width=.90\textwidth]{./Images/Trigger0x00020000.png}
+            \caption{Trigger configuration 0x00020000. The valid trigger (blue) is asserted only when both signals are high. This condition occurs at frame 39. The trigger is asserted on the following frame.}
+            \label{Fig:exampleTrig00020000}
+        \end{figure}\\
+    \item Trigger \gls{lsb} word= 0x00020002. This indicates that a valid trigger is achieved in two separated configurations (in logic OR): when both inputs are high at the same time (as in the previous case) or if \verb|IN_1| is active on its own. This is illustrated in figure~\ref{Fig:exampleTrig00020002}. It can be seen that the valid trigger is asserted immediately one clock cycle after \verb|IN_1| is high and remains high as long as this condition is met. One might assume that specifying the combination with \verb|IN_5| is redundant, but the following example should show that this is not the case.
+        \begin{figure}
+            \centering
+            \includegraphics[width=.90\textwidth]{./Images/Trigger0x00020002.png}
+            \caption{Trigger configuration 0x00020002. The valid trigger (blue) is asserted if \texttt{IN\_1} is high OR when \texttt{IN\_1} and \texttt{IN\_5} are both high at the same time.}
+            \label{Fig:exampleTrig00020002}
+        \end{figure}\\
+    \item Trigger \gls{lsb} word= 0x00000002. This indicates that the only valid configuration is the one where only \verb|IN_1| is high. It is important to understand that in this configuration all other inputs act as veto. This might produce unexpected results if the user is not careful\footnote{Specifically, pulse stretch, pulse delay and trigger logic must be configured correctly to avoid unwanted results.}.\\
+        In figure~\ref{Fig:exampleTrig00000002} it is possible to see that the logic produces two separated trigger valid pulses, both shorter than the ones in previous examples: the first one is due to \verb|IN_1| going high while \verb|IN_5| is low. As soon as \verb|IN_5| goes high, the trigger condition is no longer met. When \verb|IN_5| returns low, a trigger condition is met again because \verb|IN_1| is still high. In this specific case, the double pulse is caused by the different width of the pulses.
+        \begin{figure}
+            \centering
+            \includegraphics[width=.90\textwidth]{./Images/Trigger0x00000002.png}
+            \caption{Trigger configuration 0x00000002. The valid trigger (blue) is asserted only when \texttt{IN\_1} is active on its own. As such, two separated trigger pulses are produced because \texttt{IN\_5} goes high and returns low before \texttt{IN\_1}.}
+            \label{Fig:exampleTrig00000002}
+        \end{figure}\\
+\end{itemize}
+
+\section{Stretch and delay}
+The trigger logic is designed to detect edge transitions\footnote{Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.} at the trigger inputs and produce a pulse for each transition detected. The pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
+Each pulse can be stretched and delayed in integer numbers of clock cycles to compensate for differences in cable length. Two separate 5-bit registers are used for the task: the value written in the registers will stretch/delay the pulse by a corresponding number of clock cycles.\\
+Diagram~\ref{Fig:trigger_stretchdelay} shows the effect of the delay and stretch words on the trigger logic.
+\begin{figure}
+  \centering
+  \includegraphics[width=.95\textwidth]{./Images/tlu_trigger_logic.pdf}
+  %\includesvg[width=.90\textwidth]{./Images/tlu_trigger_logic.svg}
+  \caption{Effect of the stretch and delay values. In1 is delayed by 2 clock cycles (t1= 12.5~ns) and stretched by 5 clock cycles (t2= 31.25~ns) to create a coincidence window with in5 and produce the resulting trigger signal.}
+  \label{Fig:trigger_stretchdelay}
+\end{figure}\\
+ Further details on how to configure the stretch and delay values are provided in section~\ref{ch:EUDAQPar}. 
\ No newline at end of file
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diff --git a/AIDA_tlu/README.md b/AIDA_tlu/README.md
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+++ b/AIDA_tlu/README.md
@@ -0,0 +1,48 @@
+# firmware_AIDA
+Firmware for the AIDA TLU Hardware
+
+This repository contains the VHL used to generate the firmware for the AIDA TLU, both versions V1C (T-shaped pcb) and V1E (rectangular PCB; the one most likely to be used outside the UoB lab).
+
+# Scripts
+The repository also contains Python scripts used to test the hardware. These scripts rely on a few libraries not linked here, so they are unlikely to work "out of the box".
+
+# EUDAQ2
+The best way to operate on the TLU is by using the EUDAQ2 tools (provide link!).
+
+# Building Firmware
+
+The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware.
+
+Set up the environment for Xilinx Vivado, then:
+
+	mkdir work
+	cd work
+	git clone git@github.com:ipbus/ipbb.git 	
+	( ... or curl -L https://github.com/ipbus/ipbb/archive/v0.2.5.tar.gz | tar xvz )
+	source ipbb/env.sh
+	ipbb init build
+	cd build
+	ipbb add git https://github.com/ipbus/ipbus-firmware.git -b enhancement/28
+	ipbb add git git@github.com:DavidCussans/firmware_AIDA.git
+	ipbb proj create vivado TLU_1e firmware_AIDA:projects/TLU_v1e -t top_tlu_1e_a35.dep
+	cd proj/TLU_1e
+	ipbb vivado project
+	# Set correct file as design "top"
+	vivado -mode tcl -nojournal -nolog -notrace -source ../../src/firmware_AIDA/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr
+	# Edit the files in the IPBus repostitory to expose the 200MHz clock
+	sed -i 's/onehz);/onehz); clk_200_o<=clk200;/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
+	sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
+	# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
+	pushd ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf
+	patch  <  ../../../../../../../firmware_AIDA/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
+
+	# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
+	pushd firmware_AIDA/projects/TLU_v1e/addr_table
+	/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
+	#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/firmware_AIDA/projects/TLU_v1e/firmware/hdl/
+	cp ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
+
+	ipbb vivado impl
+	ipbb vivado bitfile
+	ipbb vivado package
+	deactivate
diff --git a/AIDA_tlu/bitFiles/.directory b/AIDA_tlu/bitFiles/.directory
new file mode 100644
index 0000000000000000000000000000000000000000..8f061b3928648a6c67e119b4fe7cca159b175d50
--- /dev/null
+++ b/AIDA_tlu/bitFiles/.directory
@@ -0,0 +1,3 @@
+[Dolphin]
+Timestamp=2017,2,17,15,3,7
+ViewMode=1
diff --git a/AIDA_tlu/bitFiles/TLU_CLK_Config.txt b/AIDA_tlu/bitFiles/TLU_CLK_Config.txt
new file mode 100644
index 0000000000000000000000000000000000000000..764535a5fe6b0b407e2c31f5df967513ff5f75e0
--- /dev/null
+++ b/AIDA_tlu/bitFiles/TLU_CLK_Config.txt
@@ -0,0 +1,394 @@
+# Si538x/4x Registers Export
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
+# Design ID: NEWTLU01
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
+# Created On: 2017-02-17 15:16:26 GMT+00:00
+Address,Data
+0x0B24,0xD8
+0x0B25,0x00
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0x00
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x0F
+0x002D,0x55
+0x002E,0x37
+0x002F,0x00
+0x0030,0x37
+0x0031,0x00
+0x0032,0x37
+0x0033,0x00
+0x0034,0x37
+0x0035,0x00
+0x0036,0x37
+0x0037,0x00
+0x0038,0x37
+0x0039,0x00
+0x003A,0x37
+0x003B,0x00
+0x003C,0x37
+0x003D,0x00
+0x003F,0xFF
+0x0040,0x04
+0x0041,0x0C
+0x0042,0x0C
+0x0043,0x0C
+0x0044,0x0C
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x32
+0x0048,0x32
+0x0049,0x32
+0x004A,0x32
+0x004B,0x32
+0x004C,0x32
+0x004D,0x32
+0x004E,0x55
+0x004F,0x55
+0x0051,0x03
+0x0052,0x03
+0x0053,0x03
+0x0054,0x03
+0x0055,0x03
+0x0056,0x03
+0x0057,0x03
+0x0058,0x03
+0x0059,0xFF
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x01
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x01
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x01
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x01
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x30
+0x009D,0x00
+0x009E,0x20
+0x00A0,0x00
+0x00A2,0x02
+0x00A8,0x89
+0x00A9,0x70
+0x00AA,0x07
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x06
+0x013B,0xCC
+0x013C,0x00
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x19
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x19
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x01
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x19
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x01
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x19
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x01
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x4E
+0x026C,0x45
+0x026D,0x57
+0x026E,0x54
+0x026F,0x4C
+0x0270,0x55
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x14
+0x0509,0x23
+0x050A,0x0C
+0x050B,0x0B
+0x050C,0x03
+0x050D,0x3F
+0x050E,0x17
+0x050F,0x2B
+0x0510,0x09
+0x0511,0x08
+0x0512,0x03
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xA4
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x05
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x42
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x0C
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x0F
+0x094A,0x0F
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x00
+0x0B48,0x00
+0x0B4A,0x1E
+0x0514,0x01
+0x001C,0x01
+0x0B24,0xDB
+0x0B25,0x02
diff --git a/AIDA_tlu/bitFiles/TLU_CLK_Config_BKP.txt b/AIDA_tlu/bitFiles/TLU_CLK_Config_BKP.txt
new file mode 100644
index 0000000000000000000000000000000000000000..85ea885e8c5494b78e3dff453cb78bb00b763fd2
--- /dev/null
+++ b/AIDA_tlu/bitFiles/TLU_CLK_Config_BKP.txt
@@ -0,0 +1,394 @@
+# Si538x/4x Registers Export
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
+# Design ID: NEWTLU00
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
+# Created On: 2017-02-07 18:25:57 GMT+00:00
+Address,Data
+0x0B24,0xD8
+0x0B25,0x00
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0xFF
+0x0019,0xFF
+0x001A,0xFF
+0x002B,0x02
+0x002C,0x00
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x00
+0x0040,0x04
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x00
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x00
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x00
+0x004F,0x00
+0x0051,0x00
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x00
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x00
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x00
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x00
+0x009B,0x00
+0x009D,0x00
+0x009E,0x00
+0x00A0,0x00
+0x00A2,0x00
+0x00A8,0x00
+0x00A9,0x00
+0x00AA,0x00
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x06
+0x013B,0xCC
+0x013C,0x00
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x4E
+0x026C,0x45
+0x026D,0x57
+0x026E,0x54
+0x026F,0x4C
+0x0270,0x55
+0x0271,0x30
+0x0272,0x30
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x00
+0x0509,0x00
+0x050A,0x00
+0x050B,0x00
+0x050C,0x00
+0x050D,0x00
+0x050E,0x00
+0x050F,0x00
+0x0510,0x00
+0x0511,0x00
+0x0512,0x00
+0x0513,0x00
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0x00
+0x051A,0x00
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x00
+0x0521,0x21
+0x052A,0x00
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x00
+0x052F,0x00
+0x0531,0x00
+0x0532,0x00
+0x0533,0x04
+0x0534,0x00
+0x0535,0x01
+0x0536,0x0E
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x01
+0x090E,0x02
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x0F
+0x0B46,0x00
+0x0B47,0x00
+0x0B48,0x0F
+0x0B4A,0x1E
+0x0514,0x01
+0x001C,0x01
+0x0B24,0xDB
+0x0B25,0x02
diff --git a/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e.txt b/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e.txt
new file mode 100644
index 0000000000000000000000000000000000000000..b60646f09e04bdf0cdc9eab8d983c4241d9308a7
--- /dev/null
+++ b/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e.txt
@@ -0,0 +1,394 @@
+# Si538x/4x Registers Export
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
+# Design ID: TLU1E_01
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
+# Created On: 2017-08-24 13:37:41 GMT+01:00
+Address,Data
+0x0B24,0xD8
+0x0B25,0x00
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0x88
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x07
+0x002D,0x15
+0x002E,0x37
+0x002F,0x00
+0x0030,0x37
+0x0031,0x00
+0x0032,0x37
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x37
+0x0037,0x00
+0x0038,0x37
+0x0039,0x00
+0x003A,0x37
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x77
+0x0040,0x04
+0x0041,0x0C
+0x0042,0x0C
+0x0043,0x0C
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x32
+0x0048,0x32
+0x0049,0x00
+0x004A,0x32
+0x004B,0x32
+0x004C,0x32
+0x004D,0x00
+0x004E,0x55
+0x004F,0x05
+0x0051,0x03
+0x0052,0x03
+0x0053,0x03
+0x0054,0x00
+0x0055,0x03
+0x0056,0x03
+0x0057,0x03
+0x0058,0x00
+0x0059,0x3F
+0x005A,0xCC
+0x005B,0xCC
+0x005C,0xCC
+0x005D,0x00
+0x005E,0xCC
+0x005F,0xCC
+0x0060,0xCC
+0x0061,0x00
+0x0062,0xCC
+0x0063,0xCC
+0x0064,0xCC
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x30
+0x009D,0x00
+0x009E,0x20
+0x00A0,0x00
+0x00A2,0x02
+0x00A8,0x89
+0x00A9,0x70
+0x00AA,0x07
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x01
+0x013B,0xCC
+0x013C,0x00
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x14
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x14
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x01
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x14
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x01
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x54
+0x026C,0x4C
+0x026D,0x55
+0x026E,0x31
+0x026F,0x45
+0x0270,0x5F
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x14
+0x0509,0x23
+0x050A,0x0C
+0x050B,0x0B
+0x050C,0x03
+0x050D,0x3F
+0x050E,0x17
+0x050F,0x2B
+0x0510,0x09
+0x0511,0x08
+0x0512,0x03
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xA4
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x05
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x42
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x08
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x07
+0x094A,0x07
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x00
+0x0B48,0x08
+0x0B4A,0x1E
+0x0514,0x01
+0x001C,0x01
+0x0B24,0xDB
+0x0B25,0x02
diff --git a/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e_2.txt b/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e_2.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7dfa96fbcb4f95931084ac7a692aedcaff8df321
--- /dev/null
+++ b/AIDA_tlu/bitFiles/TLU_CLK_Config_v1e_2.txt
@@ -0,0 +1,411 @@
+# Si538x/4x Registers Script
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\Si5345-TLU1E_02.slabtimeproj
+# Design ID: TLU1E_02
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.16.1 [2017-07-19]
+# Created On: 2017-08-24 15:55:56 GMT+01:00
+Address,Data
+# 
+# Start configuration preamble
+0x0B24,0xD8
+0x0B25,0x00
+0x0540,0x01
+# End configuration preamble
+# 
+# Delay 300 msec
+#    Delay is worst case time for device to complete any calibration
+#    that is running due to device state change previous to this script
+#    being processed.
+# 
+# Start configuration registers
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0xFF
+0x0019,0xFF
+0x001A,0xFF
+0x002B,0x02
+0x002C,0x00
+0x002D,0x00
+0x002E,0x00
+0x002F,0x00
+0x0030,0x00
+0x0031,0x00
+0x0032,0x00
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x00
+0x0037,0x00
+0x0038,0x00
+0x0039,0x00
+0x003A,0x00
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x00
+0x0040,0x04
+0x0041,0x00
+0x0042,0x00
+0x0043,0x00
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x00
+0x0047,0x00
+0x0048,0x00
+0x0049,0x00
+0x004A,0x00
+0x004B,0x00
+0x004C,0x00
+0x004D,0x00
+0x004E,0x00
+0x004F,0x00
+0x0050,0x0F
+0x0051,0x00
+0x0052,0x00
+0x0053,0x00
+0x0054,0x00
+0x0055,0x00
+0x0056,0x00
+0x0057,0x00
+0x0058,0x00
+0x0059,0x00
+0x005A,0x00
+0x005B,0x00
+0x005C,0x00
+0x005D,0x00
+0x005E,0x00
+0x005F,0x00
+0x0060,0x00
+0x0061,0x00
+0x0062,0x00
+0x0063,0x00
+0x0064,0x00
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x00
+0x009B,0x00
+0x009D,0x00
+0x009E,0x00
+0x00A0,0x00
+0x00A2,0x00
+0x00A8,0x00
+0x00A9,0x00
+0x00AA,0x00
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x06
+0x013B,0x09
+0x013C,0x33
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x00
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x00
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x00
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x00
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x00
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x00
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x54
+0x026C,0x4C
+0x026D,0x55
+0x026E,0x31
+0x026F,0x45
+0x0270,0x5F
+0x0271,0x30
+0x0272,0x32
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x00
+0x0509,0x00
+0x050A,0x00
+0x050B,0x00
+0x050C,0x00
+0x050D,0x00
+0x050E,0x00
+0x050F,0x00
+0x0510,0x00
+0x0511,0x00
+0x0512,0x00
+0x0513,0x00
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0x00
+0x051A,0x00
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x00
+0x0521,0x21
+0x052A,0x05
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x00
+0x052F,0x00
+0x0531,0x00
+0x0532,0x00
+0x0533,0x04
+0x0534,0x00
+0x0535,0x01
+0x0536,0x0C
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x01
+0x090E,0x02
+0x0943,0x00
+0x0949,0x00
+0x094A,0x00
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x0F
+0x0B46,0x00
+0x0B47,0x0F
+0x0B48,0x0F
+0x0B4A,0x1E
+# End configuration registers
+# 
+# Start configuration postamble
+0x0514,0x01
+0x001C,0x01
+0x0540,0x00
+0x0B24,0xDB
+0x0B25,0x02
+# End configuration postamble
diff --git a/AIDA_tlu/bitFiles/debug_nets.ltx b/AIDA_tlu/bitFiles/debug_nets.ltx
new file mode 100644
index 0000000000000000000000000000000000000000..1cabb35c3434ad065f41c1c2616964474c548007
--- /dev/null
+++ b/AIDA_tlu/bitFiles/debug_nets.ltx
@@ -0,0 +1,144 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="0">
+  <probeset name="EDA_PROBESET" active="true">
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="0"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="1"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_deserialized_threshold_data[0][7]"/>
+        <net name="I5/s_deserialized_threshold_data[0][6]"/>
+        <net name="I5/s_deserialized_threshold_data[0][5]"/>
+        <net name="I5/s_deserialized_threshold_data[0][4]"/>
+        <net name="I5/s_deserialized_threshold_data[0][3]"/>
+        <net name="I5/s_deserialized_threshold_data[0][2]"/>
+        <net name="I5/s_deserialized_threshold_data[0][1]"/>
+        <net name="I5/s_deserialized_threshold_data[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="2"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="3"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/trigger_i[5]"/>
+        <net name="I10/trigger_i[4]"/>
+        <net name="I10/trigger_i[3]"/>
+        <net name="I10/trigger_i[2]"/>
+        <net name="I10/trigger_i[1]"/>
+        <net name="I10/trigger_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="4"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="triggers[5]"/>
+        <net name="triggers[4]"/>
+        <net name="triggers[3]"/>
+        <net name="triggers[2]"/>
+        <net name="triggers[1]"/>
+        <net name="triggers[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="5"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_ipb"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="6"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="7"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_l"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="8"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="sysclk_40"/>
+      </nets>
+    </probe>
+  </probeset>
+</probeData>
diff --git a/AIDA_tlu/bitFiles/debug_nets_abcd000a.ltx b/AIDA_tlu/bitFiles/debug_nets_abcd000a.ltx
new file mode 100644
index 0000000000000000000000000000000000000000..423a03f85c5cb6e46038b7b4060004d9996d4f5f
--- /dev/null
+++ b/AIDA_tlu/bitFiles/debug_nets_abcd000a.ltx
@@ -0,0 +1,192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="0">
+  <probeset name="EDA_PROBESET" active="true">
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="0"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_deserialized_threshold_data[0][7]"/>
+        <net name="I5/s_deserialized_threshold_data[0][6]"/>
+        <net name="I5/s_deserialized_threshold_data[0][5]"/>
+        <net name="I5/s_deserialized_threshold_data[0][4]"/>
+        <net name="I5/s_deserialized_threshold_data[0][3]"/>
+        <net name="I5/s_deserialized_threshold_data[0][2]"/>
+        <net name="I5/s_deserialized_threshold_data[0][1]"/>
+        <net name="I5/s_deserialized_threshold_data[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="1"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_threshold_previous_late_bit[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="2"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_o[5]"/>
+        <net name="I5/trigger_o[4]"/>
+        <net name="I5/trigger_o[3]"/>
+        <net name="I5/trigger_o[2]"/>
+        <net name="I5/trigger_o[1]"/>
+        <net name="I5/trigger_o[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="3"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_times_o[0][4]"/>
+        <net name="I5/trigger_times_o[0][3]"/>
+        <net name="I5/trigger_times_o[0][2]"/>
+        <net name="I5/trigger_times_o[0][1]"/>
+        <net name="I5/trigger_times_o[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="4"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="5"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/trigger_i[5]"/>
+        <net name="I10/trigger_i[4]"/>
+        <net name="I10/trigger_i[3]"/>
+        <net name="I10/trigger_i[2]"/>
+        <net name="I10/trigger_i[1]"/>
+        <net name="I10/trigger_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="6"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="triggers[5]"/>
+        <net name="triggers[4]"/>
+        <net name="triggers[3]"/>
+        <net name="triggers[2]"/>
+        <net name="triggers[1]"/>
+        <net name="triggers[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="7"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="8"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_ipb"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="9"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="10"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_l"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="11"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="sysclk_40"/>
+      </nets>
+    </probe>
+  </probeset>
+</probeData>
diff --git a/AIDA_tlu/bitFiles/debug_nets_abcd000b.ltx b/AIDA_tlu/bitFiles/debug_nets_abcd000b.ltx
new file mode 100644
index 0000000000000000000000000000000000000000..423a03f85c5cb6e46038b7b4060004d9996d4f5f
--- /dev/null
+++ b/AIDA_tlu/bitFiles/debug_nets_abcd000b.ltx
@@ -0,0 +1,192 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="0">
+  <probeset name="EDA_PROBESET" active="true">
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="0"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_deserialized_threshold_data[0][7]"/>
+        <net name="I5/s_deserialized_threshold_data[0][6]"/>
+        <net name="I5/s_deserialized_threshold_data[0][5]"/>
+        <net name="I5/s_deserialized_threshold_data[0][4]"/>
+        <net name="I5/s_deserialized_threshold_data[0][3]"/>
+        <net name="I5/s_deserialized_threshold_data[0][2]"/>
+        <net name="I5/s_deserialized_threshold_data[0][1]"/>
+        <net name="I5/s_deserialized_threshold_data[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="1"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_threshold_previous_late_bit[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="2"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_o[5]"/>
+        <net name="I5/trigger_o[4]"/>
+        <net name="I5/trigger_o[3]"/>
+        <net name="I5/trigger_o[2]"/>
+        <net name="I5/trigger_o[1]"/>
+        <net name="I5/trigger_o[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="3"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_times_o[0][4]"/>
+        <net name="I5/trigger_times_o[0][3]"/>
+        <net name="I5/trigger_times_o[0][2]"/>
+        <net name="I5/trigger_times_o[0][1]"/>
+        <net name="I5/trigger_times_o[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="4"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="5"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/trigger_i[5]"/>
+        <net name="I10/trigger_i[4]"/>
+        <net name="I10/trigger_i[3]"/>
+        <net name="I10/trigger_i[2]"/>
+        <net name="I10/trigger_i[1]"/>
+        <net name="I10/trigger_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="6"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="triggers[5]"/>
+        <net name="triggers[4]"/>
+        <net name="triggers[3]"/>
+        <net name="triggers[2]"/>
+        <net name="triggers[1]"/>
+        <net name="triggers[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="7"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="8"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_ipb"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="9"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="10"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_l"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="11"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="sysclk_40"/>
+      </nets>
+    </probe>
+  </probeset>
+</probeData>
diff --git a/AIDA_tlu/bitFiles/debug_nets_abcd000d.bit b/AIDA_tlu/bitFiles/debug_nets_abcd000d.bit
new file mode 100644
index 0000000000000000000000000000000000000000..0b168b9ece3436fc90e8744af44884bab8965b3a
Binary files /dev/null and b/AIDA_tlu/bitFiles/debug_nets_abcd000d.bit differ
diff --git a/AIDA_tlu/bitFiles/debug_nets_abcd000d.ltx b/AIDA_tlu/bitFiles/debug_nets_abcd000d.ltx
new file mode 100644
index 0000000000000000000000000000000000000000..92fee9d2ce398588c6a648b87213badded62306b
--- /dev/null
+++ b/AIDA_tlu/bitFiles/debug_nets_abcd000d.ltx
@@ -0,0 +1,288 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="0">
+  <probeset name="EDA_PROBESET" active="true">
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="0"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="1"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_deserialized_threshold_data[0][7]"/>
+        <net name="I5/s_deserialized_threshold_data[0][6]"/>
+        <net name="I5/s_deserialized_threshold_data[0][5]"/>
+        <net name="I5/s_deserialized_threshold_data[0][4]"/>
+        <net name="I5/s_deserialized_threshold_data[0][3]"/>
+        <net name="I5/s_deserialized_threshold_data[0][2]"/>
+        <net name="I5/s_deserialized_threshold_data[0][1]"/>
+        <net name="I5/s_deserialized_threshold_data[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="2"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_threshold_previous_late_bit[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="3"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_o[5]"/>
+        <net name="I5/trigger_o[4]"/>
+        <net name="I5/trigger_o[3]"/>
+        <net name="I5/trigger_o[2]"/>
+        <net name="I5/trigger_o[1]"/>
+        <net name="I5/trigger_o[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="4"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_times_o[0][4]"/>
+        <net name="I5/trigger_times_o[0][3]"/>
+        <net name="I5/trigger_times_o[0][2]"/>
+        <net name="I5/trigger_times_o[0][1]"/>
+        <net name="I5/trigger_times_o[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="5"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="6"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/trigger_i[5]"/>
+        <net name="I10/trigger_i[4]"/>
+        <net name="I10/trigger_i[3]"/>
+        <net name="I10/trigger_i[2]"/>
+        <net name="I10/trigger_i[1]"/>
+        <net name="I10/trigger_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="7"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="postVetotrigger[5]"/>
+        <net name="postVetotrigger[4]"/>
+        <net name="postVetotrigger[3]"/>
+        <net name="postVetotrigger[2]"/>
+        <net name="postVetotrigger[1]"/>
+        <net name="postVetotrigger[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="8"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="triggers[5]"/>
+        <net name="triggers[4]"/>
+        <net name="triggers[3]"/>
+        <net name="triggers[2]"/>
+        <net name="triggers[1]"/>
+        <net name="triggers[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="9"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_ipb"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="10"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_1_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="11"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_3_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="12"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_5_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="13"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_7_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="14"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_9_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="15"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/p_11_out"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="16"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="17"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_l"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="18"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="sysclk_40"/>
+      </nets>
+    </probe>
+  </probeset>
+</probeData>
diff --git a/AIDA_tlu/bitFiles/debug_nets_abcd000e.ltx b/AIDA_tlu/bitFiles/debug_nets_abcd000e.ltx
new file mode 100644
index 0000000000000000000000000000000000000000..91741e09680e2b6270d22a3bedcb7ebb8c14db1e
--- /dev/null
+++ b/AIDA_tlu/bitFiles/debug_nets_abcd000e.ltx
@@ -0,0 +1,236 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<probeData version="2" minor="0">
+  <probeset name="EDA_PROBESET" active="true">
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="0"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/deserialized_data_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="1"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="8"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_deserialized_threshold_data[0][7]"/>
+        <net name="I5/s_deserialized_threshold_data[0][6]"/>
+        <net name="I5/s_deserialized_threshold_data[0][5]"/>
+        <net name="I5/s_deserialized_threshold_data[0][4]"/>
+        <net name="I5/s_deserialized_threshold_data[0][3]"/>
+        <net name="I5/s_deserialized_threshold_data[0][2]"/>
+        <net name="I5/s_deserialized_threshold_data[0][1]"/>
+        <net name="I5/s_deserialized_threshold_data[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="2"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/s_threshold_previous_late_bit[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="3"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_o[5]"/>
+        <net name="I5/trigger_o[4]"/>
+        <net name="I5/trigger_o[3]"/>
+        <net name="I5/trigger_o[2]"/>
+        <net name="I5/trigger_o[1]"/>
+        <net name="I5/trigger_o[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="4"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="5"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_times_o[0][4]"/>
+        <net name="I5/trigger_times_o[0][3]"/>
+        <net name="I5/trigger_times_o[0][2]"/>
+        <net name="I5/trigger_times_o[0][1]"/>
+        <net name="I5/trigger_times_o[0][0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="5"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/cmp_coincidence_logic/triggers_i[5]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[4]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[3]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[2]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[1]"/>
+        <net name="I10/cmp_coincidence_logic/triggers_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="6"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/trigger_i[5]"/>
+        <net name="I10/trigger_i[4]"/>
+        <net name="I10/trigger_i[3]"/>
+        <net name="I10/trigger_i[2]"/>
+        <net name="I10/trigger_i[1]"/>
+        <net name="I10/trigger_i[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="7"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="postVetotrigger[5]"/>
+        <net name="postVetotrigger[4]"/>
+        <net name="postVetotrigger[3]"/>
+        <net name="postVetotrigger[2]"/>
+        <net name="postVetotrigger[1]"/>
+        <net name="postVetotrigger[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="8"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="6"/>
+      </probeOptions>
+      <nets>
+        <net name="triggers[5]"/>
+        <net name="triggers[4]"/>
+        <net name="triggers[3]"/>
+        <net name="triggers[2]"/>
+        <net name="triggers[1]"/>
+        <net name="triggers[0]"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="9"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_ipb"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="10"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I5/trigger_input_loop[0].thresholdLUT/rising_edge_o"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="11"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_l"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="12"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="I10/s_external_trigger_p"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="13"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="sysclk_40"/>
+      </nets>
+    </probe>
+    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
+      <probeOptions Id="DebugProbeParams">
+        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
+        <Option Id="CORE_LOCATION" value="1:0"/>
+        <Option Id="HW_ILA" value="u_ila_0"/>
+        <Option Id="PROBE_PORT" value="14"/>
+        <Option Id="PROBE_PORT_BITS" value="0"/>
+        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
+      </probeOptions>
+      <nets>
+        <net name="clk_8x_logic"/>
+      </nets>
+    </probe>
+  </probeset>
+</probeData>
diff --git a/AIDA_tlu/bitFiles/top_tlu.bit b/AIDA_tlu/bitFiles/top_tlu.bit
new file mode 100644
index 0000000000000000000000000000000000000000..a099c9939a56372ebc24dc72200100d50b7e1f4d
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170201.bit b/AIDA_tlu/bitFiles/top_tlu_20170201.bit
new file mode 100644
index 0000000000000000000000000000000000000000..e4daf295114fe1cd488efbe38b539bc9142b23d0
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170201.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170202.bit b/AIDA_tlu/bitFiles/top_tlu_20170202.bit
new file mode 100644
index 0000000000000000000000000000000000000000..55eca11b0814363bb34a86af0ec2f544d604ed5d
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170202.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170203.bit b/AIDA_tlu/bitFiles/top_tlu_20170203.bit
new file mode 100644
index 0000000000000000000000000000000000000000..62c441e0311536e51425f5f0ab485fde59ddba58
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170203.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170206.bit b/AIDA_tlu/bitFiles/top_tlu_20170206.bit
new file mode 100644
index 0000000000000000000000000000000000000000..52603f37f8361e25fa1093da504c3d8c8645004b
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170206.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170206_2.bit b/AIDA_tlu/bitFiles/top_tlu_20170206_2.bit
new file mode 100644
index 0000000000000000000000000000000000000000..5738dc1515fccd1756a49f13454c7bef8aa51fab
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170206_2.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170207.bit b/AIDA_tlu/bitFiles/top_tlu_20170207.bit
new file mode 100644
index 0000000000000000000000000000000000000000..c710f0a52df9bcdd740050d8fdabfc700276c5de
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170207.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170208.bit b/AIDA_tlu/bitFiles/top_tlu_20170208.bit
new file mode 100644
index 0000000000000000000000000000000000000000..2f92f1a2bdb33ca3f344f35d0b41bd30ce1949af
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170208.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170209.bit b/AIDA_tlu/bitFiles/top_tlu_20170209.bit
new file mode 100644
index 0000000000000000000000000000000000000000..ca28b108f8279d2df004b42b90f2c8471173ffae
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170209.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170209_2.bit b/AIDA_tlu/bitFiles/top_tlu_20170209_2.bit
new file mode 100644
index 0000000000000000000000000000000000000000..00b2f1790fbe08819840fc03907cb6637016c480
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170209_2.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170209_3.bit b/AIDA_tlu/bitFiles/top_tlu_20170209_3.bit
new file mode 100644
index 0000000000000000000000000000000000000000..0b7655823c410aa3ac706813cb03a8a575bcc1fe
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170209_3.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170209_4.bit b/AIDA_tlu/bitFiles/top_tlu_20170209_4.bit
new file mode 100644
index 0000000000000000000000000000000000000000..15793a91584eccf4a492f37d858b43e76f8660e3
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170209_4.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170209_5.bit b/AIDA_tlu/bitFiles/top_tlu_20170209_5.bit
new file mode 100644
index 0000000000000000000000000000000000000000..7b5b7d7360751aab89726f14de169759d2a56976
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170209_5.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170215.bit b/AIDA_tlu/bitFiles/top_tlu_20170215.bit
new file mode 100644
index 0000000000000000000000000000000000000000..1b54be134428364b4f48da2828b24bddbb40c996
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170215.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170216.bit b/AIDA_tlu/bitFiles/top_tlu_20170216.bit
new file mode 100644
index 0000000000000000000000000000000000000000..6c976439a1def2c0aed3b91f6e1a7973a12058c3
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170216.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170216_2.bit b/AIDA_tlu/bitFiles/top_tlu_20170216_2.bit
new file mode 100644
index 0000000000000000000000000000000000000000..6c976439a1def2c0aed3b91f6e1a7973a12058c3
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170216_2.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170216_3.bit b/AIDA_tlu/bitFiles/top_tlu_20170216_3.bit
new file mode 100644
index 0000000000000000000000000000000000000000..0c5cc5ec821937257c92193a6e8fc0e8d5b2c761
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170216_3.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170216_messy.bit b/AIDA_tlu/bitFiles/top_tlu_20170216_messy.bit
new file mode 100644
index 0000000000000000000000000000000000000000..0c0f5aa67b615b0fd6c89878e6f77096970b30cd
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170216_messy.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170216_reclock.bit b/AIDA_tlu/bitFiles/top_tlu_20170216_reclock.bit
new file mode 100644
index 0000000000000000000000000000000000000000..294f1bbc2cc89fe3ff452161b4913aafc7066bce
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170216_reclock.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170217.bit b/AIDA_tlu/bitFiles/top_tlu_20170217.bit
new file mode 100644
index 0000000000000000000000000000000000000000..e0d1db9db4ce21f613e99c63f14162e56d0ec53a
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170217.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170217_2.bit b/AIDA_tlu/bitFiles/top_tlu_20170217_2.bit
new file mode 100644
index 0000000000000000000000000000000000000000..b678522e6106f7190d45eb76659235151a53086f
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170217_2.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170217_3.bit b/AIDA_tlu/bitFiles/top_tlu_20170217_3.bit
new file mode 100644
index 0000000000000000000000000000000000000000..23ac7cb815531abced718c7042d41883dfc9a5ae
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170217_3.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170217_4.bit b/AIDA_tlu/bitFiles/top_tlu_20170217_4.bit
new file mode 100644
index 0000000000000000000000000000000000000000..3a906a2b5621a71217652440e48e3b62cec2010e
Binary files /dev/null and b/AIDA_tlu/bitFiles/top_tlu_20170217_4.bit differ
diff --git a/AIDA_tlu/bitFiles/top_tlu_20170220_6trigIn.bit b/AIDA_tlu/bitFiles/top_tlu_20170220_6trigIn.bit
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index 0000000000000000000000000000000000000000..ee02731f52e2f44744878fd309c67b9c04715b4a
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diff --git a/AIDA_tlu/bitFiles/top_tlu_v1e_0xabcd0005.bit b/AIDA_tlu/bitFiles/top_tlu_v1e_0xabcd0005.bit
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diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/lib_mappings.tcl b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/lib_mappings.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e12b5343b41b2c7445ac4135af4e746e566ae78e
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/lib_mappings.tcl
@@ -0,0 +1,9 @@
+set xlib $::env(XILINX_SIMLIBS)
+vmap secureip $xlib/secureip
+vmap unisim $xlib/unisim
+vmap unimacro $xlib/unimacro
+vmap unifast $xlib/unifast
+vmap unisims_ver $xlib/unisims_ver
+vmap unimacro_ver $xlib/unimacro_ver
+vmap unifast_ver $xlib/unifast_ver
+vmap simprims_ver $xlib/simprims_ver
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_infra_sim.dep b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_infra_sim.dep
new file mode 100644
index 0000000000000000000000000000000000000000..3718c21163c5b7b1cba7fe147e563a152e368f5e
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_infra_sim.dep
@@ -0,0 +1,5 @@
+src pc051a_infra_sim.vhd
+src -c ipbus-firmware:components/ipbus_util ../sim_hdl/clock_sim_7s.vhd
+src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
+include -c ipbus-firmware:components/ipbus_core
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_sim.dep b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_sim.dep
new file mode 100644
index 0000000000000000000000000000000000000000..6ac2be2b9ef667351607955242fabbd08990ba8b
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/cfg/pc051a_sim.dep
@@ -0,0 +1,9 @@
+@device_family = "artix7"
+@device_name = "xc7a200t"
+@device_package = "fbg484"
+@device_speed = "-2"
+@boardname = "pc051a"
+
+src top_pc051a_sim.vhd
+include pc051a_infra_sim.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/pc051a_infra_sim.vhd b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/pc051a_infra_sim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..967d14b0dd9c0c32dfb532ce6d5ef3bc4011e8af
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/pc051a_infra_sim.vhd
@@ -0,0 +1,99 @@
+-- kc705_basex_infra
+--
+-- All board-specific stuff goes here.
+--
+-- Dave Newbold, June 2013
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity pc051a_infra_sim is
+	port(
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		clk125_o: out std_logic;
+		rst125_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end pc051a_infra_sim;
+
+architecture rtl of pc051a_infra_sim is
+
+	signal clk125_fr, clk125, clk_ipb, clk_ipb_i, rst125, rst_ipb, rst_ipb_ctrl: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clock_sim_7s
+		port map(
+			clko_125 => clk125,
+			clko_ipb => clk_ipb_i,
+			locked => open,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	clk125_o <= clk125;
+	rst125_o <= rst125;
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_mac_sim
+		generic map(
+			MULTI_PACKET => true
+		)			
+		port map(
+			clk => clk125,
+			rst => rst125,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr
+		);
+
+end rtl;
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/top_pc051a_sim.vhd b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/top_pc051a_sim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f59d5efab35be7ae9b39258611d67fc833b43f1d
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/sim/firmware/hdl/top_pc051a_sim.vhd
@@ -0,0 +1,50 @@
+-- Top-level design for ipbus demo
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 08/01/16
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity top is
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, clk125, nuke, soft_rst, userled, clk200: std_logic;
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	
+begin
+
+-- Infrastructure
+
+	infra: entity work.pc051a_infra_sim -- Should work for artix also...
+		port map(
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			clk125_o => clk125,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			mac_addr => X"020ddba11610",
+			ip_addr => X"c0a8c910", -- 192.168.201.16
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+
+	payload: entity work.payload_sim
+		port map(
+			ipb_clk => clk_ipb,
+			ipb_rst => rst_ipb,
+			ipb_in => ipb_out,
+			ipb_out => ipb_in,
+			clk125 => clk125,
+			nuke => nuke,
+			soft_rst => soft_rst
+		);
+
+end rtl;
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep
new file mode 100644
index 0000000000000000000000000000000000000000..bfe69db8f9b6bfb2017e323e38ed9ef1e5b15992
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep
@@ -0,0 +1,11 @@
+@device_family = "artix7"
+@device_name = "xc7a35t"
+@device_package = "csg324"
+@device_speed = "-2"
+@boardname = "enclustra_ax3_pm3"
+
+setup settings_v7.tcl
+# src top_enclustra_ax3_pm3.vhd
+include enclustra_ax3_pm3_infra.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
+src --cd ../ucf enclustra_ax3_pm3.tcl
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep
new file mode 100644
index 0000000000000000000000000000000000000000..83f08bf100c65c8cee784dcd80c64fa2d5829e41
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep
@@ -0,0 +1,11 @@
+@device_family = "artix7"
+@device_name = "xc7a50t"
+@device_package = "csg324"
+@device_speed = "-2"
+@boardname = "enclustra_ax3_pm3"
+
+setup settings_v7.tcl
+# src top_enclustra_ax3_pm3.vhd
+include enclustra_ax3_pm3_infra.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
+src --cd ../ucf enclustra_ax3_pm3.tcl
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_infra.dep b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_infra.dep
new file mode 100644
index 0000000000000000000000000000000000000000..fa48bce1e89d4d820522bbdb25ebd5025533d271
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_infra.dep
@@ -0,0 +1,5 @@
+src enclustra_ax3_pm3_infra.vhd
+src -c ipbus-firmware:components/ipbus_util clocks_7s_extphy_se.vhd ipbus_clock_div.vhd led_stretcher.vhd
+include -c ipbus-firmware:components/ipbus_core
+include -c ipbus-firmware:components/ipbus_eth artix_rgmii.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/settings_v7.tcl b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/settings_v7.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c4ddcf2915f6a754cbc6dfebc59c9d6091d3689b
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/settings_v7.tcl
@@ -0,0 +1,5 @@
+set obj [get_projects top]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "source_mgmt_mode" "DisplayOnly" $obj
+set_property "target_language" "VHDL" $obj
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0a09bea6dc7166ed36f81a71d5c910e9c1a39a67
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
@@ -0,0 +1,132 @@
+-- enclustra_ax3_pm3_infra
+--
+-- All board-specific stuff goes here
+--
+-- Dave Newbold, June 2013
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity enclustra_ax3_pm3_infra is
+	port(
+		sysclk: in std_logic; -- 50MHz board crystal clock
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		clk125_o: out std_logic;
+		rst125_o: out std_logic;
+		clk_aux_o: out std_logic; -- 50MHz clock
+		rst_aux_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		leds: out std_logic_vector(1 downto 0); -- status LEDs
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end enclustra_ax3_pm3_infra;
+
+architecture rtl of enclustra_ax3_pm3_infra is
+
+	signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	signal led_p: std_logic_vector(0 downto 0);
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_7s_extphy_se
+		port map(
+			sysclk => sysclk,
+			clko_125 => clk125,
+			clko_125_90 => clk125_90,
+			clko_200 => clk200,
+			clko_ipb => clk_ipb_i,
+			locked => locked,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl,
+			onehz => onehz
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	clk125_o <= clk125;	
+	rst125_o <= rst125;
+	
+	stretch: entity work.led_stretcher
+		generic map(
+			WIDTH => 1
+		)
+		port map(
+			clk => clk125,
+			d(0) => pkt,
+			q => led_p
+		);
+
+	leds <= (led_p(0), locked and onehz);
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_7s_rgmii
+		port map(
+			clk125 => clk125,
+			clk125_90 => clk125_90,
+			clk200 => clk200,
+			rst => rst125,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			pkt => pkt
+		);
+
+end rtl;
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e53b33b3b03b1c59cc499be7aecdcceb17c84ac9
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd
@@ -0,0 +1,83 @@
+-- Top-level design for ipbus demo
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.ALL;
+
+entity top is port(
+		sysclk: in std_logic;
+		leds: out std_logic_vector(3 downto 0); -- status LEDs
+		cfg: in std_logic_vector(3 downto 0); -- switches
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		phy_rstn: out std_logic
+	);
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	
+begin
+
+-- Infrastructure
+
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => sysclk,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst125_o => phy_rst_e,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	leds <= not ('0' & userled & inf_leds);
+	phy_rstn <= not phy_rst_e;
+
+	mac_addr <= X"020ddba1151" & not cfg; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81" & not cfg; -- 192.168.200.16+n
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+	slaves: entity work.ipbus_example
+		port map(
+			ipb_clk => clk_ipb,
+			ipb_rst => rst_ipb,
+			ipb_in => ipb_out,
+			ipb_out => ipb_in,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			userled => userled
+		);
+
+end rtl;
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
new file mode 100644
index 0000000000000000000000000000000000000000..47b7501cb624e0dfe88a6fb619d19cd551f1103d
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
@@ -0,0 +1,36 @@
+--- /users/phdgc//DUNE/firmware/PDTS/work/build/src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl	2017-08-22 15:31:37.014565607 +0100
++++ ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl	2018-02-19 09:57:25.320449541 +0000
+@@ -20,9 +20,11 @@
+ set_false_path -through [get_nets infra/clocks/nuke_i]
+ 
+ set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
++#set_property IOSTANDARD LVCMOS33 [get_ports sysclk]
+ set_property PACKAGE_PIN P17 [get_ports sysclk]
+ 
+ set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
++#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
+ set_property SLEW SLOW [get_ports {leds[*]}]
+ set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
+ set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
+@@ -43,13 +45,15 @@
+ set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
+ set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
+ set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
++
+ set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
+ false_path {phy_rstn} sysclk
+ 
+-set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
+-set_property PULLUP TRUE [get_ports {cfg[*]}]
+-set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
+-set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
+-set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
+-set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
++
++#set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
++#set_property PULLUP TRUE [get_ports {cfg[*]}]
++#set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
++#set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
++#set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
++#set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
+ 
diff --git a/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav
new file mode 100644
index 0000000000000000000000000000000000000000..44fa5fee1af01f535271c456a2e6e038a2efba1d
--- /dev/null
+++ b/AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav
@@ -0,0 +1,55 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+proc false_path {patt clk} {
+    set p [get_ports -quiet $patt -filter {direction != out}]
+    if {[llength $p] != 0} {
+        set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
+        set_false_path -from [get_ports $patt -filter {direction != out}]
+    }
+    set p [get_ports -quiet $patt -filter {direction != in}]
+    if {[llength $p] != 0} {
+       	set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
+	    set_false_path -to [get_ports $patt -filter {direction != in}]
+	}
+}
+
+# System clock (200MHz)
+create_clock -period 20.000 -name sysclk [get_ports sysclk]
+
+set_false_path -through [get_pins infra/clocks/rst_reg/Q]
+set_false_path -through [get_nets infra/clocks/nuke_i]
+
+set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
+set_property PACKAGE_PIN P17 [get_ports sysclk]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
+set_property SLEW SLOW [get_ports {leds[*]}]
+set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
+set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
+set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
+set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
+false_path {leds[*]} sysclk
+
+set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_* phy_rstn}]
+set_property PACKAGE_PIN R18 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN T18 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports {rgmii_tx_ctl}]
+set_property PACKAGE_PIN N16 [get_ports {rgmii_txc}]
+set_property PACKAGE_PIN U16 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN V17 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN V15 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
+set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
+set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
+false_path {phy_rstn} sysclk
+
+set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
+set_property PULLUP TRUE [get_ports {cfg[*]}]
+set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
+set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
+set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
+set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
+
diff --git a/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0dc4e9af1fdee8b4fccea67129d50fc24fedb46
--- /dev/null
+++ b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_bit_ctrl.vhd
@@ -0,0 +1,492 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------              
+
+
+--/////////////////////////////////////
+--// Bit controller section
+--/////////////////////////////////////
+--//
+--// Translate simple commands into SCL/SDA transitions
+--// Each command has 5 states, A/B/C/D/idle
+--//
+--// start:	SCL	~~~~~~~~~~\____
+--//	SDA	~~~~~~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// repstart	SCL	____/~~~~\___
+--//	SDA	__/~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// stop	SCL	____/~~~~~~~~
+--//	SDA	==\____/~~~~~
+--//		 x | A | B | C | D | i
+--//
+--//- write	SCL	____/~~~~\____
+--//	SDA	==X=========X=
+--//		 x | A | B | C | D | i
+--//
+--//- read	SCL	____/~~~~\____
+--//	SDA	XXXX=====XXXX
+--//		 x | A | B | C | D | i
+--//
+--
+--// Timing:     Normal mode      Fast mode
+--///////////////////////////////////////////////////////////////////////
+--// Fscl        100KHz           400KHz
+--// Th_scl      4.0us            0.6us   High period of SCL
+--// Tl_scl      4.7us            1.3us   Low period of SCL
+--// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+--// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+--// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+--//
+--
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_bit_ctrl is
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+        
+ 
+end;
+
+architecture arch of i2c_master_bit_ctrl is
+
+--attribute UGROUP:string;                                   
+--attribute UGROUP of arch : label is "bit_group"; 
+
+
+signal sSCL, sSDA : std_logic;	-- synchronized SCL and SDA inputs
+signal dscl_oen : std_logic;	-- delayed scl_oen
+signal sda_chk : std_logic;		-- check SDA output (Multi-master arbitration)
+signal clk_en : std_logic;		-- clock generation signals
+signal slave_wait : std_logic;
+
+-- bus status controller signals
+signal dSCL,dSDA : std_logic;
+signal sta_condition : std_logic;
+signal sto_condition : std_logic;
+signal cmd_stop : std_logic;
+
+signal cnt : std_logic_vector(15 downto 0);	-- clock divider counter
+
+signal scl_oen_int : std_logic;
+signal sda_oen_int : std_logic;
+signal busy_int : std_logic;
+signal al_int : std_logic;
+
+-- state machine variable
+signal c_state : std_logic_vector(16 downto 0);
+
+constant idle 		: std_logic_vector(16 downto 0) := "00000000000000000";
+constant start_a 	: std_logic_vector(16 downto 0) := "00000000000000001";
+constant start_b 	: std_logic_vector(16 downto 0) := "00000000000000010";
+constant start_c 	: std_logic_vector(16 downto 0) := "00000000000000100";
+constant start_d 	: std_logic_vector(16 downto 0) := "00000000000001000";
+constant start_e 	: std_logic_vector(16 downto 0) := "00000000000010000";
+constant stop_a 	: std_logic_vector(16 downto 0) := "00000000000100000";
+constant stop_b	 	: std_logic_vector(16 downto 0) := "00000000001000000";
+constant stop_c	 	: std_logic_vector(16 downto 0) := "00000000010000000";
+constant stop_d 	: std_logic_vector(16 downto 0) := "00000000100000000";
+constant rd_a	 	: std_logic_vector(16 downto 0) := "00000001000000000";
+constant rd_b 		: std_logic_vector(16 downto 0) := "00000010000000000";
+constant rd_c 		: std_logic_vector(16 downto 0) := "00000100000000000";
+constant rd_d 		: std_logic_vector(16 downto 0) := "00001000000000000";
+constant wr_a 		: std_logic_vector(16 downto 0) := "00010000000000000";
+constant wr_b 		: std_logic_vector(16 downto 0) := "00100000000000000";
+constant wr_c 		: std_logic_vector(16 downto 0) := "01000000000000000";
+constant wr_d 		: std_logic_vector(16 downto 0) := "10000000000000000";
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+begin
+
+scl_oen <= scl_oen_int;
+sda_oen <= sda_oen_int;
+
+-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+-- delay scl_oen
+process(clk)
+begin
+	if rising_edge(clk) then
+		dscl_oen <= scl_oen_int;
+	end if;
+end process;
+
+slave_wait <= '1' when ((dscl_oen = '1') AND (sSCL = '0')) else '0';
+
+-- generate clk enable signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cnt <= (others => '0');
+		clk_en <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cnt <= (others => '0');
+			clk_en <= '1';
+		elsif ((cnt = "0000000000000000") OR (ena = '0')) then
+			cnt <= clk_cnt;
+			clk_en <= '1';
+		elsif (slave_wait = '1') then
+			cnt <= cnt;
+			clk_en <= '0';
+		else
+			cnt <= cnt - '1';
+			clk_en <= '0';
+		end if;
+	end if;
+end process;
+
+-- synchronize SCL and SDA inputs
+-- reduce metastability risc
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sSCL <= '1';
+		sSDA <= '1';
+		dSCL <= '1';
+		dSDA <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sSCL <= '1';
+			sSDA <= '1';
+			dSCL <= '1';
+			dSDA <= '1';
+		else
+			dSCL <= sSCL;
+			dSDA <= sSDA;
+                        -- Don't need to treat 'H' if separate I and O
+			-- if ((scl_i = '1') OR (scl_i = 'H')) then
+                        if (scl_i = '1')  then
+				sSCL <= '1';
+			else
+				sSCL <= '0';
+			end if;
+			-- if ((sda_i = '1') OR (sda_i = 'H')) then
+                        if (sda_i = '1')  then
+				sSDA <= '1';
+			else
+				sSDA <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+-- detect start condition => detect falling edge on SDA while SCL is high
+-- detect stop condition => detect rising edge on SDA while SCL is high
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sta_condition <= '0';
+		sto_condition <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sta_condition <= '0';
+			sto_condition <= '0';
+		else
+			sta_condition <= NOT(sSDA) AND dSDA AND sSCL;
+			sto_condition <= sSDA AND NOT(dSDA) AND sSCL;
+		end if;
+	end if;
+end process;
+
+-- generate i2c bus busy signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		busy_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			busy_int <= '0';
+		else
+			busy_int <= (sta_condition OR busy_int) AND NOT(sto_condition);
+		end if;
+	end if;
+end process;
+
+busy <= busy_int;
+
+-- generate arbitration lost signal
+-- aribitration lost when:
+-- 1) master drives SDA high, but the i2c bus is low
+-- 2) stop detected while not requested
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cmd_stop <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cmd_stop <= '0';
+		elsif (clk_en = '1') then
+			if (cmd = I2C_CMD_STOP) then
+				cmd_stop <= '1';
+			else
+				cmd_stop <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		al_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			al_int <= '0';
+		else
+			if (((sda_chk = '1') AND (sSDA = '0') AND (sda_oen_int = '1')) OR ((c_state /= idle) AND (sto_condition = '1') AND (cmd_stop = '0'))) then
+				al_int <= '1';
+			else
+				al_int <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+al <= al_int;
+
+
+-- generate dout signal (store SDA on rising edge of SCL)
+process(clk)
+begin
+	if rising_edge(clk) then
+		if ((sSCL = '1') AND (dSCL = '0')) then
+			dout <= sSDA;
+		end if;
+	end if;
+end process;
+
+
+--generate state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		c_state <= idle;
+		cmd_ack <= '0';
+		scl_oen_int <= '1';
+		sda_oen_int <= '1';
+		sda_chk <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (al_int = '1')) then
+			c_state <= idle;
+			cmd_ack <= '0';
+			scl_oen_int <= '1';
+			sda_oen_int <= '1';
+			sda_chk <= '0';
+		else
+			cmd_ack <= '0';	--default no command acknowledge + assert cmd_ack only 1clk cycle
+			if (clk_en = '1') then
+				case (c_state) is
+					when idle =>
+							case (cmd) is
+								when I2C_CMD_START	=> c_state <= start_a;
+								when I2C_CMD_STOP	=> c_state <= stop_a;
+								when I2C_CMD_WRITE	=> c_state <= wr_a;
+								when I2C_CMD_READ	=> c_state <= rd_a;
+								when others			=> c_state <= idle;
+							end case;
+
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= sda_oen_int;  -- keep SDA in same state
+							sda_chk <= '0';              -- don't check SDA output
+					when start_a =>          -- start
+							c_state <= start_b;
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_b =>
+							c_state <= start_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_c =>
+							c_state <= start_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_d =>
+							c_state <= start_e;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_e =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_a =>          -- stop
+							c_state <= stop_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_b =>
+							c_state <= stop_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_c =>
+							c_state <= stop_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_a =>          -- read
+							c_state <= rd_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '1';          -- tri-state SDA
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_b =>
+							c_state <= rd_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_c =>
+							c_state <= rd_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when wr_a =>          -- write
+							c_state <= wr_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= din;          -- set SDA
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when wr_b =>
+							c_state <= wr_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= din;          -- keep SDA
+							sda_chk <= '1';              -- check SDA output
+					when wr_c =>
+							c_state <= wr_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= din;
+							sda_chk <= '1';              -- check SDA output
+					when wr_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= din;
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when others => NULL;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- assign scl and sda output (always gnd)
+scl_o <= '0';
+sda_o <= '0';
+
+end arch;
diff --git a/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f52195741d35d657cf7dad6d66f708bda9d46b28
--- /dev/null
+++ b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_byte_ctrl.vhd
@@ -0,0 +1,286 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master byte-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-----------------------------------------------------------------------
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                        
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------  
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_byte_ctrl is
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end;
+
+architecture arch of i2c_master_byte_ctrl is
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+
+constant ST_IDLE	: std_logic_vector(4 downto 0) := "00000";
+constant ST_START	: std_logic_vector(4 downto 0) := "00001";
+constant ST_READ	: std_logic_vector(4 downto 0) := "00010";
+constant ST_WRITE	: std_logic_vector(4 downto 0) := "00100";
+constant ST_ACK		: std_logic_vector(4 downto 0) := "01000";
+constant ST_STOP	: std_logic_vector(4 downto 0) := "10000";
+
+signal c_state : std_logic_vector(4 downto 0);
+
+
+signal go : std_logic;
+signal dcnt : std_logic_vector(2 downto 0);
+signal cnt_done : std_logic;
+
+signal sr : std_logic_vector(7 downto 0); --8bit shift register
+signal shift, ld : std_logic;
+
+signal cmd_ack_int : std_logic;
+
+
+begin
+
+go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
+dout <= sr;
+
+-- generate shift register
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sr <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sr <= (others => '0');
+		elsif (ld = '1') then
+			sr <= din;
+		elsif (shift = '1') then
+			sr <= sr(6 downto 0) & core_rxd;
+		end if;
+	end if;
+end process;
+
+-- generate counter
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		dcnt <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			dcnt <= (others => '0');
+		elsif (ld = '1') then
+			dcnt <= "111";
+		elsif (shift = '1') then
+			dcnt <= dcnt - '1';
+		end if;
+	end if;
+end process;
+
+cnt_done <= '1' when (dcnt = "000") else '0';
+
+-- state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		core_cmd <= I2C_CMD_NOP;
+		core_txd <= '0';
+		shift <= '0';
+		ld <= '0';
+		cmd_ack_int <= '0';
+		c_state <= ST_IDLE;
+		ack_out <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (i2c_al = '1')) then
+			core_cmd <= I2C_CMD_NOP;
+			core_txd <= '0';
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+			c_state <= ST_IDLE;
+			ack_out <= '0';
+		else
+			-- initially reset all signals
+			core_txd <= sr(7);
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+
+			case (c_state) is
+				when ST_IDLE =>
+						if (go = '1') then
+							if (start = '1') then
+								c_state <= ST_START;
+								core_cmd <= I2C_CMD_START;
+							elsif (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							elsif (write = '1') then
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_START =>
+						if (core_ack = '1') then
+							if (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_WRITE =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;		-- stay in same state
+								core_cmd <= I2C_CMD_WRITE;	-- write next bit
+								shift <= '1';
+							end if;
+						end if;
+				when ST_READ =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_READ;			-- stay in same state
+								core_cmd <= I2C_CMD_READ;	-- read next bit
+								shift <= '1';
+							end if;
+							shift <= '1';
+							core_txd <= ack_in;
+						end if;
+				when ST_ACK =>
+						if (core_ack = '1') then
+							if (stop = '1') then
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							else
+								c_state <= ST_IDLE;
+								core_cmd <= I2C_CMD_NOP;
+								-- generate command acknowledge signal
+								cmd_ack_int <= '1';
+							end if;
+							-- assign ack_out output to bit_controller_rxd (contains last received bit)
+							ack_out <= core_rxd;
+							core_txd <= '1';
+						else
+							core_txd <= ack_in;
+						end if;
+				when ST_STOP =>
+						if (core_ack = '1') then
+							c_state <= ST_IDLE;
+							core_cmd <= I2C_CMD_NOP;
+							-- generate command acknowledge signal
+							cmd_ack_int <= '1';
+						end if;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+cmd_ack <= cmd_ack_int;
+
+end arch;
diff --git a/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_registers.vhd b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_registers.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..620e226cd1582dc3f8ed20c3dbd6dd98f42cf127
--- /dev/null
+++ b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_registers.vhd
@@ -0,0 +1,196 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master registers             ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------    
+-- --------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_registers is
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end;
+
+architecture arch of i2c_master_registers is
+
+
+signal ctr_int : std_logic_vector(7 downto 0);
+signal cr_int : std_logic_vector(7 downto 0);
+
+signal al : std_logic;			-- status register arbitration lost bit
+signal rxack : std_logic;		-- received aknowledge from slave
+signal tip : std_logic;			-- transfer in progress
+signal irq_flag : std_logic;	-- interrupt pending flag
+
+begin
+
+-- generate prescale regisres, control registers, and transmit register
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		prer <= (others => '1');
+		ctr_int <= (others => '0');
+		txr <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			prer <= (others => '1');
+			ctr_int <= (others => '0');
+			txr <= (others => '0');
+		elsif (wb_wacc = '1') then
+			case (wb_adr_i) is
+				when "000" => prer(7 downto 0)	<= wb_dat_i;
+				when "001" => prer(15 downto 8)	<= wb_dat_i;
+				when "010" => ctr_int			<= wb_dat_i;
+				when "011" => txr				<= wb_dat_i;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+ctr <= ctr_int;
+
+-- generate command register (special case)
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		cr_int <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			cr_int <= (others => '0');
+		elsif (wb_wacc = '1') then
+			if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
+				cr_int <= wb_dat_i;
+			end if;
+		else
+			if ((done = '1') OR (i2c_al = '1')) then
+				cr_int(7 downto 4) <= "0000";	-- clear command b
+			end if;							-- or when aribitr
+			cr_int(2 downto 1) <= "00";			-- reserved bits
+			cr_int(0) <= '0';					-- clear IRQ_ACK b
+		end if;
+	end if;
+end process;
+
+cr <= cr_int;
+
+-- generate status register block + interrupt request signal
+-- each output will be assigned to corresponding sr register locations on top level
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		al 			<= '0';
+		rxack 		<= '0';
+		tip 		<= '0';
+		irq_flag	<= '0';
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			al 			<= '0';
+			rxack 		<= '0';
+			tip 		<= '0';
+			irq_flag	<= '0';
+		else
+			al			<= i2c_al OR (al AND NOT(cr_int(7)));
+			rxack		<= irxack;
+			tip			<= (cr_int(5) OR cr_int(4));
+			irq_flag	<= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
+		end if;
+	end if;
+end process;
+
+sr(7)	 		<= rxack;
+sr(6)			<= i2c_busy;
+sr(5)			<= al;
+sr(4 downto 2)	<= "000"; -- reserved
+sr(1)			<= tip;
+sr(0)			<= irq_flag;
+
+
+end arch;
diff --git a/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_rtl.vhd b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d0bb973aa56b1e35107d8d22fd37574f7e7eed6
--- /dev/null
+++ b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_rtl.vhd
@@ -0,0 +1,97 @@
+--=============================================================================
+--! @file i2c_master_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.i2c_master.rtl
+--
+--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
+--! are bundled together in a record\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 17:22:12 11/30/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY i2c_master IS
+   PORT( 
+      i2c_scl_i     : IN     std_logic;
+      i2c_sda_i     : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;    -- Signals from IPBus core to slave
+      ipbus_reset_i : IN     std_logic;
+      i2c_scl_enb_o : OUT    std_logic;
+      i2c_sda_enb_o : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus     -- signals from slave to IPBus core
+   );
+
+-- Declarations
+
+END ENTITY i2c_master ;
+
+--
+ARCHITECTURE rtl OF i2c_master IS
+  
+  --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
+  
+BEGIN
+  
+  --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
+  --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
+
+  i2c_interface: entity work.i2c_master_top port map(
+                wb_clk_i => ipbus_clk_i,
+                wb_rst_i => ipbus_reset_i,
+                arst_i => '1',
+                wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
+                wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
+                wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
+                wb_we_i => ipbus_i.ipb_write,
+                wb_stb_i => ipbus_i.ipb_strobe,
+                wb_cyc_i => '1',
+                wb_ack_o => ipbus_o.ipb_ack,
+                wb_inta_o => open,
+                scl_pad_i => i2c_scl_i,
+                scl_pad_o => open,
+                scl_padoen_o => i2c_scl_enb_o,
+                sda_pad_i => i2c_sda_i,
+                sda_pad_o => open,
+                sda_padoen_o => i2c_sda_enb_o
+        );
+        
+  
+  ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
+  ipbus_o.ipb_err <= '0'; -- never return an error.
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_top.vhd b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6f0aabbb39ea9507a6183182169d36ad85039a1
--- /dev/null
+++ b/AIDA_tlu/components/external/opencores_i2c/firmware/hdl/i2c_master_top.vhd
@@ -0,0 +1,344 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-------------------------------------------------------------------------------
+-- Changes at University of bristol:
+-- V1.0A|D.G.C   | 5/11     | Changed name and ports to fit OC original
+-- --------------------------------------------------------------------    
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_top is
+  generic (
+		ARST_LVL : integer := 0
+		);
+  port (
+        wb_clk_i : in  std_logic;
+        wb_rst_i : in  std_logic;
+        arst_i   : in  std_logic;
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_dat_o : out std_logic_vector(7 downto 0);
+        wb_we_i  : in  std_logic;
+        wb_stb_i : in  std_logic;
+        wb_cyc_i : in  std_logic;
+        wb_ack_o : out std_logic;
+        wb_inta_o: out std_logic;
+        scl_pad_i: in std_logic;
+        scl_pad_o: out std_logic;
+        scl_padoen_o: out std_logic;
+        sda_pad_i: in std_logic;
+        sda_pad_o: out std_logic;
+        sda_padoen_o: out std_logic
+--        scl      : inout std_logic;
+--        sda      : inout std_logic
+        );
+end;
+
+architecture arch of i2c_master_top is
+
+component i2c_master_bit_ctrl
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+end component;
+
+component i2c_master_byte_ctrl
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end component;
+
+component i2c_master_registers
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end component;
+
+
+signal prer : std_logic_vector(15 downto 0);
+signal ctr : std_logic_vector(7 downto 0);
+signal txr : std_logic_vector(7 downto 0);
+signal rxr : std_logic_vector(7 downto 0);
+signal cr : std_logic_vector(7 downto 0);
+signal sr : std_logic_vector(7 downto 0);
+
+signal done : std_logic;
+signal core_en : std_logic;
+signal ien : std_logic;
+signal irxack : std_logic;
+signal irq_flag : std_logic;
+signal i2c_busy : std_logic;
+signal i2c_al : std_logic;
+
+signal core_cmd : std_logic_vector(3 downto 0);
+signal core_txd : std_logic;
+signal core_ack, core_rxd : std_logic;
+
+-- Don't need these signals, since passing them through
+-- component interface
+--signal scl_pad_i : std_logic;
+--signal scl_pad_o : std_logic;
+--signal scl_padoen_o : std_logic;
+--
+--signal sda_pad_i : std_logic;
+--signal sda_pad_o : std_logic;
+--signal sda_padoen_o : std_logic;
+
+signal rst_i : std_logic;
+
+signal sta : std_logic;
+signal sto : std_logic;
+signal rd : std_logic;
+signal wr : std_logic;
+signal ack : std_logic;
+signal iack : std_logic;
+
+signal wb_ack_o_int : std_logic;
+
+signal wb_wacc : std_logic;
+signal acki : std_logic;
+
+begin
+
+  -- Don't need to copy these signal - passing through
+  -- component interface
+--scl_pad_i <= scl;
+--sda_pad_i <= sda;
+
+rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
+
+wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
+
+sta <= cr(7);
+sto <= cr(6);
+rd <= cr(5);
+wr <= cr(4);
+ack <= cr(3);
+acki <= cr(0);
+
+core_en <= ctr(7);
+ien <= ctr(6);
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
+	end if;
+end process;
+
+wb_ack_o <= wb_ack_o_int;
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		case (wb_adr_i) is
+			when "000" => wb_dat_o <= prer(7 downto 0);
+			when "001" => wb_dat_o <= prer(15 downto 8);
+			when "010" => wb_dat_o <= ctr;
+			when "011" => wb_dat_o <= rxr;
+			when "100" => wb_dat_o <= sr;
+			when "101" => wb_dat_o <= txr;
+			when "110" => wb_dat_o <= cr;
+			when "111" => wb_dat_o <= "00000000";
+			when others => NULL;
+		end case;
+	end if;
+end process;
+
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		wb_inta_o <= '0';
+	elsif rising_edge(wb_clk_i) then
+		wb_inta_o <= sr(0) AND ien;
+	end if;
+end process;
+
+
+
+byte_controller: i2c_master_byte_ctrl port map(
+	clk 		=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	clk_cnt		=> prer,
+	start		=> sta,
+	stop		=> sto,
+	read		=> rd,
+	write		=> wr,
+	ack_in		=> ack,
+	din			=> txr,
+	cmd_ack		=> done,
+	ack_out		=> irxack,
+	dout		=> rxr,
+	i2c_al		=> i2c_al,
+	core_cmd	=> core_cmd,
+	core_ack	=> core_ack,
+	core_txd	=> core_txd,
+	core_rxd	=> core_rxd);
+
+bit_controller: i2c_master_bit_ctrl port map(
+	clk			=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	ena			=> core_en,
+	clk_cnt		=> prer,
+	cmd			=> core_cmd,
+	cmd_ack		=> core_ack,
+	busy		=> i2c_busy,
+	al			=> i2c_al,
+	din			=> core_txd,
+	dout		=> core_rxd,
+	scl_i		=> scl_pad_i,
+	scl_o		=> scl_pad_o,
+	scl_oen		=> scl_padoen_o,
+	sda_i		=> sda_pad_i,
+	sda_o		=> sda_pad_o,
+	sda_oen		=> sda_padoen_o);
+
+registers: i2c_master_registers port map(
+	wb_clk_i	=> wb_clk_i,
+	rst_i		=> rst_i,
+	wb_rst_i	=> wb_rst_i,
+	wb_dat_i	=> wb_dat_i,
+	wb_wacc		=> wb_wacc,
+	wb_adr_i	=> wb_adr_i,
+	i2c_al		=> i2c_al,
+	i2c_busy	=> i2c_busy,
+	done		=> done,
+	irxack		=> irxack,
+	prer		=> prer,
+	ctr			=> ctr,
+	txr			=> txr,
+	cr			=> cr,
+	sr			=> sr);
+
+
+-- edited from Lattice original to pass uni-directional signals
+--scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
+--sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
+
+end arch;
diff --git a/AIDA_tlu/components/tlu/firmware/cgn/internalTriggerGenerator.xci b/AIDA_tlu/components/tlu/firmware/cgn/internalTriggerGenerator.xci
new file mode 100644
index 0000000000000000000000000000000000000000..d35060d7c1f1dc147478c8f4150f91d37f6f3b3f
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/cgn/internalTriggerGenerator.xci
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>internalTriggerGenerator</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="c_counter_binary" spirit:version="12.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CE_INTF.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_INTF.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LOAD_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.L_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.Q_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SINIT_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SSET_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.THRESH0_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.UP_INTF.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AINIT_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CE_OVERRIDES_SYNC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_BY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_MODE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FB_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_LOAD">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SCLR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SINIT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SSET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_THRESH0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESTRICT_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SCLR_OVERRIDES_SSET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SINIT_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THRESH0_VALUE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VERBOSITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AINIT_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CE">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">internalTriggerGenerator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Count_Mode">DOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fb_Latency">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fb_Latency_Configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Final_Count_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Implementation">Fabric</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Increment_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Latency_Configuration">Automatic</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Restrict_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SCLR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINIT_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SSET">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SyncCtrlPriority">Reset_Overrides_Set</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sync_CE_Priority">Sync_Overrides_CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Sync_Threshold_Output">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Threshold_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Count_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fb_Latency_Configuration" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Latency" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Latency_Configuration" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/AIDA_tlu/components/tlu/firmware/cgn/tlu_event_fifo.xci b/AIDA_tlu/components/tlu/firmware/cgn/tlu_event_fifo.xci
new file mode 100644
index 0000000000000000000000000000000000000000..b9d83fcdc236b8dd0612c48f9d440c6ea6c67679
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/cgn/tlu_event_fifo.xci
@@ -0,0 +1,536 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>tlu_event_fifo</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.LAYERED_METADATA">undef</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_BUSIF"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">tlu_event_fifo</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">8181</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">8180</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">8192</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Almost_Empty_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Almost_Full_Flag" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/GPL_doxygen_header.vhdl b/AIDA_tlu/components/tlu/firmware/hdl/GPL_doxygen_header.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d9fdc487ef25fde77339ce30d5aff5ae4a75af3f
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/GPL_doxygen_header.vhdl
@@ -0,0 +1,77 @@
+--! @file dtype_fds.vhdl
+--
+-------------------------------------------------------------------------------
+-- --
+-- (c) University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+--
+-- This file is part of IPBus.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--
+--! Standard library
+library IEEE;
+
+-- Standard logic defintions.
+use IEEE.STD_LOGIC_1164.all;
+
+--
+-- unit name: dtype_fds
+--
+--! @brief   Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/Reg_2clks.vhd b/AIDA_tlu/components/tlu/firmware/hdl/Reg_2clks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df7168fc6283b56b28cef8af2b300d774b576bf7
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/Reg_2clks.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    31/07/2012 
+-- Module Name:    Reg_2clks - Behavioral 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 1b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity Reg_2clks is
+  port(
+    clk_i : in std_logic;  --! Synchronous clock
+	 async_i : in std_logic;  --! Asynchronous input data
+	 sync_o : out std_logic   --! Synchronous output data
+	 );
+end Reg_2clks;
+
+--! @brief
+--! @details Synchronize 1 bit of data 
+
+architecture Behavioral of Reg_2clks is
+signal sreg : std_logic_vector(1 downto 0);
+
+attribute TIG : string;
+attribute IOB : string;
+attribute ASYNC_REG : string;
+attribute SHIFT_EXTRACT : string;
+attribute HBLKNM : string;
+
+attribute TIG of async_i : signal is "TRUE";
+attribute IOB of async_i : signal is "FALSE";
+attribute ASYNC_REG of sreg : signal is "TRUE";
+attribute SHIFT_EXTRACT of sreg : signal is "NO";
+attribute HBLKNM of sreg : signal is "sync_reg";
+
+begin
+
+process (clk_i)
+begin
+   if rising_edge(clk_i) then  
+     sync_o <= sreg(1);
+	  sreg <= sreg(0) & async_i;
+   end if;
+end process;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/SyncGenerator_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/SyncGenerator_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2fb335e5c1a522507b343d87163d7982bf86e7c7
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/SyncGenerator_rtl.vhd
@@ -0,0 +1,208 @@
+--=============================================================================
+--! @file syncGenerator_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------
+-- unit name: syncGenerator
+--
+--============================================================================
+--! Entity declaration for syncGenerator
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+use IEEE.math_real.all;
+
+--! @brief Generates a sync signal for, eg. KPix
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date April 2018
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! Starts sequence with trigger_veto_o high and shutter_o low.
+--! If enable_sequence_i is high then when trigger_sources_i(trigger_source_select_i) goes high
+--! then sequence starts.
+--! At time T1 after Emin signal shutter_o goes higher
+--! At time T2 after Emin veto_o goes low
+--! At time T3 after Emin shutter_o goes low and veto_o goes high.
+--! ( If sequence is not enabled, then veto_o is always low. )
+--! \n\n<b>Last changes:</b>\n
+--!
+
+
+
+ENTITY syncGenerator IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits in counter
+           g_IPBUS_WIDTH : integer := 32;
+           g_NUM_TRIG_SOURCES : integer := 4 --! Number of input trigger sources.
+           );
+  PORT
+    (
+
+      -- Input signals
+      clock_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. syncronous with rising clk
+      strobe_i: IN STD_LOGIC;  --! one strobe pulse per 4 clock cycles
+      trigger_sources_i: IN STD_LOGIC_VECTOR(g_NUM_TRIG_SOURCES-1 downto 0); --! array of possible trigger trigger_sources
+      trigger_source_select_i : IN STD_LOGIC_VECTOR(g_IPBUS_WIDTH-1 downto 0); --! Selects which input to use
+
+      threshold_t1_i, threshold_t2_i, threshold_t3_i : IN STD_LOGIC_VECTOR(g_IPBUS_WIDTH-1 downto 0); --! Times at which sequence changes state.
+
+      enable_sequence_i : in std_logic ; --! take high to enable sequence
+
+      enable_internal_cycle_i : in std_logic ; --! take high to enable internal sequence
+      internal_cycle_length_i : IN STD_LOGIC_VECTOR(g_IPBUS_WIDTH-1 downto 0); --! Length of internally generated strobe cycle.
+
+      --! Output Signals
+      shutter_o: OUT STD_LOGIC;
+      trigger_veto_o: OUT STD_LOGIC
+      );
+END syncGenerator;
+
+ARCHITECTURE rtl OF syncGenerator IS
+
+  constant c_SELWIDTH : integer := integer(ceil(log2(real(g_NUM_TRIG_SOURCES))));
+
+  signal s_sel : integer := 0;
+  signal s_counter_value: std_logic_vector(g_COUNTER_WIDTH downto 0); -- One wider that comparator values.
+  signal s_trigger, s_counter_enable, s_reset_counter: std_logic :='0';
+  -- constant c_SELWIDTH : integer := 4; --! Up to 16 different trigger sources
+  signal s_trigger_source_select: std_logic_vector(c_SELWIDTH-1 downto 0);
+  signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0';
+  signal s_shutter , s_veto : std_logic := '0';
+  signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length,  s_truncated_counter_value : unsigned(g_COUNTER_WIDTH-1 downto 0);
+BEGIN
+
+
+  -- Instantiate a counter
+  cmp_Counter: ENTITY work.counterWithResetPreset
+  GENERIC MAP (g_COUNTER_WIDTH => g_COUNTER_WIDTH+1
+           )
+  PORT MAP
+    (
+      clock_i => clock_i,
+      reset_i => s_reset_counter,
+      preset_i => reset_i, --! Preload top bit to halt counter
+      enable_i => s_counter_enable,
+      result_o => s_counter_value); --! std_logic_vector output
+
+
+  --! Process to generate a reset signal for counter
+  --! Will reset ( and hence start to count ) if input trigger is high and
+  --! the sequence isn't running and sequence is enabled.
+  --! (The sequence isn't running if either the counter exceeds T3 or the top
+  --! bit of the counter is set and has stopped running.)
+  p_generateReset: PROCESS (clock_i)
+    BEGIN
+      IF rising_edge(clock_i) THEN
+        if (s_trigger = '1') and
+           ((s_counter_lt_t3 = '0') or (s_counter_value(s_counter_value'left) = '1')) and 
+           (enable_sequence_i = '1') then
+          s_reset_counter<= '1';
+        else
+          s_reset_counter <= '0';
+        end if;
+      END IF;
+  END PROCESS p_generateReset;
+
+  --! Process to stop counter before it wraps round
+  --! and only count when strobe_i is high.
+  p_generateStrobe: PROCESS (clock_i)
+    BEGIN
+      IF rising_edge(clock_i) THEN
+        if ((s_counter_value(s_counter_value'left) = '0') and (strobe_i = '1')) then
+          s_counter_enable <= '1';
+        else
+          s_counter_enable <= '0';
+        end if;
+      END IF;
+  END PROCESS p_generateStrobe;
+
+  -- Trim the source select value and convert to integer.
+  s_trigger_source_select <= trigger_source_select_i(s_trigger_source_select'range);
+  s_sel <= to_integer(unsigned(s_trigger_source_select));
+
+  --! Process to register trigger input
+  p_triggerSelect: PROCESS (clock_i)
+  BEGIN
+    --IF rising_edge(clock_i) and (strobe_i='1') THEN
+    IF rising_edge(clock_i) THEN
+      if (enable_internal_cycle_i='0') then
+        s_trigger <= trigger_sources_i(s_sel); --! Trigger on external signals if not generating internal cycles
+      else
+        s_trigger <= s_counter_gt_cycle; --! Trigger on internal cycle
+      end if;
+
+    END IF;
+  END PROCESS p_triggerSelect;
+
+
+  -- Trim threshold values and convert to unsigned.
+  s_threshold_t1 <= unsigned(threshold_t1_i(s_threshold_t1'range));
+  s_threshold_t2 <= unsigned(threshold_t2_i(s_threshold_t2'range));
+  s_threshold_t3 <= unsigned(threshold_t3_i(s_threshold_t3'range));
+  s_internal_cycle_length <= unsigned(internal_cycle_length_i(s_internal_cycle_length'range) );
+
+  -- Truncate the top bit of the counter ( which is only used to halt count
+  -- when needed.
+  s_truncated_counter_value <= unsigned( s_counter_value(  s_truncated_counter_value'range));
+  
+  --! Process to drive s_counter_lt_t1 , s_counter_lt_t2, s_counter_lt_t3
+  p_comparators: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) and (strobe_i='1') THEN
+
+      if  s_truncated_counter_value < s_threshold_t1  THEN
+        s_counter_lt_t1 <= '1';
+      else
+        s_counter_lt_t1 <= '0';
+      end if;
+
+      if  s_truncated_counter_value < s_threshold_t2  THEN
+        s_counter_lt_t2 <= '1';
+      else
+        s_counter_lt_t2 <= '0';
+      end if;
+
+      if  s_truncated_counter_value < s_threshold_t3 THEN
+        s_counter_lt_t3 <= '1';
+      else
+        s_counter_lt_t3 <= '0';
+      end if;
+
+      if  s_truncated_counter_value > s_internal_cycle_length then
+        s_counter_gt_cycle <= '1';
+      else
+        s_counter_gt_cycle <= '0';
+      end if;
+
+    END IF;
+  END PROCESS p_comparators;
+
+  --! sequence: Emin --> Shutter-on --> Veto-off --> (shutter-off,veto-on)
+  --! NB. Need to ensure T1 < T2 < T3
+  --! If enable_sequence_i=0 then veto is always low. 
+  s_veto <= '0' when ((s_counter_lt_t3 ='1') and (s_counter_lt_t2 = '0')) or (enable_sequence_i='0') else '1';
+  s_shutter <= '1' when (s_counter_lt_t3 ='1') and (s_counter_lt_t1 = '0') else '0';
+
+  --! Process to set output signals
+  p_setOutput: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) and (strobe_i='1') THEN
+      trigger_veto_o <= s_veto;
+      shutter_o <= s_shutter;
+    END IF;
+  END PROCESS p_setOutput;
+
+
+
+
+END rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3f8a62c4d5ff2c1a8806e04ea85c9324b1fe5e00
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
@@ -0,0 +1,177 @@
+--=============================================================================
+--! @file T0_Shutter_Iface_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: T0_Shutter_Iface
+--
+--============================================================================
+--! Entity declaration for T0_Shutter_Iface
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+--! @brief Generates T0 signal and shutter signals for, eg. KPix
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date April 2018
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! \n IPBus Address map:
+--! \li 0x0 Control (bit-0 : high = shutter pulses on)
+--! \li 0x1 Select source
+--! \li 0x2 Internal trig generator period ( units = number of strobe pulses)
+--! \li 0x3 Shutter on time - time between input trigger being received and shutter asserted(T1)
+--! \li 0x4 Veto off time - time between input trigger and veto being de-asserted(T2)
+--! \li 0x5 Shutter off time - time at which shutter de-asserted(T3)
+--! \li 0x8 Pulse T0
+--! \n\n<b>Last changes:</b>\n
+--!
+
+
+
+ENTITY T0_Shutter_Iface IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits in counter
+           g_IPBUS_WIDTH : integer := 32; --! Width of IPBus data bus
+           g_NUM_ACCELERATOR_SIGNALS : integer := 4 --! Number of input trigger sources.
+           );
+  PORT
+    (
+
+      -- Input signals
+      clk_4x_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. syncronous with rising clk
+      clk_4x_strobe_i: IN STD_LOGIC;  --! one strobe pulse per 4 clock cycles
+      accelerator_signals_i: IN STD_LOGIC_VECTOR(g_NUM_ACCELERATOR_SIGNALS-1 downto 0); --! array of possible trigger trigger_sources
+
+      --! IPBus signals
+      ipbus_clk_i: in std_logic;
+      ipbus_i: in ipb_wbus;
+      ipbus_o: out ipb_rbus;
+
+      --! Output Signals
+      shutter_o: OUT STD_LOGIC; --! Shutter signal.
+      shutter_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers. NB. Should be *low* when shutters are disabled.
+      run_active_o: out std_logic;      --! goes high when run is active.
+      T0_o: out std_logic --! T0 synchronization pulse. Pulses on leading edge of run_active_o
+      );
+END T0_Shutter_Iface;
+
+ARCHITECTURE rtl OF T0_Shutter_Iface IS
+
+  signal s_sel : integer := 0;
+  signal s_counter_value: std_logic_vector(g_COUNTER_WIDTH downto 0); -- One wider that comparator values.
+  signal s_trigger, s_counter_enable, s_reset_counter: std_logic :='0';
+
+  signal s_trigger_source_select: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+  signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0';
+  signal s_shutter , s_veto : std_logic := '0';
+  signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+
+  signal s_enable_sequence : std_logic ; --! take high to enable sequence
+  signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
+  -- signal s_T0_ipbus : std_logic; --! T0 synchronization signal on IPBus clock domain.
+  signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
+  constant c_NUM_CTRL_REGS  : integer := 8;
+  constant c_NUM_STAT_REGS  : integer := 1;
+  signal s_ipbus_statusregs:   ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
+  signal s_ipbus_controlregs:  ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
+
+  constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS  - 1 downto 0) := (others => (others => '1'));
+
+--  constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write 1 to bit 0 of this address to produce a enable shutters and produce T0 pulse 
+                                                                 
+begin
+
+  cmp_SyncGen: entity work.syncGenerator
+    generic map (
+              g_COUNTER_WIDTH         => g_COUNTER_WIDTH ,
+              g_IPBUS_WIDTH           => g_IPBUS_WIDTH ,
+              g_NUM_TRIG_SOURCES      => g_NUM_ACCELERATOR_SIGNALS  )
+    port map (
+              clock_i                 => clk_4x_i,
+              reset_i                 => reset_i,
+              strobe_i                => clk_4x_strobe_i,
+              trigger_sources_i       => accelerator_signals_i,
+              trigger_source_select_i => s_trigger_source_select,
+              threshold_t1_i          => s_threshold_t1,
+              threshold_t2_i          => s_threshold_t2,
+              threshold_t3_i          => s_threshold_t3,
+              enable_sequence_i       => s_enable_sequence,
+              internal_cycle_length_i => s_internal_cycle_length,
+              enable_internal_cycle_i => s_enable_internal_cycle,
+              shutter_o               => shutter_o,
+              trigger_veto_o          => shutter_veto_o );
+
+  cmp_ipbusReg: entity work.ipbus_syncreg_v
+    generic map(
+      N_CTRL => c_NUM_CTRL_REGS,
+      N_STAT => c_NUM_STAT_REGS
+      )
+    port map (
+      clk => ipbus_clk_i,
+      rst => reset_i,
+      ipb_in => ipbus_i,
+      ipb_out => ipbus_o,
+      slv_clk => clk_4x_i,
+      d => s_ipbus_statusregs,
+      q=> s_ipbus_controlregs,
+      qmask => c_ipbus_qmask,
+      stb => open,
+      rstb => open
+      );
+
+--  s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
+  s_enable_sequence <=  ( s_ipbus_controlregs(0)(0) and  s_run_active)  when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
+--  s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter 
+  
+  s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
+  s_trigger_source_select <= s_ipbus_controlregs(1);
+
+  s_internal_cycle_length <= s_ipbus_controlregs(2);
+  
+  s_threshold_t1 <= s_ipbus_controlregs(3);
+  s_threshold_t2 <= s_ipbus_controlregs(4);
+  s_threshold_t3 <= s_ipbus_controlregs(5);
+
+  s_run_active <= s_ipbus_controlregs(6)(0);
+  
+  run_active_o <= s_run_active;
+
+  ---- A bodge. I can't figure out which standard IPBus register generates a
+  ---- pulse, so put this logic in parallel.
+  ----------------------
+  --ipbus_generateT0: process (ipbus_clk_i)
+  --begin  -- process ipbus_clk_i
+  --if rising_edge(ipbus_clk_i) then
+
+  --    if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
+  --      s_T0_ipbus <= '1'; -- set T0 signal high
+  --    else
+  --      s_T0_ipbus <= '0';
+  --    end if;
+
+  --  end if;
+  --end process ipbus_generateT0;
+
+  --! Retime T0 generated by IPBus onto clk_4x and align with strobe
+  cmp_T0_retime: entity work.stretchPulse4x
+    port map (
+      clk_4x_i      => clk_4x_i,
+      clk_4x_strobe_i => clk_4x_strobe_i,
+      pulse_i       => s_run_active,
+--      pulse_i       => s_T0_ipbus, 
+      pulse_o       => T0_o);
+
+END rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/TPx3Logic_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/TPx3Logic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e35cfacd18f53ec298aefd1d5f836b05254aa2c
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/TPx3Logic_rtl.vhd
@@ -0,0 +1,177 @@
+--=============================================================================
+--! @file TPx3Logic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
+--
+--! @brief Produces shutters \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 16:06:19 11/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY TPx3Logic IS
+	GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i      				: IN     std_logic;                                    -- ! Rising edge active
+		Start_T0sync_i			: IN 		std_logic;
+		T0syncLen_i				: IN 		std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+      logic_reset_i       	: IN     std_logic;                                    -- active high. Synchronous with clk_4x_logic
+      Busy_i					: IN     std_logic;
+		Veto_i					: IN     std_logic;
+		Shutter_o				: OUT 	std_logic;
+		T0sync_o 				: OUT 	std_logic
+   );
+	
+
+-- Declarations
+
+END ENTITY TPx3Logic ;
+
+--
+ARCHITECTURE rtl OF TPx3Logic IS
+
+	type state_values is (st0, st1);
+	signal pres_state, next_state: state_values;
+
+	signal s_Enable : std_logic := '0';
+	signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
+	signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
+	signal Rst_T0sync, T0syncT : 		std_logic;   	--Load signal and flag for the T0sync
+	signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for runs
+	
+BEGIN
+
+	-----------------------------------------------------------------------------
+	-- Counters
+	-----------------------------------------------------------------------------
+	--T0sync counter
+	c_T0sync: entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> Rst_T0sync,
+		InitVal 	=> std_logic_vector(unsigned(T0syncLen_i)-1),
+		Count		=> open,
+		Q 			=> T0syncT
+	);
+  
+  
+  -----------------------------------------------------------------------------
+  -- FSM register
+  -----------------------------------------------------------------------------
+	statereg: process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			pres_state <= next_state;  --Move to the next state
+		end if;
+	end process statereg;
+	
+	
+	-----------------------------------------------------------------------------
+	-- FSM combinational block
+	-----------------------------------------------------------------------------
+	fsm: process(pres_state, s_Start_T0sync, T0syncT)
+	begin
+		next_state<=pres_state;
+		s_T0sync	<='0';
+		Rst_T0sync <= '1';
+		
+		case pres_state is
+			when st0=>
+				if s_Start_T0sync = '1' then 
+					next_state <= st1; --Next state is "Whait for end of T0sync signal"
+				end if;
+			when st1 =>
+				Rst_T0sync <='0';
+				s_T0sync <='1';
+				if T0syncT = '1' then
+					next_state<=st0; --Next state is "Whait for end of T0-sync counter"
+				end if;
+			when others=>
+				next_state<=st0; --Next state is "Whait for T0sync start"
+		end case;
+	end process fsm;
+
+  
+	-----------------------------------------------------------------------------
+	-- Busy signals
+	-----------------------------------------------------------------------------
+	s_Enable <= not Veto_i;
+	s_Shutter <= not Busy_i and not Veto_i;
+	--Shutter_o <= s_Shutter;
+	--T0sync_o <= s_T0sync;
+  
+	
+	-----------------------------------------------------------------------------
+	-- Count runs and synchronization
+	-----------------------------------------------------------------------------
+	p_run_counter: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Start_T0sync_d1 <= Start_T0sync_i;
+			s_Start_T0sync_d2 <= s_Start_T0sync_d1;
+			s_Start_T0sync_d3 <= s_Start_T0sync_d2;
+			s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3); 
+		
+			s_Shutter_d1 <= s_Shutter;
+		
+			if logic_reset_i = '1' then
+				s_RunNumber <= (others => '0');
+			elsif s_Shutter='1' and s_Shutter_d1='0' then
+				s_RunNumber <= s_RunNumber + 1;
+			end if;
+		end if;
+		-- Signals synchronous with falling edge clock
+		if falling_edge(clk_i) then
+			s_Shutter_d1f <= s_Shutter;
+			Shutter_o <= s_Shutter_d1f;
+			
+			s_T0sync_d1f <= s_T0sync;
+			T0sync_o <= s_T0sync_d1f;
+		end if;
+  end process p_run_counter;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/TPx3_iface_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/TPx3_iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f576ac1ba6db98f073e84d5cf6abb1de943fb998
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/TPx3_iface_rtl.vhd
@@ -0,0 +1,160 @@
+--! @file TPx3_iface_rtl.vhd
+--! @brief Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
+--! Accepts T0 sync signal and shutter signal from telescope and re-transmits.
+--! @details
+--! IPBus address map:
+--! 00 - shutter. Bit 0. Output shutter = external shutter XOR ipbus shutter
+--! 01 - T0 write to pulse T0.
+--! @author David Cussans
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+
+entity TPx3_iface is
+
+  port (
+    clk_4x_i      : in  std_logic;    --! system clock
+    clk_4x_strobe : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    T0_p_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_n_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_o          : out std_logic;    --! T0 signal retimed onto system clock
+    shutter_p_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_n_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_o          : out std_logic;    --! shutter signal retimed onto system clock
+
+    ipbus_clk_i            : IN     std_logic; --! IPBus system clock
+    ipbus_i                : IN     ipb_wbus;
+    ipbus_o                : OUT    ipb_rbus
+          
+    );     
+
+end entity TPx3_iface;
+
+architecture rtl of TPx3_iface is
+
+  signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+  signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
+  signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+
+  signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+
+  signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_external_signal_mask : std_logic_vector(ipbus_i.ipb_wdata'range) := ( others => '0'); --! Set bits to mask external signals : 0 to mask external T0 , set bit 1 to mask external shutter
+  signal s_maskExternalShutter , s_maskExternalT0 : std_logic := '0';  -- ! Set to 1 to mask external signals
+                                                                             
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  
+begin  -- architecture rtl
+
+  --------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_T0_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+        case ipbus_i.ipb_addr(1 downto 0) is
+          when "00" => s_shutter_ipbus <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter
+          when "01" => s_T0_ipbus <= '1';
+          when "10" => s_external_signal_mask <= ipbus_i.ipb_wdata;
+          when others => null;
+        end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+
+
+    ------------------
+    
+  cmp_IBUFDS_T0 : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_T0,  -- Buffer output
+        I =>  T0_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => T0_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+        
+    p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
+  begin  -- process p_T0_retime
+    if rising_edge(clk_4x_i)  then
+
+      s_maskExternalShutter <= s_external_signal_mask(1);
+      s_maskExternalT0 <= s_external_signal_mask(0);
+        
+      s_T0_d1 <= s_T0;
+      s_T0_d2 <= s_T0_d1;
+
+      -- Register IPBus clocked signals onto clk 4x. So clk4x must be faster
+      -- than ipbus_clk for this to work.
+      s_T0_ipbus_d1 <= s_T0_ipbus;
+      s_T0_ipbus_d2 <= s_T0_ipbus_d1;
+
+      -- Shutter is a DC level, so clock speeds don't matter.
+      s_shutter_ipbus_d1 <= s_shutter_ipbus;
+      s_shutter_ipbus_d2 <= s_shutter_ipbus_d1;
+      
+      
+      -- Stretch T0_i pulse to 4 clock cycles on clk4x
+      if ( (( s_T0_d2 = '1' ) and ( s_maskExternalT0 = '0')) or ( s_T0_ipbus_d2 = '1' )) then
+        s_stretch_T0_in <= '1';
+        s_stretch_T0_in_sr <= "111";
+      else
+        s_stretch_T0_in <= s_stretch_T0_in_sr(0);
+        s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (clk_4x_strobe  = '1') and ( s_stretch_T0_in = '1' ) then
+        T0_o <= '1';
+        s_T0_out_sr <= "111";
+      else
+        T0_o <= s_T0_out_sr(0);
+        s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
+      end if;
+
+      
+    end if;
+  end process p_T0_retime;
+    
+  cmp_IBUFDS_shutter : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_shutter,  -- Buffer output
+        I =>  shutter_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => shutter_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  -- Just retime onto the 4x clock. Probably should retime onto 1x clock.
+  p_shutter_retime: process (s_shutter , clk_4x_i) is
+  begin  -- process p_shutter_retime
+    if rising_edge(clk_4x_i)  then
+      s_shutter_d1 <= ( ( s_shutter and not s_maskExternalShutter ) xor s_shutter_ipbus );
+      s_shutter_d2 <= s_shutter_d1;
+      shutter_o    <= s_shutter_d2;
+    end if;
+  end process p_shutter_retime;
+
+end architecture rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..217fa22453b724a07f70ef4bf27f159013828499
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl.vhd
@@ -0,0 +1,158 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    --auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_low_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (lowest 32-bits)
+    triggerPattern_high_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (highest 32-bits)
+    loadPatternHi_i    : in std_logic; --! Pattern (high 32 bits) is loaded when loadPatternHi goes high.
+    loadPatternLo_i    : in  std_logic);  --! Pattern (low 32 bits) is loaded when loadPatternLo goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR_low , s_configEnableSR_low: std_logic_vector( triggerPattern_low_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configDataSR_high , s_configEnableSR_high: std_logic_vector( triggerPattern_high_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit_low, s_configBit_high, s_configEnable_low, s_configEnable_high : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut_low, s_trigOut_high, s_auxTrigOut_low, s_auxTrigOut_high : std_logic := '0';  -- registers for output data. (s_auxTrig high and low should be removed)
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  -- We now need 6 inputs in the LUT and we need to dynamically change it so we merge two 5-inputs together:
+  -- one does the low 32 bits of the address table, the other the high 32 bits.
+  LUT_low : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs (exclude case with no input at all)
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => open ,  -- 4-LUT output
+      O6 => s_trigOut_low, -- 5-LUT output
+      CDI => s_configBit_low, -- Reconfiguration data input
+      CE => s_configEnable_low, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+      );
+   
+   LUT_high : CFGLUT5
+    generic map (
+        INIT => X"FFFFFFFF") --! Default to "OR" of all inputs
+    port map (
+        CDO => open, -- Reconfiguration cascade output
+        O5 => open ,  -- 4-LUT output
+        O6 => s_trigOut_high, -- 5-LUT output
+        CDI => s_configBit_high, -- Reconfiguration data input
+        CE => s_configEnable_high, -- Reconfiguration enable input
+        CLK => configClk_i, -- Clock input
+        I0 => triggers_i(0), -- Logic data input
+        I1 => triggers_i(1), -- Logic data input
+        I2 => triggers_i(2), -- Logic data input
+        I3 => triggers_i(3), -- Logic data input
+        I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+    );   
+
+  p_controlInitLo: process (configClk_i , triggerPattern_low_i , loadPatternLo_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Control configuration
+      if ( loadPatternLo_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR_low <= triggerPattern_low_i;
+        s_configEnableSR_low <= ( others => '1');
+        s_configBit_low <= '0';
+        s_configEnable_low <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit_low    <= s_configDataSR_low( s_configDataSR_low'left ); --! Shift in MSB first.
+        s_configDataSR_low <= s_configDataSR_low( s_configDataSR_low'left-1 downto 0) & '0'; --! Shift up
+                
+        s_configEnable_low <= s_configEnableSR_low ( s_configEnableSR_low'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR_low <= s_configEnableSR_low( s_configEnableSR_low'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInitLo;
+  
+  -- Add a second control for the secondary LUT introduced when we moved to 6 inputs.
+  p_controlInitHi: process (configClk_i , triggerPattern_high_i,  loadPatternHi_i) is
+    begin  -- process p_controlInit
+  
+      if rising_edge(configClk_i) then
+  
+        -- Control configuration
+        if ( loadPatternHi_i = '1' ) then -- Load pattern into shift register
+          s_configDataSR_high <= triggerPattern_high_i;
+          s_configEnableSR_high <= ( others => '1');
+          s_configBit_high <= '0';
+          s_configEnable_high <= '0';
+        else -- If load isn't active then shift data out.
+          s_configBit_high    <= s_configDataSR_high( s_configDataSR_high'left ); --! Shift in MSB first.
+          s_configDataSR_high <= s_configDataSR_high( s_configDataSR_high'left-1 downto 0) & '0'; --! Shift up
+                  
+          s_configEnable_high <= s_configEnableSR_high ( s_configEnableSR_high'left); --! enable will stay high for as long as there is data in config data SR
+          s_configEnableSR_high <= s_configEnableSR_high( s_configEnableSR_high'left-1 downto 0) & '0'; --! Shift up
+        end if;
+  
+    end if;
+    end process p_controlInitHi;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+        if triggers_i(5) = '0' then -- the LUT has 5 inputs. We use a MUX to considere the 6th one (triggers_i(5)).
+            trigger_o <=  s_trigOut_low;
+            --auxTrigger_o <= s_auxTrigOut_low;
+        else
+            trigger_o <=  s_trigOut_high;
+            --auxTrigger_o <= s_auxTrigOut_high;
+        end if;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl_BKP.vhd b/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..32b57b74f04c1898bbbb6668a1f1f6d6e6e1bee5
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/coincidenceLogic_rtl_BKP.vhd
@@ -0,0 +1,108 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with
+    loadPattern_i    : in  std_logic);  --! Pattern is loaded when loadPattern goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit , s_configEnable : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut , s_auxTrigOut : std_logic := '0';  -- registers for output data.
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  CFGLUT5_inst : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => s_trigOut ,  -- 4-LUT output
+      O6 => s_auxTrigOut, -- 5-LUT output
+      CDI => s_configBit, -- Reconfiguration data input
+      CE => s_configEnable, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => '1' --! Tie high to set O5 and O6 to different functions.
+      );
+
+  p_controlInit: process (configClk_i , triggerPattern_i , loadPattern_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Contol configuration
+      if ( loadPattern_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR <= triggerPattern_i;
+        s_configEnableSR <= ( others => '1');
+        s_configBit <= '0';
+        s_configEnable <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit    <= s_configDataSR( s_configDataSR'left ); --! Shift in MSB first.
+        s_configDataSR <= s_configDataSR( s_configDataSR'left-1 downto 0) & '0'; --! Shift up
+        
+        s_configEnable <= s_configEnableSR ( s_configEnableSR'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR <= s_configEnableSR( s_configEnableSR'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInit;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+      trigger_o <=  s_trigOut;
+      auxTrigger_o <= s_auxTrigOut;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/counterDownGated_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/counterDownGated_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0877c61944b8eca5dfe51a1b88ae714a2384587
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/counterDownGated_rtl.vhd
@@ -0,0 +1,84 @@
+--=============================================================================
+--! @file counterDownGated_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- 
+--
+--! @brief CountDown - load with a value and counts to zero. Flag Q_o goes high during count
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 15:42:31 01/15/2013 
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: 
+--! Author: David Cussans. Added gating. Made reset synchronous. 20/2/18
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY CounterDownGated IS
+  GENERIC(
+    g_MAX_WIDTH: positive := 32
+    );
+  PORT( 
+		Clk_i		: in  std_logic; --! Rising edge active
+                Gate_i          : in  std_logic; --! If high circuit clocks. If low, no change
+		Reset_i		: in  std_logic; --! Active high. Synchronous
+		Load_i 		: in  std_logic; --! Take high to load counter with InitVal
+		InitVal_i 	: in std_logic_vector(g_MAX_WIDTH-1 downto 0);     --! Initial value ( counts down from here )
+		Count_o		: out Std_logic_vector(g_MAX_WIDTH-1 downto 0);    --! Current Count value
+		Q_o 		: out std_logic                                  --! 0 while counting. 1 otherwise
+                
+	);
+END ENTITY Counterdowngated;
+
+architecture rtl of Counterdowngated is 
+	signal s_cnt	: std_logic_vector(g_MAX_WIDTH-1 downto 0) := (others => '0');
+	signal s_Qtmp	: std_logic;
+  
+begin 
+	Counter: process (Clk_I)
+	begin                   
+          if rising_edge(Clk_I) and ( Gate_i = '1') then
+            if (Reset_I='1') then 
+              s_cnt <= (others =>'0');
+              elsif (Load_I='1') then
+                s_cnt <= Initval_I;
+              else
+                if s_Qtmp='0' then
+                  s_cnt <= std_logic_vector(unsigned(s_cnt) - 1);
+                end if;
+              end if;
+            end if; 
+	end process;
+      
+	s_Qtmp <= 	'1' when s_cnt=(s_cnt'range=>'0') else '0';
+          
+	Count_O <= s_cnt;
+	Q_O <= s_Qtmp;
+        
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/counterWithResetPreset_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/counterWithResetPreset_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e1ffe68022cc7063e9e21fa9d69ed28c3eb404ca
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/counterWithResetPreset_rtl.vhd
@@ -0,0 +1,87 @@
+--=============================================================================
+--! @file counterWithResetPreset_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: counterWithResetPreset (counterWithResetPreset / rtl)
+--
+--============================================================================
+--! Entity declaration for counterWithResetPreset
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+--! @brief Simple counter with synchronous reset and top-bit preload
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date Feb\2012
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! \n\n<b>Last changes:</b>\n
+--! 5/Mar/12  DGC Changed to use numeric_std\n
+--! 26/Feb/14 DGC Added registers to output to aid timing closure.
+--!
+
+
+
+ENTITY counterWithResetPreset IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
+           g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
+           );
+  PORT
+    (
+      clock_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. synchronous with rising clk. Takes output to 0
+      preset_i: IN STD_LOGIC;  --! Active high. synchronous with rising clk. Takes highest bit to 1
+      enable_i: IN STD_LOGIC;  --! counts when enable=1
+      result_o:	OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
+
+      );
+END counterWithResetPreset;
+
+ARCHITECTURE rtl OF counterWithResetPreset IS
+  type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ;  -- --! Array of arrays for output register...
+  signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0'));  -- --! Output registers.
+
+BEGIN
+
+  --! Process to count up from zero when enable_i is high.
+  p_counter: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) THEN
+      IF (reset_i = '1') THEN
+        s_output_registers(0) <= (others => '0');
+      ELSIF (preset_i='1') THEN
+        s_output_registers(0)(g_COUNTER_WIDTH-1) <= '1'; -- Preload highest bit to '1'
+      ELSIF (enable_i='1') THEN
+        s_output_registers(0) <= s_output_registers(0) + 1;
+      END IF;
+    END IF;
+  END PROCESS p_counter;
+
+  --! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
+  generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
+
+    --! An individual register
+    p_outputRegister: process (clock_i)
+    begin  -- process p_outputRegister
+      if rising_edge(clock_i) then
+        s_output_registers( v_register) <=
+        s_output_registers( v_register-1);
+      end if;
+    end process p_outputRegister;
+
+  end generate generate_registers;  -- v_register
+
+  --! Copy the (registered) result to the output
+  result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
+
+END rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/counterWithReset_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/counterWithReset_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2512f986b5588355209563d702e313eec3fcd86d
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/counterWithReset_rtl.vhd
@@ -0,0 +1,84 @@
+--=============================================================================
+--! @file counterWithReset_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: counterWithReset (counterWithReset / rtl)
+--
+--============================================================================
+--! Entity declaration for counterWithReset
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+--! @brief Simple counter with synchronous reset
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date Feb\2012
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! \n\n<b>Last changes:</b>\n
+--! 5/Mar/12  DGC Changed to use numeric_std\n
+--! 26/Feb/14 DGC Added registers to output to aid timing closure.
+--! 
+
+
+
+ENTITY counterWithReset IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
+           g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
+           );
+  PORT
+    (
+      clock_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. syncronous with rising clk
+      enable_i: IN STD_LOGIC;  --! counts when enable=1
+      result_o:	OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
+      
+      );
+END counterWithReset;
+
+ARCHITECTURE rtl OF counterWithReset IS
+  type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ;  -- --! Array of arrays for output register...
+  signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0'));  -- --! Output registers.
+  
+BEGIN
+
+  --! Process to count up from zero when enable_i is high.
+  p_counter: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) THEN
+      IF (reset_i = '1') THEN
+        s_output_registers(0) <= (others => '0');
+      ELSIF (enable_i='1') THEN
+        s_output_registers(0) <= s_output_registers(0) + 1;
+      END IF;
+    END IF;
+  END PROCESS p_counter;
+
+  --! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
+  generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
+
+    --! An individual register
+    p_outputRegister: process (clock_i)
+    begin  -- process p_outputRegister
+      if rising_edge(clock_i) then
+        s_output_registers( v_register) <=
+        s_output_registers( v_register-1);
+      end if;
+    end process p_outputRegister;
+    
+  end generate generate_registers;  -- v_register
+
+  --! Copy the (registered) result to the output 
+  result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
+  
+END rtl;		
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/delayPulse4x_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/delayPulse4x_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..687b1410dc864e429574a9e79785f3b86547b894
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/delayPulse4x_rtl.vhd
@@ -0,0 +1,68 @@
+--! @file DelayPulse4x_rtl.vhd
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+--! @brief Takes a pulse on 4x clock , delays it and produces a pulse with a width determined by clk_4x_strobe
+--
+--
+--! @details
+--! @author David Cussans
+
+entity DelayPulse4x is
+  generic (
+    g_MAX_WIDTH : positive := 32);
+  port (
+    clk_4x_i                    : in  std_logic;    --! system clock
+    clk_4x_strobe_i               : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    delay_cycles_i              : in std_logic_vector(g_MAX_WIDTH-1 downto 0); --! Number of strobes of clk_4x_strobe to delay pulse by
+    pulse_i                     : in  std_logic;    --! Input pulse
+    pulse_o                     : out std_logic    --! Output pulse
+    );
+end entity DelayPulse4x;
+
+architecture rtl of DelayPulse4x is
+
+  signal s_retimed_pulse : std_logic := '0';  --! 4 cycles of clk_4x_i , synchronized by 4x strobe
+  signal s_counting_down_n, s_counting_down_n_d1 : std_logic := '0';  --! low if delay is counting down
+  
+begin  -- architecture rtl
+
+  cmp_stretchPulse: entity work.stretchPulse4x
+    port map (
+      clk_4x_i        => clk_4x_i,
+      clk_4x_strobe_i => clk_4x_strobe_i,
+      pulse_i         => pulse_i,
+      pulse_o         => s_retimed_pulse);
+
+  cmp_counter: entity work.counterDownGated
+    generic map (
+      g_MAX_WIDTH => g_MAX_WIDTH)
+    port map (
+      clk_i     => clk_4x_i,
+      Gate_i    => clk_4x_strobe_i,
+      Reset_i   => '0',
+      Load_i    => s_retimed_pulse,
+      InitVal_i => delay_cycles_i,
+      Count_o   => open,
+      Q_o       => s_counting_down_n);
+
+  
+  -- purpose: detects rising edge of s_counting_down_n
+  -- type   : combinational
+  -- inputs : clk_4x_i
+  -- outputs: pulse_o
+  p_fallingEdge: process (clk_4x_i) is
+  begin  -- process p_fallingEdge
+    if rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1') then
+      if s_counting_down_n = '1' and s_counting_down_n_d1 = '0' then
+        pulse_o <= '1';
+      else
+        pulse_o <= '0';
+      end if;
+      s_counting_down_n_d1 <= s_counting_down_n;
+    end if;
+  end process p_fallingEdge;
+  
+
+end architecture rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b944e1a8e0580f7032dd73b8d85c5f67a4141377
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_AIDA_rtl.vhd
@@ -0,0 +1,154 @@
+--=============================================================================
+--! @file DUTInterface_AIDA_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
+--
+--------------------------------------------------------------------------------
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+--! @brief "AIDA Style" Interface to a Device Under Test (DUT) connector.
+--! factorized from original DUTInterfaces_rtl.vhd firmware.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 1/Sept/2015
+--!
+--! @version v0.1
+--!
+--! @details
+--
+
+ENTITY DUTInterface_AIDA IS
+   GENERIC( 
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;      --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;      --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;      --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;      --! Goes high to indicate data-taking active. Gets passed to DUT pins
+      -- ignore_shutter_veto_i   : in     std_logic;
+      ignore_dut_busy_i       : in     std_logic;
+      --dut_mask_i              : in     std_logic;      --! Set high if DUT is active. Moved one level up
+      busy_o                  : OUT    std_logic;      --! goes high when DUT is busy or vetoed by shutter
+      
+      -- Signals to/from DUT
+      dut_busy_i       : IN     std_logic;     --! BUSY input from DUTs
+      dut_clk_o        : OUT    std_logic;     --! clocks trigger data when in EUDET mode
+      dut_reset_or_clk_o : OUT    std_logic;     --! Either reset line or trigger
+      dut_shutter_o      : OUT    std_logic;     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      dut_trigger_o      : OUT    std_logic     --! Trigger output
+
+   );
+
+-- Declarations
+
+END ENTITY DUTInterface_AIDA ;
+
+--
+ARCHITECTURE rtl OF DUTInterface_AIDA IS
+
+  signal s_strobe_4x_logic_d1 : std_logic;
+  signal s_dut_clk : std_logic := '0';  -- Clock to be sent to DUT connectors ( before final register )
+  signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+  signal s_stretch_trig_in : std_logic := '0';  -- ! stretched version of trigger_i 
+  signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
+  signal s_trigger_out : std_logic := '0';  -- ! trigger shifted to start on strobe_4x_logic
+
+  -- Set length of output trigger here ( output length = length of this vector + 1 ) 
+  signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
+  
+                                                               
+BEGIN
+
+     
+  -- Copy reset/clk signal straight through
+  dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
+
+  dut_shutter_o <= shutter_to_dut_i;
+      
+  -- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
+  -- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_i
+  -- outputs: s_dut_clk
+  p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
+  begin  -- process p_dut_clk_gen
+    if rising_edge(clk_4x_logic_i) then
+      if (strobe_4x_logic_i = '1') then
+        s_dut_clk <= '1';
+        s_dut_clk_sr <= "001";
+      else
+        s_dut_clk <= s_dut_clk_sr(0);
+        s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);          
+      end if;
+    end if;
+  end process p_dut_clk_gen;
+
+  -- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic 
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
+  -- outputs: s_premask_trigger_to_dut
+  p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
+  begin  -- process p_dut_trig_retime
+    if rising_edge(clk_4x_logic_i)  then
+
+      -- Stretch trigger_i pulse to 4 clock cycles on clk4x
+      if trigger_i = '1' then
+        s_stretch_trig_in <= '1';
+        s_stretch_trig_in_sr <= ( others => '1' );
+      else
+        s_stretch_trig_in <= s_stretch_trig_in_sr(0);
+        s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (strobe_4x_logic_i  = '1') and ( s_stretch_trig_in = '1' ) then
+        s_trigger_out <= '1';
+        s_trigger_out_sr <= ( others => '1' );
+      else
+        s_trigger_out <= s_trigger_out_sr(0);
+        s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
+      end if;
+      
+    end if;
+  end process p_dut_trig_retime;
+
+    
+  -- purpose: register for internal signals and output signals
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
+  -- outputs: busy_o
+  register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
+  begin  -- process register_signals
+    if rising_edge(clk_4x_logic_i) then
+
+      s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
+
+      --busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
+      --          ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
+                
+      --busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( (dut_busy_i and DUT_mask_i )  );
+      --busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or ( dut_busy_i    );
+      busy_o <= dut_busy_i;
+      
+      dut_clk_o <= s_dut_clk ;
+      --dut_trigger_o <= DUT_mask_i and s_trigger_out;
+      dut_trigger_o <= s_trigger_out;
+      
+    end if;
+  end process register_signals;
+
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_EUDET_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_EUDET_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..602df58568c7d588bd3a3bf458d7189ae8203420
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterface_EUDET_rtl.vhd
@@ -0,0 +1,281 @@
+--! @file
+-------------------------------------------------------------------------------
+--
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! @brief "EUDET style" interfaces to a DUT connection. Outputs TRIGGER and receives DUT_CLK and BUSY
+--! lines. Adapted from Trigger_Signal_Controller from EUDET TLU firmware.
+--!
+--! @author David.Cussans@bristol.ac.uk
+--! @date 1/Sept/2015
+------------------------------------------------------------------------------------
+entity DUTInterface_EUDET is
+  GENERIC( 
+    g_TRIGGER_DATA_WIDTH : positive := 32 -- was32
+   );
+  port (
+    rst_i : in std_logic;                --! asynchronous reset. Active high
+    busy_o : out std_logic;             --! low if FSM is in IDLE state, high otherwise
+    fsm_state_value_o : out std_logic_vector(3 downto 0);  --! detailed status of FSM.
+    trigger_i : in std_logic;        --! Trigger retimed onto system clock.active high. 
+    trigger_counter_i : in std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  --! event number
+    system_clk_i : in std_logic;          --! rising edge active clock from TLU
+    reset_or_clk_to_dut_i   : IN     std_logic;  --! Synchronization signal. Passed to DUT pins
+    shutter_to_dut_i        : IN     std_logic;  --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto flag set high
+    -- ignore_shutter_veto_i        : in     std_logic;
+    enable_dut_veto_i : in std_logic;      --! If high: if DUT raises dut_busy_i, then  busy_o is raised
+    -- Connections to DUT:
+    dut_clk_i : in std_logic;             --! rising edge active clock from DUT
+    dut_busy_i : in std_logic;            --! from DUT
+    dut_shutter_o      : OUT    std_logic;     --! Shutter output.
+    dut_trigger_o : out std_logic    --! trigger to DUT
+    );
+end DUTInterface_EUDET;
+
+architecture rtl of DUTInterface_EUDET is
+
+-----------------------------------------------------------------------------
+-- Declarations for state machine
+  type state_type is (IDLE , WAIT_FOR_BUSY_HIGH , TRIGGER_DEGLITCH_DELAY1 ,
+                      TRIGGER_DEGLITCH_DELAY2 , WAIT_FOR_BUSY_LOW 
+                     , DUT_INITIATED_VETO );
+--                      );
+  signal state , next_state : state_type;
+
+  -- Xilinx Voodoo for state machine
+  attribute SAFE_IMPLEMENTATION : string;
+  attribute SAFE_IMPLEMENTATION of state : signal is "yes";
+  -- End of Xilinx Voodoo
+
+-----------------------------------------------------------------------------
+
+--  signal internal_clk : std_logic;
+  signal serial_trig_data : std_logic;
+  signal trig_shift_reg : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  
+                                        -- shift register storing parallel trigger data
+--  signal d1_output  :  std_logic;
+--  signal d2_output  :  std_logic;
+  signal dut_rising_edge  :  std_logic;
+  signal shift_reg_ce  :  std_logic;
+
+  signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic;  -- ! registered values
+  signal trigger_counter_copy : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  --! registered copy of event number
+  
+begin  -- rtl
+
+
+  dut_shutter_o <= shutter_to_dut_i ; -- for now just pass through.
+  
+  -- purpose: suppress meta-stability by registering input signals.
+  -- type   : combinational
+  -- inputs : dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2
+  -- outputs: dut_busy_r2 , dut_clk_r2
+  register_signals: process ( dut_busy_r1 , dut_clk_r1 , system_clk_i )
+  begin  -- process register_signals
+    if rising_edge(system_clk_i) then
+
+      dut_busy_r2 <= dut_busy_r1 ;
+      dut_clk_r2 <= dut_clk_r1;
+      dut_busy_r1 <= dut_busy_i ;
+      dut_clk_r1 <= dut_clk_i;
+      
+    end if;
+  end process register_signals;
+
+
+  
+  rising_edge_pulse: entity work.single_pulse
+    port map (
+      level => dut_clk_i,
+      clk   => system_clk_i,
+      pulse => dut_rising_edge);
+
+  
+-- look for the rising edge of DUT clock and enable CE for one cycle.
+  -- I have a nasty suspicion that meta-stability issues may make this
+  -- go horribly wrong .
+-- Need to add timing constraint that shift_reg_ce must arrive before clock at trig_data_driver
+-- also WAIT_FOR_BUSY_LOW must not mess things up.
+  clk_enable_select: process (state, dut_rising_edge)
+begin  -- process
+  if (state=WAIT_FOR_BUSY_LOW) then
+    shift_reg_ce <= dut_rising_edge;
+  else
+    shift_reg_ce <= '0';
+  end if;
+end process;
+
+  
+   
+  
+  -- purpose: controls the serial_trig_data line
+  -- type   : combinational
+  -- inputs : system_clk_i , trigger_counter_i
+  -- outputs: serial_trig_data
+  trig_data_driver: process (system_clk_i , trigger_counter_copy , shift_reg_ce , trig_shift_reg , state)
+  begin
+    
+    if rising_edge( system_clk_i ) then
+
+      -- if busy is high in response to a trigger shift data out of
+      -- register on rising edge of DUT clock . This is done by having a slow
+      -- DUT clock and setting shift_reg_ce for one cycle of system_clk_i when
+      -- the DUT clock rising edge comes by.
+      if (shift_reg_ce ='1' ) then
+        trig_shift_reg <= '0' & trig_shift_reg(g_TRIGGER_DATA_WIDTH-1 downto 1);
+        serial_trig_data <= trig_shift_reg(0);
+
+      -- otherwise load shift register if we have just had a trigger.
+      elsif (state = WAIT_FOR_BUSY_HIGH ) then        
+	-- only clock out bottom 15 bits of data. 
+        -- (replace fixed width with a mask at some stage ?)
+	   trig_shift_reg <=  "00000000000000000" & trigger_counter_copy(14 downto 0);
+        serial_trig_data <= '0';
+      end if;
+      
+      if ( state = IDLE ) and ( trigger_i = '1') then
+        trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
+      end if;
+
+    end if;
+    
+  end process trig_data_driver;
+
+
+  -- purpose: Determine the next state
+  -- type   : combinational
+  -- inputs : state,Dut_Busy_r2, trigger_i
+  state_logic: process (state,  trigger_i ,  enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
+  begin  -- process state_logic
+    case state is
+	 
+      when IDLE =>
+        if ( trigger_i = '1') then  -- respond to trigger going high
+          next_state <= WAIT_FOR_BUSY_HIGH;  -- wait for DUT to respond to busy
+          --trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
+
+        elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then      -- If DUT asserts DUT_CLK_I then veto triggers
+          next_state <= DUT_INITIATED_VETO;          
+
+        else          
+          next_state <= IDLE;
+        end if;
+
+      when WAIT_FOR_BUSY_HIGH =>
+        if (DUT_Busy_r2 = '1') then
+          next_state <= TRIGGER_DEGLITCH_DELAY1;
+        else
+          next_state <= WAIT_FOR_BUSY_HIGH;
+        end if;
+
+        -- put in a pause to supress glitch in output trigger
+        -- this is an inelegant (to say the least ) way of doing it.
+      when TRIGGER_DEGLITCH_DELAY1 =>
+          next_state <= TRIGGER_DEGLITCH_DELAY2;
+
+      -- delay for two clock cycles.
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        next_state <= WAIT_FOR_BUSY_LOW;
+
+
+
+      when WAIT_FOR_BUSY_LOW =>
+        if (DUT_Busy_r2 = '1')  then
+          next_state <= WAIT_FOR_BUSY_LOW;
+        else
+          next_state <= IDLE;
+        end if;        
+
+      when DUT_INITIATED_VETO =>
+        if (( dut_clk_r2 = '0' ) or ( enable_dut_veto_i = '0')) then
+          next_state <= IDLE;
+        else
+          next_state <= DUT_INITIATED_VETO;
+        end if;
+        
+    end case;
+  end process state_logic;
+
+  -- determine clock select and trigger_mux from FSM state
+
+  
+  -- purpose: Determines the state of the dut_trigger_o output based on the state of the FSM
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: dut_trigger_o
+  output_logic: process (state,serial_trig_data)
+  begin  -- process output_logic
+    if ( state = IDLE ) then
+      -- waiting for external trigger to arrive...
+      dut_trigger_o <= '0';
+    elsif ((state = WAIT_FOR_BUSY_HIGH) or ( state=TRIGGER_DEGLITCH_DELAY1) or (state=TRIGGER_DEGLITCH_DELAY2) ) then
+      -- wait until the BUSY line goes high, then continue to hold TRIGGER high for two clock cycles.
+      dut_trigger_o <= '1';
+    elsif (state = WAIT_FOR_BUSY_LOW) then
+      -- if BUSY is high then connect TRIGGER to serial trigger number register.
+      dut_trigger_o <= serial_trig_data;
+    else
+      dut_trigger_o <= '0';
+    end if;
+  end process output_logic;
+
+    -- purpose: Register that holds the current state of the FSM
+  -- type   : combinational
+  -- inputs : system_clk_i , rst_i
+  -- outputs: state
+  state_register: process (system_clk_i , rst_i)
+  begin  -- process state_register
+    if (rst_i = '1') then
+      state <= IDLE;
+    elsif rising_edge(system_clk_i) then
+      state <= next_state;
+    end if;
+  end process state_register;
+
+
+  -- purpose: sets the value of clock_select based on FSM state
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: clock_select , trigger_muxsel , fsm_state
+  set_busy: process (system_clk_i , state)
+  begin  -- process set_muxsel
+    if rising_edge(system_clk_i) then
+          if (state = IDLE) then
+            busy_o <= '0'; -- If idle, then busy is low.
+          else
+            busy_o <= '1'; -- For all other states, busy is high
+          end if;
+    end if;
+ end process set_busy;
+  
+  -- purpose: Sets the fsm_state_value_o vector to a number representing the current state
+  -- type   : combinational
+  -- inputs : system_clk_i , state
+  -- outputs: fsm_state_value_o
+  store_state: process (system_clk_i , state)
+  begin  -- process store_state
+    case state is
+      when IDLE =>
+        fsm_state_value_o <= "0000";
+      when WAIT_FOR_BUSY_HIGH =>
+        fsm_state_value_o <= "0001";
+      when TRIGGER_DEGLITCH_DELAY1 =>
+        fsm_state_value_o <= "0010";
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        fsm_state_value_o <= "0011";
+      when WAIT_FOR_BUSY_LOW =>
+        fsm_state_value_o <= "0100";
+      when DUT_INITIATED_VETO =>
+        fsm_state_value_o <= "0101";
+      when others =>
+        fsm_state_value_o <= "1111";
+    end case;
+  end process store_state;
+
+
+
+  end rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0c6441d4b147992dcde948c75f1eb52ef5107c0
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl.vhd
@@ -0,0 +1,372 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. 
+      shutter_veto_i          : IN     std_logic;                                    --! WHen high DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs (single ended)
+      busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+      clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      
+      --clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      --reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+      --trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      --shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+  signal s_veto_from_duts : std_logic; --! Goes high if any of the DUTs are busy
+    
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+  
+  signal s_SPILL_delay : std_logic_vector(31 downto 0) := (others => '0');
+  signal s_SPILL_wait : std_logic_vector(31 downto 0) := (others => '0');
+  signal s_SPILL_width : std_logic_vector(31 downto 0) := (others => '0');
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 8;
+  constant c_N_STAT : positive := 8;
+--  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+--  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+  signal s_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                  
+  constant c_qmask : ipb_reg_v(c_N_CTRL-1 downto 0) := (others => (others => '1'));
+                  
+  attribute mark_debug : string;
+  attribute mark_debug of s_IgnoreShutterVeto: signal is "true";
+  attribute mark_debug of s_DUT_ignore_busy: signal is "true";
+                                                    
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_syncreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      rst=> '0',--ipbus_reset_i ,
+      ipb_in=>  ipbus_i,
+      ipb_out=> ipbus_o,
+      slv_clk => clk_4x_logic_i,
+      d=>  s_status_to_ipbus,
+      q=>  s_sync_control_from_ipbus,
+      qmask => c_qmask,
+      stb=>  open,
+      rstb => open
+      );
+
+--  -- Synchronize registers from logic clock to ipbus.
+--    sync_status: entity work.synchronizeRegisters
+--    generic map (
+--      g_NUM_REGISTERS => c_N_STAT )
+--    port map (
+--      clk_input_i => clk_4x_logic_i,
+--      data_i      =>  s_status_to_ipbus,
+--      data_o      => s_sync_status_to_ipbus,
+--      clk_output_i => ipbus_clk_i);
+
+--    -- Synchronize registers from logic clock to ipbus.
+--    sync_ctrl: entity work.synchronizeRegisters
+--    generic map (
+--      g_NUM_REGISTERS => c_N_CTRL )
+--    port map (
+--      clk_input_i => ipbus_clk_i,
+--      data_i      =>  s_control_from_ipbus,
+--      data_o      => s_sync_control_from_ipbus,
+--      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+------------------------------------------------------------------        
+--    clk_IOBUFDS_inst : IOBUFDS
+--      generic map (
+--        IOSTANDARD => "BLVDS_25")
+--      port map (
+--        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+--        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+--        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+--        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+--        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+--        );
+    
+        clk_to_dut(dut) <= s_clk_to_dut_aida(dut); -- do we need to disable this using T? No, the TLU now has enable signals.
+        s_clk_from_dut_eudet(dut) <= clk_from_dut(dut);
+        
+------------------------------------------------------------------        
+        -- Now the signals are single ended: remove IBUFDS and use IBUF
+--    busy_IBUFDS_inst : IBUFDS
+--      generic map (
+--        DIFF_TERM => TRUE, -- Differential Termination 
+--        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O => s_busy_from_dut(dut),  -- Buffer output
+--        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+--        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+--      );
+
+--    busy_IBUF_inst : IBUF
+--    generic map(
+--        IBUF_LOW_PWR => TRUE,
+--        IOSTANDARD => "DEFAULT"
+--    )
+--    port map(
+--        O => s_busy_from_dut(dut),
+--        I => busy_from_dut(dut)
+--    );
+    s_busy_from_dut(dut) <= busy_from_dut(dut) ;
+------------------------------------------------------------------        
+   
+--    trig_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+--        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+--      );
+
+    trigger_to_dut(dut) <= s_trigger_to_dut(dut);
+------------------------------------------------------------------        
+     
+--    clk_rst_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+--        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+--      );
+	
+	reset_to_dut(dut) <= s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut); 
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs 
+  dut_shutter_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+--    shutter_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+--        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+--        I =>  s_shutter_to_dut(dut) 	
+--        );
+        
+    shutter_to_dut(dut) <= s_shutter_to_dut(dut) ;	  
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        -- ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        --dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        -- ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs, take into account IGNORE BUSY bit
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or ( s_dut_veto(dut) and (not s_DUT_ignore_busy(dut) ) );
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  s_veto_from_duts <=  s_intermediate_busy_or(g_NUM_DUTS);
+  veto_o <= '0' when s_veto_from_duts ='0' and ((s_IgnoreShutterVeto = '1') or (shutter_veto_i = '0')) else '1';
+  
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= (( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode)) and s_DUT_mask ; -- move DutMask one level up to affect both AIDA and EUDET modes
+      s_dut_veto <= (( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode)) and s_DUT_mask ; -- move DutMask one level up to affect both AIDA and EUDET modes
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl_BKP.vhd b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6a19837a51836d597e13f99770e762fc1743831a
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTInterfaces_rtl_BKP.vhd
@@ -0,0 +1,328 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--! DUT(0) = RJ45 ( J3 )\n
+--! DUT(1) = HDMI ( J1 ) , furthest from RJ45\n
+--! DUT(2) = HDMI ( J2) , closest to RJ45\n
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut_n_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      busy_from_dut_p_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 8;
+  constant c_N_STAT : positive := 8;
+  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                                               
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+
+    clk_IOBUFDS_inst : IOBUFDS
+      generic map (
+        IOSTANDARD => "BLVDS_25")
+      port map (
+        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+        );
+    
+    busy_IBUFDS_inst : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O => s_busy_from_dut(dut),  -- Buffer output
+        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+      );
+		
+   
+    trig_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+      );
+     
+    clk_rst_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+      );
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs except RJ45  ( which (output 0) doesn't have a shutter
+  -- signal. )
+  dut_shutter_io: for dut in 1 to g_NUM_DUTS-1 generate
+
+    shutter_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+        I =>  s_shutter_to_dut(dut) 	
+        );
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or s_dut_veto(dut);
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  veto_o <=  s_intermediate_busy_or(g_NUM_DUTS);
+
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode) ;
+      s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode) ;
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTs_outputs.vhd b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTs_outputs.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5d8974e8731c524196abf56adb50953498cc2ef2
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/dut/DUTs_outputs.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 15.02.2017 13:17:26
+-- Design Name: 
+-- Module Name: DUTs_outputs - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DUTs_outputs is
+    Port ( clk_in : in STD_LOGIC;
+           d_clk_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_trg_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_busy_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_cont_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_spare_o : out STD_LOGIC_VECTOR (3 downto 0));
+end DUTs_outputs;
+
+architecture Behavioral of DUTs_outputs is
+signal toggleme : std_logic := '0'; 
+begin
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+        
+        if rising_edge(clk_in) then   -- rising clock edge
+            toggleme <= not toggleme;
+            d_clk_o(1) <= toggleme;
+            d_clk_o(2) <= toggleme;
+            d_clk_o(3) <= toggleme;
+            d_trg_o <=  (toggleme & toggleme & toggleme & toggleme);
+            d_busy_o <= (toggleme & toggleme & toggleme & toggleme);
+            d_cont_o <= (toggleme & toggleme & toggleme & toggleme);
+            d_spare_o <=(toggleme & toggleme & toggleme & toggleme);
+        end if;
+        d_clk_o(0) <= clk_in;
+    end process gen_clk;
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/enclustra_ax3_pm3_infra.vhd b/AIDA_tlu/components/tlu/firmware/hdl/enclustra_ax3_pm3_infra.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df07ba1ef1daed5d435e98f6807ffed65d8c2c7c
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/enclustra_ax3_pm3_infra.vhd
@@ -0,0 +1,131 @@
+-- enclustra_ax3_pm3_infra
+--
+-- All board-specific stuff goes here
+--
+-- Dave Newbold, June 2013---
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity enclustra_ax3_pm3_infra is
+	port(
+		sysclk: in std_logic; -- ??? board crystal clock
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		rst_125_o: out std_logic;
+		clk_200_o: out std_logic;
+		--clk_aux_o: out std_logic; -- 40MHz generated clock
+		--rst_aux_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		leds: out std_logic_vector(1 downto 0); -- status LEDs
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end enclustra_ax3_pm3_infra;
+
+architecture rtl of enclustra_ax3_pm3_infra is
+
+	signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	signal led_p: std_logic_vector(0 downto 0);
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_7s_extphy_se
+		port map(
+			sysclk => sysclk,
+			clko_125 => clk125,
+			clko_125_90 => clk125_90,
+			clko_200 => clk200,
+			clko_ipb => clk_ipb_i,
+			locked => locked,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl,
+			onehz => onehz
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	rst_125_o <= rst125;
+	clk_200_o <= clk200;
+	
+	stretch: entity work.led_stretcher
+		generic map(
+			WIDTH => 1
+		)
+		port map(
+			clk => clk125,
+			d(0) => pkt,
+			q => led_p
+		);
+	leds <= (led_p(0), locked and onehz);
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_7s_rgmii
+		port map(
+			clk125 => clk125,
+			clk125_90 => clk125_90,
+			clk200 => clk200,
+			rst => rst125,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			pkt => pkt
+		);
+
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/eventBuffer_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/eventBuffer_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b60fe5149c1e1ba1d78e778aff9edfc72d920eae
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/eventBuffer_rtl.vhd
@@ -0,0 +1,167 @@
+--=============================================================================
+--! @file eventBuffer_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+--! @brief Stores input words (64bits) for readout over IPBus. 
+--! Uses a FIFO ( 64bits at input, 32 bits at output )
+--
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:24:50 11/13/12
+--
+--! @version v0.1
+--
+--! @details
+--! \n\nIPBus Address map:
+--! \li 0x0000 - FIFO data
+--! \li 0x0001 - FIFO fill level
+--! \li 0x0010 - FIFO status/control: (Writing Bit-0 resets pointers, Reading bit-1 returns "prog_full" flag)
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--------------------------------------------------------------------------------
+
+ENTITY eventBuffer IS
+    GENERIC( 
+        g_EVENT_DATA_WIDTH    : positive := 64;
+        g_IPBUS_WIDTH         : positive := 32;
+        g_READ_COUNTER_WIDTH  : positive := 14
+    );
+    PORT( 
+        clk_4x_logic_i    : IN     std_logic;
+        data_strobe_i     : IN     std_logic;                                         -- Indicates data to transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic;
+        ipbus_i           : IN     ipb_wbus;
+        ipbus_reset_i     : IN     std_logic;
+        strobe_4x_logic_i : IN     std_logic;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o			: OUT 	std_logic;														--! rst signal to first level fifos
+        buffer_full_o     : OUT    std_logic;                                         --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus;
+        logic_reset_i     : IN     std_logic                                          -- reset buffers when high. Synch withclk_4x_logic
+    );
+
+-- Declarations
+
+END ENTITY eventBuffer ;
+
+--
+ARCHITECTURE rtl OF eventBuffer IS
+    signal s_rd_data_count    : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
+    signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0');  -- read-counter - 2*write_count
+    signal s_write_strobe    : std_logic := '0';
+    signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0';                             -- ! Take high to reset FIFO pointers.
+    signal s_fifo_prog_full : std_logic := '0';                       -- ! Controlled by programmable-full flag of FIFO core
+    signal s_fifo_rd_en : std_logic := '0';                           -- ! Take high to clock data out of FIFO
+    signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);  -- ! Output from FIFO ( fall-through mode)
+    signal s_fifo_valid : std_logic := '1';                           -- ! High when data in FIFO
+    signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
+    signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0');  -- data registered onto IPBus clock
+    signal s_ack : std_logic := '0';      -- -- IPBus ACK signal
+    COMPONENT tlu_event_fifo
+    PORT (
+        rst : IN STD_LOGIC;
+        wr_clk : IN STD_LOGIC;
+        rd_clk : IN STD_LOGIC;
+        din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+        wr_en : IN STD_LOGIC;
+        rd_en : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        full : OUT STD_LOGIC;
+        almost_full : OUT STD_LOGIC;
+        empty : OUT STD_LOGIC;
+        almost_empty : OUT STD_LOGIC;
+        rd_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
+        prog_full : OUT STD_LOGIC
+    );
+    END COMPONENT;
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus IO
+  -----------------------------------------------------------------------------
+
+  --! Generate IPBus ACK 
+    ipbus_ack: process(ipbus_clk_i)
+    begin
+    if rising_edge(ipbus_clk_i) then
+        s_ack <= ipbus_i.ipb_strobe and not s_ack;
+    end if;
+    end process ipbus_ack;
+    ipbus_o.ipb_ack <= s_ack;
+    
+    --! Generate FIFO read enable
+    --! take high for one cycle ( when ipb_strobe goes high but before ACK goes
+    --high to follow it
+    s_fifo_rd_en  <= '1' when
+        ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" and s_ack = '0'
+        else '0';
+    ipbus_o.ipb_err <= '0';
+
+    --! Multiplex output data.
+    with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
+        s_fifo_dout          when "00",
+        s_fifo_fill_level    when "01",
+        s_fifo_status_ipb	 when "10",
+        (others => '1')      when others;
+
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipbus_write
+    if rising_edge(ipbus_clk_i) then
+        s_rst_fifo_ipb <= '0';
+        if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
+            s_rst_fifo_ipb <= '1';
+        end if;
+        -- Register data onto IPBus clock domain to ease timing closure.
+        s_fifo_status_ipb <=  X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+        s_fifo_fill_level <= X"0000" & "00" & s_rd_data_count; 
+    end if;
+    end process ipbus_write;
+  
+    rst_fifo_o <= s_rst_fifo_ipb;
+    s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
+  
+  -----------------------------------------------------------------------------
+  -- FIFO and fill-level calculation
+  -----------------------------------------------------------------------------
+  
+  -- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
+  --event_fifo : entity work.tlu_event_fifo
+    event_fifo : tlu_event_fifo
+    PORT MAP (
+        rst => s_rst_fifo,
+        wr_clk => clk_4x_logic_i,
+        rd_clk => ipbus_clk_i,
+        din => event_data_i,
+        wr_en => data_strobe_i,
+        rd_en => s_fifo_rd_en,
+        dout => s_fifo_dout,
+        full => s_fifo_full,
+        almost_full => s_fifo_almost_full,
+        empty => s_fifo_empty,
+        almost_empty => s_fifo_almost_empty,
+        rd_data_count => s_rd_data_count,
+        prog_full => s_fifo_prog_full
+    );
+    buffer_full_o <= s_fifo_prog_full;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/eventFormatter_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/eventFormatter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c33279ab6feae6a81fe6bd07ef068ec4c9dfc23e
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/eventFormatter_rtl.vhd
@@ -0,0 +1,385 @@
+--=============================================================================
+--! @file eventFormatter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.fmcTLU.all;
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Takes the data delivered on each trigger and turns it into 64-bit
+--!        words to push into event buffer
+--! 
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:10:35 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBus address:
+--! \n (Decodes 3 bits)
+--! \li 000 - read/write enable data recording.
+--! \li 001 - write = reset timestamp,
+--! \li 010 - read = current timestamp (low  32-bits)
+--! \li 011 - read = current timestamp (high 16-bits)
+--!
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
+--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
+--!               doesn't like having an if that can take an array out of bounds.
+--! 26/Sept/14 DGC Hacked out shutter etc. Can't figure out bug.
+--!-----------------------------------------------------------------------------
+--! @todo Add more input data: \n
+--! a) shutter signals. One per DUT. ?? \n
+--! b) input levels ( for recording edge data ). Record rising and falling edges\n
+--! c) veto levels. One per DUT. Record rising and falling edges.\n
+--! \n
+--! Add backpressure output if short FIFOs fill up? But many inputs won't
+--! respond - e.g. scintillator inputs. This data will be lost....
+--! some ports are redundant - e.g. trigger counter, others confusingly
+--! labelled. Sort this out..
+--------------------------------------------------------------------------------
+
+
+ENTITY eventFormatter IS
+   GENERIC( 
+      g_EVENT_DATA_WIDTH   : positive := 64;
+      g_IPBUS_WIDTH        : positive := 32;
+      g_COUNTER_TRIG_WIDTH : positive := 32;
+      g_COUNTER_WIDTH      : positive := 12;
+      g_EVTTYPE_WIDTH      : positive := 4; --! Width of the event type word
+      --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+      g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+      g_NUM_TRIG_INPUTS    : positive := 6      --! Number of trigger inputs
+   );
+   PORT( 
+      clk_4x_logic_i         : IN     std_logic;                                           --! Rising edge active
+      ipbus_clk_i            : IN     std_logic;
+      logic_strobe_i         : IN     std_logic;                                           --! Pulses high once every 4 cycles of clk_4x_logic
+      logic_reset_i          : IN     std_logic;                                           --! goes high to reset counters. Synchronous with clk_4x_logic
+      rst_fifo_i             : IN     std_logic;                                           --! Goes high to reset FIFOs
+      buffer_full_i          : IN     std_logic;                                           --! Goes high when output fifo full
+      trigger_i              : IN     std_logic;                                           --! goes high to load trigger data. One cycle of clk_4x_logic
+      trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times ( w.r.t. logic_strobe)
+      trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);     --! high for each input that "fired"
+      trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);  --! Trigger count
+      shutter_i              : IN     std_logic;
+      shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      spill_i                : IN     std_logic;
+      spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when rising edge
+      edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when falling edge
+      edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      ipbus_i                : IN     ipb_wbus;
+      ipbus_o                : OUT    ipb_rbus;
+      data_strobe_o          : OUT    std_logic;                                           --! goes high when data ready to load into event buffer
+      event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+      reset_timestamp_i      : IN     std_logic;                                           --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+      reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+   );
+
+-- Declarations
+
+END eventFormatter ;
+
+--
+ARCHITECTURE rtl OF eventFormatter IS
+
+  
+  constant c_NUM_INPUT_TYPES     : positive := 3+g_NUM_EDGE_INPUTS;               -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
+  
+--  type t_fifo_io is array(natural range <>) of std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0);
+-- type t_evttype is array(natural range <>) of std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0);
+--  type t_var is array(natural range <>) of std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
+  -- Input types:
+  -- 0 - Trigger
+  -- 1 - Shutter
+  -- 2 - Edge signal
+  -- 3 - Spill
+  
+  --! delayed strobes
+  signal s_event_strobe , s_event_strobe_d1 ,s_event_strobe_d2 ,s_event_strobe_d3 , s_event_strobe_d3_opt : std_logic := '0';
+  signal shutter_i_d1, shutter_i_d2, edge_i_d1, edge_i_d2, spill_i_d1, spill_i_d2 : std_logic := '0';
+  
+--  signal s_evttype : t_evttype(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>(others=>'0'));   -- Event type
+  signal s_evttype : std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0) := ( others => '0');
+  -- 0000 trigger internal
+  -- 0001 trigger external
+  -- 0010 shutter falling
+  -- 0011 shutter rising
+  -- 0100 edge falling
+  -- 0101 edge rising
+  -- 0111 spill on
+  -- 0110 spill off
+  
+  signal s_var        : std_logic_vector(g_COUNTER_WIDTH-1 downto 0) := (others => '0');
+    
+  signal s_data_o        : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);         -- Multiplexed data from FIFOs
+  
+  constant c_COARSE_TIMESTAMP_WIDTH : positive := 48;  -- ! Number of bits in 40MHz timestamp
+  signal s_coarse_timestamp : std_logic_vector(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0');  -- 40MHz timestamp.
+  signal s_coarse_timestamp_ipbus : ipb_reg_v(1 downto 0) := ( others => (others => '0')); --! 40MHz timestamp on IPB clock domain.
+
+--  signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- increment after each post-veto trigger.
+
+  signal s_word0 , s_word1, s_word2 			: std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_p1  : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal trigger_times_d1							: t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0')); 
+
+  signal s_reset_timestamp_4x, s_reset_timestamp_4x_ipbus , s_reset_timestamp_4x_external , s_reset_timestamp_4x_external_p1 , s_reset_timestamp_4x_external_p2 : std_logic := '0'; --! Single pulse on 4x domain
+  signal s_reset_timestamp_ipbus : std_logic := '0'; --! Single pulse on IPBus clock domain
+  
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
+  signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
+  signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
+  signal s_enable_spill   : std_logic := '1'; -- Enable spill record
+  signal s_enable_edges   : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
+
+  signal s_rst_fifo_d1 , s_rst_fifo_d2 , s_rst_fifo_clk4x  : std_logic := '0';
+  signal s_buffer_full_d1 , s_buffer_full_d2 , s_buffer_full_clk4x  : std_logic := '0';
+  signal s_trigger : std_logic := '0';  -- pulses on risng edge of triger in
+
+  signal s_captured_trigger_times :  t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times,captured when trigger
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus write
+  -----------------------------------------------------------------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_reset_timestamp_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+         case ipbus_i.ipb_addr(2 downto 0) is
+           when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
+           when "001" => s_reset_timestamp_ipbus <= '1';
+           when others => null;
+         end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+  
+
+  -----------------------------------------------------------------------------
+  -- IPBUS read
+  -----------------------------------------------------------------------------
+  with ipbus_i.ipb_addr(2 downto 0) select
+    ipbus_o.ipb_rdata <=
+      s_enable_record_ipb                     when "000",
+      s_coarse_timestamp_ipbus(0)              when "010",  
+      s_coarse_timestamp_ipbus(1)             when "011",  
+      (others => '1')                         when others;
+
+  cmp_timestampDomainCross : entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => 2 )
+    port map (
+      clk_input_i  => clk_4x_logic_i,
+      data_i       => ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) ) ,
+      data_o       => s_coarse_timestamp_ipbus, 
+      clk_output_i => ipbus_clk_i
+      );
+
+  -- Move reset timestamp pulse onto clk_4x_logic
+  cmp_resetTimestampDomainCross: entity work.pulseClockDomainCrossing
+    port map (
+      clk_input_i  => ipbus_clk_i,
+      pulse_i      => s_reset_timestamp_ipbus,
+      clk_output_i => clk_4x_logic_i, 
+      pulse_o      => s_reset_timestamp_4x_ipbus
+    );
+
+  -- Combine reset timestamp from IPBus and external source
+  -- purpose: combines resets from IPBus and external source onto clk_4x_logic_i
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: s_reset_timestamp_4x
+  p_combine_reset_timestamps: process (clk_4x_logic_i) is
+  begin  -- process p_combine_reset_timestamps
+    if rising_edge(clk_4x_logic_i) then
+      s_reset_timestamp_4x_external_p2 <= reset_timestamp_i;
+      s_reset_timestamp_4x_external_p1 <= s_reset_timestamp_4x_external_p2 ;
+      s_reset_timestamp_4x_external    <= s_reset_timestamp_4x_external_p1 ;
+      s_reset_timestamp_4x <= s_reset_timestamp_4x_external or s_reset_timestamp_4x_ipbus;
+    end if;
+  end process p_combine_reset_timestamps;
+  
+  reset_timestamp_o <= s_reset_timestamp_4x;
+  
+  -- Change control signals from IPBus clock domain on to clk_4x_logic
+  -- CHANGE ME - use synchronize registers instead.
+  p_signals_clk_domain: process (clk_4x_logic_i )
+  begin  -- process p_internal_triggers
+    if rising_edge(clk_4x_logic_i) then
+      s_enable_record  <= s_enable_record_ipb;
+		
+      s_enable_trigger <= s_enable_record(0);
+      s_enable_shutter <= s_enable_record(1);
+      s_enable_spill <= s_enable_record(2);
+      s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
+
+      -- move  "reset fifo" and "buffer full"  signals onto clock4x domain
+      s_rst_fifo_d1 <= rst_fifo_i;
+      s_rst_fifo_d2 <= s_rst_fifo_d1;
+      s_rst_fifo_clk4x <= s_rst_fifo_d2 ;
+      s_buffer_full_d1 <= buffer_full_i;
+      s_buffer_full_d2 <= s_buffer_full_d1;
+      s_buffer_full_clk4x <= s_buffer_full_d2;  
+      
+    end if;
+  end process p_signals_clk_domain;
+
+  cmp_triggerEdgeDetect: entity work.single_pulse
+    port map (
+      level => trigger_i,
+      clk => clk_4x_logic_i,
+      pulse => s_trigger
+      );
+  
+  -- purpose: generate delayed strobes and write enable flags to the FIFOs
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , s_FIFO_rd
+  -- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
+  p_ff_rst: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then      
+      if s_rst_fifo_clk4x = '1' then
+        s_event_strobe_d1 <= '0';
+        s_event_strobe_d2 <= '0';
+        s_event_strobe_d3 <= '0';
+		
+      else
+        -- set s_event_strobe high if trigger_i is high and pipeline is empty
+        -- ( i.e. all event_strobe are zero)
+
+        s_event_strobe_d1 <= s_trigger and s_enable_trigger and not buffer_full_i and
+                             (not s_event_strobe_d1 ) and (not s_event_strobe_d2 ) and (not s_event_strobe_d3 );
+        s_event_strobe_d2 <= s_event_strobe_d1;
+        s_event_strobe_d3 <= s_event_strobe_d2;
+		
+      end if;
+    end if;
+  end process p_ff_rst;
+  
+  p_ff: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then
+
+		trigger_times_d1 <= trigger_times_i;
+
+        s_word0 <= s_word0_p1;
+		s_word0_d1 <= s_word0;
+		s_word1_d1 <= s_word1;
+		s_word1_d2 <= s_word1_d1;
+		s_word2_d1 <= s_word2;
+		s_word2_d2 <= s_word2_d1;
+		s_word2_d3 <= s_word2_d2;
+		
+	end if;
+  end process;
+	
+  -- If there are more than 4 trigger inputs we need to fill a second word.
+  -- .. do this by having an optional strobe.
+  -- If 4 or fewer trigger inputs, just leave s_event_strobe_d3_opt at zero..
+  gen_strobe_d3: if (g_NUM_TRIG_INPUTS > 4) generate
+    s_event_strobe_d3_opt <= s_event_strobe_d3;
+  end generate;
+
+-------------------------------------------------------------------------------
+-- Trigger event formater
+-------------------------------------------------------------------------------
+  s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 else "0001";
+
+  --s_var <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));
+  s_var <= std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS)) & trigger_inputs_fired_i; -- Pad with zeroes on the left.
+
+  s_word0_p1 <= s_evttype & s_var & s_coarse_timestamp;
+  
+  s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
+             "000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
+             trigger_cnt_i;
+				 
+	
+  -- Different number of trigger inputs require packing into s_word2 in
+  -- different ways.
+  -- Do this in a generate since g_NUM_TRIG_INPUTS is static and
+  -- Questasim doesn't like refering to indices outside declared range.
+    gen_word2_init: if (g_NUM_TRIG_INPUTS <= 4) generate
+       s_word2 <= (others=>'0');
+    end generate;
+  --s_word2 <= (others=>'0'); -- Set all bits to zero
+  -- then override with the following assignments....
+    gen_word2: for v_trigInput in 4 to g_NUM_TRIG_INPUTS-1 generate
+        s_word2( (((11-v_trigInput)*8)+c_NUM_TIME_BITS-1) downto ((11-v_trigInput)*8) ) <= trigger_times_i(v_trigInput);
+    end generate;
+  
+      
+  --! Could also output data on trigger_i , but let's use the delayed signals. \n
+  --! The counters are one cycle delayed from the signal generation
+  p_fifo_i : process (clk_4x_logic_i)
+  begin  
+    if rising_edge(clk_4x_logic_i) then
+      data_strobe_o <= s_event_strobe_d1 or s_event_strobe_d2 or s_event_strobe_d3_opt;
+      
+      if s_event_strobe_d1 = '1' then
+        event_data_o <= s_word0_d1;
+      elsif s_event_strobe_d2 = '1' then
+        event_data_o <= s_word1_d2;
+      elsif s_event_strobe_d3_opt = '1' then
+        event_data_o <= s_word2_d3;
+      else
+        event_data_o <= (others=>'0');
+      end if;
+    end if;
+  end process;
+		
+
+  cmp_timeStampCounter: entity work.counterWithReset
+    generic map (
+      g_COUNTER_WIDTH => s_coarse_timestamp'length)
+    port map (
+      clock_i  => clk_4x_logic_i,
+      reset_i  => s_reset_timestamp_4x or logic_reset_i,
+      enable_i => logic_strobe_i,
+      result_o => s_coarse_timestamp);
+    
+ 
+  -- Generate data in format decided at DESY. Put out two strobes for the
+  -- two 64 bit words.
+  -- get trigger inputs to also generate a global time-stamp ??
+  -- add trigger_inputs_active_i array (to indicate which triggers fired)
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg.vhd b/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb6b10104903070a5365064dee8d9d822d64cf42
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg.vhd
@@ -0,0 +1,27 @@
+--=============================================================================
+--! @file fmcTLU_pkg.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:44:31 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE fmcTLU IS
+  
+  constant c_NUM_TIME_BITS : natural := 5;
+  constant c_NUM_TRIG_INPUTS : natural := 4;
+  constant c_EVENT_DATA_WIDTH : natural := 32;
+  constant c_DATA_WIDTH : natural := 32;
+  
+  subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
+  --type    t_triggerTimeArray is array(natural range <>) of t_triggerTime;
+  type    t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+  type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
+  
+END fmcTLU;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg_body.vhd b/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg_body.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9437776d393daa1b6e790f3d5470fb09344259bc
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/fmcTLU_pkg_body.vhd
@@ -0,0 +1,13 @@
+--=============================================================================
+--! @file fmcTLU_pkg_body.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:45:08 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+PACKAGE BODY fmcTLU IS
+END fmcTLU;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/handshakes_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/handshakes_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ab893a2a99708784f934579adc8439a2593fe067
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/handshakes_rtl.vhd
@@ -0,0 +1,248 @@
+--=============================================================================
+--! @file handshakes_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
+--
+--! @brief Handshakes between TLU and DUTs. \n
+--
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 12:08:30 25/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY handshakes IS
+   GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i    			: IN     std_logic;
+		Trigger_i			: IN 		std_logic;
+      ipbus_clk_i       : IN     std_logic;
+      ipbus_i           : IN     ipb_wbus;
+      ipbus_reset_i     : IN     std_logic;
+      ipbus_o           : OUT    ipb_rbus;
+      logic_reset_i     : IN     std_logic;    
+		Busy_i				: IN		std_logic;
+		AIDAhandshake_o	: OUT		std_logic;		-- running an AIDA handshake or the old EUDET handshake
+		Trigger_o			: OUT 	std_logic;
+		rst_or_clk_o		: OUT 	std_logic		-- CONT in schematics
+   );
+
+-- Declarations
+
+END ENTITY handshakes ;
+
+--
+ARCHITECTURE rtl OF handshakes IS
+
+	signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+	signal s_Shutter, s_T0sync : std_logic;
+	signal s_Trigger, s_TrigAux : std_logic := '0';
+	signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
+	
+	signal TPx3_T0syncLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004";   	--! T0-sync length
+	signal TPx3_Start_T0sync 	: std_logic;   																--! Flag to start the T0-sync signal
+
+	signal s_Veto 			: std_logic := '0';
+	signal s_WU				: std_logic := '0';
+	signal s_NMaxPulses 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_SuDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_PulseLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_IpDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_RearmTime 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
+	signal s_PulseDelay 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_MaxPulses	: std_logic;
+	signal s_pulse			: std_logic;
+	
+	constant c_N_CTRL : positive := 13;
+	constant c_N_STAT : positive := 13;
+	signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+	signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_i);
+		
+	-----------------------------------------------------------------------------
+	-- Logic not ready to use
+	-----------------------------------------------------------------------------
+		
+	--Map the control registers
+	s_handshakeEnabled <= s_sync_control_from_ipbus(0);
+	
+	s_status_to_ipbus(0) <= s_handshakeEnabled;
+
+	
+	-- No handshake registers
+	s_NMaxPulses <= s_sync_control_from_ipbus(5);
+	s_SuDTime <= s_sync_control_from_ipbus(6);
+	s_PulseLen <= s_sync_control_from_ipbus(7);
+	s_IpDTime <= s_sync_control_from_ipbus(8);
+	s_RearmTime <= s_sync_control_from_ipbus(9);
+	s_PulseDelay <= s_sync_control_from_ipbus(10);
+	s_Veto <= s_sync_control_from_ipbus(11)(0);
+	s_WU <= s_sync_control_from_ipbus(11)(1);
+	
+	s_status_to_ipbus(5) <= s_NMaxPulses;
+	s_status_to_ipbus(6) <= s_SuDTime;
+	s_status_to_ipbus(7) <= s_PulseLen;
+	s_status_to_ipbus(8) <= s_IpDTime;
+	s_status_to_ipbus(9) <= s_RearmTime;
+	s_status_to_ipbus(10) <= s_PulseDelay;
+	s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
+	s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
+	
+	-- TPx3 registers
+	TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
+	TPx3_T0syncLen 	<= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
+								s_sync_control_from_ipbus(2);
+  
+	s_status_to_ipbus(1) <= x"0000000" & "000" & TPx3_Start_T0sync;
+	s_status_to_ipbus(2) <= TPx3_T0syncLen;
+  
+  
+	-----------------------------------------------------------------------------
+	-- Synchronization - Rewrite!!!
+	-----------------------------------------------------------------------------
+	p_trigger : process(Trigger_i, s_Trigger)
+	begin
+		if Trigger_i = '1' then
+			s_TrigAux <= '1';
+		elsif s_Trigger = '1' then
+			s_TrigAux <= '0';
+		end if;
+	end process p_trigger;
+	
+	p_sync: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Trigger <= s_TrigAux;
+			
+			s_Busy_d1 <= Busy_i;
+			s_Busy_d2 <= s_Busy_d1;
+			s_Busy_d3 <= s_Busy_d2;
+			s_Busy <= s_Busy_d2;
+		end if;
+  end process p_sync;
+	
+	-----------------------------------------------------------------------------
+	-- I/O
+	-----------------------------------------------------------------------------
+	Trigger_o <= 	s_Trigger when s_handshakeEnabled(1 downto 0) = "00"  and s_Busy = '0' else
+						s_pulse when s_handshakeEnabled(1 downto 0) = "01" else							-- No handshake
+						s_Shutter when s_handshakeEnabled(1 downto 0) = "10" else						-- TPx3 handshake
+						'0';
+	rst_or_clk_o <= 	s_T0sync when s_handshakeEnabled(1 downto 0) = "10" else
+							'0';
+	
+	AIDAhandshake_o <= not s_handshakeEnabled(3); 	-- s_handshakeEnabled = x"00001000" => EUDET handshake.
+																	-- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
+	
+	-- No Handshake (GPP)
+	No_handshake:  entity work.GPP
+	GENERIC MAP( 
+		g_IPBUS_WIDTH => g_IPBUS_WIDTH)
+	PORT MAP( 
+		clk_i       		=> clk_i,
+		Enable_i          => not (s_Busy or s_Veto),
+      Reset_i           => logic_reset_i,
+      RstPulsCnt_i     	=> '0',
+      Trigger_i         => s_Trigger,
+      NMaxPulses_i      => s_NMaxPulses,
+      SuDTime_i         => s_SuDTime,
+      PulsLen_i     		=> s_PulseLen,
+      IpDTime_i         => s_IpDTime,
+		RearmTime_i       => s_RearmTime,
+      Force_PullDown_i  => s_Busy or s_Veto,
+      WU_i              => s_WU,
+      PulseDelay_i      => s_PulseDelay,
+		event_number_o    => open,
+      MaxPulses_o       => s_MaxPulses,
+      Pulse_o           => s_pulse,
+      Pulse_d_o         => open);
+		
+	-- TPx3 Handshake
+	TPx3_logic: entity work.TPx3Logic
+   PORT MAP( 
+      clk_i					=> clk_i,
+		Start_T0sync_i		=> TPx3_Start_T0sync,
+		T0syncLen_i			=> TPx3_T0syncLen,
+      logic_reset_i     => logic_reset_i,
+      Busy_i				=> s_Busy,
+		Veto_i				=> s_Veto,
+		Shutter_o			=> s_Shutter,
+		T0sync_o 			=>	s_T0sync
+   );
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/ipbus_decode_TLUaddrmap.vhd b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_decode_TLUaddrmap.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0daf9b398e3268ed077f270ef991993c6ddc811
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_decode_TLUaddrmap.vhd
@@ -0,0 +1,72 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+-- 
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+-- 
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_TLUaddrmap is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_TLUaddrmap(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Mon Feb 19 12:09:48 2018 
+  constant N_SLV_VERSION: integer := 0;
+  constant N_SLV_DUTINTERFACES: integer := 1;
+  constant N_SLV_SHUTTER: integer := 2;
+  constant N_SLV_I2C_MASTER: integer := 3;
+  constant N_SLV_EVENTBUFFER: integer := 4;
+  constant N_SLV_EVENT_FORMATTER: integer := 5;
+  constant N_SLV_TRIGGERINPUTS: integer := 6;
+  constant N_SLV_TRIGGERLOGIC: integer := 7;
+  constant N_SLV_LOGIC_CLOCKS: integer := 8;
+  constant N_SLAVES: integer := 9;
+-- END automatically generated VHDL
+
+    
+end ipbus_decode_TLUaddrmap;
+
+package body ipbus_decode_TLUaddrmap is
+
+  function ipbus_sel_TLUaddrmap(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Mon Feb 19 12:09:48 2018 
+    if    std_match(addr, "----------------0000------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_VERSION, IPBUS_SEL_WIDTH)); -- version / base 0x00000001 / mask 0x0000f000
+    elsif std_match(addr, "----------------0001------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_DUTINTERFACES, IPBUS_SEL_WIDTH)); -- DUTInterfaces / base 0x00001000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0010------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_SHUTTER, IPBUS_SEL_WIDTH)); -- Shutter / base 0x00002000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0011------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_MASTER, IPBUS_SEL_WIDTH)); -- i2c_master / base 0x00003000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0100------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_EVENTBUFFER, IPBUS_SEL_WIDTH)); -- eventBuffer / base 0x00004000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0101------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_EVENT_FORMATTER, IPBUS_SEL_WIDTH)); -- Event_Formatter / base 0x00005000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0110------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_TRIGGERINPUTS, IPBUS_SEL_WIDTH)); -- triggerInputs / base 0x00006000 / mask 0x0000f000
+    elsif std_match(addr, "----------------0111------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_TRIGGERLOGIC, IPBUS_SEL_WIDTH)); -- triggerLogic / base 0x00007000 / mask 0x0000f000
+    elsif std_match(addr, "----------------1000------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_LOGIC_CLOCKS, IPBUS_SEL_WIDTH)); -- logic_clocks / base 0x00008000 / mask 0x0000f000
+-- END automatically generated VHDL
+
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_TLUaddrmap;
+
+end ipbus_decode_TLUaddrmap;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/ipbus_example.vhd b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cc5f12c11b018fd6cbf7c022792e71ff24b06da
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_example.vhd
@@ -0,0 +1,174 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_example is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_example;
+
+architecture rtl of ipbus_example is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+       COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+
+	slave4: entity work.ipbus_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_RAM),
+			ipbus_out => ipbr(N_SLV_RAM)
+		);
+	
+-- Slave 3: peephole RAM
+
+	slave5: entity work.ipbus_peephole_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_PRAM),
+			ipbus_out => ipbr(N_SLV_PRAM)
+		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/ipbus_fabric_sel.vhd b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_fabric_sel.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..86d2fa7ad9b120d636c28ad9fe3de5a35eaa0d51
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_fabric_sel.vhd
@@ -0,0 +1,61 @@
+-- The ipbus bus fabric, address select logic, data multiplexers
+--
+-- This version selects the addressed slave depending on the state
+-- of incoming control lines
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+
+entity ipbus_fabric_sel is
+  generic(
+    NSLV: positive;
+    STROBE_GAP: boolean := false;
+    SEL_WIDTH: positive
+   );
+  port(
+  	sel: in std_logic_vector(SEL_WIDTH - 1 downto 0);
+    ipb_in: in ipb_wbus;
+    ipb_out: out ipb_rbus;
+    ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0);
+    ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL)
+   );
+
+end ipbus_fabric_sel;
+
+architecture rtl of ipbus_fabric_sel is
+
+	signal sel_i: integer range 0 to NSLV := 0;
+	signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
+	signal qstrobe: std_logic;
+
+begin
+
+	sel_i <= to_integer(unsigned(sel));
+
+	ored_ack(NSLV) <= '0';
+	ored_err(NSLV) <= '0';
+	
+	qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
+	 ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
+
+	busgen: for i in NSLV-1 downto 0 generate
+	begin
+
+		ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
+		ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
+		ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0';
+		ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
+		ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
+		ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;		
+
+	end generate;
+
+  ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0');
+  ipb_out.ipb_ack <= ored_ack(0);
+  ipb_out.ipb_err <= ored_err(0);
+  
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/ipbus_slaves.vhd b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_slaves.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0ee08ffa82d15f637cdba389211c81b5a7c47c7
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/ipbus_slaves.vhd
@@ -0,0 +1,170 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_slaves is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_slaves;
+
+architecture rtl of ipbus_slaves is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+    COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+--	slave4: entity work.ipbus_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_RAM),
+--			ipbus_out => ipbr(N_SLV_RAM)
+--		);
+	
+-- Slave 3: peephole RAM
+--	slave5: entity work.ipbus_peephole_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_PRAM),
+--			ipbus_out => ipbr(N_SLV_PRAM)
+--		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/led_stretcher.vhd b/AIDA_tlu/components/tlu/firmware/hdl/led_stretcher.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c8af6c6890d6b0e50669a1527c6f09ad18ae46b4
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/led_stretcher.vhd
@@ -0,0 +1,74 @@
+-- stretcher
+--
+-- Stretches a single clock pulse so it's visible on an LED
+--
+-- Dave Newbold, January 2013
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity led_stretcher is
+	generic(
+		WIDTH: positive := 1
+	);
+	port(
+		clk: in std_logic; -- Assumed to be 125MHz ipbus clock
+		d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected)
+		q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse
+	);
+
+end led_stretcher;
+
+architecture rtl of led_stretcher is
+
+	signal d17, d17_d: std_logic;
+	
+begin
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => clk,
+			d17 => d17
+		);
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			d17_d <= d17;
+		end if;
+	end process;
+	
+	lgen: for i in WIDTH - 1 downto 0 generate
+	
+		signal s, sd, e, e_d, sl: std_logic;
+		signal scnt: unsigned(6 downto 0);
+	
+	begin
+	
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				s <= d(i); -- Possible clock domain crossing from slower clock (sync not important)
+				sd <= s;
+				e <= (e or (s and not sd)) and not e_d;
+				if d17 = '1' and d17_d = '0' then
+					e_d <= e;
+					if e = '1' then
+						scnt <= "0000001";
+					elsif sl = '0' then
+						scnt <= scnt + 1;
+					end if;					
+				end if;
+			end if;
+		end process;
+
+		sl <= '1' when scnt = "0000000" else '0';
+		
+		q(i) <= not sl;
+		
+	end generate;
+	
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..631007a5684f7176cbd027035ecfa6235abfcc21
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd
@@ -0,0 +1,344 @@
+--=============================================================================
+--! @file logic_clocks_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
+-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
+-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________40.000____________0.010
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock.
+--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock.
+--! Can also output clock to external clock pins.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 14:20:26 11/14/12
+--
+--! @version v0.1
+--
+--! @details
+--! \br <b> IPBus Address map:</b>
+--! \br (decode 2 bits)
+--! \li 0x00000000 - control/status register:
+--! \li             bit-0 - PLL locked ( 1 = locked )
+--! \li              bit-1 - buff-PLL locked ( 1 = locked )
+--! \li             bit-2 - use xtal for logic ( 1 = xtal , 0= external)
+--! \li             bit-3 - clock connector is an input ( 1=input , 0 = output)
+--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
+--!
+--!
+ENTITY logic_clocks IS
+    GENERIC( 
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT( 
+        ipbus_clk_i           : IN     std_logic;
+        ipbus_i               : IN     ipb_wbus;
+        ipbus_reset_i         : IN     std_logic;
+        Reset_i               : IN     std_logic;
+        clk_logic_xtal_i      : IN     std_logic;   --! 40MHz clock derived from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic;   --! 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic;   --! 160MHz clock
+        ipbus_o               : OUT    ipb_rbus;
+        strobe_8x_logic_o    : OUT    std_logic;   --! strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic;   --! one pulse every 4 cycles of clk_4x
+        DUT_clk_o             : OUT    std_logic;   --! 40MHz to DUTs
+        logic_clocks_locked_o : OUT    std_logic;   --! Goes high if clocks locked.
+        logic_reset_o         : OUT    std_logic    --! Goes high to reset counters etc. Sync with clk_4x_logic
+    );
+
+-- Declarations
+END ENTITY logic_clocks ;
+
+--
+ARCHITECTURE rtl OF logic_clocks IS
+    signal s_clk40 , s_clk40_internal : std_logic;
+    signal s_clk160 ,s_clk160_internal : std_logic;
+    signal ryanclock : std_logic;
+    signal s_clk320 , s_clk320_internal : std_logic;
+    signal s_clk40_out : std_logic;       -- Clock generated by DDR register to feed out of chip.
+    signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
+                                                             -- input from ext
+    --  signal s_logic_clk_rst : std_logic := '0';
+    signal s_locked_pll, s_locked_bufpll : std_logic;
+    
+    signal s_clk : std_logic;
+    signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
+    signal s_extclk, s_extclkG : std_logic;
+    -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic  : std_logic;
+    signal s_clkfbout_buf , s_clkfbout : std_logic;
+    
+    signal s_strobe_generator  : std_logic_vector(3 downto 0) := "1000";  -- ! Store state of ring buffer to generate strobe
+    signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100";  --! Stores state of 40MHz "clock"
+    --signal s_strobe_generator  : std_logic_vector(15 downto 0) := "1111000000000000";  -- ! Store state of ring buffer to generate strobe
+    --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000";  --! Stores state of 40MHz "clock"
+    signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring
+    signal s_strobe_fb : std_logic := '0';
+    
+    signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';  
+                                        -- ! Reset signal in IPBus clock domain
+    signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';  
+                                        -- ! reset signal clocked onto logic-clock domain.
+    attribute SHREG_EXTRACT: string;
+    attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre
+    attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg
+    signal s_ipbus_ack : std_logic := '0';
+    signal s_reset_pll : std_logic := '0';
+    
+    
+    -- ! Global Reset signal
+    signal  s_extclk_internal  : std_logic := '0';
+    signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range );   --! Hold status of clocks
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus write
+    -----------------------------------------------------------------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_logic_reset_ipb <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+            when "00" =>
+             s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
+             
+            when "01" =>
+             s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
+            when others => null;
+            end case;
+       end if;
+
+        -- register reset signal to aid timing.
+        s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+        -- register the clock status signals onto IPBus domain.
+        --s_clock_status_ipb <=  x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+        s_clock_status_ipb <=  x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status. 
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+    -----------------------------------------------------------------------------
+    -- IPBUS read
+    -----------------------------------------------------------------------------
+    with ipbus_i.ipb_addr(1 downto 0) select
+    ipbus_o.ipb_rdata <=
+        s_clock_status_ipb  when "00",
+        (others => '1')      when others;
+
+
+    -----------------------------------------------------------------------------
+    -- Generate reset signal on logic-clock domain
+    -- This relies on the IPBus clock being much slower than the 4x logic clock.
+    -----------------------------------------------------------------------------
+    p_reset: process (s_clk160_internal)
+    begin  -- process p_reset
+    if rising_edge(s_clk160_internal) then
+        s_logic_reset_d1 <= s_logic_reset_ipb_d1;
+        s_logic_reset_d2 <= s_logic_reset_d1;
+        s_logic_reset_d3 <= s_logic_reset_d2;
+        s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3); 
+        s_logic_reset <= s_logic_reset_d4;
+    end if;
+    end process p_reset;
+    
+    logic_reset_o <= s_logic_reset;
+    logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+
+    -- Use Generate, since can't figure out how BUFGMUX works    
+    --  gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
+    --    s_DUT_Clk <= s_extclkG; -- Hard wire for now.    
+    --  end generate gen_extclk_input;
+    --  gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
+    s_DUT_Clk <= clk_logic_xtal_i; 
+    --  end generate gen_intclk_input;  
+  
+
+  
+    --! Clocking primitive
+    -------------------------------------
+    --! Instantiation of the PLL primitive
+    pll_base_inst : PLL_BASE
+    generic map
+       (BANDWIDTH            => "OPTIMIZED",
+        --CLK_FEEDBACK         => "CLKOUT0", --"CLKFBOUT",
+        CLK_FEEDBACK         => "CLKFBOUT",
+        COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+        DIVCLK_DIVIDE        => 1,
+        CLKFBOUT_MULT        => 16,
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE       => 2, -- 1-->2 move from 640 to 320
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => 4, -- 4-->8 move from 160 to 80
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKOUT2_DIVIDE       => 16, -- 16--> 32 move from 40 to 20
+        CLKOUT2_PHASE        => 0.000,
+        CLKOUT2_DUTY_CYCLE   => 0.500,
+        CLKIN_PERIOD         => 25.000,
+        REF_JITTER           => 0.010)
+    port map(
+        -- Output clocks
+        CLKFBOUT            => s_clkfbout,
+        CLKOUT0             => s_clk320,
+        CLKOUT1             => s_clk160,
+        CLKOUT2             => s_clk40,
+        CLKOUT3             => open,
+        CLKOUT4             => open,
+        CLKOUT5             => open,
+        -- Status and control signals
+        LOCKED              => s_locked_pll,
+        --    RST                 => s_logic_clk_rst,
+        RST                 => s_reset_pll,
+        -- Input clock control
+        --    CLKFBIN             => s_clkfbout_buf,
+        CLKFBIN             => s_clkfbout,
+        CLKIN               => s_DUT_clk);
+        --      CLKIN               => clk_logic_xtal_i);
+
+    s_reset_pll <= Reset_i or s_logic_reset; 
+
+-----------------------------------------------
+--BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR 
+  -- Buffer the 16x clock and generate the ISERDES strobe signal
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK  => s_clk640_internal,          -- 1-bit output: Output I/O clock
+--      LOCK   => s_locked_bufpll,            -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => strobe_16x_logic_O,   -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK   => s_clk160_internal,          -- 1-bit input: BUFG clock input
+--      LOCKED => s_locked_pll,               -- 1-bit input: LOCKED input from PLL
+--      PLLIN  => s_clk640                    -- 1-bit input: Clock input from PLL
+--   );
+
+    BUFG_inst: BUFG
+    port map (
+        I => s_clk320,
+        O => s_clk320_internal    
+    );
+    
+--    BUFR_inst: BUFR
+--    generic map (
+--        BUFR_DIVIDE => "4"
+--    )
+--    port map (
+--        I   => s_clk160_internal,
+--        CE  => '1',
+--        CLR => '0',
+--        O   => ryanclock
+--    );
+    
+--    BUFG_inst2: BUFG
+--    port map (
+--        I => ryanclock,
+--        O => strobe_16x_logic_O    -- Not sure this is actually a strobe... Check
+--    );
+-----------------------------------------------
+
+	clk_8x_logic_o <= s_clk320_internal;
+	DUT_clk_o <= s_DUT_clk;
+
+
+  
+  -- Generate a strobe signal every 4 clocks. 
+  -- Can't use a clock signal as a combinatorial signal. Hence the baroque
+  -- method of generating a strobe. Add a mechanism to restart if the '1' gets
+  -- lost ....
+    
+    ------------------
+    generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out)
+    begin  -- process generate_4x_strobe
+    if rising_edge(s_clk160_internal) then
+        if s_logic_reset = '1' then
+            s_strobe_generator <= "1000";
+            s_logic_clk_generator <= "1100";
+            --s_strobe160 <= "1000000000000000";
+        elsif (s_locked_pll ='1') then
+            s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left      
+            s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left 
+            --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+        end if;
+    end if;
+    end process generate_4x_strobe;
+    strobe_4x_logic_o <=  s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse
+    s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems.
+    ---------------
+    
+    generate_8x_strobe: process (s_clk320_internal)
+    begin
+    if rising_edge(s_clk320_internal) then
+        if s_logic_reset = '1' then
+            s_strobe160 <= "1000000000000000"; 
+            --s_strobe_generator <= "1111000000000000";--
+            --s_logic_clk_generator <= "1111111100000000";--
+        elsif (s_locked_pll ='1') then
+            s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+            --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); --       
+            --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left
+        end if;
+    end if;
+    end process generate_8x_strobe;
+    strobe_8x_logic_O <= s_strobe160(15);
+    --strobe_4x_logic_o <=  s_strobe_generator(15); -- 
+    --s_clk40_out <= s_logic_clk_generator(15); -- 
+        
+
+  -- buffer 160MHz (4x) clock
+  --------------------------------------
+    clk160_o_buf : BUFG
+    port map(
+        O   => s_clk160_internal,
+        I   => s_clk160);
+    
+    clk_4x_logic_o <= s_clk160_internal;
+ 
+--   -- buffer 40MHz (1x) clock
+--  --------------------------------------
+--  clk40_o_buf : BUFG
+--  port map(
+--    O   => s_clk40_internal,
+--    I   => s_clk40);
+
+--  clk_logic_o <= s_clk40_out;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/pulseClockDomainCrossing_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/pulseClockDomainCrossing_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..663cac3b9e4476ee3146730afc6efc5d79225de3
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/pulseClockDomainCrossing_rtl.vhd
@@ -0,0 +1,100 @@
+--=============================================================================
+--! @file pulseClockDomainCrossing_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
+--
+--! @brief Takes a pulse synchronized with one clock and produces a
+--! pulse synchronized to another clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date September/2012
+--
+--! @version v0.1
+--
+--! @details A "ring" of D-type flip-flops is used to transfer a strobe
+--! from the input clock domain to the output clock domain and then back again.
+--! The time taken to transit from input to output is approximately
+--! two clock cycles of clock_output_i .
+--! After an additional two cycles of clk_input_i another pulse can be sent
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulseClockDomainCrossing is
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    pulse_i     : in std_logic;         --! input pulse. Active high
+    clk_output_i: in std_logic;         --! clock for output
+    pulse_o     : out std_logic         --! Single cycle pulse synchronized to clock_output_i
+    );
+
+end pulseClockDomainCrossing;
+
+architecture rtl of pulseClockDomainCrossing is
+
+  signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
+  
+begin  -- rtl
+
+  -- purpose: registers and flip-flop on clk_input_i
+  p_input_clock_logic: process (clk_input_i)
+  begin  
+    if rising_edge(clk_input_i) then
+
+      -- Register signals coming from output clock domain back to the
+      -- input clock domain
+      s_pulse_back_d1 <= s_pulse_out_d2;
+      s_pulse_back_d2 <= s_pulse_back_d1;
+
+      -- JK flip-flop
+      if (s_pulse_back_d2 = '1')  then
+        s_pulse_out <= '0';
+      elsif (pulse_i = '1')  then
+        s_pulse_out <= '1';
+      end if;
+
+    end if;
+  end process p_input_clock_logic;
+
+  -- purpose: registers and flip-flop on clk_output_o
+  p_output_clock_logic: process (clk_output_i)
+  begin  
+    if rising_edge(clk_output_i) then
+
+      -- Register signal on input clock domain onto output clock domain
+      s_pulse_out_d1 <= s_pulse_out;
+      s_pulse_out_d2 <= s_pulse_out_d1;
+
+      s_pulse_out_d3 <= s_pulse_out_d2;
+      s_pulse_out_d4 <= s_pulse_out_d3;
+
+      -- Generate single clock-cycle pulse on pulse_o
+      pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
+
+    end if;
+  end process p_output_clock_logic;
+
+
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/registerCounter_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/registerCounter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de5587cd9ab98905a3da88d0eb2cd5a3c8a279ee
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/registerCounter_rtl.vhd
@@ -0,0 +1,113 @@
+--=============================================================================
+--! @file registerCounter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.registerCounter.rtl
+--
+--! @brief Regularly transfers the input to the output.\n
+--! One clock for input , one clock for output\n
+--! Can't just put entire bus through a couple of register stages,\n
+--! Since this will just swap meta-stability issues for race issues.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 24/Nov/12
+--
+--! @version v0.1
+--
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! We could use gray-scale and put through registers, but this method
+--! should work well enough at the expense of latency.\n
+--! \n
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity registerCounter is
+  
+  generic (
+    g_DATA_WIDTH : positive := 15);     -- ! Width of counter
+
+  port (
+    clk_input_i : in std_logic;         -- ! clock for input
+    data_i      : in std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! data to transfer to output
+    data_o     : out std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! Data now in clk_read_i domain
+    clk_output_i  : in std_logic);        -- ! clock for output
+
+end registerCounter;
+
+architecture rtl of registerCounter is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0');  -- ! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  -- ! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2;  --! Generate a strobe with
+                                                --width one clk_read_i
+  
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5;  --! Generate a strobe
+                                                  --
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/serdes_1_to_n_SDR.vhd b/AIDA_tlu/components/tlu/firmware/hdl/serdes_1_to_n_SDR.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0a119e3cb6fd53afcdc50779d0affc9703b57ce
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/serdes_1_to_n_SDR.vhd
@@ -0,0 +1,235 @@
+------------------------------------------------------------------------------/
+-- Copyright (c) 2009 Xilinx, Inc.
+-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
+------------------------------------------------------------------------------/
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor: Xilinx
+-- \   \   \/    Version: 1.0
+--  \   \        Filename: top_nto1_ddr_diff_rx.vhd
+--  /   /        Date Last Modified:  November 5 2009
+-- /___/   /\    Date Created: June 1 2009
+-- \   \  /  \
+--  \___\/\___\
+-- 
+--Device:   Spartan 6
+--Purpose:    Example differential input receiver for DDR clock and data using 2 x BUFIO2
+--    Serdes factor and number of data lines are set by constants in the code
+--Reference:
+--    
+--Revision History:
+--    Rev 1.0 - First created (nicks)
+--
+------------------------------------------------------------------------------/
+--
+--  Disclaimer: 
+--
+--    This disclaimer is not a license and does not grant any rights to the materials 
+--              distributed herewith. Except as otherwise provided in a valid license issued to you 
+--              by Xilinx, and to the maximum extent permitted by applicable law: 
+--              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+--              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+--              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+--              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+--              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+--              of any kind or nature related to, arising under or in connection with these materials, 
+--              including for any direct, or any indirect, special, incidental, or consequential loss 
+--              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+--              as a result of any action brought by a third party) even if such damage or loss was 
+--              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+--
+--  Critical Applications:
+--
+--    Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+--    requiring fail-safe performance, such as life-support or safety devices or systems, 
+--    Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+--    or any other applications that could lead to death, personal injury, or severe property or 
+--    environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+--    the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+--    to applicable laws and signalulations governing limitations on product liability.
+--
+--  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Serdes 1 to n SDR
+--! @author Alvaro Dosil
+-------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all ;
+
+library unisim ;
+use unisim.vcomponents.all ;
+
+entity serdes_1_to_n_SDR is 
+generic ( g_S : integer := 4);       --! Parameter to set the serdes factor 1..8
+port( clk_i  : in std_logic;         --! Fast clock to sample data (640MHz)
+      hclk_i   : in std_logic;       --! A quarter frequency clock (160MHz)
+      reset_i  : in std_logic;       --! reset signal
+      Data_i   : in std_logic;       --! 1-Bit Input data
+      strobe_i : in std_logic;       --! Iserdes strobe_i
+      Data_o   : out std_logic_vector(2*g_S-1 downto 0)  --! data output
+		);
+    
+end serdes_1_to_n_SDR;
+
+
+architecture Behavioral of serdes_1_to_n_SDR is
+
+signal s_Data_i_d_m  : std_logic;     -- Data_i delayed master
+signal s_Data_i_d_2m : std_logic;     -- Data_i delayed master second signal
+signal s_Data_i_d_s  : std_logic;     -- Data_i delayed slave
+signal s_Data_i_d_2s : std_logic;     -- Data_i delayed slave second signal
+signal s_Data_o      : std_logic_vector(2*g_S-1 downto 0);
+
+--signal s_clk_b       : std_logic;
+--signal s_ISERDES_STROBE : std_logic;
+
+begin
+	
+---- Generate the ISERDES strobe signal
+--
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK => s_clk_b,                -- 1-bit output: Output I/O clock
+--      LOCK => open,                     -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => s_ISERDES_STROBE, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK => hclk_i,                     -- 1-bit input: BUFG clock input
+--      LOCKED => locked_pll_i,                  -- 1-bit input: LOCKED input from PLL
+--      PLLIN => clk_i                -- 1-bit input: Clock input from PLL
+--   );
+	
+
+  IODELAY2_M : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",     -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",         -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",          -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE     => 0,                -- Amount of taps for fixed input delay (0-255)
+    IDELAY2_VALUE    => 0,                -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE     => 0,                -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE      => "NONE"            -- "NONE", "MASTER" or "SLAVE" 
+--    SIM_TAPDELAY_VALUE=> 43                -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,          -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_m,     -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2m,    -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,          -- 1-bit output: Delayed data output
+    TOUT     => open,          -- 1-bit output: Delayed 3-state output
+    CAL      => '0',           -- 1-bit input: Initiate calibration input
+    CE       => '0',           -- 1-bit input: Enable INC input
+    CLK      => '0',           -- 1-bit input: Clock input
+    IDATAIN  => Data_i,        -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',           -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',           -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',           -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',           -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,         -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'            -- 1-bit input: 3-state input signal
+   );
+
+
+  IODELAY2_S : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",      -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",       -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE       => 10,--29,            -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
+    IDELAY2_VALUE      => 0,             -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE       => 0,             -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE        => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+    --SIM_TAPDELAY_VALUE => 43              -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,             -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_s,        -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2s,       -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,             -- 1-bit output: Delayed data output
+    TOUT     => open,             -- 1-bit output: Delayed 3-state output
+    CAL      => '0',              -- 1-bit input: Initiate calibration input
+    CE       => '0',              -- 1-bit input: Enable INC input
+    CLK      => '0',              -- 1-bit input: Clock input
+    IDATAIN  => Data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',              -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',              -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,            -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'               -- 1-bit input: 3-state input signal
+   );
+
+
+  ISERDES2_M : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(1),
+    Q2     => s_Data_o(3),
+    Q3     => s_Data_o(5),
+    Q4     => s_Data_o(7), 
+    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,                 -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+    CE0     => '1',                  -- 1-bit input Clock enable input
+	 CLK0    => clk_i,                -- 1-bit input I/O clock network input
+    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,               -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_m,         -- 1-bit input Input data
+    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+  ISERDES2_S : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,          -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"          -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(0),
+    Q2     => s_Data_o(2),
+    Q3     => s_Data_o(4),
+    Q4     => s_Data_o(6),
+    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,               -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+    CE0     => '1',                -- 1-bit input Clock enable input
+	 CLK0    => clk_i,              -- 1-bit input I/O clock network input
+    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,             -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_s,       -- 1-bit input Input data
+    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+reg_out : process(hclk_i)
+begin
+  if rising_edge(hclk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/single_pulse_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/single_pulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e5da6214a380987ce7b7f9d4969ead408ebbafee
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/single_pulse_rtl.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--! @file
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-------------------------------------------------------------------------------
+--
+-- VHDL for producing a single clock low-high-low pulse on the rising edge
+-- of input signal (LEVEL)
+--
+-- David Cussans, Ocala, April 2005
+--
+-- LEVEL (input) - when LEVEL goes high, PULSE goes high for one clock cycle
+--               - on next rising edge of CLK
+-- CLK (input)   - rising edge active
+-- PULSE         - changes on rising edge of clk
+--
+--! @brief gives a single cycle pulse ( high active) following the rising edge of LEVEL
+
+entity single_pulse is
+  generic (
+    g_PRE_REGISTER  : boolean := false;  -- --! Set true to put a register before rising edge detect
+    g_POST_REGISTER : boolean := false);  -- --! Set tru to put a register after rising edge detect
+  port (
+    level : in  std_logic; --! When LEVEL goes high, PULSE goes high for one clock cycle
+    clk : in  std_logic; --! rising edge active
+    pulse : out  std_logic              --! Pulses high for one cycle
+    );
+end entity single_pulse;
+
+architecture rtl of single_pulse is
+
+  signal pre_level, pre_pulse , x, v : std_logic;
+  
+begin  -- architecture rtl
+
+  -----------------------------------------------
+  -- Optional register on input
+  -----------------------------------------------
+  gen_pre_ff: if g_PRE_REGISTER=true generate
+    ffpre: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pre_level <= level;
+      end if;
+    end process ffpre;
+  end generate gen_pre_ff;
+
+  gen_no_pre_ff: if g_PRE_REGISTER=false generate
+    pre_level <= level;
+  end generate gen_no_pre_ff;
+
+  -----------------------------------------------
+  -- Register signal
+  -----------------------------------------------  
+  ff1: process (clk , level) is
+  begin  -- process ff1
+    if rising_edge(clk) then
+      x <= pre_level;
+    end if;
+  end process ff1;
+
+  -----------------------------------------------
+  -- Edge detection logic
+  -----------------------------------------------  
+  ff2: process (clk , x) is
+  begin  -- process ff2
+    if rising_edge(clk) then
+      v <= not x;
+    end if;
+  end process ff2;                           
+                           
+  pre_pulse <= ( x and v );
+
+
+  -----------------------------------------------
+  -- Optional register on output
+  -----------------------------------------------
+  gen_post_ff: if g_POST_REGISTER=true generate
+    ffpost: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pulse <= pre_pulse;
+      end if;
+    end process ffpost;
+  end generate gen_post_ff;
+
+  gen_no_post_ff: if g_POST_REGISTER=false generate
+    pulse <= pre_pulse;
+  end generate gen_no_post_ff;
+  
+end architecture rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse4x_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse4x_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7bc3d380ad030bb3e965c55df6dcdef4f3ccbbb6
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse4x_rtl.vhd
@@ -0,0 +1,69 @@
+--! @file stretchPulse4x_rtl.vhd
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+--! @brief Takes a pulse on 4x clock and produces a pulse with a width
+--!determined by clk_4x_strobe
+--
+--
+--! @details
+--! @author David Cussans
+
+entity stretchPulse4x is
+  generic (
+    g_FIND_RISING_EDGE : boolean := true);  -- ! Set true to look for rising edge of input signal. NB. "false" Not implemented yet.
+  port (
+    clk_4x_i                    : in  std_logic;    --! system clock
+    clk_4x_strobe_i               : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    pulse_i                     : in  std_logic;    --! Input pulse
+    pulse_o                     : out std_logic    --! Output pulse
+    );
+end entity stretchPulse4x;
+
+architecture rtl of stretchPulse4x is
+
+  signal s_pulse_in_rising_edge , s_stretchedPulse: std_logic; --! Shaped to be single cycle of clock 4x
+  signal s_stretchedPulseSR , s_stretchedPulseSR_retimed : std_logic_vector(2 downto 0) := (others => '0');  --! shifted by clk4x
+begin  -- architecture rtl
+
+
+  --! Shape the input signal to be a single cycle of clk4x
+  cmp_rising_edge: entity work.single_pulse
+    generic map (
+      g_PRE_REGISTER  => true,
+      g_POST_REGISTER => true)
+    port map (
+      level => pulse_i,
+      clk   => clk_4x_i,
+      pulse => s_pulse_in_rising_edge);
+
+  -- purpose: produces a pulse 4 cycles of clk4x wide that starts when clk4x_strobe is high
+  -- type   : combinational
+  -- inputs : clk_4x_i
+  -- outputs: pulse_o
+  p_pulseStretch: process (clk_4x_i) is
+  begin  -- process p_pulseStretch
+    if rising_edge(clk_4x_i) then
+      if s_pulse_in_rising_edge = '1' then
+        s_stretchedPulse <= '1';
+        s_stretchedPulseSR <= "111";
+      else
+        s_stretchedPulse <= s_stretchedPulseSR(0);
+        s_stretchedPulseSR <= '0' & s_stretchedPulseSR(s_stretchedPulseSR'left downto 1);
+      end if;
+    end if;
+  end process p_pulseStretch;
+
+  -- purpose: moves stretched pulse so that it aligns with clk_4x_strobe
+  -- type   : combinational
+  -- inputs : clk_4x_i
+  -- outputs: pulse_o
+  p_retimePulse: process (clk_4x_i) is
+  begin  -- process p_retimePulse
+    if rising_edge(clk_4x_i) and (clk_4x_strobe_i ='1') then
+      pulse_o <= s_stretchedPulse;
+    end if;
+  end process p_retimePulse;
+  
+end architecture rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..957a4c6d4164aa9b2b58dea19e86a068aa8f84de
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/stretchPulse_rtl.vhd
@@ -0,0 +1,92 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+--! @brief Takes a pulse on input, stretches it and delays it.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! Definition of trigger time
+USE work.fmcTLU.all;                    
+
+entity stretchPulse is
+  
+  generic (
+    g_PARAM_WIDTH : positive := 5);  --! number of bits in parameters (width,  delay)
+
+  port (
+    clk_i        : in  std_logic;       --! Active high
+    pulse_i      : in  std_logic;       --! Active high
+    pulse_o      : out std_logic;       --! delayed and stretched
+    triggerTime_i : in t_triggerTime;   --! 5-bit time
+    triggerTime_o : out t_triggerTime;  --! Delayed by same amount as pulse
+    
+    pulseWidth_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0);  --! Minimum pulse width ( in clock cycles )
+    pulseDelay_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0) --! Delay is pulseDelay_i +1 clock cycles
+    );      
+
+end entity stretchPulse;
+
+-- For now just delay the pulse.
+architecture rtl of stretchPulse is
+
+  signal s_delaySR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate delay
+  signal s_stretchSR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate stretch
+  signal s_delayedPulse : std_logic := '0';  -- delayed pulse before stretch
+
+  signal s_triggerTimeSR : t_triggerTimeArray ( (2**g_PARAM_WIDTH)-1 downto 0) := ( others => ( others => '0'));  -- array of trigger times
+  signal s_triggerTime_d1 : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  signal s_stretchedTriggerTime : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  
+begin  -- architecture rtl
+
+  
+  --! Delay pulse
+  p_delayPulse: process (clk_i , pulse_i) is
+  begin  -- process p_delayPulse
+    if rising_edge(clk_i) then
+      s_delaySR <= s_delaySR( (s_delaySR'left -1) downto 0 ) & pulse_i;
+      s_delayedPulse <= s_delaySR( to_integer(unsigned(pulseDelay_i)) );
+
+      -- delay the trigger time to match trigger delay
+      s_triggerTimeSR <=  s_triggerTimeSR( (s_triggerTimeSR'left -1)  downto 0 ) & triggerTime_i;
+      s_triggerTime_d1 <=  s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) ); 
+--      triggerTime_o <= s_triggerTime_d1 ;
+      
+    end if;
+  end process p_delayPulse;
+
+  --! Stretch pulse. the output pulse is always at least as long as the input pulse
+  p_stretchPulse: process (clk_i , pulse_i) is
+  begin  -- process p_stretchPulse
+    if rising_edge(clk_i) then
+      if s_delayedPulse = '1' then
+        s_stretchSR <= ( others => '1' ) ;
+        pulse_o <= s_delayedPulse ;
+      else
+        s_stretchSR <= s_stretchSR( (s_stretchSR'left -1) downto 0 ) & '0';
+        pulse_o <= s_stretchSR( to_integer(unsigned(pulseWidth_i)) );
+      end if;
+
+      if s_stretchSR( to_integer(unsigned(pulseWidth_i)) ) = '0' then
+        --s_stretchedTriggerTime <= s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) );
+        triggerTime_o <= s_triggerTime_d1;
+      end if;
+      --triggerTime_o <= s_stretchedTriggerTime ;
+      
+    end if;
+  end process p_stretchPulse;
+
+end architecture rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/sychronizedIPBusCtrlRegV_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/sychronizedIPBusCtrlRegV_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e1d751261317129227224e221add93ff745a83e
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/sychronizedIPBusCtrlRegV_rtl.vhd
@@ -0,0 +1,83 @@
+--=============================================================================
+--! @file 
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+--! @brief IPBus registers synchronzied onto logic clock
+--!
+--! @details Uses DMN ipbus_ctrlreg_v - originally tried to use
+--! ipbus_ctrlreg_sync, but had poor results and added own synchronzier.
+
+entity synchronizedIPBusCtrlRegV_rtl is
+	generic(
+		N_CTRL: positive := 1;
+		N_STAT: positive := 1
+	);
+	port(
+		ipbus_clk_i: in std_logic;
+		ipbus_reset_i: in std_logic;
+		ipbus_i: in ipb_wbus;
+		ipbus_o: out ipb_rbus;
+                logic_clk_i: in std_logic;
+		status_to_ipbus_i: in ipb_reg_v(N_STAT - 1 downto 0); --! Synchronized to logic_clk_i       
+		sync_control_from_ipbus_o: out ipb_reg_v(N_CTRL - 1 downto 0); --! Synchronized to logic_clk_i
+		stb_o: out std_logic_vector(N_CTRL - 1 downto 0) --! high when change made to a control register. Broken ( needs to be retimed )
+	);
+	
+end synchronizedIPBusCtrlRegV_rtl;
+
+
+architecture rtl of synchronizedIPBusCtrlRegV_rtl is
+
+  signal s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus   : ipb_reg_v(c_N_CTRL-1 downto 0);
+ 
+begin  -- architecture rtl
+
+  
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  stb_o
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  status_to_ipbus_i,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => sync_control_from_ipbus_o,
+      clk_output_i => clk_4x_logic_i);
+
+end architecture rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/sync_reg.vhd b/AIDA_tlu/components/tlu/firmware/hdl/sync_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e88eb54b67be346b7398099036524bcd023f6c9d
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/sync_reg.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    15/08/2012 
+-- Module Name:    Conf_Regs - Behavioral 
+-- Revision 1.00 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 32b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity sync_reg is
+  generic(g_Data_width : positive := 32);
+  port(
+    clk_i : in std_logic;  --! synchronous clock
+    Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
+	 Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
+  
+end sync_reg;
+
+--! @brief
+--! @details Synchronize words (n bits)of data 
+
+architecture Behavioral of sync_reg is
+
+signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
+signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
+begin
+  
+loop0: for i in 0 to g_Data_width-1 generate
+  begin
+  reg: entity work.Reg_2clks
+    port map(
+	   clk_i => clk_i,
+		async_i => s_async_i(i),
+		sync_o => s_sync_o(i));
+  end generate;
+ 
+s_async_i <= Async_i; 
+Sync_o <= s_sync_o;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_fifo.vhd b/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ebae77b4608297df1d02232d5891e1c0aa2cd7a9
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_fifo.vhd
@@ -0,0 +1,110 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+
+
+entity synchronizeRegisters_fifo is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters_fifo;
+
+architecture rtl of synchronizeRegisters_fifo is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+  COMPONENT sync_fifo
+    PORT (
+      rst : IN STD_LOGIC;
+      wr_clk : IN STD_LOGIC;
+      rd_clk : IN STD_LOGIC;
+      din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_en : IN STD_LOGIC;
+      rd_en : IN STD_LOGIC;
+      dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      full : OUT STD_LOGIC;
+      empty : OUT STD_LOGIC
+    );
+  END COMPONENT;
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  gen_syncReg: for v_reg in 0 to g_NUM_REGISTERS-1 generate
+      mySynchReg : sync_fifo
+        PORT MAP (
+          rst => '0',
+          wr_clk => clk_input_i,
+          rd_clk => clk_output_i,
+          din => data_i(v_reg),
+          wr_en => '1',
+          rd_en => '1',
+          dout => data_o(v_reg),
+          full => open,
+          empty => open
+        );
+  end generate gen_syncReg;
+  
+--  p_gen_capture_strobe: process (clk_input_i)
+--  begin  -- process p_gen_capture_strobe
+--    if rising_edge(clk_input_i) then
+--      s_ring_d0 <= not s_ring_d5;
+--      s_ring_d1 <= s_ring_d0;
+--      s_ring_d2 <= s_ring_d1;
+
+--      if s_read_strobe = '1' then
+--        s_registered_data <= data_i;
+--      end if;
+--    end if;    
+--  end process p_gen_capture_strobe;
+
+--  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+--  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+--  -- type   : combinational
+--  -- inputs : clk_output_i
+--  -- outputs: 
+--  p_gen_output_strobe: process (clk_output_i)
+--  begin  -- process p_gen_output_strobe
+--    if rising_edge(clk_output_i) then
+--      s_ring_d3 <= s_ring_d2;
+--      s_ring_d4 <= s_ring_d3;
+--      s_ring_d5 <= s_ring_d4;
+
+--      if s_write_strobe = '1' then
+--        data_o <= s_registered_data;
+--      end if;
+--    end if;    
+--  end process p_gen_output_strobe;
+
+--  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bb7d59a7e8d748cb160690d37e4e2225ffaf9e5a
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/synchronizeRegisters_rtl.vhd
@@ -0,0 +1,103 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Regularly transfers the input to the output.
+--! One clock for input , one clock for output
+--! Can't just put entire bus through a couple of register stages,
+--! Since this will just swap meta-stability issues for race issues.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 24/Nov/12
+--!
+--! @version v0.1
+--!
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--! Based on registerCounters
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+
+entity synchronizeRegisters is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters;
+
+architecture rtl of synchronizeRegisters is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/test_inToOut.vhd b/AIDA_tlu/components/tlu/firmware/hdl/test_inToOut.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..91b60eec700141731d07a95e72c903a597e4e6ef
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/test_inToOut.vhd
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 14:45:31
+-- Design Name: 
+-- Module Name: test_inToOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inToOut is
+    Generic(
+        DUT_TOGGLE : integer  :=1; --HDMI that toggles
+        DUT_OUT : integer := 2; --HDMI used as input
+        DUT_IN : integer := 0; --HDMI used as output
+        DUT_DULL : integer := 3 --HDMI not used
+    );
+    Port ( clk_in : in STD_LOGIC;
+           busy_in : in STD_LOGIC_VECTOR (3 downto 0);
+           control_in : in STD_LOGIC_VECTOR (3 downto 0);
+           trig_in : in STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_in : in STD_LOGIC_VECTOR (3 downto 0);
+           spare_in : in STD_LOGIC_VECTOR (3 downto 0);
+           busy_out : out STD_LOGIC_VECTOR (3 downto 0);
+           control_out : out STD_LOGIC_VECTOR (3 downto 0);
+           trig_out : out STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_out : out STD_LOGIC_VECTOR (3 downto 0);
+           spare_out : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inToOut;
+
+architecture Behavioral of test_inToOut is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(4 downto 0);
+    signal clk_slow_i : std_logic_vector(4 downto 0);
+    signal placeholder: std_logic_vector(4 downto 0);
+
+begin
+
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+        clk_slow_i(4) <= outcounter(4);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+      
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+  
+      clkDut_out(DUT_OUT) <= clkDut_in(DUT_IN);
+      busy_out(DUT_OUT) <= busy_in(DUT_IN);
+      control_out(DUT_OUT) <= control_in(DUT_IN);
+      trig_out(DUT_OUT) <= trig_in(DUT_IN);
+      spare_out(DUT_OUT) <= spare_in(DUT_IN);
+      
+      clkDut_out(DUT_DULL) <= '0';
+      busy_out(DUT_DULL) <= '0';
+      control_out(DUT_DULL) <= '0';
+      trig_out(DUT_DULL) <= '0';
+      spare_out(DUT_DULL) <= '0';
+    end if;
+    end process gen_clk;
+    
+
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/test_inputToOutput.vhd b/AIDA_tlu/components/tlu/firmware/hdl/test_inputToOutput.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b8cbb1d914de2e1c84d446bd3236885b24f318fc
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/test_inputToOutput.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 12:54:36
+-- Design Name: 
+-- Module Name: test_inputToOutput - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inputToOutput is
+    Port ( clk_i : in STD_LOGIC;
+           test_i : in STD_LOGIC_VECTOR (3 downto 0);
+           test_o : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inputToOutput;
+
+architecture Behavioral of test_inputToOutput is
+    signal synch_lines : std_logic_vector(3 downto 0);
+begin
+    synch_io : process (clk_i)
+    begin
+        if rising_edge(clk_i) then
+            synch_lines <= test_i;
+            test_o(1) <= synch_lines(0);
+            test_o(3) <= synch_lines(2);
+            test_o(0) <= '0';
+            test_o(2) <= '1';
+        end if;
+    end process synch_io;
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/test_toggleLines.vhd b/AIDA_tlu/components/tlu/firmware/hdl/test_toggleLines.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed585cdb02aabf04b00bff39d8962d0c7a571b74
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/test_toggleLines.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06.02.2017 10:09:26
+-- Design Name: 
+-- Module Name: test_toggleLines - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_toggleLines is
+    Port (
+        clk_in : in STD_LOGIC;
+        toggle_o : out std_logic_vector(3 downto 0)
+        );
+end test_toggleLines;
+
+architecture Behavioral of test_toggleLines is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(3 downto 0);
+    signal clk_slow_i : std_logic_vector(3 downto 0);
+    
+begin
+
+  gen_clk : process (clk_in)
+  begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+    end if;
+  end process gen_clk;
+
+  toggle_o <= clk_slow_i;
+
+
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/testbench_clocks.vhd b/AIDA_tlu/components/tlu/firmware/hdl/testbench_clocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..052b220c4e4e5e7b7d354731525a4e935a289d6f
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/testbench_clocks.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:26:56
+-- Design Name: 
+-- Module Name: testbench_clocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity testbench_clocks is
+--  Port ( );
+end testbench_clocks;
+
+architecture Behavioral of testbench_clocks is
+
+begin
+
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/testbench_myclocks.vhd b/AIDA_tlu/components/tlu/firmware/hdl/testbench_myclocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c17c7db550bad4f2ee74c868331b64ae7a9cd80b
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/testbench_myclocks.vhd
@@ -0,0 +1,99 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:31:53
+-- Design Name: 
+-- Module Name: testbench_myclocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+
+entity testbench_myclocks is
+end testbench_myclocks;
+
+architecture Behavioral of testbench_myclocks is
+
+ COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    SIGNAL sysclk_40         : std_logic := '0';
+    SIGNAL clk_8x_logic         : std_logic := '0';
+    SIGNAL clk_4x_logic         : std_logic := '0';
+    SIGNAL strobe_8x_logic         : std_logic := '0';
+    SIGNAL strobe_4x_logic         : std_logic := '0';
+    SIGNAL logic_reset         : std_logic := '0';
+    signal ipbus_i_const             : ipb_wbus;
+
+
+begin
+    
+      ipbus_i_const.ipb_strobe <= '0';
+      ipbus_i_const.ipb_write <= '0';
+      ipbus_i_const.ipb_wdata <= (others => '0');
+    
+        I3_Clocks : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => '0',
+        ipbus_i               => ipbus_i_const,
+        ipbus_reset_i         => '0',
+        Reset_i               => '0',
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => open,
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => open,
+        logic_reset_o         => logic_reset
+    );  
+
+end Behavioral;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/top_enclustra_ax3_pm3.vhd b/AIDA_tlu/components/tlu/firmware/hdl/top_enclustra_ax3_pm3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..589be2f2d67563dad293f528c9c23c1589e4927a
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/top_enclustra_ax3_pm3.vhd
@@ -0,0 +1,173 @@
+-- Top-level design for ipbus demo
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top is
+    generic(
+    g_NUM_DUTS  : positive := 3;
+    g_NUM_TRIG_INPUTS   :positive := 4;
+    g_NUM_EXT_SLAVES    :positive :=8;
+    g_EVENT_DATA_WIDTH  :positive := 64;
+    g_IPBUS_WIDTH   :positive := 32;
+    g_NUM_EDGE_INPUTS   :positive := 4;
+    g_SPILL_COUNTER_WIDTH   :positive := 12;
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+        sysclk: in std_logic;
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        i2c_scl_b: inout std_logic_vector(2 downto 0);
+        i2c_sda_b: inout std_logic_vector(2 downto 0);
+        phy_rstn: out std_logic; --default example ends here
+        busy_n_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        busy_p_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        cfd_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        cfd_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        gpio_hdr: out std_logic_vector(3 downto 0);
+        reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 1);
+        shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 1)
+        );
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	SIGNAL s_i2c_scl_enb         : std_logic_vector(2 downto 0);
+    SIGNAL s_i2c_sda_enb         : std_logic_vector(2 downto 0);
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b(0) <= '0' when (s_i2c_scl_enb(0) = '0') else 'Z';
+    i2c_sda_b(0) <= '0' when (s_i2c_sda_enb(0) = '0') else 'Z';
+    i2c_scl_b(1) <= '0' when (s_i2c_scl_enb(1) = '0') else 'Z';
+    i2c_sda_b(1) <= '0' when (s_i2c_sda_enb(1) = '0') else 'Z';
+    i2c_scl_b(2) <= '0' when (s_i2c_scl_enb(2) = '0') else 'Z';
+    i2c_sda_b(2) <= '0' when (s_i2c_sda_enb(2) = '0') else 'Z';
+-- Infrastructure
+
+
+
+
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => sysclk,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	leds <= not ('0' & userled & inf_leds);
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151f"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81f"; -- 192.168.200.16+n
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+--	slaves: entity work.ipbus_example
+--		port map(
+--			ipb_clk => clk_ipb,
+--			ipb_rst => rst_ipb,
+--			ipb_in => ipb_out,
+--			ipb_out => ipb_in,
+--			nuke => nuke,
+--			soft_rst => soft_rst,
+--			i2c_scl_b => i2c_scl_b,
+--            i2c_sda_b => i2c_sda_b,
+--			userled => userled
+--		);
+    --OBUFT: Single-ended 3-state Output Buffer
+--7 Series
+-- Xilinx HDL Libraries Guide, version 2012.2
+
+--OBUFT_inst_scl : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_scl_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_scl_enb, -- 3-state enable input
+--    O =>  s_i2c_scl_i
+--); -- End of OBUFT_inst instantiation
+
+--OBUFT_inst_sda : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_sda_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_sda_enb, -- 3-state enable input
+--    O =>  s_i2c_sda_i
+--); -- End of OBUFT_inst instantiation
+    
+    slaves: entity work.ipbus_example
+    port map(
+        ipb_clk => clk_ipb,
+        ipb_rst => rst_ipb,
+        ipb_in => ipb_out,
+        ipb_out => ipb_in,
+        nuke => nuke,
+        soft_rst => soft_rst,
+        --i2c_scl_i => s_i2c_scl_i,
+        --i2c_sda_i => s_i2c_sda_i,
+        i2c_sda_i => i2c_sda_b,
+        i2c_scl_i => i2c_scl_b,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        userled => userled
+    );
+
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/IODELAYCal_FSM_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/IODELAYCal_FSM_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d69931d3dd04bfae2a5f4876c7984d6ebf0e28f
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/IODELAYCal_FSM_rtl.vhd
@@ -0,0 +1,102 @@
+--=============================================================================
+--! @file IODELAYCal_FSM_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- UoB , USC
+-- --
+------------------------------------------------------------------------------- --
+--
+--! @brief Finite-state machine to control calibration and reset signals to
+--! Iserdes, IDelay
+--! based on code by Alvaro Dosil\n
+--
+--! @author  Alvaro Dosil 
+--
+--! @date 22/Feb/2014
+--
+--! @version v0.1
+--
+--! @details
+--
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--! <another thing to do> \n
+
+  LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity IODELAYCal_FSM is
+	port (
+		clk_i 		: in std_logic;		--! Global clock
+		startcal_i 	: in std_logic;      --! Start calibration
+		busy_i 		: in std_logic;     	--! Status of the IDELAY component
+		calibrate_o : out std_logic;     --! Calibration signals to IODELAY
+		reset_o 		: out std_logic  		--! Reset to IODELAY component
+    );
+end entity IODELAYCal_FSM;
+
+architecture rtl of IODELAYCal_FSM is
+
+  --! Calibration FSM state values
+  type state_values is (st0, st1, st2, st3);
+  signal pres_state, next_state: state_values := st0;
+  
+	signal s_cal_FSM      : std_logic := '0';         -- IODELAY reset
+  signal s_rst_FSM      : std_logic := '0';         -- IODELAY reset
+  
+begin  -- rtl
+
+  --! Calibration FSM register
+  statereg: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      pres_state <= next_state;     -- Move to next state
+      
+    end if;
+  end process statereg;
+
+
+  --! Calibration FSM combinational block
+  fsm: process(pres_state, startcal_i, busy_i)
+  begin
+    next_state <= pres_state;
+    -- Default values
+    s_Rst_FSM <= '0';
+    s_cal_FSM <= '0';
+    
+    case pres_state is
+      
+      -- st0 - IDLE
+      when st0=>
+        if ( startcal_i = '1') then 
+          next_state <= st1;            -- Next state is "st1 - SEND CALIBRATION SIGNAL"
+        end if;
+        
+      -- st1 - SEND CALIBRATION SIGNAL
+      when st1=>
+        s_cal_FSM <= '1';
+		  next_state <= st2;            -- Next state is "st2 - WAIT BUSY = '0'"
+        
+      -- st2 - WAIT BUSY = '0'
+      when st2=>
+        if busy_i = '0' then 
+          next_state <= st3;            -- Next state is "st3 - RESET STATE"
+        end if;
+        
+        -- st3 - RESET STATE
+      when st3=>
+        s_Rst_FSM <= '1';
+		  next_state <= st0;              -- Next state is "st0 - IDLE"
+		
+    end case;
+    
+  end process fsm;
+
+  calibrate_o <= s_cal_FSM;
+  reset_o <= s_Rst_FSM;
+                
+end rtl;
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/arrivalTimeLUT_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/arrivalTimeLUT_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f1b1acc0fb60c0741bc98fc83a2b8acf194ebddc
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/arrivalTimeLUT_rtl.vhd
@@ -0,0 +1,187 @@
+--=============================================================================
+--! @file arrivalTimeLUT_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.ArivalTimeLUT.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! @brief Uses a look-up-table to convert the eight bits from the two 1:4 deserializers\n
+--! into a 5-bit time ( 3 bits from the position in 8-bit deserialized data \n
+--! plus two bits from position w.r.t. the strobe_4x_logic_i signal ( one pulse
+--! every 4 cycles of clk_4x_logic_i 
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:46:34 11/21/12
+--
+--! @version v0.1
+--
+--! @details
+--! Rising and falling edge times encoded as a LUT. Contents:
+--! MRFrrrfff
+--! \li M = multiple edges present ( more than one rising or falling edge)
+--! \li R = at least one rising edge present
+--! \li F = at least one falling edge present.
+--! \li rrr = time of first rising edge
+--! \li fff = time of first falling edge
+ENTITY arrivalTimeLUT IS
+   GENERIC( 
+      g_NUM_FINE_BITS   : positive := 3;
+      g_NUM_COARSE_BITS : positive := 2
+   );
+   PORT( 
+      clk_4x_logic_i           : IN     std_logic;                                                        --! Rising edge active
+      strobe_4x_logic_i        : IN     std_logic;                                                        --! Pulses high once every 4 cycles of clk_4x_logic
+      deserialized_data_i      : IN     std_logic_vector (8 DOWNTO 0);                                    --! Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data
+      first_rising_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      last_falling_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      rising_edge_o            : OUT    std_logic;                                                        --! goes high if there is a rising edge in the data. Clocked by clk_4x_logic_i
+      falling_edge_o           : OUT    std_logic;                                                        --! goes high if there is a falling edge in the data.Clocked by clk_4x_logic_i
+      multiple_edges_o         : OUT    std_logic                                                         --! there is more than one rising or falling edge transition.
+   );
+
+-- Declarations
+
+END ENTITY arrivalTimeLUT ;
+
+--
+ARCHITECTURE rtl OF arrivalTimeLUT IS
+
+  constant c_FALLING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS;  --! Bit position of bit set when falling edge detected
+  constant c_RISING_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+1;  --! Bit position of bit set when rising edge detected
+  constant c_MULTI_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+2;  --! Bit position of bit set when rising edge detected
+
+
+  signal s_coarse_bits : std_logic_vector(g_NUM_COARSE_BITS-1 downto 0) := "00";  --! phase w.r.t. strobe
+
+  signal s_LUT_ENTRY : std_logic_vector(g_NUM_FINE_BITS*2 +3-1 downto 0);  -- stores intermediate LUT value.
+  
+  type t_LUT is array (natural range <>) of std_logic_vector(g_NUM_FINE_BITS*2 + 3 -1 downto 0);
+  --! Lookup table for arrival time and rising/falling edge detection (3bits
+  --! for position in 9-bit deserialized data plus two bits for rising/falling 
+  constant c_LUT : t_LUT(0 to 511) := (
+    "000000000", "001000000", "011000001", "001000001", "011001010", "011001010", "011000010", "001000010", --0 [0, 7]
+    "011010011", "011010011", "111000011", "011010011", "011001011", "011001011", "011000011", "001000011", --1 [8, 15]
+    "011011100", "011011100", "111000100", "011011100", "111001100", "111001100", "111000100", "011011100", --2 [16, 23]
+    "011010100", "011010100", "111000100", "011010100", "011001100", "011001100", "011000100", "001000100", --3 [24, 31]
+    "011100101", "011100101", "111000101", "011100101", "111001101", "111001101", "111000101", "011100101", --4 [32, 39]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011100101", --5 [40, 47]
+    "011011101", "011011101", "111000101", "011011101", "111001101", "111001101", "111000101", "011011101", --6 [48, 55]
+    "011010101", "011010101", "111000101", "011010101", "011001101", "011001101", "011000101", "001000101", --7 [56, 63]
+    "011101110", "011101110", "111000110", "011101110", "111001110", "111001110", "111000110", "011101110", --8 [64, 71]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --9 [72, 79]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --10 [80, 87]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --11 [88, 95]
+    "011100110", "011100110", "111000110", "011100110", "111001110", "111001110", "111000110", "011100110", --12 [96, 103]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011100110", --13 [104, 111]
+    "011011110", "011011110", "111000110", "011011110", "111001110", "111001110", "111000110", "011011110", --14 [112, 119]
+    "011010110", "011010110", "111000110", "011010110", "011001110", "011001110", "011000110", "001000110", --15 [120, 127]
+    "011110111", "011110111", "111000111", "011110111", "111001111", "111001111", "111000111", "011110111", --16 [128, 135]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --17 [136, 143]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --18 [144, 152]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --19 [152, 159]
+    "111100111", "111100111", "111000111", "111100111", "111001111", "111001111", "111000111", "111100111", --20 [160, 167]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "111100111", --21 [168, 175]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --22 [176, 183]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --23 [184, 191]
+    "011101111", "011101111", "111000111", "011101111", "111001111", "111001111", "111000111", "011101111", --24 [192, 199]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --25 [200, 207]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --26 [208, 215]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --27 [216, 223]
+    "011100111", "011100111", "111000111", "011100111", "111001111", "111001111", "111000111", "011100111", --28 [224, 231]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011100111", --29 [232, 239]
+    "011011111", "011011111", "111000111", "011011111", "111001111", "111001111", "111000111", "011011111", --30 [240, 247]
+    "011010111", "011010111", "111000111", "011010111", "011001111", "011001111", "011000111", "001000111", --31 [248, 255]
+    "010111000", "011111000", "111000001", "011111001", "111001010", "111001010", "111000010", "011111010", --32 [256, 263]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011111011", --33 [264, 271]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --34 [272, 279]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011111100", --35 [280, 287]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --36 [288, 295]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --37 [296, 303]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --38 [304, 311]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011111101", --39 [312, 319]
+    "111101110", "111101110", "111000110", "111101110", "111001110", "111001110", "111000110", "111101110", --40 [320, 327]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --41 [328, 333]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --42 [336, 343]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --43 [344, 351]
+    "111100110", "111100110", "111000110", "111100110", "111001110", "111001110", "111000110", "111100110", --44 [352, 359]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111100110", --45 [360, 367]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --46 [368, 375]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011111110", --47 [376, 383]
+    "010110000", "011110000", "111000001", "011110001", "111001010", "111001010", "111000010", "011110010", --48 [384, 391]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011110011", --49 [392, 399]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --50 [400, 407]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011110100", --51 [408, 415]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --52 [416, 423]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --53 [424, 431]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --54 [432, 439]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011110101", --55 [440, 447]
+    "010101000", "011101000", "111000001", "011101001", "111001010", "111001010", "111000010", "011101010", --56 [448, 455]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011101011", --57 [456, 463]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --58 [464, 471]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011101100", --59 [472, 479]
+    "010100000", "011100000", "111000001", "011100001", "111001010", "111001010", "111000010", "011100010", --60 [480, 487]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011100011", --61 [488, 495]
+    "010011000", "011011000", "111000001", "011011001", "111001010", "111001010", "111000010", "011011010", --62 [496, 503]
+    "010010000", "011010000", "111000001", "011010001", "010001000", "011001000", "010000000", "000000000" -- 63 [504, 511]
+    );  
+  
+BEGIN
+
+  -- purpose: uses the deserialized data as a index into
+  --          a lookup table holding the position of the first rising edge (if any)
+  --          and if there is a rising or falling edge
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: arrival_time_o , rising_edge_o , falling_edge_o
+  examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
+--    variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0);  --! Entry in LUT pointed to by deserialized data
+  begin  -- process examine_lut
+    
+--    v_LUT_entry := c_LUT(to_integer(unsigned(deserialized_data_i)));
+
+    if rising_edge(clk_4x_logic_i) then
+      s_LUT_ENTRY <= c_LUT(to_integer(unsigned(deserialized_data_i)));
+      first_rising_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS*2-1 downto g_NUM_FINE_BITS);
+      last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
+      rising_edge_o  <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
+      falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
+      multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT); 
+    end if;
+
+  end process examine_lut;
+  
+  --! Coarse time stamp. Phase w.r.t. strobe
+--	c_coarse_ts : entity work.CounterUp
+--   PORT MAP (
+--     clk   => clk_4x_logic_i,
+--     ce    => '1',
+--     sinit => strobe_4x_logic_i, --'0',
+--	  q(31 downto 2) => open,
+--     q(1 downto 0)  => s_coarse_bits
+--	);
+--  
+  	c_coarse_ts : entity work.CounterWithReset
+  	GENERIC MAP (
+  	  g_COUNTER_WIDTH => 2 )
+   PORT MAP (
+     clock_i   => clk_4x_logic_i,
+     enable_i   => '1',
+     reset_i => strobe_4x_logic_i,        -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
+     result_o => s_coarse_bits
+	);
+	
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/dualSERDES_1to4_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/dualSERDES_1to4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..22ea1b9d42fcecaab7c9b3686290973b6c4f5c09
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/dualSERDES_1to4_rtl.vhd
@@ -0,0 +1,421 @@
+--=============================================================================
+--! @file dualSERDES_1to4_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.dualSERDES_1to4.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other
+--! based on TDC by Alvaro Dosil
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:06:53 11/16/12
+--
+--! @version v0.1
+--
+--! @details
+--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--
+--------------------------------------------------------------------------------
+
+ENTITY dualSERDES_1to4 IS
+   PORT( 
+      reset_i        : IN     std_logic;                      --! Resets  IODELAY
+      --calibrate_i    : IN     std_logic;                      --! Starts IODELAY calibration.
+      --data_i         : IN     std_logic;                      --! from input buffer.
+      data_i_pos     : IN     std_logic;                      --! from positive differential input pin 
+      data_i_neg     : IN     std_logic;                      --! from negative differential input pin 
+      fastClk_i      : IN     std_logic;                      --! 2x fabric clock. e.g. 320MHz
+      fabricClk_i    : IN     std_logic;                      --! clock for output to FPGA. e.g. 160MHz
+      strobe_i       : IN     std_logic;                      --! Strobes once every 4 cycles of fastClk
+      data_o         : OUT    std_logic_vector (7 DOWNTO 0);  --! Deserialized data. Interleaved between prompt and delayed  serdes.
+                                                              --! data_o(0) is the oldest data
+      status_o       : OUT    std_logic_vector(1 downto 0)    --! outputs from IODELAY "busy" 0=prompt,1=delayed
+   );
+
+-- Declarations
+
+
+END ENTITY dualSERDES_1to4 ;
+
+--
+ARCHITECTURE rtl OF dualSERDES_1to4 IS
+
+    constant c_S : positive := 4;                     -- ! SERDES division ratio
+
+    signal s_Data_i_d_p   : std_logic;
+    signal s_Data_i_d_d   : std_logic;
+    signal s_busy_idelay_p  : std_logic;              -- Busy from iodelay.
+    signal s_busy_idelay_d  : std_logic;              -- Busy from iodelay.
+    signal s_busy			  : std_logic;              -- Busy from the two iodelays.
+    signal s_data_o       : std_logic_vector(7 downto 0);  --! Deserialized data
+	signal s_cal			 : std_logic := '0'; 				--! Calibration signal
+	signal s_rst_cal		: std_logic := '0'; 				--! reset after calibration process
+    signal delay_val :std_logic_vector(4 downto 0);
+    signal prompt_val :std_logic_vector(4 downto 0);
+    signal delayed_out: std_logic_vector(4 downto 0);
+    signal prompt_out: std_logic_vector(4 downto 0);
+---------------------------------------------
+    component delayIO
+    generic
+    (-- width of the data for the system
+    SYS_W       : integer := 1;
+    -- width of the data for the device
+    DEV_W       : integer := 1);
+    port
+        (
+        -- From the system into the device
+        data_in_from_pins_p     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_from_pins_n     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_to_device       : out   std_logic_vector(DEV_W-1 downto 0);
+        
+        -- Input, Output delay control signals
+        delay_clk               : in    std_logic;
+        in_delay_reset          : in    std_logic;                    -- Active high synchronous reset for input delay
+        in_delay_data_ce        : in    std_logic_vector(SYS_W -1 downto 0);                    -- Enable signal for delay 
+        in_delay_data_inc       : in    std_logic_vector(SYS_W -1 downto 0);                    -- Delay increment (high), decrement (low) signal
+        delay_locked            : out   std_logic;                    -- Locked signal from IDELAYCTRL
+        ref_clock               : in    std_logic;                    -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
+        
+        -- Clock and reset signals
+        clk_in                  : in    std_logic;                    -- Fast clock from PLL/MMCM 
+        clock_enable            : in    std_logic;
+        io_reset                : in    std_logic);                   -- Reset signal for IO circuit
+    end component;
+
+  
+BEGIN
+ 
+	-- IODELAYs calibration FSM
+	IODELAYCal: entity work.IODELAYCal_FSM
+    port map (
+        clk_i       => fabricClk_i,
+        startcal_i  => reset_i,
+        busy_i		=> s_busy,
+        calibrate_o     => s_cal,
+        reset_o         => s_rst_cal
+    );
+
+
+-----------------------------------------------------
+--    iodelay_prompt : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_p,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        io_reset => s_rst_cal
+--    );
+    prompt_val <= "00000";
+
+    IDELAY2_Prompt : IDELAYE2
+    generic map (
+        IDELAY_TYPE => "VARIABLE",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> prompt_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_p,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> prompt_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+        IDATAIN => not data_i_neg, --- THIS MUST BE INVERTED!!!!
+        --IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '0',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+    
+
+
+----IODELAY2 no longer valid. Replaced using IP delay (SelectIO interface wizard generated)
+--  IODELAY2_Prompt : IODELAY2
+--    generic map (
+--      COUNTER_WRAPAROUND => "STAY_AT_LIMIT" ,  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--      DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+--      DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+--      SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--      IDELAY_TYPE        => "VARIABLE_FROM_ZERO",
+--      IDELAY_VALUE     	=> 0                -- Amount of taps for fixed input delay (0-255)
+--      --SIM_TAPDELAY_VALUE=> 10               -- Per tap delay used for simulation in ps
+--      )
+--    port map (
+--      BUSY     => s_busy_idelay_p,      -- 1-bit output: Busy output after CAL
+--      DATAOUT  => s_Data_i_d_p,     -- 1-bit output: Delayed data output to ISERDES/input register
+--      DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--      DOUT     => open,             -- 1-bit output: Delayed data output
+--      TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--      CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--      CE       => '0',              -- 1-bit input: Enable INC input
+--      CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--      IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--      INC      => '0',              -- 1-bit input: Increment / decrement input
+--      IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--      IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--      ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--      RST      => s_rst_cal,            -- 1-bit input: reset_i to 1/2 of total delay period
+--      T        => '1'               -- 1-bit input: 3-state input signal
+--      );
+    
+    s_busy_idelay_p <= (prompt_val(0) XOR  prompt_out(0)) OR (prompt_val(1) XOR  prompt_out(1)) OR (prompt_val(2) XOR  prompt_out(2)) OR (prompt_val(3) XOR  prompt_out(3)) OR (prompt_val(4) XOR  prompt_out(4));
+	status_o(1) <= s_busy_idelay_p;
+
+--    iodelay_delay : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_d,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        clk_out => open,
+--        io_reset => s_rst_cal
+--    );
+
+    -- This should be configurable via IPBus. For now fixed value. The tap value is 200 MHz (5 ns). We want
+    -- a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 6 taps.
+    delay_val <= "00110";
+    --delay_val <= "00000";
+    
+    IDELAY2_Delayed : IDELAYE2
+    generic map (
+        --IDELAY_TYPE => "VARIABLE",
+        IDELAY_TYPE => "VAR_LOAD",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> delayed_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_d,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> delay_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+--        IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        IDATAIN => data_i_pos,
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '1',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+        
+
+--    IODELAY2_Delayed : IODELAY2
+--    generic map (
+--        COUNTER_WRAPAROUND => "STAY_AT_LIMIT",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--        DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+--        DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+--        SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--        IDELAY_TYPE        => "VARIABLE_FROM_HALF_MAX",
+--        IDELAY_VALUE       => 0,             -- Amount of taps for fixed input delay (0-255)
+--        IDELAY2_VALUE      => 0             	-- Delay value when IDELAY_MODE="PCI" (0-255)
+--    --SIM_TAPDELAY_VALUE => 10              -- Per tap delay used for simulation in ps
+--    )
+--    port map (
+--        BUSY     => s_busy_idelay_d,      -- 1-bit output: Busy output after CAL
+--        DATAOUT  => s_Data_i_d_d,     -- 1-bit output: Delayed data output to ISERDES/input register
+--        DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--        DOUT     => open,             -- 1-bit output: Delayed data output
+--        TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--        CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--        CE       => '0',              -- 1-bit input: Enable INC input
+--        CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--        IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--        INC      => '0',              -- 1-bit input: Increment / decrement input
+--        IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--        IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--        ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--        RST      => s_rst_cal,          -- 1-bit input: reset_i to zero
+--        T        => '1'               -- 1-bit input: 3-state input signal
+--    );
+
+
+    --I must check that the CNTVALUEOUT and CNTVALUEIN are the same. TO DO
+	--status_o(0) <= s_busy_idelay_d;
+	s_busy_idelay_d <= (delay_val(0) XOR  delayed_out(0)) OR (delay_val(1) XOR  delayed_out(1)) OR (delay_val(2) XOR  delayed_out(2)) OR (delay_val(3) XOR  delayed_out(3)) OR (delay_val(4) XOR  delayed_out(4));
+	status_o(0) <= s_busy_idelay_d;
+	s_busy <= s_busy_idelay_p or s_busy_idelay_d;
+
+
+-----------------------------------------------------
+--ISERDES2 replaced by ISERDESE2 in Series 7
+--  ISERDES2_Prompt : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,           -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",     -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(1),         -- Oldest data
+--    Q2     => s_Data_o(3),
+--    Q3     => s_Data_o(5),
+--    Q4     => s_Data_o(7),         -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,                 -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+--    CE0     => '1',                  -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,            -- 1-bit input I/O clock network input
+--    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,          -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_p,         -- 1-bit input Input data
+--    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+--    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+
+    ISERDESE2_Prompt: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+    generic map (
+        DATA_RATE => "DDR",
+        DATA_WIDTH => 4,
+        INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+        IOBDELAY => "IFD", -- see table 3-4 in UG471 (v1.9)
+        SERDES_MODE => "MASTER",
+        NUM_CE => 1
+    )
+    port map (
+        O => open,
+        Q4     => s_Data_o(1), -- Oldest data
+        Q3     => s_Data_o(3),
+        Q2     => s_Data_o(5),
+        Q1     => s_Data_o(7),
+        BITSLIP => '0',
+        CE1 => '1',
+        CE2 => '1',
+        CLKDIVP => '0',
+        CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+        CLKB  => not fastClk_i, --should be a unique phase shifted clock
+        CLKDIV => fabricClk_i,
+        DDLY=> s_Data_i_d_p,
+        D=> '0', -- data_i
+        RST=> reset_i,
+        SHIFTIN1 => '0',
+        SHIFTIN2 => '0',
+        DYNCLKDIVSEL=> '0',
+        DYNCLKSEL=> '0', 
+        --OCLK => strobe_i,
+        OCLK => '0',
+        OCLKB => '0',
+        OFB=> '0'
+    );
+
+--  ISERDES2_Delayed : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,       -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,         -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",   -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"       -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--	-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(0),           -- oldest data
+--    Q2     => s_Data_o(2),
+--    Q3     => s_Data_o(4),
+--    Q4     => s_Data_o(6),           -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,               -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+--    CE0     => '1',                -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,          -- 1-bit input I/O clock network input
+--    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,        -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_d,       -- 1-bit input Input data
+--    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+--    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+   
+   
+   ISERDESE2_Delayed: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+       generic map (
+           DATA_RATE => "DDR",
+           DATA_WIDTH => 4,
+           INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+           IOBDELAY =>  "IFD", -- see table 3-4 in UG471 (v1.9)
+           SERDES_MODE => "MASTER",
+           NUM_CE => 1
+       )
+       port map (
+           O => open,
+           Q4     => s_Data_o(0),           -- oldest data
+           Q3     => s_Data_o(2),
+           Q2     => s_Data_o(4),
+           Q1     => s_Data_o(6), 
+           BITSLIP => '0',
+           CE1 => '1',
+           CE2 => '1',
+           CLKDIVP => '0',
+           CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+           CLKB  => not fastClk_i, --should be a unique phase shifted clock
+           CLKDIV => fabricClk_i,
+           DDLY=> s_Data_i_d_d,
+           D=> '0', -- data_i
+           RST=> reset_i,
+           SHIFTIN1 => '0',
+           SHIFTIN2 => '0',
+           DYNCLKDIVSEL=> '0',
+           DYNCLKSEL=> '0', 
+           OCLK => strobe_i,
+           OCLKB => '0',
+           OFB=> '0'
+       );
+-----------------------------------------------------
+
+
+
+reg_out : process(fabricClk_i)
+begin
+  if rising_edge(fabricClk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4443faf09d8ea7b4404309f8a38526f389ade458
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl.vhd
@@ -0,0 +1,291 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    -- Instantiate one for each trigger input of the TLU
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        -- Differential buffer. Receives differential trigger input and produces a buffered differential signal.
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+        
+        -- Deserialize the trigger input    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            --data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+        
+        -- Add last bit from previous word to the new deserialized data.        
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        -- Use a LUT to determine the leading/trailing edges of the trigger input
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..106e7703ceb450d9081a1a68b86aafbc3ec4aa01
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd
@@ -0,0 +1,335 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            data_i_pos     => threshold_discr_p_i(triggerInput),
+            data_i_neg     => threshold_discr_n_i(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+--REMOVE CFD        
+--        CFDInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_CFD_discr_input(triggerInput),
+--            I  => CFD_discr_p_i(triggerInput),
+--            IB => CFD_discr_n_i(triggerInput)
+--            );
+    
+--        CFDDeserializer: entity work.dualSERDES_1to4
+--          port map (
+--            reset_i => s_rst_iserdes,
+--            --calibrate_i => s_calibrate_idelay,
+--            data_i         => s_CFD_discr_input(triggerInput),
+--            fastClk_i      => clk_16x_logic_i,
+--            fabricClk_i    => clk_4x_logic,
+--            strobe_i       => strobe_16x_logic_i,
+--            data_o         => s_deserialized_CFD_data(triggerInput),
+--            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+--            );
+--        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+--        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+--        CFDLUT : entity work.arrivalTimeLUT
+--          port map (
+--            clk_4x_logic_i      => clk_4x_logic,
+--            strobe_4x_logic_i   => strobe_4x_logic_i,
+--            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+--            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+--            last_falling_edge_time_o => open, 
+--            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+--            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+--            multiple_edges_o    => open
+--            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              
+            --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9e3a01e19f1004dfd39bad1c31b25d478a4091df
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd
@@ -0,0 +1,301 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+    --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+--        thresholdInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_threshold_discr_input(triggerInput),
+--            I  => threshold_discr_p_i(triggerInput),
+--            IB => threshold_discr_n_i(triggerInput)
+--            );
+    
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+            
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+                  
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+            
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3d83e3d60baa144ef7e6b9a53cd86f97a08dfafd
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerInputs_rtl.vhd
@@ -0,0 +1,338 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs ;
+
+--
+ARCHITECTURE rtl OF triggerInputs IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+          --s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+        
+        CFDInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_CFD_discr_input(triggerInput),
+            I  => CFD_discr_p_i(triggerInput),
+            IB => CFD_discr_n_i(triggerInput)
+            );
+    
+        CFDDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i => s_rst_iserdes,
+            --calibrate_i => s_calibrate_idelay,
+            data_i         => s_CFD_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_CFD_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+            );
+        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+        CFDLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+            last_falling_edge_time_o => open, 
+            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              --s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
+            s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+  --! Monitor output of deserializer
+  -- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_status_to_ipbus(0)(23 downto 20);
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <=  s_edge_rising;
+  trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerLogic_rtl.vhd b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ff175d3ccf6b58d7699686491eb531962146051
--- /dev/null
+++ b/AIDA_tlu/components/tlu/firmware/hdl/trigger/triggerLogic_rtl.vhd
@@ -0,0 +1,355 @@
+--=============================================================================
+--! @file triggerLogic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+--! @brief Produces triggers from either trigger inputs or internal generator
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 16:06:19 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \br IPBus address map:
+--! \li 0x00000000 RO - Number of triggers issued since last reset.
+--! \li 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
+--! \li 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
+--! \li 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
+--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set high to halt triggers.
+--! \li 0x00000101 RO - state of external veto
+--! \li 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
+--! \li 0x00000111 RW - delay of pulses. 0-31 clock cycles.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+--! Add stretchPulse and coincidenceLogic entities. May/15 , David Cussans
+-------------------------------------------------------------------------------
+ENTITY triggerLogic IS
+   GENERIC( 
+      g_NUM_INPUTS  : positive := 4; 
+      g_IPBUS_WIDTH : positive := 32 
+   );
+   PORT( 
+      clk_4x_logic_i      : IN     std_logic;                                     -- ! Rising edge active
+      ipbus_clk_i         : IN     std_logic;
+      ipbus_i             : IN     ipb_wbus;                                      -- Signals from IPBus core to slave
+      ipbus_reset_i       : IN     std_logic;
+      logic_reset_i       : IN     std_logic;                                     -- active high. Synchronous with clk_4x_logic
+      logic_strobe_i      : IN     std_logic;                                     -- ! Pulses high once every 4 cycles of clk_4x_logic
+      trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active
+      trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      veto_i              : IN     std_logic;                                     -- ! Halts triggers when high
+      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active and enabled
+      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);   -- starts at one. Increments for each post_veto_trigger
+      ipbus_o             : OUT    ipb_rbus;                                      -- signals from slave to IPBus core
+      post_veto_trigger_o : OUT    std_logic;                                     -- ! goes high when trigger passes
+      pre_veto_trigger_o  : OUT    std_logic;
+      trigger_active_o    : OUT    std_logic                                      --! Goes high when triggers are active ( ie. not veoted)
+   );
+
+-- Declarations
+
+END triggerLogic ;
+
+--
+ARCHITECTURE rtl OF triggerLogic IS
+
+    --! vector that stores trigger output for each combination of trigger inputs.
+    signal s_trigger_inputs_enabled , s_trigger_inputs_enabled_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := x"00000001";--(others=>'1');  
+    signal s_external_trigger_p , s_external_trigger_l , s_auxTrigger , s_internal_veto , s_internal_veto_ipb : std_logic := '0';
+    signal s_internal_trigger_interval: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- setting s_internal_trigger_interval to zero means no internal triggers
+    signal s_pre_veto_trigger_counter , s_post_veto_trigger_counter , s_aux_trigger_counter: unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto
+    signal s_pre_veto_trigger_counter_ipb , s_post_veto_trigger_counter_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto, on ipbus clock domain
+    
+    signal s_triggers : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) := (others=>'0');
+    signal s_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) := (others=>(others=>'0'));
+    signal s_internal_trigger, s_internal_trigger_d : std_logic := '0';  -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
+    --  signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation
+    signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation and counter delay
+    signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0';  -- ! Goes high when internal trigger is running.
+    
+    --  signal s_logic_reset ,  s_logic_reset_ipb : std_logic := '0';  -- ! Take high to reset counters etc.
+    signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0';  -- ! Can't read from an output port so keep internal copy
+    
+    signal s_TriggerPattern_low : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (low 32-bits)
+    signal s_TriggerPattern_high : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (high 32-bits)
+    
+    signal s_PulseStretchWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseWidthWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseDelayWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --!number of cycles to delay trigger pulses.
+    signal s_TriggerHoldOffWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! minimum number of clock cycles between triggers
+    
+    constant c_PARAM_WIDTH : positive := 5;    -- length of pulse width and delay.
+    constant c_BYTE_WIDTH : positive := 5;    --Length of padded field for parameters. This should be at least equal to c_PARAM_WIDTH.
+                                              --If c_BYTE_WIDTH= 8 then the values are aligned to bytes in the 32-bit word (but we cannot store 6 of them...)
+                                              --If c_BYTE_WIDTH=5 then all the values are one after the other.
+    
+    constant c_N_CTRL : positive := 16;
+    constant c_N_STAT : positive := 16;
+    signal s_controlRegStrobes : std_logic_vector(c_N_CTRL-1 downto 0) := ( others => '0') ; --!
+                                                                             --Bit strobes when control reg is loaded
+    signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+    signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_loadTriggerPattern , s_loadTriggerPattern_p1 : std_logic := '0';  -- take high to load trigger pattern
+    signal s_loadTriggerPatternHi , s_loadTriggerPatternHi_p1 : std_logic := '0';  -- take high to load trigger pattern
+    
+    signal s_delayedTriggerTimes, s_delayedTriggerTimes_d1, s_delayedTriggerTimes_d2 : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! Array of std_logic_vectors
+    signal s_stretchedTriggers ,  s_stretchedTriggers_d1 ,  s_stretchedTriggers_d2 : std_logic_vector( trigger_i'range) := (others => '0');  -- --! Triggers after stretch and delay
+    
+    COMPONENT internalTriggerGenerator
+    PORT (
+        CLK : IN STD_LOGIC;
+        CE : IN STD_LOGIC;
+        LOAD : IN STD_LOGIC;
+        L : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    END COMPONENT;
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+        N_CTRL => c_N_CTRL,
+        N_STAT => c_N_STAT
+    )
+    port map(
+        clk => ipbus_clk_i,
+        reset=> '0',--ipbus_reset_i ,
+        ipbus_in=>  ipbus_i,
+        ipbus_out=> ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb=> s_controlRegStrobes
+    );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic_i,
+        data_i      =>  s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      =>  s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  -- workaround to match the number of clock cycles with the configured interval
+    s_internal_trigger_interval <= x"00000000" when s_sync_control_from_ipbus(2)<x"00000005" else
+										std_logic_vector(unsigned(s_sync_control_from_ipbus(2))-2);
+										
+    --s_TriggerPattern_low <= s_control_from_ipbus(3);
+    s_LoadTriggerPattern_p1 <= s_controlRegStrobes(10);
+    s_LoadTriggerPatternHi_p1 <= s_controlRegStrobes(11);
+    s_veto_word <= s_sync_control_from_ipbus(4);
+    s_internal_veto <= s_veto_word(0);
+    s_PulseWidthWord <= s_sync_control_from_ipbus(6);
+    s_PulseDelayWord <= s_sync_control_from_ipbus(7);
+    s_TriggerHoldOffWord <= s_sync_control_from_ipbus(8);
+    s_TriggerPattern_low <= s_control_from_ipbus(10);
+    s_TriggerPattern_high <= s_control_from_ipbus(11);
+    --s_PulseWidthWord <=s_sync_control_from_ipbus(10);
+    
+    s_external_veto_word(0) <= veto_i;
+    s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
+    
+    -- Map the status registers
+    s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
+    s_status_to_ipbus(1) <= std_logic_vector(s_pre_veto_trigger_counter);
+    s_status_to_ipbus(2) <= s_internal_trigger_interval;
+    --s_status_to_ipbus(3) <= s_TriggerPattern_low;
+    s_status_to_ipbus(4) <= s_veto_word;
+    s_status_to_ipbus(5) <= s_external_veto_word;
+    s_status_to_ipbus(6) <= s_PulseWidthWord; 
+    s_status_to_ipbus(7) <= s_PulseDelayWord; --fixed in addr. map
+    s_status_to_ipbus(8) <= s_TriggerHoldOffWord;
+    s_status_to_ipbus(9) <= std_logic_vector(s_aux_trigger_counter);-- not used and never updated. Remove at some point.
+    s_status_to_ipbus(10) <= s_TriggerPattern_low;
+    s_status_to_ipbus(11) <= s_TriggerPattern_high;
+
+    -- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
+    -- type   : combinational
+    -- inputs : ipbus_clk_i
+    -- outputs: 
+    p_delayLoadPulse: process (ipbus_clk_i) is
+    begin  -- process p_delayLoadPulse
+    if rising_edge(ipbus_clk_i) then
+        s_LoadTriggerPattern <= s_LoadTriggerPattern_p1;
+        s_LoadTriggerPatternHi <= s_LoadTriggerPatternHi_p1;
+    end if;
+    end process p_delayLoadPulse;
+
+  -- Stretch and delay pulses.
+  --D Put in delay for trigger times as well.
+  
+    --
+    gen_stretchVals: for v_inputNumber in 0 to g_NUM_INPUTS-1 generate
+        cmp_stretchPulse: entity work.stretchPulse
+        generic map (
+            g_PARAM_WIDTH => c_PARAM_WIDTH)
+        port map (
+            clk_i         => clk_4x_logic_i,
+            pulse_i       => trigger_i(v_inputNumber),
+            pulse_o       => s_stretchedTriggers(v_inputNumber),
+            triggerTime_i => trigger_times_i(v_inputNumber),
+            triggerTime_o => s_delayedTriggerTimes(v_inputNumber),
+    --        pulsewidth_i  => s_PulseStretchWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulsewidth_i  => s_PulseWidthWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulseDelay_i  => s_PulseDelayWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH )
+    --        pulsewidth_i  => s_PulseStretchWord( (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH ),
+    --        pulseDelay_i  => s_PulseDelayWord(   (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH )
+            );
+    end generate gen_stretchVals;
+
+  --! Trigger coincidence logic 
+    cmp_coincidence_logic : entity work.coincidenceLogic
+    generic map(
+        g_nInputs	=> g_NUM_INPUTS,
+        g_patternWidth => g_IPBUS_WIDTH
+    )
+    Port map( 
+        configClk_i 	=> ipbus_clk_i, --! No point in moving off IPBus clock
+        logicClk_i        => clk_4x_logic_i,
+        triggers_i 	=> s_stretchedTriggers,
+        trigger_o         => s_external_trigger_l,
+        --auxTrigger_o      => s_auxTrigger,
+        -- Control ports...
+        triggerPattern_low_i  => s_TriggerPattern_low,
+        triggerPattern_high_i  => s_TriggerPattern_high,
+        loadPatternHi_i     => s_loadTriggerPatternHi,
+        loadPatternLo_i     => s_loadTriggerPattern
+        );
+	
+  --! just look for the rising edge ( with long stretch can get multiple clock
+  --! cycle triggers )
+    cmp_triggerRisingEdge : entity work.single_pulse
+    port map (
+        level => s_external_trigger_l,
+        clk => clk_4x_logic_i,
+        pulse => s_external_trigger_p
+        );
+  
+  --! Produce triggers....
+    trigGen : process  ( clk_4x_logic_i ) 
+    begin 
+        if rising_edge(clk_4x_logic_i)  then 
+            s_post_veto_trigger <= (s_external_trigger_p or s_internal_trigger) and (not ( s_internal_veto or veto_i) );
+            s_pre_veto_trigger <= (s_external_trigger_p or s_internal_trigger);
+    
+            -- delay output of which input triggers fired so that they go high at the
+            -- same time as the pre/post veto trigger signals.
+            s_stretchedTriggers_d1 <= s_stretchedTriggers;
+            s_stretchedTriggers_d2 <= s_stretchedTriggers_d1;
+                                                            
+            s_delayedTriggerTimes_d1 <= s_delayedTriggerTimes;
+            s_delayedTriggerTimes_d2 <= s_delayedTriggerTimes_d1;
+             
+            trigger_o <= s_stretchedTriggers_d2;
+            trigger_times_o <= s_delayedTriggerTimes_d2; -- trigger_times_i;  -- put delayed version of trigger times here
+        end if;
+    end process;
+	
+
+    pre_veto_trigger_o <= s_pre_veto_trigger ;
+    post_veto_trigger_o <= s_post_veto_trigger;
+    trigger_active_o <= s_post_veto_trigger;
+
+	
+	--! Internal trigger generator
+    p_internal_triggers: process (clk_4x_logic_i )
+    begin  -- process p_internal_triggers
+        if rising_edge(clk_4x_logic_i) then
+            if (s_internal_trigger_interval = x"00000000") then
+                s_internal_trigger_active <= '0';
+            else
+                s_internal_trigger_active <= '1';
+            end if;
+        
+            s_internal_trigger_active_d <= s_internal_trigger_active;    -- signal delayed
+            s_internal_trigger_timer_d <= s_internal_trigger_timer;      -- Signal delayed
+        end if;
+    end process p_internal_triggers;
+  
+    s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" )) else '0';
+				
+				
+				
+    -- Use a coregen counter to allow timing constraints to be met.
+    --c_internal_triggers: entity work.internalTriggerGenerator
+    c_internal_triggers: internalTriggerGenerator
+    PORT MAP (
+        clk => clk_4x_logic_i,
+        ce => s_internal_trigger_active,
+        load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
+        l => s_internal_trigger_interval,
+        q => s_internal_trigger_timer
+    );
+  
+  -----------------------------------------------------------------------------
+  -- Count triggers
+  -----------------------------------------------------------------------------
+    p_trigger_counter: process (clk_4x_logic_i )
+    begin  -- process p_trigger_counter
+        if rising_edge(clk_4x_logic_i) then
+            if logic_reset_i = '1' then
+                s_post_veto_trigger_counter <= ( others => '0');
+            elsif s_post_veto_trigger = '1' then
+                s_post_veto_trigger_counter <= s_post_veto_trigger_counter + 1;
+            end if;
+            
+            if logic_reset_i = '1' then
+                s_pre_veto_trigger_counter <= ( others => '0');
+            elsif s_pre_veto_trigger = '1' then
+                s_pre_veto_trigger_counter <= s_pre_veto_trigger_counter + 1;
+            end if;
+            
+            --if logic_reset_i = '1' then
+            --    s_aux_trigger_counter <= ( others => '0');
+            --elsif s_auxTrigger = '1' then
+            --    s_aux_trigger_counter <= s_aux_trigger_counter + 1;
+            --end if;
+        end if;
+    end process p_trigger_counter;
+ 
+    event_number_o <= std_logic_vector(s_post_veto_trigger_counter);
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/constraints/EUDET_dummy_constr.xdc b/AIDA_tlu/legacy/EUDETdummy/constraints/EUDET_dummy_constr.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..c39287f54b2f7e45d248f82776062196ba218cdf
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/constraints/EUDET_dummy_constr.xdc
@@ -0,0 +1,108 @@
+## Trigger inputs
+
+#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
+#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports {threshold_discr_n_i[*]}]
+#set property IOSTANDARD LVDS_25 [get_ports {threshold_discr_p_i[*]}]
+#set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
+#set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
+#set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
+#set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
+#set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
+#set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
+#set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
+#set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
+#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+#set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
+#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+#set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
+
+## Miscellaneous I/O
+set_property IOSTANDARD LVCMOS33 [get_ports clk_gen_rst]
+set_property PACKAGE_PIN C1 [get_ports clk_gen_rst]
+set_property IOSTANDARD LVCMOS33 [get_ports gpio]
+set_property PACKAGE_PIN F6 [get_ports gpio]
+
+
+## Crystal clock
+set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
+set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
+set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
+
+## Output clock (currently not working so set to 0)
+set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_p]
+set_property PACKAGE_PIN E3 [get_ports sysclk_50_o_p]
+set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_n]
+set_property PACKAGE_PIN D3 [get_ports sysclk_50_o_n]
+
+## Inputs/Outputs for DUTs
+set_property IOSTANDARD LVCMOS33 [get_ports {busy_o[*]}]
+set_property PACKAGE_PIN R7 [get_ports {busy_o[0]}]
+set_property PACKAGE_PIN U4 [get_ports {busy_o[1]}]
+set_property PACKAGE_PIN R8 [get_ports {busy_o[2]}]
+set_property PACKAGE_PIN K5 [get_ports {busy_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {triggers_o[*]}]
+set_property PACKAGE_PIN R6 [get_ports {triggers_o[0]}]
+set_property PACKAGE_PIN P2 [get_ports {triggers_o[1]}]
+set_property PACKAGE_PIN R1 [get_ports {triggers_o[2]}]
+set_property PACKAGE_PIN U1 [get_ports {triggers_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {cont_o[*]}]
+set_property PACKAGE_PIN N5 [get_ports {cont_o[0]}]
+set_property PACKAGE_PIN P4 [get_ports {cont_o[1]}]
+set_property PACKAGE_PIN M6 [get_ports {cont_o[2]}]
+set_property PACKAGE_PIN L6 [get_ports {cont_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {spare_o[*]}]
+set_property PACKAGE_PIN L1 [get_ports {spare_o[0]}]
+set_property PACKAGE_PIN M4 [get_ports {spare_o[1]}]
+set_property PACKAGE_PIN N2 [get_ports {spare_o[2]}]
+set_property PACKAGE_PIN M3 [get_ports {spare_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dut_clk_o[*]}]
+set_property PACKAGE_PIN K3 [get_ports {dut_clk_o[0]}]
+set_property PACKAGE_PIN F4 [get_ports {dut_clk_o[1]}]
+set_property PACKAGE_PIN E2 [get_ports {dut_clk_o[2]}]
+set_property PACKAGE_PIN G4 [get_ports {dut_clk_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {cont_i[*]}]
+set_property PACKAGE_PIN P5 [get_ports {cont_i[0]}]
+set_property PACKAGE_PIN P3 [get_ports {cont_i[1]}]
+set_property PACKAGE_PIN N6 [get_ports {cont_i[2]}]
+set_property PACKAGE_PIN L5 [get_ports {cont_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {spare_i[*]}]
+set_property PACKAGE_PIN M1 [get_ports {spare_i[0]}]
+set_property PACKAGE_PIN N4 [get_ports {spare_i[1]}]
+set_property PACKAGE_PIN N1 [get_ports {spare_i[2]}]
+set_property PACKAGE_PIN M2 [get_ports {spare_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {triggers_i[*]}]
+set_property PACKAGE_PIN R5 [get_ports {triggers_i[0]}]
+set_property PACKAGE_PIN R2 [get_ports {triggers_i[1]}]
+set_property PACKAGE_PIN T1 [get_ports {triggers_i[2]}]
+set_property PACKAGE_PIN V1 [get_ports {triggers_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {busy_i[*]}]
+set_property PACKAGE_PIN T6 [get_ports {busy_i[0]}]
+set_property PACKAGE_PIN U3 [get_ports {busy_i[1]}]
+set_property PACKAGE_PIN T8 [get_ports {busy_i[2]}]
+set_property PACKAGE_PIN L4 [get_ports {busy_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dut_clk_i[*]}]
+set_property PACKAGE_PIN L3 [get_ports {dut_clk_i[0]}]
+set_property PACKAGE_PIN F3 [get_ports {dut_clk_i[1]}]
+set_property PACKAGE_PIN D2 [get_ports {dut_clk_i[2]}]
+set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
+
+# -------------------------------------------------------------------------------------------------
+
+
+
+
+
+
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
diff --git a/AIDA_tlu/legacy/EUDETdummy/constraints/I2C_constr.xdc b/AIDA_tlu/legacy/EUDETdummy/constraints/I2C_constr.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..eb95fff53000585503d44895d922a06c144ba71b
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/constraints/I2C_constr.xdc
@@ -0,0 +1,40 @@
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_reset]
+set_property PACKAGE_PIN C2 [get_ports i2c_reset]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
+set_property PACKAGE_PIN N17 [get_ports i2c_scl_b]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
+set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
+
+
+
+create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
+#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d4_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d3_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d0_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d1_reg]
+
+#set_clock_groups -asynchronous -group [get_clocks pll_base_inst_n_2] -group [get_clocks mmcm_n_8]
+#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d3_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_ipbus/s_ring_d4_reg]
+#set_property ASYNC_REG true [get_cells I6/s_logic_reset_d1_reg]
+#set_property ASYNC_REG true [get_cells I6/s_logic_reset_d2_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d1_reg]
+#set_property ASYNC_REG true [get_cells I1/sync_registers/s_ring_d0_reg]
+#set_clock_groups -asynchronous -group [get_clocks mmcm_n_8] -group [get_clocks pll_base_inst_n_2]
+
+
+#Define clock groups and make them asynchronous with each other
+set_clock_groups -asynchronous -group {clk_enclustra I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p I pll_base_inst_n_2 s_clk160}
+
+# -------------------------------------------------------------------------------------------------
+
+
+
+#DEBUG PROBES
+
+
+
+
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/constraints/enclustra_ax3_pm3.tcl b/AIDA_tlu/legacy/EUDETdummy/constraints/enclustra_ax3_pm3.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7fd31b4cc9f873d26b03c33f5f534ba0b2a19aad
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/constraints/enclustra_ax3_pm3.tcl
@@ -0,0 +1,52 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+proc false_path {patt clk} {
+    set p [get_ports -quiet $patt -filter {direction != out}]
+    if {[llength $p] != 0} {
+        set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
+        set_false_path -from [get_ports $patt -filter {direction != out}]
+    }
+    set p [get_ports -quiet $patt -filter {direction != in}]
+    if {[llength $p] != 0} {
+       	set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
+	    set_false_path -to [get_ports $patt -filter {direction != in}]
+	}
+}
+
+# System clock (50MHz)
+#create_clock -period 25.000 -name sysclk [get_ports sysclk] 
+create_clock -period 20.000 -name clk_enclustra [get_ports clk_enclustra]
+
+set_false_path -through [get_pins infra/clocks/rst_reg/Q]
+set_false_path -through [get_nets infra/clocks/nuke_i]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk_enclustra]
+set_property PACKAGE_PIN P17 [get_ports clk_enclustra]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
+set_property SLEW SLOW [get_ports {leds[*]}]
+set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
+set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
+set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
+set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
+false_path {leds[*]} clk_enclustra
+
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_* phy_rstn}]
+set_property PACKAGE_PIN R18 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN T18 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports {rgmii_tx_ctl}]
+set_property PACKAGE_PIN N16 [get_ports {rgmii_txc}]
+set_property PACKAGE_PIN U16 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN V17 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN V15 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
+set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
+set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
+false_path {phy_rstn} clk_enclustra
+
+# -------------------------------------------------------------------------------------------------
+
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..898b575886164be173a281a951d9269e638f6130
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT.vhd
@@ -0,0 +1,235 @@
+----------------------------------------------------------------------------------
+--! @file
+--
+-- Company: University of Bristol 
+-- Engineer: David Cussans
+-- 
+-- Create Date:    16:28:09 07/07/2006 
+-- Design Name: 
+-- Module Name:    Dummy_DUT - RTL 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+--! @brief Pretends to be a device under test
+--
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+-- constant definitions.
+
+
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Dummy_DUT is
+    Port ( 
+           CLK : in  STD_LOGIC;         --! this is the USB clock.
+	   RST : in STD_LOGIC;          --! Synchronous clock
+           Trigger : in STD_LOGIC;      --! Trigger from TLU
+           Busy : out STD_LOGIC;        --! Busy to TLU
+           DUTClk : out STD_LOGIC;      --! clock from DUT
+           TriggerNumber : out STD_LOGIC_VECTOR(15 downto 0);
+           TriggerNumberStrobe : out STD_LOGIC;
+           FSM_Error : out STD_LOGIC
+           );
+
+end entity Dummy_DUT;
+
+architecture RTL of Dummy_DUT is
+
+  component delay is
+    generic (
+      length : integer := 1);  -- number of clock cycles to delay signal
+    port (
+      clock  : in  std_logic;             -- rising edge active
+      input  : in  std_logic;
+      output : out std_logic);
+  end component;
+    
+  -----------------------------------------------------------------------------
+
+  signal Registered_Trigger , Registered_RST : std_logic;     -- trigger and reset signals after being registered to suppress meta-stability.
+  
+  signal TriggerShiftRegister : STD_LOGIC_VECTOR (15 downto 0);  --! register
+                                                                 --to accept
+                                                                 --incoming
+                                                                 --trigger number
+
+  type state_type is (IDLE , WAIT_FOR_TRIGGER_LOW , CLOCKING , OUTPUT_TRIGGER_NUMBER);
+  signal state : state_type := IDLE;
+  signal next_state : state_type := IDLE;
+
+  signal TriggerBitCounter : unsigned(4 downto 0) := ( others => '0');  --! stores bit being clocked
+                                                         --in from TLU.
+  signal InternalDUTClk : std_logic := '0';  -- ! "can't read an output" bodge
+  
+  constant DUTClockDivider : unsigned(3 downto 0) := to_unsigned(14,4);
+  	
+  constant TriggerBitCounterLimit : unsigned(4 downto 0) :=  to_unsigned(16,5);
+
+  signal DUTClockCounter : unsigned(4 downto 0) := ( others => '0');
+
+begin
+
+  trigger_register: delay
+    generic map (
+      length => 2)
+    port map (
+      clock  => clk,
+      input  => Trigger,
+      output => Registered_Trigger);
+
+  reset_register: delay
+    generic map (
+      length => 2)
+    port map (
+      clock  => clk,
+      input  => RST,
+      output => Registered_RST);
+  
+  
+  busy_control: process (clk , state)
+  begin  -- process busy_control
+    if rising_edge(clk) then
+      if state = IDLE then
+        busy <= '0';
+      else
+        busy <= '1';
+      end if;
+    end if;
+  end process busy_control;
+
+  clock_control: process (clk , state , TriggerBitCounter )
+  begin  -- process busy_control
+    if rising_edge(clk) then
+      if state = CLOCKING then
+        if (InternalDUTClk = '0') and (DUTClockCounter = DUTClockDivider)  then
+          TriggerBitCounter <= TriggerBitCounter +1;
+        else
+          TriggerBitCounter <= TriggerBitCounter;
+        end if;
+      else
+        TriggerBitCounter <= ( others => '0');
+      end if;
+    end if;
+  end process clock_control;
+
+
+  InternalDUTClk_control: process (clk , state , InternalDUTClk)
+  begin  -- process busy_control
+    if rising_edge(clk) then
+      if state = CLOCKING  then
+        if DUTClockCounter = DUTClockDivider then
+        	InternalDUTClk <= not InternalDUTClk ;
+        	DUTClockCounter <= ( others => '0');
+        else
+            DUTClockCounter <= DUTClockCounter + 1;
+        end if;
+      else
+        InternalDUTClk <= '0';
+        DUTClockCounter <= ( others => '0');
+      end if;
+    end if;
+  end process InternalDUTClk_control;
+
+  shift_register_control: process (clk , state , TriggerShiftRegister)
+  begin  -- process shift_register_control
+    if rising_edge(clk) then
+      if  state = IDLE then
+        TriggerShiftRegister <= ( others => '0');
+      elsif state = CLOCKING then
+        if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,4 ))  then
+          -- if (InternalDUTClk = '1') and (DUTClockCounter=to_unsigned(1,DUTClockCounter'length ))  then
+          TriggerShiftRegister <= trigger & TriggerShiftRegister( 15 downto 1) ;
+          -- TriggerShiftRegister <= trigger & TriggerShiftRegister( TriggerShiftRegister'high downto 1) ;
+        else
+          TriggerShiftRegister <= TriggerShiftRegister;
+        end if;
+      end if;
+    end if;
+  end process shift_register_control;
+
+  strobe_control: process (clk , state )
+  begin  -- process stobe_control
+    if rising_edge(clk) then
+      if state = OUTPUT_TRIGGER_NUMBER then
+        TriggerNumber <= TriggerShiftRegister;
+        TriggerNumberStrobe <= '1';
+      else
+        TriggerNumberStrobe  <= '0';
+      end if;
+    end if;
+  end process strobe_control;
+  
+--! @brief controls the next state in the state machine
+-- type   : combinational
+-- inputs : pattern_we, mask_we , beam_state_counter
+-- outputs: state , beam_state_counter
+  state_logic: process (state, TriggerBitCounter , registered_trigger ,InternalDUTClk  )
+  begin  -- process state_logic
+    case state is
+	 
+      when IDLE =>
+        if ( registered_trigger = '1') then
+          next_state <= WAIT_FOR_TRIGGER_LOW;
+        else
+          next_state <= IDLE;
+         end if;
+
+      when WAIT_FOR_TRIGGER_LOW =>
+        if ( registered_trigger = '0'  ) then
+          next_state <= CLOCKING;
+        else
+          next_state <= WAIT_FOR_TRIGGER_LOW;
+        end if;
+
+      when CLOCKING =>
+        if (( TriggerBitCounter = TriggerBitCounterLimit ) and ( InternalDUTClk = '0')) then
+          next_state <= OUTPUT_TRIGGER_NUMBER;
+        else
+          next_state <= CLOCKING;
+        end if;
+
+      when  OUTPUT_TRIGGER_NUMBER =>
+         next_state <= IDLE;
+               
+      when others =>
+        next_state <= IDLE;
+        
+    end case;
+  end process state_logic;
+  
+  --! @brief Register that holds the current state of the FSM
+  -- type   : combinational
+  -- inputs : clk , next_state
+  -- outputs: state
+  state_register: process (clk )
+  begin  -- process state_register
+    if rising_edge(clk) then
+      if (registered_rst = '1') then
+        state <= IDLE;
+      else
+        state <= next_state;          
+      end if;
+    end if;
+  end process state_register;
+
+  DUTClk <= InternalDUTClk;
+
+  fsm_error <= '0';                     -- hardware to zero.
+  
+end RTL;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT_Toplevel.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT_Toplevel.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..9116dc5ad8aae6bc7ca25c364ce4b78284866c7f
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/Dummy_DUT_Toplevel.vhd
@@ -0,0 +1,627 @@
+-------------------------------------------------------------------------------
+--! @file
+--! @brief Top level of firmware for dummy JRA1-TLU
+-------------------------------------------------------------------------------
+-- File name: Dummy_DUT_Toplevel.vhd
+-- Version: 0.1
+-- Date: 20/Oct/2009
+-- David Cussans
+--
+-- Changes
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+use IEEE.NUMERIC_STD.all;
+
+--! Use library for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.vcomponents.all;
+
+--! include definition of TLU address map
+use work.TLU_Address_Map_v02.all;
+
+--! Top level with all the hardware ports.
+entity Dummy_DUT_Toplevel is
+  port (
+    USB_StreamCLK      : in    std_logic;  --! 48MHz clock from FX2
+    USB_StreamFIFOADDR : out   std_logic_vector(1 downto 0);
+    USB_StreamPKTEND_n : out   std_logic;
+    USB_StreamFlags_n  : in    std_logic_vector(2 downto 0);
+    USB_StreamSLOE_n   : out   std_logic;
+    USB_StreamSLRD_n   : out   std_logic;
+    USB_StreamSLWR_n   : out   std_logic;
+    USB_StreamData     : inout std_logic_vector(15 downto 0);
+    USB_StreamFX2Rdy   : in    std_logic;
+
+    USB_RegCLK  : in    std_logic; --! 48MHz clock from FX2
+    USB_RegAddr : in    std_logic_vector(15 downto 0);
+    USB_RegData : inout std_logic_vector(7 downto 0);
+    USB_RegOE_n : in    std_logic;
+    USB_RegRD_n : in    std_logic;
+    USB_RegWR_n : in    std_logic;
+    USB_RegCS_n : in    std_logic;
+
+    USB_Interrupt : out std_logic;
+
+    User_Signals : inout std_logic_vector(7 downto 0);
+
+    S_CLK      : out   std_logic;
+    S_A        : out   std_logic_vector(22 downto 0);
+    S_DA       : inout std_logic_vector(8 downto 0);
+    S_DB       : inout std_logic_vector(8 downto 0);
+    S_ADV_LD_N : out   std_logic;
+    S_BWA_N    : out   std_logic;
+    S_BWB_N    : out   std_logic;
+    S_OE_N     : out   std_logic;
+    S_WE_N     : out   std_logic;
+
+    IO_CLK_N : inout std_logic;         --! Posive side of differential user clock
+    IO_CLK_P : inout std_logic;         --! Posive side of differential user clock
+    IO       : inout std_logic_vector(46 downto 0)  --! The 47 I/O pins
+    );
+end Dummy_DUT_Toplevel;
+
+architecture arch of Dummy_DUT_Toplevel is
+	
+  --! Declare interfaces component
+  component ZestSC1_Interfaces
+    port (
+      --! FPGA pin connections
+      USB_StreamCLK      : in    std_logic;
+      USB_StreamFIFOADDR : out   std_logic_vector(1 downto 0);
+      USB_StreamPKTEND_n : out   std_logic;
+      USB_StreamFlags_n  : in    std_logic_vector(2 downto 0);
+      USB_StreamSLOE_n   : out   std_logic;
+      USB_StreamSLRD_n   : out   std_logic;
+      USB_StreamSLWR_n   : out   std_logic;
+      USB_StreamData     : inout std_logic_vector(15 downto 0);
+      USB_StreamFX2Rdy   : in    std_logic;
+
+      USB_RegCLK  : in    std_logic;
+      USB_RegAddr : in    std_logic_vector(15 downto 0);
+      USB_RegData : inout std_logic_vector(7 downto 0);
+      USB_RegOE_n : in    std_logic;
+      USB_RegRD_n : in    std_logic;
+      USB_RegWR_n : in    std_logic;
+      USB_RegCS_n : in    std_logic;
+
+      USB_Interrupt : out std_logic;
+
+      S_CLK      : out   std_logic;
+      S_A        : out   std_logic_vector(22 downto 0);
+      S_ADV_LD_N : out   std_logic;
+      S_BWA_N    : out   std_logic;
+      S_BWB_N    : out   std_logic;
+      S_DA       : inout std_logic_vector(8 downto 0);
+      S_DB       : inout std_logic_vector(8 downto 0);
+      S_OE_N     : out   std_logic;
+      S_WE_N     : out   std_logic;
+
+      --! User connections
+      --! Streaming interface
+      User_CLK : out std_logic;
+      User_RST : out std_logic;
+
+      User_StreamBusGrantLength : in std_logic_vector(11 downto 0);
+
+      User_StreamDataIn     : out std_logic_vector(15 downto 0);
+      User_StreamDataInWE   : out std_logic;
+      User_StreamDataInBusy : in  std_logic;
+
+      User_StreamDataOut     : in  std_logic_vector(15 downto 0);
+      User_StreamDataOutWE   : in  std_logic;
+      User_StreamDataOutBusy : out std_logic;
+
+      --! Register interface
+      User_RegAddr    : out std_logic_vector(15 downto 0);
+      User_RegDataIn  : out std_logic_vector(7 downto 0);
+      User_RegDataOut : in  std_logic_vector(7 downto 0);
+      User_RegWE      : out std_logic;
+      User_RegRE      : out std_logic;
+
+      --! Signals and interrupts
+      User_Interrupt : in std_logic;
+
+      --! SRAM interface
+      User_SRAM_A        : in  std_logic_vector(22 downto 0);
+      User_SRAM_W        : in  std_logic;
+      User_SRAM_R        : in  std_logic;
+      User_SRAM_DR_VALID : out std_logic;
+      User_SRAM_DW       : in  std_logic_vector(17 downto 0);
+      User_SRAM_DR       : out std_logic_vector(17 downto 0)
+      );
+  end component;
+
+  component Register_Controller is
+
+                                  port (
+
+                                    --! Take clock from Zest interface block
+                                    User_CLK : in std_logic;
+
+                                    --! Register interface to USB
+                                    User_RegAddr    : in  std_logic_vector(15 downto 0);
+                                    User_RegDataIn  : in  std_logic_vector(7 downto 0);
+                                    User_RegDataOut : out std_logic_vector(7 downto 0);
+                                    User_RegWE      : in  std_logic;
+                                    User_RegRE      : in  std_logic;
+
+				    Logic_CLK : in std_logic;
+				    
+                                    --! Signals to trigger logic
+                                    DUT_Reset : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);  --separate bits for each DUT
+
+                                    DUT_Trigger : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                    DUT_Debug_Trigger : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                    DUT_Busy : in std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state of DUT
+                                    DUT_Clock_Debug :  in std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state of
+                                                                                                       -- DUT_CLOCK
+
+    				    I2C_Select : out std_logic_vector(WIDTH_OF_I2C_SELECT_PORT-1 downto 0); -- output to mux/demux that selects I2C ports
+
+    				    I2C_SCL_OUT : out std_logic; -- drives SCL
+    				    I2C_SCL_IN : in std_logic; -- state of SCL
+
+    				    I2C_SDA_OUT : out std_logic; -- drives SDA
+    				    I2C_SDA_IN : in std_logic; -- state of SDA
+
+                                    -- Mask for beam trigger inputs. 
+                                    Beam_Trigger_AMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+                                    Beam_Trigger_OMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+                                    Beam_Trigger_VMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+                                    
+                                    Trigger_pattern      : out  std_logic_vector (15 downto 0);
+                                    Aux_pattern          : out  std_logic_vector (15 downto 0);
+    
+                                    Beam_Trigger_Mask_WE : out std_logic;
+                                    Beam_Trigger_Pattern_WE : out std_logic;
+    
+                                    --Beam trigger input for debugging.
+                                    beam_trigger_in : in std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+                                    calibration_trigger_interval : out std_logic_vector(7 downto 0);
+                                    -- send trigger to, and receive busy from only certain DUT....
+                                    DUT_Mask    : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                    enable_DUT_veto : out std_logic_vector(NUMBER_OF_DUT-1 downto 0); --
+                                    --! controls if a DUT can halt triggers by
+                                    --! raising DUT_CLK line.
+                                    DUT_Mask_WE : out std_logic;
+
+                                    -- because of 8-bit interface trigger a read of whole timestamp and then
+                                    -- read each byte separately
+                                    Timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
+
+                                    Trigger_Counter : in std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);
+                                    Particle_Counter : in std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);  -- fsv
+                                    Auxiliary_Counter : in std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);
+                                    Trigger_Scalers : in TRIGGER_SCALER_ARRAY;
+                                    Buffer_Pointer  : in std_logic_vector(BUFFER_COUNTER_WIDTH-1 downto 0);
+
+                                    Trigger_Output_FSM_Status : in std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                    Trigger_FSM_State_Value : in std_logic_vector(( (NUMBER_OF_DUT*4)-1) downto 0);
+                                    beam_trigger_fsm_status : in std_logic_vector(2 downto 0);
+                                    DMA_Status : in std_logic;
+                                    Host_Trig_Inhibit     : out std_logic;
+                                    Trig_Enable_Status    : in  std_logic;  -- this is the overall status of the TLU ( incl. vetos from DUT)
+                                    Clock_Source_Select   : out std_logic;
+                                    Clock_DCM_Locked      : in std_logic;
+                                    Reset_Timestamp       : out std_logic;
+                                    Reset_Buffer_Pointer  : out std_logic;
+                                    Reset_DMA_Controller  : out std_logic;
+                                    Reset_ClockGen        : out std_logic;
+                                    Initiate_Readout      : out std_logic;
+                                    Reset_Trigger_Counter : out std_logic;
+				    Reset_Trigger_Scalers : out std_logic;
+                                    Reset_Trigger_Output_FSM : out std_logic;
+                                    Reset_Beam_Trigger_FSM : out std_logic;
+                                    Stop_if_Timestamp_Buffer_Full : out std_logic;
+                                    strobe_width        : out std_logic_vector(STROBE_COUNTER_WIDTH-1 downto 0);
+                                    strobe_period        : out std_logic_vector(STROBE_COUNTER_WIDTH-1 downto 0);
+                                    write_strobe_data   : out std_logic;
+                                    enable_strobe       : out std_logic;
+                                    strobe_running      : in std_logic;
+				    Write_Trigger_Bits_Mode : out std_logic;
+                                    Trigger_Handshake_Mode : out std_logic_vector(NUMBER_OF_DUT-1 downto 0)
+                                    );
+  end component;
+
+  -----------------------------------------------------------------------------
+  
+  component Dummy_DUT 
+    Port ( 
+           CLK : in  STD_LOGIC;         --! this is the USB clock.
+	   RST : in STD_LOGIC;          --! Synchronous clock
+           Trigger : in STD_LOGIC;      --! Trigger from TLU
+           Busy : out STD_LOGIC;        --! Busy to TLU
+           DUTClk : out STD_LOGIC;      --! clock from DUT
+           TriggerNumber : out STD_LOGIC_VECTOR(15 downto 0);
+           TriggerNumberStrobe : out STD_LOGIC;
+           FSM_Error : out STD_LOGIC
+           );
+  end component;
+      
+  -----------------------------------------------------------------------------
+
+  component Trigger_Number_Error_Checker is
+    Port ( 
+           CLK : in  STD_LOGIC;         --! this is the USB clock.
+	   RST : in STD_LOGIC;          --! Synchronous with clock
+           TriggerNumber : in STD_LOGIC_VECTOR(15 downto 0);  --! should
+                                                              --incremeent from
+                                                              --0
+           TriggerNumberStrobe : in STD_LOGIC;  --! Active high
+           TriggerCounter : out  STD_LOGIC_VECTOR(15 downto 0);  --!internal counter
+           ErrorFlag : out STD_LOGIC    --! goes high if internal number
+                                        --doesn't match
+           );
+end component;
+
+  -----------------------------------------------------------------------------
+
+  -- declaration of chipscope core ....
+  
+  component dummy_dut_chipscope_ila
+  PORT (
+    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
+    CLK : IN STD_LOGIC;
+    TRIG0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    TRIG1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    TRIG2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
+  end component;
+
+  component dummy_dut_chipscope_icon
+  PORT (
+    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
+  end component;
+
+  -- Chipscope signals
+  signal CONTROL : STD_LOGIC_VECTOR(35 DOWNTO 0);
+  signal TRIG0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  signal TRIG1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  signal TRIG2 : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  
+
+  -----------------------------------------------------------------------------
+
+  
+  -- Declare signals
+  signal CLK  : std_logic;
+  signal RST  : std_logic;
+
+  -- Register interface
+  signal Addr    : std_logic_vector(15 downto 0);
+  signal DataIn  : std_logic_vector(7 downto 0);
+  signal DataOut : std_logic_vector(7 downto 0);
+  signal WE      : std_logic;
+  signal RE      : std_logic;
+
+  -- signals associated with streaming interface.
+  signal Host_Data    : std_logic_vector(15 downto 0);
+  signal Host_Data_WE : std_logic;
+  signal Host_Busy    : std_logic;
+  
+  -- Interrupt signal
+  -- not used in this design
+  signal Interrupt : std_logic;
+
+
+  -- Signals associated with DUT
+  signal DUT_Reset        : std_logic_vector(NUMBER_OF_DUT-1 downto 0);  --separate bits for each DUT
+  signal DUT_Busy : std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state of DUT
+  signal DUT_Clock :  std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state of DUT_CLK
+  signal DUT_Trigger :  std_logic_vector(NUMBER_OF_DUT-1 downto 0);  --
+
+  subtype TriggerNumberType is std_logic_vector(15 downto 0);
+  type TriggerNumberArray is array (NUMBER_OF_DUT-1 downto 0) of TriggerNumberType;
+  signal TriggerNumber : TriggerNumberArray;  -- trigger number clocked out from TLU
+
+  signal TriggerCounter : TriggerNumberArray;  -- trigger number inside
+                                                 -- error checker
+  
+  signal TriggerNumberStrobe : std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- strobes high
+
+  signal ErrorFlag : std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- strobes high
+
+  -- I2C signals
+  signal I2C_Select : std_logic_vector(WIDTH_OF_I2C_SELECT_PORT-1 downto 0); 
+  signal I2C_SDA_OUT :std_logic; 
+  signal I2C_SCL_OUT :std_logic; 
+  signal I2C_SDA_IN  :std_logic; 
+  signal I2C_SCL_IN  :std_logic; 
+  
+  signal trigger_scalers : TRIGGER_SCALER_ARRAY;  -- array of 16 bit registers
+  
+-- a bodge, since I can't figure out how to make it work with aggregates.
+  -- declare a constant for the unused IO => .
+  constant unused_io : std_logic_vector(7 downto 0) := "ZZZZZZZZ" ;
+
+  for all : zestsc1_interfaces use entity work.zestsc1_interfaces(arch);
+
+-----------------------------------------------------------------------
+-- end of declarations start of instantiation
+-----------------------------------------------------------------------
+
+begin
+
+
+
+  -- let unused IO float for now 
+  (  IO(7) , IO(10) , IO(19) , IO(24) ,
+     IO(33) , IO(39) , IO(40) , IO(45) ) <= unused_io;
+  
+    -- Instantiate interfaces component
+  Interfaces : ZestSC1_Interfaces
+    port map (
+      USB_StreamCLK      => USB_StreamCLK,
+      USB_StreamFIFOADDR => USB_StreamFIFOADDR,
+      USB_StreamPKTEND_n => USB_StreamPKTEND_n,
+      USB_StreamFlags_n  => USB_StreamFlags_n,
+      USB_StreamSLOE_n   => USB_StreamSLOE_n,
+      USB_StreamSLRD_n   => USB_StreamSLRD_n,
+      USB_StreamSLWR_n   => USB_StreamSLWR_n,
+      USB_StreamData     => USB_StreamData,
+      USB_StreamFX2Rdy   => USB_StreamFX2Rdy,
+
+      USB_RegCLK  => USB_RegCLK,
+      USB_RegAddr => USB_RegAddr,
+      USB_RegData => USB_RegData,
+      USB_RegOE_n => USB_RegOE_n,
+      USB_RegRD_n => USB_RegRD_n,
+      USB_RegWR_n => USB_RegWR_n,
+      USB_RegCS_n => USB_RegCS_n,
+
+      USB_Interrupt => USB_Interrupt,
+
+      S_CLK      => S_CLK,
+      S_A        => S_A,
+      S_ADV_LD_N => S_ADV_LD_N,
+      S_BWA_N    => S_BWA_N,
+      S_BWB_N    => S_BWB_N,
+      S_DA       => S_DA,
+      S_DB       => S_DB,
+      S_OE_N     => S_OE_N,
+      S_WE_N     => S_WE_N,
+
+      -- User connections
+      -- Streaming interface
+      User_CLK => CLK,
+      -- bodge for simulation
+      -- User_CLK => open,
+      User_RST => RST,
+
+      User_StreamBusGrantLength => "100000000000",  --! In clock cycles.
+--      User_StreamBusGrantLength => X"100",  -- In clock cycles. Clutching at
+--                                           --straws, make this the same as
+--                                           --Example2.vhd ( i.e. 256 cycles not
+--                                           --2048 )
+--
+      User_StreamDataIn     => open,
+      User_StreamDataInWE   => open,
+      User_StreamDataInBusy => '1',
+
+      User_StreamDataOut     => Host_Data,
+      User_StreamDataOutWE   => Host_Data_WE,
+      User_StreamDataOutBusy => Host_Busy,
+
+      -- Register interface
+      User_RegAddr    => Addr,
+      User_RegDataIn  => DataIn,
+      User_RegDataOut => DataOut,
+      User_RegWE      => WE,
+      User_RegRE      => RE,
+
+      -- Interrupts
+      User_Interrupt => Interrupt,
+
+      -- SRAM interface
+      User_SRAM_A        => "00000000000000000000000",
+      User_SRAM_W        => '0',
+      User_SRAM_R        => '0',
+      User_SRAM_DR_VALID => open,
+      User_SRAM_DW       => "000000000000000000",
+      User_SRAM_DR       => open
+      );
+
+
+    reg_ctrl : Register_Controller
+    port map (
+
+      -- Take clock from Zest interface block
+      User_CLK => clk,
+
+      -- Register interface
+      User_RegAddr    => Addr,
+      User_RegDataIn  => DataIn,
+      User_RegDataOut => DataOut,
+      User_RegWE      => WE,
+      User_RegRE      => RE,
+
+      Logic_CLK => clk,
+      
+      -- Signals to trigger logic
+--      DUT_Reset => ,           --separate bits for each DUT
+
+--      DUT_Trigger => Host_DUT_Trigger,
+
+--      DUT_Debug_Trigger => Host_DUT_Debug_Trigger , 
+      DUT_Busy => DUT_Busy,             -- actual state of DUT
+      DUT_Clock_Debug => DUT_Clock,
+
+      I2C_Select  => I2C_Select ,
+      I2C_SCL_OUT => I2C_SCL_OUT ,
+      I2C_SCL_IN  => I2C_SCL_IN ,
+      I2C_SDA_OUT => I2C_SDA_OUT,
+      I2C_SDA_IN  => I2C_SDA_IN ,
+  
+      -- Mask for beam trigger inputs. 
+--      Beam_Trigger_AMask   => open,
+--      Beam_Trigger_OMask   => open,
+--      Beam_Trigger_VMask   => open,
+--      Beam_Trigger_Mask_WE => open,
+      
+      				    
+--      Trigger_pattern	=> open,
+--      Aux_pattern	=> open,
+--      Beam_Trigger_Pattern_WE	=> beam_trigger_pattern_we,
+
+
+      --Beam trigger input for debugging.
+      beam_trigger_in => ( others => '0'),
+
+--      calibration_trigger_interval => Calibration_Trigger_Interval,
+      
+      -- send trigger to, and receive busy from only certain DUT....
+--      DUT_Mask    => DUT_Mask,
+--      DUT_Mask_WE => DUT_MAsk_WE,
+
+      -- because of 8-bit interface trigger a read of whole timestamp and then
+      -- read each byte separately
+      Timestamp => ( others => '0'),
+
+      Trigger_Counter => ( others => '0'),
+      Particle_Counter => ( others => '0'),   --  fsv
+      Auxiliary_Counter => ( others => '0'),                        
+      Trigger_Scalers => trigger_scalers,
+      
+      Buffer_Pointer  => ( others => '0'),
+
+      Trigger_Output_FSM_Status => ( others => '0'),
+      Trigger_FSM_State_Value => ( others => '0'),
+      beam_trigger_fsm_status => ( others => '0'),
+      DMA_Status => '0',
+--      Host_Trig_Inhibit  => host_veto,
+      Trig_Enable_Status => '0',
+      
+--      Clock_Source_Select => Clock_Source_Select,    
+      Clock_DCM_Locked => '0' , 
+---      Reset_Timestamp    => Reset_Timestamp,
+--      Reset_Buffer_Pointer => Reset_Buffer_Pointer,
+--      Reset_DMA_Controller => Reset_DMA_Controller,
+--      Reset_ClockGen => Reset_ClockGen ,
+--      Initiate_Readout => Initiate_Readout,
+--     Reset_Trigger_Counter => Reset_Trigger_Counter,
+--      Reset_Trigger_Scalers => Reset_Trigger_Scalers,
+--      Reset_Trigger_Output_FSM => trigger_fsm_reset,
+--      Reset_Beam_Trigger_FSM => beam_trigger_fsm_reset,
+--      Stop_if_Timestamp_Buffer_Full => stop_if_buffer_full,
+--      strobe_width   =>   strobe_width ,
+--      strobe_period  =>   strobe_period , 
+--      write_strobe_data   =>   write_strobe_data , 
+--      enable_strobe => enable_strobe , 
+      strobe_running => '0' 
+--      Write_Trigger_Bits_Mode => write_trigger_bits_mode,
+--      Trigger_Handshake_Mode => dut_trigger_handshake_mode
+      );
+
+-- bodge for simulation:
+--  clk <= usb_streamclk ;
+  
+----------------------------------------------
+-- Use a generate statement to generate the required number of
+-- trigger outputs.
+  Trigger_Outputs :
+  for DUT in 0 to NUMBER_OF_DUT-1 generate
+  begin
+  
+    -- connect up the input pins to the internal signals.
+    -- odd numbered inputs are inverted to reduce ground bounce in LVDS-->TTL converters
+    -- the odd-numbered outputs are inverted to reduce ground bounce.
+
+    -- Cross the TRIGGER-->BUSY and DUT_CLK-->Reset lines to allow connection
+    -- to TLU
+
+    -- Trigger and Reset are inputs to the Dummy DUT, but wired to BUSY and
+    -- CLOCK lines.
+    inverted_inputs: if ( (DUT=1) or (DUT=3) or (DUT=5) ) generate
+      DUT_Trigger(DUT) <= not IO(DUT_BUSY_BIT(DUT));
+      DUT_Reset(DUT)   <= not IO(DUT_CLOCK_BIT(DUT));
+    end generate inverted_inputs;
+    
+    noninverted_inputs: if ( (DUT=0) or (DUT=2) or (DUT=4) ) generate
+      DUT_Trigger(DUT) <= IO(DUT_BUSY_BIT(DUT));
+      DUT_Reset(DUT)   <= IO(DUT_CLOCK_BIT(DUT));
+    end generate noninverted_inputs;
+
+    ---------------------------------------------------------------------------
+    -- Busy and DUT_Clock are *outputs* from the Dummy DUT, but wired to
+    -- TRIGGER and RESET outputs.
+    inverted_outputs: if ( (DUT=1) or (DUT=3) or (DUT=5) ) generate
+      IO(TRIGGER_OUTPUT_BIT(DUT)) <= not DUT_Busy(DUT);
+      IO(DUT_RESET_BIT(DUT)) <= not DUT_Clock(DUT);
+    end generate inverted_outputs;
+
+    noninverted_outputs: if ( (DUT=0) or (DUT=2) or (DUT=4) ) generate
+      IO(TRIGGER_OUTPUT_BIT(DUT)) <= DUT_Busy(DUT);
+      IO(DUT_RESET_BIT(DUT)) <= DUT_Clock(DUT);
+    end generate noninverted_outputs;
+
+    -- generate an instance of the Dummy DUT behind each connector
+    DUT_Instance: Dummy_DUT 
+      Port map ( 
+           CLK => CLK,
+           RST => DUT_Reset(DUT),
+           Trigger => DUT_Trigger(DUT),
+           Busy => DUT_Busy(DUT),
+           DUTClk => DUT_Clock(DUT),
+           TriggerNumber => TriggerNumber(DUT),
+           TriggerNumberStrobe => TriggerNumberStrobe(DUT), 
+           FSM_Error => open
+           );
+
+    -- generate an instance of an error checker for each DUT
+    error_checker_instance :  Trigger_Number_Error_Checker 
+      Port map (
+        CLK => CLK,
+        RST => DUT_Reset(DUT),
+        TriggerNumber => TriggerNumber(DUT),
+        TriggerNumberStrobe => TriggerNumberStrobe(DUT),
+        TriggerCounter => TriggerCounter(DUT), 
+        ErrorFlag => ErrorFlag(DUT)
+        );
+      
+  end generate;
+
+  -- chipscope instrumentation
+  icon0 : dummy_dut_chipscope_icon
+  port map (
+    CONTROL0 => CONTROL );
+
+  ila0 : dummy_dut_chipscope_ila
+  port map (
+    CONTROL => CONTROL,
+    CLK => CLK,
+    TRIG0 => TRIG0,
+    TRIG1 => TRIG1,
+    TRIG2 => TRIG2);
+
+   -- copy signals to the Chipscope core ports...
+  TRIG0 <= TriggerNumber(0);
+  TRIG1 <= TriggerCounter(0);
+  TRIG2(0) <= ErrorFlag(0);
+  TRIG2(1) <= TriggerNumberStrobe(0);
+  TRIG2(2) <= DUT_Reset(0);
+  TRIG2(3) <= DUT_Trigger(0);
+  
+---------------------------------------------------------------
+
+-- connect up I2C bus-select lines.
+ i2c_bus_select: for BUS_ID in 0 to WIDTH_OF_I2C_SELECT_PORT-1 generate
+  begin
+    IO(I2C_BUS_SELECT_IO_BITS(BUS_ID)) <= I2C_Select(BUS_ID);
+  end generate;
+
+  -- conenct up I2C data lines
+  IO(I2C_SCL_OUT_IO_BIT) <= I2C_SCL_OUT;
+  IO(I2C_SDA_OUT_IO_BIT) <= I2C_SDA_OUT;
+  I2C_SCL_IN <= IO(I2C_SCL_IN_IO_BIT);
+  I2C_SDA_IN <= IO(I2C_SDA_IN_IO_BIT);
+    
+	-- connect up BEAM_TRIGGER and CLK to GPIO for debugging...
+  IO(GPIO_BIT(0)) <= DUT_Trigger(0);
+  IO(GPIO_BIT(1)) <= DUT_Reset(0);
+  IO(GPIO_BIT(2)) <= DUT_Busy(0);
+  IO(GPIO_BIT(3)) <= ErrorFlag(0); -- DUT_Clock(0);
+  
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/Register_Controller.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/Register_Controller.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0def0dfa8d21fc40520ea9eab202812a237a05d
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/Register_Controller.vhd
@@ -0,0 +1,601 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+-- include address map declarations
+use work.TLU_Address_Map.all;
+
+entity Register_Controller is
+
+  port (
+
+    -- Take clock from Zest interface block
+    User_CLK : in std_logic;
+
+    -- Register interface to USB
+    User_RegAddr    : in  std_logic_vector(15 downto 0);
+    User_RegDataIn  : in  std_logic_vector(7 downto 0);
+    User_RegDataOut : out std_logic_vector(7 downto 0);
+    User_RegWE      : in  std_logic;
+    User_RegRE      : in  std_logic;
+    
+    -- Take clock from trigger logic.
+    Logic_CLK : in std_logic;
+    
+    -- Signals to trigger logic
+    DUT_Reset : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);  --separate bits for each DUT
+
+    DUT_Trigger : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                  --separate bits for each DUT. Fed via trigger controller,
+                  -- so vetoed if DUT does not respond.
+
+    DUT_Debug_Trigger : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                  --separate bits for each DUT. Fed straight to output pins
+          
+    DUT_Busy : in std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state of DUT
+    DUT_Clock_Debug :  in std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- actual state
+                                                                       -- of dut_clk
+    DUT_Leds : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);  -- LED on each
+                                                                -- RJ45
+
+    -- Mask for beam trigger inputs. 
+    Beam_Trigger_AMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) := ( others => '1' ) ;
+    Beam_Trigger_OMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) := ( others => '0' ) ;
+    Beam_Trigger_VMask   : out std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+    Beam_Trigger_Mask_WE : out std_logic;
+
+    --Beam trigger input for debugging.
+    beam_trigger_in : in std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+
+    calibration_trigger_interval : out std_logic_vector(7 downto 0);
+    
+    -- send trigger to, and receive busy from only certain DUT....
+    DUT_Mask    : out std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+    DUT_Mask_WE : out std_logic;
+
+    -- because of 8-bit interface trigger a read of whole timestamp and then
+    -- read each byte separately
+    -- this is the current value of the timestamp
+    Timestamp : in std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
+
+    Trigger_Counter : in std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);
+    Particle_Counter : in std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);  -- fsv
+   
+    Trigger_Scalers : in TRIGGER_SCALER_ARRAY;
+
+    Buffer_Pointer  : in std_logic_vector(BUFFER_COUNTER_WIDTH-1 downto 0);
+
+    Trigger_Output_FSM_Status : in std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+    beam_trigger_fsm_status : in std_logic_vector(2 downto 0);
+    DMA_Status : in std_logic;
+    Host_Trig_Inhibit     : out std_logic;  -- this is the trigger inhibit controlled by the host
+    Trig_Enable_Status    : in  std_logic;  -- this is the overall status of the TLU ( incl. vetos from DUT)
+    Clock_Source_Select   : out std_logic;
+    Reset_Timestamp       : out std_logic;
+    Reset_Buffer_Pointer  : out std_logic;
+    Reset_DMA_Controller  : out std_logic;
+    Initiate_Readout      : out std_logic;
+    Reset_Trigger_Counter : out std_logic;
+    Reset_Trigger_Scalers : out std_logic;
+    Reset_Trigger_Output_FSM : out std_logic;
+    Reset_Beam_Trigger_FSM : out std_logic
+    );
+
+end Register_Controller;
+
+
+architecture rtl of Register_Controller is
+
+  component Select_Scaler
+  port (
+    trigger_scaler : in  TRIGGER_SCALER;
+                                        -- 16-bit register holding scintillator counts
+    low_byte_out       : out std_logic_vector(7 downto 0);  -- output to USB i/face
+    high_byte_out       : out std_logic_vector(7 downto 0)  -- output to USB i/face
+    );
+  end component;
+  
+  signal Output_Data : std_logic_vector(7 downto 0);
+  -- output data after Mux, before output reg
+
+  --    signal Internal_Trig_Inhibit : std_logic;  
+  --                              -- can't read an output port, so declare a dummy signal
+
+  signal Buffer_Pointer_Register :
+    std_logic_vector(BUFFER_POINTER_WIDTH-1 downto 0);
+  -- stores the buffer pointer after capture
+  signal Timestamp_Register :
+    std_logic_vector(TIMESTAMP_WIDTH-1 downto 0);
+  -- stores timestamp after capture
+  signal Trigger_Counter_Register :
+    std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);
+  -- stores the trigger counter after capture
+
+    signal Particle_Counter_Register :
+    std_logic_vector(TRIGGER_COUNTER_WIDTH-1 downto 0);
+  -- fsv -- stores the Particle counter after capture
+
+  signal Internal_DUT_Mask : std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                        -- can't read output port, so declare a dummy signal....
+
+  signal Internal_DUT_Leds : std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                        -- can't read output port, so declare a dummy signal....
+
+  signal Internal_Debug_Trigger : std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                        -- can't read output port, so declare a dummy signal....
+
+  signal Internal_DUT_Reset : std_logic_vector(NUMBER_OF_DUT-1 downto 0);
+                                        -- can't read output port, so declare a dummy signal....
+
+  signal Internal_Calibration_Trigger_Interval : std_logic_vector(CALIBRATION_TRIGGER_COUNTER_WIDTH-1 downto 0) := "00000000";
+                                 -- interval between calibration triggers, in units of milli-seconds. Zero turns off triggers
+  
+  signal Internal_Host_Trig_Inhibit : std_logic :='1';
+
+  signal Internal_Clock_Source_Select : std_logic :='1';
+
+  signal Internal_Beam_Trigger_AMask  : std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+  signal Internal_Beam_Trigger_OMask  : std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+  signal Internal_Beam_Trigger_VMask  : std_logic_vector(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+
+  signal Registered_Trigger_Scalers : TRIGGER_SCALER_ARRAY;  
+                                        -- register the scalers...
+  signal registered_scaler0 : TRIGGER_SCALER;
+  signal registered_scaler1 : TRIGGER_SCALER;
+  signal registered_scaler2 : TRIGGER_SCALER;
+  signal registered_scaler3 : TRIGGER_SCALER;
+  
+  signal Trigger_Scaler0_low : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler0_high : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler1_low : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler1_high : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler2_low : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler2_high : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler3_low : std_logic_vector(7 downto 0);
+  signal Trigger_Scaler3_high : std_logic_vector(7 downto 0);
+  
+begin  -- architecture rtl
+
+
+  -- purpose: selects which of inputs gets multiplexed to readout bus
+  -- type   : combinational
+  -- inputs : clk,addr,rw
+  -- outputs: User_RegDataOut
+  -- fsv add Particle_Counter_Register
+  read_mux : process (User_RegAddr, User_CLK , DUT_Busy, DUT_Clock_Debug, Internal_Host_Trig_Inhibit,
+                      Trig_Enable_Status, Buffer_Pointer_Register, Timestamp_Register,
+                      Trigger_Counter_Register, Particle_Counter_Register, Timestamp, Trigger_Counter, Internal_DUT_Mask,
+                      Internal_DUT_Leds, Trigger_Output_FSM_Status, DMA_Status) is
+  begin  -- process read_mux
+
+    if (
+      -- don't clock in data - it doesn't seem to work!
+        -- User_CLK'event and User_CLK = '1'
+        -- and User_RegRE = '1'
+        -- and
+        User_RegAddr(15 downto 6) = BASE_ADDRESS(15 downto 6)) then
+
+      case User_RegAddr(5 downto 0) is
+
+        -- read firmware ID
+        when FIRMWARE_ID_ADDRESS =>
+          Output_Data <= FIRMWARE_ID;
+
+          -- read staus of DUT_BUSY lines.
+        when DUT_BUSY_ADDRESS =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= DUT_Busy;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+        -- read DUT_CLOCK ( aka DUT_TRIGGER_DATA ) lines
+        when DUT_CLOCK_DEBUG_ADDRESS =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= DUT_Clock_Debug;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+
+          -- read state of trigger inhibit line
+        when TRIG_INHIBIT_ADDRESS =>
+          Output_Data(0) <= Internal_Host_Trig_Inhibit;
+          Output_Data(1) <= Trig_Enable_Status;
+          Output_Data(7 downto 2)   <= (others => '0');
+
+        when CLOCK_SOURCE_SELECT_ADDRESS =>
+          Output_Data(0) <= Internal_Clock_Source_Select;
+          Output_Data(7 downto 1)   <= (others => '0');
+
+        -- interval between internal triggersa
+        when INTERNAL_TRIGGER_INTERVAL =>
+          Output_Data(7 downto 0) <= Internal_Calibration_Trigger_Interval;
+          
+          -- read buffer pointer
+          -- for now assume a 16-bit buffer pointer
+        when REGISTERED_BUFFER_POINTER_ADDRESS_0 =>
+          Output_Data <= Buffer_Pointer_Register(7 downto 0);
+        when REGISTERED_BUFFER_POINTER_ADDRESS_1 =>
+          Output_Data <= Buffer_Pointer_Register(15 downto 8);
+
+          -- read buffer pointer
+          -- for now assume a 16-bit buffer pointer
+        when BUFFER_POINTER_ADDRESS_0 =>
+          Output_Data <= Buffer_Pointer(7 downto 0);
+        when BUFFER_POINTER_ADDRESS_1 =>
+          Output_Data(BUFFER_COUNTER_WIDTH-9 downto 0) <= Buffer_Pointer(BUFFER_COUNTER_WIDTH-1 downto 8);
+			 Output_Data(7 downto BUFFER_COUNTER_WIDTH-8) <= (others => '0');
+          
+          -- read timestamp
+          -- assume a 64-bit timestamp
+        when REGISTERED_TIMESTAMP_ADDRESS_0 =>
+          Output_Data <= Timestamp_Register(7 downto 0);
+        when REGISTERED_TIMESTAMP_ADDRESS_1 =>
+          Output_Data <= Timestamp_Register(15 downto 8);
+        when REGISTERED_TIMESTAMP_ADDRESS_2 =>
+          Output_Data <= Timestamp_Register(23 downto 16);
+        when REGISTERED_TIMESTAMP_ADDRESS_3 =>
+          Output_Data <= Timestamp_Register(31 downto 24);
+        when REGISTERED_TIMESTAMP_ADDRESS_4 =>
+          Output_Data <= Timestamp_Register(39 downto 32);
+        when REGISTERED_TIMESTAMP_ADDRESS_5 =>
+          Output_Data <= Timestamp_Register(47 downto 40);
+        when REGISTERED_TIMESTAMP_ADDRESS_6 =>
+          Output_Data <= Timestamp_Register(55 downto 48);
+        when REGISTERED_TIMESTAMP_ADDRESS_7 =>
+          Output_Data <= Timestamp_Register(63 downto 56);
+
+          -- read registered trigger counter.
+          -- assume a 32-bit trigger counter
+        when REGISTERED_TRIGGER_COUNTER_ADDRESS_0 =>
+          Output_Data <= Trigger_Counter_Register(7 downto 0);
+        when REGISTERED_TRIGGER_COUNTER_ADDRESS_1 =>
+          Output_Data <= Trigger_Counter_Register(15 downto 8);
+        when REGISTERED_TRIGGER_COUNTER_ADDRESS_2 =>
+          Output_Data <= Trigger_Counter_Register(23 downto 16);
+        when REGISTERED_TRIGGER_COUNTER_ADDRESS_3 =>
+          Output_Data <= Trigger_Counter_Register(31 downto 24);
+
+          -- read registered Particle counter.  -- fsv  --
+          -- assume a 32-bit trigger counter
+        when REGISTERED_PARTICLE_COUNTER_ADDRESS_0 =>
+          Output_Data <= Particle_Counter_Register(7 downto 0);
+        when REGISTERED_PARTICLE_COUNTER_ADDRESS_1 =>
+          Output_Data <= Particle_Counter_Register(15 downto 8);
+        when REGISTERED_PARTICLE_COUNTER_ADDRESS_2 =>
+          Output_Data <= Particle_Counter_Register(23 downto 16);
+        when REGISTERED_PARTICLE_COUNTER_ADDRESS_3 =>
+          Output_Data <= Particle_Counter_Register(31 downto 24);
+
+          -- read unregistered timestamp
+          -- assume a 64-bit timestamp
+        when TIMESTAMP_ADDRESS_0 =>
+          Output_Data <= Timestamp(7 downto 0);
+        when TIMESTAMP_ADDRESS_1 =>
+          Output_Data <= Timestamp(15 downto 8);
+        when TIMESTAMP_ADDRESS_2 =>
+          Output_Data <= Timestamp(23 downto 16);
+        when TIMESTAMP_ADDRESS_3 =>
+          Output_Data <= Timestamp(31 downto 24);
+        when TIMESTAMP_ADDRESS_4 =>
+          Output_Data <= Timestamp(39 downto 32);
+        when TIMESTAMP_ADDRESS_5 =>
+          Output_Data <= Timestamp(47 downto 40);
+        when TIMESTAMP_ADDRESS_6 =>
+          Output_Data <= Timestamp(55 downto 48);
+        when TIMESTAMP_ADDRESS_7 =>
+          Output_Data <= Timestamp(63 downto 56);
+
+          -- read unregisteredtrigger counter.
+          -- assume a 32-bit trigger counter
+        when TRIGGER_COUNTER_ADDRESS_0 =>
+          Output_Data <= Trigger_Counter(7 downto 0);
+        when TRIGGER_COUNTER_ADDRESS_1 =>
+          Output_Data <= Trigger_Counter(15 downto 8);
+        when TRIGGER_COUNTER_ADDRESS_2 =>
+          Output_Data <= Trigger_Counter(23 downto 16);
+        when TRIGGER_COUNTER_ADDRESS_3 =>
+          Output_Data <= Trigger_Counter(31 downto 24);
+
+          -- read status of DUT mask
+        when DUT_MASK_ADDRESS                              =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= Internal_DUT_Mask;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+          -- read status of LEDs
+        when DUT_LED_ADDRESS                               =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= Internal_DUT_Leds;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+        -- read status of debugging trigger (connected to dut trigger
+        -- outputs without trigger/busy handshake.
+        when DUT_DEBUG_TRIGGER_ADDRESS                     =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= Internal_Debug_Trigger;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+        -- read status of beam trigger inputs
+        -- (useful for debugging)
+        when BEAM_TRIGGER_IN_ADDRESS          =>
+          Output_Data(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) <= beam_trigger_in;
+          Output_Data(7 downto NUMBER_OF_BEAM_TRIGGERS)   <= (others => '0');
+
+
+        -- read status of beam_trigger_omask, amask , vmask
+        when BEAM_TRIGGER_OMASK_ADDRESS        =>
+          Output_Data(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) <= Internal_Beam_Trigger_OMask;
+          Output_Data(7 downto NUMBER_OF_BEAM_TRIGGERS)   <= (others => '0');
+
+        when BEAM_TRIGGER_AMASK_ADDRESS        =>
+          Output_Data(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) <= Internal_Beam_Trigger_AMask;
+          Output_Data(7 downto NUMBER_OF_BEAM_TRIGGERS)   <= (others => '0');
+
+        when BEAM_TRIGGER_VMASK_ADDRESS        =>
+          Output_Data(NUMBER_OF_BEAM_TRIGGERS-1 downto 0) <= Internal_Beam_Trigger_VMask;
+          Output_Data(7 downto NUMBER_OF_BEAM_TRIGGERS)   <= (others => '0');
+
+        -- read status of reset lines
+        when DUT_RESET_ADDRESS                     =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= Internal_DUT_Reset;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');          
+
+        when TRIGGER_FSM_STATUS_ADDRESS =>
+          Output_Data(NUMBER_OF_DUT-1 downto 0) <= Trigger_Output_FSM_Status;
+          Output_Data(7 downto NUMBER_OF_DUT)   <= (others => '0');
+
+        when BEAM_TRIGGER_FSM_STATUS_ADDRESS =>
+          Output_Data(2 downto 0) <= beam_trigger_fsm_status;
+          Output_Data(7 downto 3)   <= (others => '0');
+          
+        when DMA_STATUS_ADDRESS =>
+          Output_Data(0) <= DMA_Status;
+          Output_Data(7 downto 1)   <= (others => '0');
+          
+--          trigger_scaler_read_mux:
+--            for BEAM_TRIGGER_IDX in 0 to NUMBER_OF_BEAM_TRIGGERS-1 generate
+--              high_low:
+--                for HIGH_LOW_BYTE in 0 to 1 generate
+--                  when (TRIGGER_IN0_COUNTER_0 + BEAM_TRIGGER_IDX*2 + HIGH_LOW_BYTE) =>                    
+--                    register_scaler: Select_Scaler
+--                      port map (
+--                        trigger_scaler => Trigger_Scalers(BEAM_TRIGGER_IDX1),
+--                        byte_select => HIGH_LOW_BYTE1,
+--                        byte_out => Output_Data
+--                        );
+--                end generate;  -- HIGH_LOW
+--            end generate;  -- BEAM_TRIGGER_IDX
+--                    Output_Data <= Registered_Trigger_Scaler_Byte(BEAM_TRIGGER_IDX*2 + HIGH_LOW_BYTE);
+
+        when TRIGGER_IN0_COUNTER_0 =>
+          Output_Data <= Trigger_Scaler0_low;
+
+        when TRIGGER_IN0_COUNTER_1 =>
+          Output_Data <= Trigger_Scaler0_high;
+
+        when TRIGGER_IN1_COUNTER_0 =>
+          Output_Data <= Trigger_Scaler1_low;
+
+        when TRIGGER_IN1_COUNTER_1 =>
+          Output_Data <= Trigger_Scaler1_high;
+
+        when TRIGGER_IN2_COUNTER_0 =>
+          Output_Data <= Trigger_Scaler2_low;
+
+        when TRIGGER_IN2_COUNTER_1 =>
+          Output_Data <= Trigger_Scaler2_high;
+
+        when TRIGGER_IN3_COUNTER_0 =>
+          Output_Data <= Trigger_Scaler3_low;
+
+        when TRIGGER_IN3_COUNTER_1 =>
+          Output_Data <= Trigger_Scaler3_high;          
+
+          
+        when others =>
+          -- if the address is out of range return zero
+          --Output_Data(7 downto 0)   <= (others => '0');
+			 null;
+			 
+      end case;
+
+      --else
+      --  -- if the address is out of range return zero
+      --  Output_Data(7 downto 0)   <= (others => '0');
+    end if;
+
+  end process read_mux;
+
+--  trigger_scaler_register_mux:
+--  for BEAM_TRIGGER_IDX1 in 0 to NUMBER_OF_BEAM_TRIGGERS-1 generate
+--    high_low1:
+--    for HIGH_LOW_BYTE1 in 0 to 1 generate
+--      register_scaler: Select_Scaler
+--        port map (
+--          trigger_scaler => Trigger_Scalers(BEAM_TRIGGER_IDX1),
+--          byte_select => HIGH_LOW_BYTE1,
+--          byte_out => Registered_Scaler_Byte(BEAM_TRIGGER_IDX1*2 + HIGH_LOW_BYTE1)
+--          );
+--    end generate;  -- HIGH_LOW
+--  end generate;  -- BEAM_TRIGGER_IDX
+
+--              Registered_Scaler <= Registered_Trigger_Scalers(BEAM_TRIGGER_IDX);
+--  Registered_Trigger_Scaler(8*(HIGH_LOW_BYTE+1)-1 downto 7*HIGH_LOW_BYTE);
+  
+
+  -- purpose: Writing to STATE_CAPTURE_ADDRESS registers
+  --          Timestamp, Trigger_Counter, Buffer_Pointer
+  -- type   : combinational
+  -- inputs : User_CLK
+  -- outputs: Timestamp_Register, Trigger_Counter_Register,
+  --          Buffer_Pointer_Register
+
+  write_mux : process (User_CLK, Timestamp,
+                           Trigger_Counter, Buffer_Pointer) is
+  begin  -- process capture_state
+	 -- clock the data to be written on the *falling* edge of user clock.
+    if (User_CLK'event and User_CLK = '0') then
+      if ( User_RegWE = '1' and User_RegAddr(15 downto 6) = BASE_ADDRESS(15 downto 6)) then
+
+        -- Capture timestamp, trigger_counter and buffer_pointer
+        -- into registers.
+        if (User_RegAddr(5 downto 0) = STATE_CAPTURE_ADDRESS) then
+          Timestamp_Register <= Timestamp;
+          Trigger_Counter_Register <= Trigger_Counter;
+          Particle_Counter_Register <= Particle_Counter;   --  fsv
+          Buffer_Pointer_Register(BUFFER_COUNTER_WIDTH-1 downto 0)                    <= Buffer_Pointer;
+          Buffer_Pointer_Register(BUFFER_POINTER_WIDTH-1 downto BUFFER_COUNTER_WIDTH) <= (others => '0');
+
+          Registered_Trigger_Scalers <= Trigger_Scalers;
+          
+        end if;
+
+        -- output DUT reset signals.
+        if (User_RegAddr(5 downto 0) = DUT_RESET_ADDRESS ) then
+          Internal_DUT_Reset <= User_RegDataIn(NUMBER_OF_DUT-1 downto 0);
+        end if;
+
+        -- output DUT trigger signals for one clock cycle...
+        if (User_RegAddr(5 downto 0) = DUT_TRIGGER_ADDRESS
+            ) then
+          DUT_Trigger <= User_RegDataIn(NUMBER_OF_DUT-1 downto 0);
+        end if;
+
+        -- output trigger inhibit signal
+        if (User_RegAddr(5 downto 0) = TRIG_INHIBIT_ADDRESS ) then
+          Internal_Host_Trig_Inhibit <= User_RegDataIn(0);
+        end if;
+
+        -- set the frequency of the internal (calibration) triggers
+        if (User_RegAddr(5 downto 0) = INTERNAL_TRIGGER_INTERVAL ) then
+          Internal_Calibration_Trigger_Interval <= User_RegDataIn;
+        end if;
+        
+        -- output DUT_mask
+        if ( User_RegAddr(5 downto 0) = DUT_MASK_ADDRESS ) then
+          Internal_DUT_Mask <= User_RegDataIn(NUMBER_OF_DUT-1 downto 0);
+          DUT_Mask_WE       <= '1';
+        end if;
+
+        -- write to LEDs
+        if ( User_RegAddr(5 downto 0) = DUT_LED_ADDRESS ) then
+          Internal_DUT_Leds <= User_RegDataIn(NUMBER_OF_DUT-1 downto 0);
+        end if;
+
+
+        -- Select which clock source drives the trigger logic
+        -- 0 = external clock
+        -- 1 = USB ( 48MHz ) clock
+        if (User_RegAddr(5 downto 0) = CLOCK_SOURCE_SELECT_ADDRESS ) then
+          Internal_Clock_Source_Select <= User_RegDataIn(0);
+        end if;
+
+        -- Write to the trigger output.
+        if ( User_RegAddr(5 downto 0) = DUT_DEBUG_TRIGGER_ADDRESS ) then
+          Internal_Debug_Trigger <= User_RegDataIn(NUMBER_OF_DUT-1 downto 0);
+        end if;
+
+        -- output pointer/counter reset signals for one clock cycle.
+        if (User_RegAddr(5 downto 0) = RESET_REGISTER_ADDRESS
+            ) then
+          Reset_Timestamp       <=
+            User_RegDataIn(TIMESTAMP_RESET_BIT);
+          Reset_Trigger_Counter <=
+            User_RegDataIn(TRIGGER_COUNTER_RESET_BIT);
+          Reset_Buffer_Pointer  <=
+            User_RegDataIn(BUFFER_POINTER_RESET_BIT);
+          Reset_DMA_Controller  <=
+            User_RegDataIn(DMA_CONTROLLER_RESET_BIT);
+          Reset_Trigger_Output_FSM <= User_RegDataIn(TRIGGER_FSM_RESET_BIT);
+          --Reset_Beam_Trigger_FSM <= User_RegDataIn(BEAM_TRIGGER_FSM_RESET_BIT);
+	  Reset_Trigger_Scalers <= User_RegDataIn(TRIGGER_SCALERS_RESET_BIT);
+       end if;
+
+
+
+        -- Initiate readout block readout of trigger info
+        if (User_RegAddr(5 downto 0) = INITIATE_READOUT_ADDRESS
+            ) then
+          Initiate_Readout <= '1';
+        end if;
+
+                                        -- set beam trigger output masks.
+        if (User_RegAddr(5 downto 0) = BEAM_TRIGGER_AMASK_ADDRESS or
+            User_RegAddr(5 downto 0) = BEAM_TRIGGER_OMASK_ADDRESS or
+            User_RegAddr(5 downto 0) = BEAM_TRIGGER_VMASK_ADDRESS
+            ) then
+          Beam_Trigger_Mask_WE <= '1';
+          if (User_RegAddr(5 downto 0) = BEAM_TRIGGER_AMASK_ADDRESS) then
+            Internal_Beam_Trigger_AMask <= User_RegDataIn(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+          elsif (User_RegAddr(5 downto 0) = BEAM_TRIGGER_OMASK_ADDRESS) then
+            Internal_Beam_Trigger_OMask <= User_RegDataIn(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+          else
+            Internal_Beam_Trigger_VMask <= User_RegDataIn(NUMBER_OF_BEAM_TRIGGERS-1 downto 0);
+          end if;
+        end if;
+
+
+      else
+        initiate_readout <= '0';
+        DUT_Mask_WE      <= '0';
+        Beam_Trigger_Mask_WE <= '0';
+        Reset_Timestamp       <= '0';
+        Reset_Trigger_Counter <= '0';
+        Reset_Buffer_Pointer  <= '0';
+        Reset_DMA_Controller  <= '0';
+        Reset_Trigger_Output_FSM <= '0';
+        Reset_Beam_Trigger_FSM <= '0';
+        
+      end if;
+
+    end if;  -- end of clk'falling
+  end process write_mux;
+
+
+  registered_scaler0 <= Registered_Trigger_Scalers(0);
+  Trigger_Scaler0_low <= registered_scaler0(7 downto 0);
+  Trigger_Scaler0_high <= registered_scaler0(15 downto 8);
+
+  registered_scaler1 <= Registered_Trigger_Scalers(1);
+  Trigger_Scaler1_low <= registered_scaler1(7 downto 0);
+  Trigger_Scaler1_high <= registered_scaler1(15 downto 8);
+
+  registered_scaler2 <= Registered_Trigger_Scalers(2);
+  Trigger_Scaler2_low <= registered_scaler2(7 downto 0);
+  Trigger_Scaler2_high <= registered_scaler2(15 downto 8);
+
+  registered_scaler3 <= Registered_Trigger_Scalers(3);
+  Trigger_Scaler3_low <= registered_scaler3(7 downto 0);
+  Trigger_Scaler3_high <= registered_scaler3(15 downto 8);
+  
+
+  -- purpose: output register for data output to USB
+  -- type   : combinational
+  -- inputs : clk, User_RegDataOut
+  -- outputs: User_RegDataOut
+--         output_register: process (User_CLK, Output_Data) is
+--           begin                      -- process output_register
+--             if (User_CLK'event and User_CLK='1') then
+--               User_RegDataOut <= Output_Data;
+--             end if;
+--           end process output_register;
+
+  User_RegDataOut <= Output_Data;
+
+  DUT_Mask <= Internal_DUT_Mask;
+
+  DUT_Leds <= Internal_DUT_Leds;
+
+  DUT_Debug_Trigger <= Internal_Debug_Trigger;
+
+  DUT_Reset <= Internal_DUT_Reset;
+
+  Clock_Source_Select <= Internal_Clock_Source_Select;
+
+  Host_Trig_Inhibit <= Internal_Host_Trig_Inhibit;
+
+  calibration_trigger_interval <= Internal_Calibration_Trigger_Interval;
+
+  Beam_Trigger_OMask <= Internal_Beam_Trigger_OMask;
+  Beam_Trigger_AMask <= Internal_Beam_Trigger_AMask;
+  Beam_Trigger_VMask <= Internal_Beam_Trigger_VMask;
+
+  
+end architecture rtl;
+
+
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_Address_Map.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_Address_Map.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c3b75a35b16e788b2affe791df96c9944eee93ce
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_Address_Map.vhd
@@ -0,0 +1,144 @@
+--
+-- TLU_address_map.vhdl
+--
+-- package containg address map and type definitions for JRA1 TLU
+--
+-- Generated by script make_tlu_address_map.pl
+--
+-- Do not edit by hand! 
+-- Edit TLU_address_map.dat instead                                
+--
+-- Generated on Sun Aug 31 21:05:20 2008
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package TLU_Address_Map is
+
+  constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "11111010" ; 
+  constant NUMBER_OF_DUT : integer := 6; -- how many devices
+                                  -- (including telescope devices)
+                                  -- in system
+											 
+  constant BEAM_TRIGGER_MASK_WIDTH : integer := 12; -- should be three times the # trigger
+  constant NUMBER_OF_BEAM_TRIGGERS : integer := 4;
+  
+  constant TIMESTAMP_WIDTH : integer := 64;
+  constant NUMBER_WORDS_IN_TIMESTAMP : integer := 4;
+  constant TRIGGER_COUNTER_WIDTH : integer := 32;
+  constant TRIGGER_DATA_WIDTH : integer := 32;
+  constant BUFFER_POINTER_WIDTH : integer := 16;    --  width of pointer
+  constant BUFFER_COUNTER_WIDTH : integer := 12;  -- this is the width of
+                                                    -- the counter,
+                                                    -- *NOT* the pointer
+                                                    -- ( which has to be
+                                                    -- an integer number
+                                                    -- of bytes )
+  constant BUFFER_DEPTH : integer := 4096;          -- 2^BUFFER_COUNTER_WIDTH
+  constant BUFFER_HEADROOM : integer := 8; -- leave this many entries in 
+                                           -- buffer when siganlling full
+  -----------------------------------------------------------------------------
+  -- define which bits in RESET_REGISTER reset which counters/pointers...
+  constant TIMESTAMP_RESET_BIT : integer := 0;
+  constant TRIGGER_COUNTER_RESET_BIT : integer := 1;
+  constant BUFFER_POINTER_RESET_BIT : integer := 2;
+  constant TRIGGER_FSM_RESET_BIT : integer := 3;
+  constant BEAM_TRIGGER_FSM_RESET_BIT : integer := 4;
+  constant DMA_CONTROLLER_RESET_BIT : integer := 5;
+  constant TRIGGER_SCALERS_RESET_BIT : integer := 6;
+
+ -----------------------------------------------------------------------------
+  -- Constants for internal trigger generation
+  constant CALIBRATION_TRIGGER_COUNTER_WIDTH : integer := 8;
+  constant SLOW_CLOCK_COUNTER_WIDTH : integer := 16;  -- needs to store 48000
+  constant SLOW_CLOCK_RATIO : std_logic_vector (SLOW_CLOCK_COUNTER_WIDTH-1 downto 0) := "1011101110000000";  -- ratio between 48MHz and 1kHz
+
+  -----------------------------------------------------------------------------
+  constant SCALER_NUMBER_OF_BYTES : integer := 2;
+  subtype TRIGGER_SCALER is std_logic_vector(8*SCALER_NUMBER_OF_BYTES - 1 downto 0);
+  type TRIGGER_SCALER_ARRAY is array ( NUMBER_OF_BEAM_TRIGGERS-1 downto 0) of TRIGGER_SCALER;
+  
+  -----------------------------------------------------------------------------
+    -- mapping of IO pins onto signals in design.
+  -----------------------------------------------------------------------------
+  type beam_trigger_inputs is array ( 0 to 3 ) of integer; 
+  -- this beam trigger mapping assumes use of Bonn discriminator board.
+  -- i.e. 1,0,3,2
+  constant BEAM_TRIG_IN_BIT : beam_trigger_inputs := (9,6,11,8);
+  
+  type dut_io is array ( 0 to NUMBER_OF_DUT-1 ) of integer;
+  constant TRIGGER_OUTPUT_BIT : dut_io := (1,0,3,2,5,4);
+  constant DUT_RESET_BIT : dut_io := (13,12,15,14,17,16);
+  constant DUT_BUSY_BIT : dut_io := (27,26,29,28,31,30);
+  constant DUT_CLOCK_BIT : dut_io := (38,41,43,42,44,46);
+  constant DUT_LED_BIT : dut_io := (18,21,20,23,22,25);
+
+  type gpio is array (0 to 4) of integer;  -- mapping for gpio bits
+  constant GPIO_BIT : gpio := (37,36,35,34,32);
+  -----------------------------------------------------------------------------
+
+  constant BASE_ADDRESS : std_logic_vector(15 downto 0) := "0010000000000000" ;
+
+  constant FIRMWARE_ID_ADDRESS : std_logic_vector(5 downto 0) := "000001" ;
+  constant DUT_BUSY_ADDRESS : std_logic_vector(5 downto 0) := "000010" ;
+  constant DUT_RESET_ADDRESS : std_logic_vector(5 downto 0) := "000011" ;
+  constant DUT_TRIGGER_ADDRESS : std_logic_vector(5 downto 0) := "000100" ;
+  constant DUT_MASK_ADDRESS : std_logic_vector(5 downto 0) := "000101" ;
+  constant TRIG_INHIBIT_ADDRESS : std_logic_vector(5 downto 0) := "000110" ;
+  constant RESET_REGISTER_ADDRESS : std_logic_vector(5 downto 0) := "000111" ;
+  constant INITIATE_READOUT_ADDRESS : std_logic_vector(5 downto 0) := "001000" ;
+  constant STATE_CAPTURE_ADDRESS : std_logic_vector(5 downto 0) := "001001" ;
+  constant TRIGGER_FSM_STATUS_ADDRESS : std_logic_vector(5 downto 0) := "001010" ;
+  constant BEAM_TRIGGER_FSM_STATUS_ADDRESS : std_logic_vector(5 downto 0) := "001011" ;
+  constant DMA_STATUS_ADDRESS : std_logic_vector(5 downto 0) := "001100" ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_0 : std_logic_vector(5 downto 0) := "001101" ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_1 : std_logic_vector(5 downto 0) := "001110" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_0 : std_logic_vector(5 downto 0) := "001111" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_1 : std_logic_vector(5 downto 0) := "010000" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_2 : std_logic_vector(5 downto 0) := "010001" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_3 : std_logic_vector(5 downto 0) := "010010" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_4 : std_logic_vector(5 downto 0) := "010011" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_5 : std_logic_vector(5 downto 0) := "010100" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_6 : std_logic_vector(5 downto 0) := "010101" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_7 : std_logic_vector(5 downto 0) := "010110" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_0 : std_logic_vector(5 downto 0) := "010111" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_1 : std_logic_vector(5 downto 0) := "011000" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_2 : std_logic_vector(5 downto 0) := "011001" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_3 : std_logic_vector(5 downto 0) := "011010" ;
+  constant BUFFER_POINTER_ADDRESS_0 : std_logic_vector(5 downto 0) := "011011" ;
+  constant BUFFER_POINTER_ADDRESS_1 : std_logic_vector(5 downto 0) := "011100" ;
+  constant TIMESTAMP_ADDRESS_0 : std_logic_vector(5 downto 0) := "011101" ;
+  constant TIMESTAMP_ADDRESS_1 : std_logic_vector(5 downto 0) := "011110" ;
+  constant TIMESTAMP_ADDRESS_2 : std_logic_vector(5 downto 0) := "011111" ;
+  constant TIMESTAMP_ADDRESS_3 : std_logic_vector(5 downto 0) := "100000" ;
+  constant TIMESTAMP_ADDRESS_4 : std_logic_vector(5 downto 0) := "100001" ;
+  constant TIMESTAMP_ADDRESS_5 : std_logic_vector(5 downto 0) := "100010" ;
+  constant TIMESTAMP_ADDRESS_6 : std_logic_vector(5 downto 0) := "100011" ;
+  constant TIMESTAMP_ADDRESS_7 : std_logic_vector(5 downto 0) := "100100" ;
+  constant TRIGGER_COUNTER_ADDRESS_0 : std_logic_vector(5 downto 0) := "100101" ;
+  constant TRIGGER_COUNTER_ADDRESS_1 : std_logic_vector(5 downto 0) := "100110" ;
+  constant TRIGGER_COUNTER_ADDRESS_2 : std_logic_vector(5 downto 0) := "100111" ;
+  constant TRIGGER_COUNTER_ADDRESS_3 : std_logic_vector(5 downto 0) := "101000" ;
+  constant BEAM_TRIGGER_AMASK_ADDRESS : std_logic_vector(5 downto 0) := "101001" ;
+  constant BEAM_TRIGGER_OMASK_ADDRESS : std_logic_vector(5 downto 0) := "101010" ;
+  constant BEAM_TRIGGER_VMASK_ADDRESS : std_logic_vector(5 downto 0) := "101011" ;
+  constant INTERNAL_TRIGGER_INTERVAL : std_logic_vector(5 downto 0) := "101100" ;
+  constant BEAM_TRIGGER_IN_ADDRESS : std_logic_vector(5 downto 0) := "101101" ;
+  constant DUT_RESET_DEBUG_ADDRESS : std_logic_vector(5 downto 0) := "101110" ;
+  constant DUT_DEBUG_TRIGGER_ADDRESS : std_logic_vector(5 downto 0) := "101111" ;
+  constant DUT_CLOCK_DEBUG_ADDRESS : std_logic_vector(5 downto 0) := "110000" ;
+  constant DUT_LED_ADDRESS : std_logic_vector(5 downto 0) := "110001" ;
+  constant CLOCK_SOURCE_SELECT_ADDRESS : std_logic_vector(5 downto 0) := "110010" ;
+  constant TRIGGER_IN0_COUNTER_0 : std_logic_vector(5 downto 0) := "110011" ;
+  constant TRIGGER_IN0_COUNTER_1 : std_logic_vector(5 downto 0) := "110100" ;
+  constant TRIGGER_IN1_COUNTER_0 : std_logic_vector(5 downto 0) := "110101" ;
+  constant TRIGGER_IN1_COUNTER_1 : std_logic_vector(5 downto 0) := "110110" ;
+  constant TRIGGER_IN2_COUNTER_0 : std_logic_vector(5 downto 0) := "110111" ;
+  constant TRIGGER_IN2_COUNTER_1 : std_logic_vector(5 downto 0) := "111000" ;
+  constant TRIGGER_IN3_COUNTER_0 : std_logic_vector(5 downto 0) := "111001" ;
+  constant TRIGGER_IN3_COUNTER_1 : std_logic_vector(5 downto 0) := "111010" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_0 : std_logic_vector(5 downto 0) := "111011" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_1 : std_logic_vector(5 downto 0) := "111100" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_2 : std_logic_vector(5 downto 0) := "111101" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_3 : std_logic_vector(5 downto 0) := "111110" ;
+end package TLU_Address_Map;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_address_map_v0-2.vhdl b/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_address_map_v0-2.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1d2515db185d3a9d522fe7c885c6459b483bd7e2
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/TLU_address_map_v0-2.vhdl
@@ -0,0 +1,263 @@
+--
+-- TLU_address_map_v0-2.vhdl
+--
+--
+-- Generated on Mon Feb  8 18:18:05 2010
+--
+--
+-- package containg address map and type definitions for JRA1 TLU
+--
+-- Generated by script make_tlu_address_map.pl
+--
+-- Do not edit by hand! 
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+package TLU_Address_Map_v02 is
+  
+  constant NUMBER_OF_DUT : integer := 6; -- how many devices
+                                  -- (including telescope devices)
+                                  -- in system
+											 
+  constant BEAM_TRIGGER_MASK_WIDTH : integer := 12; -- should be three times the # trigger
+  constant NUMBER_OF_BEAM_TRIGGERS : integer := 4;
+  
+  constant TIMESTAMP_WIDTH : integer := 64;
+  constant TIMESTAMP_OUTPUT_WIDTH : integer := 16;
+  constant NUMBER_WORDS_IN_TIMESTAMP : integer := 4;
+  constant TRIGGER_COUNTER_WIDTH : integer := 32;
+  constant TRIGGER_DATA_WIDTH : integer := 32;
+  constant STROBE_COUNTER_WIDTH : integer := 32;  -- width for recurring strobe pulses.
+  constant BUFFER_POINTER_WIDTH : integer := 16;    --  width of pointer
+  constant BUFFER_COUNTER_WIDTH : integer := 12;  -- this is the width of
+                                                    -- the counter,
+                                                    -- *NOT* the pointer
+                                                    -- ( which has to be
+                                                    -- an integer number
+                                                    -- of bytes )
+  constant OUTPUT_BUFFER_COUNTER_WIDTH : integer := BUFFER_COUNTER_WIDTH+2;  -- pointer into 16-bit output of DPR
+  constant BUFFER_DEPTH : integer := 4096;          -- 2^BUFFER_COUNTER_WIDTH
+  constant BUFFER_HEADROOM : integer := 16; -- leave this many entries in 
+                                            -- buffer when siganlling full
+  constant NUM_WORDS_IN_LONGLONG : integer := 4;  -- Number of 16-bit words in a 64-bit word
+  
+  -----------------------------------------------------------------------------
+  -- define which bits in RESET_REGISTER reset which counters/pointers...
+  -----------------------------------------------------------------------------
+  constant TIMESTAMP_RESET_BIT : integer := 0;
+  constant TRIGGER_COUNTER_RESET_BIT : integer := 1;
+  constant BUFFER_POINTER_RESET_BIT : integer := 2;
+  constant TRIGGER_FSM_RESET_BIT : integer := 3;
+  constant BEAM_TRIGGER_FSM_RESET_BIT : integer := 4;
+  constant DMA_CONTROLLER_RESET_BIT : integer := 5;
+  constant TRIGGER_SCALERS_RESET_BIT : integer := 6;
+  constant CLOCK_GEN_RESET_BIT : integer := 7;
+
+  constant ENABLE_DMA_BIT : integer := 0;
+  constant RESET_DMA_COUNTER_BIT : integer := 1;
+  
+  -----------------------------------------------------------------------------
+  -- Constants for internal trigger generation
+  -----------------------------------------------------------------------------
+  constant CALIBRATION_TRIGGER_COUNTER_WIDTH : integer := 8;
+  constant SLOW_CLOCK_COUNTER_WIDTH : integer := 16;  -- needs to store 48000
+  --constant SLOW_CLOCK_RATIO : std_logic_vector (SLOW_CLOCK_COUNTER_WIDTH-1 downto 0) := "1011101110000000";  -- ratio between 48MHz and 1kHz
+  -- hack for Santos...
+  constant SLOW_CLOCK_RATIO : std_logic_vector (SLOW_CLOCK_COUNTER_WIDTH-1 downto 0) :=   "0000000111100000";  -- ratio between 48MHz and 100kHz
+
+  -----------------------------------------------------------------------------
+  -- define sub-types for internal trigger scalers.
+  -----------------------------------------------------------------------------
+  constant SCALER_NUMBER_OF_BYTES : integer := 2;
+  subtype TRIGGER_SCALER is std_logic_vector(8*SCALER_NUMBER_OF_BYTES - 1 downto 0);
+  type TRIGGER_SCALER_ARRAY is array ( NUMBER_OF_BEAM_TRIGGERS-1 downto 0) of TRIGGER_SCALER;
+  
+  -----------------------------------------------------------------------------
+  -- define which bits for I2C lines
+  -----------------------------------------------------------------------------
+  constant I2C_SDA_OUT_BIT : integer := 0;
+  constant I2C_SDA_IN_BIT : integer := 1;
+  constant I2C_SCL_OUT_BIT : integer := 2;
+  constant I2C_SCL_IN_BIT : integer := 3;
+  constant WIDTH_OF_I2C_SELECT_PORT : integer := 2;
+
+  -- I2C bus numbers ( write to register to select )
+  constant I2C_BUS_MOTHERBOARD  : integer := 3;  
+  constant I2C_BUS_HDMI         : integer := 2;
+  constant I2C_BUS_LEMO         : integer := 1;
+  constant I2C_BUS_DISPLAY         : integer := 0;
+
+  -- List I2C PCA9555 devices.
+  constant I2C_BUS_MOTHERBOARD_LED_IO : integer := 0;
+  constant I2C_BUS_MOTHERBOARD_TRIGGER_ENABLE_IPSEL_IO : integer := 1;
+  constant I2C_BUS_MOTHERBOARD_RESET_ENABLE_IO : integer := 2;
+  constant I2C_BUS_MOTHERBOARD_FRONT_PANEL_IO : integer := 3;
+  constant I2C_BUS_MOTHERBOARD_LCD_IO : integer := 4;
+
+  constant I2C_BUS_LEMO_RELAY_IO : integer := 0;
+
+  -- This is a bit of a cock-up. The PCA9555 attached to the LEDs changed address between version "b" ( = 1 ) and version "c" (= 0) 
+  constant I2C_BUS_LEMO_LED_IO_VB : integer := 1;
+  
+  constant I2C_BUS_LEMO_LED_IO : integer := 0;
+  constant I2C_BUS_LEMO_ADC : integer := 2;
+
+  -----------------------------------------------------------------------------
+    -- mapping of IO pins onto signals in design.
+  -----------------------------------------------------------------------------
+  type beam_trigger_inputs is array ( 0 to 3 ) of integer;
+  -- Assumes Bonn discriminator board ( ie 1,0,3,2)
+  constant BEAM_TRIG_IN_BIT : beam_trigger_inputs := (9,6,11,8);
+  
+  type dut_io is array ( 0 to NUMBER_OF_DUT-1 ) of integer;
+  constant TRIGGER_OUTPUT_BIT : dut_io := (1,0,3,2,5,4);
+  constant DUT_RESET_BIT : dut_io := (13,12,15,14,17,16);
+  constant DUT_BUSY_BIT : dut_io := (27,26,29,28,31,30);
+  constant DUT_CLOCK_BIT : dut_io := (38,41,43,42,44,46);
+
+ -- constant DUT_LED_BIT : dut_io := (18,21,20,23,22,25);
+  type i2c_select_array is array ( 0 to WIDTH_OF_I2C_SELECT_PORT-1)of integer ;
+  constant I2C_BUS_SELECT_IO_BITS : i2c_select_array := ( 25 , 22 );
+  constant I2C_SCL_OUT_IO_BIT : integer := 18;
+  constant I2C_SDA_OUT_IO_BIT : integer := 21;
+  constant I2C_SCL_IN_IO_BIT : integer := 20;
+  constant I2C_SDA_IN_IO_BIT : integer := 23;
+
+  constant I2C_FRONT_PANEL_INTERRUPT : integer := 32;
+  
+  type gpio is array (0 to 3) of integer;  -- mapping for gpio bits
+  constant GPIO_BIT : gpio := (37,36,35,34);
+  -----------------------------------------------------------------------------
+  constant FIRMWARE_ID : std_logic_vector(7 downto 0) := "01000100" ;
+-- FIRMWARE_ID = 68
+
+ constant BASE_ADDRESS : std_logic_vector(15 downto 0) := "0010000000000000" ;
+-- BASE_ADDRESS = 8192
+
+  constant NUMBER_OF_BITS_TO_DECODE : integer := 7 ;  -- how many bits of the address should be decoded?
+  constant FIRMWARE_ID_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000000" ;
+  constant DUT_BUSY_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000001" ;
+  constant DUT_RESET_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000010" ;
+  constant DUT_TRIGGER_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000011" ;
+  constant DUT_MASK_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000100" ;
+  constant TRIG_INHIBIT_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000101" ;
+  constant RESET_REGISTER_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000110" ;
+  constant INITIATE_READOUT_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0000111" ;
+  constant STATE_CAPTURE_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001000" ;
+  constant TRIGGER_FSM_STATUS_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001001" ;
+  constant BEAM_TRIGGER_FSM_STATUS_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001010" ;
+  constant DMA_STATUS_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001011" ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001100" ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_BYTES : integer := 2 ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001100" ;
+  constant REGISTERED_BUFFER_POINTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001101" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001110" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_BYTES : integer := 8 ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001110" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0001111" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010000" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010001" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_4 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010010" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_5 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010011" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_6 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010100" ;
+  constant REGISTERED_TIMESTAMP_ADDRESS_7 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010101" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010110" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_BYTES : integer := 4 ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010110" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0010111" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011000" ;
+  constant REGISTERED_TRIGGER_COUNTER_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011001" ;
+  constant BUFFER_POINTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011010" ;
+  constant BUFFER_POINTER_ADDRESS_BYTES : integer := 2 ;
+  constant BUFFER_POINTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011010" ;
+  constant BUFFER_POINTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011011" ;
+  constant TIMESTAMP_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011100" ;
+  constant TIMESTAMP_ADDRESS_BYTES : integer := 8 ;
+  constant TIMESTAMP_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011100" ;
+  constant TIMESTAMP_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011101" ;
+  constant TIMESTAMP_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011110" ;
+  constant TIMESTAMP_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0011111" ;
+  constant TIMESTAMP_ADDRESS_4 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100000" ;
+  constant TIMESTAMP_ADDRESS_5 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100001" ;
+  constant TIMESTAMP_ADDRESS_6 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100010" ;
+  constant TIMESTAMP_ADDRESS_7 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100011" ;
+  constant TRIGGER_COUNTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100100" ;
+  constant TRIGGER_COUNTER_ADDRESS_BYTES : integer := 4 ;
+  constant TRIGGER_COUNTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100100" ;
+  constant TRIGGER_COUNTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100101" ;
+  constant TRIGGER_COUNTER_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100110" ;
+  constant TRIGGER_COUNTER_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0100111" ;
+  constant BEAM_TRIGGER_AMASK_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101000" ;
+  constant BEAM_TRIGGER_OMASK_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101001" ;
+  constant BEAM_TRIGGER_VMASK_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101010" ;
+  constant INTERNAL_TRIGGER_INTERVAL : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101011" ;
+  constant BEAM_TRIGGER_IN_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101100" ;
+  constant DUT_RESET_DEBUG_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101101" ;
+  constant DUT_DEBUG_TRIGGER_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101110" ;
+  constant DUT_CLOCK_DEBUG_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0101111" ;
+  constant DUT_I2C_BUS_SELECT_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110000" ;
+  constant DUT_I2C_BUS_DATA_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110001" ;
+  constant CLOCK_SOURCE_SELECT_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110010" ;
+  constant TRIGGER_IN0_COUNTER_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110011" ;
+  constant TRIGGER_IN0_COUNTER_BYTES : integer := 2 ;
+  constant TRIGGER_IN0_COUNTER_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110011" ;
+  constant TRIGGER_IN0_COUNTER_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110100" ;
+  constant TRIGGER_IN1_COUNTER_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110101" ;
+  constant TRIGGER_IN1_COUNTER_BYTES : integer := 2 ;
+  constant TRIGGER_IN1_COUNTER_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110101" ;
+  constant TRIGGER_IN1_COUNTER_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110110" ;
+  constant TRIGGER_IN2_COUNTER_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110111" ;
+  constant TRIGGER_IN2_COUNTER_BYTES : integer := 2 ;
+  constant TRIGGER_IN2_COUNTER_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0110111" ;
+  constant TRIGGER_IN2_COUNTER_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111000" ;
+  constant TRIGGER_IN3_COUNTER_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111001" ;
+  constant TRIGGER_IN3_COUNTER_BYTES : integer := 2 ;
+  constant TRIGGER_IN3_COUNTER_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111001" ;
+  constant TRIGGER_IN3_COUNTER_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111010" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111011" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_BYTES : integer := 4 ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111011" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111100" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111101" ;
+  constant REGISTERED_PARTICLE_COUNTER_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111110" ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111111" ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_BYTES : integer := 4 ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "0111111" ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000000" ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000001" ;
+  constant REGISTERED_AUX_COUNTER_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000010" ;
+  constant HANDSHAKE_MODE_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000011" ;
+  constant BUFFER_STOP_MODE_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000100" ;
+  constant WRITE_TRIGGER_BITS_MODE_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000101" ;
+  constant TRIGGER_PATTERN_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000110" ;
+  constant TRIGGER_PATTERN_ADDRESS_BYTES : integer := 2 ;
+  constant TRIGGER_PATTERN_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000110" ;
+  constant TRIGGER_PATTERN_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1000111" ;
+  constant AUX_PATTERN_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001000" ;
+  constant AUX_PATTERN_ADDRESS_BYTES : integer := 2 ;
+  constant AUX_PATTERN_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001000" ;
+  constant AUX_PATTERN_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001001" ;
+  constant STROBE_WIDTH_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001010" ;
+  constant STROBE_WIDTH_ADDRESS_BYTES : integer := 4 ;
+  constant STROBE_WIDTH_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001010" ;
+  constant STROBE_WIDTH_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001011" ;
+  constant STROBE_WIDTH_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001100" ;
+  constant STROBE_WIDTH_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001101" ;
+  constant STROBE_PERIOD_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001110" ;
+  constant STROBE_PERIOD_ADDRESS_BYTES : integer := 4 ;
+  constant STROBE_PERIOD_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001110" ;
+  constant STROBE_PERIOD_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1001111" ;
+  constant STROBE_PERIOD_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010000" ;
+  constant STROBE_PERIOD_ADDRESS_3 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010001" ;
+  constant STROBE_ENABLE_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010010" ;
+  constant TRIGGER_FSM_STATUS_VALUE_ADDRESS_BASE : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010011" ;
+  constant TRIGGER_FSM_STATUS_VALUE_ADDRESS_BYTES : integer := 3 ;
+  constant TRIGGER_FSM_STATUS_VALUE_ADDRESS_0 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010011" ;
+  constant TRIGGER_FSM_STATUS_VALUE_ADDRESS_1 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010100" ;
+  constant TRIGGER_FSM_STATUS_VALUE_ADDRESS_2 : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010101" ;
+  constant ENABLE_DUT_VETO_ADDRESS : std_logic_vector(NUMBER_OF_BITS_TO_DECODE-1 downto 0) := "1010110" ;
+
+  constant ADDRESS_MAP_SIZE : integer := 87 ;
+
+end package TLU_Address_Map_v02 ;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/Trigger_Number_Error_Checker.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/Trigger_Number_Error_Checker.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..8c361f43f9f762566622fece046e2eba4c2bb7f1
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/Trigger_Number_Error_Checker.vhd
@@ -0,0 +1,116 @@
+----------------------------------------------------------------------------------
+--! @file
+--
+-- Company: University of Bristol 
+-- Engineer: David Cussans
+-- 
+-- Create Date:    11/11/09
+-- Design Name: 
+-- Module Name:    Trigger_Number_Error_Checker - RTL 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+--! @brief Checks the trigger numbers being returned by the dummy dut.
+--
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+-- constant definitions.
+
+
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Trigger_Number_Error_Checker is
+    Port ( 
+           CLK : in  STD_LOGIC;         --! this is the USB clock.
+	   RST : in STD_LOGIC;          --! Synchronous with clock
+           TriggerNumber : in STD_LOGIC_VECTOR(15 downto 0);  --! should
+                                                              --incremeent from
+                                                              --0
+           TriggerNumberStrobe : in STD_LOGIC;  --! Active high
+           TriggerCounter : out  STD_LOGIC_VECTOR(15 downto 0);  --!internal counter
+           ErrorFlag : out STD_LOGIC    --! goes high if internal number
+                                        --doesn't match
+           );
+
+end entity Trigger_Number_Error_Checker;
+
+architecture RTL of Trigger_Number_Error_Checker is
+
+
+  
+  signal InternalTriggerCounter : std_logic_vector(TriggerNumber'high downto 0);  -- internal
+                                                                          -- store
+                                                                          -- to compare with output from TLU
+
+  signal InternalErrorFlag : std_logic := '0';  -- VHDL can't read an out-port bodge
+
+  signal Registered_TriggerNumberStrobe0 ,Registered_TriggerNumberStrobe1 ,Registered_TriggerNumberStrobe2  : std_logic := '0';  
+                                        -- bodge 'cos I don't understand RTL...
+  signal Registered_TriggerNumber : std_logic_vector(15 downto 0);
+  
+begin
+
+  delay_triggerstrobe: process (clk , TriggerNumberStrobe ,Registered_TriggerNumberStrobe0 ,Registered_TriggerNumberStrobe1 , Registered_TriggerNumberStrobe2 )
+  begin  -- process delay_triggerstrobe
+    if rising_edge(clk) then
+      Registered_TriggerNumberStrobe0 <= TriggerNumberStrobe;
+      Registered_TriggerNumberStrobe1 <= Registered_TriggerNumberStrobe0;
+      Registered_TriggerNumberStrobe2 <= Registered_TriggerNumberStrobe1;
+    end if;
+  end process delay_triggerstrobe;
+
+  register_trigger_number: process (clk , TriggerNumber  )
+  begin  -- process register_trigger_number
+    if rising_edge(clk) then
+      Registered_TriggerNumber <= TriggerNumber;
+    end if;
+  end process register_trigger_number;
+
+  
+  check_error: process (clk ,Registered_TriggerNumberStrobe0 , Registered_TriggerNumber , InternalTriggerCounter)
+  begin  -- process busy_control
+    if (rising_edge(clk) and (Registered_TriggerNumberStrobe0 = '1'))  then
+      if ( unsigned(Registered_TriggerNumber) /= (unsigned(InternalTriggerCounter)+2) )then  --
+        -- temporary fix to check that checker is working.
+--              if ( unsigned(Registered_TriggerNumber) /= (unsigned(InternalTriggerCounter)+1) )then
+        InternalErrorFlag <= '1';
+      else
+        InternalErrorFlag <= '0';
+      end if;
+    end if;
+  end process check_error;
+
+  output_error: process (clk ,  Registered_TriggerNumberStrobe1 , InternalErrorFlag)
+  begin  -- process output_error
+    if (rising_edge(clk)and (Registered_TriggerNumberStrobe1 = '1')) then
+      ErrorFlag <=  InternalErrorFlag;
+    end if;   
+  end process output_error;
+
+  
+  register_trigger_number: process (clk ,  Registered_TriggerNumberStrobe2 , TriggerNumber )
+  begin  -- process output_error
+    if (rising_edge(clk)and (Registered_TriggerNumberStrobe2 = '1')) then
+      InternalTriggerCounter <= TriggerNumber;
+    end if;   
+  end process output_error;
+
+  TriggerCounter <= InternalTriggerCounter;
+  
+end RTL;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Host.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Host.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f7b1bf96e47c30c8b04d14abe2bcc3e7a2804237
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Host.vhd
@@ -0,0 +1,652 @@
+-- ZestSC1 Host Interface Code
+-- File name: ZestSC1_Host.vhd
+-- Version: 1.10
+-- Date: 14/3/2006
+
+-- Copyright (C) 2005 Orange Tree Technologies Ltd. All rights reserved.
+-- Orange Tree Technologies grants the purchaser of a ZestSC1 the right to use and
+-- modify this logic core in any form including but not limited to VHDL source code or
+-- EDIF netlist in FPGA designs that target the ZestSC1.
+-- Orange Tree Technologies prohibits the use of this logic core or any modification of
+-- it in any form including but not limited to VHDL source code or EDIF netlist in
+-- FPGA or ASIC designs that target any other hardware unless the purchaser of the
+-- ZestSC1 has purchased the appropriate licence from Orange Tree Technologies.
+-- Contact Orange Tree Technologies if you want to purchase such a licence.
+
+--*****************************************************************************************
+--**
+--**  Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
+--**              provided to you "as is". Orange Tree Technologies and its licensors 
+--**              make and you receive no warranties or conditions, express, implied, 
+--**              statutory or otherwise, and Orange Tree Technologies specifically 
+--**              disclaims any implied warranties of merchantability, non-infringement,
+--**              or fitness for a particular purpose. Orange Tree Technologies does not
+--**              warrant that the functions contained in these designs will meet your 
+--**              requirements, or that the operation of these designs will be 
+--**              uninterrupted or error free, or that defects in the Designs will be 
+--**              corrected. Furthermore, Orange Tree Technologies does not warrant or 
+--**              make any representations regarding use or the results of the use of the 
+--**              designs in terms of correctness, accuracy, reliability, or otherwise.                                               
+--**
+--**              LIMITATION OF LIABILITY. In no event will Orange Tree Technologies 
+--**              or its licensors be liable for any loss of data, lost profits, cost or 
+--**              procurement of substitute goods or services, or for any special, 
+--**              incidental, consequential, or indirect damages arising from the use or 
+--**              operation of the designs or accompanying documentation, however caused 
+--**              and on any theory of liability. This limitation will apply even if 
+--**              Orange Tree Technologies has been advised of the possibility of such 
+--**              damage. This limitation shall apply notwithstanding the failure of the 
+--**              essential purpose of any limited remedies herein.
+--**
+--*****************************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity ZestSC1_Host is
+    port (
+        -- FPGA pin connections
+        USB_StreamCLK : in std_logic;
+        USB_StreamFIFOADDR : out std_logic_vector(1 downto 0);
+        USB_StreamPKTEND_n : out std_logic;
+        USB_StreamFlags_n : in std_logic_vector(2 downto 0);
+        USB_StreamSLOE_n : out std_logic;
+        USB_StreamSLRD_n : out std_logic;
+        USB_StreamSLWR_n : out std_logic;
+        USB_StreamFX2Rdy : in std_logic;
+--        USB_StreamData : inout std_logic_vector(15 downto 0);
+        USB_StreamData : out std_logic_vector(15 downto 0);
+
+        USB_RegCLK : in std_logic;
+        USB_RegAddr : in std_logic_vector(15 downto 0);
+        USB_RegData : inout std_logic_vector(7 downto 0);
+        USB_RegOE_n : in std_logic;
+        USB_RegRD_n : in std_logic;
+        USB_RegWR_n : in std_logic;
+        USB_RegCS_n : in std_logic;
+
+        USB_Interrupt : out std_logic;
+
+        -- User connections
+        -- Streaming interface
+        User_CLK : out std_logic;
+        User_RST : out std_logic;
+        DCMLocked : out std_logic;
+
+        User_StreamBusGrantLength : in std_logic_vector(11 downto 0);
+
+        User_StreamDataIn : out std_logic_vector(15 downto 0);
+        User_StreamDataInWE : out std_logic;
+        User_StreamDataInBusy : in std_logic;
+
+        User_StreamDataOut : in std_logic_vector(15 downto 0);
+        User_StreamDataOutWE : in std_logic;
+        User_StreamDataOutBusy : out std_logic;
+
+        -- Register interface
+        User_RegAddr : out std_logic_vector(15 downto 0);
+        User_RegDataIn : out std_logic_vector(7 downto 0);
+        User_RegDataOut : in std_logic_vector(7 downto 0);
+        User_RegWE : out std_logic;
+        User_RegRE : out std_logic;
+
+        -- Interrupts
+        User_Interrupt : in std_logic
+    );
+end ZestSC1_Host;
+
+architecture arch of ZestSC1_Host is
+
+    -- Reset block
+    component ROC
+        port
+        (
+            O : out std_logic
+        );
+    end component;
+    attribute box_type : string;
+    attribute box_type of ROC: component is "black_box";
+
+    -- DCMs
+    component DCM 
+      -- synthesis translate_off 
+      generic (CLK_FEEDBACK : string := "1X"; 
+               CLKDV_DIVIDE : real := 2.0;
+               CLKFX_DIVIDE : integer := 1;
+               CLKFX_MULTIPLY : integer := 4;
+               CLKIN_DIVIDE_BY_2 : boolean := FALSE;
+               CLKIN_PERIOD : real := 20.0;
+               CLKOUT_PHASE_SHIFT : string := "NONE"; 
+               DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; 
+               DFS_FREQUENCY_MODE : string := "LOW"; 
+               DLL_FREQUENCY_MODE : string := "LOW"; 
+               DSS_MODE : string := "NONE"; 
+               DUTY_CYCLE_CORRECTION : boolean := TRUE;
+               PHASE_SHIFT : integer := 0; 
+               STARTUP_WAIT : boolean := FALSE);
+      -- synthesis translate_on 
+      port (CLK0 : out std_ulogic; 
+            CLK180 : out std_ulogic; 
+            CLK270 : out std_ulogic; 
+            CLK2X : out std_ulogic; 
+            CLK2X180 : out std_ulogic; 
+            CLK90 : out std_ulogic; 
+            CLKDV : out std_ulogic; 
+            CLKFX : out std_ulogic; 
+            CLKFX180 : out std_ulogic; 
+            LOCKED : out std_ulogic; 
+            PSDONE : out std_ulogic; 
+            STATUS : out std_logic_vector(7 downto 0); 
+            CLKFB : in std_ulogic; 
+            CLKIN : in std_ulogic; 
+            DSSEN : in std_ulogic; 
+            PSCLK : in std_ulogic; 
+            PSEN : in std_ulogic; 
+            PSINCDEC : in std_ulogic; 
+            RST : in std_ulogic); 
+    end component; 
+    attribute box_type of DCM: component is "black_box";
+
+    attribute CLK_FEEDBACK : string; 
+    attribute CLKDV_DIVIDE : real; 
+    attribute CLKFX_DIVIDE : integer; 
+    attribute CLKFX_MULTIPLY : integer; 
+    attribute CLKIN_DIVIDE_BY_2 : boolean; 
+    attribute CLKOUT_PHASE_SHIFT : string; 
+    attribute DESKEW_ADJUST : string; 
+    attribute DFS_FREQUENCY_MODE : string; 
+    attribute DLL_FREQUENCY_MODE : string; 
+    attribute DSS_MODE : string; 
+    attribute DUTY_CYCLE_CORRECTION : boolean; 
+    attribute PHASE_SHIFT : integer; 
+    attribute STARTUP_WAIT : boolean; 
+--    attribute FACTORY_JF : integer;
+    
+    -- Component Attribute specification for Stream clock DCM 
+    attribute CLK_FEEDBACK of StreamDCM: label is "1X"; 
+    attribute CLKDV_DIVIDE of StreamDCM: label is 2.0;
+    attribute CLKFX_DIVIDE of StreamDCM: label is 1; 
+    attribute CLKFX_MULTIPLY of StreamDCM: label is 2; 
+    attribute CLKIN_DIVIDE_BY_2 of StreamDCM: label is FALSE; 
+    attribute CLKOUT_PHASE_SHIFT of StreamDCM: label is "NONE";
+--    attribute CLKOUT_PHASE_SHIFT of StreamDCM: label is "FIXED"; 
+    attribute DESKEW_ADJUST of StreamDCM : label is "SYSTEM_SYNCHRONOUS"; 
+    attribute DFS_FREQUENCY_MODE of StreamDCM: label is "LOW"; 
+    attribute DLL_FREQUENCY_MODE of StreamDCM: label is "LOW"; 
+    attribute DSS_MODE of StreamDCM: label is "NONE"; 
+    attribute DUTY_CYCLE_CORRECTION of StreamDCM: label is TRUE;
+    attribute PHASE_SHIFT of StreamDCM: label is 0;
+--    attribute PHASE_SHIFT of StreamDCM: label is -13; 
+    attribute STARTUP_WAIT of StreamDCM: label is FALSE;
+--    attribute FACTORY_JF of StreamDCM: label is x"8080";
+    
+    -- Component Attribute specification for Register clock DCM 
+    attribute CLK_FEEDBACK of RegDCM: label is "1X"; 
+    attribute CLKDV_DIVIDE of RegDCM: label is 2.0;
+    attribute CLKFX_DIVIDE of RegDCM: label is 1; 
+    attribute CLKFX_MULTIPLY of RegDCM: label is 2; 
+    attribute CLKIN_DIVIDE_BY_2 of RegDCM: label is FALSE; 
+    attribute CLKOUT_PHASE_SHIFT of RegDCM: label is "NONE"; 
+    attribute DESKEW_ADJUST of RegDCM : label is "SYSTEM_SYNCHRONOUS"; 
+    attribute DFS_FREQUENCY_MODE of RegDCM: label is "LOW"; 
+    attribute DLL_FREQUENCY_MODE of RegDCM: label is "LOW"; 
+    attribute DSS_MODE of RegDCM: label is "NONE"; 
+    attribute DUTY_CYCLE_CORRECTION of RegDCM: label is TRUE;
+    attribute PHASE_SHIFT of RegDCM: label is 0; 
+    attribute STARTUP_WAIT of RegDCM: label is FALSE;
+
+    -- Declare global clock buffer
+    component BUFG 
+        port (I   : in std_logic;
+              O   : out std_logic
+	        ); 
+    end component;
+    attribute box_type of BUFG: component is "black_box";
+
+    -- General signals
+    signal RST : std_logic;
+    signal StreamCLK : std_logic;
+    signal StreamCLKFB : std_logic;
+    signal RegCLK : std_logic;
+    signal RegCLKFB : std_logic;
+
+    -- Streaming interface
+--    signal StreamRead : std_logic;
+    signal StreamWrite : std_logic;
+    signal StreamDataIn : std_logic_vector(15 downto 0);
+    signal StreamDataOut : std_logic_vector(15 downto 0);
+    signal DataOutRegFull : std_logic;
+    signal StreamBusy : std_logic;
+    signal StreamDataAvailable : std_logic;
+    signal StreamReadStrobe : std_logic;
+    signal WriteToFIFOIn : std_logic;
+    signal StreamWriteStrobe : std_logic;
+    signal ReadFromFIFOOut : std_logic;
+    signal ReadOK : std_logic;
+    signal WriteOK : std_logic;
+--    signal ReadCycle : std_logic;
+    signal WriteCycle : std_logic;
+    signal User_DataInStrobe : std_logic;
+    signal GrantPeriod : std_logic_vector(11 downto 0);
+    signal Granted : std_logic;
+    signal LastDir : std_logic;
+
+    signal FX2FIFOFull : std_logic;
+    signal FX2FIFOEmpty : std_logic;
+
+    type FIFO_ARRAY_TYPE is array(15 downto 0) of std_logic_vector(15 downto 0);
+    signal FIFOOut : FIFO_ARRAY_TYPE;
+    signal FIFOIn : FIFO_ARRAY_TYPE;
+    signal FIFOInEmpty : std_logic;
+
+    signal FIFOOutWriteCount : std_logic_vector(3 downto 0);
+    signal FIFOOutWriteCountG : std_logic_vector(3 downto 0);
+    signal RegFIFOOutWriteCountG : std_logic_vector(3 downto 0);
+    signal FIFOOutWriteCountInUSB : std_logic_vector(3 downto 0);
+
+    signal FIFOOutReadCount : std_logic_vector(3 downto 0);
+    signal FIFOOutReadCountG : std_logic_vector(3 downto 0);
+    signal RegFIFOOutReadCountG : std_logic_vector(3 downto 0);
+    signal FIFOOutReadCountInUser : std_logic_vector(3 downto 0);
+
+    signal FIFOInWriteCount : std_logic_vector(3 downto 0);
+    signal FIFOInWriteCountG : std_logic_vector(3 downto 0);
+    signal RegFIFOInWriteCountG : std_logic_vector(3 downto 0);
+    signal FIFOInWriteCountInUser : std_logic_vector(3 downto 0);
+
+    signal FIFOInReadCount : std_logic_vector(3 downto 0);
+    signal FIFOInReadCountG : std_logic_vector(3 downto 0);
+    signal RegFIFOInReadCountG : std_logic_vector(3 downto 0);
+    signal FIFOInReadCountInUSB : std_logic_vector(3 downto 0);
+
+    signal FIFOOutDataCount : std_logic_vector(3 downto 0);
+    signal FIFOInDataCount : std_logic_vector(3 downto 0);
+
+    -- Memory mapped interface
+    signal RegCS : std_logic;
+    signal RegLastCS : std_logic;
+    signal RegOE : std_logic;
+    signal RegLastOE : std_logic;
+    signal RegWR : std_logic;
+    signal RegLastWR : std_logic;
+    signal RegRD : std_logic;
+    signal RegLastRD : std_logic;
+    signal RegOutput : std_logic_vector(7 downto 0);
+
+    -- Counter for interrupt generation
+    signal IntCounter : std_logic_vector(2 downto 0);
+
+begin
+
+    -- Generate resets and clocks
+    ROC_1 : ROC port map ( O => RST );
+    User_RST <= RST;
+    User_CLK <= RegCLK;
+
+    -------------------------
+    -- Streaming interface --
+    -------------------------
+
+    -- Control signals
+    USB_StreamPKTEND_n <= '1';
+    USB_StreamSLRD_n <= not StreamReadStrobe;
+    USB_StreamSLWR_n <= not StreamWriteStrobe;
+    USB_StreamSLOE_n <= '1'; -- modify for write stream data only 
+
+    USB_StreamData <= StreamDataOut; -- modify for output only 
+
+--    USB_StreamFIFOADDR <= "00" when (ReadCycle='1' or StreamRead='1') else "10";
+    USB_StreamFIFOADDR <= "10";
+
+
+    -- Generate FIFO full and empty flags for the FX2
+    -- This must be done internally because the timing of the FX2 flags
+    -- and read/write strobes is such that we cannot respond to the flags
+    -- in one clock cycle.  The flags from the FX2 are therefore set to
+    -- one empty place (full flag) and one available word (empty flag).
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+            FX2FIFOFull <= '1';
+            FX2FIFOEmpty <= '1';
+        elsif (StreamCLK'event and StreamCLK='1') then
+            if (USB_StreamFlags_n(0)='1' and USB_StreamFX2Rdy='1') then
+                FX2FIFOEmpty <= '0';
+            elsif (StreamReadStrobe='1') then
+                FX2FIFOEmpty <= '1';
+            end if;
+
+            if (USB_StreamFlags_n(1)='1' and USB_StreamFX2Rdy='1') then
+                FX2FIFOFull <= '0';
+            elsif (StreamWriteStrobe='1') then
+                FX2FIFOFull <= '1';
+            end if;
+        end if;
+    end process;
+
+    -- Read and write strobe generation and registering of input and output data
+    StreamReadStrobe <= '0'; -- modify for write only
+    
+    WriteToFIFOIn <= '0'; -- modify for write only
+
+    StreamWriteStrobe <= '1' when (WriteCycle='1') else '0';
+    ReadFromFIFOOut <= '1' when (WriteCycle='0' and DataOutRegFull='0' and
+                                 StreamDataAvailable='1') else '0';
+    WriteOK <= '1' when FX2FIFOFull='0' and (StreamDataAvailable='1' or DataOutRegFull='1') and
+                        USB_StreamFX2Rdy='1' and StreamWrite='1' else '0';
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+            DataOutRegFull <= '0';
+        elsif (StreamCLK'event and StreamCLK='1') then
+            if (ReadFromFIFOOut='1') then
+                StreamDataOut <= FIFOOut(conv_integer(FIFOOutReadCount));
+                DataOutRegFull <= '1';
+            elsif (StreamWriteStrobe='1') then
+                DataOutRegFull <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- Control individual reads and writes from/to the FX2
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+--            ReadCycle <= '0';
+            WriteCycle <= '0';
+        elsif (StreamCLK'event and StreamCLK='1') then
+
+--          ReadCycle <= '0';             -- modify for write only.
+
+            if (WriteCycle='0') then
+                WriteCycle <= WriteOK;
+            else
+                WriteCycle <= '0';
+            end if;
+
+        end if;
+    end process;
+
+    -- Manage transfers
+    -- Checks whether a transfer is needed and possible
+    -- Use round robin to alternate between reads and writes
+    --
+    -- GrantLength limits the length of time the streaming bus is granted to
+    -- reads or writes.  Set it low for rapid bus turn arounds at the expense
+    -- of overall bandwidth.  Set high for larger maximum bandwidth at the 
+    -- expense of slower bus turnarounds
+    -- DGC, Dec 09.
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+--            StreamRead <= '0';
+            StreamWrite <= '0';
+            GrantPeriod <= X"000";
+            Granted <= '0';
+            FIFOInWriteCount <= X"0";
+            FIFOOutReadCount <= X"0";
+            LastDir <= '0';
+
+        elsif (StreamCLK'event and StreamCLK='1') then
+
+--          StreamRead <= '0';
+          
+            if (Granted='0') then
+
+              -- modify for output data only
+              if (FX2FIFOFull='0' and (StreamDataAvailable='1' or DataOutRegFull='1')) then
+                    -- EP6 full flag is clear and we have data
+                    StreamWrite <= '1';
+--                    GrantPeriod <= User_StreamBusGrantLength; -- no point in
+--                    loading grant period - since don't do anything with it.
+                    LastDir <= '1';
+                    Granted <= '1';
+                end if;
+
+            end if;
+
+            if (WriteToFIFOIn='1') then
+                FIFOInWriteCount <= FIFOInWriteCount + 1;
+            end if;
+            if (ReadFromFIFOOut='1') then
+                FIFOOutReadCount <= FIFOOutReadCount + 1;
+            end if;
+
+        end if;
+    end process;
+
+    -- Short FIFOs for crossing clock domains
+    -- User domain -> USB
+    process (RST, RegCLK)
+    begin
+        if (RST='1') then
+            FIFOOutWriteCount <= "0000";
+        elsif (RegCLK'event and RegCLK='1') then
+            if (User_StreamDataOutWE='1') then
+                FIFOOutWriteCount <= FIFOOutWriteCount + 1;
+            end if;
+        end if;
+    end process;
+    process (RegCLK)
+    begin
+        if (RegCLK'event and RegCLK='1') then
+            if (User_StreamDataOutWE='1') then
+                FIFOOut(conv_integer(FIFOOutWriteCount)) <= User_StreamDataOut;
+            end if;
+        end if;
+    end process;
+
+    -- Note fixup for behavioural simulation - holds the data during write strobe
+    User_StreamDataIn <= ( others => '0' );
+    User_StreamDataInWE <= User_DataInStrobe;
+    User_DataInStrobe <= not FIFOInEmpty and not User_StreamDataInBusy;
+
+    -- Generate busy flag to User
+    -- Grey code the DataOut read counter, cross clock domain and decode
+    FIFOOutReadCountG <= FIFOOutReadCount(3) &
+                         (FIFOOutReadCount(3) xor FIFOOutReadCount(2)) &
+                         (FIFOOutReadCount(2) xor FIFOOutReadCount(1)) &
+                         (FIFOOutReadCount(1) xor FIFOOutReadCount(0));
+    process (RST, RegCLK)
+    begin
+        if (RST='1') then
+            RegFIFOOutReadCountG <= "0000";
+        elsif (RegCLK'event and RegClk='1') then
+            RegFIFOOutReadCountG <= FIFOOutReadCountG;
+        end if;
+    end process;
+    FIFOOutReadCountInUser <= RegFIFOOutReadCountG(3) &
+                              (RegFIFOOutReadCountG(3) xor RegFIFOOutReadCountG(2)) &
+                              (RegFIFOOutReadCountG(3) xor RegFIFOOutReadCountG(2) xor RegFIFOOutReadCountG(1)) &
+                              (RegFIFOOutReadCountG(3) xor RegFIFOOutReadCountG(2) xor RegFIFOOutReadCountG(1) xor RegFIFOOutReadCountG(0));
+    FIFOOutDataCount <= FIFOOutWriteCount-FIFOOutReadCountInUser;
+    User_StreamDataOutBusy <= '1' when (FIFOOutDataCount(3)='1') else '0';
+
+    -- Generate write enable strobe to the User
+    -- Grey code the DataIn write counter, cross clock domain and decode
+    FIFOInWriteCountG <= FIFOInWriteCount(3) &
+                         (FIFOInWriteCount(3) xor FIFOInWriteCount(2)) &
+                         (FIFOInWriteCount(2) xor FIFOInWriteCount(1)) &
+                         (FIFOInWriteCount(1) xor FIFOInWriteCount(0));
+    process (RST, RegCLK)
+    begin
+        if (RST='1') then
+            RegFIFOInWriteCountG <= "0000";
+        elsif (RegCLK'event and RegClk='1') then
+            RegFIFOInWriteCountG <= FIFOInWriteCountG;
+        end if;
+    end process;
+    FIFOInWriteCountInUser <= RegFIFOInWriteCountG(3) &
+                              (RegFIFOInWriteCountG(3) xor RegFIFOInWriteCountG(2)) &
+                              (RegFIFOInWriteCountG(3) xor RegFIFOInWriteCountG(2) xor RegFIFOInWriteCountG(1)) &
+                              (RegFIFOInWriteCountG(3) xor RegFIFOInWriteCountG(2) xor RegFIFOInWriteCountG(1) xor RegFIFOInWriteCountG(0));
+    FIFOInEmpty <= '1' when FIFOInWriteCountInUser=FIFOInReadCount else '0';
+
+    -- Generate 'data available' flag to the USB chip
+    FIFOOutWriteCountG <= FIFOOutWriteCount(3) &
+                          (FIFOOutWriteCount(3) xor FIFOOutWriteCount(2)) &
+                          (FIFOOutWriteCount(2) xor FIFOOutWriteCount(1)) &
+                          (FIFOOutWriteCount(1) xor FIFOOutWriteCount(0));
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+            RegFIFOOutWriteCountG <= "0000";
+        elsif (StreamCLK'event and StreamCLK='1') then
+            RegFIFOOutWriteCountG <= FIFOOutWriteCountG;
+        end if;
+    end process;
+    FIFOOutWriteCountInUSB <= RegFIFOOutWriteCountG(3) &
+                              (RegFIFOOutWriteCountG(3) xor RegFIFOOutWriteCountG(2)) &
+                              (RegFIFOOutWriteCountG(3) xor RegFIFOOutWriteCountG(2) xor RegFIFOOutWriteCountG(1)) &
+                              (RegFIFOOutWriteCountG(3) xor RegFIFOOutWriteCountG(2) xor RegFIFOOutWriteCountG(1) xor RegFIFOOutWriteCountG(0));
+    StreamDataAvailable <= '1' when (FIFOOutWriteCountInUSB/=FIFOOutReadCount) else '0';
+
+    -- Generate 'space available' flag to the USB chip
+    FIFOInReadCountG <= FIFOInReadCount(3) &
+                        (FIFOInReadCount(3) xor FIFOInReadCount(2)) &
+                        (FIFOInReadCount(2) xor FIFOInReadCount(1)) &
+                        (FIFOInReadCount(1) xor FIFOInReadCount(0));
+    process (RST, StreamCLK)
+    begin
+        if (RST='1') then
+            RegFIFOInReadCountG <= "0000";
+        elsif (StreamCLK'event and StreamCLK='1') then
+            RegFIFOInReadCountG <= FIFOInReadCountG;
+        end if;
+    end process;
+    FIFOInReadCountInUSB <= RegFIFOInReadCountG(3) &
+                            (RegFIFOInReadCountG(3) xor RegFIFOInReadCountG(2)) &
+                            (RegFIFOInReadCountG(3) xor RegFIFOInReadCountG(2) xor RegFIFOInReadCountG(1)) &
+                            (RegFIFOInReadCountG(3) xor RegFIFOInReadCountG(2) xor RegFIFOInReadCountG(1) xor RegFIFOInReadCountG(0));
+    FIFOInDataCount <= FIFOInWriteCount-FIFOInReadCountInUSB;
+    StreamBusy <= '1' when (FIFOInDataCount(3)='1') else '0';
+
+
+    -----------------------------
+    -- Memory mapped interface --
+    -----------------------------
+    User_RegAddr <= USB_RegAddr - X"2000"; -- 8051 external memory starts at 0x2000
+    User_RegWE <= RegCS and RegLastCS and RegWR and RegLastWR;
+    User_RegRE <= RegCS and not RegLastCS and RegRD and not RegLastRD;
+    User_RegDataIn <= USB_RegData;
+
+    RegCS <= not USB_RegCS_n;
+    RegOE <= not USB_RegOE_n;
+    RegWR <= not USB_RegWR_n;
+    RegRD <= not USB_RegRD_n;
+    process (RegCLK)
+    begin
+        if (RegCLK'event and RegCLK='1') then
+            RegLastCS <= RegCS;
+            RegLastRD <= RegRD;
+            RegLastWR <= RegWR;
+            RegLastOE <= RegOE;
+        end if;
+    end process;
+
+    -- Register read interface
+    process (RegCLK)
+    begin
+        if (RegCLK'event and RegCLK='1') then
+            RegOutput <= User_RegDataOut;
+        end if;
+    end process;
+
+    USB_RegData <= RegOutput when (RegRD='1' and RegCS='1' and RegOE='1') else (others=>'Z');
+
+
+    ---------------------------
+    -- Generate an interrupt --
+    ---------------------------
+    -- Interrupt is active low, edge triggered and must be held for
+    -- 4 cycles of the register interface clock
+    process (RST, RegCLK)
+    begin
+        if (RST='1') then
+            IntCounter <= "000";
+        elsif (RegCLK'event and RegCLK='1') then
+            if (User_Interrupt='1') then
+                IntCounter <= "100";
+            elsif (IntCounter/="000") then
+                IntCounter <= IntCounter + 1;
+            end if;
+        end if;
+    end process;
+    USB_Interrupt <= not IntCounter(2);
+
+
+    -------------------------------
+    -- Instatiate DCMs on clocks --
+    -------------------------------
+    StreamDCM : DCM 
+        -- synthesis translate_off 
+        generic map(CLK_FEEDBACK => "1X", 
+                    CLKDV_DIVIDE => 2.0,
+                    CLKFX_DIVIDE => 1,
+                    CLKFX_MULTIPLY => 2,
+                    CLKIN_DIVIDE_BY_2 => false,
+                    CLKOUT_PHASE_SHIFT => "NONE",
+--                    CLKOUT_PHASE_SHIFT => "NONE",
+                    CLKIN_PERIOD => 20.833,
+                    CLKOUT_PHASE_SHIFT => "FIXED", 
+                    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", 
+                    DFS_FREQUENCY_MODE => "LOW", 
+                    DLL_FREQUENCY_MODE => "LOW", 
+                    DSS_MODE => "NONE", 
+                    DUTY_CYCLE_CORRECTION => true,
+--                    PHASE_SHIFT => -13,
+                    PHASE_SHIFT => 0,
+--                    FACTORY_JF => x"8080",
+                    STARTUP_WAIT => false)
+        -- synthesis translate_on 
+        port map (CLK0 => StreamCLKFB,
+                  CLKFB => StreamCLK,
+                  CLKIN => USB_StreamCLK, 
+                  DSSEN => '0',
+                  PSCLK => '0',
+                  PSEN => '0',
+                  PSINCDEC => '0',
+                  RST => RST); 
+    StreamCLK_BUFG: BUFG
+        port map (
+            I => StreamCLKFB,
+            O => StreamCLK
+        );
+
+    RegDCM : DCM 
+        -- synthesis translate_off 
+        generic map(CLK_FEEDBACK => "1X", 
+                    CLKDV_DIVIDE => 2.0,
+                    CLKFX_DIVIDE => 1,
+                    CLKFX_MULTIPLY => 2,
+                    CLKIN_DIVIDE_BY_2 => false,
+                    CLKOUT_PHASE_SHIFT => "NONE", 
+                    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", 
+                    DFS_FREQUENCY_MODE => "LOW", 
+                    DLL_FREQUENCY_MODE => "LOW", 
+                    DSS_MODE => "NONE", 
+                    DUTY_CYCLE_CORRECTION => true,
+                    PHASE_SHIFT => 0, 
+                    STARTUP_WAIT => false)
+        -- synthesis translate_on 
+        port map (CLK0 => RegCLKFB,
+                  CLKFB => RegCLK,
+                  CLKIN => USB_RegCLK, 
+                  DSSEN => '0',
+                  PSCLK => '0',
+                  PSEN => '0',
+                  PSINCDEC => '0',
+                  RST => RST,
+                  LOCKED => DCMLocked); 
+    RegCLK_BUFG: BUFG
+        port map (
+  	        I => RegCLKFB,
+            O => RegCLK
+  	    );
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Interfaces.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Interfaces.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6f9909e26ddc9648ccf6b85008091ac620d11a3d
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ZestSC1_Interfaces.vhd
@@ -0,0 +1,329 @@
+-- ZestSC1 Top Level Code
+-- File name: ZestSC1_Interfaces.vhd
+-- Version: 1.00
+-- Date: 9/2/2005
+
+-- Copyright (C) 2005 Orange Tree Technologies Ltd. All rights reserved.
+-- Orange Tree Technologies grants the purchaser of a ZestSC1 the right to use and
+-- modify this logic core in any form including but not limited to VHDL source code or
+-- EDIF netlist in FPGA designs that target the ZestSC1.
+-- Orange Tree Technologies prohibits the use of this logic core or any modification of
+-- it in any form including but not limited to VHDL source code or EDIF netlist in
+-- FPGA or ASIC designs that target any other hardware unless the purchaser of the
+-- ZestSC1 has purchased the appropriate licence from Orange Tree Technologies.
+-- Contact Orange Tree Technologies if you want to purchase such a licence.
+
+--*****************************************************************************************
+--**
+--**  Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
+--**              provided to you "as is". Orange Tree Technologies and its licensors 
+--**              make and you receive no warranties or conditions, express, implied, 
+--**              statutory or otherwise, and Orange Tree Technologies specifically 
+--**              disclaims any implied warranties of merchantability, non-infringement,
+--**              or fitness for a particular purpose. Orange Tree Technologies does not
+--**              warrant that the functions contained in these designs will meet your 
+--**              requirements, or that the operation of these designs will be 
+--**              uninterrupted or error free, or that defects in the Designs will be 
+--**              corrected. Furthermore, Orange Tree Technologies does not warrant or 
+--**              make any representations regarding use or the results of the use of the 
+--**              designs in terms of correctness, accuracy, reliability, or otherwise.                                               
+--**
+--**              LIMITATION OF LIABILITY. In no event will Orange Tree Technologies 
+--**              or its licensors be liable for any loss of data, lost profits, cost or 
+--**              procurement of substitute goods or services, or for any special, 
+--**              incidental, consequential, or indirect damages arising from the use or 
+--**              operation of the designs or accompanying documentation, however caused 
+--**              and on any theory of liability. This limitation will apply even if 
+--**              Orange Tree Technologies has been advised of the possibility of such 
+--**              damage. This limitation shall apply notwithstanding the failure of the 
+--**              essential purpose of any limited remedies herein.
+--**
+--*****************************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--  Uncomment the following lines to use the declarations that are
+--  provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ZestSC1_Interfaces is
+    port (
+        -- User connections
+        -- General connections
+        User_CLK : out std_logic;                          -- User logic clock
+        User_RST : out std_logic;                          -- User logic reset
+
+        -- USB Streaming interface
+        User_StreamBusGrantLength : in std_logic_vector(11 downto 0); -- Round robin grant length
+                                                           -- Controls read and write grant times
+                                                           -- on the streaming bus
+
+        User_StreamDataIn : out std_logic_vector(15 downto 0); -- Stream data from host
+        User_StreamDataInWE : out std_logic;               -- Stream write strobe from host
+        User_StreamDataInBusy : in std_logic;              -- Busy for stream from host
+
+        User_StreamDataOut : in std_logic_vector(15 downto 0); -- Stream data to host
+        User_StreamDataOutWE : in std_logic;               -- Stream write strobe to host
+        User_StreamDataOutBusy : out std_logic;            -- Busy for stream to host
+
+        -- USB Register interface
+        User_RegAddr : out std_logic_vector(15 downto 0);  -- Register interface address
+        User_RegDataIn : out std_logic_vector(7 downto 0); -- Register write data
+        User_RegDataOut : in std_logic_vector(7 downto 0); -- Register read data
+        User_RegWE : out std_logic;                        -- Write strobe for register
+        User_RegRE : out std_logic;                        -- Read strobe for register
+
+        -- USB Interrupts
+        User_Interrupt : in std_logic;                     -- Interrupt to host PC
+
+        -- SRAM interface
+        User_SRAM_A: in std_logic_vector(22 downto 0);     -- 23-bit address
+        User_SRAM_W: in std_logic;                         -- write strobe active high
+        User_SRAM_R: in std_logic;                         -- read strobe active high
+        User_SRAM_DR_VALID: out std_logic;                 -- read data valid strobe active high
+        User_SRAM_DW: in std_logic_vector(17 downto 0);    -- 18-bit data bus for writing to SRAM
+        User_SRAM_DR: out std_logic_vector(17 downto 0);   -- 18-bit data bus for reading from SRAM
+
+        -- FPGA pin connections
+        -- External USB Controller interface
+        USB_StreamCLK : in std_logic;
+        USB_StreamFIFOADDR : out std_logic_vector(1 downto 0);
+        USB_StreamPKTEND_n : out std_logic;
+        USB_StreamFlags_n : in std_logic_vector(2 downto 0);
+        USB_StreamSLOE_n : out std_logic;
+        USB_StreamSLRD_n : out std_logic;
+        USB_StreamSLWR_n : out std_logic;
+        USB_StreamFX2Rdy : in std_logic;
+        USB_StreamData : inout std_logic_vector(15 downto 0);
+
+        USB_RegCLK : in std_logic;
+        USB_RegAddr : in std_logic_vector(15 downto 0);
+        USB_RegData : inout std_logic_vector(7 downto 0);
+        USB_RegOE_n : in std_logic;
+        USB_RegRD_n : in std_logic;
+        USB_RegWR_n : in std_logic;
+        USB_RegCS_n : in std_logic;
+
+        USB_Interrupt : out std_logic;
+
+        -- External SRAM interface
+        S_CLK: out std_logic;
+        S_A: out std_logic_vector(22 downto 0);
+        S_ADV_LD_N: out std_logic;
+        S_BWA_N: out std_logic;
+        S_BWB_N: out std_logic;
+        S_DA: inout std_logic_vector(8 downto 0);
+        S_DB: inout std_logic_vector(8 downto 0);
+        S_OE_N: out std_logic;
+        S_WE_N: out std_logic
+    );
+ 
+end ZestSC1_Interfaces;
+
+architecture arch of ZestSC1_Interfaces is
+
+component ZestSC1_Host is
+    port (
+        -- FPGA pin connections
+        USB_StreamCLK : in std_logic;
+        USB_StreamFIFOADDR : out std_logic_vector(1 downto 0);
+        USB_StreamPKTEND_n : out std_logic;
+        USB_StreamFlags_n : in std_logic_vector(2 downto 0);
+        USB_StreamSLOE_n : out std_logic;
+        USB_StreamSLRD_n : out std_logic;
+        USB_StreamSLWR_n : out std_logic;
+        USB_StreamFX2Rdy : in std_logic;
+        USB_StreamData : inout std_logic_vector(15 downto 0);
+
+        USB_RegCLK : in std_logic;
+        USB_RegAddr : in std_logic_vector(15 downto 0);
+        USB_RegData : inout std_logic_vector(7 downto 0);
+        USB_RegOE_n : in std_logic;
+        USB_RegRD_n : in std_logic;
+        USB_RegWR_n : in std_logic;
+        USB_RegCS_n : in std_logic;
+
+        USB_Interrupt : out std_logic;
+
+        -- User connections
+        -- General connections
+        User_CLK : out std_logic;
+        User_RST : out std_logic;
+        DCMLocked : out std_logic;
+
+        -- Streaming interface
+        User_StreamBusGrantLength : in std_logic_vector(11 downto 0);
+
+        User_StreamDataIn : out std_logic_vector(15 downto 0);
+        User_StreamDataInWE : out std_logic;
+        User_StreamDataInBusy : in std_logic;
+
+        User_StreamDataOut : in std_logic_vector(15 downto 0);
+        User_StreamDataOutWE : in std_logic;
+        User_StreamDataOutBusy : out std_logic;
+
+        -- Register interface
+        User_RegAddr : out std_logic_vector(15 downto 0);
+        User_RegDataIn : out std_logic_vector(7 downto 0);
+        User_RegDataOut : in std_logic_vector(7 downto 0);
+        User_RegWE : out std_logic;
+        User_RegRE : out std_logic;
+
+        -- Interrupts
+        User_Interrupt : in std_logic
+    );
+end component;
+
+
+-- comment out unused SRAM 
+--component ZestSC1_SRAM is
+--    port (
+--        -- User interface
+--        USER_CLK: in std_logic;                       -- clock from user logic
+--        USER_RESET: in std_logic;                     -- reset
+--        USER_A: in std_logic_vector(22 downto 0);     -- 23-bit address
+--        USER_W: in std_logic;                         -- write strobe active high
+--        USER_R: in std_logic;                         -- read strobe active high
+--        USER_DR_VALID: out std_logic;                 -- read data valid strobe active high
+--        USER_DW: in std_logic_vector(17 downto 0);    -- 18-bit data bus for writing to SRAM
+--        USER_DR: out std_logic_vector(17 downto 0);   -- 18-bit data bus for reading from SRAM
+--
+--        -- ZBT SRAM interface
+--        CLK_SRAM: out std_logic;
+--        S_A: out std_logic_vector(22 downto 0);
+--        S_ADV_LD_N: out std_logic;
+--        S_BWA_N: out std_logic;
+--        S_BWB_N: out std_logic;
+--        S_DA: inout std_logic_vector(8 downto 0);
+--        S_DB: inout std_logic_vector(8 downto 0);
+--        S_OE_N: out std_logic;
+--        S_WE_N: out std_logic
+--    );
+--end component;
+
+signal Clk: std_logic;
+signal Reset: std_logic;
+signal SRAMReset : std_logic;
+signal DCMLocked : std_logic;
+
+-- Preserve IO signals to prevent errors from the UCF file
+-- Comment out all keep attributes in an attempt to see if it
+-- screws ISE 9.1
+--attribute keep : string;
+--attribute keep of USB_StreamCLK: signal is "true";
+--attribute keep of USB_StreamSLRD_n: signal is "true";
+--attribute keep of USB_StreamSLWR_n: signal is "true";
+--attribute keep of USB_StreamSLOE_n: signal is "true";
+--attribute keep of USB_StreamFX2Rdy: signal is "true";
+--attribute keep of USB_StreamFIFOADDR: signal is "true";
+--attribute keep of USB_StreamPKTEND_n: signal is "true";
+--attribute keep of USB_StreamData: signal is "true";
+--attribute keep of USB_StreamFlags_n: signal is "true";
+--
+--attribute keep of USB_RegCLK: signal is "true";
+--attribute keep of USB_RegAddr: signal is "true";
+--attribute keep of USB_RegOE_n: signal is "true";
+--attribute keep of USB_RegRD_n: signal is "true";
+--attribute keep of USB_RegWR_n: signal is "true";
+--attribute keep of USB_RegCS_n: signal is "true";
+--attribute keep of USB_RegData: signal is "true";
+--
+--attribute keep of USB_Interrupt: signal is "true";
+--
+--attribute keep of S_CLK: signal is "true";
+--attribute keep of S_A: signal is "true";
+--attribute keep of S_BWA_N: signal is "true";
+--attribute keep of S_BWB_N: signal is "true";
+--attribute keep of S_DA: signal is "true";
+--attribute keep of S_DB: signal is "true";
+--attribute keep of S_OE_N: signal is "true";
+--attribute keep of S_WE_N: signal is "true";
+--attribute keep of S_ADV_LD_N: signal is "true";
+
+begin
+
+User_CLK <= Clk;
+User_RST <= Reset;
+SRAMReset <= Reset or not DCMLocked;
+
+INST_ZestSC1_Host: ZestSC1_Host 
+    port map (
+        -- FPGA pin connections
+        USB_StreamCLK => USB_StreamCLK,
+        USB_StreamFIFOADDR => USB_StreamFIFOADDR,
+        USB_StreamPKTEND_n => USB_StreamPKTEND_n,
+        USB_StreamFlags_n => USB_StreamFlags_n,
+        USB_StreamSLOE_n => USB_StreamSLOE_n,
+        USB_StreamSLRD_n => USB_StreamSLRD_n,
+        USB_StreamSLWR_n => USB_StreamSLWR_n,
+        USB_StreamFX2Rdy => USB_StreamFX2Rdy,
+        USB_StreamData => USB_StreamData,
+
+        USB_RegCLK => USB_RegCLK,
+        USB_RegAddr => USB_RegAddr,
+        USB_RegData => USB_RegData,
+        USB_RegOE_n => USB_RegOE_n,
+        USB_RegRD_n => USB_RegRD_n,
+        USB_RegWR_n => USB_RegWR_n,
+        USB_RegCS_n => USB_RegCS_n,
+
+        USB_Interrupt => USB_Interrupt,
+
+        -- User connections
+        -- General connections
+        User_CLK => Clk,
+        User_RST => Reset,
+        DCMLocked => DCMLocked,
+
+        -- Streaming interface
+        User_StreamBusGrantLength => User_StreamBusGrantLength,
+
+        User_StreamDataIn => User_StreamDataIn,
+        User_StreamDataInWE => User_StreamDataInWE,
+        User_StreamDataInBusy => User_StreamDataInBusy,
+
+        User_StreamDataOut => User_StreamDataOut,
+        User_StreamDataOutWE => User_StreamDataOutWE,
+        User_StreamDataOutBusy => User_StreamDataOutBusy,
+
+        -- Register interface
+        User_RegAddr => User_RegAddr,
+        User_RegDataIn => User_RegDataIn,
+        User_RegDataOut => User_RegDataOut,
+        User_RegWE => User_RegWE,
+        User_RegRE => User_RegRE,
+
+        -- Interrupts
+        User_Interrupt => User_Interrupt
+    );
+
+-- Comment out SRAM since it isn't needed.
+--INST_SRAM: ZestSC1_SRAM
+--  port map(
+--        -- User interface
+--        USER_CLK => Clk,
+--        USER_RESET => SRAMReset,
+--        USER_A => USER_SRAM_A,
+--        USER_W => USER_SRAM_W,
+--        USER_R => USER_SRAM_R,
+--        USER_DR_VALID => USER_SRAM_DR_VALID,
+--        USER_DW => USER_SRAM_DW,
+--        USER_DR => USER_SRAM_DR,
+--
+--        -- ZBT SRAM interface
+--        CLK_SRAM => S_CLK,
+--        S_A => S_A,    
+--        S_ADV_LD_N => S_ADV_LD_N,
+--        S_BWA_N => S_BWA_N,
+--        S_BWB_N => S_BWB_N,
+--        S_DA => S_DA,
+--        S_DB => S_DB,
+--        S_OE_N => S_OE_N,
+--        S_WE_N => S_WE_N
+--    );
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/clocks_7s_extphy_se.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/clocks_7s_extphy_se.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90c77ffd8e81f354ff8f4bc9b4032b834ee70ce3
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/clocks_7s_extphy_se.vhd
@@ -0,0 +1,151 @@
+-- clocks_7s_extphy_se
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 50MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy_Se is
+	port(
+		sysclk: in std_logic;
+		clko_125: out std_logic;
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;
+		rsto_ipb: out std_logic;
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic
+	);
+
+end clocks_7s_extphy_se;
+
+architecture rtl of clocks_7s_extphy_se is
+	
+	signal dcm_locked, sysclk_i, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b, clk_200_i: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+	ibufgds0: IBUFG port map(
+		i => sysclk,
+		o => sysclk_i
+	);
+	
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clko_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	bufg200: BUFG port map(
+		i => clk_200_i,
+		o => clko_200
+	);	
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 20.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90.0,
+			clkout3_divide => 32,
+			clkout4_divide => 5,
+			clkin1_period => 20.0
+		)
+		port map(
+			clkin1 => sysclk_i,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk_125_90_i,
+			clkout3 => clk_ipb_i,
+			clkout4 => clk_200_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk_i,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk_i)
+	begin
+		if rising_edge(sysclk_i) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/delay.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/delay.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d819105910f185ee80ddc60624f109f62a3303e9
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/delay.vhd
@@ -0,0 +1,52 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+entity delay is
+  
+  generic (
+    length : integer := 1);  -- number of clock cycles to delay signal
+  port (
+    clock  : in  std_logic;             -- rising edge active
+    input  : in  std_logic;
+    output : out std_logic);
+
+end delay;
+
+architecture rtl of delay is
+
+  component dtype
+    port (
+      Q : out std_logic;
+      C   : in std_logic;
+      CLR : in std_logic;
+      D   : in std_logic;
+      CE  : in std_logic;
+      PRE : in std_logic
+      );
+  end component;
+
+  signal internal_signal : std_logic_vector( length downto 0);  -- signals along the pipe-line
+  
+begin  -- rtl
+
+  internal_signal(0) <= input;
+  
+  pipeline: for N in 1 to length generate
+
+    pipelinestage: dtype
+      port map (
+        q => internal_signal(N),
+        c => clock ,
+        clr => '0' ,
+        d => internal_signal(N-1),
+        ce => '1' ,
+        pre => '0'
+        );
+    
+  end generate pipeline;
+
+  output <= internal_signal(length);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/delay_word.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/delay_word.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e520714df1070560e516c3299665f80b89b3167a
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/delay_word.vhd
@@ -0,0 +1,43 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use IEEE.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+entity delay_word is
+  
+  generic (
+    length : integer := 1 ; -- number of clock cycles to delay signal
+    width : integer := 1 );             -- width of bus
+  port (
+    clock  : in  std_logic;             -- rising edge active
+    input  : in  std_logic_vector(width-1 downto 0);
+    output : out std_logic_vector(width-1 downto 0)
+    );
+
+end delay_word;
+
+architecture rtl of delay_word is
+
+
+  subtype DataWord is std_logic_vector( width-1 downto 0 );
+  type WordArray is array (length downto 0) of DataWord;
+  signal InternalSignal : WordArray;  -- signals along the pipe-line
+  
+begin  -- rtl
+
+  InternalSignal(0) <= input;
+  
+  pipeline: for N in 1 to length generate
+
+    pipelinestage: process (clock , InternalSignal(N-1))
+    begin  -- process pipelinestage
+      if rising_edge(clock) then
+        InternalSignal(N) <= InternalSignal(N-1);
+      end if;      
+    end process pipelinestage;
+    
+  end generate pipeline;
+
+  output <= InternalSignal(length);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/dtype.vhdl b/AIDA_tlu/legacy/EUDETdummy/hdl/dtype.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d2dd17107a7fc5bafbfa1b675de11fd10f2391d1
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/dtype.vhdl
@@ -0,0 +1,34 @@
+----- CELL dtype                       -----
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+-- use IEEE.VITAL_Timing.all;
+
+entity dtype is
+
+  port(
+    Q : out std_logic;
+    C   : in std_logic;
+    CLR : in std_logic;
+    D   : in std_logic;
+	 CE  : in std_logic;
+    PRE : in std_logic
+    );
+
+end dtype;
+
+architecture dtype_V of dtype is
+begin
+
+  VITALBehavior         : process(C, CLR, PRE)
+  begin
+
+    if (CLR = '1') then
+      Q <= '0';
+    elsif (PRE = '1') then
+      Q <= '1';
+    elsif (rising_edge(C) and CE='1') then
+      Q <= D ;
+    end if;
+  end process;
+end dtype_V;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/enclustra_ax3_pm3_infra.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/enclustra_ax3_pm3_infra.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df07ba1ef1daed5d435e98f6807ffed65d8c2c7c
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/enclustra_ax3_pm3_infra.vhd
@@ -0,0 +1,131 @@
+-- enclustra_ax3_pm3_infra
+--
+-- All board-specific stuff goes here
+--
+-- Dave Newbold, June 2013---
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity enclustra_ax3_pm3_infra is
+	port(
+		sysclk: in std_logic; -- ??? board crystal clock
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		rst_125_o: out std_logic;
+		clk_200_o: out std_logic;
+		--clk_aux_o: out std_logic; -- 40MHz generated clock
+		--rst_aux_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		leds: out std_logic_vector(1 downto 0); -- status LEDs
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end enclustra_ax3_pm3_infra;
+
+architecture rtl of enclustra_ax3_pm3_infra is
+
+	signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	signal led_p: std_logic_vector(0 downto 0);
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_7s_extphy_se
+		port map(
+			sysclk => sysclk,
+			clko_125 => clk125,
+			clko_125_90 => clk125_90,
+			clko_200 => clk200,
+			clko_ipb => clk_ipb_i,
+			locked => locked,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl,
+			onehz => onehz
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	rst_125_o <= rst125;
+	clk_200_o <= clk200;
+	
+	stretch: entity work.led_stretcher
+		generic map(
+			WIDTH => 1
+		)
+		port map(
+			clk => clk125,
+			d(0) => pkt,
+			q => led_p
+		);
+	leds <= (led_p(0), locked and onehz);
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_7s_rgmii
+		port map(
+			clk125 => clk125,
+			clk125_90 => clk125_90,
+			clk200 => clk200,
+			rst => rst125,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			pkt => pkt
+		);
+
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/eth_7s_rgmii.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/eth_7s_rgmii.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3e2e16709360b5ebcd8a9337e77cc9e881c516ba
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/eth_7s_rgmii.vhd
@@ -0,0 +1,184 @@
+-- Contains the instantiation of the Xilinx MAC & PHY interface for RGMII
+--
+-- Do not change signal names in here without corresponding alteration to the timing contraints file
+--
+-- Dave Newbold, October 2016
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+use work.emac_hostbus_decl.all;
+
+entity eth_7s_rgmii is
+	port(
+		clk125: in std_logic;
+		clk125_90: in std_logic;
+		clk200: in std_logic;
+		rst: in std_logic;
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		tx_data: in std_logic_vector(7 downto 0);
+		tx_valid: in std_logic;
+		tx_last: in std_logic;
+		tx_error: in std_logic;
+		tx_ready: out std_logic;
+		rx_data: out std_logic_vector(7 downto 0);
+		rx_valid: out std_logic;
+		rx_last: out std_logic;
+		rx_error: out std_logic;
+		hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
+		hostbus_out: out emac_hostbus_out;
+		status: out std_logic_vector(3 downto 0)
+	);
+
+end eth_7s_rgmii;
+
+architecture rtl of eth_7s_rgmii is
+
+	COMPONENT temac_gbe_v9_rgmii
+		PORT (
+			gtx_clk : IN STD_LOGIC;
+			gtx_clk90 : IN STD_LOGIC;
+			glbl_rstn : IN STD_LOGIC;
+			rx_axi_rstn : IN STD_LOGIC;
+			tx_axi_rstn : IN STD_LOGIC;
+			rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
+			rx_statistics_valid : OUT STD_LOGIC;
+			rx_mac_aclk : OUT STD_LOGIC;
+			rx_reset : OUT STD_LOGIC;
+			rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			rx_axis_mac_tvalid : OUT STD_LOGIC;
+			rx_axis_mac_tlast : OUT STD_LOGIC;
+			rx_axis_mac_tuser : OUT STD_LOGIC;
+			tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			tx_statistics_valid : OUT STD_LOGIC;
+			tx_mac_aclk : OUT STD_LOGIC;
+			tx_reset : OUT STD_LOGIC;
+			tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_axis_mac_tvalid : IN STD_LOGIC;
+			tx_axis_mac_tlast : IN STD_LOGIC;
+			tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+			tx_axis_mac_tready : OUT STD_LOGIC;
+			pause_req : IN STD_LOGIC;
+			pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+			speedis100 : OUT STD_LOGIC;
+			speedis10100 : OUT STD_LOGIC;
+			rgmii_txd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_tx_ctl : OUT STD_LOGIC;
+			rgmii_txc : OUT STD_LOGIC;
+			rgmii_rxd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_rx_ctl : IN STD_LOGIC;
+			rgmii_rxc : IN STD_LOGIC;
+			inband_link_status : OUT STD_LOGIC;
+			inband_clock_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			inband_duplex_status : OUT STD_LOGIC;
+			rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
+			tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT mac_fifo_axi4
+	  PORT (
+		 m_aclk : IN STD_LOGIC;
+		 s_aclk : IN STD_LOGIC;
+		 s_aresetn : IN STD_LOGIC;
+		 s_axis_tvalid : IN STD_LOGIC;
+		 s_axis_tready : OUT STD_LOGIC;
+		 s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 s_axis_tlast : IN STD_LOGIC;
+		 s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		 m_axis_tvalid : OUT STD_LOGIC;
+		 m_axis_tready : IN STD_LOGIC;
+		 m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 m_axis_tlast : OUT STD_LOGIC;
+		 m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+	  );
+	END COMPONENT;
+	
+	signal rx_data_e: std_logic_vector(7 downto 0);
+	signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
+	signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
+	
+begin
+
+	idelayctrl0: idelayctrl port map(
+		refclk => clk200,
+		rst => rst
+	);
+	
+	rstn <= not rst;
+
+	emac0: temac_gbe_v9_rgmii
+		port map(
+			gtx_clk => clk125,
+			gtx_clk90 => clk125_90,
+			glbl_rstn => rstn,
+			rx_axi_rstn => '1',
+			tx_axi_rstn => '1',
+			rx_statistics_vector => open,
+			rx_statistics_valid => open,		
+			rx_mac_aclk => rx_clk_e,
+			rx_reset => rx_rst_e,
+			rx_axis_mac_tdata => rx_data_e,
+			rx_axis_mac_tvalid => rx_valid_e,
+			rx_axis_mac_tlast => rx_last_e,
+			rx_axis_mac_tuser => rx_user_e,
+			tx_ifg_delay => X"00",
+			tx_statistics_vector => open,
+			tx_statistics_valid => open,	
+			tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
+			tx_reset => open,
+			tx_axis_mac_tdata => tx_data,
+			tx_axis_mac_tvalid => tx_valid,
+			tx_axis_mac_tlast => tx_last,
+			tx_axis_mac_tuser(0) => tx_error,
+			tx_axis_mac_tready => tx_ready,
+			pause_req => '0',
+			pause_val => X"0000",
+			speedis100 => open,
+			speedis10100 => open,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			inband_link_status => status(0),
+			inband_clock_speed => status(3 downto 2),
+			inband_duplex_status => status(1),
+			rx_configuration_vector => X"0000_0000_0000_0000_0812",
+			tx_configuration_vector => X"0000_0000_0000_0000_0012"
+		);
+	
+	rx_user_ef(0) <= rx_user_e;
+	rx_error <= rx_user_f(0);
+	rx_rst_en <= not rx_rst_e;
+	
+	fifo: mac_fifo_axi4
+		port map(
+			m_aclk => clk125,
+			s_aclk => rx_clk_e,
+			s_aresetn => rx_rst_en,
+			s_axis_tvalid => rx_valid_e,
+			s_axis_tready => open,
+			s_axis_tdata => rx_data_e,
+			s_axis_tlast => rx_last_e,
+			s_axis_tuser => rx_user_ef,
+			m_axis_tvalid => rx_valid,
+			m_axis_tready => '1',
+			m_axis_tdata => rx_data,
+			m_axis_tlast => rx_last,
+			m_axis_tuser => rx_user_f
+		); -- Clock domain crossing FIFO
+
+	hostbus_out.hostrddata <= (others => '0');
+	hostbus_out.hostmiimrdy <= '0';
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb6b10104903070a5365064dee8d9d822d64cf42
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg.vhd
@@ -0,0 +1,27 @@
+--=============================================================================
+--! @file fmcTLU_pkg.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:44:31 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE fmcTLU IS
+  
+  constant c_NUM_TIME_BITS : natural := 5;
+  constant c_NUM_TRIG_INPUTS : natural := 4;
+  constant c_EVENT_DATA_WIDTH : natural := 32;
+  constant c_DATA_WIDTH : natural := 32;
+  
+  subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
+  --type    t_triggerTimeArray is array(natural range <>) of t_triggerTime;
+  type    t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+  type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
+  
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg_body.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg_body.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9437776d393daa1b6e790f3d5470fb09344259bc
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/fmcTLU_pkg_body.vhd
@@ -0,0 +1,13 @@
+--=============================================================================
+--! @file fmcTLU_pkg_body.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:45:08 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+PACKAGE BODY fmcTLU IS
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_bit_ctrl.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_bit_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0dc4e9af1fdee8b4fccea67129d50fc24fedb46
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_bit_ctrl.vhd
@@ -0,0 +1,492 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------              
+
+
+--/////////////////////////////////////
+--// Bit controller section
+--/////////////////////////////////////
+--//
+--// Translate simple commands into SCL/SDA transitions
+--// Each command has 5 states, A/B/C/D/idle
+--//
+--// start:	SCL	~~~~~~~~~~\____
+--//	SDA	~~~~~~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// repstart	SCL	____/~~~~\___
+--//	SDA	__/~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// stop	SCL	____/~~~~~~~~
+--//	SDA	==\____/~~~~~
+--//		 x | A | B | C | D | i
+--//
+--//- write	SCL	____/~~~~\____
+--//	SDA	==X=========X=
+--//		 x | A | B | C | D | i
+--//
+--//- read	SCL	____/~~~~\____
+--//	SDA	XXXX=====XXXX
+--//		 x | A | B | C | D | i
+--//
+--
+--// Timing:     Normal mode      Fast mode
+--///////////////////////////////////////////////////////////////////////
+--// Fscl        100KHz           400KHz
+--// Th_scl      4.0us            0.6us   High period of SCL
+--// Tl_scl      4.7us            1.3us   Low period of SCL
+--// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+--// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+--// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+--//
+--
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_bit_ctrl is
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+        
+ 
+end;
+
+architecture arch of i2c_master_bit_ctrl is
+
+--attribute UGROUP:string;                                   
+--attribute UGROUP of arch : label is "bit_group"; 
+
+
+signal sSCL, sSDA : std_logic;	-- synchronized SCL and SDA inputs
+signal dscl_oen : std_logic;	-- delayed scl_oen
+signal sda_chk : std_logic;		-- check SDA output (Multi-master arbitration)
+signal clk_en : std_logic;		-- clock generation signals
+signal slave_wait : std_logic;
+
+-- bus status controller signals
+signal dSCL,dSDA : std_logic;
+signal sta_condition : std_logic;
+signal sto_condition : std_logic;
+signal cmd_stop : std_logic;
+
+signal cnt : std_logic_vector(15 downto 0);	-- clock divider counter
+
+signal scl_oen_int : std_logic;
+signal sda_oen_int : std_logic;
+signal busy_int : std_logic;
+signal al_int : std_logic;
+
+-- state machine variable
+signal c_state : std_logic_vector(16 downto 0);
+
+constant idle 		: std_logic_vector(16 downto 0) := "00000000000000000";
+constant start_a 	: std_logic_vector(16 downto 0) := "00000000000000001";
+constant start_b 	: std_logic_vector(16 downto 0) := "00000000000000010";
+constant start_c 	: std_logic_vector(16 downto 0) := "00000000000000100";
+constant start_d 	: std_logic_vector(16 downto 0) := "00000000000001000";
+constant start_e 	: std_logic_vector(16 downto 0) := "00000000000010000";
+constant stop_a 	: std_logic_vector(16 downto 0) := "00000000000100000";
+constant stop_b	 	: std_logic_vector(16 downto 0) := "00000000001000000";
+constant stop_c	 	: std_logic_vector(16 downto 0) := "00000000010000000";
+constant stop_d 	: std_logic_vector(16 downto 0) := "00000000100000000";
+constant rd_a	 	: std_logic_vector(16 downto 0) := "00000001000000000";
+constant rd_b 		: std_logic_vector(16 downto 0) := "00000010000000000";
+constant rd_c 		: std_logic_vector(16 downto 0) := "00000100000000000";
+constant rd_d 		: std_logic_vector(16 downto 0) := "00001000000000000";
+constant wr_a 		: std_logic_vector(16 downto 0) := "00010000000000000";
+constant wr_b 		: std_logic_vector(16 downto 0) := "00100000000000000";
+constant wr_c 		: std_logic_vector(16 downto 0) := "01000000000000000";
+constant wr_d 		: std_logic_vector(16 downto 0) := "10000000000000000";
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+begin
+
+scl_oen <= scl_oen_int;
+sda_oen <= sda_oen_int;
+
+-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+-- delay scl_oen
+process(clk)
+begin
+	if rising_edge(clk) then
+		dscl_oen <= scl_oen_int;
+	end if;
+end process;
+
+slave_wait <= '1' when ((dscl_oen = '1') AND (sSCL = '0')) else '0';
+
+-- generate clk enable signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cnt <= (others => '0');
+		clk_en <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cnt <= (others => '0');
+			clk_en <= '1';
+		elsif ((cnt = "0000000000000000") OR (ena = '0')) then
+			cnt <= clk_cnt;
+			clk_en <= '1';
+		elsif (slave_wait = '1') then
+			cnt <= cnt;
+			clk_en <= '0';
+		else
+			cnt <= cnt - '1';
+			clk_en <= '0';
+		end if;
+	end if;
+end process;
+
+-- synchronize SCL and SDA inputs
+-- reduce metastability risc
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sSCL <= '1';
+		sSDA <= '1';
+		dSCL <= '1';
+		dSDA <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sSCL <= '1';
+			sSDA <= '1';
+			dSCL <= '1';
+			dSDA <= '1';
+		else
+			dSCL <= sSCL;
+			dSDA <= sSDA;
+                        -- Don't need to treat 'H' if separate I and O
+			-- if ((scl_i = '1') OR (scl_i = 'H')) then
+                        if (scl_i = '1')  then
+				sSCL <= '1';
+			else
+				sSCL <= '0';
+			end if;
+			-- if ((sda_i = '1') OR (sda_i = 'H')) then
+                        if (sda_i = '1')  then
+				sSDA <= '1';
+			else
+				sSDA <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+-- detect start condition => detect falling edge on SDA while SCL is high
+-- detect stop condition => detect rising edge on SDA while SCL is high
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sta_condition <= '0';
+		sto_condition <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sta_condition <= '0';
+			sto_condition <= '0';
+		else
+			sta_condition <= NOT(sSDA) AND dSDA AND sSCL;
+			sto_condition <= sSDA AND NOT(dSDA) AND sSCL;
+		end if;
+	end if;
+end process;
+
+-- generate i2c bus busy signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		busy_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			busy_int <= '0';
+		else
+			busy_int <= (sta_condition OR busy_int) AND NOT(sto_condition);
+		end if;
+	end if;
+end process;
+
+busy <= busy_int;
+
+-- generate arbitration lost signal
+-- aribitration lost when:
+-- 1) master drives SDA high, but the i2c bus is low
+-- 2) stop detected while not requested
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cmd_stop <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cmd_stop <= '0';
+		elsif (clk_en = '1') then
+			if (cmd = I2C_CMD_STOP) then
+				cmd_stop <= '1';
+			else
+				cmd_stop <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		al_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			al_int <= '0';
+		else
+			if (((sda_chk = '1') AND (sSDA = '0') AND (sda_oen_int = '1')) OR ((c_state /= idle) AND (sto_condition = '1') AND (cmd_stop = '0'))) then
+				al_int <= '1';
+			else
+				al_int <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+al <= al_int;
+
+
+-- generate dout signal (store SDA on rising edge of SCL)
+process(clk)
+begin
+	if rising_edge(clk) then
+		if ((sSCL = '1') AND (dSCL = '0')) then
+			dout <= sSDA;
+		end if;
+	end if;
+end process;
+
+
+--generate state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		c_state <= idle;
+		cmd_ack <= '0';
+		scl_oen_int <= '1';
+		sda_oen_int <= '1';
+		sda_chk <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (al_int = '1')) then
+			c_state <= idle;
+			cmd_ack <= '0';
+			scl_oen_int <= '1';
+			sda_oen_int <= '1';
+			sda_chk <= '0';
+		else
+			cmd_ack <= '0';	--default no command acknowledge + assert cmd_ack only 1clk cycle
+			if (clk_en = '1') then
+				case (c_state) is
+					when idle =>
+							case (cmd) is
+								when I2C_CMD_START	=> c_state <= start_a;
+								when I2C_CMD_STOP	=> c_state <= stop_a;
+								when I2C_CMD_WRITE	=> c_state <= wr_a;
+								when I2C_CMD_READ	=> c_state <= rd_a;
+								when others			=> c_state <= idle;
+							end case;
+
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= sda_oen_int;  -- keep SDA in same state
+							sda_chk <= '0';              -- don't check SDA output
+					when start_a =>          -- start
+							c_state <= start_b;
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_b =>
+							c_state <= start_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_c =>
+							c_state <= start_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_d =>
+							c_state <= start_e;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_e =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_a =>          -- stop
+							c_state <= stop_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_b =>
+							c_state <= stop_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_c =>
+							c_state <= stop_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_a =>          -- read
+							c_state <= rd_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '1';          -- tri-state SDA
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_b =>
+							c_state <= rd_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_c =>
+							c_state <= rd_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when wr_a =>          -- write
+							c_state <= wr_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= din;          -- set SDA
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when wr_b =>
+							c_state <= wr_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= din;          -- keep SDA
+							sda_chk <= '1';              -- check SDA output
+					when wr_c =>
+							c_state <= wr_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= din;
+							sda_chk <= '1';              -- check SDA output
+					when wr_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= din;
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when others => NULL;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- assign scl and sda output (always gnd)
+scl_o <= '0';
+sda_o <= '0';
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_byte_ctrl.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_byte_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f52195741d35d657cf7dad6d66f708bda9d46b28
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_byte_ctrl.vhd
@@ -0,0 +1,286 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master byte-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-----------------------------------------------------------------------
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                        
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------  
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_byte_ctrl is
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end;
+
+architecture arch of i2c_master_byte_ctrl is
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+
+constant ST_IDLE	: std_logic_vector(4 downto 0) := "00000";
+constant ST_START	: std_logic_vector(4 downto 0) := "00001";
+constant ST_READ	: std_logic_vector(4 downto 0) := "00010";
+constant ST_WRITE	: std_logic_vector(4 downto 0) := "00100";
+constant ST_ACK		: std_logic_vector(4 downto 0) := "01000";
+constant ST_STOP	: std_logic_vector(4 downto 0) := "10000";
+
+signal c_state : std_logic_vector(4 downto 0);
+
+
+signal go : std_logic;
+signal dcnt : std_logic_vector(2 downto 0);
+signal cnt_done : std_logic;
+
+signal sr : std_logic_vector(7 downto 0); --8bit shift register
+signal shift, ld : std_logic;
+
+signal cmd_ack_int : std_logic;
+
+
+begin
+
+go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
+dout <= sr;
+
+-- generate shift register
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sr <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sr <= (others => '0');
+		elsif (ld = '1') then
+			sr <= din;
+		elsif (shift = '1') then
+			sr <= sr(6 downto 0) & core_rxd;
+		end if;
+	end if;
+end process;
+
+-- generate counter
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		dcnt <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			dcnt <= (others => '0');
+		elsif (ld = '1') then
+			dcnt <= "111";
+		elsif (shift = '1') then
+			dcnt <= dcnt - '1';
+		end if;
+	end if;
+end process;
+
+cnt_done <= '1' when (dcnt = "000") else '0';
+
+-- state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		core_cmd <= I2C_CMD_NOP;
+		core_txd <= '0';
+		shift <= '0';
+		ld <= '0';
+		cmd_ack_int <= '0';
+		c_state <= ST_IDLE;
+		ack_out <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (i2c_al = '1')) then
+			core_cmd <= I2C_CMD_NOP;
+			core_txd <= '0';
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+			c_state <= ST_IDLE;
+			ack_out <= '0';
+		else
+			-- initially reset all signals
+			core_txd <= sr(7);
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+
+			case (c_state) is
+				when ST_IDLE =>
+						if (go = '1') then
+							if (start = '1') then
+								c_state <= ST_START;
+								core_cmd <= I2C_CMD_START;
+							elsif (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							elsif (write = '1') then
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_START =>
+						if (core_ack = '1') then
+							if (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_WRITE =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;		-- stay in same state
+								core_cmd <= I2C_CMD_WRITE;	-- write next bit
+								shift <= '1';
+							end if;
+						end if;
+				when ST_READ =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_READ;			-- stay in same state
+								core_cmd <= I2C_CMD_READ;	-- read next bit
+								shift <= '1';
+							end if;
+							shift <= '1';
+							core_txd <= ack_in;
+						end if;
+				when ST_ACK =>
+						if (core_ack = '1') then
+							if (stop = '1') then
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							else
+								c_state <= ST_IDLE;
+								core_cmd <= I2C_CMD_NOP;
+								-- generate command acknowledge signal
+								cmd_ack_int <= '1';
+							end if;
+							-- assign ack_out output to bit_controller_rxd (contains last received bit)
+							ack_out <= core_rxd;
+							core_txd <= '1';
+						else
+							core_txd <= ack_in;
+						end if;
+				when ST_STOP =>
+						if (core_ack = '1') then
+							c_state <= ST_IDLE;
+							core_cmd <= I2C_CMD_NOP;
+							-- generate command acknowledge signal
+							cmd_ack_int <= '1';
+						end if;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+cmd_ack <= cmd_ack_int;
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_registers.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_registers.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..620e226cd1582dc3f8ed20c3dbd6dd98f42cf127
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_registers.vhd
@@ -0,0 +1,196 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master registers             ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------    
+-- --------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_registers is
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end;
+
+architecture arch of i2c_master_registers is
+
+
+signal ctr_int : std_logic_vector(7 downto 0);
+signal cr_int : std_logic_vector(7 downto 0);
+
+signal al : std_logic;			-- status register arbitration lost bit
+signal rxack : std_logic;		-- received aknowledge from slave
+signal tip : std_logic;			-- transfer in progress
+signal irq_flag : std_logic;	-- interrupt pending flag
+
+begin
+
+-- generate prescale regisres, control registers, and transmit register
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		prer <= (others => '1');
+		ctr_int <= (others => '0');
+		txr <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			prer <= (others => '1');
+			ctr_int <= (others => '0');
+			txr <= (others => '0');
+		elsif (wb_wacc = '1') then
+			case (wb_adr_i) is
+				when "000" => prer(7 downto 0)	<= wb_dat_i;
+				when "001" => prer(15 downto 8)	<= wb_dat_i;
+				when "010" => ctr_int			<= wb_dat_i;
+				when "011" => txr				<= wb_dat_i;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+ctr <= ctr_int;
+
+-- generate command register (special case)
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		cr_int <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			cr_int <= (others => '0');
+		elsif (wb_wacc = '1') then
+			if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
+				cr_int <= wb_dat_i;
+			end if;
+		else
+			if ((done = '1') OR (i2c_al = '1')) then
+				cr_int(7 downto 4) <= "0000";	-- clear command b
+			end if;							-- or when aribitr
+			cr_int(2 downto 1) <= "00";			-- reserved bits
+			cr_int(0) <= '0';					-- clear IRQ_ACK b
+		end if;
+	end if;
+end process;
+
+cr <= cr_int;
+
+-- generate status register block + interrupt request signal
+-- each output will be assigned to corresponding sr register locations on top level
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		al 			<= '0';
+		rxack 		<= '0';
+		tip 		<= '0';
+		irq_flag	<= '0';
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			al 			<= '0';
+			rxack 		<= '0';
+			tip 		<= '0';
+			irq_flag	<= '0';
+		else
+			al			<= i2c_al OR (al AND NOT(cr_int(7)));
+			rxack		<= irxack;
+			tip			<= (cr_int(5) OR cr_int(4));
+			irq_flag	<= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
+		end if;
+	end if;
+end process;
+
+sr(7)	 		<= rxack;
+sr(6)			<= i2c_busy;
+sr(5)			<= al;
+sr(4 downto 2)	<= "000"; -- reserved
+sr(1)			<= tip;
+sr(0)			<= irq_flag;
+
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_rtl.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d0bb973aa56b1e35107d8d22fd37574f7e7eed6
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_rtl.vhd
@@ -0,0 +1,97 @@
+--=============================================================================
+--! @file i2c_master_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.i2c_master.rtl
+--
+--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
+--! are bundled together in a record\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 17:22:12 11/30/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY i2c_master IS
+   PORT( 
+      i2c_scl_i     : IN     std_logic;
+      i2c_sda_i     : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;    -- Signals from IPBus core to slave
+      ipbus_reset_i : IN     std_logic;
+      i2c_scl_enb_o : OUT    std_logic;
+      i2c_sda_enb_o : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus     -- signals from slave to IPBus core
+   );
+
+-- Declarations
+
+END ENTITY i2c_master ;
+
+--
+ARCHITECTURE rtl OF i2c_master IS
+  
+  --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
+  
+BEGIN
+  
+  --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
+  --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
+
+  i2c_interface: entity work.i2c_master_top port map(
+                wb_clk_i => ipbus_clk_i,
+                wb_rst_i => ipbus_reset_i,
+                arst_i => '1',
+                wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
+                wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
+                wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
+                wb_we_i => ipbus_i.ipb_write,
+                wb_stb_i => ipbus_i.ipb_strobe,
+                wb_cyc_i => '1',
+                wb_ack_o => ipbus_o.ipb_ack,
+                wb_inta_o => open,
+                scl_pad_i => i2c_scl_i,
+                scl_pad_o => open,
+                scl_padoen_o => i2c_scl_enb_o,
+                sda_pad_i => i2c_sda_i,
+                sda_pad_o => open,
+                sda_padoen_o => i2c_sda_enb_o
+        );
+        
+  
+  ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
+  ipbus_o.ipb_err <= '0'; -- never return an error.
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_top.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6f0aabbb39ea9507a6183182169d36ad85039a1
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/i2c/i2c_master_top.vhd
@@ -0,0 +1,344 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-------------------------------------------------------------------------------
+-- Changes at University of bristol:
+-- V1.0A|D.G.C   | 5/11     | Changed name and ports to fit OC original
+-- --------------------------------------------------------------------    
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_top is
+  generic (
+		ARST_LVL : integer := 0
+		);
+  port (
+        wb_clk_i : in  std_logic;
+        wb_rst_i : in  std_logic;
+        arst_i   : in  std_logic;
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_dat_o : out std_logic_vector(7 downto 0);
+        wb_we_i  : in  std_logic;
+        wb_stb_i : in  std_logic;
+        wb_cyc_i : in  std_logic;
+        wb_ack_o : out std_logic;
+        wb_inta_o: out std_logic;
+        scl_pad_i: in std_logic;
+        scl_pad_o: out std_logic;
+        scl_padoen_o: out std_logic;
+        sda_pad_i: in std_logic;
+        sda_pad_o: out std_logic;
+        sda_padoen_o: out std_logic
+--        scl      : inout std_logic;
+--        sda      : inout std_logic
+        );
+end;
+
+architecture arch of i2c_master_top is
+
+component i2c_master_bit_ctrl
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+end component;
+
+component i2c_master_byte_ctrl
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end component;
+
+component i2c_master_registers
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end component;
+
+
+signal prer : std_logic_vector(15 downto 0);
+signal ctr : std_logic_vector(7 downto 0);
+signal txr : std_logic_vector(7 downto 0);
+signal rxr : std_logic_vector(7 downto 0);
+signal cr : std_logic_vector(7 downto 0);
+signal sr : std_logic_vector(7 downto 0);
+
+signal done : std_logic;
+signal core_en : std_logic;
+signal ien : std_logic;
+signal irxack : std_logic;
+signal irq_flag : std_logic;
+signal i2c_busy : std_logic;
+signal i2c_al : std_logic;
+
+signal core_cmd : std_logic_vector(3 downto 0);
+signal core_txd : std_logic;
+signal core_ack, core_rxd : std_logic;
+
+-- Don't need these signals, since passing them through
+-- component interface
+--signal scl_pad_i : std_logic;
+--signal scl_pad_o : std_logic;
+--signal scl_padoen_o : std_logic;
+--
+--signal sda_pad_i : std_logic;
+--signal sda_pad_o : std_logic;
+--signal sda_padoen_o : std_logic;
+
+signal rst_i : std_logic;
+
+signal sta : std_logic;
+signal sto : std_logic;
+signal rd : std_logic;
+signal wr : std_logic;
+signal ack : std_logic;
+signal iack : std_logic;
+
+signal wb_ack_o_int : std_logic;
+
+signal wb_wacc : std_logic;
+signal acki : std_logic;
+
+begin
+
+  -- Don't need to copy these signal - passing through
+  -- component interface
+--scl_pad_i <= scl;
+--sda_pad_i <= sda;
+
+rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
+
+wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
+
+sta <= cr(7);
+sto <= cr(6);
+rd <= cr(5);
+wr <= cr(4);
+ack <= cr(3);
+acki <= cr(0);
+
+core_en <= ctr(7);
+ien <= ctr(6);
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
+	end if;
+end process;
+
+wb_ack_o <= wb_ack_o_int;
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		case (wb_adr_i) is
+			when "000" => wb_dat_o <= prer(7 downto 0);
+			when "001" => wb_dat_o <= prer(15 downto 8);
+			when "010" => wb_dat_o <= ctr;
+			when "011" => wb_dat_o <= rxr;
+			when "100" => wb_dat_o <= sr;
+			when "101" => wb_dat_o <= txr;
+			when "110" => wb_dat_o <= cr;
+			when "111" => wb_dat_o <= "00000000";
+			when others => NULL;
+		end case;
+	end if;
+end process;
+
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		wb_inta_o <= '0';
+	elsif rising_edge(wb_clk_i) then
+		wb_inta_o <= sr(0) AND ien;
+	end if;
+end process;
+
+
+
+byte_controller: i2c_master_byte_ctrl port map(
+	clk 		=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	clk_cnt		=> prer,
+	start		=> sta,
+	stop		=> sto,
+	read		=> rd,
+	write		=> wr,
+	ack_in		=> ack,
+	din			=> txr,
+	cmd_ack		=> done,
+	ack_out		=> irxack,
+	dout		=> rxr,
+	i2c_al		=> i2c_al,
+	core_cmd	=> core_cmd,
+	core_ack	=> core_ack,
+	core_txd	=> core_txd,
+	core_rxd	=> core_rxd);
+
+bit_controller: i2c_master_bit_ctrl port map(
+	clk			=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	ena			=> core_en,
+	clk_cnt		=> prer,
+	cmd			=> core_cmd,
+	cmd_ack		=> core_ack,
+	busy		=> i2c_busy,
+	al			=> i2c_al,
+	din			=> core_txd,
+	dout		=> core_rxd,
+	scl_i		=> scl_pad_i,
+	scl_o		=> scl_pad_o,
+	scl_oen		=> scl_padoen_o,
+	sda_i		=> sda_pad_i,
+	sda_o		=> sda_pad_o,
+	sda_oen		=> sda_padoen_o);
+
+registers: i2c_master_registers port map(
+	wb_clk_i	=> wb_clk_i,
+	rst_i		=> rst_i,
+	wb_rst_i	=> wb_rst_i,
+	wb_dat_i	=> wb_dat_i,
+	wb_wacc		=> wb_wacc,
+	wb_adr_i	=> wb_adr_i,
+	i2c_al		=> i2c_al,
+	i2c_busy	=> i2c_busy,
+	done		=> done,
+	irxack		=> irxack,
+	prer		=> prer,
+	ctr			=> ctr,
+	txr			=> txr,
+	cr			=> cr,
+	sr			=> sr);
+
+
+-- edited from Lattice original to pass uni-directional signals
+--scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
+--sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
+
+end arch;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_addr_decode.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_addr_decode.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dc630e87a5945dbbdfb05c850418867e503ddf39
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_addr_decode.vhd
@@ -0,0 +1,50 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+    variable sel : integer;
+  begin
+		if    std_match(addr, "-----------------------0001-----") then
+			sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
+		elsif std_match(addr, "-----------------------0010-----") then
+			sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
+		elsif std_match(addr, "-----------------------0011-----") then
+			sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
+		elsif std_match(addr, "-----------------------0100-----") then
+			sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
+		elsif std_match(addr, "-----------------------0101-----") then
+			sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
+		elsif std_match(addr, "-----------------------0110-----") then
+			sel := 5; -- i2c_master / base 000000c0 / mask 00000007
+		elsif std_match(addr, "-----------------------1010-----") then
+                        sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
+                elsif std_match(addr, "-----------------------1011-----") then
+                        sel := 7; -- TPix3_iface   / base 00000160 / mask 0000001f
+		elsif std_match(addr, "-----------------------0000-----") then
+			sel := 8; -- version / base 00000000 / mask 00000000
+		else
+			sel := 99;
+		end if;
+		return sel;
+	end ipbus_addr_sel;
+ 
+end ipbus_addr_decode;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a315ed0358c7662662ddd26e751043300ed6937c
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_ipbus_example.vhd
@@ -0,0 +1,69 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+-- 
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_ipbus_example is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_ipbus_example;
+
+package body ipbus_decode_ipbus_example is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "-----------------000----------0-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "-----------------000----------1-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    --elsif std_match(addr, "-----------------001------------") then
+      --sel := ipbus_sel_t(to_unsigned(N_SLV_RAM, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    --elsif std_match(addr, "-----------------010----------0-") then
+     -- sel := ipbus_sel_t(to_unsigned(N_SLV_PRAM, IPBUS_SEL_WIDTH)); -- pram / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "-----------------011------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "-----------------100------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- i2c / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "-----------------101------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- i2c / base 0x00005000 / mask 0x00003002
+-- END automatically generated VHDL
+
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_ipbus_example;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_tlu.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_tlu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..114da4012cbed8bf184566ff856f82576a074ff7
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_decode_tlu.vhd
@@ -0,0 +1,73 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- 
+-- Paolo Baesso, February 2017
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_tlu is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of IPBus slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_tlu;
+
+package body ipbus_decode_tlu is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "----------------0000----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "----------------0000----------1-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    elsif std_match(addr, "----------------0001------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    elsif std_match(addr, "----------------0010----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_SHUT, IPBUS_SEL_WIDTH)); -- shutter / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "----------------0011------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "----------------0100------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVBUF, IPBUS_SEL_WIDTH)); -- event buffer / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "----------------0101------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVFMT, IPBUS_SEL_WIDTH)); -- event formatter / base 0x00005000 / mask 0x00003002
+    elsif std_match(addr, "----------------0110------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- trigger inputs / base 0x00006000 / mask 0x00003002
+    elsif std_match(addr, "----------------0111------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGLGC, IPBUS_SEL_WIDTH)); -- trigger logic / base 0x00007000 / mask 0x00003002
+    elsif std_match(addr, "----------------1000------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_LGCCLK, IPBUS_SEL_WIDTH)); -- logic clocks / base 0x00008000 / mask 0x00003002
+-- END automatically generated VHDL
+ 
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_tlu;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_example.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cc5f12c11b018fd6cbf7c022792e71ff24b06da
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_example.vhd
@@ -0,0 +1,174 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_example is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_example;
+
+architecture rtl of ipbus_example is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+       COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+
+	slave4: entity work.ipbus_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_RAM),
+			ipbus_out => ipbr(N_SLV_RAM)
+		);
+	
+-- Slave 3: peephole RAM
+
+	slave5: entity work.ipbus_peephole_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_PRAM),
+			ipbus_out => ipbr(N_SLV_PRAM)
+		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_fabric_sel.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_fabric_sel.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..86d2fa7ad9b120d636c28ad9fe3de5a35eaa0d51
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_fabric_sel.vhd
@@ -0,0 +1,61 @@
+-- The ipbus bus fabric, address select logic, data multiplexers
+--
+-- This version selects the addressed slave depending on the state
+-- of incoming control lines
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+
+entity ipbus_fabric_sel is
+  generic(
+    NSLV: positive;
+    STROBE_GAP: boolean := false;
+    SEL_WIDTH: positive
+   );
+  port(
+  	sel: in std_logic_vector(SEL_WIDTH - 1 downto 0);
+    ipb_in: in ipb_wbus;
+    ipb_out: out ipb_rbus;
+    ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0);
+    ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL)
+   );
+
+end ipbus_fabric_sel;
+
+architecture rtl of ipbus_fabric_sel is
+
+	signal sel_i: integer range 0 to NSLV := 0;
+	signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
+	signal qstrobe: std_logic;
+
+begin
+
+	sel_i <= to_integer(unsigned(sel));
+
+	ored_ack(NSLV) <= '0';
+	ored_err(NSLV) <= '0';
+	
+	qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
+	 ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
+
+	busgen: for i in NSLV-1 downto 0 generate
+	begin
+
+		ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
+		ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
+		ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0';
+		ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
+		ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
+		ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;		
+
+	end generate;
+
+  ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0');
+  ipb_out.ipb_ack <= ored_ack(0);
+  ipb_out.ipb_err <= ored_err(0);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_slaves.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_slaves.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0ee08ffa82d15f637cdba389211c81b5a7c47c7
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_slaves.vhd
@@ -0,0 +1,170 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_slaves is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_slaves;
+
+architecture rtl of ipbus_slaves is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+    COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+--	slave4: entity work.ipbus_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_RAM),
+--			ipbus_out => ipbr(N_SLV_RAM)
+--		);
+	
+-- Slave 3: peephole RAM
+--	slave5: entity work.ipbus_peephole_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_PRAM),
+--			ipbus_out => ipbr(N_SLV_PRAM)
+--		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_ver.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_ver.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..068f126f8c11346b8a47aeed7e018fb70274f6a1
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/ipbus_ver.vhd
@@ -0,0 +1,46 @@
+--=============================================================================
+--! @file  ipbus_ver.vhd
+--=============================================================================
+
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+--! @brief IPBus fixed register returning Firmware version number
+entity ipbus_ver is
+	port(
+		ipbus_in: in ipb_wbus;
+		ipbus_out: out ipb_rbus
+	);
+	
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+  ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+  ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/led_stretcher.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/led_stretcher.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c8af6c6890d6b0e50669a1527c6f09ad18ae46b4
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/led_stretcher.vhd
@@ -0,0 +1,74 @@
+-- stretcher
+--
+-- Stretches a single clock pulse so it's visible on an LED
+--
+-- Dave Newbold, January 2013
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity led_stretcher is
+	generic(
+		WIDTH: positive := 1
+	);
+	port(
+		clk: in std_logic; -- Assumed to be 125MHz ipbus clock
+		d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected)
+		q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse
+	);
+
+end led_stretcher;
+
+architecture rtl of led_stretcher is
+
+	signal d17, d17_d: std_logic;
+	
+begin
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => clk,
+			d17 => d17
+		);
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			d17_d <= d17;
+		end if;
+	end process;
+	
+	lgen: for i in WIDTH - 1 downto 0 generate
+	
+		signal s, sd, e, e_d, sl: std_logic;
+		signal scnt: unsigned(6 downto 0);
+	
+	begin
+	
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				s <= d(i); -- Possible clock domain crossing from slower clock (sync not important)
+				sd <= s;
+				e <= (e or (s and not sd)) and not e_d;
+				if d17 = '1' and d17_d = '0' then
+					e_d <= e;
+					if e = '1' then
+						scnt <= "0000001";
+					elsif sl = '0' then
+						scnt <= scnt + 1;
+					end if;					
+				end if;
+			end if;
+		end process;
+
+		sl <= '1' when scnt = "0000000" else '0';
+		
+		q(i) <= not sl;
+		
+	end generate;
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/logic_clocks_rtl.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/logic_clocks_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..631007a5684f7176cbd027035ecfa6235abfcc21
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/logic_clocks_rtl.vhd
@@ -0,0 +1,344 @@
+--=============================================================================
+--! @file logic_clocks_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
+-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
+-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________40.000____________0.010
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock.
+--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock.
+--! Can also output clock to external clock pins.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 14:20:26 11/14/12
+--
+--! @version v0.1
+--
+--! @details
+--! \br <b> IPBus Address map:</b>
+--! \br (decode 2 bits)
+--! \li 0x00000000 - control/status register:
+--! \li             bit-0 - PLL locked ( 1 = locked )
+--! \li              bit-1 - buff-PLL locked ( 1 = locked )
+--! \li             bit-2 - use xtal for logic ( 1 = xtal , 0= external)
+--! \li             bit-3 - clock connector is an input ( 1=input , 0 = output)
+--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
+--!
+--!
+ENTITY logic_clocks IS
+    GENERIC( 
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT( 
+        ipbus_clk_i           : IN     std_logic;
+        ipbus_i               : IN     ipb_wbus;
+        ipbus_reset_i         : IN     std_logic;
+        Reset_i               : IN     std_logic;
+        clk_logic_xtal_i      : IN     std_logic;   --! 40MHz clock derived from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic;   --! 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic;   --! 160MHz clock
+        ipbus_o               : OUT    ipb_rbus;
+        strobe_8x_logic_o    : OUT    std_logic;   --! strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic;   --! one pulse every 4 cycles of clk_4x
+        DUT_clk_o             : OUT    std_logic;   --! 40MHz to DUTs
+        logic_clocks_locked_o : OUT    std_logic;   --! Goes high if clocks locked.
+        logic_reset_o         : OUT    std_logic    --! Goes high to reset counters etc. Sync with clk_4x_logic
+    );
+
+-- Declarations
+END ENTITY logic_clocks ;
+
+--
+ARCHITECTURE rtl OF logic_clocks IS
+    signal s_clk40 , s_clk40_internal : std_logic;
+    signal s_clk160 ,s_clk160_internal : std_logic;
+    signal ryanclock : std_logic;
+    signal s_clk320 , s_clk320_internal : std_logic;
+    signal s_clk40_out : std_logic;       -- Clock generated by DDR register to feed out of chip.
+    signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
+                                                             -- input from ext
+    --  signal s_logic_clk_rst : std_logic := '0';
+    signal s_locked_pll, s_locked_bufpll : std_logic;
+    
+    signal s_clk : std_logic;
+    signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
+    signal s_extclk, s_extclkG : std_logic;
+    -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic  : std_logic;
+    signal s_clkfbout_buf , s_clkfbout : std_logic;
+    
+    signal s_strobe_generator  : std_logic_vector(3 downto 0) := "1000";  -- ! Store state of ring buffer to generate strobe
+    signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100";  --! Stores state of 40MHz "clock"
+    --signal s_strobe_generator  : std_logic_vector(15 downto 0) := "1111000000000000";  -- ! Store state of ring buffer to generate strobe
+    --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000";  --! Stores state of 40MHz "clock"
+    signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring
+    signal s_strobe_fb : std_logic := '0';
+    
+    signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';  
+                                        -- ! Reset signal in IPBus clock domain
+    signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';  
+                                        -- ! reset signal clocked onto logic-clock domain.
+    attribute SHREG_EXTRACT: string;
+    attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre
+    attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg
+    signal s_ipbus_ack : std_logic := '0';
+    signal s_reset_pll : std_logic := '0';
+    
+    
+    -- ! Global Reset signal
+    signal  s_extclk_internal  : std_logic := '0';
+    signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range );   --! Hold status of clocks
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus write
+    -----------------------------------------------------------------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_logic_reset_ipb <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+            when "00" =>
+             s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
+             
+            when "01" =>
+             s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
+            when others => null;
+            end case;
+       end if;
+
+        -- register reset signal to aid timing.
+        s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+        -- register the clock status signals onto IPBus domain.
+        --s_clock_status_ipb <=  x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+        s_clock_status_ipb <=  x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status. 
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+    -----------------------------------------------------------------------------
+    -- IPBUS read
+    -----------------------------------------------------------------------------
+    with ipbus_i.ipb_addr(1 downto 0) select
+    ipbus_o.ipb_rdata <=
+        s_clock_status_ipb  when "00",
+        (others => '1')      when others;
+
+
+    -----------------------------------------------------------------------------
+    -- Generate reset signal on logic-clock domain
+    -- This relies on the IPBus clock being much slower than the 4x logic clock.
+    -----------------------------------------------------------------------------
+    p_reset: process (s_clk160_internal)
+    begin  -- process p_reset
+    if rising_edge(s_clk160_internal) then
+        s_logic_reset_d1 <= s_logic_reset_ipb_d1;
+        s_logic_reset_d2 <= s_logic_reset_d1;
+        s_logic_reset_d3 <= s_logic_reset_d2;
+        s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3); 
+        s_logic_reset <= s_logic_reset_d4;
+    end if;
+    end process p_reset;
+    
+    logic_reset_o <= s_logic_reset;
+    logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+
+    -- Use Generate, since can't figure out how BUFGMUX works    
+    --  gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
+    --    s_DUT_Clk <= s_extclkG; -- Hard wire for now.    
+    --  end generate gen_extclk_input;
+    --  gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
+    s_DUT_Clk <= clk_logic_xtal_i; 
+    --  end generate gen_intclk_input;  
+  
+
+  
+    --! Clocking primitive
+    -------------------------------------
+    --! Instantiation of the PLL primitive
+    pll_base_inst : PLL_BASE
+    generic map
+       (BANDWIDTH            => "OPTIMIZED",
+        --CLK_FEEDBACK         => "CLKOUT0", --"CLKFBOUT",
+        CLK_FEEDBACK         => "CLKFBOUT",
+        COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+        DIVCLK_DIVIDE        => 1,
+        CLKFBOUT_MULT        => 16,
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE       => 2, -- 1-->2 move from 640 to 320
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => 4, -- 4-->8 move from 160 to 80
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKOUT2_DIVIDE       => 16, -- 16--> 32 move from 40 to 20
+        CLKOUT2_PHASE        => 0.000,
+        CLKOUT2_DUTY_CYCLE   => 0.500,
+        CLKIN_PERIOD         => 25.000,
+        REF_JITTER           => 0.010)
+    port map(
+        -- Output clocks
+        CLKFBOUT            => s_clkfbout,
+        CLKOUT0             => s_clk320,
+        CLKOUT1             => s_clk160,
+        CLKOUT2             => s_clk40,
+        CLKOUT3             => open,
+        CLKOUT4             => open,
+        CLKOUT5             => open,
+        -- Status and control signals
+        LOCKED              => s_locked_pll,
+        --    RST                 => s_logic_clk_rst,
+        RST                 => s_reset_pll,
+        -- Input clock control
+        --    CLKFBIN             => s_clkfbout_buf,
+        CLKFBIN             => s_clkfbout,
+        CLKIN               => s_DUT_clk);
+        --      CLKIN               => clk_logic_xtal_i);
+
+    s_reset_pll <= Reset_i or s_logic_reset; 
+
+-----------------------------------------------
+--BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR 
+  -- Buffer the 16x clock and generate the ISERDES strobe signal
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK  => s_clk640_internal,          -- 1-bit output: Output I/O clock
+--      LOCK   => s_locked_bufpll,            -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => strobe_16x_logic_O,   -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK   => s_clk160_internal,          -- 1-bit input: BUFG clock input
+--      LOCKED => s_locked_pll,               -- 1-bit input: LOCKED input from PLL
+--      PLLIN  => s_clk640                    -- 1-bit input: Clock input from PLL
+--   );
+
+    BUFG_inst: BUFG
+    port map (
+        I => s_clk320,
+        O => s_clk320_internal    
+    );
+    
+--    BUFR_inst: BUFR
+--    generic map (
+--        BUFR_DIVIDE => "4"
+--    )
+--    port map (
+--        I   => s_clk160_internal,
+--        CE  => '1',
+--        CLR => '0',
+--        O   => ryanclock
+--    );
+    
+--    BUFG_inst2: BUFG
+--    port map (
+--        I => ryanclock,
+--        O => strobe_16x_logic_O    -- Not sure this is actually a strobe... Check
+--    );
+-----------------------------------------------
+
+	clk_8x_logic_o <= s_clk320_internal;
+	DUT_clk_o <= s_DUT_clk;
+
+
+  
+  -- Generate a strobe signal every 4 clocks. 
+  -- Can't use a clock signal as a combinatorial signal. Hence the baroque
+  -- method of generating a strobe. Add a mechanism to restart if the '1' gets
+  -- lost ....
+    
+    ------------------
+    generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out)
+    begin  -- process generate_4x_strobe
+    if rising_edge(s_clk160_internal) then
+        if s_logic_reset = '1' then
+            s_strobe_generator <= "1000";
+            s_logic_clk_generator <= "1100";
+            --s_strobe160 <= "1000000000000000";
+        elsif (s_locked_pll ='1') then
+            s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left      
+            s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left 
+            --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+        end if;
+    end if;
+    end process generate_4x_strobe;
+    strobe_4x_logic_o <=  s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse
+    s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems.
+    ---------------
+    
+    generate_8x_strobe: process (s_clk320_internal)
+    begin
+    if rising_edge(s_clk320_internal) then
+        if s_logic_reset = '1' then
+            s_strobe160 <= "1000000000000000"; 
+            --s_strobe_generator <= "1111000000000000";--
+            --s_logic_clk_generator <= "1111111100000000";--
+        elsif (s_locked_pll ='1') then
+            s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+            --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); --       
+            --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left
+        end if;
+    end if;
+    end process generate_8x_strobe;
+    strobe_8x_logic_O <= s_strobe160(15);
+    --strobe_4x_logic_o <=  s_strobe_generator(15); -- 
+    --s_clk40_out <= s_logic_clk_generator(15); -- 
+        
+
+  -- buffer 160MHz (4x) clock
+  --------------------------------------
+    clk160_o_buf : BUFG
+    port map(
+        O   => s_clk160_internal,
+        I   => s_clk160);
+    
+    clk_4x_logic_o <= s_clk160_internal;
+ 
+--   -- buffer 40MHz (1x) clock
+--  --------------------------------------
+--  clk40_o_buf : BUFG
+--  port map(
+--    O   => s_clk40_internal,
+--    I   => s_clk40);
+
+--  clk_logic_o <= s_clk40_out;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/EUDETdummy/hdl/top_EUDET_dummy.vhd b/AIDA_tlu/legacy/EUDETdummy/hdl/top_EUDET_dummy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3d57cdca0a1217e7106452957e81d2680c539e03
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/hdl/top_EUDET_dummy.vhd
@@ -0,0 +1,783 @@
+-- Top-level design for TLU v1E
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fmcTLU.all;
+use work.ipbus_decode_tlu.all;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use UNISIM.vcomponents.all;
+
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top_EUDET_dummy is
+    generic(
+    constant FW_VERSION : unsigned(31 downto 0):= X"ffff0001"; -- Firmware revision. Remember to change this as needed.
+    g_NUM_DUTS  : positive := 4; -- <- was 3
+    g_NUM_TRIG_INPUTS   :positive := 6;-- <- was 4
+    g_NUM_EDGE_INPUTS   :positive := 6;--  <-- was 4
+    g_NUM_EXT_SLAVES    :positive :=8;--  <-- ??
+    g_EVENT_DATA_WIDTH  :positive := 64;--  <-- ??
+    g_IPBUS_WIDTH   :positive := 32;--  <-- was 32 
+    g_SPILL_COUNTER_WIDTH   :positive := 12;--  <-- ??
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+    --Clock
+        --sysclk: in std_logic; --50 MHz clock input from FPGA
+        clk_enclustra: in std_logic; --Enclustra onboard oscillator 40 MHz. Used for the IPBus block
+        sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_40_i_p: in std_logic;
+        sysclk_40_i_n: in std_logic;
+    --Misc
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
+    --RGMII interface signals
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        phy_rstn: out std_logic; 
+    --I2C bus
+        i2c_scl_b: inout std_logic;
+        i2c_sda_b: inout std_logic;
+        i2c_reset: out std_logic; --Reset line for the expander serial lines
+    --Clock generator controls
+        clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low)
+        --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0>
+    --TLU signals for DUTs
+        busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA)
+        busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA)
+        cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs
+        cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs
+        spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs
+        spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs
+        triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs
+        triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs
+        dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs
+        dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0) --Clock to DUTs
+        
+        --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal
+        --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output
+        --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+                
+     --TLU trigger inputs   
+        --threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        --threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0)
+        --gpio_hdr: out std_logic_vector(3 downto 0);
+        --extclk_n_b: inout std_logic; --External clock in or clock output
+        --extclk_p_b: inout std_logic
+    );
+
+end top_EUDET_dummy;
+
+architecture rtl of top_EUDET_dummy is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	signal s_i2c_scl_enb         : std_logic;
+    signal s_i2c_sda_enb         : std_logic;
+    signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input)
+    
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	------------------------------------------
+	-- Internal signal declarations
+    SIGNAL T0_o                  : std_logic;
+    SIGNAL buffer_full_o         : std_logic;                                             --! Goes high when event buffer almost full
+    SIGNAL clk_8x_logic         : std_logic;                                             -- 320MHz clock
+    SIGNAL clk_4x_logic          : std_logic;                                             --! normally 160MHz
+    SIGNAL clk_logic_xtal        : std_logic;                                             -- ! 40MHz clock from onboard xtal
+    SIGNAL data_strobe           : std_logic;                                             -- goes high when data ready to load into event buffer
+    SIGNAL dout                  : std_logic;
+    SIGNAL dout1                 : std_logic;
+    SIGNAL event_data            : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+    signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
+    signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+    SIGNAL logic_clocks_reset    : std_logic;                                             -- Goes high to reset counters etc. Sync with clk_4x_logic
+    SIGNAL logic_reset           : std_logic;
+    SIGNAL overall_trigger       : std_logic;                                             --! goes high to load trigger data
+    SIGNAL overall_veto          : std_logic;                                             --! Halts triggers when high
+    SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL postVetotrigger       : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        -- ! High when trigger from input connector active and enabled
+    --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+    SIGNAL rst_fifo_o            : std_logic;                                             --! rst signal to first level fifos
+    SIGNAL s_edge_fall_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_falling        : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when falling edge
+    SIGNAL s_edge_rise_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_rising         : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when rising edge
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+    SIGNAL s_shutter             : std_logic;                                             --! shutter signal from TimePix, retimed onto local clock
+    SIGNAL s_triggerLogic_reset  : std_logic;
+    SIGNAL shutter_cnt_i         : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL shutter_i             : std_logic;
+    SIGNAL spill_cnt_i           : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL spill_i               : std_logic;
+    SIGNAL strobe_8x_logic      : std_logic;                                             --! Pulses one cycle every 4 of 16x clock.
+    SIGNAL strobe_4x_logic       : std_logic;                                             -- one pulse every 4 cycles of clk_4x
+    SIGNAL trigger_count         : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+    SIGNAL trigger_times         : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL triggers              : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+    SIGNAL veto_o                : std_logic;                                             --! goes high when one or more DUT are busy
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+	--My signals
+	--SIGNAL busy_toggle_o         : std_logic_vector(g_NUM_DUTS-1 downto 0);
+	
+----------------------------------------------
+----------------------------------------------
+    component DUTInterfaces
+    generic(
+	   g_NUM_DUTS : positive := 4;-- <- was 3
+	   g_IPBUS_WIDTH : positive := 32
+	   );
+    port (
+        clk_4x_logic_i          : IN     std_logic ;
+        strobe_4x_logic_i       : IN     std_logic ;                                  --! goes high every 4th clock cycle
+        trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
+        trigger_i               : IN     std_logic ;                                  --! goes high when trigger logic issues a trigger
+        reset_or_clk_to_dut_i   : IN     std_logic ;                                  --! Synchronization signal. Passed TO DUT pins
+        shutter_to_dut_i        : IN     std_logic ;                                  --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+        -- IPBus signals.
+        ipbus_clk_i             : IN     std_logic ;
+        ipbus_i                 : IN     ipb_wbus ;                                   --! Signals from IPBus core TO slave
+        ipbus_reset_i           : IN     std_logic ;
+        ipbus_o                 : OUT    ipb_rbus ;                                   --! signals from slave TO IPBus core
+        -- Signals to/from DUT
+        busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+        busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+        clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+        trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+        shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+        veto_o                  : OUT    std_logic   
+    );
+    end component DUTInterfaces;
+----------------------------------------------
+----------------------------------------------
+    component Dummy_DUT 
+    Port ( 
+        CLK : in  STD_LOGIC;         --! this is the USB clock.
+        RST : in STD_LOGIC;          --! Synchronous clock
+        Trigger : in STD_LOGIC;      --! Trigger from TLU
+        Busy : out STD_LOGIC;        --! Busy to TLU
+        DUTClk : out STD_LOGIC;      --! clock from DUT
+        TriggerNumber : out STD_LOGIC_VECTOR(15 downto 0);
+        TriggerNumberStrobe : out STD_LOGIC;
+        FSM_Error : out STD_LOGIC
+        );
+end component;
+----------------------------------------------
+----------------------------------------------
+
+--    COMPONENT T0_Shutter_Iface
+--    PORT (
+--        clk_4x_i      : IN     std_logic;
+--        clk_4x_strobe : IN     std_logic;
+--        ipbus_clk_i   : IN     std_logic;
+--        ipbus_i       : IN     ipb_wbus;
+--        T0_o          : OUT    std_logic;
+--        ipbus_o       : OUT    ipb_rbus;
+--        shutter_o     : OUT    std_logic
+--    );
+--    END COMPONENT T0_Shutter_Iface;
+----------------------------------------------
+----------------------------------------------
+
+--   COMPONENT eventBuffer
+--   GENERIC (
+--        g_EVENT_DATA_WIDTH   : positive := 64;
+--        g_IPBUS_WIDTH        : positive := 32;
+--        g_READ_COUNTER_WIDTH : positive := 16
+--   );
+--   PORT (
+--        clk_4x_logic_i    : IN     std_logic ;
+--        data_strobe_i     : IN     std_logic ;                                     -- Indicates data TO transfer
+--        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+--        ipbus_clk_i       : IN     std_logic ;
+--        ipbus_i           : IN     ipb_wbus ;
+--        ipbus_reset_i     : IN     std_logic ;
+--        strobe_4x_logic_i : IN     std_logic ;
+--        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+--        rst_fifo_o        : OUT    std_logic ;                                     --! rst signal TO first level fifos
+--        buffer_full_o     : OUT    std_logic ;                                     --! Goes high when event buffer almost full
+--        ipbus_o           : OUT    ipb_rbus ;
+--        logic_reset_i     : IN     std_logic                                       -- reset buffers when high. Synch withclk_4x_logic
+--   );
+--   END COMPONENT eventBuffer;
+----------------------------------------------
+----------------------------------------------
+--    COMPONENT eventFormatter
+--    GENERIC (
+--        g_EVENT_DATA_WIDTH   : positive := 64;
+--        g_IPBUS_WIDTH        : positive := 32;
+--        g_COUNTER_TRIG_WIDTH : positive := 32;
+--        g_COUNTER_WIDTH      : positive := 12;
+--        g_EVTTYPE_WIDTH      : positive := 4;      --! Width of the event type word
+--        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+--        g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+--        g_NUM_TRIG_INPUTS    : positive := 6       --! Number of trigger inputs (POSSIBLY WRONG!)
+--    );
+--    PORT (
+--        clk_4x_logic_i         : IN     std_logic ;                                         --! Rising edge active
+--        ipbus_clk_i            : IN     std_logic ;
+--        logic_strobe_i         : IN     std_logic ;                                         --! Pulses high once every 4 cycles of clk_4x_logic
+--        logic_reset_i          : IN     std_logic ;                                         --! goes high TO reset counters. Synchronous with clk_4x_logic
+--        rst_fifo_i             : IN     std_logic ;                                         --! Goes high TO reset FIFOs
+--        buffer_full_i          : IN     std_logic ;                                         --! Goes high when output fifo full
+--        trigger_i              : IN     std_logic ;                                         --! goes high TO load trigger data. One cycle of clk_4x_logic
+--        trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);  --! Array of trigger times ( w.r.t. logic_strobe)
+--        trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);    --! high for each input that "fired"
+--        trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
+--        shutter_i              : IN     std_logic ;
+--        shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+--        spill_i                : IN     std_logic ;
+--        spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+--        edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when rising edge
+--        edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when falling edge
+--        edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+--        edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+--        ipbus_i                : IN     ipb_wbus ;
+--        ipbus_o                : OUT    ipb_rbus ;
+--        data_strobe_o          : OUT    std_logic ;                                         --! goes high when data ready TO load into event buffer
+--        event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+--        reset_timestamp_i      : IN     std_logic ;                                         --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+--        reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+--    );
+--    END COMPONENT eventFormatter;   
+----------------------------------------------
+----------------------------------------------
+    COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+----------------------------------------------
+----------------------------------------------
+--    COMPONENT triggerInputs_newTLU
+--    GENERIC (
+--        g_NUM_INPUTS  : natural  := 1;
+--        g_IPBUS_WIDTH : positive := 32
+--    );
+--    PORT (
+--        --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Inputs from constant-fraction discriminators
+--        --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Input from CFD
+--        clk_4x_logic         : IN     std_logic ;                                        --! Rising edge active. By default = 4*40MHz = 160MHz
+--        clk_200_i : IN     std_logic ;
+--        strobe_4x_logic_i    : IN     std_logic ;                                        --! Pulses high once every 4 cycles of clk_4x_logic
+--        threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+--        threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+--        reset_i              : IN     std_logic ;
+--        trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+--        trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+--        --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+--        edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+--        edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+--        edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when rising edge. Syncronous with clk_4x_logic_i
+--        edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when falling edge
+--        ipbus_clk_i          : IN     std_logic ;
+--        ipbus_reset_i        : IN     std_logic ;
+--        ipbus_i              : IN     ipb_wbus ;                                         --! Signals from IPBus core TO slave
+--        ipbus_o              : OUT    ipb_rbus ;                                         --! signals from slave TO IPBus core
+--        clk_8x_logic_i      : IN     std_logic ;                                        --! 640MHz clock ( 16x 40MHz )
+--        strobe_8x_logic_i   : IN     std_logic                                          --! Pulses one cycle every 4 of 8x clock.
+--    );
+--    END COMPONENT triggerInputs_newTLU;
+----------------------------------------------
+----------------------------------------------
+--    COMPONENT triggerLogic
+--    GENERIC (
+--        g_NUM_INPUTS  : positive := 4;
+--        g_IPBUS_WIDTH : positive := 32
+--    );
+--    PORT (
+--        clk_4x_logic_i      : IN     std_logic ;                                   -- ! Rising edge active
+--        ipbus_clk_i         : IN     std_logic ;
+--        ipbus_i             : IN     ipb_wbus ;                                    -- Signals from IPBus core TO slave
+--        ipbus_reset_i       : IN     std_logic ;
+--        logic_reset_i       : IN     std_logic ;                                   -- active high. Synchronous with clk_4x_logic
+--        logic_strobe_i      : IN     std_logic ;                                   -- ! Pulses high once every 4 cycles of clk_4x_logic
+--        trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active
+--        trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+--        veto_i              : IN     std_logic ;                                   -- ! Halts triggers when high
+--        trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active and enabled
+--        trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+--        event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  -- starts at one. Increments for each post_veto_trigger
+--        ipbus_o             : OUT    ipb_rbus ;                                    -- signals from slave TO IPBus core
+--        post_veto_trigger_o : OUT    std_logic ;                                   -- ! goes high when trigger passes
+--        pre_veto_trigger_o  : OUT    std_logic ;
+--        trigger_active_o    : OUT    std_logic                                     --! Goes high when triggers are active ( ie. not veoted)
+--    );
+--    END COMPONENT triggerLogic;
+    
+    COMPONENT i2c_master
+        PORT (
+           i2c_scl_i     : IN     std_logic;
+           i2c_sda_i     : IN     std_logic;
+           ipbus_clk_i   : IN     std_logic;
+           ipbus_i       : IN     ipb_wbus;
+           ipbus_reset_i : IN     std_logic;
+           i2c_scl_enb_o : OUT    std_logic;
+           i2c_sda_enb_o : OUT    std_logic;
+           ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    
+--    component clk_wiz_0
+--    port
+--     (-- Clock in ports
+--      clk_in1           : in     std_logic;
+--      -- Clock out ports
+--      clk_out1          : out    std_logic;
+--      -- Status and control signals
+--      reset             : in     std_logic;
+--      locked            : out    std_logic
+--     );
+--    end component;
+    
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+    --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+    FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
+    FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+    FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    FOR ALL : triggerInputs_newTLU USE ENTITY work.triggerInputs_newTLU;
+    FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+    -- pragma synthesis_on 
+      	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+    
+    
+    -- Infrastructure
+    -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+    logic_clocks_reset <= '0';
+    -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+    spill_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+    spill_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+    shutter_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+    shutter_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
+    dout1 <= '0';
+    -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
+    dout <= '0';
+    -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
+    --gpio_hdr <= dout1 & dout & s_shutter & T0_o;
+    -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+    overall_veto <= buffer_full_o OR veto_o;
+    -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
+    s_triggerLogic_reset <= logic_reset OR T0_o;
+
+    i2c_reset <= '1';
+    clk_gen_rst <= '1';
+    gpio <= strobe_8x_logic;
+    sysclk_50_o_p <= '0';
+    sysclk_50_o_n <= '0';
+    --busy_o <= std_logic_vector(to_unsigned(0,    busy_o'length));
+    --busy_o <= '000000';
+    --sysclk_40_o_p <= sysclk;
+
+------------------------------------------
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => clk_encl_buf,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			clk_200_o => clk_200,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	--leds <= not ('0' & userled & inf_leds); -- Check this.
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151d"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81d"; -- 192.168.200.29
+
+------------------------------------------
+    I1 : entity work.ipbus_ctrlreg_v
+    port map(
+        clk => clk_ipb,
+        reset => rst_ipb,
+        ipbus_in => ipbww(N_SLV_CTRL_REG),
+        ipbus_out => ipbrr(N_SLV_CTRL_REG),
+        d => stat,
+        q => ctrl
+    );
+    stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
+    soft_rst <= ctrl(0)(0);
+    nuke <= ctrl(0)(1);
+    
+------------------------------------------
+	I2 : entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_out,
+      ipb_out => ipb_in,
+      sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
+      ipb_to_slaves => ipbww,
+      ipb_from_slaves => ipbrr
+    );
+
+------------------------------------------
+    I3 : i2c_master
+    PORT MAP (
+        i2c_scl_i     => i2c_scl_b,
+        i2c_sda_i     => i2c_sda_b,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_I2C_0),
+        ipbus_reset_i => rst_ipb,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        ipbus_o       => ipbrr(N_SLV_I2C_0)
+    );
+    
+----------------------------------------------
+    I4 : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => clk_ipb,
+        ipbus_i               => ipbww(N_SLV_LGCCLK),
+        ipbus_reset_i         => rst_ipb,
+        Reset_i               => logic_clocks_reset,
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => ipbrr(N_SLV_LGCCLK),
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => leds(3),
+        logic_reset_o         => logic_reset
+    );    
+
+----------------------------------------------
+--    I5 : triggerInputs_newTLU 
+--    GENERIC MAP (
+--        g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+--        g_IPBUS_WIDTH => 32
+--    )
+--    PORT MAP (
+--        clk_4x_logic         => clk_4x_logic,
+--        clk_200_i => clk_200,
+--        strobe_4x_logic_i    => strobe_4x_logic,
+--        threshold_discr_p_i  => threshold_discr_p_i,
+--        threshold_discr_n_i  => threshold_discr_n_i,
+--        reset_i              => logic_reset,
+--        trigger_times_o      => trigger_times,
+--        trigger_o            => triggers,
+--        --trigger_debug_o      => OPEN,
+--        edge_rising_times_o  => s_edge_rise_times,
+--        edge_falling_times_o => s_edge_fall_times,
+--        edge_rising_o        => s_edge_rising,
+--        edge_falling_o       => s_edge_falling,
+--        ipbus_clk_i          => clk_ipb,
+--        ipbus_reset_i        => rst_ipb,
+--        ipbus_i              => ipbww(N_SLV_TRGIN),
+--        ipbus_o              => ipbrr(N_SLV_TRGIN),
+--        clk_8x_logic_i      => clk_8x_logic,
+--        strobe_8x_logic_i   => strobe_8x_logic
+--    );
+
+------------------------------------------      
+--    I6 : eventFormatter
+--    GENERIC MAP (
+--        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+--        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+--        g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+--        g_COUNTER_WIDTH      => 12,
+--        g_EVTTYPE_WIDTH      => 4,                         --! Width of the event type word
+--        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+--        g_NUM_EDGE_INPUTS    => g_NUM_EDGE_INPUTS,         --! Number of edge inputs
+--        g_NUM_TRIG_INPUTS    => g_NUM_TRIG_INPUTS          --! Number of trigger inputs
+--    )
+--    PORT MAP (
+--        clk_4x_logic_i         => clk_4x_logic,
+--        ipbus_clk_i            => clk_ipb,
+--        logic_strobe_i         => strobe_4x_logic,
+--        logic_reset_i          => logic_reset,
+--        rst_fifo_i             => rst_fifo_o,
+--        buffer_full_i          => buffer_full_o,
+--        trigger_i              => overall_trigger,
+--        trigger_times_i        => postVetoTrigger_times,
+--        trigger_inputs_fired_i => postVetotrigger,
+--        trigger_cnt_i          => trigger_count,
+--        shutter_i              => shutter_i,
+--        shutter_cnt_i          => shutter_cnt_i,
+--        spill_i                => spill_i,
+--        spill_cnt_i            => spill_cnt_i,
+--        edge_rise_i            => s_edge_rising,
+--        edge_fall_i            => s_edge_falling,
+--        edge_rise_time_i       => s_edge_rise_times,
+--        edge_fall_time_i       => s_edge_fall_times,
+--        ipbus_i                => ipbww(N_SLV_EVFMT),
+--        ipbus_o                => ipbrr(N_SLV_EVFMT),
+--        data_strobe_o          => data_strobe,
+--        event_data_o           => event_data,
+--        reset_timestamp_i      => T0_o,
+--        reset_timestamp_o      => OPEN
+--    );
+
+------------------------------------------
+--    I7 : eventBuffer
+--    GENERIC MAP (
+--        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+--        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+--        g_READ_COUNTER_WIDTH => 14
+        
+--    )
+--    PORT MAP (
+--        clk_4x_logic_i    => clk_4x_logic,
+--        data_strobe_i     => data_strobe,
+--        event_data_i      => event_data,
+--        ipbus_clk_i       => clk_ipb,
+--        ipbus_i           => ipbww(N_SLV_EVBUF),
+--        ipbus_reset_i     => rst_ipb,
+--        strobe_4x_logic_i => strobe_4x_logic,
+--        rst_fifo_o        => rst_fifo_o,
+--        buffer_full_o     => buffer_full_o,
+--        ipbus_o           => ipbrr(N_SLV_EVBUF),
+--        logic_reset_i     => logic_reset
+--    );
+    
+--------------------------------------------
+--    I8 : T0_Shutter_Iface
+--    PORT MAP (
+--        clk_4x_i      => clk_4x_logic,
+--        clk_4x_strobe => strobe_4x_logic,
+--        T0_o          => T0_o,
+--        shutter_o     => s_shutter,
+--        ipbus_clk_i   => clk_ipb,
+--        ipbus_i       => ipbww(N_SLV_SHUT),
+--        ipbus_o       => ipbrr(N_SLV_SHUT)
+--    );
+
+------------------------------------------
+--    I9 : DUTInterfaces
+--    GENERIC MAP (
+--        g_NUM_DUTS    => g_NUM_DUTS,
+--        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+--    )
+--    PORT MAP (
+--         clk_4x_logic_i          => clk_4x_logic,
+--         strobe_4x_logic_i       => strobe_4x_logic,
+--         trigger_counter_i       => trigger_count,
+--         trigger_i               => overall_trigger,
+--         reset_or_clk_to_dut_i   => T0_o,
+--         shutter_to_dut_i        => s_shutter,
+--         ipbus_clk_i             => clk_ipb,
+--         ipbus_i                 => ipbww(N_SLV_DUT),
+--         ipbus_reset_i           => rst_ipb,
+--         ipbus_o                 => ipbrr(N_SLV_DUT),
+--         busy_from_dut       => busy_i,
+--         busy_to_dut        => open,
+--         clk_from_dut => dut_clk_i,
+--         clk_to_dut => dut_clk_o,
+--         --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+--         --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+--         reset_to_dut => spare_o,
+--         trigger_to_dut => triggers_o,
+--         --shutter_to_dut_n_o      => shutter_to_dut_n_o,
+--         --shutter_to_dut_p_o      => shutter_to_dut_p_o,
+--         shutter_to_dut  => cont_o,
+--         veto_o                  => veto_o
+--    );
+    
+------------------------------------------ 
+--        I10 : triggerLogic
+--        GENERIC MAP (
+--            g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+--            g_IPBUS_WIDTH => g_IPBUS_WIDTH
+--        )
+--        PORT MAP (
+--            clk_4x_logic_i      => clk_4x_logic,
+--            ipbus_clk_i         => clk_ipb,
+--            ipbus_i             => ipbww(N_SLV_TRGLGC),
+--            ipbus_reset_i       => rst_ipb,
+--            logic_reset_i       => s_triggerLogic_reset,
+--            logic_strobe_i      => strobe_4x_logic,
+--            trigger_i           => triggers,
+--            trigger_times_i     => trigger_times,
+--            veto_i              => overall_veto,
+--            trigger_o           => postVetotrigger,
+--            trigger_times_o     => postVetoTrigger_times,
+--            event_number_o      => trigger_count,
+--            ipbus_o             => ipbrr(N_SLV_TRGLGC),
+--            post_veto_trigger_o => overall_trigger,
+--            pre_veto_trigger_o  => OPEN,
+--            trigger_active_o    => leds(2)
+--        );     
+         
+-------------TEST AREA------------    
+--    test0: entity work.test_inToOut
+--    port map(
+--        clk_in => clk_200,
+--        busy_in=> busy_i,
+--        control_in=> cont_i,
+--        trig_in=> triggers_i,
+--        clkDut_in=> dut_clk_i,
+--        spare_in=> spare_i,
+--        busy_out=> busy_o,
+--        control_out=> cont_o,
+--        trig_out=> triggers_o,
+--        clkDut_out=> dut_clk_o,
+--        spare_out=> spare_o
+--    );
+
+--    dutout0: entity work.DUTs_outputs
+--    port map(
+--        clk_in => encl_clock50, 
+--        d_clk_o => dut_clk_o,
+--        d_trg_o => triggers_o,
+--        d_busy_o => busy_o,
+--        d_cont_o => cont_o,
+--        d_spare_o => spare_o
+--    );
+   
+--    clk50_o_fromEnclustra : clk_wiz_0
+--       port map ( 
+--       -- Clock in ports
+--       clk_in1 => clk_encl_buf, --sysclk_40,
+--      -- Clock out ports  
+--       clk_out1 => encl_clock50,
+--      -- Status and control signals                
+--       reset => '0',
+--       locked =>  open          
+--     );
+
+    
+----------------------------------------------
+    OutBlocks:
+    for iDUT in 0 to g_NUM_DUTS-1 generate
+    begin
+
+
+--     generate an instance of the Dummy DUT behind connector 0
+    DUT_Instance: Dummy_DUT 
+      Port map ( 
+           --CLK => clk_4x_logic,--160 Mhz clock
+           CLK => sysclk_40,
+           RST => cont_i(iDUT),-- coming from HDMI pin
+           Trigger => triggers_i(iDUT), --coming from HDMI pin
+           Busy => busy_o(iDUT), --going out on HDMI pin
+           DUTClk => dut_clk_o(iDUT), --going out on HDMI pin
+           --TriggerNumber => TriggerNumber(DUT),
+           --TriggerNumberStrobe => TriggerNumberStrobe(DUT),
+           FSM_Error => open
+           );
+
+
+
+    end generate;
+
+
+    
+
+------------------------------------------      
+
+
+------------------------------------------
+    IBUFGDS_inst: IBUFGDS
+    generic map (
+        IBUF_LOW_PWR=> false
+    )
+    port map (
+        O => sysclk_40,
+        I => sysclk_40_i_p,
+        IB => sysclk_40_i_n
+    );
+    
+------------------------------------------
+    IBUFG_inst: IBUFG
+    port map (
+        O => clk_encl_buf,
+        I => clk_enclustra--sysclk
+    );    
+
+------------------------------------------
+-- Do not use this: we need differential 3.3 V, not available.
+--    OBUFDS_inst : OBUFDS
+--    generic map (
+--        SLEW => "FAST") -- Specify the output slew rate
+--    port map (
+--        O => sysclk_50_o_p, -- Diff_p output (connect directly to top-level port)
+--        OB => sysclk_50_o_n, -- Diff_n output (connect directly to top-level port)
+--        I => encl_clock50 -- Buffer input
+--    );
+    -- This might not work: these are just two single ended. If we remove R coupling maybe?
+    --sysclk_50_o_p <= encl_clock50;
+    --sysclk_50_o_n <= not encl_clock50;
+
+      
+
+
+end rtl;
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummy.py b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummy.py
new file mode 100644
index 0000000000000000000000000000000000000000..60f03abf092d55584df15f9693fa7856bd198c67
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummy.py
@@ -0,0 +1,587 @@
+# -*- coding: utf-8 -*-
+import uhal;
+import pprint;
+from FmcTluI2c import *
+from I2CuHal import I2CCore
+from si5345 import si5345 # Library for clock chip
+from AD5665R import AD5665R # Library for DAC
+from PCA9539PW import PCA9539PW # Library for serial line expander
+
+class EUDETdummy:
+    """docstring for TLU"""
+    def __init__(self, dev_name, man_file):
+        self.dev_name = dev_name
+        self.manager= uhal.ConnectionManager(man_file)
+        self.hw = self.manager.getDevice(self.dev_name)
+        self.nDUTs= 4 #Number of DUT connectors
+        self.nChannels= 6 #Number of trigger inputs
+        self.VrefInt= 2.5 #Internal DAC voltage reference
+        self.VrefExt= 1.3 #External DAC voltage reference
+        self.intRefOn= False #Internal reference is OFF by default
+
+        self.fwVersion = self.hw.getNode("version").read()
+        self.hw.dispatch()
+        print "EUDUMMY FIRMWARE VERSION= " , hex(self.fwVersion)
+
+        # Instantiate a I2C core to configure components
+        self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
+        #self.TLU_I2C.state()
+
+        enableCore= True #Only need to run this once, after power-up
+        self.enableCore()
+
+        # Instantiate clock chip
+        self.zeClock=si5345(self.TLU_I2C, 0x68)
+        res= self.zeClock.getDeviceVersion()
+        self.zeClock.checkDesignID()
+
+        # Instantiate DACs and configure them to use reference based on TLU setting
+        self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
+        self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
+        self.zeDAC1.setIntRef(self.intRefOn)
+        self.zeDAC2.setIntRef(self.intRefOn)
+
+        # Instantiate the serial line expanders and configure them to default values
+        self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
+        self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(0, 0xAA)# If output, set to XX
+
+        self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(1, 0xAA)# If output, set to XX
+
+        self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
+        self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(0, 0x0F)# If output, set to XX
+
+        self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(1, 0x50)# If output, set to XX
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def DUTOutputs(self, dutN, enable=False, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "to", enable
+        if verbose:
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getIOReg(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newStatus= oldStatus & (~mask)
+        if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
+            newStatus |= mask
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC6.setIOReg(bank, newStatus)
+        return newStatus
+
+    def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
+        ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
+        ## clkSrc= 0: clock disabled
+        ## clkSrc= 1: clock from Si5345
+        ## clkSrc=2: clock from FPGA
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        if (clkSrc < 0) | (clkSrc> 2):
+            print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
+            return -1
+        bank=0
+        maskLow= 1 << (1* dutN) #CLK FROM FPGA
+        maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
+        mask= maskLow | maskHigh
+        res= self.IC7.getIOReg(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask #set both bits to zero
+        outStat= ""
+        if clkSrc==0:
+            newStatus = newStatus | mask
+            outStat= "disabled"
+        elif clkSrc==1:
+            newStatus = newStatus | maskLow
+            outStat= "Si5435"
+        elif clkSrc==2:
+            newStatus= newStatus | maskHigh
+            outStat= "FPGA"
+        print "  Setting DUT:", dutN, "clock source to", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setIOReg(bank, newStatus)
+        return newStatus
+
+    def enableClkLEMO(self, enable= False, verbose= False):
+        ## Enable or disable the output clock to the differential LEMO output
+        bank=1
+        mask= 0x10
+        res= self.IC7.getIOReg(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask
+        outStat= "enabled"
+        if (not enable): #A 0 activates the output. A 1 disables it.
+            newStatus= newStatus | mask
+            outStat= "disabled"
+        print "  Clk LEMO", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setIOReg(bank, newStatus)
+        return newStatus
+
+    def enableCore(self):
+        ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
+        ## This function enables the lines. It is only required once.
+        mystop=True
+        print "  Enabling I2C bus (expect 127):"
+        myslave= 0x21
+        mycmd= [0x01, 0x7F]
+        nwords= 1
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+
+        mystop=False
+        mycmd= [0x01]
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tPost RegDir: ", res
+
+    def getAllChannelsCounts(self):
+        chCounts=[]
+        for ch in range (0,self.nChannels):
+            chCounts.append(int(self.getChCount(ch)))
+        return chCounts
+
+    def getChStatus(self):
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\tInput status= " , hex(inputStatus)
+        return inputStatus
+
+    def getChCount(self, channel):
+        regString= "triggerInputs.ThrCount"+ str(channel)+"R"
+        count = self.hw.getNode(regString).read()
+        self.hw.dispatch()
+        print "\tCh", channel, "Count:" , count
+        return count
+
+    def getClockStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "  CLOCK STATUS [expected 1]"
+        print "\t", hex(clockStatus)
+        if ( clockStatus == 0 ):
+            "ERROR: Clocks in EUDUMMY FPGA are not locked."
+        return clockStatus
+
+    def getDUTmask(self):
+        DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
+        self.hw.dispatch()
+        print "\tDUTMask read back as:" , hex(DUTMaskR)
+        return DUTMaskR
+
+    def getExternalVeto(self):
+        extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tEXTERNAL Veto read back as:", hex(extVeto)
+        return extVeto
+
+    def getFifoData(self, nWords):
+    	#fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
+    	fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
+    	self.hw.dispatch()
+    	#print "\tFIFO Data:", hex(fifoData)
+    	return fifoData
+
+    def getFifoLevel(self):
+        FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
+        self.hw.dispatch()
+        print "\tFIFO level read back as:", hex(FifoFill)
+        return FifoFill
+
+    def getFifoCSR(self):
+        FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
+        self.hw.dispatch()
+        print "\tFIFO CSR read back as:", hex(FifoCSR)
+        return FifoCSR
+
+    def getInternalTrg(self):
+        trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\tTrigger frequency read back as:", trigIntervalR, "Hz"
+        return trigIntervalR
+
+    def getMode(self):
+        DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
+        self.hw.dispatch()
+        print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
+        return DUTInterfaceModeR
+
+    def getModeModifier(self):
+        DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
+        self.hw.dispatch()
+        print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
+        return DUTInterfaceModeModifierR
+
+    def getSN(self):
+        epromcontent=self.readEEPROM(0xfa, 6)
+        print "  EUDET dummy serial number (EEPROM):"
+        result="\t"
+        for iaddr in epromcontent:
+            result+="%02x "%(iaddr)
+        print result
+        return epromcontent
+
+    def getPostVetoTrg(self):
+        triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
+        self.hw.dispatch()
+        print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
+        return triggerN
+
+    def getPulseDelay(self):
+        pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
+        self.hw.dispatch()
+        print "\tPulse delay read back as:", hex(pulseDelayR)
+        return pulseDelayR
+
+    def getPulseStretch(self):
+        pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
+        self.hw.dispatch()
+        print "\tPulse stretch read back as:", hex(pulseStretchR)
+        return pulseStretchR
+
+    def getRecordDataStatus(self):
+        RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
+        self.hw.dispatch()
+        print "\tData recording:", RecordStatus
+        return RecordStatus
+
+    def getTriggerVetoStatus(self):
+        trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tTrigger veto status read back as:", trgVetoStatus
+        return trgVetoStatus
+
+    def getTrgPattern(self):
+        triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
+        triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
+        self.hw.dispatch()
+        print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
+        return triggerPattern_low, triggerPattern_high
+
+    def getVetoDUT(self):
+        IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
+        self.hw.dispatch()
+        print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
+        return IgnoreDUTBusyR
+
+    def getVetoShutters(self):
+        IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
+        self.hw.dispatch()
+        print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
+        return IgnoreShutterVeto
+
+    def pulseT0(self):
+        cmd = int("0x1",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tPulsing T0"
+
+    def readEEPROM(self, startadd, bytes):
+        mystop= 1
+        time.sleep(0.1)
+        myaddr= [startadd]#0xfa
+        self.TLU_I2C.write( 0x50, [startadd], mystop)
+        res= self.TLU_I2C.read( 0x50, bytes)
+        return res
+
+    def resetClock(self):
+        # Set the RST pin from the PLL to 1
+        print "  Clocks reset"
+        cmd = int("0x1",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def resetClocks(self):
+        #Reset clock PLL
+        self.resetClock()
+        #Get clock status after reset
+        self.getClockStatus()
+        #Restore clock PLL
+        self.restoreClock()
+        #Get clock status after restore
+        self.getClockStatus()
+        #Get serdes status
+        self.getChStatus()
+
+    def resetCounters(self):
+    	cmd = int("0x2", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	cmd = int("0x0", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	#print "Trigger Reset: 0x%X" % restatus
+    	print "\tTrigger counters reset"
+
+    def resetSerdes(self):
+        cmd = int("0x3",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during reset = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after reset = " , hex(inputStatus)
+
+        cmd = int("0x4",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during calibration = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after calibration = " , hex(inputStatus)
+
+    def restoreClock(self):
+        # Set the RST pin from the PLL to 0
+        print "  Clocks restore"
+        cmd = int("0x0",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def setChStatus(self, cmd):
+        self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "  INPUT STATUS SET TO= " , hex(inputStatus)
+
+    def setClockStatus(self, cmd):
+        # Only use this for testing. The clock source is actually selected in the Si5345.
+        self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
+        self.hw.dispatch()
+
+    def setDUTmask(self, DUTMask):
+        print "  DUT MASK ENABLING: Mask= " , hex(DUTMask)
+        self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
+        self.hw.dispatch()
+        self.getDUTmask()
+
+    def setFifoCSR(self, cmd):
+        self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
+        self.hw.dispatch()
+        self.getFifoCSR()
+
+    def setInternalTrg(self, triggerInterval):
+        print "  TRIGGERS INTERNAL:"
+        if triggerInterval == 0:
+            internalTriggerFreq = 0
+            print "\tdisabled"
+        else:
+            internalTriggerFreq = 160000.0/triggerInterval
+            print "\t  Setting:", internalTriggerFreq, "Hz"
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
+        self.hw.dispatch()
+        self.getInternalTrg()
+
+    def setMode(self, mode):
+        print "  DUT MODE SET TO: ", hex(mode)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
+        self.hw.dispatch()
+        self.getMode()
+
+    def setModeModifier(self, modifier):
+        print "  DUT MODE MODIFIER:", hex(modifier)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
+        self.hw.dispatch()
+        self.getModeModifier()
+
+    def setPulseDelay(self, pulseDelay):
+        print "  TRIGGER DELAY SET TO", hex(pulseDelay), "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
+        self.hw.dispatch()
+        self.getPulseDelay()
+
+    def setPulseStretch(self, pulseStretch):
+        print "  INPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
+        self.hw.dispatch()
+        self.getPulseStretch()
+
+    def setRecordDataStatus(self, status=False):
+        print "  Data recording set:"
+        self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
+        self.hw.dispatch()
+        self.getRecordDataStatus()
+
+    def setTriggerVetoStatus(self, status=False):
+        self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
+        self.hw.dispatch()
+        self.getTriggerVetoStatus()
+
+    def setTrgPattern(self, triggerPatternH, triggerPatternL):
+        triggerPatternL &= 0xffffffff
+        triggerPatternH &= 0xffffffff
+        print "  TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
+        self.hw.dispatch()
+        self.getTrgPattern()
+
+    def setVetoDUT(self, ignoreDUTBusy):
+        print "  VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
+        self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
+        self.hw.dispatch()
+        self.getVetoDUT()
+
+    def setVetoShutters(self, newState):
+        if newState:
+            print "  IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
+            cmd= int("0x0",16)
+        else:
+            print "  IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
+            cmd= int("0x1",16)
+        self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
+        self.hw.dispatch()
+        self.getVetoShutters()
+
+    def writeThreshold(self, DACtarget, Vtarget, channel):
+        #Writes the threshold. The DAC voltage differs from the threshold voltage because
+        #the range is shifted to be symmetrical around 0V.
+
+        #Check if the DACs are using the internal reference
+        if (self.intRefOn):
+            Vref= self.VrefInt
+        else:
+            Vref= self.VrefExt
+
+        #Calculate offset voltage (because of the following shifter)
+        Vdac= ( Vtarget + Vref ) / 2
+        print"  THRESHOLD setting:"
+        if channel==7:
+            print "\tCH: ALL"
+        else:
+            print "\tCH:", channel
+        print "\tTarget V:", Vtarget
+        dacValue = 0xFFFF * (Vdac / Vref)
+        DACtarget.writeDAC(int(dacValue), channel, True)
+
+    def parseFifoData(self, fifoData, nEvents, verbose):
+        #for index in range(0, len(fifoData)-1, 6):
+        outList= []
+        for index in range(0, (nEvents)*6, 6):
+            word0= (fifoData[index] << 32) + fifoData[index + 1]
+            word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
+            word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
+            evType= (fifoData[index] & 0xF0000000) >> 28
+            inTrig= (fifoData[index] & 0x0FFF0000) >> 16
+            tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
+            fineTs= fifoData[index + 2]
+            evNum= fifoData[index + 3]
+            fineTsList=[-1]*12
+            fineTsList[3]= (fineTs & 0x000000FF)
+            fineTsList[2]= (fineTs & 0x0000FF00) >> 8
+            fineTsList[1]= (fineTs & 0x00FF0000) >> 16
+            fineTsList[0]= (fineTs & 0xFF000000) >> 24
+            fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
+            fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
+            fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
+            fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
+            fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
+            fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
+            fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
+            fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
+            if verbose:
+                print "====== EVENT", evNum, "================================================="
+                print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
+                print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
+                print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
+                print fineTsList
+            fineTsList.insert(0, tStamp)
+            fineTsList.insert(0, evNum)
+            #print fineTsList
+            outList.insert(len(outList), fineTsList)
+        printdata= False
+        if (printdata):
+            print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
+            print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
+            pprint.pprint(outList)
+        return outList
+
+
+
+
+##################################################################################################################################
+##################################################################################################################################
+
+    def initialize(self):
+        print "\nEUDUMMY INITIALIZING..."
+
+        # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
+
+        #READ CONTENT OF EPROM VIA I2C
+        self.getSN()
+
+
+        #
+        # #SET DACs
+        targetV= -0.12
+        DACchannel= 7
+        self.writeThreshold(self.zeDAC1, targetV, DACchannel, )
+        self.writeThreshold(self.zeDAC2, targetV, DACchannel, )
+
+        #
+        # #ENABLE/DISABLE HDMI OUTPUTS
+        #self.DUTOutputs(0, True, False)
+        #self.DUTOutputs(1, True, False)
+        #self.DUTOutputs(2, True, False)
+        #self.DUTOutputs(3, True, False)
+
+        ## ENABLE/DISABLE LEMO CLOCK OUTPUT
+        #self.enableClkLEMO(True, False)
+
+        #
+        # #Check clock status
+        self.getClockStatus()
+
+        resetClocks = 0
+        resetSerdes = 0
+        resetCounters= 0
+        if resetClocks:
+            self.resetClocks()
+            self.getClockStatus()
+        if resetSerdes:
+            self.resetSerdes()
+        if resetCounters:
+	    self.resetCounters()
+
+
+
+        print "EUDUMMY INITIALIZED"
+
+##################################################################################################################################
+##################################################################################################################################
+    def start(self, logtimestamps=False):
+        print "EUDUMMY STARTING..."
+
+        print "  EUDUMMY RUNNING"
+
+##################################################################################################################################
+##################################################################################################################################
+    def stop(self):
+        print "EUDUMMY STOPPING..."
+
+        print "  EUDUMMY STOPPED"
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyaddrmap.xml b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyaddrmap.xml
new file mode 100644
index 0000000000000000000000000000000000000000..5d9ab7b33f7bf5cb2b11b1e8196281c7af32b776
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyaddrmap.xml
@@ -0,0 +1,96 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="eudummy">
+
+<!-- Registers for the DUTs. These should be correct -->
+<!--
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+-->
+<!--
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+-->
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<!--
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+-->
+<!-- Event formatter registers. Should be ok -->
+<!--
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+-->
+<!-- This needs checking. The counters work, not sure about the reset -->
+<!--
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+-->
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<!--
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" />
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+</node>
+-->
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+</node>
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyconnection.xml b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyconnection.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6084306e1d235d7c3162dfd35a18621b65a1f4bc
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDETdummyconnection.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="eudummy" uri="ipbusudp-2.0://192.168.200.29:50001"
+   address_table="file://./EUDETdummyaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/EUDummy_testscript.py b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDummy_testscript.py
new file mode 100644
index 0000000000000000000000000000000000000000..3e780ea92e5549d4a45460c4b7b8a97cc8e438f0
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/EUDummy_testscript.py
@@ -0,0 +1,155 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./EUDETdummyconnection.xml")
+hw = manager.getDevice("eudummy")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
+#zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL: 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS: 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0xF7)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0xFF)# 0= normal
+IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(0, 0xFF)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/initTLU.py b/AIDA_tlu/legacy/EUDETdummy/scripts/initTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/initTLU.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/startDUMMY.sh b/AIDA_tlu/legacy/EUDETdummy/scripts/startDUMMY.sh
new file mode 100644
index 0000000000000000000000000000000000000000..03f6c55f0eee34eb5b60085651418ce5eeb9accc
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/startDUMMY.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+echo "=========================="
+CURRENT_DIR=${0%/*}
+echo "CURRENT DIRECTORY: " $CURRENT_DIR
+
+echo "============"
+echo "SETTING PATHS"
+export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_preexport PYTHONPATH=../../packages:$PYTHONPATH2A/src:$PYTHONPATH
+echo "PYTHON PATH= " $PYTHONPATH
+export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
+echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
+export PATH=/usr/bin/:/opt/cactus/bin:$PATH
+echo "PATH= " $PATH
+
+cd $CURRENT_DIR
+
+echo "============"
+echo "STARTING PYTHON SCRIPT FOR TLU"
+#python $CURRENT_DIR/startTLU_v8.py $@
+
+python startEUDETdummy.py $@
+#python testTLU_script.py
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/startEUDETdummy.py b/AIDA_tlu/legacy/EUDETdummy/scripts/startEUDETdummy.py
new file mode 100644
index 0000000000000000000000000000000000000000..2efbf71b3e8fb9c71cf8430928ba706547df09cd
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/startEUDETdummy.py
@@ -0,0 +1,72 @@
+# -*- coding: utf-8 -*-
+# miniTLU test script
+
+#from PyChipsUser import *
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from EUDETdummy import EUDETdummy
+# Use to have interactive shell
+import cmd
+
+class MyPrompt(cmd.Cmd):
+
+
+    def do_startRun(self, args):
+	"""Starts the TLU run"""
+	print "COMMAND RECEIVED: STARTING TLU RUN"
+	startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+	#print self.hw
+
+    def do_stopRun(self, args):
+	"""Stops the TLU run"""
+	print "COMMAND RECEIVED: STOP TLU RUN"
+	#stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "COMMAND RECEIVED: QUITTING SCRIPT."
+        #raise SystemExit
+	return True
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    EUDummy= EUDETdummy("eudummy", "file://./EUDETdummyconnection.xml")
+    EUDummy.initialize()
+
+    logdata= True
+    EUDummy.start(logdata)
+    time.sleep(0.2)
+    EUDummy.stop()
+    # prompt = MyPrompt()
+    # prompt.prompt = '>> '
+    # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/AIDA_tlu/legacy/EUDETdummy/scripts/testTLU_script.py b/AIDA_tlu/legacy/EUDETdummy/scripts/testTLU_script.py
new file mode 100644
index 0000000000000000000000000000000000000000..9d8b334bb4a6fd01050c3d622f54847616fce208
--- /dev/null
+++ b/AIDA_tlu/legacy/EUDETdummy/scripts/testTLU_script.py
@@ -0,0 +1,79 @@
+# miniTLU test script
+
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+from I2CuHal import I2CCore
+from miniTLU import MiniTLU
+from datetime import datetime
+
+if __name__ == "__main__":
+    print "\tTEST TLU SCRIPT"
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    #(self, target, wclk, i2cclk, name="i2c", delay=None)
+    TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
+    TLU_I2C.state()
+
+
+    #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
+    mystop= 1
+    time.sleep(0.1)
+    myaddr= [0xfa]
+    TLU_I2C.write( 0x50, myaddr, mystop)
+    res=TLU_I2C.read( 0x50, 6)
+    print "Checkin EEPROM:"
+    result="\t"
+    for iaddr in res:
+        result+="%02x "%(iaddr)
+    print result
+
+    #SCAN I2C ADDRESSES
+    #WRITE PROM
+    #WRITE DAC
+
+
+    #Convert required threshold voltage to DAC code
+    #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+    print("Writing DAC setting:")
+    Vref= 1.300
+    desiredVoltage= 3.3
+    channel= 0
+    i2cSlaveAddrDac = 0x1F
+    vrefOn= 0
+    Vdaq = ( desiredVoltage + Vref ) / 2
+    dacCode = 0xFFFF * Vdaq / Vref
+    dacCode= 0x391d
+    print "\tVreq:", desiredVoltage
+    print "\tDAC code:"  , dacCode
+    print "\tCH:", channel
+    print "\tIntRef:", vrefOn
+
+    #Set DAC value
+    #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+    if channel<0 or channel>7:
+        print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+        ##return -1
+    if dacCode<0 or dacCode>0xFFFF:
+        print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
+        ##return -1
+    # AD5665R chip with A0,A1 tied to ground
+    #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+
+    # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+    # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+    # # if we want to enable internal voltage reference:
+
+    if vrefOn:
+        # enter vref-on mode:
+        print "\tTurning internal reference ON"
+        #dac.write([0x38,0x00,0x01])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
+    else:
+        print "\tTurning internal reference OFF"
+        #dac.write([0x38,0x00,0x00])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
+    # Now set the actual value
+    sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+    print "\tWriting byte sequence:", sequence
+    TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_AIDA_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_AIDA_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..243913c711a1431f18caa56fe08fc638c1478574
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_AIDA_rtl.vhd
@@ -0,0 +1,149 @@
+--=============================================================================
+--! @file DUTInterface_AIDA_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
+--
+--------------------------------------------------------------------------------
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+--! @brief "AIDA Style" Interface to a Device Under Test (DUT) connector.
+--! factorized from original DUTInterfaces_rtl.vhd firmware.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 1/Sept/2015
+--!
+--! @version v0.1
+--!
+--! @details
+--
+
+ENTITY DUTInterface_AIDA IS
+   GENERIC( 
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;      --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;      --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;      --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;      --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto  flag is set high
+      ignore_shutter_veto_i   : in     std_logic;
+      ignore_dut_busy_i       : in     std_logic;
+      dut_mask_i              : in     std_logic;      --! Set high if DUT is active.
+      busy_o                  : OUT    std_logic;      --! goes high when DUT is busy or vetoed by shutter
+      
+      -- Signals to/from DUT
+      dut_busy_i       : IN     std_logic;     --! BUSY input from DUTs
+      dut_clk_o        : OUT    std_logic;     --! clocks trigger data when in EUDET mode
+      dut_reset_or_clk_o : OUT    std_logic;     --! Either reset line or trigger
+      dut_shutter_o      : OUT    std_logic;     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      dut_trigger_o      : OUT    std_logic     --! Trigger output
+
+   );
+
+-- Declarations
+
+END ENTITY DUTInterface_AIDA ;
+
+--
+ARCHITECTURE rtl OF DUTInterface_AIDA IS
+
+  signal s_strobe_4x_logic_d1 : std_logic;
+  signal s_dut_clk : std_logic := '0';  -- Clock to be sent to DUT connectors ( before final register )
+  signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+  signal s_stretch_trig_in : std_logic := '0';  -- ! stretched version of trigger_i 
+  signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
+  signal s_trigger_out : std_logic := '0';  -- ! trigger shifted to start on strobe_4x_logic
+
+  -- Set length of output trigger here ( output length = length of this vector + 1 ) 
+  signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
+  
+                                                               
+BEGIN
+
+     
+  -- Copy reset/clk signal straight through
+  dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
+
+  dut_shutter_o <= shutter_to_dut_i;
+      
+  -- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
+  -- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_i
+  -- outputs: s_dut_clk
+  p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
+  begin  -- process p_dut_clk_gen
+    if rising_edge(clk_4x_logic_i) then
+      if (strobe_4x_logic_i = '1') then
+        s_dut_clk <= '1';
+        s_dut_clk_sr <= "001";
+      else
+        s_dut_clk <= s_dut_clk_sr(0);
+        s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);          
+      end if;
+    end if;
+  end process p_dut_clk_gen;
+
+  -- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic 
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
+  -- outputs: s_premask_trigger_to_dut
+  p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
+  begin  -- process p_dut_trig_retime
+    if rising_edge(clk_4x_logic_i)  then
+
+      -- Stretch trigger_i pulse to 4 clock cycles on clk4x
+      if trigger_i = '1' then
+        s_stretch_trig_in <= '1';
+        s_stretch_trig_in_sr <= ( others => '1' );
+      else
+        s_stretch_trig_in <= s_stretch_trig_in_sr(0);
+        s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (strobe_4x_logic_i  = '1') and ( s_stretch_trig_in = '1' ) then
+        s_trigger_out <= '1';
+        s_trigger_out_sr <= ( others => '1' );
+      else
+        s_trigger_out <= s_trigger_out_sr(0);
+        s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
+      end if;
+      
+    end if;
+  end process p_dut_trig_retime;
+
+    
+  -- purpose: register for internal signals and output signals
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
+  -- outputs: busy_o
+  register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
+  begin  -- process register_signals
+    if rising_edge(clk_4x_logic_i) then
+
+      s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
+
+      busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
+                ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
+
+      dut_clk_o <= s_dut_clk ;
+      dut_trigger_o <= DUT_mask_i and s_trigger_out;
+      
+    end if;
+  end process register_signals;
+
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_EUDET_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_EUDET_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..33b10128ece8ffa87532155333abf2d4105196e2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterface_EUDET_rtl.vhd
@@ -0,0 +1,275 @@
+--! @file
+-------------------------------------------------------------------------------
+--
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! @brief "EUDET style" interfaces to a DUT connection. Outputs TRIGGER and receives DUT_CLK and BUSY
+--! lines. Adapted from Trigger_Signal_Controller from EUDET TLU firmware.
+--!
+--! @author David.Cussans@bristol.ac.uk
+--! @date 1/Sept/2015
+------------------------------------------------------------------------------------
+entity DUTInterface_EUDET is
+  GENERIC( 
+    g_TRIGGER_DATA_WIDTH : positive := 32 -- was32
+   );
+  port (
+    rst_i : in std_logic;                --! asynchronous reset. Active high
+    busy_o : out std_logic;             --! low if FSM is in IDLE state, high otherwise
+    fsm_state_value_o : out std_logic_vector(3 downto 0);  --! detailed status of FSM.
+    trigger_i : in std_logic;        --! Trigger retimed onto system clock.active high. 
+    trigger_counter_i : in std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  --! event number
+    system_clk_i : in std_logic;          --! rising edge active clock from TLU
+    reset_or_clk_to_dut_i   : IN     std_logic;  --! Synchronization signal. Passed to DUT pins
+    shutter_to_dut_i        : IN     std_logic;  --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto flag set high
+    ignore_shutter_veto_i        : in     std_logic;
+    enable_dut_veto_i : in std_logic;      --! If high: if DUT raises dut_busy_i, then  busy_o is raised
+    -- Connections to DUT:
+    dut_clk_i : in std_logic;             --! rising edge active clock from DUT
+    dut_busy_i : in std_logic;            --! from DUT
+    dut_shutter_o      : OUT    std_logic;     --! Shutter output.
+    dut_trigger_o : out std_logic    --! trigger to DUT
+    );
+end DUTInterface_EUDET;
+
+architecture rtl of DUTInterface_EUDET is
+
+-----------------------------------------------------------------------------
+-- Declarations for state machine
+  type state_type is (IDLE , WAIT_FOR_BUSY_HIGH , TRIGGER_DEGLITCH_DELAY1 ,
+                      TRIGGER_DEGLITCH_DELAY2 , WAIT_FOR_BUSY_LOW 
+                     , DUT_INITIATED_VETO );
+--                      );
+  signal state , next_state : state_type;
+
+  -- Xilinx Voodoo for state machine
+  attribute SAFE_IMPLEMENTATION : string;
+  attribute SAFE_IMPLEMENTATION of state : signal is "yes";
+  -- End of Xilinx Voodoo
+
+-----------------------------------------------------------------------------
+
+--  signal internal_clk : std_logic;
+  signal serial_trig_data : std_logic;
+  signal trig_shift_reg : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  
+                                        -- shift register storing parallel trigger data
+--  signal d1_output  :  std_logic;
+--  signal d2_output  :  std_logic;
+  signal dut_rising_edge  :  std_logic;
+  signal shift_reg_ce  :  std_logic;
+
+  signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic;  -- ! registered values
+  
+begin  -- rtl
+
+
+  dut_shutter_o <= shutter_to_dut_i ; -- for now just pass through.
+  
+  -- purpose: suppress meta-stability by registering input signals.
+  -- type   : combinational
+  -- inputs : dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2
+  -- outputs: dut_busy_r2 , dut_clk_r2
+  register_signals: process ( dut_busy_r1 , dut_clk_r1 , system_clk_i )
+  begin  -- process register_signals
+    if rising_edge(system_clk_i) then
+
+      dut_busy_r2 <= dut_busy_r1 ;
+      dut_clk_r2 <= dut_clk_r1;
+      dut_busy_r1 <= dut_busy_i ;
+      dut_clk_r1 <= dut_clk_i;
+      
+    end if;
+  end process register_signals;
+
+
+  
+  rising_edge_pulse: entity work.single_pulse
+    port map (
+      level => dut_clk_i,
+      clk   => system_clk_i,
+      pulse => dut_rising_edge);
+
+  
+-- look for the rising edge of DUT clock and enable CE for one cycle.
+  -- I have a nasty suspicion that meta-stability issues may make this
+  -- go horribly wrong .
+-- Need to add timing constraint that shift_reg_ce must arrive before clock at trig_data_driver
+-- also WAIT_FOR_BUSY_LOW must not mess things up.
+  clk_enable_select: process (state, dut_rising_edge)
+begin  -- process
+  if (state=WAIT_FOR_BUSY_LOW) then
+    shift_reg_ce <= dut_rising_edge;
+  else
+    shift_reg_ce <= '0';
+  end if;
+end process;
+
+  
+   
+  
+  -- purpose: controls the serial_trig_data line
+  -- type   : combinational
+  -- inputs : system_clk_i , trigger_counter_i
+  -- outputs: serial_trig_data
+  trig_data_driver: process (system_clk_i , trigger_counter_i , shift_reg_ce , trig_shift_reg , state)
+  begin
+    
+    if rising_edge( system_clk_i ) then
+
+      -- if busy is high in response to a trigger shift data out of
+      -- register on rising edge of DUT clock . This is done by having a slow
+      -- DUT clock and setting shift_reg_ce for one cycle of system_clk_i when
+      -- the DUT clock rising edge comes by.
+      if (shift_reg_ce ='1' ) then
+        trig_shift_reg <= '0' & trig_shift_reg(g_TRIGGER_DATA_WIDTH-1 downto 1);
+        serial_trig_data <= trig_shift_reg(0);
+
+      -- otherwise load shift register if we have just had a trigger.
+      elsif (state = WAIT_FOR_BUSY_HIGH ) then        
+	-- only clock out bottom 15 bits of data. 
+        -- (replace fixed width with a mask at some stage ?)
+	trig_shift_reg <=  "00000000000000000" & trigger_counter_i(14 downto 0);
+        serial_trig_data <= '0';
+      end if;
+
+    end if;
+    
+  end process trig_data_driver;
+
+
+  -- purpose: Determine the next state
+  -- type   : combinational
+  -- inputs : state,Dut_Busy_r2, trigger_i
+  state_logic: process (state,  trigger_i ,  enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
+  begin  -- process state_logic
+    case state is
+	 
+      when IDLE =>
+        if ( trigger_i = '1') then  -- respond to trigger going high
+          next_state <= WAIT_FOR_BUSY_HIGH;  -- wait for DUT to respond to busy
+
+        elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then      -- If DUT asserts DUT_CLK_I then veto triggers
+          next_state <= DUT_INITIATED_VETO;          
+
+        else          
+          next_state <= IDLE;
+        end if;
+
+      when WAIT_FOR_BUSY_HIGH =>
+        if (DUT_Busy_r2 = '1') then
+          next_state <= TRIGGER_DEGLITCH_DELAY1;
+        else
+          next_state <= WAIT_FOR_BUSY_HIGH;
+        end if;
+
+        -- put in a pause to supress glitch in output trigger
+        -- this is an inelegant (to say the least ) way of doing it.
+      when TRIGGER_DEGLITCH_DELAY1 =>
+          next_state <= TRIGGER_DEGLITCH_DELAY2;
+
+      -- delay for two clock cycles.
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        next_state <= WAIT_FOR_BUSY_LOW;
+
+
+
+      when WAIT_FOR_BUSY_LOW =>
+        if (DUT_Busy_r2 = '1')  then
+          next_state <= WAIT_FOR_BUSY_LOW;
+        else
+          next_state <= IDLE;
+        end if;        
+
+      when DUT_INITIATED_VETO =>
+        if (( dut_clk_r2 = '0' ) or ( enable_dut_veto_i = '0')) then
+          next_state <= IDLE;
+        else
+          next_state <= DUT_INITIATED_VETO;
+        end if;
+        
+    end case;
+  end process state_logic;
+
+  -- determine clock select and trigger_mux from FSM state
+
+  
+  -- purpose: Determines the state of the dut_trigger_o output based on the state of the FSM
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: dut_trigger_o
+  output_logic: process (state,serial_trig_data)
+  begin  -- process output_logic
+    if ( state = IDLE ) then
+      -- waiting for external trigger to arrive...
+      dut_trigger_o <= '0';
+    elsif ((state = WAIT_FOR_BUSY_HIGH) or ( state=TRIGGER_DEGLITCH_DELAY1) or (state=TRIGGER_DEGLITCH_DELAY2) ) then
+      -- wait until the BUSY line goes high, then continue to hold TRIGGER high for two clock cycles.
+      dut_trigger_o <= '1';
+    elsif (state = WAIT_FOR_BUSY_LOW) then
+      -- if BUSY is high then connect TRIGGER to serial trigger number register.
+      dut_trigger_o <= serial_trig_data;
+    else
+      dut_trigger_o <= '0';
+    end if;
+  end process output_logic;
+
+    -- purpose: Register that holds the current state of the FSM
+  -- type   : combinational
+  -- inputs : system_clk_i , rst_i
+  -- outputs: state
+  state_register: process (system_clk_i , rst_i)
+  begin  -- process state_register
+    if (rst_i = '1') then
+      state <= IDLE;
+    elsif rising_edge(system_clk_i) then
+      state <= next_state;
+    end if;
+  end process state_register;
+
+
+  -- purpose: sets the value of clock_select based on FSM state
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: clock_select , trigger_muxsel , fsm_state
+  set_busy: process (system_clk_i , state)
+  begin  -- process set_muxsel
+    if rising_edge(system_clk_i) then
+          if (state = IDLE) then
+            busy_o <= '0';
+          else
+            busy_o <= '1';
+          end if;
+    end if;
+ end process set_busy;
+  
+  -- purpose: Sets the fsm_state_value_o vector to a number representing the current state
+  -- type   : combinational
+  -- inputs : system_clk_i , state
+  -- outputs: fsm_state_value_o
+  store_state: process (system_clk_i , state)
+  begin  -- process store_state
+    case state is
+      when IDLE =>
+        fsm_state_value_o <= "0000";
+      when WAIT_FOR_BUSY_HIGH =>
+        fsm_state_value_o <= "0001";
+      when TRIGGER_DEGLITCH_DELAY1 =>
+        fsm_state_value_o <= "0010";
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        fsm_state_value_o <= "0011";
+      when WAIT_FOR_BUSY_LOW =>
+        fsm_state_value_o <= "0100";
+      when DUT_INITIATED_VETO =>
+        fsm_state_value_o <= "0101";
+      when others =>
+        fsm_state_value_o <= "1111";
+    end case;
+  end process store_state;
+
+
+
+  end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a5e89dae6a3b69e96ba0f5462be534fe860e07ff
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl.vhd
@@ -0,0 +1,353 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs (single ended)
+      busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+      clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      
+      --clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      --reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+      --trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      --shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 8;
+  constant c_N_STAT : positive := 8;
+  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                                               
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+------------------------------------------------------------------        
+--    clk_IOBUFDS_inst : IOBUFDS
+--      generic map (
+--        IOSTANDARD => "BLVDS_25")
+--      port map (
+--        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+--        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+--        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+--        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+--        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+--        );
+    
+        clk_to_dut(dut) <= s_clk_to_dut_aida(dut); -- do we need to disable this using T? No, the TLU now has enable signals.
+        s_clk_from_dut_eudet(dut) <= clk_from_dut(dut);
+        
+------------------------------------------------------------------        
+        -- Now the signals are single ended: remove IBUFDS and use IBUF
+--    busy_IBUFDS_inst : IBUFDS
+--      generic map (
+--        DIFF_TERM => TRUE, -- Differential Termination 
+--        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O => s_busy_from_dut(dut),  -- Buffer output
+--        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+--        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+--      );
+
+--    busy_IBUF_inst : IBUF
+--    generic map(
+--        IBUF_LOW_PWR => TRUE,
+--        IOSTANDARD => "DEFAULT"
+--    )
+--    port map(
+--        O => s_busy_from_dut(dut),
+--        I => busy_from_dut(dut)
+--    );
+    s_busy_from_dut(dut) <= busy_from_dut(dut) ;
+------------------------------------------------------------------        
+   
+--    trig_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+--        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+--      );
+
+    trigger_to_dut(dut) <= s_trigger_to_dut(dut);
+------------------------------------------------------------------        
+     
+--    clk_rst_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+--        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+--      );
+	
+	reset_to_dut(dut) <= s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut); 
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs 
+  dut_shutter_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+--    shutter_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+--        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+--        I =>  s_shutter_to_dut(dut) 	
+--        );
+        
+    shutter_to_dut(dut) <= s_shutter_to_dut(dut) ;	  
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or s_dut_veto(dut);
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  veto_o <=  s_intermediate_busy_or(g_NUM_DUTS);
+
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode) ;
+      s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode) ;
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6a19837a51836d597e13f99770e762fc1743831a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/DUTInterfaces_rtl_BKP.vhd
@@ -0,0 +1,328 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--! DUT(0) = RJ45 ( J3 )\n
+--! DUT(1) = HDMI ( J1 ) , furthest from RJ45\n
+--! DUT(2) = HDMI ( J2) , closest to RJ45\n
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut_n_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      busy_from_dut_p_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 8;
+  constant c_N_STAT : positive := 8;
+  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                                               
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+
+    clk_IOBUFDS_inst : IOBUFDS
+      generic map (
+        IOSTANDARD => "BLVDS_25")
+      port map (
+        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+        );
+    
+    busy_IBUFDS_inst : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O => s_busy_from_dut(dut),  -- Buffer output
+        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+      );
+		
+   
+    trig_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+      );
+     
+    clk_rst_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+      );
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs except RJ45  ( which (output 0) doesn't have a shutter
+  -- signal. )
+  dut_shutter_io: for dut in 1 to g_NUM_DUTS-1 generate
+
+    shutter_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+        I =>  s_shutter_to_dut(dut) 	
+        );
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or s_dut_veto(dut);
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  veto_o <=  s_intermediate_busy_or(g_NUM_DUTS);
+
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode) ;
+      s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode) ;
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/DUTs_outputs.vhd b/AIDA_tlu/legacy/TLU_v1c/common/DUTs_outputs.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..11366cba709fc387f9051a4f275eae7d22b01be1
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/DUTs_outputs.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 15.02.2017 13:17:26
+-- Design Name: 
+-- Module Name: DUTs_outputs - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DUTs_outputs is
+    Port ( clk_in : in STD_LOGIC;
+           d_clk_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_trg_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_busy_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_cont_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_spare_o : out STD_LOGIC_VECTOR (3 downto 0));
+end DUTs_outputs;
+
+architecture Behavioral of DUTs_outputs is
+signal toggleme : std_logic := '0'; 
+begin
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+        
+        if rising_edge(clk_in) then   -- rising clock edge
+            toggleme <= not toggleme;
+            d_clk_o(1) <= toggleme;
+            d_clk_o(2) <= '0';
+            d_clk_o(3) <= '0';
+            d_trg_o <=  ('0' & '0' & '0' & '0');
+            d_busy_o <= ('0' & '0' & '0' & '0');
+            d_cont_o <= ('0' & '0' & '0' & '0');
+            d_spare_o <=('0' & '0' & '0' & '0');
+        end if;
+        d_clk_o(0) <= clk_in;
+    end process gen_clk;
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/GPL_doxygen_header.vhdl b/AIDA_tlu/legacy/TLU_v1c/common/GPL_doxygen_header.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d9fdc487ef25fde77339ce30d5aff5ae4a75af3f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/GPL_doxygen_header.vhdl
@@ -0,0 +1,77 @@
+--! @file dtype_fds.vhdl
+--
+-------------------------------------------------------------------------------
+-- --
+-- (c) University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+--
+-- This file is part of IPBus.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--
+--! Standard library
+library IEEE;
+
+-- Standard logic defintions.
+use IEEE.STD_LOGIC_1164.all;
+
+--
+-- unit name: dtype_fds
+--
+--! @brief   Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/GPP_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/GPP_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bc02a5efb0ee30d0bdc486bac320ba25b6c7f611
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/GPP_rtl.vhd
@@ -0,0 +1,312 @@
+--=============================================================================
+--! @file GPP_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- 
+--
+--! @brief GPP - General purpose pulser. Generates a sycronous custom pulse \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 15:42:31 01/15/2013 
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: 
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity GPP is
+   GENERIC( 
+      g_IPBUS_WIDTH      : positive := 32
+   );
+	PORT( clk_i       		: IN     std_logic;                                          		--! Rising edge active
+			Enable_i          : IN     std_logic;                                          --
+			Reset_i           : IN     std_logic;                                          --
+			RstPulsCnt_i     	: IN     std_logic;                                          -- Reset pulse counter
+			Trigger_i         : IN     std_logic;                                          -- Trigger input signal
+			NMaxPulses_i      : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Max number of pulses
+			SuDTime_i         : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Startup dead time
+			PulsLen_i     		: IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Pulse length
+		   IpDTime_i         : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Interpulse dead time
+			RearmTime_i       : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Time before rearm after reach the max number of pulses
+			Force_PullDown_i  : IN     std_logic;                                          -- Force pull down
+			WU_i              : IN     std_logic;                                          -- Output trigger signal with update
+			PulseDelay_i      : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);    		 -- Pulse delay
+	      event_number_o    : OUT    std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Event number
+			MaxPulses_o       : OUT    std_logic;                                          -- Maximun number of pulses reached
+			Pulse_o           : OUT    std_logic;                                          --! pulse output
+			Pulse_d_o         : OUT    std_logic                                           --! pulse output delayed
+			);
+end GPP;
+
+architecture rtl of GPP is
+   --! FSM state values
+   type state_values is (st0, st1, st2, st3, st4, st5, st6);
+	signal pres_state, next_state: state_values;
+	
+	signal s_PulsCnt_en  		: std_logic := '0';                                             --! Pulse counter enable
+	signal s_RstPulsCnt       	: std_logic := '0';                                             --! Reset pulse counter
+	signal s_RstPulsCnt_int   	: std_logic := '0';                                             --! Reset pulse counter internal signal
+	signal s_PulsLen		      : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Pulse Length
+	signal s_PulsCnt     		: unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');        --! Pulse counter value
+	signal s_MaxPulses         : std_logic := '0';                                             --! Max number of pulses reached
+	signal s_Pulse             : std_logic := '0';                                             --! Active pulse signal
+	signal s_Pulse_d           : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others=>'0');  --! Active pulse signal delayed
+   
+	signal s_load_SuDTime      : std_logic := '1';                                             --! Counter load signal
+	signal s_SuDTime 				: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Startup dead time counter
+	signal EOSDT               : std_logic := '0';                                             --! End of startup dead time signal
+	
+	signal s_load_PulsLen     : std_logic := '1';                                           	--! Counter load
+	signal EOP                 : std_logic := '0';                                             --! End of pulse length signal
+	
+	signal s_load_IpDTime      : std_logic := '1';                                             --! Counter load signal
+	signal s_IpDTime 				: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Interpulse dead time counter
+	signal EOIDT               : std_logic := '0';                                             --! End of interpulse dead time signal
+	
+	signal s_load_RearmTime    : std_logic := '1';                                             --! Rearm counter load signal
+	signal s_RearmLen     		: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Startup dead time counter
+	signal EOREARM             : std_logic := '0';                                             --! End of startup dead time signal
+
+begin
+	-----------------------------------------------------------------------------
+	-- Counters
+	-----------------------------------------------------------------------------
+	--! Startup dead time counter
+   c_startup_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_SuDTime,
+		InitVal 	=> std_logic_vector(unsigned(s_SuDTime)-1),
+		Count		=> open,
+		Q 			=> EOSDT
+	);
+	s_SuDTime <= x"00000001" when SuDTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else SuDTime_i;
+	
+	--! Pulse time counter
+   c_pulse_time : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_PulsLen,
+		InitVal 	=> std_logic_vector(unsigned(s_PulsLen)-1),
+		Count		=> open,
+		Q 			=> EOP
+	);
+	s_PulsLen <= x"00000001" when PulsLen_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else PulsLen_i;
+	
+	--! Interpulse dead time counter
+   c_interpulse_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_IpDTime,
+		InitVal 	=> std_logic_vector(unsigned(s_IpDTime)-1),
+		Count		=> open,
+		Q 			=> EOIDT
+	);
+	s_IpDTime <= x"00000001" when IpDTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else IpDTime_i;
+	
+	--! Rearm time after the max pulses reached
+   c_rearm_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_RearmTime,
+		InitVal 	=> std_logic_vector(unsigned(s_RearmLen)-1),
+		Count		=> open,
+		Q 			=> EOREARM
+	);
+	s_RearmLen <= x"00000001" when RearmTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+						else RearmTime_i;
+			 
+
+	--! FSM register
+	statereg: process(clk_i, Enable_i, Reset_i)
+	begin
+		if Enable_i = '0'  then 
+			pres_state <= st0;            -- Move to st0 - INITIAL STATE
+      
+		elsif Reset_i = '1' then
+			pres_state <= st0;            -- Move to st0 - INITIAL STATE
+        
+		elsif rising_edge(clk_i) then
+			pres_state <= next_state;     -- Move to next state
+        
+		end if;
+	end process statereg;
+
+
+   --! FSM combinational block
+	fsm: process(pres_state, Enable_i, Reset_i, Trigger_i, s_MaxPulses, EOP, EOSDT, EOIDT, Force_PullDown_i)
+	begin
+	  next_state <= pres_state;
+	  -- Default values
+	  s_Pulse          	<= '0';
+	  s_load_SuDTime     <= '1';
+	  s_load_PulsLen 		<= '1';
+	  s_load_IpDTime     <= '1';
+	  s_load_RearmTime	<= '1';
+	  s_RstPulsCnt_int   <= '0';
+  
+     case pres_state is
+	  
+	    -- st0 - INITIAL STATE
+		 when st0=>
+         if (Enable_i = '1') and (Reset_i = '0') then 
+           next_state <= st1;            -- Next state is "st1 - IDLE"
+         end if;
+       
+		 -- st1 - IDLE STATE
+       when st1=>
+         if s_MaxPulses = '1' then
+           next_state <= st5;            -- Next state is "st5 - NMAX PULSES REACHED"
+         else
+           if Trigger_i = '1' and Force_PullDown_i = '0' then 
+             if (to_integer(unsigned(SuDTime_i)) = 0) then
+               next_state <= st3;        -- Next state is "st3 - PULSE"
+             else
+               next_state <= st2;        -- Next state is "st2 - STARTUP DEAD-TIME"
+             end if; 
+           end if;
+         end if;
+		 
+		 -- st2 - STARTUP DEAD-TIME
+       when st2=>
+         s_load_SuDTime <= '0';
+           if EOSDT = '1' then
+             next_state <= st3;          -- Next state is "st3 - PULSE"
+           end if;
+		
+		 -- st3 - PULSE
+       when st3=>
+         s_Pulse <= '1';
+         s_load_PulsLen <= '0';
+				
+         if (EOP = '1') or (Force_PullDown_i = '1')then
+           if (to_integer(unsigned(IpDTime_i)) = 0) then
+             next_state <= st1;         -- Next state is "st1 - IDLE"
+           else
+             next_state <= st4;         -- Next state is "st4 - INTERPULSE DEAD-TIME"
+           end if;
+         end if;
+				
+         if Trigger_i = '1' then
+           if (WU_i = '1') then
+             next_state <= st6;         -- Next state is "st6 - RELOAD PULSE TIMER"
+           end if;	
+         end if;
+       
+		 
+		 -- st4 - INTERPULSE DEAD-TIME
+       when st4=>
+         s_load_IpDTime <= '0';
+         if EOIDT = '1' then
+           next_state <= st1;            -- Next state is "st1 - IDLE"
+         end if;
+				
+		 -- st5 - NMAX PULSES REACHED
+       when st5=>
+		   s_load_RearmTime <= '0';
+			if EOREARM = '1' then
+			  next_state <= st1;            -- Next state is "st1 - IDLE"
+			  s_RstPulsCnt_int <= '1';
+			end if;
+			
+		 -- st6 - RELOAD PULSE TIMER
+       when st6=>
+         s_Pulse <= '1';
+         next_state <= st3;              -- Next state is "st3 - PULSE"
+			
+--       when others=>
+--         next_state<=st0;                -- Next state is "st0 - INITIAL STATE"
+     
+	  end case;
+	
+	end process fsm;    
+	
+	-- Pulse reg
+	p_reg_pulse : process ( clk_i , Reset_i )
+   begin  
+	  if Reset_i = '1' then
+	    s_Pulse_d <= (others => '0');
+	  
+	  elsif rising_edge(clk_i) then
+       for i in 0 to g_IPBUS_WIDTH-2 loop
+         s_Pulse_d(i+1) <= s_Pulse_d(i);
+       end loop;
+	    s_Pulse_d(0) <= s_Pulse;
+	  end if;
+	end process p_reg_pulse;
+	
+	event_number_o <= std_logic_vector(s_PulsCnt);
+	MaxPulses_o <= s_MaxPulses;
+	Pulse_o 		<= s_Pulse;
+	Pulse_d_o 	<= s_Pulse when PulseDelay_i = x"00000000" else
+						s_Pulse_d(to_integer(unsigned(PulseDelay_i)-1));
+	
+	
+	-----------------------------------------------------------------------------
+	-- Count runs and synchronization
+	-----------------------------------------------------------------------------
+	p_PulsCounter : process (clk_i )
+	begin  -- process p_run_counter
+
+		if rising_edge(clk_i) then
+			if s_RstPulsCnt = '1' then
+				s_PulsCnt <= (others => '0');
+			elsif s_PulsCnt_en = '1' then
+				s_PulsCnt <= s_PulsCnt + 1;
+			end if;
+		
+		end if;
+	end process p_PulsCounter;
+  
+	s_RstPulsCnt <= Reset_i or RstPulsCnt_i or s_RstPulsCnt_int;
+	s_PulsCnt_en <= '1' when (s_Pulse = '1') and (s_Pulse_d(0) = '0') and (s_MaxPulses = '0')
+	                      else '0'; 
+	s_MaxPulses <= '1' when (s_PulsCnt = unsigned(NMaxPulses_i)) and (NMaxPulses_i /= x"00000000")
+                  else '0';
+
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/IODELAYCal_FSM_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/IODELAYCal_FSM_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d69931d3dd04bfae2a5f4876c7984d6ebf0e28f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/IODELAYCal_FSM_rtl.vhd
@@ -0,0 +1,102 @@
+--=============================================================================
+--! @file IODELAYCal_FSM_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- UoB , USC
+-- --
+------------------------------------------------------------------------------- --
+--
+--! @brief Finite-state machine to control calibration and reset signals to
+--! Iserdes, IDelay
+--! based on code by Alvaro Dosil\n
+--
+--! @author  Alvaro Dosil 
+--
+--! @date 22/Feb/2014
+--
+--! @version v0.1
+--
+--! @details
+--
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--! <another thing to do> \n
+
+  LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity IODELAYCal_FSM is
+	port (
+		clk_i 		: in std_logic;		--! Global clock
+		startcal_i 	: in std_logic;      --! Start calibration
+		busy_i 		: in std_logic;     	--! Status of the IDELAY component
+		calibrate_o : out std_logic;     --! Calibration signals to IODELAY
+		reset_o 		: out std_logic  		--! Reset to IODELAY component
+    );
+end entity IODELAYCal_FSM;
+
+architecture rtl of IODELAYCal_FSM is
+
+  --! Calibration FSM state values
+  type state_values is (st0, st1, st2, st3);
+  signal pres_state, next_state: state_values := st0;
+  
+	signal s_cal_FSM      : std_logic := '0';         -- IODELAY reset
+  signal s_rst_FSM      : std_logic := '0';         -- IODELAY reset
+  
+begin  -- rtl
+
+  --! Calibration FSM register
+  statereg: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      pres_state <= next_state;     -- Move to next state
+      
+    end if;
+  end process statereg;
+
+
+  --! Calibration FSM combinational block
+  fsm: process(pres_state, startcal_i, busy_i)
+  begin
+    next_state <= pres_state;
+    -- Default values
+    s_Rst_FSM <= '0';
+    s_cal_FSM <= '0';
+    
+    case pres_state is
+      
+      -- st0 - IDLE
+      when st0=>
+        if ( startcal_i = '1') then 
+          next_state <= st1;            -- Next state is "st1 - SEND CALIBRATION SIGNAL"
+        end if;
+        
+      -- st1 - SEND CALIBRATION SIGNAL
+      when st1=>
+        s_cal_FSM <= '1';
+		  next_state <= st2;            -- Next state is "st2 - WAIT BUSY = '0'"
+        
+      -- st2 - WAIT BUSY = '0'
+      when st2=>
+        if busy_i = '0' then 
+          next_state <= st3;            -- Next state is "st3 - RESET STATE"
+        end if;
+        
+        -- st3 - RESET STATE
+      when st3=>
+        s_Rst_FSM <= '1';
+		  next_state <= st0;              -- Next state is "st0 - IDLE"
+		
+    end case;
+    
+  end process fsm;
+
+  calibrate_o <= s_cal_FSM;
+  reset_o <= s_Rst_FSM;
+                
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/IPBusInterface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/IPBusInterface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..aa9bd6decdaad84c5b7eceef5aa580c92b5c28e2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/IPBusInterface_rtl.vhd
@@ -0,0 +1,261 @@
+--=============================================================================
+--! @file IPBusInterface_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+--! @brief IPBus interface between 1GBit/s Ethernet and IPBus internal bus
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 16:06:57 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+ENTITY IPBusInterface IS
+   GENERIC( 
+      NUM_EXT_SLAVES : positive := 5;
+      BUILD_SIMULATED_ETHERNET : integer := 0 --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
+   );
+   PORT( 
+      gmii_rx_clk_i    : IN     std_logic;
+      gmii_rx_dv_i     : IN     std_logic;
+      gmii_rx_er_i     : IN     std_logic;
+      gmii_rxd_i       : IN     std_logic_vector (7 DOWNTO 0);
+      ipbr_i           : IN     ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0);  --! IPBus read signals
+      sysclk_n_i       : IN     std_logic;
+      sysclk_p_i       : IN     std_logic;                                   --! 200 MHz xtal clock
+      clocks_locked_o  : OUT    std_logic;
+      gmii_gtx_clk_o   : OUT    std_logic;
+      gmii_tx_en_o     : OUT    std_logic;
+      gmii_tx_er_o     : OUT    std_logic;
+      gmii_txd_o       : OUT    std_logic_vector (7 DOWNTO 0);
+      ipb_clk_o        : OUT    std_logic;                                   --! IPBus clock to slaves
+      ipb_rst_o        : OUT    std_logic;                                   --! IPBus reset to slaves
+      ipbw_o           : OUT    ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0);  --! IBus write signals
+      onehz_o          : OUT    std_logic;
+      phy_rstb_o       : OUT    std_logic;
+      dip_switch_i     : IN     std_logic_vector (3 DOWNTO 0); --! Used to select IP address
+      clk_logic_xtal_o : OUT    std_logic  --! 40MHz clock that can be used for logic if not using external clock
+   );
+
+-- Declarations
+
+END ENTITY IPBusInterface ;
+
+--
+ARCHITECTURE rtl OF IPBusInterface IS
+  
+  --! Number of slaves inside the IPBusInterface block.
+  constant c_NUM_INTERNAL_SLAVES : positive := 1;
+
+  signal clk125,  rst_125, rst_ipb: STD_LOGIC;
+  signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
+  signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
+  signal ipb_master_out : ipb_wbus;
+  signal ipb_master_in : ipb_rbus;
+  signal mac_addr: std_logic_vector(47 downto 0);
+  signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+  signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+
+  signal ip_addr: std_logic_vector(31 downto 0);
+  signal s_ipb_clk : std_logic;
+  signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+  signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+  signal s_sysclk : std_logic;
+  signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
+  
+BEGIN
+
+  -- Connect IPBus clock and reset to output ports.
+  ipb_clk_o <= s_ipb_clk;
+  ipb_rst_o <= rst_ipb;
+
+  --! By default generate a physical MAC
+  generate_physicalmac: if ( BUILD_SIMULATED_ETHERNET /= 1 ) generate
+      
+--	DCM clock generation for internal bus, ethernet
+--	clocks: entity work.clocks_s6_extphy port map(
+--          sysclk_p => sysclk_p_i,
+--          sysclk_n => sysclk_n_i,
+--          clk_logic_xtal_o => clk_logic_xtal_o,
+--          clko_125 => clk125,
+--          clko_ipb => s_ipb_clk,
+--          locked => clocks_locked_o,
+--          rsto_125 => rst_125,
+--          rsto_ipb => rst_ipb,
+--          onehz => onehz_o
+--          );
+    
+    clocks: entity work.clocks_7s_extphy_Se port map(
+        sysclk_p => sysclk_p_i,
+        sysclk_n => sysclk_n_i,
+        clk_logic_xtal_o => clk_logic_xtal_o,
+        clko_125 => clk125,
+        clko_ipb => s_ipb_clk,
+        locked => clocks_locked_o,
+        rsto_125 => rst_125,
+        rsto_ipb => rst_ipb,
+        onehz => onehz_o
+        );
+				
+	-- leds <= ('0', '0', locked, onehz);
+	
+--	Ethernet MAC core and PHY interface
+-- In this version, consists of hard MAC core and GMII interface to external PHY
+-- Can be replaced by any other MAC / PHY combination
+
+--        eth: entity work.eth_s6_gmii port map(
+--          clk125 => clk125,
+--          rst => rst_125,
+--          gmii_gtx_clk => gmii_gtx_clk_o,
+--          gmii_tx_en => gmii_tx_en_o,
+--          gmii_tx_er => gmii_tx_er_o,
+--          gmii_txd => gmii_txd_o,
+--          gmii_rx_clk => gmii_rx_clk_i,
+--          gmii_rx_dv => gmii_rx_dv_i,
+--          gmii_rx_er => gmii_rx_er_i,
+--          gmii_rxd => gmii_rxd_i,
+--          tx_data => mac_tx_data,
+--          tx_valid => mac_tx_valid,
+--          tx_last => mac_tx_last,
+--          tx_error => mac_tx_error,
+--          tx_ready => mac_tx_ready,
+--          rx_data => mac_rx_data,
+--          rx_valid => mac_rx_valid,
+--          rx_last => mac_rx_last,
+--          rx_error => mac_rx_error
+--          );
+          
+      eth: entity work.eth_7s_rgmii port map(
+            clk125 => clk125,
+            rst => rst_125,
+            tx_data => mac_tx_data,
+            tx_valid => mac_tx_valid,
+            tx_last => mac_tx_last,
+            tx_error => mac_tx_error,
+            tx_ready => mac_tx_ready,
+            rx_data => mac_rx_data,
+            rx_valid => mac_rx_valid,
+            rx_last => mac_rx_last,
+            rx_error => mac_rx_error,
+            gmii_gtx_clk => gmii_gtx_clk_o,
+            gmii_tx_en => gmii_tx_en_o,
+            gmii_tx_er => gmii_tx_er_o,
+            gmii_txd => gmii_txd_o,
+            gmii_rx_clk => gmii_rx_clk_i,
+            gmii_rx_dv => gmii_rx_dv_i,
+            gmii_rx_er => gmii_rx_er_i,
+            gmii_rxd => gmii_rxd_i            
+            );
+          	
+  end generate generate_physicalmac;
+
+    --! Set generic BUILD_SIMULATED_ETHERNET to 1 to generate a simulated MAC
+    generate_simulatedmac: if ( BUILD_SIMULATED_ETHERNET = 1 ) generate
+
+      sim_clocks: entity work.clock_sim
+	port map (
+	  clko125 => clk125,
+	  clko25 => s_ipb_clk,
+	  clko40 =>  clk_logic_xtal_o,
+	  nuke   => '0',
+	  rsto   => rst_125
+          );
+      rst_ipb <= rst_125;
+      clocks_locked_o  <= '1';
+      
+      -- clk125 <= sysclk_i; -- *must* run this simulation with 125MHz sysclk...
+      simulated_eth: entity work.eth_mac_sim
+        port map(
+          clk => clk125,
+          rst => rst_125,
+          tx_data => mac_tx_data,
+          tx_valid => mac_tx_valid,
+          tx_last => mac_tx_last,
+          tx_error => mac_tx_error,
+          tx_ready => mac_tx_ready,
+          rx_data => mac_rx_data,
+          rx_valid => mac_rx_valid,
+          rx_last => mac_rx_last,
+          rx_error => mac_rx_error
+          );
+    end generate generate_simulatedmac;
+
+  phy_rstb_o <= '1';
+  
+-- ipbus control logic
+        ipbus: entity work.ipbus_ctrl
+          generic map (
+            BUFWIDTH => 2)
+          port map(
+            mac_clk => clk125,
+            rst_macclk => rst_125,
+            ipb_clk => s_ipb_clk,
+            rst_ipb => rst_ipb,
+            mac_rx_data => mac_rx_data,
+            mac_rx_valid => mac_rx_valid,
+            mac_rx_last => mac_rx_last,
+            mac_rx_error => mac_rx_error,
+            mac_tx_data => mac_tx_data,
+            mac_tx_valid => mac_tx_valid,
+            mac_tx_last => mac_tx_last,
+            mac_tx_error => mac_tx_error,
+            mac_tx_ready => mac_tx_ready,
+            ipb_out => ipb_master_out,
+            ipb_in => ipb_master_in,
+            mac_addr => mac_addr,
+            ip_addr => ip_addr,
+            pkt_rx => pkt_rx,
+            pkt_tx => pkt_tx,
+            pkt_rx_led => pkt_rx_led,
+            pkt_tx_led => pkt_tx_led
+            );
+
+	
+	mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
+	ip_addr   <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
+ 
+  fabric: entity work.ipbus_fabric
+    generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
+    port map(
+      ipb_in => ipb_master_out,
+      ipb_out => ipb_master_in,
+      ipb_to_slaves => s_ipbw_internal,
+      ipb_from_slaves => s_ipbr_internal
+    );
+    
+    ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
+
+    s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
+         
+  -- Slave: firmware ID
+  firmware_id: entity work.ipbus_ver
+    port map(
+      ipbus_in =>  s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
+      ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
+      );
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/Reg_2clks.vhd b/AIDA_tlu/legacy/TLU_v1c/common/Reg_2clks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df7168fc6283b56b28cef8af2b300d774b576bf7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/Reg_2clks.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    31/07/2012 
+-- Module Name:    Reg_2clks - Behavioral 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 1b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity Reg_2clks is
+  port(
+    clk_i : in std_logic;  --! Synchronous clock
+	 async_i : in std_logic;  --! Asynchronous input data
+	 sync_o : out std_logic   --! Synchronous output data
+	 );
+end Reg_2clks;
+
+--! @brief
+--! @details Synchronize 1 bit of data 
+
+architecture Behavioral of Reg_2clks is
+signal sreg : std_logic_vector(1 downto 0);
+
+attribute TIG : string;
+attribute IOB : string;
+attribute ASYNC_REG : string;
+attribute SHIFT_EXTRACT : string;
+attribute HBLKNM : string;
+
+attribute TIG of async_i : signal is "TRUE";
+attribute IOB of async_i : signal is "FALSE";
+attribute ASYNC_REG of sreg : signal is "TRUE";
+attribute SHIFT_EXTRACT of sreg : signal is "NO";
+attribute HBLKNM of sreg : signal is "sync_reg";
+
+begin
+
+process (clk_i)
+begin
+   if rising_edge(clk_i) then  
+     sync_o <= sreg(1);
+	  sreg <= sreg(0) & async_i;
+   end if;
+end process;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/T0_Shutter_Iface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/T0_Shutter_Iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ef24ee2a7bc35342592fd06c079f0650de54c878
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/T0_Shutter_Iface_rtl.vhd
@@ -0,0 +1,114 @@
+--! @file T0_Shutter_Iface_rtl.vhd
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Simple module to generate T0 and shutter signals under IPBus control
+--! Similar interface to TPx3_iface_rtl.vhd
+--
+--! @details
+--! \n \n IPBus address map:
+--! \li 00 - shutter. Bit 0. Output shutter = value of bit-0
+--! \li 01 - T0 write to pulse T0.
+--
+--! @author David Cussans
+
+entity T0_Shutter_Iface is
+
+  port (
+    clk_4x_i      : in  std_logic;    --! system clock
+    clk_4x_strobe : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    T0_o          : out std_logic;    --! T0 signal retimed onto system clock
+    shutter_o          : out std_logic;    --! shutter signal retimed onto system clock
+
+    ipbus_clk_i            : IN     std_logic; --! IPBus system clock
+    ipbus_i                : IN     ipb_wbus;
+    ipbus_o                : OUT    ipb_rbus
+          
+    );     
+
+end entity T0_Shutter_Iface;
+
+architecture rtl of T0_Shutter_Iface is
+
+  signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+  signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
+  signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+
+  signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+
+  signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+                                                                             
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  
+begin  -- architecture rtl
+
+  --------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_T0_ipbus <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+                when "00" => s_shutter_ipbus <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter
+                when "01" => s_T0_ipbus <= '1';
+                when others => null;
+            end case;
+        end if;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+
+    ------------------
+    p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
+    begin  -- process p_T0_retime
+    if rising_edge(clk_4x_i)  then
+        -- Register IPBus clocked signals onto clk 4x. So clk4x must be faster
+        -- than ipbus_clk for this to work.
+        s_T0_ipbus_d1 <= s_T0_ipbus;
+        s_T0_ipbus_d2 <= s_T0_ipbus_d1;
+        -- Shutter is a DC level, so clock speeds don't matter.
+        s_shutter_ipbus_d1 <= s_shutter_ipbus;
+        s_shutter_ipbus_d2 <= s_shutter_ipbus_d1;
+        -- Stretch T0_i pulse to 4 clock cycles on clk4x
+        if ( s_T0_ipbus_d2 = '1' ) then
+            s_stretch_T0_in <= '1';
+            s_stretch_T0_in_sr <= "111";
+        else
+            s_stretch_T0_in <= s_stretch_T0_in_sr(0);
+            s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
+        end if;
+ 
+        if (clk_4x_strobe  = '1') and ( s_stretch_T0_in = '1' ) then
+            T0_o <= '1';
+            s_T0_out_sr <= "111";
+        else
+            T0_o <= s_T0_out_sr(0);
+            s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
+        end if;
+    end if;
+    end process p_T0_retime;
+    
+  -- Just retime onto the 4x clock. Probably should retime onto 1x clock.
+    p_shutter_retime: process (s_shutter , clk_4x_i) is
+    begin  -- process p_shutter_retime
+    if rising_edge(clk_4x_i)  then
+        s_shutter_d1 <= ( s_shutter_ipbus );
+        s_shutter_d2 <= s_shutter_d1;
+        shutter_o    <= s_shutter_d2;
+    end if;
+    end process p_shutter_retime;
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/TPx3Logic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/TPx3Logic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e35cfacd18f53ec298aefd1d5f836b05254aa2c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/TPx3Logic_rtl.vhd
@@ -0,0 +1,177 @@
+--=============================================================================
+--! @file TPx3Logic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
+--
+--! @brief Produces shutters \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 16:06:19 11/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY TPx3Logic IS
+	GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i      				: IN     std_logic;                                    -- ! Rising edge active
+		Start_T0sync_i			: IN 		std_logic;
+		T0syncLen_i				: IN 		std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+      logic_reset_i       	: IN     std_logic;                                    -- active high. Synchronous with clk_4x_logic
+      Busy_i					: IN     std_logic;
+		Veto_i					: IN     std_logic;
+		Shutter_o				: OUT 	std_logic;
+		T0sync_o 				: OUT 	std_logic
+   );
+	
+
+-- Declarations
+
+END ENTITY TPx3Logic ;
+
+--
+ARCHITECTURE rtl OF TPx3Logic IS
+
+	type state_values is (st0, st1);
+	signal pres_state, next_state: state_values;
+
+	signal s_Enable : std_logic := '0';
+	signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
+	signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
+	signal Rst_T0sync, T0syncT : 		std_logic;   	--Load signal and flag for the T0sync
+	signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for runs
+	
+BEGIN
+
+	-----------------------------------------------------------------------------
+	-- Counters
+	-----------------------------------------------------------------------------
+	--T0sync counter
+	c_T0sync: entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> Rst_T0sync,
+		InitVal 	=> std_logic_vector(unsigned(T0syncLen_i)-1),
+		Count		=> open,
+		Q 			=> T0syncT
+	);
+  
+  
+  -----------------------------------------------------------------------------
+  -- FSM register
+  -----------------------------------------------------------------------------
+	statereg: process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			pres_state <= next_state;  --Move to the next state
+		end if;
+	end process statereg;
+	
+	
+	-----------------------------------------------------------------------------
+	-- FSM combinational block
+	-----------------------------------------------------------------------------
+	fsm: process(pres_state, s_Start_T0sync, T0syncT)
+	begin
+		next_state<=pres_state;
+		s_T0sync	<='0';
+		Rst_T0sync <= '1';
+		
+		case pres_state is
+			when st0=>
+				if s_Start_T0sync = '1' then 
+					next_state <= st1; --Next state is "Whait for end of T0sync signal"
+				end if;
+			when st1 =>
+				Rst_T0sync <='0';
+				s_T0sync <='1';
+				if T0syncT = '1' then
+					next_state<=st0; --Next state is "Whait for end of T0-sync counter"
+				end if;
+			when others=>
+				next_state<=st0; --Next state is "Whait for T0sync start"
+		end case;
+	end process fsm;
+
+  
+	-----------------------------------------------------------------------------
+	-- Busy signals
+	-----------------------------------------------------------------------------
+	s_Enable <= not Veto_i;
+	s_Shutter <= not Busy_i and not Veto_i;
+	--Shutter_o <= s_Shutter;
+	--T0sync_o <= s_T0sync;
+  
+	
+	-----------------------------------------------------------------------------
+	-- Count runs and synchronization
+	-----------------------------------------------------------------------------
+	p_run_counter: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Start_T0sync_d1 <= Start_T0sync_i;
+			s_Start_T0sync_d2 <= s_Start_T0sync_d1;
+			s_Start_T0sync_d3 <= s_Start_T0sync_d2;
+			s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3); 
+		
+			s_Shutter_d1 <= s_Shutter;
+		
+			if logic_reset_i = '1' then
+				s_RunNumber <= (others => '0');
+			elsif s_Shutter='1' and s_Shutter_d1='0' then
+				s_RunNumber <= s_RunNumber + 1;
+			end if;
+		end if;
+		-- Signals synchronous with falling edge clock
+		if falling_edge(clk_i) then
+			s_Shutter_d1f <= s_Shutter;
+			Shutter_o <= s_Shutter_d1f;
+			
+			s_T0sync_d1f <= s_T0sync;
+			T0sync_o <= s_T0sync_d1f;
+		end if;
+  end process p_run_counter;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/TPx3_iface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/TPx3_iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f576ac1ba6db98f073e84d5cf6abb1de943fb998
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/TPx3_iface_rtl.vhd
@@ -0,0 +1,160 @@
+--! @file TPx3_iface_rtl.vhd
+--! @brief Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
+--! Accepts T0 sync signal and shutter signal from telescope and re-transmits.
+--! @details
+--! IPBus address map:
+--! 00 - shutter. Bit 0. Output shutter = external shutter XOR ipbus shutter
+--! 01 - T0 write to pulse T0.
+--! @author David Cussans
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+
+entity TPx3_iface is
+
+  port (
+    clk_4x_i      : in  std_logic;    --! system clock
+    clk_4x_strobe : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    T0_p_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_n_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_o          : out std_logic;    --! T0 signal retimed onto system clock
+    shutter_p_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_n_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_o          : out std_logic;    --! shutter signal retimed onto system clock
+
+    ipbus_clk_i            : IN     std_logic; --! IPBus system clock
+    ipbus_i                : IN     ipb_wbus;
+    ipbus_o                : OUT    ipb_rbus
+          
+    );     
+
+end entity TPx3_iface;
+
+architecture rtl of TPx3_iface is
+
+  signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+  signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
+  signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+
+  signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+
+  signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_external_signal_mask : std_logic_vector(ipbus_i.ipb_wdata'range) := ( others => '0'); --! Set bits to mask external signals : 0 to mask external T0 , set bit 1 to mask external shutter
+  signal s_maskExternalShutter , s_maskExternalT0 : std_logic := '0';  -- ! Set to 1 to mask external signals
+                                                                             
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  
+begin  -- architecture rtl
+
+  --------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_T0_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+        case ipbus_i.ipb_addr(1 downto 0) is
+          when "00" => s_shutter_ipbus <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter
+          when "01" => s_T0_ipbus <= '1';
+          when "10" => s_external_signal_mask <= ipbus_i.ipb_wdata;
+          when others => null;
+        end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+
+
+    ------------------
+    
+  cmp_IBUFDS_T0 : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_T0,  -- Buffer output
+        I =>  T0_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => T0_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+        
+    p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
+  begin  -- process p_T0_retime
+    if rising_edge(clk_4x_i)  then
+
+      s_maskExternalShutter <= s_external_signal_mask(1);
+      s_maskExternalT0 <= s_external_signal_mask(0);
+        
+      s_T0_d1 <= s_T0;
+      s_T0_d2 <= s_T0_d1;
+
+      -- Register IPBus clocked signals onto clk 4x. So clk4x must be faster
+      -- than ipbus_clk for this to work.
+      s_T0_ipbus_d1 <= s_T0_ipbus;
+      s_T0_ipbus_d2 <= s_T0_ipbus_d1;
+
+      -- Shutter is a DC level, so clock speeds don't matter.
+      s_shutter_ipbus_d1 <= s_shutter_ipbus;
+      s_shutter_ipbus_d2 <= s_shutter_ipbus_d1;
+      
+      
+      -- Stretch T0_i pulse to 4 clock cycles on clk4x
+      if ( (( s_T0_d2 = '1' ) and ( s_maskExternalT0 = '0')) or ( s_T0_ipbus_d2 = '1' )) then
+        s_stretch_T0_in <= '1';
+        s_stretch_T0_in_sr <= "111";
+      else
+        s_stretch_T0_in <= s_stretch_T0_in_sr(0);
+        s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (clk_4x_strobe  = '1') and ( s_stretch_T0_in = '1' ) then
+        T0_o <= '1';
+        s_T0_out_sr <= "111";
+      else
+        T0_o <= s_T0_out_sr(0);
+        s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
+      end if;
+
+      
+    end if;
+  end process p_T0_retime;
+    
+  cmp_IBUFDS_shutter : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_shutter,  -- Buffer output
+        I =>  shutter_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => shutter_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  -- Just retime onto the 4x clock. Probably should retime onto 1x clock.
+  p_shutter_retime: process (s_shutter , clk_4x_i) is
+  begin  -- process p_shutter_retime
+    if rising_edge(clk_4x_i)  then
+      s_shutter_d1 <= ( ( s_shutter and not s_maskExternalShutter ) xor s_shutter_ipbus );
+      s_shutter_d2 <= s_shutter_d1;
+      shutter_o    <= s_shutter_d2;
+    end if;
+  end process p_shutter_retime;
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/arrivalTimeLUT_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/arrivalTimeLUT_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f1b1acc0fb60c0741bc98fc83a2b8acf194ebddc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/arrivalTimeLUT_rtl.vhd
@@ -0,0 +1,187 @@
+--=============================================================================
+--! @file arrivalTimeLUT_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.ArivalTimeLUT.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! @brief Uses a look-up-table to convert the eight bits from the two 1:4 deserializers\n
+--! into a 5-bit time ( 3 bits from the position in 8-bit deserialized data \n
+--! plus two bits from position w.r.t. the strobe_4x_logic_i signal ( one pulse
+--! every 4 cycles of clk_4x_logic_i 
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:46:34 11/21/12
+--
+--! @version v0.1
+--
+--! @details
+--! Rising and falling edge times encoded as a LUT. Contents:
+--! MRFrrrfff
+--! \li M = multiple edges present ( more than one rising or falling edge)
+--! \li R = at least one rising edge present
+--! \li F = at least one falling edge present.
+--! \li rrr = time of first rising edge
+--! \li fff = time of first falling edge
+ENTITY arrivalTimeLUT IS
+   GENERIC( 
+      g_NUM_FINE_BITS   : positive := 3;
+      g_NUM_COARSE_BITS : positive := 2
+   );
+   PORT( 
+      clk_4x_logic_i           : IN     std_logic;                                                        --! Rising edge active
+      strobe_4x_logic_i        : IN     std_logic;                                                        --! Pulses high once every 4 cycles of clk_4x_logic
+      deserialized_data_i      : IN     std_logic_vector (8 DOWNTO 0);                                    --! Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data
+      first_rising_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      last_falling_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      rising_edge_o            : OUT    std_logic;                                                        --! goes high if there is a rising edge in the data. Clocked by clk_4x_logic_i
+      falling_edge_o           : OUT    std_logic;                                                        --! goes high if there is a falling edge in the data.Clocked by clk_4x_logic_i
+      multiple_edges_o         : OUT    std_logic                                                         --! there is more than one rising or falling edge transition.
+   );
+
+-- Declarations
+
+END ENTITY arrivalTimeLUT ;
+
+--
+ARCHITECTURE rtl OF arrivalTimeLUT IS
+
+  constant c_FALLING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS;  --! Bit position of bit set when falling edge detected
+  constant c_RISING_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+1;  --! Bit position of bit set when rising edge detected
+  constant c_MULTI_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+2;  --! Bit position of bit set when rising edge detected
+
+
+  signal s_coarse_bits : std_logic_vector(g_NUM_COARSE_BITS-1 downto 0) := "00";  --! phase w.r.t. strobe
+
+  signal s_LUT_ENTRY : std_logic_vector(g_NUM_FINE_BITS*2 +3-1 downto 0);  -- stores intermediate LUT value.
+  
+  type t_LUT is array (natural range <>) of std_logic_vector(g_NUM_FINE_BITS*2 + 3 -1 downto 0);
+  --! Lookup table for arrival time and rising/falling edge detection (3bits
+  --! for position in 9-bit deserialized data plus two bits for rising/falling 
+  constant c_LUT : t_LUT(0 to 511) := (
+    "000000000", "001000000", "011000001", "001000001", "011001010", "011001010", "011000010", "001000010", --0 [0, 7]
+    "011010011", "011010011", "111000011", "011010011", "011001011", "011001011", "011000011", "001000011", --1 [8, 15]
+    "011011100", "011011100", "111000100", "011011100", "111001100", "111001100", "111000100", "011011100", --2 [16, 23]
+    "011010100", "011010100", "111000100", "011010100", "011001100", "011001100", "011000100", "001000100", --3 [24, 31]
+    "011100101", "011100101", "111000101", "011100101", "111001101", "111001101", "111000101", "011100101", --4 [32, 39]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011100101", --5 [40, 47]
+    "011011101", "011011101", "111000101", "011011101", "111001101", "111001101", "111000101", "011011101", --6 [48, 55]
+    "011010101", "011010101", "111000101", "011010101", "011001101", "011001101", "011000101", "001000101", --7 [56, 63]
+    "011101110", "011101110", "111000110", "011101110", "111001110", "111001110", "111000110", "011101110", --8 [64, 71]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --9 [72, 79]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --10 [80, 87]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --11 [88, 95]
+    "011100110", "011100110", "111000110", "011100110", "111001110", "111001110", "111000110", "011100110", --12 [96, 103]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011100110", --13 [104, 111]
+    "011011110", "011011110", "111000110", "011011110", "111001110", "111001110", "111000110", "011011110", --14 [112, 119]
+    "011010110", "011010110", "111000110", "011010110", "011001110", "011001110", "011000110", "001000110", --15 [120, 127]
+    "011110111", "011110111", "111000111", "011110111", "111001111", "111001111", "111000111", "011110111", --16 [128, 135]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --17 [136, 143]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --18 [144, 152]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --19 [152, 159]
+    "111100111", "111100111", "111000111", "111100111", "111001111", "111001111", "111000111", "111100111", --20 [160, 167]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "111100111", --21 [168, 175]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --22 [176, 183]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --23 [184, 191]
+    "011101111", "011101111", "111000111", "011101111", "111001111", "111001111", "111000111", "011101111", --24 [192, 199]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --25 [200, 207]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --26 [208, 215]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --27 [216, 223]
+    "011100111", "011100111", "111000111", "011100111", "111001111", "111001111", "111000111", "011100111", --28 [224, 231]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011100111", --29 [232, 239]
+    "011011111", "011011111", "111000111", "011011111", "111001111", "111001111", "111000111", "011011111", --30 [240, 247]
+    "011010111", "011010111", "111000111", "011010111", "011001111", "011001111", "011000111", "001000111", --31 [248, 255]
+    "010111000", "011111000", "111000001", "011111001", "111001010", "111001010", "111000010", "011111010", --32 [256, 263]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011111011", --33 [264, 271]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --34 [272, 279]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011111100", --35 [280, 287]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --36 [288, 295]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --37 [296, 303]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --38 [304, 311]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011111101", --39 [312, 319]
+    "111101110", "111101110", "111000110", "111101110", "111001110", "111001110", "111000110", "111101110", --40 [320, 327]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --41 [328, 333]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --42 [336, 343]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --43 [344, 351]
+    "111100110", "111100110", "111000110", "111100110", "111001110", "111001110", "111000110", "111100110", --44 [352, 359]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111100110", --45 [360, 367]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --46 [368, 375]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011111110", --47 [376, 383]
+    "010110000", "011110000", "111000001", "011110001", "111001010", "111001010", "111000010", "011110010", --48 [384, 391]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011110011", --49 [392, 399]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --50 [400, 407]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011110100", --51 [408, 415]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --52 [416, 423]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --53 [424, 431]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --54 [432, 439]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011110101", --55 [440, 447]
+    "010101000", "011101000", "111000001", "011101001", "111001010", "111001010", "111000010", "011101010", --56 [448, 455]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011101011", --57 [456, 463]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --58 [464, 471]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011101100", --59 [472, 479]
+    "010100000", "011100000", "111000001", "011100001", "111001010", "111001010", "111000010", "011100010", --60 [480, 487]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011100011", --61 [488, 495]
+    "010011000", "011011000", "111000001", "011011001", "111001010", "111001010", "111000010", "011011010", --62 [496, 503]
+    "010010000", "011010000", "111000001", "011010001", "010001000", "011001000", "010000000", "000000000" -- 63 [504, 511]
+    );  
+  
+BEGIN
+
+  -- purpose: uses the deserialized data as a index into
+  --          a lookup table holding the position of the first rising edge (if any)
+  --          and if there is a rising or falling edge
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: arrival_time_o , rising_edge_o , falling_edge_o
+  examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
+--    variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0);  --! Entry in LUT pointed to by deserialized data
+  begin  -- process examine_lut
+    
+--    v_LUT_entry := c_LUT(to_integer(unsigned(deserialized_data_i)));
+
+    if rising_edge(clk_4x_logic_i) then
+      s_LUT_ENTRY <= c_LUT(to_integer(unsigned(deserialized_data_i)));
+      first_rising_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS*2-1 downto g_NUM_FINE_BITS);
+      last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
+      rising_edge_o  <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
+      falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
+      multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT); 
+    end if;
+
+  end process examine_lut;
+  
+  --! Coarse time stamp. Phase w.r.t. strobe
+--	c_coarse_ts : entity work.CounterUp
+--   PORT MAP (
+--     clk   => clk_4x_logic_i,
+--     ce    => '1',
+--     sinit => strobe_4x_logic_i, --'0',
+--	  q(31 downto 2) => open,
+--     q(1 downto 0)  => s_coarse_bits
+--	);
+--  
+  	c_coarse_ts : entity work.CounterWithReset
+  	GENERIC MAP (
+  	  g_COUNTER_WIDTH => 2 )
+   PORT MAP (
+     clock_i   => clk_4x_logic_i,
+     enable_i   => '1',
+     reset_i => strobe_4x_logic_i,        -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
+     result_o => s_coarse_bits
+	);
+	
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ax3_pm3_mTLUvC.xdc b/AIDA_tlu/legacy/TLU_v1c/common/ax3_pm3_mTLUvC.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..8ba1064658293761a501e40ee6056de99763e53e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ax3_pm3_mTLUvC.xdc
@@ -0,0 +1,377 @@
+# -------------------------------------------------------------------------------------------------
+# -- Project             : Mars AX3 
+# -- File description    : User Constraint File for Mars PM3 Base Board
+# -- File name           : mars_ax3_pm3.xdc
+# -- Authors             : Kanishk Sugand / Marc Oberholzer
+# -------------------------------------------------------------------------------------------------
+# -- Copyright © 2012 by Enclustra GmbH, Switzerland. All rights are reserved. 
+# -- Unauthorized duplication of this document, in whole or in part, by any means is prohibited
+# -- without the prior written permission of Enclustra GmbH, Switzerland.
+# -- 
+# -- Although Enclustra GmbH believes that the information included in this publication is correct
+# -- as of the date of publication, Enclustra GmbH reserves the right to make changes at any time
+# -- without notice.
+# -- 
+# -- All information in this document may only be published by Enclustra GmbH, Switzerland.
+# -------------------------------------------------------------------------------------------------
+# -- Notes:
+# -- 1. For best I/O timing, it is necessary to set the following options in Xilinx ISE/PlanAhead: 
+# --    map option "Pack I/O registers into IOBs" to "Inputs and Outputs"
+# -- 2. The IO standards for banks 0, 2 and 3 are only valid if VCCO_0/VCCO_2/VCCO_3 = 3.3 V
+# -------------------------------------------------------------------------------------------------
+# -- File history:
+# --
+# -- Version | Date       | Author             | Remarks
+# -- ----------------------------------------------------------------------------------------------
+# -- 1.0     | 11.4.14    | C. Glattfelder     | converted from UCF
+# -------------------------------------------------------------------------------------------------
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: global clock inputs
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN P17 [get_ports {Clk_50}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Clk_50}]
+set_property PACKAGE_PIN L16 [get_ports {Fpga_Emcclk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Fpga_Emcclk}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ddr3 sdram
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[8]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[5]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cas_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[0]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Odt]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[4]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cke]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[2]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_We_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_N]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Ras_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[12]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_P]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[11]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Reset_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN A15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN E15 [get_ports {Ddr3_Dq[3]}]
+set_property PACKAGE_PIN B11 [get_ports {Ddr3_Dq[15]}]
+set_property PACKAGE_PIN B18 [get_ports {Ddr3_Dq[4]}]
+set_property PACKAGE_PIN F14 [get_ports {Ddr3_Dq[14]}]
+set_property PACKAGE_PIN B17 [get_ports {Ddr3_Dq[5]}]
+set_property PACKAGE_PIN A11 [get_ports {Ddr3_Dq[13]}]
+set_property PACKAGE_PIN A16 [get_ports {Ddr3_Dq[6]}]
+set_property PACKAGE_PIN F13 [get_ports {Ddr3_Dq[12]}]
+set_property PACKAGE_PIN B16 [get_ports {Ddr3_Dq[7]}]
+set_property PACKAGE_PIN D14 [get_ports {Ddr3_Dq[11]}]
+set_property PACKAGE_PIN B14 [get_ports {Ddr3_Dq[8]}]
+set_property PACKAGE_PIN B13 [get_ports {Ddr3_Dq[10]}]
+set_property PACKAGE_PIN C14 [get_ports {Ddr3_Dq[9]}]
+set_property PACKAGE_PIN E16 [get_ports {Ddr3_Dq[1]}]
+set_property PACKAGE_PIN A14 [get_ports {Ddr3_Dqs_N[0]}]
+set_property PACKAGE_PIN A18 [get_ports {Ddr3_Dq[0]}]
+set_property PACKAGE_PIN D12 [get_ports {Ddr3_Dm[1]}]
+set_property PACKAGE_PIN D15 [get_ports {Ddr3_Dm[0]}]
+set_property PACKAGE_PIN A13 [get_ports {Ddr3_Dqs_P[0]}]
+set_property PACKAGE_PIN C16 [get_ports Ddr3_Clk_P]
+set_property PACKAGE_PIN C17 [get_ports Ddr3_Clk_N]
+set_property PACKAGE_PIN G14 [get_ports Ddr3_Cke]
+set_property PACKAGE_PIN B12 [get_ports {Ddr3_Dqs_N[1]}]
+set_property PACKAGE_PIN F16 [get_ports Ddr3_Cas_N]
+set_property PACKAGE_PIN K15 [get_ports {Ddr3_Ba[2]}]
+set_property PACKAGE_PIN H14 [get_ports {Ddr3_Ba[1]}]
+set_property PACKAGE_PIN C12 [get_ports {Ddr3_Dqs_P[1]}]
+set_property PACKAGE_PIN D17 [get_ports {Ddr3_Ba[0]}]
+set_property PACKAGE_PIN F18 [get_ports {Ddr3_A[9]}]
+set_property PACKAGE_PIN H17 [get_ports {Ddr3_A[8]}]
+set_property PACKAGE_PIN K16 [get_ports Ddr3_Odt]
+set_property PACKAGE_PIN E18 [get_ports {Ddr3_A[7]}]
+set_property PACKAGE_PIN K13 [get_ports {Ddr3_A[6]}]
+set_property PACKAGE_PIN E17 [get_ports {Ddr3_A[5]}]
+set_property PACKAGE_PIN F15 [get_ports Ddr3_Ras_N]
+set_property PACKAGE_PIN J13 [get_ports {Ddr3_A[4]}]
+set_property PACKAGE_PIN D18 [get_ports {Ddr3_A[3]}]
+set_property PACKAGE_PIN J18 [get_ports {Ddr3_A[2]}]
+set_property PACKAGE_PIN G13 [get_ports Ddr3_Reset_N]
+set_property PACKAGE_PIN G17 [get_ports {Ddr3_A[13]}]
+set_property PACKAGE_PIN H16 [get_ports {Ddr3_A[12]}]
+set_property PACKAGE_PIN G18 [get_ports {Ddr3_A[11]}]
+set_property PACKAGE_PIN J15 [get_ports Ddr3_We_N]
+set_property PACKAGE_PIN G16 [get_ports {Ddr3_A[10]}]
+set_property PACKAGE_PIN J14 [get_ports {Ddr3_A[1]}]
+set_property PACKAGE_PIN J17 [get_ports {Ddr3_A[0]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ethernet
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rst_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Txc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports Eth_Link_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Tx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports Eth_Tx_Ctl]
+set_property PACKAGE_PIN R18 [get_ports {Eth_Txd[0]}]
+set_property PACKAGE_PIN V16 [get_ports {Eth_Rxd[3]}]
+set_property PACKAGE_PIN V15 [get_ports {Eth_Rxd[2]}]
+set_property PACKAGE_PIN V17 [get_ports {Eth_Rxd[1]}]
+set_property PACKAGE_PIN T18 [get_ports {Eth_Txd[1]}]
+set_property PACKAGE_PIN U16 [get_ports {Eth_Rxd[0]}]
+set_property PACKAGE_PIN T14 [get_ports Eth_Rxc]
+set_property PACKAGE_PIN R16 [get_ports Eth_Rx_Ctl]
+set_property PACKAGE_PIN U17 [get_ports {Eth_Txd[2]}]
+set_property PACKAGE_PIN M13 [get_ports Eth_Rst_N]
+set_property PACKAGE_PIN N14 [get_ports Eth_Mdio]
+set_property PACKAGE_PIN P14 [get_ports Eth_Mdc]
+set_property PACKAGE_PIN U18 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN C15 [get_ports Eth_Link_N]
+set_property PACKAGE_PIN N16 [get_ports Eth_Txc]
+set_property PACKAGE_PIN T15 [get_ports Eth_Int_N]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: i2c
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R17 [get_ports I2c_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Int_N]
+set_property PACKAGE_PIN N17 [get_ports I2c_Scl]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Scl]
+set_property PACKAGE_PIN P18 [get_ports I2c_Sda]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Sda]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: spi flash
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN L13 [get_ports Flash_Cs_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Cs_N]
+set_property PACKAGE_PIN K17 [get_ports Flash_Di]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Di]
+set_property PACKAGE_PIN M14 [get_ports Flash_Hold_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Hold_N]
+set_property PACKAGE_PIN L14 [get_ports Flash_Wp_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Wp_N]
+set_property PACKAGE_PIN R10 [get_ports Flash_Clk]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Clk]
+set_property PACKAGE_PIN K18 [get_ports Flash_Do]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Do]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: led		
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN M17 [get_ports {Led_N[1]}]
+set_property PACKAGE_PIN M16 [get_ports {Led_N[0]}]
+set_property PACKAGE_PIN M18 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN L18 [get_ports {Led_N[2]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: system		
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R11 [get_ports Pwr_Good]
+set_property IOSTANDARD LVCMOS33 [get_ports Pwr_Good]
+set_property PACKAGE_PIN N15 [get_ports {Reset_N}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Reset_N}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: fmc lpc connector
+# -------------------------------------------------------------------------------------------------
+set_property PACKAGE_PIN T4 [get_ports {CLK_TO_FPGA_N}]
+set_property PACKAGE_PIN T5 [get_ports {CLK_TO_FPGA_P}]
+set_property PACKAGE_PIN D3 [get_ports {CLK_FROM_FPGA_N}]
+set_property PACKAGE_PIN E3 [get_ports {CLK_FROM_FPGA_P}]
+
+set_property PACKAGE_PIN N5 [get_ports {CLK_GEN_LOL_N}]
+set_property PACKAGE_PIN C1 [get_ports {CLK_GEN_RST_N}]
+set_property PACKAGE_PIN C2 [get_ports {I2C_RESET_N}]
+set_property PACKAGE_PIN F6 [get_ports {GPIO}]
+
+set_property PACKAGE_PIN P5 [get_ports {CONT_TO_FPGA[0]}]
+set_property PACKAGE_PIN P3 [get_ports {CONT_TO_FPGA[1]}]
+set_property PACKAGE_PIN N6 [get_ports {CONT_TO_FPGA[2]}]
+set_property PACKAGE_PIN L5 [get_ports {CONT_TO_FPGA[3]}]
+
+# Warning - can't find CONT_FROM_FPGA[0] in Allegro netlist ....
+set_property PACKAGE_PIN P4 [get_ports {CONT_FROM_FPGA[1]}]
+set_property PACKAGE_PIN M6 [get_ports {CONT_FROM_FPGA[2]}]
+set_property PACKAGE_PIN L6 [get_ports {CONT_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN M1 [get_ports {SPARE_TO_FPGA[0]}]
+set_property PACKAGE_PIN N4 [get_ports {SPARE_TO_FPGA[1]}]
+set_property PACKAGE_PIN N1 [get_ports {SPARE_TO_FPGA[2]}]
+set_property PACKAGE_PIN M2 [get_ports {SPARE_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN L1 [get_ports {SPARE_FROM_FPGA[0]}]
+set_property PACKAGE_PIN M4 [get_ports {SPARE_FROM_FPGA[1]}]
+set_property PACKAGE_PIN N2 [get_ports {SPARE_FROM_FPGA[2]}]
+set_property PACKAGE_PIN M3 [get_ports {SPARE_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN R5 [get_ports {TRIG_TO_FPGA[0]}]
+set_property PACKAGE_PIN R2 [get_ports {TRIG_TO_FPGA[1]}]
+set_property PACKAGE_PIN T1 [get_ports {TRIG_TO_FPGA[2]}]
+set_property PACKAGE_PIN V1 [get_ports {TRIG_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R6 [get_ports {TRIG_FROM_FPGA[0]}]
+set_property PACKAGE_PIN P2 [get_ports {TRIG_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R1 [get_ports {TRIG_FROM_FPGA[2]}]
+set_property PACKAGE_PIN U1 [get_ports {TRIG_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN T6 [get_ports {BUSY_TO_FPGA[0]}]
+set_property PACKAGE_PIN U3 [get_ports {BUSY_TO_FPGA[1]}]
+set_property PACKAGE_PIN T8 [get_ports {BUSY_TO_FPGA[2]}]
+set_property PACKAGE_PIN L4 [get_ports {BUSY_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R7 [get_ports {BUSY_FROM_FPGA[0]}]
+set_property PACKAGE_PIN U4 [get_ports {BUSY_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R8 [get_ports {BUSY_FROM_FPGA[2]}]
+set_property PACKAGE_PIN K5 [get_ports {BUSY_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN L3 [get_ports {DUT_CLK_TO_FPGA[0]}]
+set_property PACKAGE_PIN F3 [get_ports {DUT_CLK_TO_FPGA[1]}]
+set_property PACKAGE_PIN D2 [get_ports {DUT_CLK_TO_FPGA[2]}]
+set_property PACKAGE_PIN G3 [get_ports {DUT_CLK_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN K3 [get_ports {DUT_CLK_FROM_FPGA_P[0]}]
+set_property PACKAGE_PIN F4 [get_ports {DUT_CLK_FROM_FPGA_P[1]}]
+set_property PACKAGE_PIN E2 [get_ports {DUT_CLK_FROM_FPGA_P[2]}]
+set_property PACKAGE_PIN G4 [get_ports {DUT_CLK_FROM_FPGA_P[3]}]
+
+set_property PACKAGE_PIN A1 [get_ports {BEAM_TRIGGER_N[0]}]
+set_property PACKAGE_PIN B1 [get_ports {BEAM_TRIGGER_P[0]}]
+set_property PACKAGE_PIN B4 [get_ports {BEAM_TRIGGER_N[1]}]
+set_property PACKAGE_PIN C4 [get_ports {BEAM_TRIGGER_P[1]}]
+set_property PACKAGE_PIN K1 [get_ports {BEAM_TRIGGER_N[2]}]
+set_property PACKAGE_PIN K2 [get_ports {BEAM_TRIGGER_P[2]}]
+set_property PACKAGE_PIN C5 [get_ports {BEAM_TRIGGER_N[3]}]
+set_property PACKAGE_PIN C6 [get_ports {BEAM_TRIGGER_P[3]}]
+set_property PACKAGE_PIN H4 [get_ports {BEAM_TRIGGER_N[4]}]
+set_property PACKAGE_PIN J4 [get_ports {BEAM_TRIGGER_P[4]}]
+set_property PACKAGE_PIN G1 [get_ports {BEAM_TRIGGER_N[5]}]
+set_property PACKAGE_PIN H1 [get_ports {BEAM_TRIGGER_P[5]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ft232 uart interface
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B3 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B2 [get_ports FTDI_RXD]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ez-usb fx3 interface
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN V2 [get_ports FX3_A1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_A1]
+set_property PACKAGE_PIN V7 [get_ports FX3_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_CLK]
+set_property PACKAGE_PIN U12 [get_ports FX3_DQ0]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ0]
+set_property PACKAGE_PIN R15 [get_ports FX3_DQ1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ1]
+set_property PACKAGE_PIN U9 [get_ports FX3_DQ10]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ10]
+set_property PACKAGE_PIN V5 [get_ports FX3_DQ11]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ11]
+set_property PACKAGE_PIN T3 [get_ports FX3_DQ12]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ12]
+set_property PACKAGE_PIN R3 [get_ports FX3_DQ13]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ13]
+set_property PACKAGE_PIN V4 [get_ports FX3_DQ14]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ14]
+set_property PACKAGE_PIN U7 [get_ports FX3_DQ15]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ15]
+set_property PACKAGE_PIN V12 [get_ports FX3_DQ2]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ2]
+set_property PACKAGE_PIN P15 [get_ports FX3_DQ3]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ3]
+set_property PACKAGE_PIN U11 [get_ports FX3_DQ4]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ4]
+set_property PACKAGE_PIN U13 [get_ports FX3_DQ5]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ5]
+set_property PACKAGE_PIN T13 [get_ports FX3_DQ6]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ6]
+set_property PACKAGE_PIN T11 [get_ports FX3_DQ7]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ7]
+set_property PACKAGE_PIN V9 [get_ports FX3_DQ8]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ8]
+set_property PACKAGE_PIN U6 [get_ports FX3_DQ9]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ9]
+set_property PACKAGE_PIN V6 [get_ports FX3_FLAGA]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGA]
+set_property PACKAGE_PIN U2 [get_ports FX3_FLAGB]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGB]
+set_property PACKAGE_PIN T10 [get_ports FX3_PKTEND_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_PKTEND_N]
+set_property PACKAGE_PIN T9 [get_ports FX3_SLOE_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLOE_N]
+set_property PACKAGE_PIN R12 [get_ports FX3_SLRD_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLRD_N]
+set_property PACKAGE_PIN R13 [get_ports FX3_SLWR_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLWR_N]
+
+# -------------------------------------------------------------------------------------------------
+# timing constraints
+# -------------------------------------------------------------------------------------------------
+
+
+create_clock -name {Clk_50} -period 20.000 [get_ports {Clk_50}]
+
+
+# -------------------------------------------------------------------------------------------------
+# eof
+# -------------------------------------------------------------------------------------------------
+
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/clock_sim.vhd b/AIDA_tlu/legacy/TLU_v1c/common/clock_sim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7a9e09e740105fc390fbad6b54b8a9b81f15070a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/clock_sim.vhd
@@ -0,0 +1,47 @@
+-- Behavioural model of clocks for ipbus testing
+--
+-- The clock edges are *not* delta cycle accurate
+-- Do not assume any phase relationship between clk125, clk25
+--
+-- Dave Newbold, March 2011
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clock_sim is
+	port(
+	  clko125: out std_logic;
+	  clko25: out std_logic;
+	  clko40: out std_logic;
+	  nuke: in std_logic;
+	  rsto: out std_logic
+  );
+
+end clock_sim;
+
+architecture behavioural of clock_sim is
+
+  signal clk125, clk25, clk40, nuke_del: std_logic := '0';
+  signal reset_vec: std_logic_vector(3 downto 0) := X"f";
+
+begin
+
+  clk125 <= not clk125 after 4 ns;
+  clk25 <= not clk25 after 20 ns;
+  clk40 <= not clk40 after 12.5ns;
+  
+  clko125 <= clk125;
+  clko25 <= clk25;
+  clko40 <= clk40;
+  
+  process(clk25)
+  begin
+    if rising_edge(clk25) then
+      reset_vec <= '0' & reset_vec(3 downto 1);
+    end if;
+  end process;
+
+  nuke_del <= nuke after 50us;
+  rsto <= reset_vec(0) or nuke_del;
+
+end behavioural;
\ No newline at end of file
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy.vhd b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..47c0f3b8be2e66484167147fed8c5fec8f591d97
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy.vhd
@@ -0,0 +1,148 @@
+-- clocks_7s_extphy
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy is
+	port(
+		sysclk_p: in std_logic;
+		sysclk_n: in std_logic;
+		clko_125: out std_logic;
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;
+		rsto_ipb: out std_logic;
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic
+	);
+
+end clocks_7s_extphy;
+
+architecture rtl of clocks_7s_extphy is
+	
+	signal dcm_locked, sysclk, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+	ibufgds0: IBUFGDS port map(
+		i => sysclk_p,
+		ib => sysclk_n,
+		o => sysclk
+	);
+	
+	clko_200 <= sysclk; -- io delay ref clock only, no bufg
+
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clk_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 5.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90,
+			clkout3_divide => 32,
+			clkin1_period => 5.0
+		)
+		port map(
+			clkin1 => sysclk,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk125_90_i,
+			clkout3 => clk_ipb_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk)
+	begin
+		if rising_edge(sysclk) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se.vhd b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90c77ffd8e81f354ff8f4bc9b4032b834ee70ce3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se.vhd
@@ -0,0 +1,151 @@
+-- clocks_7s_extphy_se
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 50MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy_Se is
+	port(
+		sysclk: in std_logic;
+		clko_125: out std_logic;
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;
+		rsto_ipb: out std_logic;
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic
+	);
+
+end clocks_7s_extphy_se;
+
+architecture rtl of clocks_7s_extphy_se is
+	
+	signal dcm_locked, sysclk_i, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b, clk_200_i: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+	ibufgds0: IBUFG port map(
+		i => sysclk,
+		o => sysclk_i
+	);
+	
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clko_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	bufg200: BUFG port map(
+		i => clk_200_i,
+		o => clko_200
+	);	
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 20.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90.0,
+			clkout3_divide => 32,
+			clkout4_divide => 5,
+			clkin1_period => 20.0
+		)
+		port map(
+			clkin1 => sysclk_i,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk_125_90_i,
+			clkout3 => clk_ipb_i,
+			clkout4 => clk_200_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk_i,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk_i)
+	begin
+		if rising_edge(sysclk_i) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se_MOD.vhd b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se_MOD.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7d67ef7b0a9bb441d1b7c26831c9c5859768fc03
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/clocks_7s_extphy_se_MOD.vhd
@@ -0,0 +1,158 @@
+-- clocks_7s_extphy_se
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 50MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy_Se is
+	port(
+		--sysclk: in std_logic;
+		sysclk_p: in std_logic;--
+        sysclk_n: in std_logic;--
+        clko_125: out std_logic;--
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;--
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;--
+		rsto_ipb: out std_logic;--
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic--
+	);
+
+end clocks_7s_extphy_se;
+
+architecture rtl of clocks_7s_extphy_se is
+	
+	signal dcm_locked, sysclk_i, sysclk, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b, clk_200_i: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+--	ibufgds0: IBUFG port map(
+--		i => sysclk,
+--		o => sysclk_i
+--	);
+    ibufgds0: IBUFGDS port map(
+    i => sysclk_p,
+    ib => sysclk_n,
+    o => sysclk
+    );
+	
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clko_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	bufg200: BUFG port map(
+		i => clk_200_i,
+		o => clko_200
+	);	
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 20.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90.0,
+			clkout3_divide => 32,
+			clkout4_divide => 5,
+			clkin1_period => 20.0
+		)
+		port map(
+			clkin1 => sysclk_i,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk_125_90_i,
+			clkout3 => clk_ipb_i,
+			clkout4 => clk_200_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk_i,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk_i)
+	begin
+		if rising_edge(sysclk_i) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/clocks_s6_extphy.vhd b/AIDA_tlu/legacy/TLU_v1c/common/clocks_s6_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d823b524a714e4dc09385c67def20a0f3baa83f4
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/clocks_s6_extphy.vhd
@@ -0,0 +1,137 @@
+--! @file clocks_s6_extphy
+-- 
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+--! Includes reset logic for ipbus
+--
+--! @author Dave Newbold
+--! @date April 2011
+--
+entity clocks_s6_extphy is port(
+	sysclk_p, sysclk_n: in std_logic; --! From on board crystal. By default 200MHz
+	clk_logic_xtal_o : out std_logic; --! Clock for TLU timing logic ( when not using external clock ). sysclk/5 ( i.e. by default 40MHz) 
+	clko_125: out std_logic; --! 125MHz for IPBus logic
+	clko_ipb: out std_logic; --! 32.5MHz for IPBus logic
+	locked: out std_logic;
+	rsto_125: out std_logic;
+	rsto_ipb: out std_logic;
+	onehz: out std_logic
+	);
+
+end clocks_s6_extphy;
+
+architecture rtl of clocks_s6_extphy is
+
+	signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
+        -- signal sysclk_in : std_logic;
+	signal d25, d25_d, dcm_locked: std_logic;
+	signal rst: std_logic := '1';
+	signal s_xtal_dcm_locked: std_logic;
+        signal s_clk_logic_xtal : std_logic;
+	-- signal clk_400: std_logic;
+	
+--	component clock_divider_s6 port(
+--		clk: in std_logic;
+--		d25: out std_logic;
+--		d28: out std_logic
+--	);
+--	end component;
+	
+begin
+
+	ibufgds0: IBUFGDS port map(
+		i => sysclk_p,
+		ib => sysclk_n,
+		o => sysclk
+	);
+
+--        -- Add global clock buffer in sysclk path.
+--        bufg_sysclk : BUFG port map (
+--          i => sysclk_in,
+--          o => sysclk);
+        
+	bufg_125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+	
+	clko_125 <= clk_125_b;
+	
+	bufg_ipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	bufg_clk_logic_xtal: BUFG port map(
+	  i => s_clk_logic_xtal,
+	  o => clk_logic_xtal_o
+	  );
+	  
+	clko_ipb <= clk_ipb_b;
+
+	dcm0: DCM_CLKGEN
+		generic map(
+			CLKIN_PERIOD => 5.0,
+			CLKFX_MULTIPLY => 5,
+			CLKFX_DIVIDE => 8,
+			CLKFXDV_DIVIDE => 4
+		)
+		port map(
+			clkin => sysclk,
+			clkfx => clk_125_i,
+			clkfxdv => clk_ipb_i,
+			locked => dcm_locked,
+			rst => '0'
+		);
+		
+	clkdiv: entity work.clock_divider_s6 port map(
+--        clkdiv: entity work.clock_div port map(
+		clk => sysclk,
+--                D17 => open,
+		d25 => d25,
+		d28 => onehz
+	);
+	  
+	process(sysclk)
+	begin
+		if rising_edge(sysclk) then
+			d25_d <= d25;
+			if d25='1' and d25_d='0' then
+				rst <= not dcm_locked;
+			end if;
+		end if;
+	end process;
+	
+	locked <= dcm_locked;
+
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rsto_ipb <= rst;
+		end if;
+	end process;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rsto_125 <= rst;
+		end if;
+	end process;
+
+        sys40_gen : BUFIO2
+          generic map (
+            DIVIDE => 5,            -- DIVCLK divider (1-8)
+            DIVIDE_BYPASS => FALSE) -- Bypass the divider circuitry (TRUE/FALSE)
+          port map (
+            I => SysClk,        -- 1-bit input: Clock input (connect to IBUFG)
+            DIVCLK =>  s_clk_logic_xtal,   -- 1-bit output: Divided clock output
+            IOCLK => open,          -- 1-bit output: I/O output clock
+            SERDESSTROBE => open);  -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+        
+                
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..217fa22453b724a07f70ef4bf27f159013828499
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl.vhd
@@ -0,0 +1,158 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    --auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_low_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (lowest 32-bits)
+    triggerPattern_high_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (highest 32-bits)
+    loadPatternHi_i    : in std_logic; --! Pattern (high 32 bits) is loaded when loadPatternHi goes high.
+    loadPatternLo_i    : in  std_logic);  --! Pattern (low 32 bits) is loaded when loadPatternLo goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR_low , s_configEnableSR_low: std_logic_vector( triggerPattern_low_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configDataSR_high , s_configEnableSR_high: std_logic_vector( triggerPattern_high_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit_low, s_configBit_high, s_configEnable_low, s_configEnable_high : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut_low, s_trigOut_high, s_auxTrigOut_low, s_auxTrigOut_high : std_logic := '0';  -- registers for output data. (s_auxTrig high and low should be removed)
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  -- We now need 6 inputs in the LUT and we need to dynamically change it so we merge two 5-inputs together:
+  -- one does the low 32 bits of the address table, the other the high 32 bits.
+  LUT_low : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs (exclude case with no input at all)
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => open ,  -- 4-LUT output
+      O6 => s_trigOut_low, -- 5-LUT output
+      CDI => s_configBit_low, -- Reconfiguration data input
+      CE => s_configEnable_low, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+      );
+   
+   LUT_high : CFGLUT5
+    generic map (
+        INIT => X"FFFFFFFF") --! Default to "OR" of all inputs
+    port map (
+        CDO => open, -- Reconfiguration cascade output
+        O5 => open ,  -- 4-LUT output
+        O6 => s_trigOut_high, -- 5-LUT output
+        CDI => s_configBit_high, -- Reconfiguration data input
+        CE => s_configEnable_high, -- Reconfiguration enable input
+        CLK => configClk_i, -- Clock input
+        I0 => triggers_i(0), -- Logic data input
+        I1 => triggers_i(1), -- Logic data input
+        I2 => triggers_i(2), -- Logic data input
+        I3 => triggers_i(3), -- Logic data input
+        I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+    );   
+
+  p_controlInitLo: process (configClk_i , triggerPattern_low_i , loadPatternLo_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Control configuration
+      if ( loadPatternLo_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR_low <= triggerPattern_low_i;
+        s_configEnableSR_low <= ( others => '1');
+        s_configBit_low <= '0';
+        s_configEnable_low <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit_low    <= s_configDataSR_low( s_configDataSR_low'left ); --! Shift in MSB first.
+        s_configDataSR_low <= s_configDataSR_low( s_configDataSR_low'left-1 downto 0) & '0'; --! Shift up
+                
+        s_configEnable_low <= s_configEnableSR_low ( s_configEnableSR_low'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR_low <= s_configEnableSR_low( s_configEnableSR_low'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInitLo;
+  
+  -- Add a second control for the secondary LUT introduced when we moved to 6 inputs.
+  p_controlInitHi: process (configClk_i , triggerPattern_high_i,  loadPatternHi_i) is
+    begin  -- process p_controlInit
+  
+      if rising_edge(configClk_i) then
+  
+        -- Control configuration
+        if ( loadPatternHi_i = '1' ) then -- Load pattern into shift register
+          s_configDataSR_high <= triggerPattern_high_i;
+          s_configEnableSR_high <= ( others => '1');
+          s_configBit_high <= '0';
+          s_configEnable_high <= '0';
+        else -- If load isn't active then shift data out.
+          s_configBit_high    <= s_configDataSR_high( s_configDataSR_high'left ); --! Shift in MSB first.
+          s_configDataSR_high <= s_configDataSR_high( s_configDataSR_high'left-1 downto 0) & '0'; --! Shift up
+                  
+          s_configEnable_high <= s_configEnableSR_high ( s_configEnableSR_high'left); --! enable will stay high for as long as there is data in config data SR
+          s_configEnableSR_high <= s_configEnableSR_high( s_configEnableSR_high'left-1 downto 0) & '0'; --! Shift up
+        end if;
+  
+    end if;
+    end process p_controlInitHi;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+        if triggers_i(5) = '0' then -- the LUT has 5 inputs. We use a MUX to considere the 6th one (triggers_i(5)).
+            trigger_o <=  s_trigOut_low;
+            --auxTrigger_o <= s_auxTrigOut_low;
+        else
+            trigger_o <=  s_trigOut_high;
+            --auxTrigger_o <= s_auxTrigOut_high;
+        end if;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..32b57b74f04c1898bbbb6668a1f1f6d6e6e1bee5
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/coincidenceLogic_rtl_BKP.vhd
@@ -0,0 +1,108 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with
+    loadPattern_i    : in  std_logic);  --! Pattern is loaded when loadPattern goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit , s_configEnable : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut , s_auxTrigOut : std_logic := '0';  -- registers for output data.
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  CFGLUT5_inst : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => s_trigOut ,  -- 4-LUT output
+      O6 => s_auxTrigOut, -- 5-LUT output
+      CDI => s_configBit, -- Reconfiguration data input
+      CE => s_configEnable, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => '1' --! Tie high to set O5 and O6 to different functions.
+      );
+
+  p_controlInit: process (configClk_i , triggerPattern_i , loadPattern_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Contol configuration
+      if ( loadPattern_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR <= triggerPattern_i;
+        s_configEnableSR <= ( others => '1');
+        s_configBit <= '0';
+        s_configEnable <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit    <= s_configDataSR( s_configDataSR'left ); --! Shift in MSB first.
+        s_configDataSR <= s_configDataSR( s_configDataSR'left-1 downto 0) & '0'; --! Shift up
+        
+        s_configEnable <= s_configEnableSR ( s_configEnableSR'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR <= s_configEnableSR( s_configEnableSR'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInit;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+      trigger_o <=  s_trigOut;
+      auxTrigger_o <= s_auxTrigOut;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/counterDown.vhd b/AIDA_tlu/legacy/TLU_v1c/common/counterDown.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de1509001a37cdc74e132a60d4201581a96d83aa
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/counterDown.vhd
@@ -0,0 +1,50 @@
+--Counter down
+--Outputs: 	Q<='1' while counting
+--				Q<='0' if not counting
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY CounterDown IS
+	GENERIC(
+		MAX_WIDTH: positive := 32
+	);
+	PORT( 
+		Clk		: in  std_logic; 
+		Reset		: in  std_logic; 
+		Load 		: in  std_logic; 
+		InitVal 	: in std_logic_vector(MAX_WIDTH-1 downto 0);
+		Count		: out Std_logic_vector(MAX_WIDTH-1 downto 0);
+		Q 			: out std_logic
+	);
+END ENTITY CounterDown;
+
+architecture rtl of CounterDown is 
+	signal cnt	: std_logic_vector(MAX_WIDTH-1 downto 0);
+	signal Qtmp	: std_logic;
+  
+begin 
+	Counter: process (Clk, Reset)
+	begin 
+		if (Reset='1') then 
+			cnt <= (others =>'0');
+		elsif rising_edge(Clk) then
+			if (Load='1') then
+				cnt <= InitVal;
+			else
+				if Qtmp='0' then
+					cnt <= std_logic_vector(unsigned(cnt) - 1);
+				end if;
+			end if;
+		end if; 
+	end process;
+      
+	Qtmp <= 	'1' when cnt=(cnt'range=>'0') else
+				'0';
+          
+	Count <= cnt;
+	Q <= Qtmp;
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/counterWithReset_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/counterWithReset_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2512f986b5588355209563d702e313eec3fcd86d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/counterWithReset_rtl.vhd
@@ -0,0 +1,84 @@
+--=============================================================================
+--! @file counterWithReset_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: counterWithReset (counterWithReset / rtl)
+--
+--============================================================================
+--! Entity declaration for counterWithReset
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+--! @brief Simple counter with synchronous reset
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date Feb\2012
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! \n\n<b>Last changes:</b>\n
+--! 5/Mar/12  DGC Changed to use numeric_std\n
+--! 26/Feb/14 DGC Added registers to output to aid timing closure.
+--! 
+
+
+
+ENTITY counterWithReset IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
+           g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
+           );
+  PORT
+    (
+      clock_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. syncronous with rising clk
+      enable_i: IN STD_LOGIC;  --! counts when enable=1
+      result_o:	OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
+      
+      );
+END counterWithReset;
+
+ARCHITECTURE rtl OF counterWithReset IS
+  type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ;  -- --! Array of arrays for output register...
+  signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0'));  -- --! Output registers.
+  
+BEGIN
+
+  --! Process to count up from zero when enable_i is high.
+  p_counter: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) THEN
+      IF (reset_i = '1') THEN
+        s_output_registers(0) <= (others => '0');
+      ELSIF (enable_i='1') THEN
+        s_output_registers(0) <= s_output_registers(0) + 1;
+      END IF;
+    END IF;
+  END PROCESS p_counter;
+
+  --! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
+  generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
+
+    --! An individual register
+    p_outputRegister: process (clock_i)
+    begin  -- process p_outputRegister
+      if rising_edge(clock_i) then
+        s_output_registers( v_register) <=
+        s_output_registers( v_register-1);
+      end if;
+    end process p_outputRegister;
+    
+  end generate generate_registers;  -- v_register
+
+  --! Copy the (registered) result to the output 
+  result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
+  
+END rtl;		
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/dualSERDES_1to4_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/dualSERDES_1to4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dd090f4a5f79647ace4788bde06ab9fd167acc0d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/dualSERDES_1to4_rtl.vhd
@@ -0,0 +1,421 @@
+--=============================================================================
+--! @file dualSERDES_1to4_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.dualSERDES_1to4.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other
+--! based on TDC by Alvaro Dosil
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:06:53 11/16/12
+--
+--! @version v0.1
+--
+--! @details
+--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--
+--------------------------------------------------------------------------------
+
+ENTITY dualSERDES_1to4 IS
+   PORT( 
+      reset_i        : IN     std_logic;                      --! Resets  IODELAY
+      --calibrate_i    : IN     std_logic;                      --! Starts IODELAY calibration.
+      --data_i         : IN     std_logic;                      --! from input buffer.
+      data_i_pos     : IN     std_logic;                      --! from positive differential input pin 
+      data_i_neg     : IN     std_logic;                      --! from negative differential input pin 
+      fastClk_i      : IN     std_logic;                      --! 2x fabric clock. e.g. 320MHz
+      fabricClk_i    : IN     std_logic;                      --! clock for output to FPGA. e.g. 160MHz
+      strobe_i       : IN     std_logic;                      --! Strobes once every 4 cycles of fastClk
+      data_o         : OUT    std_logic_vector (7 DOWNTO 0);  --! Deserialized data. Interleaved between prompt and delayed  serdes.
+                                                              --! data_o(0) is the oldest data
+      status_o       : OUT    std_logic_vector(1 downto 0)    --! outputs from IODELAY "busy" 0=prompt,1=delayed
+   );
+
+-- Declarations
+
+
+END ENTITY dualSERDES_1to4 ;
+
+--
+ARCHITECTURE rtl OF dualSERDES_1to4 IS
+
+    constant c_S : positive := 4;                     -- ! SERDES division ratio
+
+    signal s_Data_i_d_p   : std_logic;
+    signal s_Data_i_d_d   : std_logic;
+    signal s_busy_idelay_p  : std_logic;              -- Busy from iodelay.
+    signal s_busy_idelay_d  : std_logic;              -- Busy from iodelay.
+    signal s_busy			  : std_logic;              -- Busy from the two iodelays.
+    signal s_data_o       : std_logic_vector(7 downto 0);  --! Deserialized data
+	signal s_cal			 : std_logic := '0'; 				--! Calibration signal
+	signal s_rst_cal		: std_logic := '0'; 				--! reset after calibration process
+    signal delay_val :std_logic_vector(4 downto 0);
+    signal prompt_val :std_logic_vector(4 downto 0);
+    signal delayed_out: std_logic_vector(4 downto 0);
+    signal prompt_out: std_logic_vector(4 downto 0);
+---------------------------------------------
+    component delayIO
+    generic
+    (-- width of the data for the system
+    SYS_W       : integer := 1;
+    -- width of the data for the device
+    DEV_W       : integer := 1);
+    port
+        (
+        -- From the system into the device
+        data_in_from_pins_p     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_from_pins_n     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_to_device       : out   std_logic_vector(DEV_W-1 downto 0);
+        
+        -- Input, Output delay control signals
+        delay_clk               : in    std_logic;
+        in_delay_reset          : in    std_logic;                    -- Active high synchronous reset for input delay
+        in_delay_data_ce        : in    std_logic_vector(SYS_W -1 downto 0);                    -- Enable signal for delay 
+        in_delay_data_inc       : in    std_logic_vector(SYS_W -1 downto 0);                    -- Delay increment (high), decrement (low) signal
+        delay_locked            : out   std_logic;                    -- Locked signal from IDELAYCTRL
+        ref_clock               : in    std_logic;                    -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
+        
+        -- Clock and reset signals
+        clk_in                  : in    std_logic;                    -- Fast clock from PLL/MMCM 
+        clock_enable            : in    std_logic;
+        io_reset                : in    std_logic);                   -- Reset signal for IO circuit
+    end component;
+
+  
+BEGIN
+ 
+	-- IODELAYs calibration FSM
+	IODELAYCal: entity work.IODELAYCal_FSM
+    port map (
+        clk_i       => fabricClk_i,
+        startcal_i  => reset_i,
+        busy_i		=> s_busy,
+        calibrate_o     => s_cal,
+        reset_o         => s_rst_cal
+    );
+
+
+-----------------------------------------------------
+--    iodelay_prompt : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_p,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        io_reset => s_rst_cal
+--    );
+    prompt_val <= "00000";
+
+    IDELAY2_Prompt : IDELAYE2
+    generic map (
+        IDELAY_TYPE => "VARIABLE",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> prompt_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_p,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> prompt_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+        IDATAIN => not data_i_neg, --- THIS MUST BE INVERTED!!!!
+        --IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '0',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+    
+
+
+----IODELAY2 no longer valid. Replaced using IP delay (SelectIO interface wizard generated)
+--  IODELAY2_Prompt : IODELAY2
+--    generic map (
+--      COUNTER_WRAPAROUND => "STAY_AT_LIMIT" ,  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--      DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+--      DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+--      SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--      IDELAY_TYPE        => "VARIABLE_FROM_ZERO",
+--      IDELAY_VALUE     	=> 0                -- Amount of taps for fixed input delay (0-255)
+--      --SIM_TAPDELAY_VALUE=> 10               -- Per tap delay used for simulation in ps
+--      )
+--    port map (
+--      BUSY     => s_busy_idelay_p,      -- 1-bit output: Busy output after CAL
+--      DATAOUT  => s_Data_i_d_p,     -- 1-bit output: Delayed data output to ISERDES/input register
+--      DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--      DOUT     => open,             -- 1-bit output: Delayed data output
+--      TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--      CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--      CE       => '0',              -- 1-bit input: Enable INC input
+--      CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--      IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--      INC      => '0',              -- 1-bit input: Increment / decrement input
+--      IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--      IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--      ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--      RST      => s_rst_cal,            -- 1-bit input: reset_i to 1/2 of total delay period
+--      T        => '1'               -- 1-bit input: 3-state input signal
+--      );
+    
+    s_busy_idelay_p <= (prompt_val(0) XOR  prompt_out(0)) OR (prompt_val(1) XOR  prompt_out(1)) OR (prompt_val(2) XOR  prompt_out(2)) OR (prompt_val(3) XOR  prompt_out(3)) OR (prompt_val(4) XOR  prompt_out(4));
+	status_o(1) <= s_busy_idelay_p;
+
+--    iodelay_delay : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_d,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        clk_out => open,
+--        io_reset => s_rst_cal
+--    );
+
+    -- This should be configurable via IPBus. For now fixed value. The tap value is 200 MHz (5 ns). We want
+    -- a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 6 taps.
+    delay_val <= "00110";
+    --delay_val <= "00000";
+    
+    IDELAY2_Delayed : IDELAYE2
+    generic map (
+        --IDELAY_TYPE => "VARIABLE",
+        IDELAY_TYPE => "VAR_LOAD",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> delayed_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_d,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> delay_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+--        IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        IDATAIN => data_i_pos,
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '1',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+        
+
+--    IODELAY2_Delayed : IODELAY2
+--    generic map (
+--        COUNTER_WRAPAROUND => "STAY_AT_LIMIT",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--        DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+--        DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+--        SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--        IDELAY_TYPE        => "VARIABLE_FROM_HALF_MAX",
+--        IDELAY_VALUE       => 0,             -- Amount of taps for fixed input delay (0-255)
+--        IDELAY2_VALUE      => 0             	-- Delay value when IDELAY_MODE="PCI" (0-255)
+--    --SIM_TAPDELAY_VALUE => 10              -- Per tap delay used for simulation in ps
+--    )
+--    port map (
+--        BUSY     => s_busy_idelay_d,      -- 1-bit output: Busy output after CAL
+--        DATAOUT  => s_Data_i_d_d,     -- 1-bit output: Delayed data output to ISERDES/input register
+--        DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--        DOUT     => open,             -- 1-bit output: Delayed data output
+--        TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--        CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--        CE       => '0',              -- 1-bit input: Enable INC input
+--        CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--        IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--        INC      => '0',              -- 1-bit input: Increment / decrement input
+--        IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--        IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--        ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--        RST      => s_rst_cal,          -- 1-bit input: reset_i to zero
+--        T        => '1'               -- 1-bit input: 3-state input signal
+--    );
+
+
+    --I must check that the CNTVALUEOUT and CNTVALUEIN are the same. TO DO
+	--status_o(0) <= s_busy_idelay_d;
+	s_busy_idelay_d <= (delay_val(0) XOR  delayed_out(0)) OR (delay_val(1) XOR  delayed_out(1)) OR (delay_val(2) XOR  delayed_out(2)) OR (delay_val(3) XOR  delayed_out(3)) OR (delay_val(4) XOR  delayed_out(4));
+	status_o(0) <= s_busy_idelay_d;
+	s_busy <= s_busy_idelay_p or s_busy_idelay_d;
+
+
+-----------------------------------------------------
+--ISERDES2 replaced by ISERDESE2 in Series 7
+--  ISERDES2_Prompt : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,           -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",     -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(1),         -- Oldest data
+--    Q2     => s_Data_o(3),
+--    Q3     => s_Data_o(5),
+--    Q4     => s_Data_o(7),         -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,                 -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+--    CE0     => '1',                  -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,            -- 1-bit input I/O clock network input
+--    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,          -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_p,         -- 1-bit input Input data
+--    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+--    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+
+    ISERDESE2_Prompt: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+    generic map (
+        DATA_RATE => "DDR",
+        DATA_WIDTH => 4,
+        INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+        IOBDELAY => "BOTH", --same as above
+        SERDES_MODE => "MASTER",
+        NUM_CE => 1
+    )
+    port map (
+        O => open,
+        Q4     => s_Data_o(1), -- Oldest data
+        Q3     => s_Data_o(3),
+        Q2     => s_Data_o(5),
+        Q1     => s_Data_o(7),
+        BITSLIP => '0',
+        CE1 => '1',
+        CE2 => '1',
+        CLKDIVP => '0',
+        CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+        CLKB  => not fastClk_i, --should be a unique phase shifted clock
+        CLKDIV => fabricClk_i,
+        DDLY=> s_Data_i_d_p,
+        D=> '0', -- data_i
+        RST=> reset_i,
+        SHIFTIN1 => '0',
+        SHIFTIN2 => '0',
+        DYNCLKDIVSEL=> '0',
+        DYNCLKSEL=> '0', 
+        --OCLK => strobe_i,
+        OCLK => '0',
+        OCLKB => '0',
+        OFB=> '0'
+    );
+
+--  ISERDES2_Delayed : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,       -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,         -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",   -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"       -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--	-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(0),           -- oldest data
+--    Q2     => s_Data_o(2),
+--    Q3     => s_Data_o(4),
+--    Q4     => s_Data_o(6),           -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,               -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+--    CE0     => '1',                -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,          -- 1-bit input I/O clock network input
+--    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,        -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_d,       -- 1-bit input Input data
+--    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+--    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+   
+   
+   ISERDESE2_Delayed: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+       generic map (
+           DATA_RATE => "DDR",
+           DATA_WIDTH => 4,
+           INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+           IOBDELAY => "BOTH", --same as above
+           SERDES_MODE => "MASTER",
+           NUM_CE => 1
+       )
+       port map (
+           O => open,
+           Q4     => s_Data_o(0),           -- oldest data
+           Q3     => s_Data_o(2),
+           Q2     => s_Data_o(4),
+           Q1     => s_Data_o(6), 
+           BITSLIP => '0',
+           CE1 => '1',
+           CE2 => '1',
+           CLKDIVP => '0',
+           CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+           CLKB  => not fastClk_i, --should be a unique phase shifted clock
+           CLKDIV => fabricClk_i,
+           DDLY=> s_Data_i_d_d,
+           D=> '0', -- data_i
+           RST=> reset_i,
+           SHIFTIN1 => '0',
+           SHIFTIN2 => '0',
+           DYNCLKDIVSEL=> '0',
+           DYNCLKSEL=> '0', 
+           OCLK => strobe_i,
+           OCLKB => '0',
+           OFB=> '0'
+       );
+-----------------------------------------------------
+
+
+
+reg_out : process(fabricClk_i)
+begin
+  if rising_edge(fabricClk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/enclustra_ax3_pm3_infra.vhd b/AIDA_tlu/legacy/TLU_v1c/common/enclustra_ax3_pm3_infra.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8e255beab6a2d0d75119021edb88c3ea549a3cdd
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/enclustra_ax3_pm3_infra.vhd
@@ -0,0 +1,131 @@
+-- enclustra_ax3_pm3_infra
+--
+-- All board-specific stuff goes here
+--
+-- Dave Newbold, June 2013---
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity enclustra_ax3_pm3_infra is
+	port(
+		sysclk: in std_logic; -- ??? board crystal clock
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		rst_125_o: out std_logic;
+		clk_200_o: out std_logic;
+		clk_aux_o: out std_logic; -- 40MHz generated clock
+		rst_aux_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		leds: out std_logic_vector(1 downto 0); -- status LEDs
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end enclustra_ax3_pm3_infra;
+
+architecture rtl of enclustra_ax3_pm3_infra is
+
+	signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	signal led_p: std_logic_vector(0 downto 0);
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_7s_extphy_se
+		port map(
+			sysclk => sysclk,
+			clko_125 => clk125,
+			clko_125_90 => clk125_90,
+			clko_200 => clk200,
+			clko_ipb => clk_ipb_i,
+			locked => locked,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl,
+			onehz => onehz
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	rst_125_o <= rst125;
+	clk_200_o <= clk200;
+	
+	stretch: entity work.led_stretcher
+		generic map(
+			WIDTH => 1
+		)
+		port map(
+			clk => clk125,
+			d(0) => pkt,
+			q => led_p
+		);
+	leds <= (led_p(0), locked and onehz);
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_7s_rgmii
+		port map(
+			clk125 => clk125,
+			clk125_90 => clk125_90,
+			clk200 => clk200,
+			rst => rst125,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			pkt => pkt
+		);
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_gmii.vhd b/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_gmii.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4db967adaed3b9e9240b70ffe1bb8661c5668bc6
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_gmii.vhd
@@ -0,0 +1,183 @@
+-- Contains the instantiation of the Xilinx MAC IP plus the GMII PHY interface
+--
+-- Do not change signal names in here without corresponding alteration to the timing contraints file
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+use work.emac_hostbus_decl.all;
+
+entity eth_7s_gmii is
+	port(
+		clk125: in std_logic;
+		clk200: in std_logic;
+		rst: in std_logic;
+		gmii_gtx_clk: out std_logic;
+		gmii_txd: out std_logic_vector(7 downto 0);
+		gmii_tx_en: out std_logic;
+		gmii_tx_er: out std_logic;
+		gmii_rx_clk: in std_logic;
+		gmii_rxd: in std_logic_vector(7 downto 0);
+		gmii_rx_dv: in std_logic;
+		gmii_rx_er: in std_logic;
+		tx_data: in std_logic_vector(7 downto 0);
+		tx_valid: in std_logic;
+		tx_last: in std_logic;
+		tx_error: in std_logic;
+		tx_ready: out std_logic;
+		rx_data: out std_logic_vector(7 downto 0);
+		rx_valid: out std_logic;
+		rx_last: out std_logic;
+		rx_error: out std_logic;
+		hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
+		hostbus_out: out emac_hostbus_out
+	);
+
+end eth_7s_gmii;
+
+architecture rtl of eth_7s_gmii is
+
+	COMPONENT temac_gbe_v9_0_rgmii
+		PORT (
+			gtx_clk : IN STD_LOGIC;
+			glbl_rstn : IN STD_LOGIC;
+			rx_axi_rstn : IN STD_LOGIC;
+			tx_axi_rstn : IN STD_LOGIC;
+			rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
+			rx_statistics_valid : OUT STD_LOGIC;
+			rx_mac_aclk : OUT STD_LOGIC;
+			rx_reset : OUT STD_LOGIC;
+			rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			rx_axis_mac_tvalid : OUT STD_LOGIC;
+			rx_axis_mac_tlast : OUT STD_LOGIC;
+			rx_axis_mac_tuser : OUT STD_LOGIC;
+			tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			tx_statistics_valid : OUT STD_LOGIC;
+			tx_mac_aclk : OUT STD_LOGIC;
+			tx_reset : OUT STD_LOGIC;
+			tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_axis_mac_tvalid : IN STD_LOGIC;
+			tx_axis_mac_tlast : IN STD_LOGIC;
+			tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+			tx_axis_mac_tready : OUT STD_LOGIC;
+			pause_req : IN STD_LOGIC;
+			pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+			speedis100 : OUT STD_LOGIC;
+			speedis10100 : OUT STD_LOGIC;
+			gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			gmii_tx_en : OUT STD_LOGIC;
+			gmii_tx_er : OUT STD_LOGIC;
+			gmii_tx_clk : OUT STD_LOGIC;
+			gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			gmii_rx_dv : IN STD_LOGIC;
+			gmii_rx_er : IN STD_LOGIC;
+			gmii_rx_clk : IN STD_LOGIC;
+			rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
+			tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT mac_fifo_axi4
+	  PORT (
+		 m_aclk : IN STD_LOGIC;
+		 s_aclk : IN STD_LOGIC;
+		 s_aresetn : IN STD_LOGIC;
+		 s_axis_tvalid : IN STD_LOGIC;
+		 s_axis_tready : OUT STD_LOGIC;
+		 s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 s_axis_tlast : IN STD_LOGIC;
+		 s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		 m_axis_tvalid : OUT STD_LOGIC;
+		 m_axis_tready : IN STD_LOGIC;
+		 m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 m_axis_tlast : OUT STD_LOGIC;
+		 m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+	  );
+	END COMPONENT;
+	
+	signal rx_data_e: std_logic_vector(7 downto 0);
+	signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
+	signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
+
+begin
+
+	idelayctrl0: idelayctrl port map(
+		refclk => clk200,
+		rst => rst
+	);
+
+	rstn <= not rst;
+
+	emac0: temac_gbe_v9_0_rgmii
+		port map(
+			gtx_clk => clk125,
+			glbl_rstn => rstn,
+			rx_axi_rstn => '1',
+			tx_axi_rstn => '1',
+			rx_statistics_vector => open,
+			rx_statistics_valid => open,		
+			rx_mac_aclk => rx_clk_e,
+			rx_reset => rx_rst_e,
+			rx_axis_mac_tdata => rx_data_e,
+			rx_axis_mac_tvalid => rx_valid_e,
+			rx_axis_mac_tlast => rx_last_e,
+			rx_axis_mac_tuser => rx_user_e,
+			tx_ifg_delay => X"00",
+			tx_statistics_vector => open,
+			tx_statistics_valid => open,	
+			tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
+			tx_reset => open,
+			tx_axis_mac_tdata => tx_data,
+			tx_axis_mac_tvalid => tx_valid,
+			tx_axis_mac_tlast => tx_last,
+			tx_axis_mac_tuser(0) => tx_error,
+			tx_axis_mac_tready => tx_ready,
+			pause_req => '0',
+			pause_val => X"0000",
+			speedis100 => open,
+			speedis10100 => open,
+			gmii_txd => gmii_txd,
+			gmii_tx_en => gmii_tx_en,
+			gmii_tx_er => gmii_tx_er,
+			gmii_tx_clk => gmii_gtx_clk,
+			gmii_rxd => gmii_rxd,
+			gmii_rx_dv => gmii_rx_dv,
+			gmii_rx_er => gmii_rx_er,
+			gmii_rx_clk => gmii_rx_clk,
+			rx_configuration_vector => X"0000_0000_0000_0000_0812",
+			tx_configuration_vector => X"0000_0000_0000_0000_0012"
+		);
+	
+	rx_user_ef(0) <= rx_user_e;
+	rx_error <= rx_user_f(0);
+	rx_rst_en <= not rx_rst_e;
+	
+	fifo: mac_fifo_axi4
+		port map(
+			m_aclk => clk125,
+			s_aclk => rx_clk_e,
+			s_aresetn => rx_rst_en,
+			s_axis_tvalid => rx_valid_e,
+			s_axis_tready => open,
+			s_axis_tdata => rx_data_e,
+			s_axis_tlast => rx_last_e,
+			s_axis_tuser => rx_user_ef,
+			m_axis_tvalid => rx_valid,
+			m_axis_tready => '1',
+			m_axis_tdata => rx_data,
+			m_axis_tlast => rx_last,
+			m_axis_tuser => rx_user_f
+		); -- Clock domain crossing FIFO
+
+	hostbus_out.hostrddata <= (others => '0');
+	hostbus_out.hostmiimrdy <= '0';
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_rgmii.vhd b/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_rgmii.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a3b374a288366df9a6ebc96b4371212aae819fe5
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/eth_7s_rgmii.vhd
@@ -0,0 +1,184 @@
+-- Contains the instantiation of the Xilinx MAC & PHY interface for RGMII
+--
+-- Do not change signal names in here without corresponding alteration to the timing contraints file
+--
+-- Dave Newbold, October 2016
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+use work.emac_hostbus_decl.all;
+
+entity eth_7s_rgmii is
+	port(
+		clk125: in std_logic;
+		clk125_90: in std_logic;
+		clk200: in std_logic;
+		rst: in std_logic;
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		tx_data: in std_logic_vector(7 downto 0);
+		tx_valid: in std_logic;
+		tx_last: in std_logic;
+		tx_error: in std_logic;
+		tx_ready: out std_logic;
+		rx_data: out std_logic_vector(7 downto 0);
+		rx_valid: out std_logic;
+		rx_last: out std_logic;
+		rx_error: out std_logic;
+		hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
+		hostbus_out: out emac_hostbus_out;
+		status: out std_logic_vector(3 downto 0)
+	);
+
+end eth_7s_rgmii;
+
+architecture rtl of eth_7s_rgmii is
+
+	COMPONENT temac_gbe_v9_0_rgmii
+		PORT (
+			gtx_clk : IN STD_LOGIC;
+			gtx_clk90 : IN STD_LOGIC;
+			glbl_rstn : IN STD_LOGIC;
+			rx_axi_rstn : IN STD_LOGIC;
+			tx_axi_rstn : IN STD_LOGIC;
+			rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
+			rx_statistics_valid : OUT STD_LOGIC;
+			rx_mac_aclk : OUT STD_LOGIC;
+			rx_reset : OUT STD_LOGIC;
+			rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			rx_axis_mac_tvalid : OUT STD_LOGIC;
+			rx_axis_mac_tlast : OUT STD_LOGIC;
+			rx_axis_mac_tuser : OUT STD_LOGIC;
+			tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			tx_statistics_valid : OUT STD_LOGIC;
+			tx_mac_aclk : OUT STD_LOGIC;
+			tx_reset : OUT STD_LOGIC;
+			tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_axis_mac_tvalid : IN STD_LOGIC;
+			tx_axis_mac_tlast : IN STD_LOGIC;
+			tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+			tx_axis_mac_tready : OUT STD_LOGIC;
+			pause_req : IN STD_LOGIC;
+			pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+			speedis100 : OUT STD_LOGIC;
+			speedis10100 : OUT STD_LOGIC;
+			rgmii_txd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_tx_ctl : OUT STD_LOGIC;
+			rgmii_txc : OUT STD_LOGIC;
+			rgmii_rxd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_rx_ctl : IN STD_LOGIC;
+			rgmii_rxc : IN STD_LOGIC;
+			inband_link_status : OUT STD_LOGIC;
+			inband_clock_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			inband_duplex_status : OUT STD_LOGIC;
+			rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
+			tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT mac_fifo_axi4
+	  PORT (
+		 m_aclk : IN STD_LOGIC;
+		 s_aclk : IN STD_LOGIC;
+		 s_aresetn : IN STD_LOGIC;
+		 s_axis_tvalid : IN STD_LOGIC;
+		 s_axis_tready : OUT STD_LOGIC;
+		 s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 s_axis_tlast : IN STD_LOGIC;
+		 s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		 m_axis_tvalid : OUT STD_LOGIC;
+		 m_axis_tready : IN STD_LOGIC;
+		 m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 m_axis_tlast : OUT STD_LOGIC;
+		 m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+	  );
+	END COMPONENT;
+	
+	signal rx_data_e: std_logic_vector(7 downto 0);
+	signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
+	signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
+	
+begin
+
+	idelayctrl0: idelayctrl port map(
+		refclk => clk200,
+		rst => rst
+	);
+	
+	rstn <= not rst;
+
+	emac0: temac_gbe_v9_0_rgmii
+		port map(
+			gtx_clk => clk125,
+			gtx_clk90 => clk125_90,
+			glbl_rstn => rstn,
+			rx_axi_rstn => '1',
+			tx_axi_rstn => '1',
+			rx_statistics_vector => open,
+			rx_statistics_valid => open,		
+			rx_mac_aclk => rx_clk_e,
+			rx_reset => rx_rst_e,
+			rx_axis_mac_tdata => rx_data_e,
+			rx_axis_mac_tvalid => rx_valid_e,
+			rx_axis_mac_tlast => rx_last_e,
+			rx_axis_mac_tuser => rx_user_e,
+			tx_ifg_delay => X"00",
+			tx_statistics_vector => open,
+			tx_statistics_valid => open,	
+			tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
+			tx_reset => open,
+			tx_axis_mac_tdata => tx_data,
+			tx_axis_mac_tvalid => tx_valid,
+			tx_axis_mac_tlast => tx_last,
+			tx_axis_mac_tuser(0) => tx_error,
+			tx_axis_mac_tready => tx_ready,
+			pause_req => '0',
+			pause_val => X"0000",
+			speedis100 => open,
+			speedis10100 => open,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			inband_link_status => status(0),
+			inband_clock_speed => status(3 downto 2),
+			inband_duplex_status => status(1),
+			rx_configuration_vector => X"0000_0000_0000_0000_0812",
+			tx_configuration_vector => X"0000_0000_0000_0000_0012"
+		);
+	
+	rx_user_ef(0) <= rx_user_e;
+	rx_error <= rx_user_f(0);
+	rx_rst_en <= not rx_rst_e;
+	
+	fifo: mac_fifo_axi4
+		port map(
+			m_aclk => clk125,
+			s_aclk => rx_clk_e,
+			s_aresetn => rx_rst_en,
+			s_axis_tvalid => rx_valid_e,
+			s_axis_tready => open,
+			s_axis_tdata => rx_data_e,
+			s_axis_tlast => rx_last_e,
+			s_axis_tuser => rx_user_ef,
+			m_axis_tvalid => rx_valid,
+			m_axis_tready => '1',
+			m_axis_tdata => rx_data,
+			m_axis_tlast => rx_last,
+			m_axis_tuser => rx_user_f
+		); -- Clock domain crossing FIFO
+
+	hostbus_out.hostrddata <= (others => '0');
+	hostbus_out.hostmiimrdy <= '0';
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/eventBuffer_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/eventBuffer_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b60fe5149c1e1ba1d78e778aff9edfc72d920eae
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/eventBuffer_rtl.vhd
@@ -0,0 +1,167 @@
+--=============================================================================
+--! @file eventBuffer_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+--! @brief Stores input words (64bits) for readout over IPBus. 
+--! Uses a FIFO ( 64bits at input, 32 bits at output )
+--
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:24:50 11/13/12
+--
+--! @version v0.1
+--
+--! @details
+--! \n\nIPBus Address map:
+--! \li 0x0000 - FIFO data
+--! \li 0x0001 - FIFO fill level
+--! \li 0x0010 - FIFO status/control: (Writing Bit-0 resets pointers, Reading bit-1 returns "prog_full" flag)
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--------------------------------------------------------------------------------
+
+ENTITY eventBuffer IS
+    GENERIC( 
+        g_EVENT_DATA_WIDTH    : positive := 64;
+        g_IPBUS_WIDTH         : positive := 32;
+        g_READ_COUNTER_WIDTH  : positive := 14
+    );
+    PORT( 
+        clk_4x_logic_i    : IN     std_logic;
+        data_strobe_i     : IN     std_logic;                                         -- Indicates data to transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic;
+        ipbus_i           : IN     ipb_wbus;
+        ipbus_reset_i     : IN     std_logic;
+        strobe_4x_logic_i : IN     std_logic;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o			: OUT 	std_logic;														--! rst signal to first level fifos
+        buffer_full_o     : OUT    std_logic;                                         --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus;
+        logic_reset_i     : IN     std_logic                                          -- reset buffers when high. Synch withclk_4x_logic
+    );
+
+-- Declarations
+
+END ENTITY eventBuffer ;
+
+--
+ARCHITECTURE rtl OF eventBuffer IS
+    signal s_rd_data_count    : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
+    signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0');  -- read-counter - 2*write_count
+    signal s_write_strobe    : std_logic := '0';
+    signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0';                             -- ! Take high to reset FIFO pointers.
+    signal s_fifo_prog_full : std_logic := '0';                       -- ! Controlled by programmable-full flag of FIFO core
+    signal s_fifo_rd_en : std_logic := '0';                           -- ! Take high to clock data out of FIFO
+    signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);  -- ! Output from FIFO ( fall-through mode)
+    signal s_fifo_valid : std_logic := '1';                           -- ! High when data in FIFO
+    signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
+    signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0');  -- data registered onto IPBus clock
+    signal s_ack : std_logic := '0';      -- -- IPBus ACK signal
+    COMPONENT tlu_event_fifo
+    PORT (
+        rst : IN STD_LOGIC;
+        wr_clk : IN STD_LOGIC;
+        rd_clk : IN STD_LOGIC;
+        din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+        wr_en : IN STD_LOGIC;
+        rd_en : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        full : OUT STD_LOGIC;
+        almost_full : OUT STD_LOGIC;
+        empty : OUT STD_LOGIC;
+        almost_empty : OUT STD_LOGIC;
+        rd_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
+        prog_full : OUT STD_LOGIC
+    );
+    END COMPONENT;
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus IO
+  -----------------------------------------------------------------------------
+
+  --! Generate IPBus ACK 
+    ipbus_ack: process(ipbus_clk_i)
+    begin
+    if rising_edge(ipbus_clk_i) then
+        s_ack <= ipbus_i.ipb_strobe and not s_ack;
+    end if;
+    end process ipbus_ack;
+    ipbus_o.ipb_ack <= s_ack;
+    
+    --! Generate FIFO read enable
+    --! take high for one cycle ( when ipb_strobe goes high but before ACK goes
+    --high to follow it
+    s_fifo_rd_en  <= '1' when
+        ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" and s_ack = '0'
+        else '0';
+    ipbus_o.ipb_err <= '0';
+
+    --! Multiplex output data.
+    with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
+        s_fifo_dout          when "00",
+        s_fifo_fill_level    when "01",
+        s_fifo_status_ipb	 when "10",
+        (others => '1')      when others;
+
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipbus_write
+    if rising_edge(ipbus_clk_i) then
+        s_rst_fifo_ipb <= '0';
+        if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
+            s_rst_fifo_ipb <= '1';
+        end if;
+        -- Register data onto IPBus clock domain to ease timing closure.
+        s_fifo_status_ipb <=  X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+        s_fifo_fill_level <= X"0000" & "00" & s_rd_data_count; 
+    end if;
+    end process ipbus_write;
+  
+    rst_fifo_o <= s_rst_fifo_ipb;
+    s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
+  
+  -----------------------------------------------------------------------------
+  -- FIFO and fill-level calculation
+  -----------------------------------------------------------------------------
+  
+  -- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
+  --event_fifo : entity work.tlu_event_fifo
+    event_fifo : tlu_event_fifo
+    PORT MAP (
+        rst => s_rst_fifo,
+        wr_clk => clk_4x_logic_i,
+        rd_clk => ipbus_clk_i,
+        din => event_data_i,
+        wr_en => data_strobe_i,
+        rd_en => s_fifo_rd_en,
+        dout => s_fifo_dout,
+        full => s_fifo_full,
+        almost_full => s_fifo_almost_full,
+        empty => s_fifo_empty,
+        almost_empty => s_fifo_almost_empty,
+        rd_data_count => s_rd_data_count,
+        prog_full => s_fifo_prog_full
+    );
+    buffer_full_o <= s_fifo_prog_full;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/eventFormatter_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/eventFormatter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c33279ab6feae6a81fe6bd07ef068ec4c9dfc23e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/eventFormatter_rtl.vhd
@@ -0,0 +1,385 @@
+--=============================================================================
+--! @file eventFormatter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.fmcTLU.all;
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Takes the data delivered on each trigger and turns it into 64-bit
+--!        words to push into event buffer
+--! 
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:10:35 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBus address:
+--! \n (Decodes 3 bits)
+--! \li 000 - read/write enable data recording.
+--! \li 001 - write = reset timestamp,
+--! \li 010 - read = current timestamp (low  32-bits)
+--! \li 011 - read = current timestamp (high 16-bits)
+--!
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
+--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
+--!               doesn't like having an if that can take an array out of bounds.
+--! 26/Sept/14 DGC Hacked out shutter etc. Can't figure out bug.
+--!-----------------------------------------------------------------------------
+--! @todo Add more input data: \n
+--! a) shutter signals. One per DUT. ?? \n
+--! b) input levels ( for recording edge data ). Record rising and falling edges\n
+--! c) veto levels. One per DUT. Record rising and falling edges.\n
+--! \n
+--! Add backpressure output if short FIFOs fill up? But many inputs won't
+--! respond - e.g. scintillator inputs. This data will be lost....
+--! some ports are redundant - e.g. trigger counter, others confusingly
+--! labelled. Sort this out..
+--------------------------------------------------------------------------------
+
+
+ENTITY eventFormatter IS
+   GENERIC( 
+      g_EVENT_DATA_WIDTH   : positive := 64;
+      g_IPBUS_WIDTH        : positive := 32;
+      g_COUNTER_TRIG_WIDTH : positive := 32;
+      g_COUNTER_WIDTH      : positive := 12;
+      g_EVTTYPE_WIDTH      : positive := 4; --! Width of the event type word
+      --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+      g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+      g_NUM_TRIG_INPUTS    : positive := 6      --! Number of trigger inputs
+   );
+   PORT( 
+      clk_4x_logic_i         : IN     std_logic;                                           --! Rising edge active
+      ipbus_clk_i            : IN     std_logic;
+      logic_strobe_i         : IN     std_logic;                                           --! Pulses high once every 4 cycles of clk_4x_logic
+      logic_reset_i          : IN     std_logic;                                           --! goes high to reset counters. Synchronous with clk_4x_logic
+      rst_fifo_i             : IN     std_logic;                                           --! Goes high to reset FIFOs
+      buffer_full_i          : IN     std_logic;                                           --! Goes high when output fifo full
+      trigger_i              : IN     std_logic;                                           --! goes high to load trigger data. One cycle of clk_4x_logic
+      trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times ( w.r.t. logic_strobe)
+      trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);     --! high for each input that "fired"
+      trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);  --! Trigger count
+      shutter_i              : IN     std_logic;
+      shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      spill_i                : IN     std_logic;
+      spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when rising edge
+      edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when falling edge
+      edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      ipbus_i                : IN     ipb_wbus;
+      ipbus_o                : OUT    ipb_rbus;
+      data_strobe_o          : OUT    std_logic;                                           --! goes high when data ready to load into event buffer
+      event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+      reset_timestamp_i      : IN     std_logic;                                           --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+      reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+   );
+
+-- Declarations
+
+END eventFormatter ;
+
+--
+ARCHITECTURE rtl OF eventFormatter IS
+
+  
+  constant c_NUM_INPUT_TYPES     : positive := 3+g_NUM_EDGE_INPUTS;               -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
+  
+--  type t_fifo_io is array(natural range <>) of std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0);
+-- type t_evttype is array(natural range <>) of std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0);
+--  type t_var is array(natural range <>) of std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
+  -- Input types:
+  -- 0 - Trigger
+  -- 1 - Shutter
+  -- 2 - Edge signal
+  -- 3 - Spill
+  
+  --! delayed strobes
+  signal s_event_strobe , s_event_strobe_d1 ,s_event_strobe_d2 ,s_event_strobe_d3 , s_event_strobe_d3_opt : std_logic := '0';
+  signal shutter_i_d1, shutter_i_d2, edge_i_d1, edge_i_d2, spill_i_d1, spill_i_d2 : std_logic := '0';
+  
+--  signal s_evttype : t_evttype(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>(others=>'0'));   -- Event type
+  signal s_evttype : std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0) := ( others => '0');
+  -- 0000 trigger internal
+  -- 0001 trigger external
+  -- 0010 shutter falling
+  -- 0011 shutter rising
+  -- 0100 edge falling
+  -- 0101 edge rising
+  -- 0111 spill on
+  -- 0110 spill off
+  
+  signal s_var        : std_logic_vector(g_COUNTER_WIDTH-1 downto 0) := (others => '0');
+    
+  signal s_data_o        : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);         -- Multiplexed data from FIFOs
+  
+  constant c_COARSE_TIMESTAMP_WIDTH : positive := 48;  -- ! Number of bits in 40MHz timestamp
+  signal s_coarse_timestamp : std_logic_vector(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0');  -- 40MHz timestamp.
+  signal s_coarse_timestamp_ipbus : ipb_reg_v(1 downto 0) := ( others => (others => '0')); --! 40MHz timestamp on IPB clock domain.
+
+--  signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- increment after each post-veto trigger.
+
+  signal s_word0 , s_word1, s_word2 			: std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_p1  : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal trigger_times_d1							: t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0')); 
+
+  signal s_reset_timestamp_4x, s_reset_timestamp_4x_ipbus , s_reset_timestamp_4x_external , s_reset_timestamp_4x_external_p1 , s_reset_timestamp_4x_external_p2 : std_logic := '0'; --! Single pulse on 4x domain
+  signal s_reset_timestamp_ipbus : std_logic := '0'; --! Single pulse on IPBus clock domain
+  
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
+  signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
+  signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
+  signal s_enable_spill   : std_logic := '1'; -- Enable spill record
+  signal s_enable_edges   : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
+
+  signal s_rst_fifo_d1 , s_rst_fifo_d2 , s_rst_fifo_clk4x  : std_logic := '0';
+  signal s_buffer_full_d1 , s_buffer_full_d2 , s_buffer_full_clk4x  : std_logic := '0';
+  signal s_trigger : std_logic := '0';  -- pulses on risng edge of triger in
+
+  signal s_captured_trigger_times :  t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times,captured when trigger
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus write
+  -----------------------------------------------------------------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_reset_timestamp_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+         case ipbus_i.ipb_addr(2 downto 0) is
+           when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
+           when "001" => s_reset_timestamp_ipbus <= '1';
+           when others => null;
+         end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+  
+
+  -----------------------------------------------------------------------------
+  -- IPBUS read
+  -----------------------------------------------------------------------------
+  with ipbus_i.ipb_addr(2 downto 0) select
+    ipbus_o.ipb_rdata <=
+      s_enable_record_ipb                     when "000",
+      s_coarse_timestamp_ipbus(0)              when "010",  
+      s_coarse_timestamp_ipbus(1)             when "011",  
+      (others => '1')                         when others;
+
+  cmp_timestampDomainCross : entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => 2 )
+    port map (
+      clk_input_i  => clk_4x_logic_i,
+      data_i       => ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) ) ,
+      data_o       => s_coarse_timestamp_ipbus, 
+      clk_output_i => ipbus_clk_i
+      );
+
+  -- Move reset timestamp pulse onto clk_4x_logic
+  cmp_resetTimestampDomainCross: entity work.pulseClockDomainCrossing
+    port map (
+      clk_input_i  => ipbus_clk_i,
+      pulse_i      => s_reset_timestamp_ipbus,
+      clk_output_i => clk_4x_logic_i, 
+      pulse_o      => s_reset_timestamp_4x_ipbus
+    );
+
+  -- Combine reset timestamp from IPBus and external source
+  -- purpose: combines resets from IPBus and external source onto clk_4x_logic_i
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: s_reset_timestamp_4x
+  p_combine_reset_timestamps: process (clk_4x_logic_i) is
+  begin  -- process p_combine_reset_timestamps
+    if rising_edge(clk_4x_logic_i) then
+      s_reset_timestamp_4x_external_p2 <= reset_timestamp_i;
+      s_reset_timestamp_4x_external_p1 <= s_reset_timestamp_4x_external_p2 ;
+      s_reset_timestamp_4x_external    <= s_reset_timestamp_4x_external_p1 ;
+      s_reset_timestamp_4x <= s_reset_timestamp_4x_external or s_reset_timestamp_4x_ipbus;
+    end if;
+  end process p_combine_reset_timestamps;
+  
+  reset_timestamp_o <= s_reset_timestamp_4x;
+  
+  -- Change control signals from IPBus clock domain on to clk_4x_logic
+  -- CHANGE ME - use synchronize registers instead.
+  p_signals_clk_domain: process (clk_4x_logic_i )
+  begin  -- process p_internal_triggers
+    if rising_edge(clk_4x_logic_i) then
+      s_enable_record  <= s_enable_record_ipb;
+		
+      s_enable_trigger <= s_enable_record(0);
+      s_enable_shutter <= s_enable_record(1);
+      s_enable_spill <= s_enable_record(2);
+      s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
+
+      -- move  "reset fifo" and "buffer full"  signals onto clock4x domain
+      s_rst_fifo_d1 <= rst_fifo_i;
+      s_rst_fifo_d2 <= s_rst_fifo_d1;
+      s_rst_fifo_clk4x <= s_rst_fifo_d2 ;
+      s_buffer_full_d1 <= buffer_full_i;
+      s_buffer_full_d2 <= s_buffer_full_d1;
+      s_buffer_full_clk4x <= s_buffer_full_d2;  
+      
+    end if;
+  end process p_signals_clk_domain;
+
+  cmp_triggerEdgeDetect: entity work.single_pulse
+    port map (
+      level => trigger_i,
+      clk => clk_4x_logic_i,
+      pulse => s_trigger
+      );
+  
+  -- purpose: generate delayed strobes and write enable flags to the FIFOs
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , s_FIFO_rd
+  -- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
+  p_ff_rst: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then      
+      if s_rst_fifo_clk4x = '1' then
+        s_event_strobe_d1 <= '0';
+        s_event_strobe_d2 <= '0';
+        s_event_strobe_d3 <= '0';
+		
+      else
+        -- set s_event_strobe high if trigger_i is high and pipeline is empty
+        -- ( i.e. all event_strobe are zero)
+
+        s_event_strobe_d1 <= s_trigger and s_enable_trigger and not buffer_full_i and
+                             (not s_event_strobe_d1 ) and (not s_event_strobe_d2 ) and (not s_event_strobe_d3 );
+        s_event_strobe_d2 <= s_event_strobe_d1;
+        s_event_strobe_d3 <= s_event_strobe_d2;
+		
+      end if;
+    end if;
+  end process p_ff_rst;
+  
+  p_ff: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then
+
+		trigger_times_d1 <= trigger_times_i;
+
+        s_word0 <= s_word0_p1;
+		s_word0_d1 <= s_word0;
+		s_word1_d1 <= s_word1;
+		s_word1_d2 <= s_word1_d1;
+		s_word2_d1 <= s_word2;
+		s_word2_d2 <= s_word2_d1;
+		s_word2_d3 <= s_word2_d2;
+		
+	end if;
+  end process;
+	
+  -- If there are more than 4 trigger inputs we need to fill a second word.
+  -- .. do this by having an optional strobe.
+  -- If 4 or fewer trigger inputs, just leave s_event_strobe_d3_opt at zero..
+  gen_strobe_d3: if (g_NUM_TRIG_INPUTS > 4) generate
+    s_event_strobe_d3_opt <= s_event_strobe_d3;
+  end generate;
+
+-------------------------------------------------------------------------------
+-- Trigger event formater
+-------------------------------------------------------------------------------
+  s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 else "0001";
+
+  --s_var <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));
+  s_var <= std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS)) & trigger_inputs_fired_i; -- Pad with zeroes on the left.
+
+  s_word0_p1 <= s_evttype & s_var & s_coarse_timestamp;
+  
+  s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
+             "000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
+             trigger_cnt_i;
+				 
+	
+  -- Different number of trigger inputs require packing into s_word2 in
+  -- different ways.
+  -- Do this in a generate since g_NUM_TRIG_INPUTS is static and
+  -- Questasim doesn't like refering to indices outside declared range.
+    gen_word2_init: if (g_NUM_TRIG_INPUTS <= 4) generate
+       s_word2 <= (others=>'0');
+    end generate;
+  --s_word2 <= (others=>'0'); -- Set all bits to zero
+  -- then override with the following assignments....
+    gen_word2: for v_trigInput in 4 to g_NUM_TRIG_INPUTS-1 generate
+        s_word2( (((11-v_trigInput)*8)+c_NUM_TIME_BITS-1) downto ((11-v_trigInput)*8) ) <= trigger_times_i(v_trigInput);
+    end generate;
+  
+      
+  --! Could also output data on trigger_i , but let's use the delayed signals. \n
+  --! The counters are one cycle delayed from the signal generation
+  p_fifo_i : process (clk_4x_logic_i)
+  begin  
+    if rising_edge(clk_4x_logic_i) then
+      data_strobe_o <= s_event_strobe_d1 or s_event_strobe_d2 or s_event_strobe_d3_opt;
+      
+      if s_event_strobe_d1 = '1' then
+        event_data_o <= s_word0_d1;
+      elsif s_event_strobe_d2 = '1' then
+        event_data_o <= s_word1_d2;
+      elsif s_event_strobe_d3_opt = '1' then
+        event_data_o <= s_word2_d3;
+      else
+        event_data_o <= (others=>'0');
+      end if;
+    end if;
+  end process;
+		
+
+  cmp_timeStampCounter: entity work.counterWithReset
+    generic map (
+      g_COUNTER_WIDTH => s_coarse_timestamp'length)
+    port map (
+      clock_i  => clk_4x_logic_i,
+      reset_i  => s_reset_timestamp_4x or logic_reset_i,
+      enable_i => logic_strobe_i,
+      result_o => s_coarse_timestamp);
+    
+ 
+  -- Generate data in format decided at DESY. Put out two strobes for the
+  -- two 64 bit words.
+  -- get trigger inputs to also generate a global time-stamp ??
+  -- add trigger_inputs_active_i array (to indicate which triggers fired)
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg.vhd b/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb6b10104903070a5365064dee8d9d822d64cf42
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg.vhd
@@ -0,0 +1,27 @@
+--=============================================================================
+--! @file fmcTLU_pkg.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:44:31 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE fmcTLU IS
+  
+  constant c_NUM_TIME_BITS : natural := 5;
+  constant c_NUM_TRIG_INPUTS : natural := 4;
+  constant c_EVENT_DATA_WIDTH : natural := 32;
+  constant c_DATA_WIDTH : natural := 32;
+  
+  subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
+  --type    t_triggerTimeArray is array(natural range <>) of t_triggerTime;
+  type    t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+  type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
+  
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg_body.vhd b/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg_body.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9437776d393daa1b6e790f3d5470fb09344259bc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/fmcTLU_pkg_body.vhd
@@ -0,0 +1,13 @@
+--=============================================================================
+--! @file fmcTLU_pkg_body.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:45:08 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+PACKAGE BODY fmcTLU IS
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/handshakes_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/handshakes_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ab893a2a99708784f934579adc8439a2593fe067
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/handshakes_rtl.vhd
@@ -0,0 +1,248 @@
+--=============================================================================
+--! @file handshakes_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
+--
+--! @brief Handshakes between TLU and DUTs. \n
+--
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 12:08:30 25/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY handshakes IS
+   GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i    			: IN     std_logic;
+		Trigger_i			: IN 		std_logic;
+      ipbus_clk_i       : IN     std_logic;
+      ipbus_i           : IN     ipb_wbus;
+      ipbus_reset_i     : IN     std_logic;
+      ipbus_o           : OUT    ipb_rbus;
+      logic_reset_i     : IN     std_logic;    
+		Busy_i				: IN		std_logic;
+		AIDAhandshake_o	: OUT		std_logic;		-- running an AIDA handshake or the old EUDET handshake
+		Trigger_o			: OUT 	std_logic;
+		rst_or_clk_o		: OUT 	std_logic		-- CONT in schematics
+   );
+
+-- Declarations
+
+END ENTITY handshakes ;
+
+--
+ARCHITECTURE rtl OF handshakes IS
+
+	signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+	signal s_Shutter, s_T0sync : std_logic;
+	signal s_Trigger, s_TrigAux : std_logic := '0';
+	signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
+	
+	signal TPx3_T0syncLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004";   	--! T0-sync length
+	signal TPx3_Start_T0sync 	: std_logic;   																--! Flag to start the T0-sync signal
+
+	signal s_Veto 			: std_logic := '0';
+	signal s_WU				: std_logic := '0';
+	signal s_NMaxPulses 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_SuDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_PulseLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_IpDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_RearmTime 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
+	signal s_PulseDelay 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_MaxPulses	: std_logic;
+	signal s_pulse			: std_logic;
+	
+	constant c_N_CTRL : positive := 13;
+	constant c_N_STAT : positive := 13;
+	signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+	signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_i);
+		
+	-----------------------------------------------------------------------------
+	-- Logic not ready to use
+	-----------------------------------------------------------------------------
+		
+	--Map the control registers
+	s_handshakeEnabled <= s_sync_control_from_ipbus(0);
+	
+	s_status_to_ipbus(0) <= s_handshakeEnabled;
+
+	
+	-- No handshake registers
+	s_NMaxPulses <= s_sync_control_from_ipbus(5);
+	s_SuDTime <= s_sync_control_from_ipbus(6);
+	s_PulseLen <= s_sync_control_from_ipbus(7);
+	s_IpDTime <= s_sync_control_from_ipbus(8);
+	s_RearmTime <= s_sync_control_from_ipbus(9);
+	s_PulseDelay <= s_sync_control_from_ipbus(10);
+	s_Veto <= s_sync_control_from_ipbus(11)(0);
+	s_WU <= s_sync_control_from_ipbus(11)(1);
+	
+	s_status_to_ipbus(5) <= s_NMaxPulses;
+	s_status_to_ipbus(6) <= s_SuDTime;
+	s_status_to_ipbus(7) <= s_PulseLen;
+	s_status_to_ipbus(8) <= s_IpDTime;
+	s_status_to_ipbus(9) <= s_RearmTime;
+	s_status_to_ipbus(10) <= s_PulseDelay;
+	s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
+	s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
+	
+	-- TPx3 registers
+	TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
+	TPx3_T0syncLen 	<= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
+								s_sync_control_from_ipbus(2);
+  
+	s_status_to_ipbus(1) <= x"0000000" & "000" & TPx3_Start_T0sync;
+	s_status_to_ipbus(2) <= TPx3_T0syncLen;
+  
+  
+	-----------------------------------------------------------------------------
+	-- Synchronization - Rewrite!!!
+	-----------------------------------------------------------------------------
+	p_trigger : process(Trigger_i, s_Trigger)
+	begin
+		if Trigger_i = '1' then
+			s_TrigAux <= '1';
+		elsif s_Trigger = '1' then
+			s_TrigAux <= '0';
+		end if;
+	end process p_trigger;
+	
+	p_sync: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Trigger <= s_TrigAux;
+			
+			s_Busy_d1 <= Busy_i;
+			s_Busy_d2 <= s_Busy_d1;
+			s_Busy_d3 <= s_Busy_d2;
+			s_Busy <= s_Busy_d2;
+		end if;
+  end process p_sync;
+	
+	-----------------------------------------------------------------------------
+	-- I/O
+	-----------------------------------------------------------------------------
+	Trigger_o <= 	s_Trigger when s_handshakeEnabled(1 downto 0) = "00"  and s_Busy = '0' else
+						s_pulse when s_handshakeEnabled(1 downto 0) = "01" else							-- No handshake
+						s_Shutter when s_handshakeEnabled(1 downto 0) = "10" else						-- TPx3 handshake
+						'0';
+	rst_or_clk_o <= 	s_T0sync when s_handshakeEnabled(1 downto 0) = "10" else
+							'0';
+	
+	AIDAhandshake_o <= not s_handshakeEnabled(3); 	-- s_handshakeEnabled = x"00001000" => EUDET handshake.
+																	-- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
+	
+	-- No Handshake (GPP)
+	No_handshake:  entity work.GPP
+	GENERIC MAP( 
+		g_IPBUS_WIDTH => g_IPBUS_WIDTH)
+	PORT MAP( 
+		clk_i       		=> clk_i,
+		Enable_i          => not (s_Busy or s_Veto),
+      Reset_i           => logic_reset_i,
+      RstPulsCnt_i     	=> '0',
+      Trigger_i         => s_Trigger,
+      NMaxPulses_i      => s_NMaxPulses,
+      SuDTime_i         => s_SuDTime,
+      PulsLen_i     		=> s_PulseLen,
+      IpDTime_i         => s_IpDTime,
+		RearmTime_i       => s_RearmTime,
+      Force_PullDown_i  => s_Busy or s_Veto,
+      WU_i              => s_WU,
+      PulseDelay_i      => s_PulseDelay,
+		event_number_o    => open,
+      MaxPulses_o       => s_MaxPulses,
+      Pulse_o           => s_pulse,
+      Pulse_d_o         => open);
+		
+	-- TPx3 Handshake
+	TPx3_logic: entity work.TPx3Logic
+   PORT MAP( 
+      clk_i					=> clk_i,
+		Start_T0sync_i		=> TPx3_Start_T0sync,
+		T0syncLen_i			=> TPx3_T0syncLen,
+      logic_reset_i     => logic_reset_i,
+      Busy_i				=> s_Busy,
+		Veto_i				=> s_Veto,
+		Shutter_o			=> s_Shutter,
+		T0sync_o 			=>	s_T0sync
+   );
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/i2c_master_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/i2c_master_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d0bb973aa56b1e35107d8d22fd37574f7e7eed6
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/i2c_master_rtl.vhd
@@ -0,0 +1,97 @@
+--=============================================================================
+--! @file i2c_master_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.i2c_master.rtl
+--
+--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
+--! are bundled together in a record\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 17:22:12 11/30/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY i2c_master IS
+   PORT( 
+      i2c_scl_i     : IN     std_logic;
+      i2c_sda_i     : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;    -- Signals from IPBus core to slave
+      ipbus_reset_i : IN     std_logic;
+      i2c_scl_enb_o : OUT    std_logic;
+      i2c_sda_enb_o : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus     -- signals from slave to IPBus core
+   );
+
+-- Declarations
+
+END ENTITY i2c_master ;
+
+--
+ARCHITECTURE rtl OF i2c_master IS
+  
+  --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
+  
+BEGIN
+  
+  --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
+  --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
+
+  i2c_interface: entity work.i2c_master_top port map(
+                wb_clk_i => ipbus_clk_i,
+                wb_rst_i => ipbus_reset_i,
+                arst_i => '1',
+                wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
+                wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
+                wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
+                wb_we_i => ipbus_i.ipb_write,
+                wb_stb_i => ipbus_i.ipb_strobe,
+                wb_cyc_i => '1',
+                wb_ack_o => ipbus_o.ipb_ack,
+                wb_inta_o => open,
+                scl_pad_i => i2c_scl_i,
+                scl_pad_o => open,
+                scl_padoen_o => i2c_scl_enb_o,
+                sda_pad_i => i2c_sda_i,
+                sda_pad_o => open,
+                sda_padoen_o => i2c_sda_enb_o
+        );
+        
+  
+  ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
+  ipbus_o.ipb_err <= '0'; -- never return an error.
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_addr_decode.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_addr_decode.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dc630e87a5945dbbdfb05c850418867e503ddf39
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_addr_decode.vhd
@@ -0,0 +1,50 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+    variable sel : integer;
+  begin
+		if    std_match(addr, "-----------------------0001-----") then
+			sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
+		elsif std_match(addr, "-----------------------0010-----") then
+			sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
+		elsif std_match(addr, "-----------------------0011-----") then
+			sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
+		elsif std_match(addr, "-----------------------0100-----") then
+			sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
+		elsif std_match(addr, "-----------------------0101-----") then
+			sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
+		elsif std_match(addr, "-----------------------0110-----") then
+			sel := 5; -- i2c_master / base 000000c0 / mask 00000007
+		elsif std_match(addr, "-----------------------1010-----") then
+                        sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
+                elsif std_match(addr, "-----------------------1011-----") then
+                        sel := 7; -- TPix3_iface   / base 00000160 / mask 0000001f
+		elsif std_match(addr, "-----------------------0000-----") then
+			sel := 8; -- version / base 00000000 / mask 00000000
+		else
+			sel := 99;
+		end if;
+		return sel;
+	end ipbus_addr_sel;
+ 
+end ipbus_addr_decode;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_ipbus_example.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a315ed0358c7662662ddd26e751043300ed6937c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_ipbus_example.vhd
@@ -0,0 +1,69 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+-- 
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_ipbus_example is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_ipbus_example;
+
+package body ipbus_decode_ipbus_example is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "-----------------000----------0-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "-----------------000----------1-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    --elsif std_match(addr, "-----------------001------------") then
+      --sel := ipbus_sel_t(to_unsigned(N_SLV_RAM, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    --elsif std_match(addr, "-----------------010----------0-") then
+     -- sel := ipbus_sel_t(to_unsigned(N_SLV_PRAM, IPBUS_SEL_WIDTH)); -- pram / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "-----------------011------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "-----------------100------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- i2c / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "-----------------101------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- i2c / base 0x00005000 / mask 0x00003002
+-- END automatically generated VHDL
+
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_ipbus_example;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_tlu.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_tlu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..114da4012cbed8bf184566ff856f82576a074ff7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_decode_tlu.vhd
@@ -0,0 +1,73 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- 
+-- Paolo Baesso, February 2017
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_tlu is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of IPBus slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_tlu;
+
+package body ipbus_decode_tlu is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "----------------0000----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "----------------0000----------1-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    elsif std_match(addr, "----------------0001------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    elsif std_match(addr, "----------------0010----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_SHUT, IPBUS_SEL_WIDTH)); -- shutter / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "----------------0011------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "----------------0100------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVBUF, IPBUS_SEL_WIDTH)); -- event buffer / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "----------------0101------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVFMT, IPBUS_SEL_WIDTH)); -- event formatter / base 0x00005000 / mask 0x00003002
+    elsif std_match(addr, "----------------0110------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- trigger inputs / base 0x00006000 / mask 0x00003002
+    elsif std_match(addr, "----------------0111------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGLGC, IPBUS_SEL_WIDTH)); -- trigger logic / base 0x00007000 / mask 0x00003002
+    elsif std_match(addr, "----------------1000------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_LGCCLK, IPBUS_SEL_WIDTH)); -- logic clocks / base 0x00008000 / mask 0x00003002
+-- END automatically generated VHDL
+ 
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_tlu;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_example.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cc5f12c11b018fd6cbf7c022792e71ff24b06da
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_example.vhd
@@ -0,0 +1,174 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_example is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_example;
+
+architecture rtl of ipbus_example is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+       COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+
+	slave4: entity work.ipbus_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_RAM),
+			ipbus_out => ipbr(N_SLV_RAM)
+		);
+	
+-- Slave 3: peephole RAM
+
+	slave5: entity work.ipbus_peephole_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_PRAM),
+			ipbus_out => ipbr(N_SLV_PRAM)
+		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_fabric_sel.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_fabric_sel.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..86d2fa7ad9b120d636c28ad9fe3de5a35eaa0d51
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_fabric_sel.vhd
@@ -0,0 +1,61 @@
+-- The ipbus bus fabric, address select logic, data multiplexers
+--
+-- This version selects the addressed slave depending on the state
+-- of incoming control lines
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+
+entity ipbus_fabric_sel is
+  generic(
+    NSLV: positive;
+    STROBE_GAP: boolean := false;
+    SEL_WIDTH: positive
+   );
+  port(
+  	sel: in std_logic_vector(SEL_WIDTH - 1 downto 0);
+    ipb_in: in ipb_wbus;
+    ipb_out: out ipb_rbus;
+    ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0);
+    ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL)
+   );
+
+end ipbus_fabric_sel;
+
+architecture rtl of ipbus_fabric_sel is
+
+	signal sel_i: integer range 0 to NSLV := 0;
+	signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
+	signal qstrobe: std_logic;
+
+begin
+
+	sel_i <= to_integer(unsigned(sel));
+
+	ored_ack(NSLV) <= '0';
+	ored_err(NSLV) <= '0';
+	
+	qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
+	 ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
+
+	busgen: for i in NSLV-1 downto 0 generate
+	begin
+
+		ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
+		ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
+		ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0';
+		ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
+		ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
+		ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;		
+
+	end generate;
+
+  ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0');
+  ipb_out.ipb_ack <= ored_ack(0);
+  ipb_out.ipb_err <= ored_err(0);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_slaves.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_slaves.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0ee08ffa82d15f637cdba389211c81b5a7c47c7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_slaves.vhd
@@ -0,0 +1,170 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_slaves is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_slaves;
+
+architecture rtl of ipbus_slaves is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+    COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+--	slave4: entity work.ipbus_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_RAM),
+--			ipbus_out => ipbr(N_SLV_RAM)
+--		);
+	
+-- Slave 3: peephole RAM
+--	slave5: entity work.ipbus_peephole_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_PRAM),
+--			ipbus_out => ipbr(N_SLV_PRAM)
+--		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/ipbus_ver.vhd b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_ver.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..068f126f8c11346b8a47aeed7e018fb70274f6a1
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/ipbus_ver.vhd
@@ -0,0 +1,46 @@
+--=============================================================================
+--! @file  ipbus_ver.vhd
+--=============================================================================
+
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+--! @brief IPBus fixed register returning Firmware version number
+entity ipbus_ver is
+	port(
+		ipbus_in: in ipb_wbus;
+		ipbus_out: out ipb_rbus
+	);
+	
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+  ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+  ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/led_stretcher.vhd b/AIDA_tlu/legacy/TLU_v1c/common/led_stretcher.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c8af6c6890d6b0e50669a1527c6f09ad18ae46b4
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/led_stretcher.vhd
@@ -0,0 +1,74 @@
+-- stretcher
+--
+-- Stretches a single clock pulse so it's visible on an LED
+--
+-- Dave Newbold, January 2013
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity led_stretcher is
+	generic(
+		WIDTH: positive := 1
+	);
+	port(
+		clk: in std_logic; -- Assumed to be 125MHz ipbus clock
+		d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected)
+		q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse
+	);
+
+end led_stretcher;
+
+architecture rtl of led_stretcher is
+
+	signal d17, d17_d: std_logic;
+	
+begin
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => clk,
+			d17 => d17
+		);
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			d17_d <= d17;
+		end if;
+	end process;
+	
+	lgen: for i in WIDTH - 1 downto 0 generate
+	
+		signal s, sd, e, e_d, sl: std_logic;
+		signal scnt: unsigned(6 downto 0);
+	
+	begin
+	
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				s <= d(i); -- Possible clock domain crossing from slower clock (sync not important)
+				sd <= s;
+				e <= (e or (s and not sd)) and not e_d;
+				if d17 = '1' and d17_d = '0' then
+					e_d <= e;
+					if e = '1' then
+						scnt <= "0000001";
+					elsif sl = '0' then
+						scnt <= scnt + 1;
+					end if;					
+				end if;
+			end if;
+		end process;
+
+		sl <= '1' when scnt = "0000000" else '0';
+		
+		q(i) <= not sl;
+		
+	end generate;
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/logic_clocks_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/logic_clocks_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..631007a5684f7176cbd027035ecfa6235abfcc21
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/logic_clocks_rtl.vhd
@@ -0,0 +1,344 @@
+--=============================================================================
+--! @file logic_clocks_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
+-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
+-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________40.000____________0.010
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock.
+--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock.
+--! Can also output clock to external clock pins.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 14:20:26 11/14/12
+--
+--! @version v0.1
+--
+--! @details
+--! \br <b> IPBus Address map:</b>
+--! \br (decode 2 bits)
+--! \li 0x00000000 - control/status register:
+--! \li             bit-0 - PLL locked ( 1 = locked )
+--! \li              bit-1 - buff-PLL locked ( 1 = locked )
+--! \li             bit-2 - use xtal for logic ( 1 = xtal , 0= external)
+--! \li             bit-3 - clock connector is an input ( 1=input , 0 = output)
+--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
+--!
+--!
+ENTITY logic_clocks IS
+    GENERIC( 
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT( 
+        ipbus_clk_i           : IN     std_logic;
+        ipbus_i               : IN     ipb_wbus;
+        ipbus_reset_i         : IN     std_logic;
+        Reset_i               : IN     std_logic;
+        clk_logic_xtal_i      : IN     std_logic;   --! 40MHz clock derived from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic;   --! 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic;   --! 160MHz clock
+        ipbus_o               : OUT    ipb_rbus;
+        strobe_8x_logic_o    : OUT    std_logic;   --! strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic;   --! one pulse every 4 cycles of clk_4x
+        DUT_clk_o             : OUT    std_logic;   --! 40MHz to DUTs
+        logic_clocks_locked_o : OUT    std_logic;   --! Goes high if clocks locked.
+        logic_reset_o         : OUT    std_logic    --! Goes high to reset counters etc. Sync with clk_4x_logic
+    );
+
+-- Declarations
+END ENTITY logic_clocks ;
+
+--
+ARCHITECTURE rtl OF logic_clocks IS
+    signal s_clk40 , s_clk40_internal : std_logic;
+    signal s_clk160 ,s_clk160_internal : std_logic;
+    signal ryanclock : std_logic;
+    signal s_clk320 , s_clk320_internal : std_logic;
+    signal s_clk40_out : std_logic;       -- Clock generated by DDR register to feed out of chip.
+    signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
+                                                             -- input from ext
+    --  signal s_logic_clk_rst : std_logic := '0';
+    signal s_locked_pll, s_locked_bufpll : std_logic;
+    
+    signal s_clk : std_logic;
+    signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
+    signal s_extclk, s_extclkG : std_logic;
+    -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic  : std_logic;
+    signal s_clkfbout_buf , s_clkfbout : std_logic;
+    
+    signal s_strobe_generator  : std_logic_vector(3 downto 0) := "1000";  -- ! Store state of ring buffer to generate strobe
+    signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100";  --! Stores state of 40MHz "clock"
+    --signal s_strobe_generator  : std_logic_vector(15 downto 0) := "1111000000000000";  -- ! Store state of ring buffer to generate strobe
+    --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000";  --! Stores state of 40MHz "clock"
+    signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring
+    signal s_strobe_fb : std_logic := '0';
+    
+    signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';  
+                                        -- ! Reset signal in IPBus clock domain
+    signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';  
+                                        -- ! reset signal clocked onto logic-clock domain.
+    attribute SHREG_EXTRACT: string;
+    attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre
+    attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg
+    signal s_ipbus_ack : std_logic := '0';
+    signal s_reset_pll : std_logic := '0';
+    
+    
+    -- ! Global Reset signal
+    signal  s_extclk_internal  : std_logic := '0';
+    signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range );   --! Hold status of clocks
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus write
+    -----------------------------------------------------------------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_logic_reset_ipb <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+            when "00" =>
+             s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
+             
+            when "01" =>
+             s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
+            when others => null;
+            end case;
+       end if;
+
+        -- register reset signal to aid timing.
+        s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+        -- register the clock status signals onto IPBus domain.
+        --s_clock_status_ipb <=  x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+        s_clock_status_ipb <=  x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status. 
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+    -----------------------------------------------------------------------------
+    -- IPBUS read
+    -----------------------------------------------------------------------------
+    with ipbus_i.ipb_addr(1 downto 0) select
+    ipbus_o.ipb_rdata <=
+        s_clock_status_ipb  when "00",
+        (others => '1')      when others;
+
+
+    -----------------------------------------------------------------------------
+    -- Generate reset signal on logic-clock domain
+    -- This relies on the IPBus clock being much slower than the 4x logic clock.
+    -----------------------------------------------------------------------------
+    p_reset: process (s_clk160_internal)
+    begin  -- process p_reset
+    if rising_edge(s_clk160_internal) then
+        s_logic_reset_d1 <= s_logic_reset_ipb_d1;
+        s_logic_reset_d2 <= s_logic_reset_d1;
+        s_logic_reset_d3 <= s_logic_reset_d2;
+        s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3); 
+        s_logic_reset <= s_logic_reset_d4;
+    end if;
+    end process p_reset;
+    
+    logic_reset_o <= s_logic_reset;
+    logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+
+    -- Use Generate, since can't figure out how BUFGMUX works    
+    --  gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
+    --    s_DUT_Clk <= s_extclkG; -- Hard wire for now.    
+    --  end generate gen_extclk_input;
+    --  gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
+    s_DUT_Clk <= clk_logic_xtal_i; 
+    --  end generate gen_intclk_input;  
+  
+
+  
+    --! Clocking primitive
+    -------------------------------------
+    --! Instantiation of the PLL primitive
+    pll_base_inst : PLL_BASE
+    generic map
+       (BANDWIDTH            => "OPTIMIZED",
+        --CLK_FEEDBACK         => "CLKOUT0", --"CLKFBOUT",
+        CLK_FEEDBACK         => "CLKFBOUT",
+        COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+        DIVCLK_DIVIDE        => 1,
+        CLKFBOUT_MULT        => 16,
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE       => 2, -- 1-->2 move from 640 to 320
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => 4, -- 4-->8 move from 160 to 80
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKOUT2_DIVIDE       => 16, -- 16--> 32 move from 40 to 20
+        CLKOUT2_PHASE        => 0.000,
+        CLKOUT2_DUTY_CYCLE   => 0.500,
+        CLKIN_PERIOD         => 25.000,
+        REF_JITTER           => 0.010)
+    port map(
+        -- Output clocks
+        CLKFBOUT            => s_clkfbout,
+        CLKOUT0             => s_clk320,
+        CLKOUT1             => s_clk160,
+        CLKOUT2             => s_clk40,
+        CLKOUT3             => open,
+        CLKOUT4             => open,
+        CLKOUT5             => open,
+        -- Status and control signals
+        LOCKED              => s_locked_pll,
+        --    RST                 => s_logic_clk_rst,
+        RST                 => s_reset_pll,
+        -- Input clock control
+        --    CLKFBIN             => s_clkfbout_buf,
+        CLKFBIN             => s_clkfbout,
+        CLKIN               => s_DUT_clk);
+        --      CLKIN               => clk_logic_xtal_i);
+
+    s_reset_pll <= Reset_i or s_logic_reset; 
+
+-----------------------------------------------
+--BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR 
+  -- Buffer the 16x clock and generate the ISERDES strobe signal
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK  => s_clk640_internal,          -- 1-bit output: Output I/O clock
+--      LOCK   => s_locked_bufpll,            -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => strobe_16x_logic_O,   -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK   => s_clk160_internal,          -- 1-bit input: BUFG clock input
+--      LOCKED => s_locked_pll,               -- 1-bit input: LOCKED input from PLL
+--      PLLIN  => s_clk640                    -- 1-bit input: Clock input from PLL
+--   );
+
+    BUFG_inst: BUFG
+    port map (
+        I => s_clk320,
+        O => s_clk320_internal    
+    );
+    
+--    BUFR_inst: BUFR
+--    generic map (
+--        BUFR_DIVIDE => "4"
+--    )
+--    port map (
+--        I   => s_clk160_internal,
+--        CE  => '1',
+--        CLR => '0',
+--        O   => ryanclock
+--    );
+    
+--    BUFG_inst2: BUFG
+--    port map (
+--        I => ryanclock,
+--        O => strobe_16x_logic_O    -- Not sure this is actually a strobe... Check
+--    );
+-----------------------------------------------
+
+	clk_8x_logic_o <= s_clk320_internal;
+	DUT_clk_o <= s_DUT_clk;
+
+
+  
+  -- Generate a strobe signal every 4 clocks. 
+  -- Can't use a clock signal as a combinatorial signal. Hence the baroque
+  -- method of generating a strobe. Add a mechanism to restart if the '1' gets
+  -- lost ....
+    
+    ------------------
+    generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out)
+    begin  -- process generate_4x_strobe
+    if rising_edge(s_clk160_internal) then
+        if s_logic_reset = '1' then
+            s_strobe_generator <= "1000";
+            s_logic_clk_generator <= "1100";
+            --s_strobe160 <= "1000000000000000";
+        elsif (s_locked_pll ='1') then
+            s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left      
+            s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left 
+            --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+        end if;
+    end if;
+    end process generate_4x_strobe;
+    strobe_4x_logic_o <=  s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse
+    s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems.
+    ---------------
+    
+    generate_8x_strobe: process (s_clk320_internal)
+    begin
+    if rising_edge(s_clk320_internal) then
+        if s_logic_reset = '1' then
+            s_strobe160 <= "1000000000000000"; 
+            --s_strobe_generator <= "1111000000000000";--
+            --s_logic_clk_generator <= "1111111100000000";--
+        elsif (s_locked_pll ='1') then
+            s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+            --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); --       
+            --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left
+        end if;
+    end if;
+    end process generate_8x_strobe;
+    strobe_8x_logic_O <= s_strobe160(15);
+    --strobe_4x_logic_o <=  s_strobe_generator(15); -- 
+    --s_clk40_out <= s_logic_clk_generator(15); -- 
+        
+
+  -- buffer 160MHz (4x) clock
+  --------------------------------------
+    clk160_o_buf : BUFG
+    port map(
+        O   => s_clk160_internal,
+        I   => s_clk160);
+    
+    clk_4x_logic_o <= s_clk160_internal;
+ 
+--   -- buffer 40MHz (1x) clock
+--  --------------------------------------
+--  clk40_o_buf : BUFG
+--  port map(
+--    O   => s_clk40_internal,
+--    I   => s_clk40);
+
+--  clk_logic_o <= s_clk40_out;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/pulseClockDomainCrossing_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/pulseClockDomainCrossing_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..663cac3b9e4476ee3146730afc6efc5d79225de3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/pulseClockDomainCrossing_rtl.vhd
@@ -0,0 +1,100 @@
+--=============================================================================
+--! @file pulseClockDomainCrossing_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
+--
+--! @brief Takes a pulse synchronized with one clock and produces a
+--! pulse synchronized to another clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date September/2012
+--
+--! @version v0.1
+--
+--! @details A "ring" of D-type flip-flops is used to transfer a strobe
+--! from the input clock domain to the output clock domain and then back again.
+--! The time taken to transit from input to output is approximately
+--! two clock cycles of clock_output_i .
+--! After an additional two cycles of clk_input_i another pulse can be sent
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulseClockDomainCrossing is
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    pulse_i     : in std_logic;         --! input pulse. Active high
+    clk_output_i: in std_logic;         --! clock for output
+    pulse_o     : out std_logic         --! Single cycle pulse synchronized to clock_output_i
+    );
+
+end pulseClockDomainCrossing;
+
+architecture rtl of pulseClockDomainCrossing is
+
+  signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
+  
+begin  -- rtl
+
+  -- purpose: registers and flip-flop on clk_input_i
+  p_input_clock_logic: process (clk_input_i)
+  begin  
+    if rising_edge(clk_input_i) then
+
+      -- Register signals coming from output clock domain back to the
+      -- input clock domain
+      s_pulse_back_d1 <= s_pulse_out_d2;
+      s_pulse_back_d2 <= s_pulse_back_d1;
+
+      -- JK flip-flop
+      if (s_pulse_back_d2 = '1')  then
+        s_pulse_out <= '0';
+      elsif (pulse_i = '1')  then
+        s_pulse_out <= '1';
+      end if;
+
+    end if;
+  end process p_input_clock_logic;
+
+  -- purpose: registers and flip-flop on clk_output_o
+  p_output_clock_logic: process (clk_output_i)
+  begin  
+    if rising_edge(clk_output_i) then
+
+      -- Register signal on input clock domain onto output clock domain
+      s_pulse_out_d1 <= s_pulse_out;
+      s_pulse_out_d2 <= s_pulse_out_d1;
+
+      s_pulse_out_d3 <= s_pulse_out_d2;
+      s_pulse_out_d4 <= s_pulse_out_d3;
+
+      -- Generate single clock-cycle pulse on pulse_o
+      pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
+
+    end if;
+  end process p_output_clock_logic;
+
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/registerCounter_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/registerCounter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de5587cd9ab98905a3da88d0eb2cd5a3c8a279ee
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/registerCounter_rtl.vhd
@@ -0,0 +1,113 @@
+--=============================================================================
+--! @file registerCounter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.registerCounter.rtl
+--
+--! @brief Regularly transfers the input to the output.\n
+--! One clock for input , one clock for output\n
+--! Can't just put entire bus through a couple of register stages,\n
+--! Since this will just swap meta-stability issues for race issues.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 24/Nov/12
+--
+--! @version v0.1
+--
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! We could use gray-scale and put through registers, but this method
+--! should work well enough at the expense of latency.\n
+--! \n
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity registerCounter is
+  
+  generic (
+    g_DATA_WIDTH : positive := 15);     -- ! Width of counter
+
+  port (
+    clk_input_i : in std_logic;         -- ! clock for input
+    data_i      : in std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! data to transfer to output
+    data_o     : out std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! Data now in clk_read_i domain
+    clk_output_i  : in std_logic);        -- ! clock for output
+
+end registerCounter;
+
+architecture rtl of registerCounter is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0');  -- ! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  -- ! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2;  --! Generate a strobe with
+                                                --width one clk_read_i
+  
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5;  --! Generate a strobe
+                                                  --
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/serdes_1_to_n_SDR.vhd b/AIDA_tlu/legacy/TLU_v1c/common/serdes_1_to_n_SDR.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0a119e3cb6fd53afcdc50779d0affc9703b57ce
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/serdes_1_to_n_SDR.vhd
@@ -0,0 +1,235 @@
+------------------------------------------------------------------------------/
+-- Copyright (c) 2009 Xilinx, Inc.
+-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
+------------------------------------------------------------------------------/
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor: Xilinx
+-- \   \   \/    Version: 1.0
+--  \   \        Filename: top_nto1_ddr_diff_rx.vhd
+--  /   /        Date Last Modified:  November 5 2009
+-- /___/   /\    Date Created: June 1 2009
+-- \   \  /  \
+--  \___\/\___\
+-- 
+--Device:   Spartan 6
+--Purpose:    Example differential input receiver for DDR clock and data using 2 x BUFIO2
+--    Serdes factor and number of data lines are set by constants in the code
+--Reference:
+--    
+--Revision History:
+--    Rev 1.0 - First created (nicks)
+--
+------------------------------------------------------------------------------/
+--
+--  Disclaimer: 
+--
+--    This disclaimer is not a license and does not grant any rights to the materials 
+--              distributed herewith. Except as otherwise provided in a valid license issued to you 
+--              by Xilinx, and to the maximum extent permitted by applicable law: 
+--              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+--              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+--              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+--              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+--              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+--              of any kind or nature related to, arising under or in connection with these materials, 
+--              including for any direct, or any indirect, special, incidental, or consequential loss 
+--              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+--              as a result of any action brought by a third party) even if such damage or loss was 
+--              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+--
+--  Critical Applications:
+--
+--    Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+--    requiring fail-safe performance, such as life-support or safety devices or systems, 
+--    Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+--    or any other applications that could lead to death, personal injury, or severe property or 
+--    environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+--    the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+--    to applicable laws and signalulations governing limitations on product liability.
+--
+--  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Serdes 1 to n SDR
+--! @author Alvaro Dosil
+-------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all ;
+
+library unisim ;
+use unisim.vcomponents.all ;
+
+entity serdes_1_to_n_SDR is 
+generic ( g_S : integer := 4);       --! Parameter to set the serdes factor 1..8
+port( clk_i  : in std_logic;         --! Fast clock to sample data (640MHz)
+      hclk_i   : in std_logic;       --! A quarter frequency clock (160MHz)
+      reset_i  : in std_logic;       --! reset signal
+      Data_i   : in std_logic;       --! 1-Bit Input data
+      strobe_i : in std_logic;       --! Iserdes strobe_i
+      Data_o   : out std_logic_vector(2*g_S-1 downto 0)  --! data output
+		);
+    
+end serdes_1_to_n_SDR;
+
+
+architecture Behavioral of serdes_1_to_n_SDR is
+
+signal s_Data_i_d_m  : std_logic;     -- Data_i delayed master
+signal s_Data_i_d_2m : std_logic;     -- Data_i delayed master second signal
+signal s_Data_i_d_s  : std_logic;     -- Data_i delayed slave
+signal s_Data_i_d_2s : std_logic;     -- Data_i delayed slave second signal
+signal s_Data_o      : std_logic_vector(2*g_S-1 downto 0);
+
+--signal s_clk_b       : std_logic;
+--signal s_ISERDES_STROBE : std_logic;
+
+begin
+	
+---- Generate the ISERDES strobe signal
+--
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK => s_clk_b,                -- 1-bit output: Output I/O clock
+--      LOCK => open,                     -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => s_ISERDES_STROBE, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK => hclk_i,                     -- 1-bit input: BUFG clock input
+--      LOCKED => locked_pll_i,                  -- 1-bit input: LOCKED input from PLL
+--      PLLIN => clk_i                -- 1-bit input: Clock input from PLL
+--   );
+	
+
+  IODELAY2_M : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",     -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",         -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",          -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE     => 0,                -- Amount of taps for fixed input delay (0-255)
+    IDELAY2_VALUE    => 0,                -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE     => 0,                -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE      => "NONE"            -- "NONE", "MASTER" or "SLAVE" 
+--    SIM_TAPDELAY_VALUE=> 43                -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,          -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_m,     -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2m,    -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,          -- 1-bit output: Delayed data output
+    TOUT     => open,          -- 1-bit output: Delayed 3-state output
+    CAL      => '0',           -- 1-bit input: Initiate calibration input
+    CE       => '0',           -- 1-bit input: Enable INC input
+    CLK      => '0',           -- 1-bit input: Clock input
+    IDATAIN  => Data_i,        -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',           -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',           -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',           -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',           -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,         -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'            -- 1-bit input: 3-state input signal
+   );
+
+
+  IODELAY2_S : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",      -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",       -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE       => 10,--29,            -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
+    IDELAY2_VALUE      => 0,             -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE       => 0,             -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE        => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+    --SIM_TAPDELAY_VALUE => 43              -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,             -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_s,        -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2s,       -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,             -- 1-bit output: Delayed data output
+    TOUT     => open,             -- 1-bit output: Delayed 3-state output
+    CAL      => '0',              -- 1-bit input: Initiate calibration input
+    CE       => '0',              -- 1-bit input: Enable INC input
+    CLK      => '0',              -- 1-bit input: Clock input
+    IDATAIN  => Data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',              -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',              -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,            -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'               -- 1-bit input: 3-state input signal
+   );
+
+
+  ISERDES2_M : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(1),
+    Q2     => s_Data_o(3),
+    Q3     => s_Data_o(5),
+    Q4     => s_Data_o(7), 
+    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,                 -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+    CE0     => '1',                  -- 1-bit input Clock enable input
+	 CLK0    => clk_i,                -- 1-bit input I/O clock network input
+    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,               -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_m,         -- 1-bit input Input data
+    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+  ISERDES2_S : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,          -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"          -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(0),
+    Q2     => s_Data_o(2),
+    Q3     => s_Data_o(4),
+    Q4     => s_Data_o(6),
+    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,               -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+    CE0     => '1',                -- 1-bit input Clock enable input
+	 CLK0    => clk_i,              -- 1-bit input I/O clock network input
+    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,             -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_s,       -- 1-bit input Input data
+    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+reg_out : process(hclk_i)
+begin
+  if rising_edge(hclk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/single_pulse_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/single_pulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e5da6214a380987ce7b7f9d4969ead408ebbafee
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/single_pulse_rtl.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--! @file
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-------------------------------------------------------------------------------
+--
+-- VHDL for producing a single clock low-high-low pulse on the rising edge
+-- of input signal (LEVEL)
+--
+-- David Cussans, Ocala, April 2005
+--
+-- LEVEL (input) - when LEVEL goes high, PULSE goes high for one clock cycle
+--               - on next rising edge of CLK
+-- CLK (input)   - rising edge active
+-- PULSE         - changes on rising edge of clk
+--
+--! @brief gives a single cycle pulse ( high active) following the rising edge of LEVEL
+
+entity single_pulse is
+  generic (
+    g_PRE_REGISTER  : boolean := false;  -- --! Set true to put a register before rising edge detect
+    g_POST_REGISTER : boolean := false);  -- --! Set tru to put a register after rising edge detect
+  port (
+    level : in  std_logic; --! When LEVEL goes high, PULSE goes high for one clock cycle
+    clk : in  std_logic; --! rising edge active
+    pulse : out  std_logic              --! Pulses high for one cycle
+    );
+end entity single_pulse;
+
+architecture rtl of single_pulse is
+
+  signal pre_level, pre_pulse , x, v : std_logic;
+  
+begin  -- architecture rtl
+
+  -----------------------------------------------
+  -- Optional register on input
+  -----------------------------------------------
+  gen_pre_ff: if g_PRE_REGISTER=true generate
+    ffpre: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pre_level <= level;
+      end if;
+    end process ffpre;
+  end generate gen_pre_ff;
+
+  gen_no_pre_ff: if g_PRE_REGISTER=false generate
+    pre_level <= level;
+  end generate gen_no_pre_ff;
+
+  -----------------------------------------------
+  -- Register signal
+  -----------------------------------------------  
+  ff1: process (clk , level) is
+  begin  -- process ff1
+    if rising_edge(clk) then
+      x <= pre_level;
+    end if;
+  end process ff1;
+
+  -----------------------------------------------
+  -- Edge detection logic
+  -----------------------------------------------  
+  ff2: process (clk , x) is
+  begin  -- process ff2
+    if rising_edge(clk) then
+      v <= not x;
+    end if;
+  end process ff2;                           
+                           
+  pre_pulse <= ( x and v );
+
+
+  -----------------------------------------------
+  -- Optional register on output
+  -----------------------------------------------
+  gen_post_ff: if g_POST_REGISTER=true generate
+    ffpost: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pulse <= pre_pulse;
+      end if;
+    end process ffpost;
+  end generate gen_post_ff;
+
+  gen_no_post_ff: if g_POST_REGISTER=false generate
+    pulse <= pre_pulse;
+  end generate gen_no_post_ff;
+  
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/stretchPulse_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/stretchPulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..957a4c6d4164aa9b2b58dea19e86a068aa8f84de
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/stretchPulse_rtl.vhd
@@ -0,0 +1,92 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+--! @brief Takes a pulse on input, stretches it and delays it.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! Definition of trigger time
+USE work.fmcTLU.all;                    
+
+entity stretchPulse is
+  
+  generic (
+    g_PARAM_WIDTH : positive := 5);  --! number of bits in parameters (width,  delay)
+
+  port (
+    clk_i        : in  std_logic;       --! Active high
+    pulse_i      : in  std_logic;       --! Active high
+    pulse_o      : out std_logic;       --! delayed and stretched
+    triggerTime_i : in t_triggerTime;   --! 5-bit time
+    triggerTime_o : out t_triggerTime;  --! Delayed by same amount as pulse
+    
+    pulseWidth_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0);  --! Minimum pulse width ( in clock cycles )
+    pulseDelay_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0) --! Delay is pulseDelay_i +1 clock cycles
+    );      
+
+end entity stretchPulse;
+
+-- For now just delay the pulse.
+architecture rtl of stretchPulse is
+
+  signal s_delaySR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate delay
+  signal s_stretchSR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate stretch
+  signal s_delayedPulse : std_logic := '0';  -- delayed pulse before stretch
+
+  signal s_triggerTimeSR : t_triggerTimeArray ( (2**g_PARAM_WIDTH)-1 downto 0) := ( others => ( others => '0'));  -- array of trigger times
+  signal s_triggerTime_d1 : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  signal s_stretchedTriggerTime : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  
+begin  -- architecture rtl
+
+  
+  --! Delay pulse
+  p_delayPulse: process (clk_i , pulse_i) is
+  begin  -- process p_delayPulse
+    if rising_edge(clk_i) then
+      s_delaySR <= s_delaySR( (s_delaySR'left -1) downto 0 ) & pulse_i;
+      s_delayedPulse <= s_delaySR( to_integer(unsigned(pulseDelay_i)) );
+
+      -- delay the trigger time to match trigger delay
+      s_triggerTimeSR <=  s_triggerTimeSR( (s_triggerTimeSR'left -1)  downto 0 ) & triggerTime_i;
+      s_triggerTime_d1 <=  s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) ); 
+--      triggerTime_o <= s_triggerTime_d1 ;
+      
+    end if;
+  end process p_delayPulse;
+
+  --! Stretch pulse. the output pulse is always at least as long as the input pulse
+  p_stretchPulse: process (clk_i , pulse_i) is
+  begin  -- process p_stretchPulse
+    if rising_edge(clk_i) then
+      if s_delayedPulse = '1' then
+        s_stretchSR <= ( others => '1' ) ;
+        pulse_o <= s_delayedPulse ;
+      else
+        s_stretchSR <= s_stretchSR( (s_stretchSR'left -1) downto 0 ) & '0';
+        pulse_o <= s_stretchSR( to_integer(unsigned(pulseWidth_i)) );
+      end if;
+
+      if s_stretchSR( to_integer(unsigned(pulseWidth_i)) ) = '0' then
+        --s_stretchedTriggerTime <= s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) );
+        triggerTime_o <= s_triggerTime_d1;
+      end if;
+      --triggerTime_o <= s_stretchedTriggerTime ;
+      
+    end if;
+  end process p_stretchPulse;
+
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/sychronizedIPBusCtrlRegV_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/sychronizedIPBusCtrlRegV_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e1d751261317129227224e221add93ff745a83e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/sychronizedIPBusCtrlRegV_rtl.vhd
@@ -0,0 +1,83 @@
+--=============================================================================
+--! @file 
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+--! @brief IPBus registers synchronzied onto logic clock
+--!
+--! @details Uses DMN ipbus_ctrlreg_v - originally tried to use
+--! ipbus_ctrlreg_sync, but had poor results and added own synchronzier.
+
+entity synchronizedIPBusCtrlRegV_rtl is
+	generic(
+		N_CTRL: positive := 1;
+		N_STAT: positive := 1
+	);
+	port(
+		ipbus_clk_i: in std_logic;
+		ipbus_reset_i: in std_logic;
+		ipbus_i: in ipb_wbus;
+		ipbus_o: out ipb_rbus;
+                logic_clk_i: in std_logic;
+		status_to_ipbus_i: in ipb_reg_v(N_STAT - 1 downto 0); --! Synchronized to logic_clk_i       
+		sync_control_from_ipbus_o: out ipb_reg_v(N_CTRL - 1 downto 0); --! Synchronized to logic_clk_i
+		stb_o: out std_logic_vector(N_CTRL - 1 downto 0) --! high when change made to a control register. Broken ( needs to be retimed )
+	);
+	
+end synchronizedIPBusCtrlRegV_rtl;
+
+
+architecture rtl of synchronizedIPBusCtrlRegV_rtl is
+
+  signal s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus   : ipb_reg_v(c_N_CTRL-1 downto 0);
+ 
+begin  -- architecture rtl
+
+  
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  stb_o
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  status_to_ipbus_i,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => sync_control_from_ipbus_o,
+      clk_output_i => clk_4x_logic_i);
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/sync_reg.vhd b/AIDA_tlu/legacy/TLU_v1c/common/sync_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e88eb54b67be346b7398099036524bcd023f6c9d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/sync_reg.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    15/08/2012 
+-- Module Name:    Conf_Regs - Behavioral 
+-- Revision 1.00 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 32b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity sync_reg is
+  generic(g_Data_width : positive := 32);
+  port(
+    clk_i : in std_logic;  --! synchronous clock
+    Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
+	 Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
+  
+end sync_reg;
+
+--! @brief
+--! @details Synchronize words (n bits)of data 
+
+architecture Behavioral of sync_reg is
+
+signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
+signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
+begin
+  
+loop0: for i in 0 to g_Data_width-1 generate
+  begin
+  reg: entity work.Reg_2clks
+    port map(
+	   clk_i => clk_i,
+		async_i => s_async_i(i),
+		sync_o => s_sync_o(i));
+  end generate;
+ 
+s_async_i <= Async_i; 
+Sync_o <= s_sync_o;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_fifo.vhd b/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ebae77b4608297df1d02232d5891e1c0aa2cd7a9
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_fifo.vhd
@@ -0,0 +1,110 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+
+
+entity synchronizeRegisters_fifo is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters_fifo;
+
+architecture rtl of synchronizeRegisters_fifo is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+  COMPONENT sync_fifo
+    PORT (
+      rst : IN STD_LOGIC;
+      wr_clk : IN STD_LOGIC;
+      rd_clk : IN STD_LOGIC;
+      din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_en : IN STD_LOGIC;
+      rd_en : IN STD_LOGIC;
+      dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      full : OUT STD_LOGIC;
+      empty : OUT STD_LOGIC
+    );
+  END COMPONENT;
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  gen_syncReg: for v_reg in 0 to g_NUM_REGISTERS-1 generate
+      mySynchReg : sync_fifo
+        PORT MAP (
+          rst => '0',
+          wr_clk => clk_input_i,
+          rd_clk => clk_output_i,
+          din => data_i(v_reg),
+          wr_en => '1',
+          rd_en => '1',
+          dout => data_o(v_reg),
+          full => open,
+          empty => open
+        );
+  end generate gen_syncReg;
+  
+--  p_gen_capture_strobe: process (clk_input_i)
+--  begin  -- process p_gen_capture_strobe
+--    if rising_edge(clk_input_i) then
+--      s_ring_d0 <= not s_ring_d5;
+--      s_ring_d1 <= s_ring_d0;
+--      s_ring_d2 <= s_ring_d1;
+
+--      if s_read_strobe = '1' then
+--        s_registered_data <= data_i;
+--      end if;
+--    end if;    
+--  end process p_gen_capture_strobe;
+
+--  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+--  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+--  -- type   : combinational
+--  -- inputs : clk_output_i
+--  -- outputs: 
+--  p_gen_output_strobe: process (clk_output_i)
+--  begin  -- process p_gen_output_strobe
+--    if rising_edge(clk_output_i) then
+--      s_ring_d3 <= s_ring_d2;
+--      s_ring_d4 <= s_ring_d3;
+--      s_ring_d5 <= s_ring_d4;
+
+--      if s_write_strobe = '1' then
+--        data_o <= s_registered_data;
+--      end if;
+--    end if;    
+--  end process p_gen_output_strobe;
+
+--  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bb7d59a7e8d748cb160690d37e4e2225ffaf9e5a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/synchronizeRegisters_rtl.vhd
@@ -0,0 +1,103 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Regularly transfers the input to the output.
+--! One clock for input , one clock for output
+--! Can't just put entire bus through a couple of register stages,
+--! Since this will just swap meta-stability issues for race issues.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 24/Nov/12
+--!
+--! @version v0.1
+--!
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--! Based on registerCounters
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+
+entity synchronizeRegisters is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters;
+
+architecture rtl of synchronizeRegisters is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/test_inToOut.vhd b/AIDA_tlu/legacy/TLU_v1c/common/test_inToOut.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..91b60eec700141731d07a95e72c903a597e4e6ef
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/test_inToOut.vhd
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 14:45:31
+-- Design Name: 
+-- Module Name: test_inToOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inToOut is
+    Generic(
+        DUT_TOGGLE : integer  :=1; --HDMI that toggles
+        DUT_OUT : integer := 2; --HDMI used as input
+        DUT_IN : integer := 0; --HDMI used as output
+        DUT_DULL : integer := 3 --HDMI not used
+    );
+    Port ( clk_in : in STD_LOGIC;
+           busy_in : in STD_LOGIC_VECTOR (3 downto 0);
+           control_in : in STD_LOGIC_VECTOR (3 downto 0);
+           trig_in : in STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_in : in STD_LOGIC_VECTOR (3 downto 0);
+           spare_in : in STD_LOGIC_VECTOR (3 downto 0);
+           busy_out : out STD_LOGIC_VECTOR (3 downto 0);
+           control_out : out STD_LOGIC_VECTOR (3 downto 0);
+           trig_out : out STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_out : out STD_LOGIC_VECTOR (3 downto 0);
+           spare_out : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inToOut;
+
+architecture Behavioral of test_inToOut is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(4 downto 0);
+    signal clk_slow_i : std_logic_vector(4 downto 0);
+    signal placeholder: std_logic_vector(4 downto 0);
+
+begin
+
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+        clk_slow_i(4) <= outcounter(4);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+      
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+  
+      clkDut_out(DUT_OUT) <= clkDut_in(DUT_IN);
+      busy_out(DUT_OUT) <= busy_in(DUT_IN);
+      control_out(DUT_OUT) <= control_in(DUT_IN);
+      trig_out(DUT_OUT) <= trig_in(DUT_IN);
+      spare_out(DUT_OUT) <= spare_in(DUT_IN);
+      
+      clkDut_out(DUT_DULL) <= '0';
+      busy_out(DUT_DULL) <= '0';
+      control_out(DUT_DULL) <= '0';
+      trig_out(DUT_DULL) <= '0';
+      spare_out(DUT_DULL) <= '0';
+    end if;
+    end process gen_clk;
+    
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/test_inputToOutput.vhd b/AIDA_tlu/legacy/TLU_v1c/common/test_inputToOutput.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b8cbb1d914de2e1c84d446bd3236885b24f318fc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/test_inputToOutput.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 12:54:36
+-- Design Name: 
+-- Module Name: test_inputToOutput - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inputToOutput is
+    Port ( clk_i : in STD_LOGIC;
+           test_i : in STD_LOGIC_VECTOR (3 downto 0);
+           test_o : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inputToOutput;
+
+architecture Behavioral of test_inputToOutput is
+    signal synch_lines : std_logic_vector(3 downto 0);
+begin
+    synch_io : process (clk_i)
+    begin
+        if rising_edge(clk_i) then
+            synch_lines <= test_i;
+            test_o(1) <= synch_lines(0);
+            test_o(3) <= synch_lines(2);
+            test_o(0) <= '0';
+            test_o(2) <= '1';
+        end if;
+    end process synch_io;
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/test_toggleLines.vhd b/AIDA_tlu/legacy/TLU_v1c/common/test_toggleLines.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed585cdb02aabf04b00bff39d8962d0c7a571b74
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/test_toggleLines.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06.02.2017 10:09:26
+-- Design Name: 
+-- Module Name: test_toggleLines - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_toggleLines is
+    Port (
+        clk_in : in STD_LOGIC;
+        toggle_o : out std_logic_vector(3 downto 0)
+        );
+end test_toggleLines;
+
+architecture Behavioral of test_toggleLines is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(3 downto 0);
+    signal clk_slow_i : std_logic_vector(3 downto 0);
+    
+begin
+
+  gen_clk : process (clk_in)
+  begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+    end if;
+  end process gen_clk;
+
+  toggle_o <= clk_slow_i;
+
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/testbench_clocks.vhd b/AIDA_tlu/legacy/TLU_v1c/common/testbench_clocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..052b220c4e4e5e7b7d354731525a4e935a289d6f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/testbench_clocks.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:26:56
+-- Design Name: 
+-- Module Name: testbench_clocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity testbench_clocks is
+--  Port ( );
+end testbench_clocks;
+
+architecture Behavioral of testbench_clocks is
+
+begin
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/testbench_myclocks.vhd b/AIDA_tlu/legacy/TLU_v1c/common/testbench_myclocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c17c7db550bad4f2ee74c868331b64ae7a9cd80b
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/testbench_myclocks.vhd
@@ -0,0 +1,99 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:31:53
+-- Design Name: 
+-- Module Name: testbench_myclocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+
+entity testbench_myclocks is
+end testbench_myclocks;
+
+architecture Behavioral of testbench_myclocks is
+
+ COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    SIGNAL sysclk_40         : std_logic := '0';
+    SIGNAL clk_8x_logic         : std_logic := '0';
+    SIGNAL clk_4x_logic         : std_logic := '0';
+    SIGNAL strobe_8x_logic         : std_logic := '0';
+    SIGNAL strobe_4x_logic         : std_logic := '0';
+    SIGNAL logic_reset         : std_logic := '0';
+    signal ipbus_i_const             : ipb_wbus;
+
+
+begin
+    
+      ipbus_i_const.ipb_strobe <= '0';
+      ipbus_i_const.ipb_write <= '0';
+      ipbus_i_const.ipb_wdata <= (others => '0');
+    
+        I3_Clocks : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => '0',
+        ipbus_i               => ipbus_i_const,
+        ipbus_reset_i         => '0',
+        Reset_i               => '0',
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => open,
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => open,
+        logic_reset_o         => logic_reset
+    );  
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_ax3_pm3.vhd b/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_ax3_pm3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..589be2f2d67563dad293f528c9c23c1589e4927a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_ax3_pm3.vhd
@@ -0,0 +1,173 @@
+-- Top-level design for ipbus demo
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top is
+    generic(
+    g_NUM_DUTS  : positive := 3;
+    g_NUM_TRIG_INPUTS   :positive := 4;
+    g_NUM_EXT_SLAVES    :positive :=8;
+    g_EVENT_DATA_WIDTH  :positive := 64;
+    g_IPBUS_WIDTH   :positive := 32;
+    g_NUM_EDGE_INPUTS   :positive := 4;
+    g_SPILL_COUNTER_WIDTH   :positive := 12;
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+        sysclk: in std_logic;
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        i2c_scl_b: inout std_logic_vector(2 downto 0);
+        i2c_sda_b: inout std_logic_vector(2 downto 0);
+        phy_rstn: out std_logic; --default example ends here
+        busy_n_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        busy_p_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        cfd_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        cfd_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        gpio_hdr: out std_logic_vector(3 downto 0);
+        reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 1);
+        shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 1)
+        );
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	SIGNAL s_i2c_scl_enb         : std_logic_vector(2 downto 0);
+    SIGNAL s_i2c_sda_enb         : std_logic_vector(2 downto 0);
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b(0) <= '0' when (s_i2c_scl_enb(0) = '0') else 'Z';
+    i2c_sda_b(0) <= '0' when (s_i2c_sda_enb(0) = '0') else 'Z';
+    i2c_scl_b(1) <= '0' when (s_i2c_scl_enb(1) = '0') else 'Z';
+    i2c_sda_b(1) <= '0' when (s_i2c_sda_enb(1) = '0') else 'Z';
+    i2c_scl_b(2) <= '0' when (s_i2c_scl_enb(2) = '0') else 'Z';
+    i2c_sda_b(2) <= '0' when (s_i2c_sda_enb(2) = '0') else 'Z';
+-- Infrastructure
+
+
+
+
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => sysclk,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	leds <= not ('0' & userled & inf_leds);
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151f"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81f"; -- 192.168.200.16+n
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+--	slaves: entity work.ipbus_example
+--		port map(
+--			ipb_clk => clk_ipb,
+--			ipb_rst => rst_ipb,
+--			ipb_in => ipb_out,
+--			ipb_out => ipb_in,
+--			nuke => nuke,
+--			soft_rst => soft_rst,
+--			i2c_scl_b => i2c_scl_b,
+--            i2c_sda_b => i2c_sda_b,
+--			userled => userled
+--		);
+    --OBUFT: Single-ended 3-state Output Buffer
+--7 Series
+-- Xilinx HDL Libraries Guide, version 2012.2
+
+--OBUFT_inst_scl : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_scl_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_scl_enb, -- 3-state enable input
+--    O =>  s_i2c_scl_i
+--); -- End of OBUFT_inst instantiation
+
+--OBUFT_inst_sda : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_sda_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_sda_enb, -- 3-state enable input
+--    O =>  s_i2c_sda_i
+--); -- End of OBUFT_inst instantiation
+    
+    slaves: entity work.ipbus_example
+    port map(
+        ipb_clk => clk_ipb,
+        ipb_rst => rst_ipb,
+        ipb_in => ipb_out,
+        ipb_out => ipb_in,
+        nuke => nuke,
+        soft_rst => soft_rst,
+        --i2c_scl_i => s_i2c_scl_i,
+        --i2c_sda_i => s_i2c_sda_i,
+        i2c_sda_i => i2c_sda_b,
+        i2c_scl_i => i2c_scl_b,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        userled => userled
+    );
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_tlu.vhd b/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_tlu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e14ae242c7b7479abf590e488071ac7b9b36cbec
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/top_enclustra_tlu.vhd
@@ -0,0 +1,752 @@
+-- Top-level design for TLU
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fmcTLU.all;
+use work.ipbus_decode_tlu.all;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use UNISIM.vcomponents.all;
+
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top_tlu is
+    generic(
+    constant FW_VERSION : unsigned(31 downto 0):= X"abcd000d"; -- Firmware revision. Remember to change this as needed.
+    g_NUM_DUTS  : positive := 4; -- <- was 3
+    g_NUM_TRIG_INPUTS   :positive := 6;-- <- was 4
+    g_NUM_EDGE_INPUTS   :positive := 6;--  <-- was 4
+    g_NUM_EXT_SLAVES    :positive :=8;--  <-- ??
+    g_EVENT_DATA_WIDTH  :positive := 64;--  <-- ??
+    g_IPBUS_WIDTH   :positive := 32;--  <-- was 32 
+    g_SPILL_COUNTER_WIDTH   :positive := 12;--  <-- ??
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+    --Clock
+        --sysclk: in std_logic; --50 MHz clock input from FPGA
+        clk_enclustra: in std_logic; --Enclustra onboard oscillator 40 MHz. Used for the IPBus block
+        sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_40_i_p: in std_logic;
+        sysclk_40_i_n: in std_logic;
+    --Misc
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
+    --RGMII interface signals
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        phy_rstn: out std_logic; 
+    --I2C bus
+        i2c_scl_b: inout std_logic;
+        i2c_sda_b: inout std_logic;
+        i2c_reset: out std_logic; --Reset line for the expander serial lines
+    --Clock generator controls
+        clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low)
+        --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0>
+    --TLU signals for DUTs
+        busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA)
+        busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA)
+        cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs
+        cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs
+        spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs
+        spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs
+        triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs
+        triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs
+        dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs
+        dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock to DUTs
+        
+        --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal
+        --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output
+        --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+                
+     --TLU trigger inputs   
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0)
+        --gpio_hdr: out std_logic_vector(3 downto 0);
+        --extclk_n_b: inout std_logic; --External clock in or clock output
+        --extclk_p_b: inout std_logic
+    );
+
+end top_tlu;
+
+architecture rtl of top_tlu is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	signal s_i2c_scl_enb         : std_logic;
+    signal s_i2c_sda_enb         : std_logic;
+    signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input)
+    
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	------------------------------------------
+	-- Internal signal declarations
+    SIGNAL T0_o                  : std_logic;
+    SIGNAL buffer_full_o         : std_logic;                                             --! Goes high when event buffer almost full
+    SIGNAL clk_8x_logic         : std_logic;                                             -- 320MHz clock
+    SIGNAL clk_4x_logic          : std_logic;                                             --! normally 160MHz
+    SIGNAL clk_logic_xtal        : std_logic;                                             -- ! 40MHz clock from onboard xtal
+    SIGNAL data_strobe           : std_logic;                                             -- goes high when data ready to load into event buffer
+    SIGNAL dout                  : std_logic;
+    SIGNAL dout1                 : std_logic;
+    SIGNAL event_data            : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+    signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
+    signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+    SIGNAL logic_clocks_reset    : std_logic;                                             -- Goes high to reset counters etc. Sync with clk_4x_logic
+    SIGNAL logic_reset           : std_logic;
+    SIGNAL overall_trigger       : std_logic;                                             --! goes high to load trigger data
+    SIGNAL overall_veto          : std_logic;                                             --! Halts triggers when high
+    SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL postVetotrigger       : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        -- ! High when trigger from input connector active and enabled
+    --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+    SIGNAL rst_fifo_o            : std_logic;                                             --! rst signal to first level fifos
+    SIGNAL s_edge_fall_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_falling        : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when falling edge
+    SIGNAL s_edge_rise_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_rising         : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when rising edge
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+    SIGNAL s_shutter             : std_logic;                                             --! shutter signal from TimePix, retimed onto local clock
+    SIGNAL s_triggerLogic_reset  : std_logic;
+    SIGNAL shutter_cnt_i         : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL shutter_i             : std_logic;
+    SIGNAL spill_cnt_i           : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL spill_i               : std_logic;
+    SIGNAL strobe_8x_logic      : std_logic;                                             --! Pulses one cycle every 4 of 16x clock.
+    SIGNAL strobe_4x_logic       : std_logic;                                             -- one pulse every 4 cycles of clk_4x
+    SIGNAL trigger_count         : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+    SIGNAL trigger_times         : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL triggers              : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+    SIGNAL veto_o                : std_logic;                                             --! goes high when one or more DUT are busy
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+	--My signals
+	--SIGNAL busy_toggle_o         : std_logic_vector(g_NUM_DUTS-1 downto 0);
+	
+----------------------------------------------
+----------------------------------------------
+    component DUTInterfaces
+    generic(
+	   g_NUM_DUTS : positive := 4;-- <- was 3
+	   g_IPBUS_WIDTH : positive := 32
+	   );
+    port (
+        clk_4x_logic_i          : IN     std_logic ;
+        strobe_4x_logic_i       : IN     std_logic ;                                  --! goes high every 4th clock cycle
+        trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
+        trigger_i               : IN     std_logic ;                                  --! goes high when trigger logic issues a trigger
+        reset_or_clk_to_dut_i   : IN     std_logic ;                                  --! Synchronization signal. Passed TO DUT pins
+        shutter_to_dut_i        : IN     std_logic ;                                  --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+        -- IPBus signals.
+        ipbus_clk_i             : IN     std_logic ;
+        ipbus_i                 : IN     ipb_wbus ;                                   --! Signals from IPBus core TO slave
+        ipbus_reset_i           : IN     std_logic ;
+        ipbus_o                 : OUT    ipb_rbus ;                                   --! signals from slave TO IPBus core
+        -- Signals to/from DUT
+        busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+        clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+        trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+        shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+        veto_o                  : OUT    std_logic   
+    );
+    end component DUTInterfaces;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT T0_Shutter_Iface
+    PORT (
+        clk_4x_i      : IN     std_logic;
+        clk_4x_strobe : IN     std_logic;
+        ipbus_clk_i   : IN     std_logic;
+        ipbus_i       : IN     ipb_wbus;
+        T0_o          : OUT    std_logic;
+        ipbus_o       : OUT    ipb_rbus;
+        shutter_o     : OUT    std_logic
+    );
+    END COMPONENT T0_Shutter_Iface;
+----------------------------------------------
+----------------------------------------------
+
+   COMPONENT eventBuffer
+   GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_READ_COUNTER_WIDTH : positive := 16
+   );
+   PORT (
+        clk_4x_logic_i    : IN     std_logic ;
+        data_strobe_i     : IN     std_logic ;                                     -- Indicates data TO transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic ;
+        ipbus_i           : IN     ipb_wbus ;
+        ipbus_reset_i     : IN     std_logic ;
+        strobe_4x_logic_i : IN     std_logic ;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o        : OUT    std_logic ;                                     --! rst signal TO first level fifos
+        buffer_full_o     : OUT    std_logic ;                                     --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus ;
+        logic_reset_i     : IN     std_logic                                       -- reset buffers when high. Synch withclk_4x_logic
+   );
+   END COMPONENT eventBuffer;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT eventFormatter
+    GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_COUNTER_TRIG_WIDTH : positive := 32;
+        g_COUNTER_WIDTH      : positive := 12;
+        g_EVTTYPE_WIDTH      : positive := 4;      --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    : positive := 6       --! Number of trigger inputs (POSSIBLY WRONG!)
+    );
+    PORT (
+        clk_4x_logic_i         : IN     std_logic ;                                         --! Rising edge active
+        ipbus_clk_i            : IN     std_logic ;
+        logic_strobe_i         : IN     std_logic ;                                         --! Pulses high once every 4 cycles of clk_4x_logic
+        logic_reset_i          : IN     std_logic ;                                         --! goes high TO reset counters. Synchronous with clk_4x_logic
+        rst_fifo_i             : IN     std_logic ;                                         --! Goes high TO reset FIFOs
+        buffer_full_i          : IN     std_logic ;                                         --! Goes high when output fifo full
+        trigger_i              : IN     std_logic ;                                         --! goes high TO load trigger data. One cycle of clk_4x_logic
+        trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);  --! Array of trigger times ( w.r.t. logic_strobe)
+        trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);    --! high for each input that "fired"
+        trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
+        shutter_i              : IN     std_logic ;
+        shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        spill_i                : IN     std_logic ;
+        spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when rising edge
+        edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when falling edge
+        edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        ipbus_i                : IN     ipb_wbus ;
+        ipbus_o                : OUT    ipb_rbus ;
+        data_strobe_o          : OUT    std_logic ;                                         --! goes high when data ready TO load into event buffer
+        event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        reset_timestamp_i      : IN     std_logic ;                                         --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+        reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+    );
+    END COMPONENT eventFormatter;   
+----------------------------------------------
+----------------------------------------------
+    COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerInputs_newTLU
+    GENERIC (
+        g_NUM_INPUTS  : natural  := 1;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Inputs from constant-fraction discriminators
+        --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Input from CFD
+        clk_4x_logic         : IN     std_logic ;                                        --! Rising edge active. By default = 4*40MHz = 160MHz
+        clk_200_i : IN     std_logic ;
+        strobe_4x_logic_i    : IN     std_logic ;                                        --! Pulses high once every 4 cycles of clk_4x_logic
+        threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        reset_i              : IN     std_logic ;
+        trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+        trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+        --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+        edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when rising edge. Syncronous with clk_4x_logic_i
+        edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when falling edge
+        ipbus_clk_i          : IN     std_logic ;
+        ipbus_reset_i        : IN     std_logic ;
+        ipbus_i              : IN     ipb_wbus ;                                         --! Signals from IPBus core TO slave
+        ipbus_o              : OUT    ipb_rbus ;                                         --! signals from slave TO IPBus core
+        clk_8x_logic_i      : IN     std_logic ;                                        --! 640MHz clock ( 16x 40MHz )
+        strobe_8x_logic_i   : IN     std_logic                                          --! Pulses one cycle every 4 of 8x clock.
+    );
+    END COMPONENT triggerInputs_newTLU;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerLogic
+    GENERIC (
+        g_NUM_INPUTS  : positive := 4;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        clk_4x_logic_i      : IN     std_logic ;                                   -- ! Rising edge active
+        ipbus_clk_i         : IN     std_logic ;
+        ipbus_i             : IN     ipb_wbus ;                                    -- Signals from IPBus core TO slave
+        ipbus_reset_i       : IN     std_logic ;
+        logic_reset_i       : IN     std_logic ;                                   -- active high. Synchronous with clk_4x_logic
+        logic_strobe_i      : IN     std_logic ;                                   -- ! Pulses high once every 4 cycles of clk_4x_logic
+        trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active
+        trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        veto_i              : IN     std_logic ;                                   -- ! Halts triggers when high
+        trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active and enabled
+        trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  -- starts at one. Increments for each post_veto_trigger
+        ipbus_o             : OUT    ipb_rbus ;                                    -- signals from slave TO IPBus core
+        post_veto_trigger_o : OUT    std_logic ;                                   -- ! goes high when trigger passes
+        pre_veto_trigger_o  : OUT    std_logic ;
+        trigger_active_o    : OUT    std_logic                                     --! Goes high when triggers are active ( ie. not veoted)
+    );
+    END COMPONENT triggerLogic;
+    
+    COMPONENT i2c_master
+        PORT (
+           i2c_scl_i     : IN     std_logic;
+           i2c_sda_i     : IN     std_logic;
+           ipbus_clk_i   : IN     std_logic;
+           ipbus_i       : IN     ipb_wbus;
+           ipbus_reset_i : IN     std_logic;
+           i2c_scl_enb_o : OUT    std_logic;
+           i2c_sda_enb_o : OUT    std_logic;
+           ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    
+    component clk_wiz_0
+    port
+     (-- Clock in ports
+      clk_in1           : in     std_logic;
+      -- Clock out ports
+      clk_out1          : out    std_logic;
+      -- Status and control signals
+      reset             : in     std_logic;
+      locked            : out    std_logic
+     );
+    end component;
+    
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+    --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+    FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
+    FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+    FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    FOR ALL : triggerInputs_newTLU USE ENTITY work.triggerInputs_newTLU;
+    FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+    -- pragma synthesis_on 
+      	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+    
+    
+    -- Infrastructure
+    -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+    logic_clocks_reset <= '0';
+    -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+    spill_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+    spill_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+    shutter_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+    shutter_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
+    dout1 <= '0';
+    -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
+    dout <= '0';
+    -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
+    --gpio_hdr <= dout1 & dout & s_shutter & T0_o;
+    -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+    overall_veto <= buffer_full_o OR veto_o;
+    -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
+    s_triggerLogic_reset <= logic_reset OR T0_o;
+
+    i2c_reset <= '1';
+    clk_gen_rst <= '1';
+    gpio <= strobe_8x_logic;
+    sysclk_50_o_p <= '0';
+    sysclk_50_o_n <= '0';
+    busy_o <= std_logic_vector(to_unsigned(0,    busy_o'length));
+    --busy_o <= '000000';
+    --sysclk_40_o_p <= sysclk;
+
+------------------------------------------
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => clk_encl_buf,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			clk_200_o => clk_200,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	--leds <= not ('0' & userled & inf_leds); -- Check this.
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151f"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81f"; -- 192.168.200.16+n
+
+------------------------------------------
+    I1 : entity work.ipbus_ctrlreg_v
+    port map(
+        clk => clk_ipb,
+        reset => rst_ipb,
+        ipbus_in => ipbww(N_SLV_CTRL_REG),
+        ipbus_out => ipbrr(N_SLV_CTRL_REG),
+        d => stat,
+        q => ctrl
+    );
+    stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
+    soft_rst <= ctrl(0)(0);
+    nuke <= ctrl(0)(1);
+    
+------------------------------------------
+	I2 : entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_out,
+      ipb_out => ipb_in,
+      sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
+      ipb_to_slaves => ipbww,
+      ipb_from_slaves => ipbrr
+    );
+
+------------------------------------------
+    I3 : i2c_master
+    PORT MAP (
+        i2c_scl_i     => i2c_scl_b,
+        i2c_sda_i     => i2c_sda_b,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_I2C_0),
+        ipbus_reset_i => rst_ipb,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        ipbus_o       => ipbrr(N_SLV_I2C_0)
+    );
+    
+----------------------------------------------
+    I4 : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => clk_ipb,
+        ipbus_i               => ipbww(N_SLV_LGCCLK),
+        ipbus_reset_i         => rst_ipb,
+        Reset_i               => logic_clocks_reset,
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => ipbrr(N_SLV_LGCCLK),
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => leds(3),
+        logic_reset_o         => logic_reset
+    );    
+
+----------------------------------------------
+    I5 : triggerInputs_newTLU 
+    GENERIC MAP (
+        g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+        g_IPBUS_WIDTH => 32
+    )
+    PORT MAP (
+        clk_4x_logic         => clk_4x_logic,
+        clk_200_i => clk_200,
+        strobe_4x_logic_i    => strobe_4x_logic,
+        threshold_discr_p_i  => threshold_discr_p_i,
+        threshold_discr_n_i  => threshold_discr_n_i,
+        reset_i              => logic_reset,
+        trigger_times_o      => trigger_times,
+        trigger_o            => triggers,
+        --trigger_debug_o      => OPEN,
+        edge_rising_times_o  => s_edge_rise_times,
+        edge_falling_times_o => s_edge_fall_times,
+        edge_rising_o        => s_edge_rising,
+        edge_falling_o       => s_edge_falling,
+        ipbus_clk_i          => clk_ipb,
+        ipbus_reset_i        => rst_ipb,
+        ipbus_i              => ipbww(N_SLV_TRGIN),
+        ipbus_o              => ipbrr(N_SLV_TRGIN),
+        clk_8x_logic_i      => clk_8x_logic,
+        strobe_8x_logic_i   => strobe_8x_logic
+    );
+
+------------------------------------------      
+    I6 : eventFormatter
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+        g_COUNTER_WIDTH      => 12,
+        g_EVTTYPE_WIDTH      => 4,                         --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    => g_NUM_EDGE_INPUTS,         --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    => g_NUM_TRIG_INPUTS          --! Number of trigger inputs
+    )
+    PORT MAP (
+        clk_4x_logic_i         => clk_4x_logic,
+        ipbus_clk_i            => clk_ipb,
+        logic_strobe_i         => strobe_4x_logic,
+        logic_reset_i          => logic_reset,
+        rst_fifo_i             => rst_fifo_o,
+        buffer_full_i          => buffer_full_o,
+        trigger_i              => overall_trigger,
+        trigger_times_i        => postVetoTrigger_times,
+        trigger_inputs_fired_i => postVetotrigger,
+        trigger_cnt_i          => trigger_count,
+        shutter_i              => shutter_i,
+        shutter_cnt_i          => shutter_cnt_i,
+        spill_i                => spill_i,
+        spill_cnt_i            => spill_cnt_i,
+        edge_rise_i            => s_edge_rising,
+        edge_fall_i            => s_edge_falling,
+        edge_rise_time_i       => s_edge_rise_times,
+        edge_fall_time_i       => s_edge_fall_times,
+        ipbus_i                => ipbww(N_SLV_EVFMT),
+        ipbus_o                => ipbrr(N_SLV_EVFMT),
+        data_strobe_o          => data_strobe,
+        event_data_o           => event_data,
+        reset_timestamp_i      => T0_o,
+        reset_timestamp_o      => OPEN
+    );
+
+------------------------------------------
+    I7 : eventBuffer
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_READ_COUNTER_WIDTH => 14
+        
+    )
+    PORT MAP (
+        clk_4x_logic_i    => clk_4x_logic,
+        data_strobe_i     => data_strobe,
+        event_data_i      => event_data,
+        ipbus_clk_i       => clk_ipb,
+        ipbus_i           => ipbww(N_SLV_EVBUF),
+        ipbus_reset_i     => rst_ipb,
+        strobe_4x_logic_i => strobe_4x_logic,
+        rst_fifo_o        => rst_fifo_o,
+        buffer_full_o     => buffer_full_o,
+        ipbus_o           => ipbrr(N_SLV_EVBUF),
+        logic_reset_i     => logic_reset
+    );
+    
+------------------------------------------
+    I8 : T0_Shutter_Iface
+    PORT MAP (
+        clk_4x_i      => clk_4x_logic,
+        clk_4x_strobe => strobe_4x_logic,
+        T0_o          => T0_o,
+        shutter_o     => s_shutter,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_SHUT),
+        ipbus_o       => ipbrr(N_SLV_SHUT)
+    );
+
+------------------------------------------
+    I9 : DUTInterfaces
+    GENERIC MAP (
+        g_NUM_DUTS    => g_NUM_DUTS,
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+    )
+    PORT MAP (
+         clk_4x_logic_i          => clk_4x_logic,
+         strobe_4x_logic_i       => strobe_4x_logic,
+         trigger_counter_i       => trigger_count,
+         trigger_i               => overall_trigger,
+         reset_or_clk_to_dut_i   => T0_o,
+         shutter_to_dut_i        => s_shutter,
+         ipbus_clk_i             => clk_ipb,
+         ipbus_i                 => ipbww(N_SLV_DUT),
+         ipbus_reset_i           => rst_ipb,
+         ipbus_o                 => ipbrr(N_SLV_DUT),
+         busy_from_dut       => busy_i, 
+         clk_from_dut => dut_clk_i,
+         clk_to_dut => dut_clk_o,
+         --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+         --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+         reset_to_dut => spare_o,
+         trigger_to_dut => triggers_o,
+         --shutter_to_dut_n_o      => shutter_to_dut_n_o,
+         --shutter_to_dut_p_o      => shutter_to_dut_p_o,
+         shutter_to_dut  => cont_o,
+         veto_o                  => veto_o
+    );
+    
+------------------------------------------ 
+        I10 : triggerLogic
+        GENERIC MAP (
+            g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+            g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+        PORT MAP (
+            clk_4x_logic_i      => clk_4x_logic,
+            ipbus_clk_i         => clk_ipb,
+            ipbus_i             => ipbww(N_SLV_TRGLGC),
+            ipbus_reset_i       => rst_ipb,
+            logic_reset_i       => s_triggerLogic_reset,
+            logic_strobe_i      => strobe_4x_logic,
+            trigger_i           => triggers,
+            trigger_times_i     => trigger_times,
+            veto_i              => overall_veto,
+            trigger_o           => postVetotrigger,
+            trigger_times_o     => postVetoTrigger_times,
+            event_number_o      => trigger_count,
+            ipbus_o             => ipbrr(N_SLV_TRGLGC),
+            post_veto_trigger_o => overall_trigger,
+            pre_veto_trigger_o  => OPEN,
+            trigger_active_o    => leds(2)
+        );     
+         
+-------------TEST AREA------------    
+--    test0: entity work.test_inToOut
+--    port map(
+--        clk_in => clk_200,
+--        busy_in=> busy_i,
+--        control_in=> cont_i,
+--        trig_in=> triggers_i,
+--        clkDut_in=> dut_clk_i,
+--        spare_in=> spare_i,
+--        busy_out=> busy_o,
+--        control_out=> cont_o,
+--        trig_out=> triggers_o,
+--        clkDut_out=> dut_clk_o,
+--        spare_out=> spare_o
+--    );
+
+--    dutout0: entity work.DUTs_outputs
+--    port map(
+--        clk_in => encl_clock50, 
+--        d_clk_o => dut_clk_o,
+--        d_trg_o => triggers_o,
+--        d_busy_o => busy_o,
+--        d_cont_o => cont_o,
+--        d_spare_o => spare_o
+--    );
+   
+--    clk50_o_fromEnclustra : clk_wiz_0
+--       port map ( 
+--       -- Clock in ports
+--       clk_in1 => clk_encl_buf, --sysclk_40,
+--      -- Clock out ports  
+--       clk_out1 => encl_clock50,
+--      -- Status and control signals                
+--       reset => '0',
+--       locked =>  open          
+--     );
+
+    
+----------------------------------------------
+
+
+
+
+
+
+
+
+
+
+    
+
+------------------------------------------      
+
+
+------------------------------------------
+    IBUFGDS_inst: IBUFGDS
+    generic map (
+        IBUF_LOW_PWR=> false
+    )
+    port map (
+        O => sysclk_40,
+        I => sysclk_40_i_p,
+        IB => sysclk_40_i_n
+    );
+    
+------------------------------------------
+    IBUFG_inst: IBUFG
+    port map (
+        O => clk_encl_buf,
+        I => clk_enclustra--sysclk
+    );    
+
+------------------------------------------
+-- Do not use this: we need differential 3.3 V, not available.
+--    OBUFDS_inst : OBUFDS
+--    generic map (
+--        SLEW => "FAST") -- Specify the output slew rate
+--    port map (
+--        O => sysclk_50_o_p, -- Diff_p output (connect directly to top-level port)
+--        OB => sysclk_50_o_n, -- Diff_n output (connect directly to top-level port)
+--        I => encl_clock50 -- Buffer input
+--    );
+    -- This might not work: these are just two single ended. If we remove R coupling maybe?
+    --sysclk_50_o_p <= encl_clock50;
+    --sysclk_50_o_n <= not encl_clock50;
+
+      
+
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4443faf09d8ea7b4404309f8a38526f389ade458
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl.vhd
@@ -0,0 +1,291 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    -- Instantiate one for each trigger input of the TLU
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        -- Differential buffer. Receives differential trigger input and produces a buffered differential signal.
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+        
+        -- Deserialize the trigger input    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            --data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+        
+        -- Add last bit from previous word to the new deserialized data.        
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        -- Use a LUT to determine the leading/trailing edges of the trigger input
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..106e7703ceb450d9081a1a68b86aafbc3ec4aa01
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_BKP.vhd
@@ -0,0 +1,335 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            data_i_pos     => threshold_discr_p_i(triggerInput),
+            data_i_neg     => threshold_discr_n_i(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+--REMOVE CFD        
+--        CFDInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_CFD_discr_input(triggerInput),
+--            I  => CFD_discr_p_i(triggerInput),
+--            IB => CFD_discr_n_i(triggerInput)
+--            );
+    
+--        CFDDeserializer: entity work.dualSERDES_1to4
+--          port map (
+--            reset_i => s_rst_iserdes,
+--            --calibrate_i => s_calibrate_idelay,
+--            data_i         => s_CFD_discr_input(triggerInput),
+--            fastClk_i      => clk_16x_logic_i,
+--            fabricClk_i    => clk_4x_logic,
+--            strobe_i       => strobe_16x_logic_i,
+--            data_o         => s_deserialized_CFD_data(triggerInput),
+--            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+--            );
+--        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+--        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+--        CFDLUT : entity work.arrivalTimeLUT
+--          port map (
+--            clk_4x_logic_i      => clk_4x_logic,
+--            strobe_4x_logic_i   => strobe_4x_logic_i,
+--            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+--            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+--            last_falling_edge_time_o => open, 
+--            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+--            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+--            multiple_edges_o    => open
+--            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              
+            --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_fastClock.vhd b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_fastClock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9e3a01e19f1004dfd39bad1c31b25d478a4091df
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_newTLU_rtl_fastClock.vhd
@@ -0,0 +1,301 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+    --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+--        thresholdInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_threshold_discr_input(triggerInput),
+--            I  => threshold_discr_p_i(triggerInput),
+--            IB => threshold_discr_n_i(triggerInput)
+--            );
+    
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+            
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+                  
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+            
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3d83e3d60baa144ef7e6b9a53cd86f97a08dfafd
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/triggerInputs_rtl.vhd
@@ -0,0 +1,338 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs ;
+
+--
+ARCHITECTURE rtl OF triggerInputs IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+          --s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+        
+        CFDInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_CFD_discr_input(triggerInput),
+            I  => CFD_discr_p_i(triggerInput),
+            IB => CFD_discr_n_i(triggerInput)
+            );
+    
+        CFDDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i => s_rst_iserdes,
+            --calibrate_i => s_calibrate_idelay,
+            data_i         => s_CFD_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_CFD_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+            );
+        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+        CFDLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+            last_falling_edge_time_o => open, 
+            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              --s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
+            s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+  --! Monitor output of deserializer
+  -- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_status_to_ipbus(0)(23 downto 20);
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <=  s_edge_rising;
+  trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/common/triggerLogic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/common/triggerLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ff175d3ccf6b58d7699686491eb531962146051
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/common/triggerLogic_rtl.vhd
@@ -0,0 +1,355 @@
+--=============================================================================
+--! @file triggerLogic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+--! @brief Produces triggers from either trigger inputs or internal generator
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 16:06:19 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \br IPBus address map:
+--! \li 0x00000000 RO - Number of triggers issued since last reset.
+--! \li 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
+--! \li 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
+--! \li 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
+--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set high to halt triggers.
+--! \li 0x00000101 RO - state of external veto
+--! \li 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
+--! \li 0x00000111 RW - delay of pulses. 0-31 clock cycles.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+--! Add stretchPulse and coincidenceLogic entities. May/15 , David Cussans
+-------------------------------------------------------------------------------
+ENTITY triggerLogic IS
+   GENERIC( 
+      g_NUM_INPUTS  : positive := 4; 
+      g_IPBUS_WIDTH : positive := 32 
+   );
+   PORT( 
+      clk_4x_logic_i      : IN     std_logic;                                     -- ! Rising edge active
+      ipbus_clk_i         : IN     std_logic;
+      ipbus_i             : IN     ipb_wbus;                                      -- Signals from IPBus core to slave
+      ipbus_reset_i       : IN     std_logic;
+      logic_reset_i       : IN     std_logic;                                     -- active high. Synchronous with clk_4x_logic
+      logic_strobe_i      : IN     std_logic;                                     -- ! Pulses high once every 4 cycles of clk_4x_logic
+      trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active
+      trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      veto_i              : IN     std_logic;                                     -- ! Halts triggers when high
+      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active and enabled
+      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);   -- starts at one. Increments for each post_veto_trigger
+      ipbus_o             : OUT    ipb_rbus;                                      -- signals from slave to IPBus core
+      post_veto_trigger_o : OUT    std_logic;                                     -- ! goes high when trigger passes
+      pre_veto_trigger_o  : OUT    std_logic;
+      trigger_active_o    : OUT    std_logic                                      --! Goes high when triggers are active ( ie. not veoted)
+   );
+
+-- Declarations
+
+END triggerLogic ;
+
+--
+ARCHITECTURE rtl OF triggerLogic IS
+
+    --! vector that stores trigger output for each combination of trigger inputs.
+    signal s_trigger_inputs_enabled , s_trigger_inputs_enabled_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := x"00000001";--(others=>'1');  
+    signal s_external_trigger_p , s_external_trigger_l , s_auxTrigger , s_internal_veto , s_internal_veto_ipb : std_logic := '0';
+    signal s_internal_trigger_interval: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- setting s_internal_trigger_interval to zero means no internal triggers
+    signal s_pre_veto_trigger_counter , s_post_veto_trigger_counter , s_aux_trigger_counter: unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto
+    signal s_pre_veto_trigger_counter_ipb , s_post_veto_trigger_counter_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto, on ipbus clock domain
+    
+    signal s_triggers : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) := (others=>'0');
+    signal s_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) := (others=>(others=>'0'));
+    signal s_internal_trigger, s_internal_trigger_d : std_logic := '0';  -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
+    --  signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation
+    signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation and counter delay
+    signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0';  -- ! Goes high when internal trigger is running.
+    
+    --  signal s_logic_reset ,  s_logic_reset_ipb : std_logic := '0';  -- ! Take high to reset counters etc.
+    signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0';  -- ! Can't read from an output port so keep internal copy
+    
+    signal s_TriggerPattern_low : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (low 32-bits)
+    signal s_TriggerPattern_high : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (high 32-bits)
+    
+    signal s_PulseStretchWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseWidthWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseDelayWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --!number of cycles to delay trigger pulses.
+    signal s_TriggerHoldOffWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! minimum number of clock cycles between triggers
+    
+    constant c_PARAM_WIDTH : positive := 5;    -- length of pulse width and delay.
+    constant c_BYTE_WIDTH : positive := 5;    --Length of padded field for parameters. This should be at least equal to c_PARAM_WIDTH.
+                                              --If c_BYTE_WIDTH= 8 then the values are aligned to bytes in the 32-bit word (but we cannot store 6 of them...)
+                                              --If c_BYTE_WIDTH=5 then all the values are one after the other.
+    
+    constant c_N_CTRL : positive := 16;
+    constant c_N_STAT : positive := 16;
+    signal s_controlRegStrobes : std_logic_vector(c_N_CTRL-1 downto 0) := ( others => '0') ; --!
+                                                                             --Bit strobes when control reg is loaded
+    signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+    signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_loadTriggerPattern , s_loadTriggerPattern_p1 : std_logic := '0';  -- take high to load trigger pattern
+    signal s_loadTriggerPatternHi , s_loadTriggerPatternHi_p1 : std_logic := '0';  -- take high to load trigger pattern
+    
+    signal s_delayedTriggerTimes, s_delayedTriggerTimes_d1, s_delayedTriggerTimes_d2 : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! Array of std_logic_vectors
+    signal s_stretchedTriggers ,  s_stretchedTriggers_d1 ,  s_stretchedTriggers_d2 : std_logic_vector( trigger_i'range) := (others => '0');  -- --! Triggers after stretch and delay
+    
+    COMPONENT internalTriggerGenerator
+    PORT (
+        CLK : IN STD_LOGIC;
+        CE : IN STD_LOGIC;
+        LOAD : IN STD_LOGIC;
+        L : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    END COMPONENT;
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+        N_CTRL => c_N_CTRL,
+        N_STAT => c_N_STAT
+    )
+    port map(
+        clk => ipbus_clk_i,
+        reset=> '0',--ipbus_reset_i ,
+        ipbus_in=>  ipbus_i,
+        ipbus_out=> ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb=> s_controlRegStrobes
+    );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic_i,
+        data_i      =>  s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      =>  s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  -- workaround to match the number of clock cycles with the configured interval
+    s_internal_trigger_interval <= x"00000000" when s_sync_control_from_ipbus(2)<x"00000005" else
+										std_logic_vector(unsigned(s_sync_control_from_ipbus(2))-2);
+										
+    --s_TriggerPattern_low <= s_control_from_ipbus(3);
+    s_LoadTriggerPattern_p1 <= s_controlRegStrobes(10);
+    s_LoadTriggerPatternHi_p1 <= s_controlRegStrobes(11);
+    s_veto_word <= s_sync_control_from_ipbus(4);
+    s_internal_veto <= s_veto_word(0);
+    s_PulseWidthWord <= s_sync_control_from_ipbus(6);
+    s_PulseDelayWord <= s_sync_control_from_ipbus(7);
+    s_TriggerHoldOffWord <= s_sync_control_from_ipbus(8);
+    s_TriggerPattern_low <= s_control_from_ipbus(10);
+    s_TriggerPattern_high <= s_control_from_ipbus(11);
+    --s_PulseWidthWord <=s_sync_control_from_ipbus(10);
+    
+    s_external_veto_word(0) <= veto_i;
+    s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
+    
+    -- Map the status registers
+    s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
+    s_status_to_ipbus(1) <= std_logic_vector(s_pre_veto_trigger_counter);
+    s_status_to_ipbus(2) <= s_internal_trigger_interval;
+    --s_status_to_ipbus(3) <= s_TriggerPattern_low;
+    s_status_to_ipbus(4) <= s_veto_word;
+    s_status_to_ipbus(5) <= s_external_veto_word;
+    s_status_to_ipbus(6) <= s_PulseWidthWord; 
+    s_status_to_ipbus(7) <= s_PulseDelayWord; --fixed in addr. map
+    s_status_to_ipbus(8) <= s_TriggerHoldOffWord;
+    s_status_to_ipbus(9) <= std_logic_vector(s_aux_trigger_counter);-- not used and never updated. Remove at some point.
+    s_status_to_ipbus(10) <= s_TriggerPattern_low;
+    s_status_to_ipbus(11) <= s_TriggerPattern_high;
+
+    -- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
+    -- type   : combinational
+    -- inputs : ipbus_clk_i
+    -- outputs: 
+    p_delayLoadPulse: process (ipbus_clk_i) is
+    begin  -- process p_delayLoadPulse
+    if rising_edge(ipbus_clk_i) then
+        s_LoadTriggerPattern <= s_LoadTriggerPattern_p1;
+        s_LoadTriggerPatternHi <= s_LoadTriggerPatternHi_p1;
+    end if;
+    end process p_delayLoadPulse;
+
+  -- Stretch and delay pulses.
+  --D Put in delay for trigger times as well.
+  
+    --
+    gen_stretchVals: for v_inputNumber in 0 to g_NUM_INPUTS-1 generate
+        cmp_stretchPulse: entity work.stretchPulse
+        generic map (
+            g_PARAM_WIDTH => c_PARAM_WIDTH)
+        port map (
+            clk_i         => clk_4x_logic_i,
+            pulse_i       => trigger_i(v_inputNumber),
+            pulse_o       => s_stretchedTriggers(v_inputNumber),
+            triggerTime_i => trigger_times_i(v_inputNumber),
+            triggerTime_o => s_delayedTriggerTimes(v_inputNumber),
+    --        pulsewidth_i  => s_PulseStretchWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulsewidth_i  => s_PulseWidthWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulseDelay_i  => s_PulseDelayWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH )
+    --        pulsewidth_i  => s_PulseStretchWord( (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH ),
+    --        pulseDelay_i  => s_PulseDelayWord(   (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH )
+            );
+    end generate gen_stretchVals;
+
+  --! Trigger coincidence logic 
+    cmp_coincidence_logic : entity work.coincidenceLogic
+    generic map(
+        g_nInputs	=> g_NUM_INPUTS,
+        g_patternWidth => g_IPBUS_WIDTH
+    )
+    Port map( 
+        configClk_i 	=> ipbus_clk_i, --! No point in moving off IPBus clock
+        logicClk_i        => clk_4x_logic_i,
+        triggers_i 	=> s_stretchedTriggers,
+        trigger_o         => s_external_trigger_l,
+        --auxTrigger_o      => s_auxTrigger,
+        -- Control ports...
+        triggerPattern_low_i  => s_TriggerPattern_low,
+        triggerPattern_high_i  => s_TriggerPattern_high,
+        loadPatternHi_i     => s_loadTriggerPatternHi,
+        loadPatternLo_i     => s_loadTriggerPattern
+        );
+	
+  --! just look for the rising edge ( with long stretch can get multiple clock
+  --! cycle triggers )
+    cmp_triggerRisingEdge : entity work.single_pulse
+    port map (
+        level => s_external_trigger_l,
+        clk => clk_4x_logic_i,
+        pulse => s_external_trigger_p
+        );
+  
+  --! Produce triggers....
+    trigGen : process  ( clk_4x_logic_i ) 
+    begin 
+        if rising_edge(clk_4x_logic_i)  then 
+            s_post_veto_trigger <= (s_external_trigger_p or s_internal_trigger) and (not ( s_internal_veto or veto_i) );
+            s_pre_veto_trigger <= (s_external_trigger_p or s_internal_trigger);
+    
+            -- delay output of which input triggers fired so that they go high at the
+            -- same time as the pre/post veto trigger signals.
+            s_stretchedTriggers_d1 <= s_stretchedTriggers;
+            s_stretchedTriggers_d2 <= s_stretchedTriggers_d1;
+                                                            
+            s_delayedTriggerTimes_d1 <= s_delayedTriggerTimes;
+            s_delayedTriggerTimes_d2 <= s_delayedTriggerTimes_d1;
+             
+            trigger_o <= s_stretchedTriggers_d2;
+            trigger_times_o <= s_delayedTriggerTimes_d2; -- trigger_times_i;  -- put delayed version of trigger times here
+        end if;
+    end process;
+	
+
+    pre_veto_trigger_o <= s_pre_veto_trigger ;
+    post_veto_trigger_o <= s_post_veto_trigger;
+    trigger_active_o <= s_post_veto_trigger;
+
+	
+	--! Internal trigger generator
+    p_internal_triggers: process (clk_4x_logic_i )
+    begin  -- process p_internal_triggers
+        if rising_edge(clk_4x_logic_i) then
+            if (s_internal_trigger_interval = x"00000000") then
+                s_internal_trigger_active <= '0';
+            else
+                s_internal_trigger_active <= '1';
+            end if;
+        
+            s_internal_trigger_active_d <= s_internal_trigger_active;    -- signal delayed
+            s_internal_trigger_timer_d <= s_internal_trigger_timer;      -- Signal delayed
+        end if;
+    end process p_internal_triggers;
+  
+    s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" )) else '0';
+				
+				
+				
+    -- Use a coregen counter to allow timing constraints to be met.
+    --c_internal_triggers: entity work.internalTriggerGenerator
+    c_internal_triggers: internalTriggerGenerator
+    PORT MAP (
+        clk => clk_4x_logic_i,
+        ce => s_internal_trigger_active,
+        load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
+        l => s_internal_trigger_interval,
+        q => s_internal_trigger_timer
+    );
+  
+  -----------------------------------------------------------------------------
+  -- Count triggers
+  -----------------------------------------------------------------------------
+    p_trigger_counter: process (clk_4x_logic_i )
+    begin  -- process p_trigger_counter
+        if rising_edge(clk_4x_logic_i) then
+            if logic_reset_i = '1' then
+                s_post_veto_trigger_counter <= ( others => '0');
+            elsif s_post_veto_trigger = '1' then
+                s_post_veto_trigger_counter <= s_post_veto_trigger_counter + 1;
+            end if;
+            
+            if logic_reset_i = '1' then
+                s_pre_veto_trigger_counter <= ( others => '0');
+            elsif s_pre_veto_trigger = '1' then
+                s_pre_veto_trigger_counter <= s_pre_veto_trigger_counter + 1;
+            end if;
+            
+            --if logic_reset_i = '1' then
+            --    s_aux_trigger_counter <= ( others => '0');
+            --elsif s_auxTrigger = '1' then
+            --    s_aux_trigger_counter <= s_aux_trigger_counter + 1;
+            --end if;
+        end if;
+    end process p_trigger_counter;
+ 
+    event_number_o <= std_logic_vector(s_post_veto_trigger_counter);
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_23ns.txt b/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_23ns.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7d050b429780e1400749f8ec90a6b009c11b5619
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_23ns.txt
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diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_24ns.txt b/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_24ns.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c6f9734c1fc3f4b1c087f6d1be0c50abad0b542f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/500ns_24ns.txt
@@ -0,0 +1,665 @@
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diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/AIDA_testScript.py b/AIDA_tlu/legacy/TLU_v1c/scripts/AIDA_testScript.py
new file mode 100644
index 0000000000000000000000000000000000000000..4b8f505554c9b9bbab411b280e33957c37ac9390
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/AIDA_testScript.py
@@ -0,0 +1,183 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0B]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL: 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS: 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0xFF)# 0= normal
+IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(0, 0xFF)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x0F)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/TLU.py b/AIDA_tlu/legacy/TLU_v1c/scripts/TLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..c9398feb35980e1d20ff9449061de2a835a7cf0e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/TLU.py
@@ -0,0 +1,748 @@
+# -*- coding: utf-8 -*-
+import uhal;
+import pprint;
+from FmcTluI2c import *
+from I2CuHal import I2CCore
+from si5345 import si5345 # Library for clock chip
+from AD5665R import AD5665R # Library for DAC
+from PCA9539PW import PCA9539PW # Library for serial line expander
+
+class TLU:
+    """docstring for TLU"""
+    def __init__(self, dev_name, man_file):
+        self.dev_name = dev_name
+        self.manager= uhal.ConnectionManager(man_file)
+        self.hw = self.manager.getDevice(self.dev_name)
+        self.nDUTs= 4 #Number of DUT connectors
+        self.nChannels= 6 #Number of trigger inputs
+        self.VrefInt= 2.5 #Internal DAC voltage reference
+        self.VrefExt= 1.3 #External DAC voltage reference
+        self.intRefOn= False #Internal reference is OFF by default
+
+        self.fwVersion = self.hw.getNode("version").read()
+        self.hw.dispatch()
+        print "TLU FIRMWARE VERSION= " , hex(self.fwVersion)
+
+        # Instantiate a I2C core to configure components
+        self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
+        #self.TLU_I2C.state()
+
+        enableCore= True #Only need to run this once, after power-up
+        self.enableCore()
+
+        # Instantiate clock chip
+        self.zeClock=si5345(self.TLU_I2C, 0x68)
+        res= self.zeClock.getDeviceVersion()
+        self.zeClock.checkDesignID()
+
+        # Instantiate DACs and configure them to use reference based on TLU setting
+        self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
+        self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
+        self.zeDAC1.setIntRef(self.intRefOn)
+        self.zeDAC2.setIntRef(self.intRefOn)
+
+        # Instantiate the serial line expanders and configure them to default values
+        self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
+        self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(0, 0xFF)# 0= output, 1= input
+        self.IC6.setOutputs(0, 0xFF)# If output, set to 1
+        self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(1, 0xFF)# 0= output, 1= input
+        self.IC6.setOutputs(1, 0xFF)# If output, set to 1
+
+        self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
+        self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(0, 0xFF)# 0= output, 1= input
+        self.IC7.setOutputs(0, 0xFF)# If output, set to 1
+        self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(1, 0xFF)# 0= output, 1= input
+        self.IC7.setOutputs(1, 0xFF)# If output, set to 1
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def DUTOutputs(self, dutN, enable=False, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "to", enable
+        if verbose:
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getIOReg(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newStatus= oldStatus & (~mask)
+        if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
+            newStatus |= mask
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC6.setIOReg(bank, newStatus)
+        return newStatus
+
+    def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
+        ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
+        ## clkSrc= 0: clock disabled
+        ## clkSrc= 1: clock from Si5345
+        ## clkSrc=2: clock from FPGA
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        if (clkSrc < 0) | (clkSrc> 2):
+            print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
+            return -1
+        bank=0
+        maskLow= 1 << (1* dutN) #CLK FROM FPGA
+        maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
+        mask= maskLow | maskHigh
+        res= self.IC7.getIOReg(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask #set both bits to zero
+        outStat= ""
+        if clkSrc==0:
+            newStatus = newStatus | mask
+            outStat= "disabled"
+        elif clkSrc==1:
+            newStatus = newStatus | maskLow
+            outStat= "Si5435"
+        elif clkSrc==2:
+            newStatus= newStatus | maskHigh
+            outStat= "FPGA"
+        print "  Setting DUT:", dutN, "clock source to", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setIOReg(bank, newStatus)
+        return newStatus
+
+    def enableClkLEMO(self, enable= False, verbose= False):
+        ## Enable or disable the output clock to the differential LEMO output
+        bank=1
+        mask= 0x10
+        res= self.IC7.getIOReg(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask
+        outStat= "enabled"
+        if (not enable): #A 0 activates the output. A 1 disables it.
+            newStatus= newStatus | mask
+            outStat= "disabled"
+        print "  Clk LEMO", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setIOReg(bank, newStatus)
+        return newStatus
+
+    def enableCore(self):
+        ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
+        ## This function enables the lines. It is only required once.
+        mystop=True
+        print "  Enabling I2C bus (expect 127):"
+        myslave= 0x21
+        mycmd= [0x01, 0x7F]
+        nwords= 1
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+
+        mystop=False
+        mycmd= [0x01]
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tPost RegDir: ", res
+
+    def getAllChannelsCounts(self):
+        chCounts=[]
+        for ch in range (0,self.nChannels):
+            chCounts.append(int(self.getChCount(ch)))
+        return chCounts
+
+    def getChStatus(self):
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\tInput status= " , hex(inputStatus)
+        return inputStatus
+
+    def getChCount(self, channel):
+        regString= "triggerInputs.ThrCount"+ str(channel)+"R"
+        count = self.hw.getNode(regString).read()
+        self.hw.dispatch()
+        print "\tCh", channel, "Count:" , count
+        return count
+
+    def getClockStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "  CLOCK STATUS [expected 1]"
+        print "\t", hex(clockStatus)
+        if ( clockStatus == 0 ):
+            "ERROR: Clocks in TLU FPGA are not locked."
+        return clockStatus
+
+    def getDUTmask(self):
+        DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
+        self.hw.dispatch()
+        print "\tDUTMask read back as:" , hex(DUTMaskR)
+        return DUTMaskR
+
+    def getExternalVeto(self):
+        extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tEXTERNAL Veto read back as:", hex(extVeto)
+        return extVeto
+
+    def getFifoData(self, nWords):
+    	#fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
+    	fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
+    	self.hw.dispatch()
+    	#print "\tFIFO Data:", hex(fifoData)
+    	return fifoData
+
+    def getFifoLevel(self):
+        FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
+        self.hw.dispatch()
+        print "\tFIFO level read back as:", hex(FifoFill)
+        return FifoFill
+
+    def getFifoCSR(self):
+        FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
+        self.hw.dispatch()
+        print "\tFIFO CSR read back as:", hex(FifoCSR)
+        return FifoCSR
+
+    def getInternalTrg(self):
+        trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\tTrigger frequency read back as:", trigIntervalR, "Hz"
+        return trigIntervalR
+
+    def getMode(self):
+        DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
+        self.hw.dispatch()
+        print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
+        return DUTInterfaceModeR
+
+    def getModeModifier(self):
+        DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
+        self.hw.dispatch()
+        print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
+        return DUTInterfaceModeModifierR
+
+    def getSN(self):
+        epromcontent=self.readEEPROM(0xfa, 6)
+        print "  FMC-TLU serial number (EEPROM):"
+        result="\t"
+        for iaddr in epromcontent:
+            result+="%02x "%(iaddr)
+        print result
+        return epromcontent
+
+    def getPostVetoTrg(self):
+        triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
+        self.hw.dispatch()
+        print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
+        return triggerN
+
+    def getPulseDelay(self):
+        pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
+        self.hw.dispatch()
+        print "\tPulse delay read back as:", hex(pulseDelayR)
+        return pulseDelayR
+
+    def getPulseStretch(self):
+        pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
+        self.hw.dispatch()
+        print "\tPulse stretch read back as:", hex(pulseStretchR)
+        return pulseStretchR
+
+    def getRecordDataStatus(self):
+        RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
+        self.hw.dispatch()
+        print "\tData recording:", RecordStatus
+        return RecordStatus
+
+    def getTriggerVetoStatus(self):
+        trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tTrigger veto status read back as:", trgVetoStatus
+        return trgVetoStatus
+
+    def getTrgPattern(self):
+        triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
+        triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
+        self.hw.dispatch()
+        print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
+        return triggerPattern_low, triggerPattern_high
+
+    def getVetoDUT(self):
+        IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
+        self.hw.dispatch()
+        print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
+        return IgnoreDUTBusyR
+
+    def getVetoShutters(self):
+        IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
+        self.hw.dispatch()
+        print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
+        return IgnoreShutterVeto
+
+    def pulseT0(self):
+        cmd = int("0x1",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tPulsing T0"
+
+    def readEEPROM(self, startadd, bytes):
+        mystop= 1
+        time.sleep(0.1)
+        myaddr= [startadd]#0xfa
+        self.TLU_I2C.write( 0x50, [startadd], mystop)
+        res= self.TLU_I2C.read( 0x50, bytes)
+        return res
+
+    def resetClock(self):
+        # Set the RST pin from the PLL to 1
+        print "  Clocks reset"
+        cmd = int("0x1",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def resetClocks(self):
+        #Reset clock PLL
+        self.resetClock()
+        #Get clock status after reset
+        self.getClockStatus()
+        #Restore clock PLL
+        self.restoreClock()
+        #Get clock status after restore
+        self.getClockStatus()
+        #Get serdes status
+        self.getChStatus()
+
+    def resetCounters(self):
+    	cmd = int("0x2", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	cmd = int("0x0", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	#print "Trigger Reset: 0x%X" % restatus
+    	print "\tTrigger counters reset"
+
+    def resetSerdes(self):
+        cmd = int("0x3",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during reset = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after reset = " , hex(inputStatus)
+
+        cmd = int("0x4",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during calibration = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after calibration = " , hex(inputStatus)
+
+    def restoreClock(self):
+        # Set the RST pin from the PLL to 0
+        print "  Clocks restore"
+        cmd = int("0x0",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def setChStatus(self, cmd):
+        self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "  INPUT STATUS SET TO= " , hex(inputStatus)
+
+    def setClockStatus(self, cmd):
+        # Only use this for testing. The clock source is actually selected in the Si5345.
+        self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
+        self.hw.dispatch()
+
+    def setDUTmask(self, DUTMask):
+        print "  DUT MASK ENABLING: Mask= " , hex(DUTMask)
+        self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
+        self.hw.dispatch()
+        self.getDUTmask()
+
+    def setFifoCSR(self, cmd):
+        self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
+        self.hw.dispatch()
+        self.getFifoCSR()
+
+    def setInternalTrg(self, triggerInterval):
+        print "  TRIGGERS INTERNAL:"
+        if triggerInterval == 0:
+            internalTriggerFreq = 0
+            print "\tdisabled"
+        else:
+            internalTriggerFreq = 160000.0/triggerInterval
+            print "\t  Setting:", internalTriggerFreq, "Hz"
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
+        self.hw.dispatch()
+        self.getInternalTrg()
+
+    def setMode(self, mode):
+        print "  DUT MODE SET TO: ", hex(mode)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
+        self.hw.dispatch()
+        self.getMode()
+
+    def setModeModifier(self, modifier):
+        print "  DUT MODE MODIFIER:", hex(modifier)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
+        self.hw.dispatch()
+        self.getModeModifier()
+
+    def setPulseDelay(self, pulseDelay):
+        print "  TRIGGER DELAY SET TO", hex(pulseDelay), "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
+        self.hw.dispatch()
+        self.getPulseDelay()
+
+    def setPulseStretch(self, pulseStretch):
+        print "  INPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
+        self.hw.dispatch()
+        self.getPulseStretch()
+
+    def setRecordDataStatus(self, status=False):
+        print "  Data recording set:"
+        self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
+        self.hw.dispatch()
+        self.getRecordDataStatus()
+
+    def setTriggerVetoStatus(self, status=False):
+        self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
+        self.hw.dispatch()
+        self.getTriggerVetoStatus()
+
+    def setTrgPattern(self, triggerPatternH, triggerPatternL):
+        triggerPatternL &= 0xffffffff
+        triggerPatternH &= 0xffffffff
+        print "  TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
+        self.hw.dispatch()
+        self.getTrgPattern()
+
+    def setVetoDUT(self, ignoreDUTBusy):
+        print "  VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
+        self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
+        self.hw.dispatch()
+        self.getVetoDUT()
+
+    def setVetoShutters(self, newState):
+        if newState:
+            print "  IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
+            cmd= int("0x0",16)
+        else:
+            print "  IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
+            cmd= int("0x1",16)
+        self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
+        self.hw.dispatch()
+        self.getVetoShutters()
+
+    def writeThreshold(self, DACtarget, Vtarget, channel):
+        #Writes the threshold. The DAC voltage differs from the threshold voltage because
+        #the range is shifted to be symmetrical around 0V.
+
+        #Check if the DACs are using the internal reference
+        if (self.intRefOn):
+            Vref= self.VrefInt
+        else:
+            Vref= self.VrefExt
+
+        #Calculate offset voltage (because of the following shifter)
+        Vdac= ( Vtarget + Vref ) / 2
+        print"  THRESHOLD setting:"
+        if channel==7:
+            print "\tCH: ALL"
+        else:
+            print "\tCH:", channel
+        print "\tTarget V:", Vtarget
+        dacValue = 0xFFFF * (Vdac / Vref)
+        DACtarget.writeDAC(int(dacValue), channel, True)
+
+    def parseFifoData(self, fifoData, nEvents, verbose):
+        #for index in range(0, len(fifoData)-1, 6):
+        outList= []
+        for index in range(0, (nEvents)*6, 6):
+            word0= (fifoData[index] << 32) + fifoData[index + 1]
+            word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
+            word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
+            evType= (fifoData[index] & 0xF0000000) >> 28
+            inTrig= (fifoData[index] & 0x0FFF0000) >> 16
+            tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
+            fineTs= fifoData[index + 2]
+            evNum= fifoData[index + 3]
+            fineTsList=[-1]*12
+            fineTsList[3]= (fineTs & 0x000000FF)
+            fineTsList[2]= (fineTs & 0x0000FF00) >> 8
+            fineTsList[1]= (fineTs & 0x00FF0000) >> 16
+            fineTsList[0]= (fineTs & 0xFF000000) >> 24
+            fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
+            fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
+            fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
+            fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
+            fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
+            fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
+            fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
+            fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
+            if verbose:
+                print "====== EVENT", evNum, "================================================="
+                print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
+                print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
+                print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
+                print fineTsList
+            fineTsList.insert(0, tStamp)
+            fineTsList.insert(0, evNum)
+            #print fineTsList
+            outList.insert(len(outList), fineTsList)
+        printdata= False
+        if (printdata):
+            print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
+            print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
+            pprint.pprint(outList)
+        return outList
+
+    def plotFifoData(self, outList):
+        import matplotlib.pyplot as plt
+        import numpy as np
+        import matplotlib.mlab as mlab
+
+        coarseColumn= [row[1] for row in outList]
+        fineColumn= [row[2] for row in outList]
+        timeStamp= [sum(x) for x in zip(coarseColumn, fineColumn)]
+        correctTs= [-1]*len(coarseColumn)
+        coarseVal= 0.000000025 #coarse time value (40 Mhz, 25 ns)
+        fineVal=   0.00000000078125 #fine time value (1280 MHz, 0.78125 ns)
+        for iTs in range(0, len(coarseColumn)):
+            correctTs[iTs]= coarseColumn[iTs]*coarseVal + fineColumn[iTs]*fineVal
+            #if iTs:
+                #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
+
+        xdiff = np.diff(correctTs)
+        np.all(xdiff[0] == xdiff)
+        P= 1000000000 #display in ns
+        nsDeltas = [x * P for x in xdiff]
+        #centerRange= np.mean(nsDeltas)
+        centerRange= 476
+        windowsns= 30
+        minRange= centerRange-windowsns
+        maxRange= centerRange+windowsns
+
+        #Divide figure in two axes
+        plt.subplot(311)
+
+        #Create first histogram
+        plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+        #plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+        #plt.xlim((min(nsDeltas), max(nsDeltas)))
+        plt.xlabel('Time (ns)')
+        plt.ylabel('Entries')
+        plt.title('Histogram DeltaTime')
+        plt.grid(True)
+
+        #Superimpose Gauss to first plot
+        mean = np.mean(nsDeltas)
+        variance = np.var(nsDeltas)
+        sigma = np.sqrt(variance)
+        x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+        plt.plot(x, mlab.normpdf(x, mean, sigma))
+
+        MSBTs= [-1]*len(fineColumn)
+        LSBTs= [-1]*len(fineColumn)
+        for iTs in range(0, len(fineColumn)):
+            MSBTs[iTs]= fineColumn[iTs] & 0b11000
+            LSBTs[iTs]= fineColumn[iTs] & 0b00111
+            #if iTs:
+                #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
+
+        #Second plot
+        plt.subplot(312)
+        plt.xlabel('Clock sample')
+        plt.ylabel('Entries')
+        plt.title('Histogram Fine Time Stamp (2 MSB)')
+        plt.grid(True)
+        plt.hist(MSBTs, 100, normed=False, facecolor='blue', align='mid', alpha=0.75)
+
+        #Third plot
+        plt.subplot(313)
+        plt.xlabel('Clock sample')
+        plt.ylabel('Entries')
+        plt.title('Histogram Fine Time Stamp (3 LSB)')
+        plt.grid(True)
+        plt.hist(LSBTs, 100, normed=False, facecolor='blue', align='mid', alpha=0.75)
+
+        #Display plot
+        plt.show()
+
+
+    def saveFifoData(self, outList):
+        import csv
+        with open("output.csv", "wb") as f:
+            writer = csv.writer(f)
+            writer.writerows(outList)
+
+
+##################################################################################################################################
+##################################################################################################################################
+
+    def initialize(self):
+        print "\nTLU INITIALIZING..."
+
+        # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
+
+        #READ CONTENT OF EPROM VIA I2C
+        self.getSN()
+
+        print "  Turning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        #
+        # #SET DACs
+        targetV= -0.12
+        DACchannel= 7
+        self.writeThreshold(self.zeDAC1, targetV, DACchannel, )
+        self.writeThreshold(self.zeDAC2, targetV, DACchannel, )
+
+        #
+        # #ENABLE/DISABLE HDMI OUTPUTS
+        self.DUTOutputs(0, True, False)
+        self.DUTOutputs(1, True, False)
+        self.DUTOutputs(2, True, False)
+        self.DUTOutputs(3, True, False)
+
+        ## ENABLE/DISABLE LEMO CLOCK OUTPUT
+        self.enableClkLEMO(True, False)
+
+        #
+        # #Check clock status
+        self.getClockStatus()
+
+        resetClocks = 0
+        resetSerdes = 0
+        resetCounters= 0
+        if resetClocks:
+            self.resetClocks()
+            self.getClockStatus()
+        if resetSerdes:
+            self.resetSerdes()
+        if resetCounters:
+	    self.resetCounters()
+
+        # # Get inputs status and counters
+        self.getChStatus()
+        self.getAllChannelsCounts()
+        #
+        # # Stop internal triggers until setup complete
+        cmd = int("0x0",16)
+        self.setInternalTrg(cmd)
+        #
+        # # Set pulse stretch
+        pulseStretch= 0x00000000
+        self.setPulseStretch(pulseStretch)
+        #
+        # # Set pulse delay
+        pulseDelay= 0x00
+        self.setPulseDelay(pulseDelay)
+
+        # # Set trigger pattern
+        #triggerPattern_low= 0xFFFEFFFE
+        #triggerPattern_high= 0xFFFFFFFF
+        triggerPattern_low= 0x00010102
+        triggerPattern_low= 0x00000002
+        triggerPattern_high= 0x00000000
+        self.setTrgPattern(triggerPattern_high, triggerPattern_low)
+
+        # # Set DUTs
+        DUTMask= 0xF
+        self.setDUTmask(DUTMask)
+        #
+        # # # Set mode
+        DUTMode= 0xFFFFFFFF
+        self.setMode(DUTMode)
+
+        # # # Set modifier
+        modifier = int("0xFF",16)
+        self.setModeModifier(modifier)
+        #
+        # # Set veto shutter
+        setVetoShutters=0
+        self.setVetoShutters(setVetoShutters)
+
+        # # Set veto by DUT
+        ignoreDUTBusy=0x0
+        self.setVetoDUT(ignoreDUTBusy)
+        self.getExternalVeto()
+        #
+        # # Set trigger interval (use 0 to disable internal triggers)
+        triggerInterval= 0000
+        self.setInternalTrg(triggerInterval)
+
+        print "TLU INITIALIZED"
+
+##################################################################################################################################
+##################################################################################################################################
+    def start(self, logtimestamps=False):
+        print "TLU STARTING..."
+
+        print "  FIFO RESET:"
+        FIFOcmd= 0x2
+        self.setFifoCSR(FIFOcmd)
+
+        eventFifoFillLevel= self.getFifoLevel()
+        cmd = int("0x000",16)
+        self.setInternalTrg(cmd)
+
+        if logtimestamps:
+            self.setRecordDataStatus(True)
+        else:
+            self.setRecordDataStatus(False)
+
+        # Pulse T0
+        self.pulseT0()
+
+        print "  Turning off software trigger veto"
+        cmd = int("0x0",16)
+        self.setTriggerVetoStatus(cmd)
+
+        print "TLU RUNNING"
+
+##################################################################################################################################
+##################################################################################################################################
+    def stop(self):
+        print "TLU STOPPING..."
+
+        self.getPostVetoTrg()
+        eventFifoFillLevel= self.getFifoLevel()
+        print "  Turning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        nFifoWords= int(eventFifoFillLevel)
+        fifoData= self.getFifoData(nFifoWords)
+
+        outList= self.parseFifoData(fifoData, nFifoWords/6, False)
+        self.saveFifoData(outList)
+        self.plotFifoData(outList)
+        #outFile = open('./test.txt', 'w')
+        #for iData in range (0, 30):
+    	#    outFile.write("%s\n" % fifoData[iData])
+        #    print hex(fifoData[iData])
+        print "TLU STOPPED"
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/TLUaddrmap.xml b/AIDA_tlu/legacy/TLU_v1c/scripts/TLUaddrmap.xml
new file mode 100644
index 0000000000000000000000000000000000000000..65fb5340f2155f8c5c92d96a2ef66d8dcb209d41
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/TLUaddrmap.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/TLUconnection.xml b/AIDA_tlu/legacy/TLU_v1c/scripts/TLUconnection.xml
new file mode 100644
index 0000000000000000000000000000000000000000..213a5b1f0060562e4970e5ca64c4552549f72750
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/TLUconnection.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="tlu" uri="ipbusudp-2.0://192.168.200.31:50001"
+   address_table="file://./TLUaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/initTLU.py b/AIDA_tlu/legacy/TLU_v1c/scripts/initTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/initTLU.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/output.csv b/AIDA_tlu/legacy/TLU_v1c/scripts/output.csv
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/output_check.csv b/AIDA_tlu/legacy/TLU_v1c/scripts/output_check.csv
new file mode 100644
index 0000000000000000000000000000000000000000..7932e233b96ceb28e7c3f773c9c75e28070c998d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/output_check.csv
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diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU.sh b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ac0b41ba589ddbc5836252e59ee1b23614455825
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+
+echo "=========================="
+CURRENT_DIR=${0%/*}
+echo "CURRENT DIRECTORY: " $CURRENT_DIR
+
+echo "============"
+echo "SETTING PATHS"
+export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+export PYTHONPATH=../../packages:$PYTHONPATH
+echo "PYTHON PATH= " $PYTHONPATH
+export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
+echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
+export PATH=/usr/bin/:/opt/cactus/bin:$PATH
+echo "PATH= " $PATH
+
+cd $CURRENT_DIR
+
+echo "============"
+echo "STARTING PYTHON SCRIPT FOR TLU"
+#python $CURRENT_DIR/startTLU_v8.py $@
+
+python startTLU_v8.py $@
+#python testTLU_script.py
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v6.py b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v6.py
new file mode 100644
index 0000000000000000000000000000000000000000..b7948f204682346e898a3126ac22b3e8aaa310a8
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v6.py
@@ -0,0 +1,232 @@
+#
+# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
+#
+# David Cussans, December 2012
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+
+import time
+
+from datetime import datetime
+
+from optparse import OptionParser
+
+# For single character non-blocking input:
+import select
+import tty
+import termios
+
+from initTLU import *
+
+def isData():
+    return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
+
+now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+default_filename = 'tluData_' + now + '.root'
+parser = OptionParser()
+
+parser.add_option('-r','--rootFname',dest='rootFname',
+                       default=default_filename,help='Path of output file')
+parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
+                       default="True",help='Set True to write timestamps to ROOT file')
+parser.add_option('-p','--printTimestamps',dest='printTimestamps',
+                       default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
+parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
+                       default=False,help='Set True to veto triggers when shutter goes high')
+parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
+                       default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
+parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
+                       default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
+parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
+                       default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
+parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
+                       default=0x01,help='Three-bit mask selecting which DUTs are active.')
+parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
+                       default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
+parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
+                       default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
+parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
+                       default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
+
+(options, args) = parser.parse_args(sys.argv[1:])
+
+from ROOT import TFile, TTree
+from ROOT import gROOT
+
+print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+
+# Point to board in uHAL
+manager = uhal.ConnectionManager("file://./connection.xml")
+hw = manager.getDevice("minitlu")
+device_id = hw.id()
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+# Assume DIP-switch controlled address. Switches at 2
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Open Root file
+print "OPENING ROOT FILE:", options.rootFname
+f = TFile( options.rootFname, 'RECREATE' )
+
+# Create a root "tree"
+tree = TTree( 'T', 'TLU Data' )
+highWord =0
+lowWord =0
+evtNumber=0
+timeStamp=0
+evtType=0
+trigsFired=0
+bufPos = 0
+
+# Create a branch for each piece of data
+tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+
+# Initialize TLU registers
+initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
+
+loopWait = 0.1
+oldEvtNumber = 0
+
+oldPreVetotriggerCount = board.read("PreVetoTriggersR")
+oldPostVetotriggerCount = board.read("PostVetoTriggersR")
+
+oldThresholdCounter0 =0
+oldThresholdCounter1 =0
+oldThresholdCounter2 =0
+oldThresholdCounter3 =0
+
+print "STARTING POLLING LOOP"
+
+eventFifoFillLevel = 0
+loopRunning = True
+runStarted = False
+
+oldTime = time.time()
+
+# Save old terminal settings
+oldTermSettings = termios.tcgetattr(sys.stdin)
+tty.setcbreak(sys.stdin.fileno())
+
+while loopRunning:
+
+    if isData():
+        c = sys.stdin.read(1)
+        print "\tGOT INPUT:", c
+        if c == 't':
+            loopRunning = False
+            print "\tTERMINATING LOOP"
+        elif c == 'c':
+            runStarted = True
+            print "\tSTARTING RUN"
+            startTLU( uhalDevice = hw, pychipsBoard = board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        elif c == 'f':
+            # runStarted = True
+            print "\tSTOPPING TRIGGERS"
+            stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+
+    if runStarted:
+
+        eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
+
+        preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
+        postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
+
+        timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
+        timestampLow  = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+
+        thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
+        thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
+        thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
+        thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
+
+        hw.dispatch()
+
+        newTime = time.time()
+        timeDelta = newTime - oldTime
+        oldTime = newTime
+        #print "time delta = " , timeDelta
+        preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
+        postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
+        oldPreVetotriggerCount = preVetotriggerCount
+        oldPostVetotriggerCount = postVetotriggerCount
+
+        deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
+        oldThresholdCounter0 = thresholdCounter0
+        deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
+        oldThresholdCounter1 = thresholdCounter1
+        deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
+        oldThresholdCounter2 = thresholdCounter2
+        deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
+        oldThresholdCounter3 = thresholdCounter3
+
+        print "pre , post  veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
+
+        print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
+
+        print "Input counts 0,1,2,3 = "      , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
+        print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
+
+        nEvents = int(eventFifoFillLevel)//4  # only read out whole events ( 4 x 32-bit words )
+        wordsToRead =  nEvents*4
+
+        print "FIFO FILL LEVEL= " , eventFifoFillLevel
+
+        print "# EVENTS IN FIFO = ",nEvents
+        print "WORDS TO READ FROM FIFO  = ",wordsToRead
+
+        # get timestamp data and fifo fill in same outgoing packet.
+        timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
+
+        hw.dispatch()
+
+    #    print timestampData
+        for bufPos in range (0, nEvents ):
+            lowWord  = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
+
+            highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
+            evtNumber = timestampData[bufPos*4 + 3]
+
+            if evtNumber != ( oldEvtNumber + 1 ):
+                print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ",  evtNumber , oldEvtNumber
+
+            oldEvtNumber = evtNumber
+
+            timeStamp = lowWord & 0xFFFFFFFFFFFF
+
+            evtType = timestampData[ (bufPos*4) + 0] >> 28
+
+            trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
+
+            if (options.printTimestamps == "True" ):
+                print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
+
+            # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
+            tree.Fill()
+
+    time.sleep( loopWait)
+
+# Fixme - at the moment infinite loop.
+preVetotriggerCount = board.read("PreVetoTriggersR")
+postVetotriggerCount = board.read("PostVetoTriggersR")
+print "EXIT POLLING LOOP"
+print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
+
+termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
+f.Write()
+f.Close()
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v8.py b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v8.py
new file mode 100644
index 0000000000000000000000000000000000000000..5682cbaf8d4efb75dc94f3771f6fba8c1e69c0ba
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/startTLU_v8.py
@@ -0,0 +1,72 @@
+# -*- coding: utf-8 -*-
+# miniTLU test script
+
+#from PyChipsUser import *
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from TLU import TLU
+# Use to have interactive shell
+import cmd
+
+class MyPrompt(cmd.Cmd):
+
+
+    def do_startRun(self, args):
+	"""Starts the TLU run"""
+	print "COMMAND RECEIVED: STARTING TLU RUN"
+	startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+	#print self.hw
+
+    def do_stopRun(self, args):
+	"""Stops the TLU run"""
+	print "COMMAND RECEIVED: STOP TLU RUN"
+	#stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "COMMAND RECEIVED: QUITTING SCRIPT."
+        #raise SystemExit
+	return True
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    TLU= TLU("tlu", "file://./TLUconnection.xml")
+    TLU.initialize()
+
+    logdata= True
+    TLU.start(logdata)
+    time.sleep(0.2)
+    TLU.stop()
+    # prompt = MyPrompt()
+    # prompt.prompt = '>> '
+    # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/test.py b/AIDA_tlu/legacy/TLU_v1c/scripts/test.py
new file mode 100644
index 0000000000000000000000000000000000000000..ac68201827840fbba1f2dad4c1c9596cba6ea9eb
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/test.py
@@ -0,0 +1,34 @@
+import matplotlib.pyplot as plt
+import numpy as np
+import matplotlib.mlab as mlab
+
+print "TEST.py"
+myFile= "./500ns_23ns.txt"
+
+with open(myFile) as f:
+    nsDeltas = map(float, f)
+
+P= 1000000000 #display in ns
+nsDeltas = [x * P for x in nsDeltas]
+centerRange= 25
+windowsns= 5
+minRange= centerRange-windowsns
+maxRange= centerRange+windowsns
+plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+#plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+#plt.xlim((min(nsDeltas), max(nsDeltas)))
+plt.xlabel('Time (ns)')
+plt.ylabel('Entries')
+plt.title('Histogram DeltaTime')
+plt.grid(True)
+
+#Superimpose Gauss
+mean = np.mean(nsDeltas)
+variance = np.var(nsDeltas)
+sigma = np.sqrt(variance)
+x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+plt.plot(x, mlab.normpdf(x, mean, sigma))
+print (mean, sigma)
+
+#Display plot
+plt.show()
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/testTLU_script.py b/AIDA_tlu/legacy/TLU_v1c/scripts/testTLU_script.py
new file mode 100644
index 0000000000000000000000000000000000000000..9d8b334bb4a6fd01050c3d622f54847616fce208
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/testTLU_script.py
@@ -0,0 +1,79 @@
+# miniTLU test script
+
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+from I2CuHal import I2CCore
+from miniTLU import MiniTLU
+from datetime import datetime
+
+if __name__ == "__main__":
+    print "\tTEST TLU SCRIPT"
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    #(self, target, wclk, i2cclk, name="i2c", delay=None)
+    TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
+    TLU_I2C.state()
+
+
+    #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
+    mystop= 1
+    time.sleep(0.1)
+    myaddr= [0xfa]
+    TLU_I2C.write( 0x50, myaddr, mystop)
+    res=TLU_I2C.read( 0x50, 6)
+    print "Checkin EEPROM:"
+    result="\t"
+    for iaddr in res:
+        result+="%02x "%(iaddr)
+    print result
+
+    #SCAN I2C ADDRESSES
+    #WRITE PROM
+    #WRITE DAC
+
+
+    #Convert required threshold voltage to DAC code
+    #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+    print("Writing DAC setting:")
+    Vref= 1.300
+    desiredVoltage= 3.3
+    channel= 0
+    i2cSlaveAddrDac = 0x1F
+    vrefOn= 0
+    Vdaq = ( desiredVoltage + Vref ) / 2
+    dacCode = 0xFFFF * Vdaq / Vref
+    dacCode= 0x391d
+    print "\tVreq:", desiredVoltage
+    print "\tDAC code:"  , dacCode
+    print "\tCH:", channel
+    print "\tIntRef:", vrefOn
+
+    #Set DAC value
+    #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+    if channel<0 or channel>7:
+        print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+        ##return -1
+    if dacCode<0 or dacCode>0xFFFF:
+        print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
+        ##return -1
+    # AD5665R chip with A0,A1 tied to ground
+    #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+
+    # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+    # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+    # # if we want to enable internal voltage reference:
+
+    if vrefOn:
+        # enter vref-on mode:
+        print "\tTurning internal reference ON"
+        #dac.write([0x38,0x00,0x01])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
+    else:
+        print "\tTurning internal reference OFF"
+        #dac.write([0x38,0x00,0x00])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
+    # Now set the actual value
+    sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+    print "\tWriting byte sequence:", sequence
+    TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/AIDA_tlu/legacy/TLU_v1c/scripts/test_T0.py b/AIDA_tlu/legacy/TLU_v1c/scripts/test_T0.py
new file mode 100644
index 0000000000000000000000000000000000000000..cf81b33d0fcac1767da1923d9abb62634a5885a2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/scripts/test_T0.py
@@ -0,0 +1,92 @@
+#
+# Script to exercise AIDA mini-TLU
+#
+# David Cussans, December 2012
+# 
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+# Assume DIP-switch controlled address. Switches at 2 
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+firmwareID=board.read("FirmwareId")
+
+print "Firmware (from PyChips) = " , hex(firmwareID)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+ 
+
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+    print "Resetting clocks"
+    board.write("LogicRst", 1 )
+
+    clockStatus = board.read("LogicClocksCSR")
+    print "Clock status after reset = " , hex(clockStatus)
+
+
+board.write("InternalTriggerIntervalW",0)
+
+print "Enabling DUT 0 and 1"
+board.write("DUTMaskW",3)
+DUTMask = board.read("DUTMaskR")
+print "DUTMaskR = " , DUTMask
+
+print "Ignore veto on DUT 0 and 1"
+board.write("IgnoreDUTBusyW",3)
+IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
+print "IgnoreDUTBusyR = " , IgnoreDUTBusy
+
+print "Turning off software trigger veto"
+board.write("TriggerVetoW",0)
+
+print "Reseting FIFO"
+board.write("EventFifoCSR",0x2)
+eventFifoFillLevel = board.read("EventFifoFillLevel")
+print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
+
+print "Enabling data recording"
+board.write("Enable_Record_Data",1)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+#TriggerInterval = 400000
+TriggerInterval = 0
+print "Setting internal trigger interval to " , TriggerInterval
+board.write("InternalTriggerIntervalW",TriggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+trigInterval = board.read("InternalTriggerIntervalR")
+print "Trigger interval read back as ", trigInterval
+
+print "Setting TPix_maskexternal to ignore external shutter and T0"
+board.write("TPix_maskexternal",0x0003)
+
+numLoops = 500000
+oldEvtNumber = 0
+
+for iLoop in range(0,numLoops):
+
+    board.write("TPix_T0", 0x0001)
+
+#   time.sleep( 1.0)
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/clock_divider_s6.v b/AIDA_tlu/legacy/TLU_v1c/test/clock_divider_s6.v
new file mode 100644
index 0000000000000000000000000000000000000000..3e29a336be8c059d649a8f5d9862f4dcb41c7f01
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/clock_divider_s6.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+
+module clock_divider_s6(
+    input clk,
+    output d25,
+    output d28
+    );
+
+	wire [6:0] q;
+	reg [5:0] qr = 0;
+	reg [2:0] ctr = 0;
+   //wire 	  unconnected; // horrid hack
+   
+	assign q[0] = 1'b1;
+	
+	generate
+		genvar i;
+		for(i=1; i<=5; i=i+1) begin: gen_sr
+
+			SRLC32E #(
+				.INIT(32'h80000000)
+			) sr_0 (
+				.Q(q[i]),
+				.A(5'b11111),
+				.CE(q[i-1] & ~qr[i-1]),
+				.CLK(clk),
+				.D(q[i])
+			);
+
+			always @(posedge clk)
+			begin
+				qr[i] <= q[i];
+			end
+
+		end
+	endgenerate
+
+	assign d25 = q[5];
+
+	always @(posedge clk)
+	begin
+		if(q[5] & ~qr[5]) ctr <= ctr + 1;
+	end
+	
+	assign d28 = ctr[2];
+	
+endmodule
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/clocks_s6_extphy.vhd b/AIDA_tlu/legacy/TLU_v1c/test/clocks_s6_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ddca849e191c6a2c380e422d3dc42b46e088e3b8
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/clocks_s6_extphy.vhd
@@ -0,0 +1,110 @@
+-- clocks_s6_extphy
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_s6_extphy is port(
+	sysclk_p, sysclk_n: in std_logic;
+	clko_125: out std_logic;
+	clko_ipb: out std_logic;
+	locked: out std_logic;
+	rsto_125: out std_logic;
+	rsto_ipb: out std_logic;
+	onehz: out std_logic
+	);
+
+end clocks_s6_extphy;
+
+architecture rtl of clocks_s6_extphy is
+
+	signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk: std_logic;
+	signal d25, d25_d, dcm_locked: std_logic;
+	signal rst: std_logic := '1';
+	
+	component clock_divider_s6 port(
+		clk: in std_logic;
+		d25: out std_logic;
+		d28: out std_logic
+	);
+	end component;
+	
+begin
+
+	ibufgds0: IBUFGDS port map(
+		i => sysclk_p,
+		ib => sysclk_n,
+		o => sysclk
+	);
+
+	bufg_125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+	
+	clko_125 <= clk_125_b;
+	
+	bufg_ipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+
+	dcm0: DCM_CLKGEN
+		generic map(
+			CLKIN_PERIOD => 5.0,
+			CLKFX_MULTIPLY => 5,
+			CLKFX_DIVIDE => 8,
+			CLKFXDV_DIVIDE => 4
+		)
+		port map(
+			clkin => sysclk,
+			clkfx => clk_125_i,
+			clkfxdv => clk_ipb_i,
+			locked => dcm_locked,
+			rst => '0'
+		);
+		
+	clkdiv: clock_divider_s6 port map(
+		clk => sysclk,
+		d25 => d25,
+		d28 => onehz
+	);
+	
+	process(sysclk)
+	begin
+		if rising_edge(sysclk) then
+			d25_d <= d25;
+			if d25='1' and d25_d='0' then
+				rst <= not dcm_locked;
+			end if;
+		end if;
+	end process;
+	
+	locked <= dcm_locked;
+
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rsto_ipb <= rst;
+		end if;
+	end process;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rsto_125 <= rst;
+		end if;
+	end process;
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/comb_generator_rtl.vhd b/AIDA_tlu/legacy/TLU_v1c/test/comb_generator_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0ad1db2c2724fdf1664fe4ef3cd3fc3d7856ba83
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/comb_generator_rtl.vhd
@@ -0,0 +1,90 @@
+--@file
+--
+--@brief Generates a series of "10" bits followed by a run of "0". The number
+-- of "10" is the same as the output bit plus one.
+--
+--@detailed i.e. output(0) has "1000......0010......" etc.
+-- output(1) has "1010.......001010......" etc. and so on.
+--
+-- David Cussans, February 2011
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+
+entity comb_generator is
+  
+  generic (
+    g_SEQUENCE_LENGTH : positive := 4;  -- --! Length of sequence before repeat = 2^g_SEQUENCE_LENGTH
+    g_N_OUTPUT_BITS   : positive := 5);  -- --! Number of bits in output. g_N_OUTPUT_BITS<2^g_SEQUENCE_LENGTH
+
+  port (
+    clk_i   : in  std_logic;            -- --! Rising edge active
+    reset_i : in  std_logic;            -- --! Active high. Synchronous
+    data_o  : out std_logic_vector(g_N_OUTPUT_BITS-1 downto 0));  --! Output pattern
+
+  subtype t_COMB_ARRAY is std_logic_vector( 2**g_SEQUENCE_LENGTH -1 downto 0);
+  -- Function to generate a "10101010" pattern. 
+  function f_GenerateComb ( v_Length : positive ) return t_COMB_ARRAY is
+    variable v_Comb : t_COMB_ARRAY ;
+    begin
+      for v_bit in v_Comb'range loop
+        if ((v_bit mod 2) = 0) then
+          v_Comb(v_bit) := '0';
+        else
+          v_Comb(v_bit) := '1';
+        end if;
+      end loop;
+      return v_Comb;
+    end f_GenerateComb;
+    
+end entity comb_generator;
+
+architecture rtl of comb_generator is
+
+  signal s_counter : unsigned( g_SEQUENCE_LENGTH-1 downto 0) := ( others => '0');  -- --! roll over of the counter sets the sequence length
+  constant c_SEQUENCE_WIDTH : positive := 2**g_SEQUENCE_LENGTH;  -- generate a constant to make code easier to read...
+  constant c_ZEROS : std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0) := (others => '0');  --! a vector of zeros to pad out sequence
+  constant c_COMB : std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0)  := f_GenerateComb(1);  -- --! Pattern of 1 and 0
+  subtype t_sequence is std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0);
+  type t_patternArray is array(g_N_OUTPUT_BITS-1 downto 0) of t_sequence;
+  signal s_pattern : t_patternArray := ( others => ( others => '0'));  --! Array of patterns. One for each output bit.
+  
+begin  -- architecture rtl
+
+  gen_bits: for v_bitNumber in 1 to g_N_OUTPUT_BITS generate
+
+    -- purpose: Generates the comb pattern. Different for each bit
+    -- type   : sequential
+    -- inputs : clk_i, reset_i, s_counter
+    -- outputs: data_o(v_bitNumber)
+    p_genPattern: process (clk_i, reset_i) is
+    begin  -- process p_genPattern
+      if rising_edge(clk_i) then  -- rising clock edge
+        if reset_i = '1' then             -- synchronous reset (active high)
+          s_counter <= ( others => '0');
+        else
+          
+          s_counter <= s_counter + 1 ;
+          data_o(v_bitNumber-1) <= s_pattern(v_bitNumber-1)(0);
+          
+          if ( s_counter = 0 ) then
+            s_pattern(v_bitNumber-1) <= c_COMB( (v_bitNumber*2)-1 downto 0) & c_ZEROS( c_SEQUENCE_WIDTH - (v_bitNumber*2)-1 downto 0);
+          else
+            s_pattern(v_bitNumber-1) <= '0' & s_pattern(v_bitNumber-1)(c_SEQUENCE_WIDTH-1 downto 1);
+          end if;
+        end if;
+      end if;
+    end process p_genPattern;
+    
+  end generate gen_bits;
+  
+
+
+end architecture rtl;
+
+
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/dtype_fd.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fd.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..2ab1f6763c8db5ff55ba4fd49116bbbb499a5d7e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fd.vhdl
@@ -0,0 +1,38 @@
+----- CELL dtype_fd                       -----
+--
+--@file
+--
+--@brief Aims to be the same as the Xilinx "FD" primitive -
+-- D-Type flip-flop
+--
+-- Modified from D-type example in VHDL book.
+-- See Xilinx spartan6_scm.pdf
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity dtype_fd is
+
+  port(
+    Q : out std_logic;      --! Output
+    CLK   : in std_logic;   --! Clock - rising edge active
+    D   : in std_logic     --! Input
+    );
+
+end dtype_fd;
+
+architecture rtl of dtype_fd is
+begin
+
+  VITALBehavior         : process(CLK)
+  begin
+
+    if  rising_edge(CLK) then
+      Q <= D ;
+    end if;
+  end process;
+
+end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdpe.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdpe.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d6c2e8a315345d0cbd35f3787cbaf4cc693ea482
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdpe.vhdl
@@ -0,0 +1,43 @@
+----- CELL dtype_fdpe                       -----
+--
+--@file
+--
+--@brief Aims to be the same as the Xilinx "FDPE" primitive -
+-- D-Type flip-flop with asynchronous set.
+--
+-- Modified from D-type example in VHDL book.
+-- See Xilinx spartan6_scm.pdf
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+-- use IEEE.VITAL_Timing.all;
+
+entity dtype_fdpe is
+
+  port(
+    Q : out std_logic;      --! Output
+    CLK   : in std_logic;   --! Clock - rising edge active
+    D   : in std_logic;     --! Input
+    CE  : in std_logic;     --! Clock enable
+    PRE : in std_logic      --! Asynchronous preload
+    );
+
+end dtype_fdpe;
+
+architecture dtype_V of dtype_fdpe is
+begin
+
+  VITALBehavior         : process(CLK, PRE , CE)
+  begin
+
+    if (PRE = '1') then
+      Q <= '1';
+    elsif ( rising_edge(CLK) and CE = '1' ) then
+      Q <= D ;
+    end if;
+  end process;
+
+end dtype_V;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdr.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdr.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..cd388ae802200cfc9e3f50167e8b4e41a3e2befc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fdr.vhdl
@@ -0,0 +1,75 @@
+
+--! @file dtype_fdr.vhdl
+--
+
+--
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: dtype_fdr
+--
+--! @brief   Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdfOutput goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
+entity dtype_fdr is
+
+  port(
+    Q : out std_logic;      --! Output
+    CLK   : in std_logic;   --! Clock - rising edge active
+    RST : in std_logic;     --! Active high, synchronous
+    D   : in STD_LOGIC     --! Input
+    );
+
+end dtype_fdr;
+
+architecture rtl of dtype_fdr is
+begin
+
+  VITALBehavior : process(CLK)
+  begin
+
+    if  rising_edge(CLK) then
+      if (RST = '1') then
+        Q <= '0';
+      else
+        Q <= D ;
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/dtype_fds.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fds.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..22593c5c96bcc0acccfd21615d9025ef7a5c046e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/dtype_fds.vhdl
@@ -0,0 +1,76 @@
+
+--! @file dtype_fds.vhdl
+--
+
+--
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: dtype_fds
+--
+--! @brief   Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
+entity dtype_fds is
+
+  port(
+    Q : out std_logic;      --! Output
+    CLK   : in std_logic;   --! Clock - rising edge active
+    SET : in std_logic;     --! Active high, synchronous
+    D   : in STD_LOGIC     --! Input
+    );
+
+end dtype_fds;
+
+architecture rtl of dtype_fds is
+begin
+
+  VITALBehavior : process(CLK)
+  begin
+
+    if  rising_edge(CLK) then
+      if (SET = '1') then
+        Q <= '1';
+      else
+        Q <= D ;
+      end if;
+    end if;
+  end process;
+
+end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/fmc-tlu_sp601_pulse_shaper.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/fmc-tlu_sp601_pulse_shaper.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..f9fe826f276fc8ff8d0f059c92994a18236cc240
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/fmc-tlu_sp601_pulse_shaper.vhdl
@@ -0,0 +1,65 @@
+--@file
+--
+--@brief Top level for AIDA Mini-TLU in FMC format using IPBUS.
+--
+-- David Cussans, February 2011
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+--! Use library for instantiating Xilinx primitive components.
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity fmc_tlu_sp601 is
+  port (
+    SYSCLK_N , SYSCLK_P : in  std_logic;   --! 200MHz crystal clock
+    D                   : in  std_logic;   --! pulse input
+    Q                   : out std_logic;   --! pulse_output
+    RST : in std_logic;                 --! active high. Syncronous
+    pulse_length          : in std_logic_vector(3 downto 0)  --!
+                                                                       --Dummy
+                                                                       --to
+                                                                       --avoid pruning
+    
+    );  
+
+end fmc_tlu_sp601;
+
+architecture rtl of fmc_tlu_sp601 is
+
+  -- constant MASK_WIDTH : integer := 16;  -- Number of registers in shift-reg
+  
+  component pulse_shaper
+    port (
+      D_a_i          : in  std_logic;         --! Input pulse
+      Q_a_o          : out std_logic;         --! output pulse
+      CLK_i        : in  std_logic;         --! Clock , rising edge active
+      RST_i        : in std_logic;        --! Active high. Synchronous
+      PULSE_LENGTH_i : in  std_logic_vector(3 downto 0));  -- ! Load with desired
+                                                        -- width of pulse.
+  end component;
+
+  signal buffered_clock : std_logic := '0';
+  
+begin  -- rtl
+
+ -- buf_sysclk : IBUFGDS
+--    port map (
+--      I  => sysclk_p,
+--      IB => sysclk_n,
+--      O  => buffered_clock);
+
+  -- for simulation bodge up by connecting buffered_clock to sysclk_p
+  buffered_clock <= sysclk_p;
+  
+  shaper : pulse_shaper
+    port map (
+      D_a_i          => D,
+      Q_a_o          => Q,
+      RST_i        => RST,
+      CLK_i        => buffered_clock,
+      pulse_length_i => pulse_length);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_pin_test.vhd b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_pin_test.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3430ed9b7bc6040460d0c3d09fe1ebcf1c977dba
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_pin_test.vhd
@@ -0,0 +1,216 @@
+--=============================================================================
+--! @file fmcTlu_pinTest_struct.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL -- VHDL Architecture work.fmcTlu_pinTest.struct
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
+--
+--! @date 16:18:26 01/24/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY fmcTlu_pinTest IS
+   GENERIC( 
+      g_NUM_DUTS            : positive := 3;
+      g_NUM_TRIG_INPUTS     : positive := 4;
+      g_NUM_EXT_SLAVES      : positive := 11;      --! Number of slaves outside IPBus interface
+      g_EVENT_DATA_WIDTH    : positive := 64;
+      g_IPBUS_WIDTH         : positive := 32;
+      g_NUM_EDGE_INPUTS     : positive := 4;
+      g_SPILL_COUNTER_WIDTH : positive := 12
+   );
+   PORT( 
+      cfd_discr_n_i       : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      cfd_discr_p_i       : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      dip_switch_i        : IN     std_logic_vector (3 DOWNTO 0);
+      gmii_rx_clk_i       : IN     std_logic;
+      gmii_rx_dv_i        : IN     std_logic;
+      gmii_rx_er_i        : IN     std_logic;
+      gmii_rxd_i          : IN     std_logic_vector (7 DOWNTO 0);
+      sysclk_n_i          : IN     std_logic;                                        --! 200 MHz xtal clock
+      sysclk_p_i          : IN     std_logic;
+      threshold_discr_n_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      threshold_discr_p_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      reset_i				  : IN 		std_logic;
+      gmii_gtx_clk_o      : OUT    std_logic;
+      gmii_tx_en_o        : OUT    std_logic;
+      gmii_tx_er_o        : OUT    std_logic;
+      gmii_txd_o          : OUT    std_logic_vector (7 DOWNTO 0);
+      gpio_hdr            : OUT    std_logic_vector (7 DOWNTO 0);
+      leds_o              : OUT    std_logic_vector (3 DOWNTO 0);
+      phy_rstb_o          : OUT    std_logic;
+      i2c_scl_b           : INOUT  std_logic;
+      i2c_sda_b           : INOUT  std_logic;
+      -- Signal definitions for TLU in normal use:
+      --busy_n_i            : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --busy_p_i            : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Busy lines from DUTs ( active high )
+      --dut_clk_n_o         : INOUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --dut_clk_p_o         : INOUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --reset_or_clk_n_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --reset_or_clk_p_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --triggers_n_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      --triggers_p_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Trigger lines to DUT
+      --extclk_n_b          : INOUT  std_logic;
+      --extclk_p_b          : INOUT  std_logic;                                        --! either external clock in, or a clock being driven out
+      -- Declare all as outputs for test purposes
+      busy_n_o            : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      busy_p_o            : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Busy lines from DUTs ( active high )
+      dut_clk_n_o         : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      dut_clk_p_o         : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      reset_or_clk_n_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      reset_or_clk_p_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      triggers_n_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      triggers_p_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Trigger lines to DUT
+		spare_p_o           : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
+		spare_n_o           : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
+      extclk_n_o          : OUT  std_logic;
+      extclk_p_o          : OUT  std_logic                                      --! either external clock in, or a clock being driven out
+
+   );
+
+-- Declarations
+
+END ENTITY fmcTlu_pinTest ;
+
+
+
+LIBRARY work;
+--USE work.ipbus.all;
+--USE work.emac_hostbus_decl.all;
+--
+--USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;
+
+
+ARCHITECTURE struct OF fmcTlu_pinTest IS
+
+   -- Architecture declarations
+	
+   constant c_NUM_OUTPUTS : positive := 6;
+   signal s_patternData : std_logic_vector( c_NUM_OUTPUTS-1 downto 0);
+   signal s_reset : std_logic := '0';
+	signal ipbus_clk : std_logic := '0';
+	
+BEGIN
+
+	cmp_clks: entity work.clocks_s6_extphy
+		port map (
+			sysclk_p        => sysclk_p_i,
+			sysclk_n        => sysclk_n_i,
+			clk_logic_xtal_o=> OPEN,
+			clko_125        => OPEN,
+			clko_ipb        => ipbus_clk,
+			locked          => leds_o(2),
+			rsto_125        => OPEN,
+			rsto_ipb        => s_reset,
+			onehz           => leds_o(3)
+		);
+	                              
+	leds_o(1 downto 0) <= ( others => '0');
+	
+	i2c_scl_b  <= 'Z';
+   i2c_sda_b  <= 'Z';
+		
+   cmp_pattern: entity work.comb_generator
+     generic map (
+       g_N_OUTPUT_BITS => c_NUM_OUTPUTS
+       )
+     port map (
+       clk_i => ipbus_clk,
+       reset_i => s_reset,
+       data_o => s_patternData
+       );
+
+   gen_duts: for nDut in 0 to g_NUM_DUTS-1 generate
+
+     OBUFDS_busy_inst : OBUFDS
+       generic map (
+         IOSTANDARD => "DEFAULT")
+       port map (
+         O =>  busy_p_o(nDut),    -- Diff_p output 
+         OB => busy_n_o(nDut),   -- Diff_n output 
+         I =>  s_patternData(0)      -- Buffer input
+         );     
+
+     OBUFDS_dut_clk_inst : OBUFDS
+       generic map (
+         IOSTANDARD => "DEFAULT")
+       port map (
+         O =>  dut_clk_p_o(nDut),    -- Diff_p output 
+         OB => dut_clk_n_o(nDut),   -- Diff_n output 
+         I =>  s_patternData(1)      -- Buffer input
+         );
+
+     OBUFDS_reset_or_clk_inst : OBUFDS
+       generic map (
+         IOSTANDARD => "DEFAULT")
+       port map (
+         O =>  reset_or_clk_p_o(nDut),    -- Diff_p output 
+         OB => reset_or_clk_n_o(nDut),   -- Diff_n output 
+         I =>  s_patternData(2)      -- Buffer input
+         );
+
+     OBUFDS_triggers_inst : OBUFDS
+       generic map (
+         IOSTANDARD => "DEFAULT")
+       port map (
+         O =>  triggers_p_o(nDut),    -- Diff_p output 
+         OB => triggers_n_o(nDut),   -- Diff_n output 
+         I =>  s_patternData(3)      -- Buffer input
+         );
+     		
+   end generate gen_duts;
+
+	gen_duts1: for nDut in 1 to g_NUM_DUTS-1 generate
+	    OBUFDS_spare_inst : OBUFDS
+			generic map (
+				IOSTANDARD => "DEFAULT")
+			port map (
+				O =>  spare_p_o(nDut),    -- Diff_p output 
+				OB => spare_n_o(nDut),   -- Diff_n output 
+				I =>  s_patternData(4)      -- Buffer input
+				);
+	end generate gen_duts1;
+	
+   OBUFDS_extclk_inst : OBUFDS
+     generic map (
+       IOSTANDARD => "DEFAULT")
+     port map (
+       O =>  extclk_p_o,    -- Diff_p output 
+       OB => extclk_n_o,   -- Diff_n output 
+       I =>  s_patternData(5)      -- Buffer input
+       );
+   
+END ARCHITECTURE struct;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_sp601_tb.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_sp601_tb.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1ac494f5ae50c5209a2f23088642a7d19bf32894
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_sp601_tb.vhdl
@@ -0,0 +1,160 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   16:24:12 02/25/2011
+-- Design Name:   
+-- Module Name:   /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/synthesis/ise/mTLU/fmc_tlu_sp601_tb.vhd
+-- Project Name:  mTLU
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: fmc_tlu_sp601
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+use IEEE.Math_real.all;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+ 
+ENTITY fmc_tlu_sp601_tb IS
+END fmc_tlu_sp601_tb;
+ 
+ARCHITECTURE behavior OF fmc_tlu_sp601_tb IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+  COMPONENT fmc_tlu_sp601
+    PORT(
+      SYSCLK_N : IN  std_logic;
+      SYSCLK_P : IN  std_logic;
+      D : IN  std_logic;
+      Q : OUT  std_logic;
+      RST: in std_logic;
+      pulse_length : IN  std_logic_vector(3 downto 0)
+      );
+  END COMPONENT;
+    
+  component pulse_shaper_scorer
+    port (
+      clk_i       : in std_logic;         -- ! system clock
+      pulse_in_a_i  : in std_logic;         -- ! input ( unstretched) pulse
+      pulse_out_a_i : in std_logic; -- ! stretched pulse (output of pulse_stretcher)
+      pulse_length_i : in std_logic_vector      --! Parameter to pulse_strecher
+      );  
+  end component;
+  
+  --min and max can be swapped quite happily
+  procedure rand_int( variable seed1, seed2 : inout positive;
+                      min, max : in integer;
+                      result : out integer) is
+    variable rand     : real;
+  begin
+    uniform(seed1, seed2, rand);
+    result := integer(real(min) + (rand * (real(max)-real(min)) ) );
+  end procedure;
+
+   --Inputs
+    signal SYSCLK_N : std_logic := '0';
+    signal SYSCLK_P : std_logic := '0';
+    signal SYSCLK : std_logic := '0';
+    signal D : std_logic := '0';
+  signal RST : std_logic := '0';
+    signal pulse_length : std_logic_vector(3 downto 0) := (others => '0');
+
+ 	--Outputs
+    signal Q : std_logic;
+ 
+    constant sysclk_period : time := 10.0 ns;
+ 
+    constant averagePulseWidth : real := 3.0;
+    constant averagePulseLow : real := 500.0;
+	
+BEGIN
+
+  --! set pulse length to 7(?) clock cycles + internal
+--	pulse_length <= "0100" ; 
+  --! set pulse length to 5 clock cycles + internal
+	pulse_length <= "0001" ; 
+	
+	-- Instantiate the Unit Under Test (UUT)
+        uut: fmc_tlu_sp601 PORT MAP (
+          SYSCLK_N => SYSCLK_N,
+          SYSCLK_P => SYSCLK_P,
+          D => D,
+          Q => Q,
+          RST => RST,
+          pulse_length => pulse_length
+        );
+
+        --! Instantiate "scorer" process
+        --! Examine signals and check for errors
+        scorer: pulse_shaper_scorer
+          port map (
+            clk_i       => sysclk , 
+            pulse_in_a_i  => D,
+            pulse_out_a_i => Q,
+            pulse_length_i => pulse_length
+            );  
+        
+   -- Clock process definitions
+   sysclk_process :process
+   begin
+		sysclk <= '0';
+		wait for sysclk_period/2;
+		sysclk <= '1';
+		wait for sysclk_period/2;
+   end process;
+	sysclk_n <= not sysclk;
+	sysclk_p <= sysclk;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+	variable seed1 , seed2 : POSITIVE;
+	variable PulseWidth , PulseLow : time ;
+	variable Rand : real;
+	
+   begin
+     D <= '0';
+     RST <= '1';
+      -- hold reset state for 100 ns.
+     wait for 100 ns;	
+     RST <= '0';
+     
+     wait for sysclk_period*10;
+
+     -- insert stimulus here 
+     for I in 1 to 50 loop
+       D<= '1';
+       -- wait for random pulse width
+       uniform(seed1, seed2, Rand);
+       PulseWidth := Rand * averagePulseWidth * sysclk_period;
+       wait for PulseWidth;
+       D<= '0';
+       -- wait for random gap between pulses
+       uniform(seed1, seed2, Rand);
+       PulseLow := Rand * averagePulseLow * sysclk_period;
+       wait for PulseLow;
+     end loop;
+     wait;
+   end process;
+
+END;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_top_sp601.vhd b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_top_sp601.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7587013ab73124ab02a16046488495aad0533dca
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/fmc_tlu_top_sp601.vhd
@@ -0,0 +1,164 @@
+--=============================================================================
+--! @file fmc_tlu_top_sp601.vhd
+--=============================================================================
+-- @brief Top-level design for ipbus Maroc test . You must edit this file to set the IP and MAC addresses
+--
+--! @details Based on ipbus_demo_sp601 by Dave Newbold, 23/2/11
+--! This version is for xc6slx16 on Xilinx SP601 eval board
+--! Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
+--! You will need a license for the core
+--
+--! @author David Cussans, 31/07/12
+--
+
+-- Top-level design for trigger logic unit with IPBus readout
+--
+-- This version is for xc6slx16 on Xilinx SP601 eval board
+-- Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
+-- You will need a license for the core
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.ALL;
+use work.ipbus_bus_decl.all;
+use work.emac_hostbus_decl.all;
+
+--! Use UNISIM for Xilix primitives
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity fmc_tlu_top is port(
+	sysclk_p, sysclk_n : in STD_LOGIC;
+	leds: out STD_LOGIC_VECTOR(3 downto 0);
+	gmii_gtx_clk, gmii_tx_en, gmii_tx_er : out STD_LOGIC;
+	gmii_txd : out STD_LOGIC_VECTOR(7 downto 0);
+	gmii_rx_clk, gmii_rx_dv, gmii_rx_er: in STD_LOGIC;
+	gmii_rxd : in STD_LOGIC_VECTOR(7 downto 0);
+	phy_rstb : out STD_LOGIC;
+	dip_switch: in std_logic_vector(3 downto 0);
+
+       	-- Main I2C signals
+	i2c_sda_io: inout std_logic;
+	i2c_scl_io: inout std_logic;
+
+	);
+end top;
+
+architecture rtl of top is
+        
+        --
+	signal clk125, ipb_clk, locked, rst_125, rst_ipb, onehz : STD_LOGIC;
+        signal ipb_clk_n : STD_LOGIC;
+	signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
+	signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
+	signal ipb_master_out : ipb_wbus;
+	signal ipb_master_in : ipb_rbus;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal hostbus_in: emac_hostbus_in;
+	signal hostbus_out: emac_hostbus_out;
+
+	-- signals for main I2C
+	signal i2c_sda_oen_s: std_logic;
+	signal i2c_scl_oen_s: std_logic;
+
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_s6_extphy port map(
+		sysclk_p => sysclk_p,
+		sysclk_n => sysclk_n,
+		clko_125 => clk125,
+		clko_ipb => ipb_clk,
+		locked => locked,
+		rsto_125 => rst_125,
+		rsto_ipb => rst_ipb,
+		onehz => onehz
+		);
+		
+	leds <= ('0', '0', locked, onehz);
+	
+--	Ethernet MAC core and PHY interface
+-- In this version, consists of hard MAC core and GMII interface to external PHY
+-- Can be replaced by any other MAC / PHY combination
+	
+	eth: entity work.eth_s6_gmii port map(
+		clk125 => clk125,
+		rst => rst_125,
+		gmii_gtx_clk => gmii_gtx_clk,
+		gmii_tx_en => gmii_tx_en,
+		gmii_tx_er => gmii_tx_er,
+		gmii_txd => gmii_txd,
+		gmii_rx_clk => gmii_rx_clk,
+		gmii_rx_dv => gmii_rx_dv,
+		gmii_rx_er => gmii_rx_er,
+		gmii_rxd => gmii_rxd,
+		txd => mac_txd,
+		txdvld => mac_txdvld,
+		txack => mac_txack,
+		rxd => mac_rxd,
+		rxclko => mac_rxclko,
+		rxdvld => mac_rxdvld,
+		rxgoodframe => mac_rxgoodframe,
+		rxbadframe => mac_rxbadframe,
+		hostbus_in => hostbus_in,
+		hostbus_out => hostbus_out
+	);
+	
+	phy_rstb <= '1';
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl_udponly port map(
+		ipb_clk => ipb_clk,
+		rst_ipb => rst_ipb,
+		rst_macclk => rst_125,
+		mac_txclk => clk125,
+		mac_rxclk => mac_rxclko,
+		mac_rxd => mac_rxd,
+		mac_rxdvld => mac_rxdvld,
+		mac_rxgoodframe => mac_rxgoodframe,
+		mac_rxbadframe => mac_rxbadframe,
+		mac_txd => mac_txd,
+		mac_txdvld => mac_txdvld,
+		mac_txack => mac_txack,
+		ipb_out => ipb_master_out,
+		ipb_in => ipb_master_in,
+		mac_addr => mac_addr,
+		ip_addr => ip_addr
+	);
+		
+	mac_addr <= X"020ddba115" & dip_switch & X"0"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c8" & dip_switch & X"0"; -- 192.168.200.X
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+	slaves: entity work.slaves port map(
+		ipb_clk => ipb_clk,
+		rst => rst_ipb,
+		ipb_in => ipb_master_out,
+		ipb_out => ipb_master_in,
+-- Top level ports from here
+		hostbus_out => hostbus_in,
+		hostbus_in => hostbus_out,
+
+                gpio => open,
+		-- Main I2C signals
+		i2c_scl_i => i2c_scl_io ,
+		i2c_scl_oen_o => i2c_scl_oen_s ,
+		i2c_sda_i => i2c_sda_io,
+		i2c_sda_oen_o => i2c_sda_oen_s,
+                
+	);
+
+        -- For main I2C bus, need to put in a tri-state....
+	i2c_scl_io <= '0' when (i2c_scl_oen_s = '0') else 'Z';
+	i2c_sda_io <= '0' when (i2c_sda_oen_s = '0') else 'Z';
+
+end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/i2c_chipscope_debug.cdc b/AIDA_tlu/legacy/TLU_v1c/test/i2c_chipscope_debug.cdc
new file mode 100644
index 0000000000000000000000000000000000000000..1ead4c373d277470c4838bfb9317a569447e32d2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/i2c_chipscope_debug.cdc
@@ -0,0 +1,41 @@
+#ChipScope Core Inserter Project File Version 3.0
+#Tue Jul 23 13:58:01 BST 2013
+Project.device.designInputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
+Project.device.designOutputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
+Project.device.deviceFamily=18
+Project.device.enableRPMs=true
+Project.device.outputDirectory=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/_ngo
+Project.device.useSRL16=true
+Project.filter.dimension=7
+Project.filter<0>=*i2c*
+Project.filter<1>=*sda*
+Project.filter<2>=i2c*
+Project.filter<3>=ipbus_clk*
+Project.filter<4>=*wb_clk*
+Project.filter<5>=wb_clk*
+Project.filter<6>=
+Project.icon.boundaryScanChain=1
+Project.icon.enableExtTriggerIn=false
+Project.icon.enableExtTriggerOut=false
+Project.icon.triggerInPinName=
+Project.icon.triggerOutPinName=
+Project.unit.dimension=1
+Project.unit<0>.clockEdge=Rising
+Project.unit<0>.dataDepth=1024
+Project.unit<0>.dataEqualsTrigger=true
+Project.unit<0>.dataPortWidth=8
+Project.unit<0>.enableGaps=false
+Project.unit<0>.enableStorageQualification=false
+Project.unit<0>.enableTimestamps=false
+Project.unit<0>.timestampDepth=0
+Project.unit<0>.timestampWidth=0
+Project.unit<0>.triggerConditionCountWidth=0
+Project.unit<0>.triggerMatchCount<0>=1
+Project.unit<0>.triggerMatchCountWidth<0><0>=0
+Project.unit<0>.triggerMatchType<0><0>=1
+Project.unit<0>.triggerPortCount=1
+Project.unit<0>.triggerPortIsData<0>=true
+Project.unit<0>.triggerPortWidth<0>=8
+Project.unit<0>.triggerSequencerLevels=16
+Project.unit<0>.triggerSequencerType=0
+Project.unit<0>.type=ilapro
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/ipbus_addr_decode.vhd b/AIDA_tlu/legacy/TLU_v1c/test/ipbus_addr_decode.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6521459dbf6a85b9942d185a27176e84e0ef7937
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/ipbus_addr_decode.vhd
@@ -0,0 +1,46 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+    variable sel : integer;
+  begin
+		if    std_match(addr, "--------------------------000-00") then
+			sel := 0; -- statusReg / base 00000000 / mask 00000000
+		elsif std_match(addr, "--------------------------000-01") then
+			sel := 1; -- controlReg / base 00000001 / mask 00000000
+		elsif std_match(addr, "--------------------------000-10") then
+			sel := 2; -- pulser / base 00000002 / mask 00000000
+		elsif std_match(addr, "--------------------------001---") then
+			sel := 3; -- cbcI2C / base 00000008 / mask 00000007
+		elsif std_match(addr, "--------------------------010---") then
+			sel := 4; -- mainI2C / base 00000010 / mask 00000007
+		elsif std_match(addr, "--------------------------011---") then
+			sel := 5; -- captureBuffer / base 00000018 / mask 00000007
+		elsif std_match(addr, "--------------------------100-0-") then
+			sel := 6; -- emac_hostbus / base 00000020 / mask 00000001
+		else
+			sel := 99;
+		end if;
+		return sel;
+	end ipbus_addr_sel;
+ 
+end ipbus_addr_decode;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/ipbus_ver.vhd b/AIDA_tlu/legacy/TLU_v1c/test/ipbus_ver.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..81529bda8ac545c7dd15926a8d8f332ded42d02a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/ipbus_ver.vhd
@@ -0,0 +1,41 @@
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+entity ipbus_ver is
+	port(
+		ipbus_in: in ipb_wbus;
+		ipbus_out: out ipb_rbus
+	);
+	
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+  ipbus_out.ipb_rdata <= X"a5cd" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+  ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1d363ac8757df26cb7082eff3d098ea79cd24196
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper.vhdl
@@ -0,0 +1,200 @@
+--=============================================================================
+--! @file pulse_shaper.vhdl
+--=============================================================================
+
+--! Standard library
+Library IEEE;
+
+--! Standard logic package
+use IEEE.STD_LOGIC_1164.all;
+
+--! Xilinx library
+Library UNISIM;
+
+--! Xilinx component
+use UNISIM.vcomponents.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: pulse_shaper
+--
+--! @brief  Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details Output won't retrigger if input is still high at end of pulse.
+--! Length of pulse (in clock cycles) is pulse_length+4
+--
+--! <b>Dependencies:</b>\n
+--! dtype_fdpe
+--! dtype_fdr
+--! dtype_fds
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+--
+-------------------------------------------------------------------------------
+--! @todo Broaden pulse fed into set/reset flip-flop \n
+--
+-------------------------------------------------------------------------------
+
+entity pulse_shaper is
+  port (
+    D_a_i                   : in  std_logic;         --! Input pulse
+    Q_a_o                   : out std_logic;         --! output pulse
+    CLK_i                 : in  std_logic;         --! Clock , rising edge active
+    RST_i                 : in std_logic;         --! Hold high for PULSE_LENGTH+4 
+    PULSE_LENGTH_i        : in  std_logic_vector(3 downto 0) --! length of output pulse
+    );  
+
+end pulse_shaper;
+
+architecture rtl of pulse_shaper is
+
+  component dtype_fdpe
+    port(
+      Q : out std_logic;      --! Output
+      CLK   : in std_logic;   --! Clock - rising edge active
+      D   : in std_logic;     --! Input
+      CE  : in std_logic;     --! Clock enable
+      PRE : in std_logic      --! Asynchronous preload
+      );
+  end component;
+
+  
+  component dtype_fd
+    port(
+      Q : out std_logic;     --! Output
+      CLK   : in std_logic;  --! Clock - rising edge active
+      D   : in std_logic     --! Input
+      );
+  end component;
+  
+  component dtype_fds
+    port(
+      Q : out std_logic;     --! Output
+      CLK   : in std_logic;  --! Clock - rising edge active
+      SET : in std_logic;    --! Active high. Synchronous
+      D   : in std_logic     --! Input
+      );
+  end component;
+
+    component dtype_fdr
+    port(
+      Q : out std_logic;     --! Output
+      CLK   : in std_logic;  --! Clock - rising edge active
+      RST : in std_logic;    --! Active high. Synchronous
+      D   : in std_logic     --! Input
+      );
+  end component;
+
+  signal s_vetoed_pulse_a : std_logic := '0';  --! input signal after internal veto
+
+  signal s_async_pulse_a : std_logic := '0';  -- ! Output from pre-settable D-type
+  
+  signal s_srl_ce , s_srl_d , s_srl_q : std_logic := '0';  -- ! Input, output from shift reg.
+
+  signal s_Q_d1 , s_Q_d2 , s_Q_d3 : std_logic := '0';       --! Output, delayed by one clock. Used to form veto.
+
+  signal s_D_d1 , s_D_d2  : std_logic := '0';       --! Input, delayed by one clock. Used to form veto.
+  
+begin  -- rtl
+
+  --! Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST
+  s_srl_d <= s_Q_d2 and (not s_Q_d3);         
+
+  --! Clock the SRL if the output is high ( or if the output of the SRL is high.... )
+  s_srl_ce <= s_Q_d2 or s_srl_q ;
+  
+  SRL16E_inst : SRL16E
+    generic map (
+      INIT => X"0000")
+    port map (
+      Q => S_SRL_Q, -- SRL data output
+      A0 => PULSE_LENGTH_i(0), -- Select[0] input
+      A1 => PULSE_LENGTH_i(1), -- Select[1] input
+      A2 => PULSE_LENGTH_i(2), -- Select[2] input
+      A3 => PULSE_LENGTH_i(3), -- Select[3] input
+      CE => S_SRL_CE, -- Clock enable input
+      CLK => CLK_i, --Clock input
+      D => S_SRL_D -- SRL data input
+      );
+
+  --! In order for a pulse to get to the PREset input, the output must be low
+  --! and the input must be low. Goes low on RST high
+  s_vetoed_pulse_a <= D_a_i and (not s_Q_d2) and (not s_D_d2);
+  
+  Q_a_o <= s_async_pulse_a;                     --! Connect output of FDPE to output.
+
+  --! Async. set, sync clear.
+  async_reg: dtype_fdpe
+    port map (
+      Q   => s_async_pulse_a,
+      D   => '0',                       --! Clock in zero when shift reg. spits out a '1'
+      CLK => CLK_i,
+      CE  => S_SRL_Q,
+      PRE => s_vetoed_pulse_a ) ;
+    
+  q_reg1 : dtype_fdr                     --! Delay the output signal
+    port map (
+      Q   => s_Q_d1,
+      D   => s_async_pulse_a,
+      RST => RST_i,
+      CLK => CLK_i
+      ) ;
+
+  --! Delay the output signal
+  q_reg2 : dtype_fds                     
+    port map (
+      Q   => s_Q_d2,
+      D   => s_Q_d1,
+      SET => RST_i, --! Take high on reset.
+      CLK => CLK_i
+      ) ;
+
+  --! Delay the output signal
+  q_reg3 : dtype_fdr                     
+    port map (
+      Q   => s_Q_d3,
+      D   => s_Q_d2,
+      RST => RST_i, --! Take low on reset
+      CLK => CLK_i
+      ) ;
+
+  d_reg1 : dtype_fd                     --! Delay the input
+    port map (
+      Q   => s_D_d1,
+      D   => D_a_i,     
+      CLK => CLK_i
+      ) ;
+
+  d_reg2 : dtype_fds                     --! Delay the input
+    port map (
+      Q   => s_D_d2,
+      D   => s_D_d1,
+      SET => RST_i,
+      CLK => CLK_i
+      ) ;
+
+
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_async_dtypes.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_async_dtypes.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..6ba14ad38c67726b4b0cfeb17e87083ab7600268
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_async_dtypes.vhdl
@@ -0,0 +1,92 @@
+----- CELL pulse_shaper                       -----
+--
+--@file
+--
+--@brief Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--! Pile-up will result in timing errors ( veto-cleared sync. with clock )
+--
+--! Output won't retrigger if input is still high at end of pulse.
+--
+--! Fill top bits of PULSE_MASK
+--! For example for a pulse width of 4.X clock cycles load '1111000000000000'
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity pulse_shaper_async_dtypes is
+  generic (
+    MASK_WIDTH : integer := 16);  --! Width of shift register and hence maximum width of pulse
+  port (
+    D          : in  std_logic;         --! Input pulse
+    Q          : out std_logic;         --! output pulse
+    CLK        : in  std_logic;         --! Clock , rising edge active
+    PULSE_MASK : in  std_logic_vector(MASK_WIDTH-1 downto 0));  -- ! preload for shift-register. Fill with number of '1's that the ouput pulse should be
+
+end pulse_shaper_async_dtypes;
+
+architecture rtl of pulse_shaper_async_dtypes is
+
+  component dtype_fdpe
+    port(
+      Q : out std_logic;      --! Output
+      CLK   : in std_logic;   --! Clock - rising edge active
+      D   : in std_logic;     --! Input
+      CE  : in std_logic;     --! Clock enable
+      PRE : in std_logic      --! Asynchronous preload
+      );
+  end component;
+  
+  signal shift_reg : std_logic_vector(MASK_WIDTH downto 0) := ( others => '0' );  --! shift register holding '1's to be shifted out
+
+    signal preload : std_logic_vector(MASK_WIDTH-1 downto 0) := ( others => '0' ); --! Mask register holding '1's to be shifted out
+
+  signal vetoed_pulse : std_logic := '0';  --! input signal after internal veto
+
+  signal Q_R1 , Q_R2 , D_R1 : std_logic := '0';       --! Output, input  delayed by one clock. Used
+                                        --to form veto.
+  
+begin  -- rtl
+
+  shift_reg(0) <= '0';   --! Shift in zero at start of SReg.
+
+  --! Generate a shift register out of flip-flops.
+  --! Unfortunately SRL16 , SRL32 don't have async. load.
+  SR : for bit in 0 to MASK_WIDTH-1 generate
+    preload(bit) <=  (vetoed_pulse and pulse_mask(bit));
+    dtype : dtype_fdpe
+      port map (
+        Q   => shift_reg(bit+1),
+        D   => shift_reg(bit),
+        CLK => CLK,
+        CE  => '1',
+        PRE => preload(bit)) ;
+  end generate SR ;
+
+  Q <= shift_reg(MASK_WIDTH);           --! Take output from end of SR.
+
+  q_reg : dtype_fdpe                     --! Delay the output signal
+    port map (
+      Q   => Q_R1,
+      D   => shift_reg(MASK_WIDTH),     
+      CLK => CLK,
+      CE  => '1',
+      PRE => '0') ;
+
+  d_reg : dtype_fdpe                     --! Delay the input signal
+    port map (
+      Q   => D_R1,
+      D   => D,     
+      CLK => CLK,
+      CE  => '1',
+      PRE => '0') ;
+
+  --! Arrgh... problems with glitching if veto immediately.
+  -- put in a transparent latch or something to force some delay???
+  vetoed_pulse <= D and (not shift_reg(MASK_WIDTH) ) and (not Q_R1) and (not D_R1);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_scorer.vhdl b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_scorer.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..ef7b48acb7403dd2c0955d41ab3315ac1339e0a5
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/pulse_shaper_scorer.vhdl
@@ -0,0 +1,67 @@
+--=============================================================================
+--! @file pulse_stretcher_scorer.vhdl
+--=============================================================================
+
+--! Standard library
+Library IEEE;
+
+--! Standard logic package
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: pulse_stretcher_scoer
+--
+--! @brief Checks that pulse_shaper is behaving correctly.
+--! Check for Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details
+--
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+--
+-------------------------------------------------------------------------------
+--! @todo  \n
+--
+-------------------------------------------------------------------------------
+
+entity pulse_shaper_scorer is
+  port (
+    clk_i       : in std_logic;         -- ! system clock
+    pulse_in_a_i  : in std_logic;         -- ! input ( unstretched) pulse
+    pulse_out_a_i : in std_logic -- ! stretched pulse (output of pulse_stretcher)
+    pulse_length_i : in std_logic_vector;      --! Parameter to pulse_strecher
+    );  
+end pulse_shaper_scorer;
+
+architecture rtl of pulse_shaper_scorer is
+
+  
+begin  -- rtl
+
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/slaves.vhd b/AIDA_tlu/legacy/TLU_v1c/test/slaves.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0bb0f37ce106c6585c361dbd0d426c141469c904
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/slaves.vhd
@@ -0,0 +1,199 @@
+-- The ipbus slaves live in this entity - modify according to requirements
+--
+-- Ports can be added to give ipbus slaves access to the chip top level.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+use work.emac_hostbus_decl.all;
+
+entity slaves is port(
+	ipb_clk, rst : in STD_LOGIC;
+	ipb_in : in ipb_wbus;
+	ipb_out : out ipb_rbus;
+-- Top level ports from here
+	hostbus_out: out emac_hostbus_in;
+	hostbus_in: in emac_hostbus_out;
+
+        -- GPIO
+        gpio : out STD_LOGIC_VECTOR(3 downto 0);
+	-- Main I2C signals
+	i2c_scl_i: in std_logic;
+	i2c_scl_oen_o: out std_logic;
+	i2c_sda_i: in std_logic;
+	i2c_sda_oen_o: out std_logic;
+        -- CBC I2C signals
+	cbc_i2c_sda_enb_o: out std_logic;  --! Active low. SDA pulled low when enb is high 
+	cbc_i2c_scl_o: out std_logic;     --! I2C Clock output.
+	cbc_i2c_sda_i : in std_logic;
+	-- CBC "fast" signals
+	cbc_trg_o, ext_trg_o, cbc_reset_o: out std_logic;
+	cbc_data_i: in std_logic
+        
+	);
+
+end slaves;
+
+architecture rtl of slaves is
+
+	constant NSLV: positive := 7;
+	signal ipbw: ipb_wbus_array(NSLV-1 downto 0);
+	signal ipbr, ipbr_d: ipb_rbus_array(NSLV-1 downto 0);
+
+	signal cbc_i2c_scl_o_int: std_logic;
+        signal ctrl_reg: std_logic_vector(31 downto 0);
+        signal s_pulse_reg : std_logic_vector(31 downto 0);  -- ! pulsed control signals
+
+        signal s_cbc_reset : std_logic := '0';  -- ! Active high. Driven from cbcstuff
+
+        signal s_cap_trg : std_logic := '0';  -- ! Starts capture of incoming data into capture buffer
+
+begin
+
+  fabric: entity work.ipbus_fabric
+    generic map(NSLV => NSLV)
+    port map(
+      ipb_clk => ipb_clk,
+      rst => rst,
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: version register
+
+  slave0: entity work.ipbus_ver
+    port map(
+      ipbus_in => ipbw(0),
+      ipbus_out => ipbr(0));
+
+  -- Slave 1: 32b register
+  slave1: entity work.ipbus_reg
+    generic map(addr_width => 0)
+    port map(
+      clk => ipb_clk,
+      reset => rst,
+      ipbus_in => ipbw(1),
+      ipbus_out => ipbr(1),
+      q => ctrl_reg
+      );
+
+  s_cbc_reset <= ctrl_reg(16);
+  cbc_reset_o <= s_cbc_reset;
+
+  -- Slave 2: 32b pulser
+  slave2: entity work.ipbus_pulser
+    port map(
+      clk_i => ipb_clk,
+      reset_i => rst,
+      ipbus_i => ipbw(2),
+      ipbus_o => ipbr(2),
+      q_o => s_pulse_reg
+      );
+
+  -- CBC clock and trigger signals. Connected to slave-1 ( 32 bit register )
+  cbcstuff: entity work.cbc_logic
+    port map(
+      clk_i => ipb_clk,
+      cbc_trg_o => cbc_trg_o,
+      ext_trg_o => ext_trg_o,
+      cap_trg_o => s_cap_trg,
+      go_p_i => s_pulse_reg(0),
+      delay_i => unsigned(ctrl_reg(31 downto 24)),
+      trg_patt_i => ctrl_reg(22 downto 20)
+      );
+
+
+  -- Slave 3: I2C core connected to CBC
+
+  slave3: entity work.i2c_master_top
+    generic map (
+      ARST_LVL => 0
+      )
+    port map(
+      wb_clk_i => ipb_clk,
+      wb_rst_i => rst,
+      arst_i => '1', --! Active low reset.
+      wb_adr_i => ipbw(3).ipb_addr(2 downto 0),
+      wb_dat_i => ipbw(3).ipb_wdata(7 downto 0),
+      wb_dat_o => ipbr(3).ipb_rdata(7 downto 0),
+      wb_we_i => ipbw(3).ipb_write,
+      wb_stb_i => ipbw(3).ipb_strobe,
+      wb_cyc_i => '1',
+      wb_ack_o => ipbr(3).ipb_ack,
+      wb_inta_o => open,
+      scl_pad_i => cbc_i2c_scl_o_int,
+      scl_pad_o => open,
+      scl_padoen_o => cbc_i2c_scl_o_int,
+      sda_pad_i => cbc_i2c_sda_i,
+      sda_pad_o => open,
+      sda_padoen_o => cbc_i2c_sda_enb_o
+      );
+
+	
+  cbc_i2c_scl_o <= cbc_i2c_scl_o_int;
+  
+  ipbr(3).ipb_rdata(31 downto 8) <= (others => '0');
+
+
+  -- Slave 4: I2C core connected to main I2C
+  slave4: entity work.i2c_master_top
+    generic map (
+      ARST_LVL => 0
+      )
+    port map(
+      wb_clk_i => ipb_clk,
+      wb_rst_i => rst,
+      arst_i => '1', --! Active low reset.
+      wb_adr_i => ipbw(4).ipb_addr(2 downto 0),
+      wb_dat_i => ipbw(4).ipb_wdata(7 downto 0),
+      wb_dat_o => ipbr(4).ipb_rdata(7 downto 0),
+      wb_we_i => ipbw(4).ipb_write,
+      wb_stb_i => ipbw(4).ipb_strobe,
+      wb_cyc_i => '1',
+      wb_ack_o => ipbr(4).ipb_ack,
+      wb_inta_o => open,
+      scl_pad_i => i2c_scl_i,
+      scl_pad_o => open,
+      scl_padoen_o => i2c_scl_oen_o,
+      sda_pad_i => i2c_sda_i,
+      sda_pad_o => open,
+      sda_padoen_o => i2c_sda_oen_o
+      );
+  ipbr(4).ipb_rdata(31 downto 8) <= (others => '0');
+  
+  -- Slave 5: Capture register.
+  slave5 : entity work.ipbus_capture_buffer
+    generic map (
+      g_DATA_WIDTH  => 32,  --! Width of WB bus
+      g_RAM_ADDRESS_WIDTH => 3)  --! size of RAM = 2^ram_address_width
+    port map (
+      -- Wishbone signals
+      ipbus_clk_i => ipb_clk,
+      ipbus_i    => ipbw(5),
+      ipbus_o    => ipbr(5),
+      -- Data to capture.
+      reset_i => s_cbc_reset,
+      cap_clk_i => ipb_clk,
+      cap_d_i => cbc_data_i,
+      cap_go_i  => s_cap_trg,
+      cap_edge_i => ctrl_reg(8)
+      );
+
+  
+-- Slave 6: MAC host interface
+
+  slave6: entity work.ipbus_emac_hostbus
+    port map(
+      clk => ipb_clk,
+      reset => rst,
+      ipbus_in => ipbw(6),
+      ipbus_out => ipbr(6),
+      hostbus_out => hostbus_out,
+      hostbus_in => hostbus_in);
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU.ucf b/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..9ae9c0d9395019baee0834ba5947cb0cb19ee4f7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU.ucf
@@ -0,0 +1,176 @@
+NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125  TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET I6/s_clk_is_xtal TIG;
+
+NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=D14;
+NET dip_switch_i<1> LOC=E12;
+NET dip_switch_i<2> LOC=F12;
+NET dip_switch_i<3> LOC=V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
+
+# Main I2C bus
+NET "I2C_SCL_B"				LOC = "P11"; ##  C30 on FMC
+NET "I2C_SDA_B"				LOC = "N10"; ##  C31 on FMC
+
+#
+# I/O to devices under test
+
+
+#NET "BUSY_P_I<0>"				LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>"				LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>"				LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>"				LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>"				LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>"				LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>"				LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
+##NET "TRIGGERS_N_O<0>"				LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>"				LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
+##NET "TRIGGERS_N_O<1>"				LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>"				LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
+##NET "TRIGGERS_N_O<2>"				LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
+
+# Remove for now.
+#NET "SHUTTERS_P_O<0>"				LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
+##NET "SHUTTERS_N_O<0>"				LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>"				LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
+##NET "SHUTTERS_N_O<1>"				LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>"				LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
+##NET "SHUTTERS_N_O<2>"				LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>"			LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>"			LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>"				LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>"				LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>"				LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>"				LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>"				LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>"				LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>"				LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>"				LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>"				LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>"				LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+#NET "CFD_DISCR_P_I<0>"		LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
+#NET "CFD_DISCR_N_I<0>"		LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
+#
+#NET "CFD_DISCR_P_I<1>"		LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
+#NET "CFD_DISCR_N_I<1>"		LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+#
+#NET "CFD_DISCR_P_I<2>"		LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
+#NET "CFD_DISCR_N_I<2>"		LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
+#
+#NET "CFD_DISCR_P_I<3>"		LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
+#NET "CFD_DISCR_N_I<3>"		LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
+
+# Threshold comparator outputs
+NET "THRESHOLD_DISCR_P_I<0>"			LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
+NET "THRESHOLD_DISCR_N_I<0>"			LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
+
+NET "THRESHOLD_DISCR_P_I<1>"			LOC = "C13"; ## "FMC_LA03_P" , G9  on FMC
+NET "THRESHOLD_DISCR_N_I<1>"			LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+
+NET "THRESHOLD_DISCR_P_I<2>"			LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
+NET "THRESHOLD_DISCR_N_I<2>"			LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+
+NET "THRESHOLD_DISCR_P_I<3>"			LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
+NET "THRESHOLD_DISCR_N_I<3>"			LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+
+#NET "SPARE_P<2>"			LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>"			LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>"			LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>"			LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B"			LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"	
+NET "EXTCLK_N_B"			LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC ,  "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1"		LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2"		LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+
+# GPIO pins for debugging.
+#NET "GPIO_HDR<0>"                     LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
+#NET "GPIO_HDR<1>"                     LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
+#NET "GPIO_HDR<2>"                     LOC = "A3";  ## 5 on J13 (thru series R101 200 ohm)
+#NET "GPIO_HDR<3>"                     LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
+#NET "GPIO_HDR<4>"                     LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
+#NET "GPIO_HDR<5>"                     LOC = "B4";  ## 4 on J13 (thru series R98 200 ohm)
+#NET "GPIO_HDR<6>"                     LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
+#NET "GPIO_HDR<7>"                     LOC = "P12"; ## 8 on J13 (thru series R96 20
+
+NET "output_0_p[0]" LOC = D8;
+NET "output_0_p[1]" LOC = U15;
+NET "output_0_p[2]" LOC = G11;
+NET "output_0_n[0]" LOC = C8;
+NET "output_0_n[1]" LOC = V15;
+NET "output_0_n[2]" LOC = F10;
+NET "output_1_p[0]" LOC = T6;
+NET "output_1_p[1]" LOC = U8;
+NET "output_1_p[2]" LOC = F11;
+NET "output_1_n[0]" LOC = V6;
+NET "output_1_n[1]" LOC = V8;
+NET "output_1_n[2]" LOC = E11;
+NET "output_2_p[0]" LOC = M10;
+NET "output_2_p[1]" LOC = T4;
+NET "output_2_p[2]" LOC = B16;
+NET "output_2_n[0]" LOC = N9;
+NET "output_2_n[1]" LOC = V4;
+NET "output_2_n[2]" LOC = A16;
+NET "output_3_p[0]" LOC = D12;
+NET "output_3_p[1]" LOC = U11;
+NET "output_3_p[2]" LOC = E7;
+NET "output_3_n[0]" LOC = C12;
+NET "output_3_n[1]" LOC = V11;
+NET "output_3_n[2]" LOC = E8;
\ No newline at end of file
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU_v1a.ucf b/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..c605cd9d78f22933b891b835b8a4f3abd617dba7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/sp601_FMC_mTLU_v1a.ucf
@@ -0,0 +1,279 @@
+#
+# UCF for version 1a of updated mini-TLU
+#
+
+NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
+NET "sysclk_p_i" LOC = K15;
+NET "sysclk_p_i" IOSTANDARD = LVDS_25;
+NET "sysclk_p_i" DIFF_TERM = "TRUE";
+NET "sysclk_n_i" LOC = K16;
+NET "sysclk_n_i" IOSTANDARD = LVDS_25;
+NET "sysclk_n_i" DIFF_TERM = "TRUE";
+
+TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125  TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET "I6/s_clk_is_xtal" TIG;
+
+NET "leds_o[0]" LOC = E13;
+NET "leds_o[0]" IOSTANDARD = LVCMOS25;
+NET "leds_o[1]" LOC = C14;
+NET "leds_o[1]" IOSTANDARD = LVCMOS25;
+NET "leds_o[2]" LOC = C4;
+NET "leds_o[2]" IOSTANDARD = LVCMOS25;
+NET "leds_o[3]" LOC = A4;
+NET "leds_o[3]" IOSTANDARD = LVCMOS25;
+
+NET "dip_switch_i[0]" LOC = D14;
+NET "dip_switch_i[1]" LOC = E12;
+NET "dip_switch_i[2]" LOC = F12;
+NET "dip_switch_i[3]" LOC = V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx =   PADS("gmii_tx*");
+TIMEGRP "TG_gmii_tx" OFFSET = OUT  AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET "gmii_gtx_clk_o" LOC = A9;
+NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
+NET "gmii_gtx_clk_o" SLEW = FAST;
+NET "gmii_txd_o[0]" LOC = F8;
+NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[1]" LOC = G8;
+NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[2]" LOC = A6;
+NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[3]" LOC = B6;
+NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[4]" LOC = E6;
+NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[5]" LOC = F7;
+NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[6]" LOC = A5;
+NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[7]" LOC = C5;
+NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_en_o" LOC = B8;
+NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_er_o" LOC = A8;
+NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;
+
+NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
+NET "gmii_rx_clk_i" LOC = L16;
+NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
+TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
+OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
+NET "gmii_rxd_i[0]" LOC = M14;
+NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[1]" LOC = U18;
+NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[2]" LOC = U17;
+NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[3]" LOC = T18;
+NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[4]" LOC = T17;
+NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[5]" LOC = N16;
+NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[6]" LOC = N15;
+NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[7]" LOC = P18;
+NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_dv_i" LOC = N18;
+NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_er_i" LOC = P17;
+NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;
+
+NET "phy_rstb_o" LOC = L13;
+NET "phy_rstb_o" IOSTANDARD = LVCMOS25;
+
+# Main I2C bus
+##  C30 on FMC
+NET "i2c_scl_b" LOC = P11;
+##  C31 on FMC
+NET "i2c_sda_b" LOC = N10;
+
+#
+# I/O to devices under test
+
+#NET "BUSY_N_I<0>"  LOC = "P7"; ##  "FMC_LA19_N"  ,  H23  on FMC
+#NET "BUSY_N_I<1>"  LOC = "A2"; ##  "FMC_LA14_N"  ,  C19  on FMC
+#NET "BUSY_N_I<2>"  LOC = "C6"; ##  "FMC_LA12_N"  ,  G16  on FMC
+##  "FMC_LA19_P"  ,  H22  on FMC
+#NET "busy_p_i[0]" LOC = N6;
+##  "FMC_LA14_P"  ,  C18  on FMC
+#NET "busy_p_i[1]" LOC = B2;
+##  "FMC_LA12_P"  ,  G15  on FMC
+#NET "busy_p_i[2]" LOC = D6;
+
+#NET "TRIGGERS_N_O<0>"  LOC = "P8"; ##  "FMC_LA20_N"  ,  G22  on FMC
+#NET "TRIGGERS_N_O<1>"  LOC = "A13"; ##  "FMC_LA03_N"  ,  G10  on FMC
+#NET "TRIGGERS_N_O<2>"  LOC = "A7"; ##  "FMC_LA16_N"  ,  G19  on FMC
+##  "FMC_LA20_P"  ,  G21  on FMC
+#NET "triggers_p_o[0]" LOC = N7;
+##  "FMC_LA03_P"  ,  G9  on FMC
+#NET "triggers_p_o[1]" LOC = C13;
+##  "FMC_LA16_P"  ,  G18  on FMC
+#NET "triggers_p_o[2]" LOC = C7;
+
+# Remove shutters ( also known as SPARE ) for now
+#NET "SPARE_N_O<1>"  LOC = "E11"; ##  "FMC_LA08_N"  ,  G13  on FMC
+#NET "SPARE_N_O<2>"  LOC = "A12"; ##  "FMC_LA11_N"  ,  H17  on FMC
+#NET "SPARE_P_O<1>"  LOC = "F11"; ##  "FMC_LA08_P"  ,  G12  on FMC
+#NET "SPARE_P_O<2>"  LOC = "B12"; ##  "FMC_LA11_P"  ,  H16  on FMC
+
+# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
+#NET "DUT_CLK_N_I<0>"  LOC = "V4"; ##  "FMC_LA21_N"  ,  H26  on FMC
+#NET "DUT_CLK_N_I<1>"  LOC = "T11"; ##  "FMC_LA27_N"  ,  C27  on FMC
+#NET "DUT_CLK_N_I<2>"  LOC = "A15"; ##  "FMC_LA02_N"  ,  H8  on FMC
+##  "FMC_LA27_P"  ,  C26  on FMC
+##  "FMC_LA02_P"  ,  H7  on FMC
+##  "FMC_LA21_P"  ,  H25  on FMC
+
+# Labelled CONT on schematic.
+#NET "RESET_OR_CLK_N_O<0>"  LOC = "T7"; ##  "FMC_LA22_N"  ,  G25  on FMC
+#NET "RESET_OR_CLK_N_O<1>"  LOC = "T10"; ##  "FMC_LA18_CC_N"  ,  C23  on FMC
+#NET "RESET_OR_CLK_N_O<2>"  LOC = "E8"; ##  "FMC_LA07_N"  ,  H14  on FMC
+##  "FMC_LA22_P"  ,  G24  on FMC
+#NET "reset_or_clk_p_o[0]" LOC = R7;
+##  "FMC_LA18_CC_P"  ,  C22  on FMC
+#NET "reset_or_clk_p_o[1]" LOC = R10;
+##  "FMC_LA07_P"  ,  H13  on FMC
+#NET "reset_or_clk_p_o[2]" LOC = E7;
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+##  "FMC_LA32_N"  ,  H38  on FMC
+NET "cfd_discr_n_i[0]" LOC = V15;
+##  "FMC_LA30_N"  ,  H35  on FMC
+NET "cfd_discr_n_i[1]" LOC = V12;
+##  "FMC_LA28_N"  ,  H32  on FMC
+NET "cfd_discr_n_i[2]" LOC = V11;
+##  "FMC_LA24_N"  ,  H29  on FMC
+NET "cfd_discr_n_i[3]" LOC = V8;
+##  "FMC_LA32_P"  ,  H37  on FMC
+NET "cfd_discr_p_i[0]" LOC = U15;
+##  "FMC_LA30_P"  ,  H34  on FMC
+NET "cfd_discr_p_i[1]" LOC = T12;
+##  "FMC_LA28_P"  ,  H31  on FMC
+NET "cfd_discr_p_i[2]" LOC = U11;
+##  "FMC_LA24_P"  ,  H28  on FMC
+NET "cfd_discr_p_i[3]" LOC = U8;
+
+# Threshold comparator outputs
+##  "FMC_LA33_N"  ,  G37  on FMC
+NET "threshold_discr_n_i[0]" LOC = N9;
+##  "FMC_LA31_N"  ,  G34  on FMC
+NET "threshold_discr_n_i[1]" LOC = V6;
+##  "FMC_LA29_N"  ,  G31  on FMC
+NET "threshold_discr_n_i[2]" LOC = N8;
+##  "FMC_LA25_N"  ,  G28  on FMC
+NET "threshold_discr_n_i[3]" LOC = N11;
+##  "FMC_LA33_P"  ,  G36  on FMC
+NET "threshold_discr_p_i[0]" LOC = M10;
+##  "FMC_LA31_P"  ,  G33  on FMC
+NET "threshold_discr_p_i[1]" LOC = T6;
+##  "FMC_LA29_P"  ,  G30  on FMC
+NET "threshold_discr_p_i[2]" LOC = M8;
+##  "FMC_LA25_P"  ,  G27  on FMC
+NET "threshold_discr_p_i[3]" LOC = M11;
+
+############
+# External clock pins
+## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"	
+NET "extclk_p_b" LOC = C10;
+## "FMC_CLK0_M2C_N" , H5 on FMC ,  "FRONT_PANEL_CLK_N"
+NET "extclk_n_b" LOC = A10;
+
+
+#NET "HDMI_POWER_ENABLE1"  LOC = "B16"; ##  "FMC_LA04_P"  ,  H10  on FMC
+#NET "HDMI_POWER_ENABLE2"  LOC = "F9"; ##  "FMC_LA15_N"  ,  H20  on FMC
+
+# GPIO pins for debugging.
+## 1 on J13 (thru series R100 200 ohm)
+#NET "gpio_hdr[0]" LOC = N17;
+## 3 on J13 (thru series R102 200 ohm)
+#NET "gpio_hdr[1]" LOC = M18;
+## 5 on J13 (thru series R101 200 ohm)
+#NET "gpio_hdr[2]" LOC = A3;
+## 7 on J13 (thru series R103 200 ohm)
+#NET "gpio_hdr[3]" LOC = L15;
+## 2 on J13 (thru series R99 200 ohm)
+#NET "gpio_hdr[4]" LOC = F15;
+## 4 on J13 (thru series R98 200 ohm)
+#NET "gpio_hdr[5]" LOC = B4;
+## 6 on J13 (thru series R97 200 ohm)
+#NET "gpio_hdr[6]" LOC = F13;
+## 8 on J13 (thru series R96 20
+#NET "gpio_hdr[7]" LOC = P12;
+
+
+#NET "busy_p_i[2]" PULLDOWN;
+#NET "busy_p_i[1]" PULLDOWN;
+#NET "busy_p_i[0]" PULLDOWN;
+
+# PlanAhead Generated miscellaneous constraints 
+
+NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[0]" KEEP = "TRUE";
+
+# PlanAhead Generated physical constraints 
+
+NET "output_0_p[0]" LOC = N7;
+NET "output_0_p[1]" LOC = C13;
+NET "output_0_p[2]" LOC = C7;
+NET "output_0_n[0]" LOC = P8;
+NET "output_0_n[1]" LOC = A13;
+NET "output_0_n[2]" LOC = A7;
+NET "output_1_p[0]" LOC = R11;
+NET "output_1_p[1]" LOC = C15;
+NET "output_1_p[2]" LOC = T4;
+NET "output_1_n[0]" LOC = T11;
+NET "output_1_n[1]" LOC = A15;
+NET "output_1_n[2]" LOC = V4;
+NET "output_2_p[0]" LOC = R7;
+NET "output_2_p[1]" LOC = R10;
+NET "output_2_p[2]" LOC = E7;
+NET "output_2_n[0]" LOC = T7;
+NET "output_2_n[1]" LOC = T10;
+NET "output_2_n[2]" LOC = E8;
+NET "output_3_p[0]" LOC = N6;
+NET "output_3_p[1]" LOC = B2;
+NET "output_3_p[2]" LOC = D6;
+NET "output_3_n[0]" LOC = P7;
+NET "output_3_n[1]" LOC = A2;
+NET "output_3_n[2]" LOC = C6;
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU.ucf b/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..66bb1db813ae7648f2743e5470e826095cf77eb8
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU.ucf
@@ -0,0 +1,164 @@
+NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+#NET Reset_i LOC=F3; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125  TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+
+NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=C18;
+NET dip_switch_i<1> LOC=Y6;
+NET dip_switch_i<2> LOC=W6;
+NET dip_switch_i<3> LOC=E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9  |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+
+
+# Main I2C bus
+#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
+#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
+NET "I2C_SDA_B"				LOC = "R22"; ##  C30 on FMC
+NET "I2C_SCL_B"				LOC = "T21"; ##  C31 on FMC
+
+#
+# I/O to devices under test
+
+#NET "BUSY_P_I<0>"				LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>"				LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>"				LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>"				LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>"				LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>"				LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>"				LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>"				LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>"				LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>"				LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>"				LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>"				LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
+
+#NET "SHUTTERS_P_O<0>"				LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
+#NET "SHUTTERS_N_O<0>"				LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>"				LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "SHUTTERS_N_O<1>"				LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>"				LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
+#NET "SHUTTERS_N_O<2>"				LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>"			LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>"			LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>"				LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>"				LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>"				LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>"				LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>"				LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>"				LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>"				LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>"				LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>"				LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>"				LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger inputs
+# first constant-fraction-discrimiator comparator outputs
+NET "CFD_DISCR_P_I<0>"		LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "CFD_DISCR_N_I<0>"		LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
+NET "CFD_DISCR_P_I<1>"		LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
+NET "CFD_DISCR_N_I<1>"		LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
+NET "CFD_DISCR_P_I<2>"		LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
+NET "CFD_DISCR_N_I<2>"		LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
+NET "CFD_DISCR_P_I<3>"		LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
+NET "CFD_DISCR_N_I<3>"		LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
+#NET "CFD_DISCR_P_I<2>"		LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "CFD_DISCR_N_I<2>"		LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "CFD_DISCR_P_I<3>"		LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
+#NET "CFD_DISCR_N_I<3>"		LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
+# then threshold comparator outputs
+# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
+NET "THRESHOLD_DISCR_P_I<0>"			LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
+#NET "THRESHOLD_DISCR_N_I<0>"			LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "THRESHOLD_DISCR_P_I<1>"			LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
+#NET "THRESHOLD_DISCR_N_I<1>"			LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
+NET "THRESHOLD_DISCR_P_I<2>"			LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
+#NET "THRESHOLD_DISCR_N_I<2>"			LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
+NET "THRESHOLD_DISCR_P_I<3>"			LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+#NET "THRESHOLD_DISCR_N_I<3>"			LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+
+#NET "SPARE_P<2>"			LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>"			LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>"			LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>"			LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B"			LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"	
+NET "EXTCLK_N_B"			LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC ,  "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1"		LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2"		LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
+
+
+NET "output_0_p[0]" LOC = H10;
+NET "output_0_p[1]" LOC = W17;
+NET "output_0_p[2]" LOC = F7;
+NET "output_0_n[0]" LOC = H11;
+NET "output_0_n[1]" LOC = Y18;
+NET "output_0_n[2]" LOC = F8;
+NET "output_1_p[0]" LOC = U16;
+NET "output_1_p[1]" LOC = V11;
+NET "output_1_p[2]" LOC = C19;
+NET "output_1_n[0]" LOC = V15;
+NET "output_1_n[1]" LOC = W11;
+NET "output_1_n[2]" LOC = A19;
+NET "output_2_p[0]" LOC = Y17;
+NET "output_2_p[1]" LOC = AA14;
+NET "output_2_p[2]" LOC = B20;
+NET "output_2_n[0]" LOC = AB17;
+NET "output_2_n[1]" LOC = AB14;
+NET "output_2_n[2]" LOC = A20;
+NET "output_3_p[0]" LOC = D4;
+NET "output_3_p[1]" LOC = AA16;
+NET "output_3_p[2]" LOC = B2;
+NET "output_3_n[0]" LOC = D5;
+NET "output_3_n[1]" LOC = AB16;
+NET "output_3_n[2]" LOC = A2;
\ No newline at end of file
diff --git a/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU_v1a.ucf b/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..994eafd1308f29d2872304e56ca066a2c6155b34
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/test/sp605_FMC_mTLU_v1a.ucf
@@ -0,0 +1,164 @@
+NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+#NET Reset_i LOC=F3; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125  TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+
+NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=C18;
+NET dip_switch_i<1> LOC=Y6;
+NET dip_switch_i<2> LOC=W6;
+NET dip_switch_i<3> LOC=E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9  |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+
+
+# Main I2C bus
+#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
+#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
+NET "I2C_SDA_B"				LOC = "R22"; ##  C30 on FMC
+NET "I2C_SCL_B"				LOC = "T21"; ##  C31 on FMC
+
+#
+# I/O to devices under test
+
+#NET "BUSY_P_I<0>"				LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>"				LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>"				LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>"				LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>"				LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>"				LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>"				LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>"				LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>"				LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>"				LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>"				LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>"				LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
+
+#NET "SHUTTERS_P_O<0>"				LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
+#NET "SHUTTERS_N_O<0>"				LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>"				LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "SHUTTERS_N_O<1>"				LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>"				LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
+#NET "SHUTTERS_N_O<2>"				LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>"			LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>"			LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>"				LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>"				LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>"				LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>"				LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>"				LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>"				LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>"				LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>"				LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>"				LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>"				LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger inputs
+# first constant-fraction-discrimiator comparator outputs
+#NET "CFD_DISCR_P_I<0>"		LOC = "W17"; ## "FMC_LA00_CC_P" , G6 on FMC
+#NET "CFD_DISCR_N_I<0>"		LOC = "Y18"; ## "FMC_LA00_CC_N" , G7 on FMC
+#NET "CFD_DISCR_P_I<1>"		LOC = "Y15"; ## "FMC_LA14_P" , C18 on FMC
+#NET "CFD_DISCR_N_I<1>"		LOC = "AB15"; ## "FMC_LA14_N" , C19 on FMC
+#NET "CFD_DISCR_P_I<2>"		LOC = "AA16"; ## "FMC_LA12_P" , C22 on FMC
+#NET "CFD_DISCR_N_I<2>"		LOC = "AB16"; ## "FMC_LA12_N" , C23 on FMC
+#NET "CFD_DISCR_P_I<3>"		LOC = "AA14"; ## "FMC_LA16_P" , C26 on FMC
+#NET "CFD_DISCR_N_I<3>"		LOC = "AB14"; ## "FMC_LA16_N" , C27 on FMC
+##NET "CFD_DISCR_P_I<2>"		LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+##NET "CFD_DISCR_N_I<2>"		LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+##NET "CFD_DISCR_P_I<3>"		LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
+##NET "CFD_DISCR_N_I<3>"		LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
+# then threshold comparator outputs
+# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
+NET "THRESHOLD_DISCR_P_I<0>"			LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
+#NET "THRESHOLD_DISCR_N_I<0>"			LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "THRESHOLD_DISCR_P_I<1>"			LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
+#NET "THRESHOLD_DISCR_N_I<1>"			LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
+NET "THRESHOLD_DISCR_P_I<2>"			LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
+#NET "THRESHOLD_DISCR_N_I<2>"			LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
+NET "THRESHOLD_DISCR_P_I<3>"			LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+#NET "THRESHOLD_DISCR_N_I<3>"			LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+
+#NET "SPARE_P<2>"			LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>"			LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>"			LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>"			LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B"			LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"	
+NET "EXTCLK_N_B"			LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC ,  "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1"		LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2"		LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
+
+
+NET "output_0_p[0]" LOC = R9;
+NET "output_0_p[1]" LOC = B18;
+NET "output_0_p[2]" LOC = C5;
+NET "output_0_n[0]" LOC = R8;
+NET "output_0_n[1]" LOC = A18;
+NET "output_0_n[2]" LOC = A5;
+NET "output_1_p[0]" LOC = AA10;
+NET "output_1_p[1]" LOC = G8;
+NET "output_1_p[2]" LOC = V11;
+NET "output_1_n[0]" LOC = AB10;
+NET "output_1_n[1]" LOC = F9;
+NET "output_1_n[2]" LOC = W11;
+NET "output_2_p[0]" LOC = V7;
+NET "output_2_p[1]" LOC = T12;
+NET "output_2_p[2]" LOC = B2;
+NET "output_2_n[0]" LOC = W8;
+NET "output_2_n[1]" LOC = U12;
+NET "output_2_n[2]" LOC = A2;
+NET "output_3_p[0]" LOC = R11;
+NET "output_3_p[1]" LOC = C17;
+NET "output_3_p[2]" LOC = H13;
+NET "output_3_n[0]" LOC = T11;
+NET "output_3_n[1]" LOC = A17;
+NET "output_3_n[2]" LOC = G13;
\ No newline at end of file
diff --git a/AIDA_tlu/legacy/TLU_v1c/top_extphy_struct.vhd b/AIDA_tlu/legacy/TLU_v1c/top_extphy_struct.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..da5e79646faccf7e13f3da48a3166f01552d636c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1c/top_extphy_struct.vhd
@@ -0,0 +1,668 @@
+-- VHDL Entity work.top_extphy.symbol
+--
+-- Created:
+--          by - phdgc.users (voltar.phy.bris.ac.uk)
+--          at - 11:30:28 09/03/15
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY top_extphy IS
+   GENERIC( 
+      g_NUM_DUTS            : positive := 3;
+      g_NUM_TRIG_INPUTS     : positive := 4;
+      g_NUM_EXT_SLAVES      : positive := 8;      --! Number of slaves outside IPBus interface
+      g_EVENT_DATA_WIDTH    : positive := 64;
+      g_IPBUS_WIDTH         : positive := 32;
+      g_NUM_EDGE_INPUTS     : positive := 4;
+      g_SPILL_COUNTER_WIDTH : positive := 12;
+      g_BUILD_SIMULATED_MAC : integer  := 0
+   );
+   PORT( 
+      busy_n_i            : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      busy_p_i            : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Busy lines from DUTs ( active high )
+      cfd_discr_n_i       : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      cfd_discr_p_i       : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      dip_switch_i        : IN     std_logic_vector (3 DOWNTO 0);
+      gmii_rx_clk_i       : IN     std_logic;
+      gmii_rx_dv_i        : IN     std_logic;
+      gmii_rx_er_i        : IN     std_logic;
+      gmii_rxd_i          : IN     std_logic_vector (7 DOWNTO 0);
+      sysclk_n_i          : IN     std_logic;                                        --! 200 MHz xtal clock
+      sysclk_p_i          : IN     std_logic;
+      threshold_discr_n_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      threshold_discr_p_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+      gmii_gtx_clk_o      : OUT    std_logic;
+      gmii_tx_en_o        : OUT    std_logic;
+      gmii_tx_er_o        : OUT    std_logic;
+      gmii_txd_o          : OUT    std_logic_vector (7 DOWNTO 0);
+      gpio_hdr            : OUT    std_logic_vector (3 DOWNTO 0);
+      leds_o              : OUT    std_logic_vector (3 DOWNTO 0);
+      phy_rstb_o          : OUT    std_logic;
+      reset_or_clk_n_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      reset_or_clk_p_o    : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! T0 synchronization signal
+      shutter_to_dut_n_o  : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);         --! Shutter output
+      shutter_to_dut_p_o  : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);         --! Shutter output
+      triggers_n_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      triggers_p_o        : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Trigger lines to DUT
+      dut_clk_n_o         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+      dut_clk_p_o         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);         --! Clock to DUT (P)
+      extclk_n_b          : INOUT  std_logic;
+      extclk_p_b          : INOUT  std_logic;                                        --! either external clock in, or a clock being driven out
+      i2c_scl_b           : INOUT  std_logic;
+      i2c_sda_b           : INOUT  std_logic
+   );
+
+-- Declarations
+
+END ENTITY top_extphy ;
+
+--
+-- VHDL Architecture work.top_extphy.struct
+--
+-- Created:
+--          by - phdgc.users (voltar.phy.bris.ac.uk)
+--          at - 11:30:28 09/03/15
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2013.1b (Build 2)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+LIBRARY work;
+USE work.ipbus.all;
+-- USE work.emac_hostbus_decl.all;
+
+USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;
+USE work.ipbus_reg_types.all;
+
+
+ARCHITECTURE struct OF top_extphy IS
+
+   -- Architecture declarations
+
+   -- Internal signal declarations
+   SIGNAL T0_o                  : std_logic;
+   SIGNAL buffer_full_o         : std_logic;                                             --! Goes high when event buffer almost full
+   SIGNAL clk_16x_logic         : std_logic;                                             -- 640MHz clock
+   SIGNAL clk_4x_logic          : std_logic;                                             --! normally 160MHz
+   SIGNAL clk_logic_xtal        : std_logic;                                             -- ! 40MHz clock from onboard xtal
+   SIGNAL data_strobe           : std_logic;                                             -- goes high when data ready to load into event buffer
+   SIGNAL dout                  : std_logic;
+   SIGNAL dout1                 : std_logic;
+   SIGNAL event_data            : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+   SIGNAL ipbr                  : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0);           --! IPBus read signals
+   SIGNAL ipbus_clk             : std_logic;
+   SIGNAL ipbus_reset           : std_logic;                                             -- ! IPBus reset to slaves
+   SIGNAL ipbw                  : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0);           --! IBus write signals
+   SIGNAL logic_clocks_reset    : std_logic;                                             -- Goes high to reset counters etc. Sync with clk_4x_logic
+   SIGNAL logic_reset           : std_logic;
+   SIGNAL overall_trigger       : std_logic;                                             --! goes high to load trigger data
+   SIGNAL overall_veto          : std_logic;                                             --! Halts triggers when high
+   SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+   SIGNAL postVetotrigger       : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        -- ! High when trigger from input connector active and enabled
+   --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+   SIGNAL rst_fifo_o            : std_logic;                                             --! rst signal to first level fifos
+   SIGNAL s_edge_fall_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+   SIGNAL s_edge_falling        : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when falling edge
+   SIGNAL s_edge_rise_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+   SIGNAL s_edge_rising         : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when rising edge
+   SIGNAL s_i2c_scl_enb         : std_logic;
+   SIGNAL s_i2c_sda_enb         : std_logic;
+   SIGNAL s_shutter             : std_logic;                                             --! shutter signal from TimePix, retimed onto local clock
+   SIGNAL s_triggerLogic_reset  : std_logic;
+   SIGNAL shutter_cnt_i         : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+   SIGNAL shutter_i             : std_logic;
+   SIGNAL spill_cnt_i           : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+   SIGNAL spill_i               : std_logic;
+   SIGNAL strobe_16x_logic      : std_logic;                                             --! Pulses one cycle every 4 of 16x clock.
+   SIGNAL strobe_4x_logic       : std_logic;                                             -- one pulse every 4 cycles of clk_4x
+   SIGNAL trigger_count         : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+   SIGNAL trigger_times         : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+   SIGNAL triggers              : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+   SIGNAL veto_o                : std_logic;                                             --! goes high when one or more DUT are busy
+
+
+   -- Component Declarations
+   COMPONENT DUTInterfaces
+   GENERIC (
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT (
+      clk_4x_logic_i          : IN     std_logic ;
+      strobe_4x_logic_i       : IN     std_logic ;                                  --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic ;                                  --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic ;                                  --! Synchronization signal. Passed TO DUT pins
+      shutter_to_dut_i        : IN     std_logic ;                                  --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic ;
+      ipbus_i                 : IN     ipb_wbus ;                                   --! Signals from IPBus core TO slave
+      ipbus_reset_i           : IN     std_logic ;
+      ipbus_o                 : OUT    ipb_rbus ;                                   --! signals from slave TO IPBus core
+      -- Signals to/from DUT
+      busy_from_dut_n_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+      busy_from_dut_p_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+      clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! clocks trigger data when in EUDET mode
+      clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! clocks trigger data when in EUDET mode
+      reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! Either reset line or trigger
+      reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! Either reset line or trigger
+      trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! Trigger output
+      trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! Trigger output
+      shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);    --! Shutter output. Output 0 (RJ45) has no shutter signal
+      shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);    --! Shutter output
+      veto_o                  : OUT    std_logic                                    --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+   END COMPONENT DUTInterfaces;
+   COMPONENT IPBusInterface
+   GENERIC (
+      NUM_EXT_SLAVES           : positive := 5;
+      BUILD_SIMULATED_ETHERNET : integer  := 0      --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
+   );
+   PORT (
+      gmii_rx_clk_i    : IN     std_logic ;
+      gmii_rx_dv_i     : IN     std_logic ;
+      gmii_rx_er_i     : IN     std_logic ;
+      gmii_rxd_i       : IN     std_logic_vector (7 DOWNTO 0);
+      ipbr_i           : IN     ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
+      sysclk_n_i       : IN     std_logic ;
+      sysclk_p_i       : IN     std_logic ;                                 -- ! 200 MHz xtal clock
+      clocks_locked_o  : OUT    std_logic ;
+      gmii_gtx_clk_o   : OUT    std_logic ;
+      gmii_tx_en_o     : OUT    std_logic ;
+      gmii_tx_er_o     : OUT    std_logic ;
+      gmii_txd_o       : OUT    std_logic_vector (7 DOWNTO 0);
+      ipb_clk_o        : OUT    std_logic ;                                 -- ! IPBus clock TO slaves
+      ipb_rst_o        : OUT    std_logic ;                                 -- ! IPBus reset TO slaves
+      ipbw_o           : OUT    ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
+      onehz_o          : OUT    std_logic ;
+      phy_rstb_o       : OUT    std_logic ;
+      dip_switch_i     : IN     std_logic_vector (3 DOWNTO 0);
+      clk_logic_xtal_o : OUT    std_logic 
+   );
+   END COMPONENT IPBusInterface;
+   COMPONENT T0_Shutter_Iface
+   PORT (
+      clk_4x_i      : IN     std_logic;
+      clk_4x_strobe : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;
+      T0_o          : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus;
+      shutter_o     : OUT    std_logic
+   );
+   END COMPONENT T0_Shutter_Iface;
+   COMPONENT eventBuffer
+   GENERIC (
+      g_EVENT_DATA_WIDTH   : positive := 64;
+      g_IPBUS_WIDTH        : positive := 32;
+      g_READ_COUNTER_WIDTH : positive := 16
+   );
+   PORT (
+      clk_4x_logic_i    : IN     std_logic ;
+      data_strobe_i     : IN     std_logic ;                                     -- Indicates data TO transfer
+      event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+      ipbus_clk_i       : IN     std_logic ;
+      ipbus_i           : IN     ipb_wbus ;
+      ipbus_reset_i     : IN     std_logic ;
+      strobe_4x_logic_i : IN     std_logic ;
+      --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+      rst_fifo_o        : OUT    std_logic ;                                     --! rst signal TO first level fifos
+      buffer_full_o     : OUT    std_logic ;                                     --! Goes high when event buffer almost full
+      ipbus_o           : OUT    ipb_rbus ;
+      logic_reset_i     : IN     std_logic                                       -- reset buffers when high. Synch withclk_4x_logic
+   );
+   END COMPONENT eventBuffer;
+   COMPONENT eventFormatter
+   GENERIC (
+      g_EVENT_DATA_WIDTH   : positive := 64;
+      g_IPBUS_WIDTH        : positive := 32;
+      g_COUNTER_TRIG_WIDTH : positive := 32;
+      g_COUNTER_WIDTH      : positive := 12;
+      g_EVTTYPE_WIDTH      : positive := 4;      --! Width of the event type word
+      --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+      g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+      g_NUM_TRIG_INPUTS    : positive := 5       --! Number of trigger inputs
+   );
+   PORT (
+      clk_4x_logic_i         : IN     std_logic ;                                         --! Rising edge active
+      ipbus_clk_i            : IN     std_logic ;
+      logic_strobe_i         : IN     std_logic ;                                         --! Pulses high once every 4 cycles of clk_4x_logic
+      logic_reset_i          : IN     std_logic ;                                         --! goes high TO reset counters. Synchronous with clk_4x_logic
+      rst_fifo_i             : IN     std_logic ;                                         --! Goes high TO reset FIFOs
+      buffer_full_i          : IN     std_logic ;                                         --! Goes high when output fifo full
+      trigger_i              : IN     std_logic ;                                         --! goes high TO load trigger data. One cycle of clk_4x_logic
+      trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);  --! Array of trigger times ( w.r.t. logic_strobe)
+      trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);    --! high for each input that "fired"
+      trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
+      shutter_i              : IN     std_logic ;
+      shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      spill_i                : IN     std_logic ;
+      spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when rising edge
+      edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when falling edge
+      edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+      edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+      ipbus_i                : IN     ipb_wbus ;
+      ipbus_o                : OUT    ipb_rbus ;
+      data_strobe_o          : OUT    std_logic ;                                         --! goes high when data ready TO load into event buffer
+      event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+      reset_timestamp_i      : IN     std_logic ;                                         --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+      reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+   );
+   END COMPONENT eventFormatter;
+   COMPONENT i2c_master
+   PORT (
+      i2c_scl_i     : IN     std_logic;
+      i2c_sda_i     : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;
+      ipbus_reset_i : IN     std_logic;
+      i2c_scl_enb_o : OUT    std_logic;
+      i2c_sda_enb_o : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus
+   );
+   END COMPONENT i2c_master;
+   COMPONENT logic_clocks
+   GENERIC (
+      g_USE_EXTERNAL_CLK : integer := 1
+   );
+   PORT (
+      ipbus_clk_i           : IN     std_logic ;
+      ipbus_i               : IN     ipb_wbus ;
+      ipbus_reset_i         : IN     std_logic ;
+      Reset_i               : IN     std_logic ;
+      clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+      clk_16x_logic_o       : OUT    std_logic ; -- 640MHz clock
+      clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+      ipbus_o               : OUT    ipb_rbus ;
+      strobe_16x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+      strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+      extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+      extclk_n_b            : INOUT  std_logic ;
+      DUT_clk_o             : OUT    std_logic ;
+      logic_clocks_locked_o : OUT    std_logic ;
+      logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+   );
+   END COMPONENT logic_clocks;
+   COMPONENT triggerInputs
+   GENERIC (
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT (
+      cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Inputs from constant-fraction discriminators
+      cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Input from CFD
+      clk_4x_logic         : IN     std_logic ;                                        --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic ;                                        --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+      reset_i              : IN     std_logic ;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when falling edge
+      ipbus_clk_i          : IN     std_logic ;
+      ipbus_reset_i        : IN     std_logic ;
+      ipbus_i              : IN     ipb_wbus ;                                         --! Signals from IPBus core TO slave
+      ipbus_o              : OUT    ipb_rbus ;                                         --! signals from slave TO IPBus core
+      clk_16x_logic_i      : IN     std_logic ;                                        --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                          --! Pulses one cycle every 4 of 16x clock.
+   );
+   END COMPONENT triggerInputs;
+   COMPONENT triggerLogic
+   GENERIC (
+      g_NUM_INPUTS  : positive := 4;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT (
+      clk_4x_logic_i      : IN     std_logic ;                                   -- ! Rising edge active
+      ipbus_clk_i         : IN     std_logic ;
+      ipbus_i             : IN     ipb_wbus ;                                    -- Signals from IPBus core TO slave
+      ipbus_reset_i       : IN     std_logic ;
+      logic_reset_i       : IN     std_logic ;                                   -- active high. Synchronous with clk_4x_logic
+      logic_strobe_i      : IN     std_logic ;                                   -- ! Pulses high once every 4 cycles of clk_4x_logic
+      trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active
+      trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+      veto_i              : IN     std_logic ;                                   -- ! Halts triggers when high
+      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active and enabled
+      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+      event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  -- starts at one. Increments for each post_veto_trigger
+      ipbus_o             : OUT    ipb_rbus ;                                    -- signals from slave TO IPBus core
+      post_veto_trigger_o : OUT    std_logic ;                                   -- ! goes high when trigger passes
+      pre_veto_trigger_o  : OUT    std_logic ;
+      trigger_active_o    : OUT    std_logic                                     --! Goes high when triggers are active ( ie. not veoted)
+   );
+   END COMPONENT triggerLogic;
+
+   -- Optional embedded configurations
+   -- pragma synthesis_off
+   FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+   FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+   FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
+   FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+   FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+   FOR ALL : i2c_master USE ENTITY work.i2c_master;
+   FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+   FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
+   FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+   -- pragma synthesis_on
+
+
+BEGIN
+   -- Architecture concurrent statements
+   -- HDL Embedded Text Block 1 i2c_tristate
+   -- eb1 1
+   i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+   i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+   
+                               
+
+
+   -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+   logic_clocks_reset <= '0';
+
+   -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+   spill_i <= '0';
+
+   -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+   spill_cnt_i <= (OTHERS => '0');
+
+   -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+   shutter_i <= '0';
+
+   -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+   shutter_cnt_i <= (OTHERS => '0');
+
+   -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
+   dout1 <= '0';
+
+   -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
+   dout <= '0';
+
+   -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
+   gpio_hdr <= dout1 & dout & s_shutter & T0_o;
+
+   -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+   overall_veto <= buffer_full_o OR veto_o;
+
+   -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
+   s_triggerLogic_reset <= logic_reset OR T0_o;
+
+   -- Instance port mappings.
+   --! @brief Interfaces to Device Under Test (DUT) connectors.
+   --!
+   --! @author David Cussans , David.Cussans@bristol.ac.uk
+   --!
+   --! @date 15:09:50 11/09/12
+   --!
+   --! @version v0.1
+   --!
+   --! @details
+   --! \n\n IPBUS Address map:
+   --! \n (Decodes 4 bits)
+   --! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+   --! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+   --! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+   --! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
+   --! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+   --! \li 0x00000008 - DUT mask ( read )
+   --!
+   --! DUT(0) = RJ45 ( J3 )\n
+   --! DUT(1) = HDMI ( J1 ) , furthest from RJ45\n
+   --! DUT(2) = HDMI ( J2) , closest to RJ45\n
+   --!
+   --! <b>Modified by:</b>\n
+   --! -----------------------------------------------------------------------------
+   --! \n\n<b>Last changes:</b>\n
+   -------------------------------------------------------------------------------
+   -- todo  Indicate if the DUT works under AIDA/EUDET style
+   --
+   I0 : DUTInterfaces
+      GENERIC MAP (
+         g_NUM_DUTS    => g_NUM_DUTS,
+         g_IPBUS_WIDTH => g_IPBUS_WIDTH
+      )
+      PORT MAP (
+         clk_4x_logic_i          => clk_4x_logic,
+         strobe_4x_logic_i       => strobe_4x_logic,
+         trigger_counter_i       => trigger_count,
+         trigger_i               => overall_trigger,
+         reset_or_clk_to_dut_i   => T0_o,
+         shutter_to_dut_i        => s_shutter,
+         ipbus_clk_i             => ipbus_clk,
+         ipbus_i                 => ipbw(0),
+         ipbus_reset_i           => ipbus_reset,
+         ipbus_o                 => ipbr(0),
+         busy_from_dut_n_i       => busy_n_i,
+         busy_from_dut_p_i       => busy_p_i,
+         clk_to_dut_n_io         => dut_clk_n_o,
+         clk_to_dut_p_io         => dut_clk_p_o,
+         reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+         reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+         trigger_to_dut_n_o      => triggers_n_o,
+         trigger_to_dut_p_o      => triggers_p_o,
+         shutter_to_dut_n_o      => shutter_to_dut_n_o,
+         shutter_to_dut_p_o      => shutter_to_dut_p_o,
+         veto_o                  => veto_o
+      );
+   I4 : IPBusInterface
+      GENERIC MAP (
+         NUM_EXT_SLAVES           => g_NUM_EXT_SLAVES,
+         BUILD_SIMULATED_ETHERNET => g_BUILD_SIMULATED_MAC         --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
+      )
+      PORT MAP (
+         gmii_rx_clk_i    => gmii_rx_clk_i,
+         gmii_rx_dv_i     => gmii_rx_dv_i,
+         gmii_rx_er_i     => gmii_rx_er_i,
+         gmii_rxd_i       => gmii_rxd_i,
+         ipbr_i           => ipbr,
+         sysclk_n_i       => sysclk_n_i,
+         sysclk_p_i       => sysclk_p_i,
+         clocks_locked_o  => leds_o(2),
+         gmii_gtx_clk_o   => gmii_gtx_clk_o,
+         gmii_tx_en_o     => gmii_tx_en_o,
+         gmii_tx_er_o     => gmii_tx_er_o,
+         gmii_txd_o       => gmii_txd_o,
+         ipb_clk_o        => ipbus_clk,
+         ipb_rst_o        => ipbus_reset,
+         ipbw_o           => ipbw,
+         onehz_o          => leds_o(3),
+         phy_rstb_o       => phy_rstb_o,
+         dip_switch_i     => dip_switch_i,
+         clk_logic_xtal_o => clk_logic_xtal
+      );
+   I10 : T0_Shutter_Iface
+      PORT MAP (
+         clk_4x_i      => clk_4x_logic,
+         clk_4x_strobe => strobe_4x_logic,
+         T0_o          => T0_o,
+         shutter_o     => s_shutter,
+         ipbus_clk_i   => ipbus_clk,
+         ipbus_i       => ipbw(7),
+         ipbus_o       => ipbr(7)
+      );
+   I5 : eventBuffer
+      GENERIC MAP (
+         g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+         g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+         g_READ_COUNTER_WIDTH => 14
+      )
+      PORT MAP (
+         clk_4x_logic_i    => clk_4x_logic,
+         data_strobe_i     => data_strobe,
+         event_data_i      => event_data,
+         ipbus_clk_i       => ipbus_clk,
+         ipbus_i           => ipbw(3),
+         ipbus_reset_i     => ipbus_reset,
+         strobe_4x_logic_i => strobe_4x_logic,
+         rst_fifo_o        => rst_fifo_o,
+         buffer_full_o     => buffer_full_o,
+         ipbus_o           => ipbr(3),
+         logic_reset_i     => logic_reset
+      );
+   --! @brief Takes the data delivered on each trigger and turns it into 64-bit
+   --!        words to push into event buffer
+   --!
+   --!
+   --! @author David Cussans , David.Cussans@bristol.ac.uk
+   --!
+   --! @date 15:10:35 11/09/12
+   --!
+   --! @version v0.1
+   --!
+   --! @details
+   --! \n\n IPBus address:
+   --! \n (Decodes 3 bits)
+   --! \li 000 - read/write enable data recording.
+   --! \li 001 - write = reset timestamp,
+   --! \li 010 - read = current timestamp (low  32-bits)
+   --! \li 011 - read = current timestamp (high 16-bits)
+   --!
+   --! -----------------------------------------------------------------------------
+   --! \n\n<b>Last changes:</b>\n
+   --! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
+   --! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
+   --!               doesn't like having an if that can take an array out of bounds.
+   --!-----------------------------------------------------------------------------
+   --! @todo Add more input data: \n
+   --! a) shutter signals. One per DUT. ?? \n
+   --! b) input levels ( for recording edge data ). Record rising and falling edges\n
+   --! c) veto levels. One per DUT. Record rising and falling edges.\n
+   --! \n
+   --! Add backpressure output if short FIFOs fill up? But many inputs won't
+   --! respond - e.g. scintillator inputs. This data will be lost....
+   --! some ports are redundant - e.g. trigger counter, others confusingly
+   --! labelled. Sort this out..
+   --------------------------------------------------------------------------------
+   I2 : eventFormatter
+      GENERIC MAP (
+         g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+         g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+         g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+         g_COUNTER_WIDTH      => 12,
+         g_EVTTYPE_WIDTH      => 4,                         --! Width of the event type word
+         --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+         g_NUM_EDGE_INPUTS    => g_NUM_EDGE_INPUTS,         --! Number of edge inputs
+         g_NUM_TRIG_INPUTS    => g_NUM_TRIG_INPUTS          --! Number of trigger inputs
+      )
+      PORT MAP (
+         clk_4x_logic_i         => clk_4x_logic,
+         ipbus_clk_i            => ipbus_clk,
+         logic_strobe_i         => strobe_4x_logic,
+         logic_reset_i          => logic_reset,
+         rst_fifo_i             => rst_fifo_o,
+         buffer_full_i          => buffer_full_o,
+         trigger_i              => overall_trigger,
+         trigger_times_i        => postVetoTrigger_times,
+         trigger_inputs_fired_i => postVetotrigger,
+         trigger_cnt_i          => trigger_count,
+         shutter_i              => shutter_i,
+         shutter_cnt_i          => shutter_cnt_i,
+         spill_i                => spill_i,
+         spill_cnt_i            => spill_cnt_i,
+         edge_rise_i            => s_edge_rising,
+         edge_fall_i            => s_edge_falling,
+         edge_rise_time_i       => s_edge_rise_times,
+         edge_fall_time_i       => s_edge_fall_times,
+         ipbus_i                => ipbw(6),
+         ipbus_o                => ipbr(6),
+         data_strobe_o          => data_strobe,
+         event_data_o           => event_data,
+         reset_timestamp_i      => T0_o,
+         reset_timestamp_o      => OPEN
+      );
+   I7 : i2c_master
+      PORT MAP (
+         i2c_scl_i     => i2c_scl_b,
+         i2c_sda_i     => i2c_sda_b,
+         ipbus_clk_i   => ipbus_clk,
+         ipbus_i       => ipbw(5),
+         ipbus_reset_i => ipbus_reset,
+         i2c_scl_enb_o => s_i2c_scl_enb,
+         i2c_sda_enb_o => s_i2c_sda_enb,
+         ipbus_o       => ipbr(5)
+      );
+   I6 : logic_clocks
+      GENERIC MAP (
+         g_USE_EXTERNAL_CLK => 0
+      )
+      PORT MAP (
+         ipbus_clk_i           => ipbus_clk,
+         ipbus_i               => ipbw(4),
+         ipbus_reset_i         => ipbus_reset,
+         Reset_i               => logic_clocks_reset,
+         clk_logic_xtal_i      => clk_logic_xtal,
+         clk_16x_logic_o       => clk_16x_logic,
+         clk_4x_logic_o        => clk_4x_logic,
+         ipbus_o               => ipbr(4),
+         strobe_16x_logic_o    => strobe_16x_logic,
+         strobe_4x_logic_o     => strobe_4x_logic,
+         extclk_p_b            => extclk_p_b,
+         extclk_n_b            => extclk_n_b,
+         DUT_clk_o             => OPEN,
+         logic_clocks_locked_o => leds_o(1),
+         logic_reset_o         => logic_reset
+      );
+   I1 : triggerInputs
+      GENERIC MAP (
+         g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+         g_IPBUS_WIDTH => 32
+      )
+      PORT MAP (
+         cfd_discr_p_i        => cfd_discr_p_i,
+         cfd_discr_n_i        => cfd_discr_n_i,
+         clk_4x_logic         => clk_4x_logic,
+         strobe_4x_logic_i    => strobe_4x_logic,
+         threshold_discr_p_i  => threshold_discr_p_i,
+         threshold_discr_n_i  => threshold_discr_n_i,
+         reset_i              => logic_reset,
+         trigger_times_o      => trigger_times,
+         trigger_o            => triggers,
+         trigger_debug_o      => OPEN,
+         edge_rising_times_o  => s_edge_rise_times,
+         edge_falling_times_o => s_edge_fall_times,
+         edge_rising_o        => s_edge_rising,
+         edge_falling_o       => s_edge_falling,
+         ipbus_clk_i          => ipbus_clk,
+         ipbus_reset_i        => ipbus_reset,
+         ipbus_i              => ipbw(1),
+         ipbus_o              => ipbr(1),
+         clk_16x_logic_i      => clk_16x_logic,
+         strobe_16x_logic_i   => strobe_16x_logic
+      );
+   I3 : triggerLogic
+      GENERIC MAP (
+         g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+         g_IPBUS_WIDTH => g_IPBUS_WIDTH
+      )
+      PORT MAP (
+         clk_4x_logic_i      => clk_4x_logic,
+         ipbus_clk_i         => ipbus_clk,
+         ipbus_i             => ipbw(2),
+         ipbus_reset_i       => ipbus_reset,
+         logic_reset_i       => s_triggerLogic_reset,
+         logic_strobe_i      => strobe_4x_logic,
+         trigger_i           => triggers,
+         trigger_times_i     => trigger_times,
+         veto_i              => overall_veto,
+         trigger_o           => postVetotrigger,
+         trigger_times_o     => postVetoTrigger_times,
+         event_number_o      => trigger_count,
+         ipbus_o             => ipbr(2),
+         post_veto_trigger_o => overall_trigger,
+         pre_veto_trigger_o  => OPEN,
+         trigger_active_o    => leds_o(0)
+      );
+
+END ARCHITECTURE struct;
diff --git a/AIDA_tlu/legacy/TLU_v1e/.svn/entries b/AIDA_tlu/legacy/TLU_v1e/.svn/entries
new file mode 100644
index 0000000000000000000000000000000000000000..b806c374d79494f42d320357bcf9a291343034c3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/.svn/entries
@@ -0,0 +1,28 @@
+10
+
+dir
+0
+https://app.deveo.com/universityofbristol/projects/fmc_tlu/repositories/subversion/AIDA/TLU_v1e
+https://app.deveo.com/universityofbristol/projects/fmc_tlu/repositories/subversion/AIDA
+add
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+a80b426a-c11e-11e6-a987-c3d832fc0b90
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/constraints/I2C_constr.xdc b/AIDA_tlu/legacy/TLU_v1e/constraints/I2C_constr.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..9990653c1dd622084319134f02e46320ebf15a85
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/constraints/I2C_constr.xdc
@@ -0,0 +1,26 @@
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_reset]
+set_property PACKAGE_PIN C2 [get_ports i2c_reset]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
+set_property PACKAGE_PIN N17 [get_ports i2c_scl_b]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
+set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
+
+
+
+create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
+
+
+#Define clock groups and make them asynchronous with each other
+set_clock_groups -asynchronous -group {clk_enclustra I I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
+
+# -------------------------------------------------------------------------------------------------
+
+
+#DEBUG PROBES
+
+
+
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/constraints/TLU_enclustra_v1e.xdc b/AIDA_tlu/legacy/TLU_v1e/constraints/TLU_enclustra_v1e.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..455961aea23256391a49908df30c3cbf81977821
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/constraints/TLU_enclustra_v1e.xdc
@@ -0,0 +1,109 @@
+## Trigger inputs
+
+#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
+#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports {threshold_discr_n_i[*]}]
+set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
+set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
+set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
+set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
+set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
+set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
+set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
+set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
+set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
+set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
+set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+
+## Miscellaneous I/O
+set_property IOSTANDARD LVCMOS33 [get_ports clk_gen_rst]
+set_property PACKAGE_PIN C1 [get_ports clk_gen_rst]
+set_property IOSTANDARD LVCMOS33 [get_ports gpio]
+set_property PACKAGE_PIN F6 [get_ports gpio]
+
+
+## Crystal clock
+set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
+set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
+set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
+
+## Output clock (currently not working so set to 0)
+set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_p]
+set_property PACKAGE_PIN E3 [get_ports sysclk_50_o_p]
+set_property IOSTANDARD LVCMOS33 [get_ports sysclk_50_o_n]
+set_property PACKAGE_PIN D3 [get_ports sysclk_50_o_n]
+
+## Inputs/Outputs for DUTs
+set_property IOSTANDARD LVCMOS33 [get_ports {busy_o[*]}]
+set_property PACKAGE_PIN R7 [get_ports {busy_o[0]}]
+set_property PACKAGE_PIN U4 [get_ports {busy_o[1]}]
+set_property PACKAGE_PIN R8 [get_ports {busy_o[2]}]
+set_property PACKAGE_PIN K5 [get_ports {busy_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {triggers_o[*]}]
+set_property PACKAGE_PIN R6 [get_ports {triggers_o[0]}]
+set_property PACKAGE_PIN P2 [get_ports {triggers_o[1]}]
+set_property PACKAGE_PIN R1 [get_ports {triggers_o[2]}]
+set_property PACKAGE_PIN U1 [get_ports {triggers_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {cont_o[*]}]
+set_property PACKAGE_PIN N5 [get_ports {cont_o[0]}]
+set_property PACKAGE_PIN P4 [get_ports {cont_o[1]}]
+set_property PACKAGE_PIN M6 [get_ports {cont_o[2]}]
+set_property PACKAGE_PIN L6 [get_ports {cont_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {spare_o[*]}]
+set_property PACKAGE_PIN L1 [get_ports {spare_o[0]}]
+set_property PACKAGE_PIN M4 [get_ports {spare_o[1]}]
+set_property PACKAGE_PIN N2 [get_ports {spare_o[2]}]
+set_property PACKAGE_PIN M3 [get_ports {spare_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dut_clk_o[*]}]
+set_property PACKAGE_PIN K3 [get_ports {dut_clk_o[0]}]
+set_property PACKAGE_PIN F4 [get_ports {dut_clk_o[1]}]
+set_property PACKAGE_PIN E2 [get_ports {dut_clk_o[2]}]
+set_property PACKAGE_PIN G4 [get_ports {dut_clk_o[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {cont_i[*]}]
+set_property PACKAGE_PIN P5 [get_ports {cont_i[0]}]
+set_property PACKAGE_PIN P3 [get_ports {cont_i[1]}]
+set_property PACKAGE_PIN N6 [get_ports {cont_i[2]}]
+set_property PACKAGE_PIN L5 [get_ports {cont_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {spare_i[*]}]
+set_property PACKAGE_PIN M1 [get_ports {spare_i[0]}]
+set_property PACKAGE_PIN N4 [get_ports {spare_i[1]}]
+set_property PACKAGE_PIN N1 [get_ports {spare_i[2]}]
+set_property PACKAGE_PIN M2 [get_ports {spare_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {triggers_i[*]}]
+set_property PACKAGE_PIN R5 [get_ports {triggers_i[0]}]
+set_property PACKAGE_PIN R2 [get_ports {triggers_i[1]}]
+set_property PACKAGE_PIN T1 [get_ports {triggers_i[2]}]
+set_property PACKAGE_PIN V1 [get_ports {triggers_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {busy_i[*]}]
+set_property PACKAGE_PIN T6 [get_ports {busy_i[0]}]
+set_property PACKAGE_PIN U3 [get_ports {busy_i[1]}]
+set_property PACKAGE_PIN T8 [get_ports {busy_i[2]}]
+set_property PACKAGE_PIN L4 [get_ports {busy_i[3]}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dut_clk_i[*]}]
+set_property PACKAGE_PIN L3 [get_ports {dut_clk_i[0]}]
+set_property PACKAGE_PIN F3 [get_ports {dut_clk_i[1]}]
+set_property PACKAGE_PIN D2 [get_ports {dut_clk_i[2]}]
+set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
+
+# -------------------------------------------------------------------------------------------------
+
+
+
+
+set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 0.400 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+
+
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
diff --git a/AIDA_tlu/legacy/TLU_v1e/constraints/enclustra_ax3_pm3.tcl b/AIDA_tlu/legacy/TLU_v1e/constraints/enclustra_ax3_pm3.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7fd31b4cc9f873d26b03c33f5f534ba0b2a19aad
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/constraints/enclustra_ax3_pm3.tcl
@@ -0,0 +1,52 @@
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+proc false_path {patt clk} {
+    set p [get_ports -quiet $patt -filter {direction != out}]
+    if {[llength $p] != 0} {
+        set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
+        set_false_path -from [get_ports $patt -filter {direction != out}]
+    }
+    set p [get_ports -quiet $patt -filter {direction != in}]
+    if {[llength $p] != 0} {
+       	set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
+	    set_false_path -to [get_ports $patt -filter {direction != in}]
+	}
+}
+
+# System clock (50MHz)
+#create_clock -period 25.000 -name sysclk [get_ports sysclk] 
+create_clock -period 20.000 -name clk_enclustra [get_ports clk_enclustra]
+
+set_false_path -through [get_pins infra/clocks/rst_reg/Q]
+set_false_path -through [get_nets infra/clocks/nuke_i]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk_enclustra]
+set_property PACKAGE_PIN P17 [get_ports clk_enclustra]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
+set_property SLEW SLOW [get_ports {leds[*]}]
+set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
+set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
+set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
+set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
+false_path {leds[*]} clk_enclustra
+
+set_property IOSTANDARD LVCMOS33 [get_ports {rgmii_* phy_rstn}]
+set_property PACKAGE_PIN R18 [get_ports {rgmii_txd[0]}]
+set_property PACKAGE_PIN T18 [get_ports {rgmii_txd[1]}]
+set_property PACKAGE_PIN U17 [get_ports {rgmii_txd[2]}]
+set_property PACKAGE_PIN U18 [get_ports {rgmii_txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports {rgmii_tx_ctl}]
+set_property PACKAGE_PIN N16 [get_ports {rgmii_txc}]
+set_property PACKAGE_PIN U16 [get_ports {rgmii_rxd[0]}]
+set_property PACKAGE_PIN V17 [get_ports {rgmii_rxd[1]}]
+set_property PACKAGE_PIN V15 [get_ports {rgmii_rxd[2]}]
+set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
+set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
+set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
+set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
+false_path {phy_rstn} clk_enclustra
+
+# -------------------------------------------------------------------------------------------------
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf b/AIDA_tlu/legacy/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..e1c970af85b9ad060a0119273d28ddc4febc18e7
Binary files /dev/null and b/AIDA_tlu/legacy/TLU_v1e/documents/FMC_TLU_TOPLEVEL_E.SCH.1.pdf differ
diff --git a/AIDA_tlu/legacy/TLU_v1e/documents/TLU_v1E_TestPoints.pdf b/AIDA_tlu/legacy/TLU_v1e/documents/TLU_v1E_TestPoints.pdf
new file mode 100644
index 0000000000000000000000000000000000000000..4e7a2b4e210115969169f68205e5b3e6bcfd2f0e
Binary files /dev/null and b/AIDA_tlu/legacy/TLU_v1e/documents/TLU_v1E_TestPoints.pdf differ
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/GPL_doxygen_header.vhdl b/AIDA_tlu/legacy/TLU_v1e/hdl/GPL_doxygen_header.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d9fdc487ef25fde77339ce30d5aff5ae4a75af3f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/GPL_doxygen_header.vhdl
@@ -0,0 +1,77 @@
+--! @file dtype_fds.vhdl
+--
+-------------------------------------------------------------------------------
+-- --
+-- (c) University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+--
+-- This file is part of IPBus.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--    IPBus is free software: you can redistribute it and/or modify
+--    it under the terms of the GNU General Public License as published by
+--    the Free Software Foundation, either version 3 of the License, or
+--    (at your option) any later version.
+--
+--    IPBus is distributed in the hope that it will be useful,
+--    but WITHOUT ANY WARRANTY; without even the implied warranty of
+--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--    GNU General Public License for more details.
+--
+--    You should have received a copy of the GNU General Public License
+--    along with IPBus.  If not, see <http://www.gnu.org/licenses/>.
+--
+--
+--! Standard library
+library IEEE;
+
+-- Standard logic defintions.
+use IEEE.STD_LOGIC_1164.all;
+
+--
+-- unit name: dtype_fds
+--
+--! @brief   Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/GPP_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/GPP_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bc02a5efb0ee30d0bdc486bac320ba25b6c7f611
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/GPP_rtl.vhd
@@ -0,0 +1,312 @@
+--=============================================================================
+--! @file GPP_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- 
+--
+--! @brief GPP - General purpose pulser. Generates a sycronous custom pulse \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 15:42:31 01/15/2013 
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: 
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity GPP is
+   GENERIC( 
+      g_IPBUS_WIDTH      : positive := 32
+   );
+	PORT( clk_i       		: IN     std_logic;                                          		--! Rising edge active
+			Enable_i          : IN     std_logic;                                          --
+			Reset_i           : IN     std_logic;                                          --
+			RstPulsCnt_i     	: IN     std_logic;                                          -- Reset pulse counter
+			Trigger_i         : IN     std_logic;                                          -- Trigger input signal
+			NMaxPulses_i      : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Max number of pulses
+			SuDTime_i         : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Startup dead time
+			PulsLen_i     		: IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Pulse length
+		   IpDTime_i         : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Interpulse dead time
+			RearmTime_i       : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Time before rearm after reach the max number of pulses
+			Force_PullDown_i  : IN     std_logic;                                          -- Force pull down
+			WU_i              : IN     std_logic;                                          -- Output trigger signal with update
+			PulseDelay_i      : IN     std_logic_vector(g_IPBUS_WIDTH-1 downto 0);    		 -- Pulse delay
+	      event_number_o    : OUT    std_logic_vector(g_IPBUS_WIDTH-1 downto 0);         -- Event number
+			MaxPulses_o       : OUT    std_logic;                                          -- Maximun number of pulses reached
+			Pulse_o           : OUT    std_logic;                                          --! pulse output
+			Pulse_d_o         : OUT    std_logic                                           --! pulse output delayed
+			);
+end GPP;
+
+architecture rtl of GPP is
+   --! FSM state values
+   type state_values is (st0, st1, st2, st3, st4, st5, st6);
+	signal pres_state, next_state: state_values;
+	
+	signal s_PulsCnt_en  		: std_logic := '0';                                             --! Pulse counter enable
+	signal s_RstPulsCnt       	: std_logic := '0';                                             --! Reset pulse counter
+	signal s_RstPulsCnt_int   	: std_logic := '0';                                             --! Reset pulse counter internal signal
+	signal s_PulsLen		      : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Pulse Length
+	signal s_PulsCnt     		: unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');        --! Pulse counter value
+	signal s_MaxPulses         : std_logic := '0';                                             --! Max number of pulses reached
+	signal s_Pulse             : std_logic := '0';                                             --! Active pulse signal
+	signal s_Pulse_d           : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others=>'0');  --! Active pulse signal delayed
+   
+	signal s_load_SuDTime      : std_logic := '1';                                             --! Counter load signal
+	signal s_SuDTime 				: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Startup dead time counter
+	signal EOSDT               : std_logic := '0';                                             --! End of startup dead time signal
+	
+	signal s_load_PulsLen     : std_logic := '1';                                           	--! Counter load
+	signal EOP                 : std_logic := '0';                                             --! End of pulse length signal
+	
+	signal s_load_IpDTime      : std_logic := '1';                                             --! Counter load signal
+	signal s_IpDTime 				: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Interpulse dead time counter
+	signal EOIDT               : std_logic := '0';                                             --! End of interpulse dead time signal
+	
+	signal s_load_RearmTime    : std_logic := '1';                                             --! Rearm counter load signal
+	signal s_RearmLen     		: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);                   --! Startup dead time counter
+	signal EOREARM             : std_logic := '0';                                             --! End of startup dead time signal
+
+begin
+	-----------------------------------------------------------------------------
+	-- Counters
+	-----------------------------------------------------------------------------
+	--! Startup dead time counter
+   c_startup_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_SuDTime,
+		InitVal 	=> std_logic_vector(unsigned(s_SuDTime)-1),
+		Count		=> open,
+		Q 			=> EOSDT
+	);
+	s_SuDTime <= x"00000001" when SuDTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else SuDTime_i;
+	
+	--! Pulse time counter
+   c_pulse_time : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_PulsLen,
+		InitVal 	=> std_logic_vector(unsigned(s_PulsLen)-1),
+		Count		=> open,
+		Q 			=> EOP
+	);
+	s_PulsLen <= x"00000001" when PulsLen_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else PulsLen_i;
+	
+	--! Interpulse dead time counter
+   c_interpulse_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_IpDTime,
+		InitVal 	=> std_logic_vector(unsigned(s_IpDTime)-1),
+		Count		=> open,
+		Q 			=> EOIDT
+	);
+	s_IpDTime <= x"00000001" when IpDTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+	             else IpDTime_i;
+	
+	--! Rearm time after the max pulses reached
+   c_rearm_dtime : entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> s_load_RearmTime,
+		InitVal 	=> std_logic_vector(unsigned(s_RearmLen)-1),
+		Count		=> open,
+		Q 			=> EOREARM
+	);
+	s_RearmLen <= x"00000001" when RearmTime_i = x"00000000"    -- At least one clock cycle pulse is generated
+						else RearmTime_i;
+			 
+
+	--! FSM register
+	statereg: process(clk_i, Enable_i, Reset_i)
+	begin
+		if Enable_i = '0'  then 
+			pres_state <= st0;            -- Move to st0 - INITIAL STATE
+      
+		elsif Reset_i = '1' then
+			pres_state <= st0;            -- Move to st0 - INITIAL STATE
+        
+		elsif rising_edge(clk_i) then
+			pres_state <= next_state;     -- Move to next state
+        
+		end if;
+	end process statereg;
+
+
+   --! FSM combinational block
+	fsm: process(pres_state, Enable_i, Reset_i, Trigger_i, s_MaxPulses, EOP, EOSDT, EOIDT, Force_PullDown_i)
+	begin
+	  next_state <= pres_state;
+	  -- Default values
+	  s_Pulse          	<= '0';
+	  s_load_SuDTime     <= '1';
+	  s_load_PulsLen 		<= '1';
+	  s_load_IpDTime     <= '1';
+	  s_load_RearmTime	<= '1';
+	  s_RstPulsCnt_int   <= '0';
+  
+     case pres_state is
+	  
+	    -- st0 - INITIAL STATE
+		 when st0=>
+         if (Enable_i = '1') and (Reset_i = '0') then 
+           next_state <= st1;            -- Next state is "st1 - IDLE"
+         end if;
+       
+		 -- st1 - IDLE STATE
+       when st1=>
+         if s_MaxPulses = '1' then
+           next_state <= st5;            -- Next state is "st5 - NMAX PULSES REACHED"
+         else
+           if Trigger_i = '1' and Force_PullDown_i = '0' then 
+             if (to_integer(unsigned(SuDTime_i)) = 0) then
+               next_state <= st3;        -- Next state is "st3 - PULSE"
+             else
+               next_state <= st2;        -- Next state is "st2 - STARTUP DEAD-TIME"
+             end if; 
+           end if;
+         end if;
+		 
+		 -- st2 - STARTUP DEAD-TIME
+       when st2=>
+         s_load_SuDTime <= '0';
+           if EOSDT = '1' then
+             next_state <= st3;          -- Next state is "st3 - PULSE"
+           end if;
+		
+		 -- st3 - PULSE
+       when st3=>
+         s_Pulse <= '1';
+         s_load_PulsLen <= '0';
+				
+         if (EOP = '1') or (Force_PullDown_i = '1')then
+           if (to_integer(unsigned(IpDTime_i)) = 0) then
+             next_state <= st1;         -- Next state is "st1 - IDLE"
+           else
+             next_state <= st4;         -- Next state is "st4 - INTERPULSE DEAD-TIME"
+           end if;
+         end if;
+				
+         if Trigger_i = '1' then
+           if (WU_i = '1') then
+             next_state <= st6;         -- Next state is "st6 - RELOAD PULSE TIMER"
+           end if;	
+         end if;
+       
+		 
+		 -- st4 - INTERPULSE DEAD-TIME
+       when st4=>
+         s_load_IpDTime <= '0';
+         if EOIDT = '1' then
+           next_state <= st1;            -- Next state is "st1 - IDLE"
+         end if;
+				
+		 -- st5 - NMAX PULSES REACHED
+       when st5=>
+		   s_load_RearmTime <= '0';
+			if EOREARM = '1' then
+			  next_state <= st1;            -- Next state is "st1 - IDLE"
+			  s_RstPulsCnt_int <= '1';
+			end if;
+			
+		 -- st6 - RELOAD PULSE TIMER
+       when st6=>
+         s_Pulse <= '1';
+         next_state <= st3;              -- Next state is "st3 - PULSE"
+			
+--       when others=>
+--         next_state<=st0;                -- Next state is "st0 - INITIAL STATE"
+     
+	  end case;
+	
+	end process fsm;    
+	
+	-- Pulse reg
+	p_reg_pulse : process ( clk_i , Reset_i )
+   begin  
+	  if Reset_i = '1' then
+	    s_Pulse_d <= (others => '0');
+	  
+	  elsif rising_edge(clk_i) then
+       for i in 0 to g_IPBUS_WIDTH-2 loop
+         s_Pulse_d(i+1) <= s_Pulse_d(i);
+       end loop;
+	    s_Pulse_d(0) <= s_Pulse;
+	  end if;
+	end process p_reg_pulse;
+	
+	event_number_o <= std_logic_vector(s_PulsCnt);
+	MaxPulses_o <= s_MaxPulses;
+	Pulse_o 		<= s_Pulse;
+	Pulse_d_o 	<= s_Pulse when PulseDelay_i = x"00000000" else
+						s_Pulse_d(to_integer(unsigned(PulseDelay_i)-1));
+	
+	
+	-----------------------------------------------------------------------------
+	-- Count runs and synchronization
+	-----------------------------------------------------------------------------
+	p_PulsCounter : process (clk_i )
+	begin  -- process p_run_counter
+
+		if rising_edge(clk_i) then
+			if s_RstPulsCnt = '1' then
+				s_PulsCnt <= (others => '0');
+			elsif s_PulsCnt_en = '1' then
+				s_PulsCnt <= s_PulsCnt + 1;
+			end if;
+		
+		end if;
+	end process p_PulsCounter;
+  
+	s_RstPulsCnt <= Reset_i or RstPulsCnt_i or s_RstPulsCnt_int;
+	s_PulsCnt_en <= '1' when (s_Pulse = '1') and (s_Pulse_d(0) = '0') and (s_MaxPulses = '0')
+	                      else '0'; 
+	s_MaxPulses <= '1' when (s_PulsCnt = unsigned(NMaxPulses_i)) and (NMaxPulses_i /= x"00000000")
+                  else '0';
+
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/IPBusInterface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/IPBusInterface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..aa9bd6decdaad84c5b7eceef5aa580c92b5c28e2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/IPBusInterface_rtl.vhd
@@ -0,0 +1,261 @@
+--=============================================================================
+--! @file IPBusInterface_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+--! @brief IPBus interface between 1GBit/s Ethernet and IPBus internal bus
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 16:06:57 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+ENTITY IPBusInterface IS
+   GENERIC( 
+      NUM_EXT_SLAVES : positive := 5;
+      BUILD_SIMULATED_ETHERNET : integer := 0 --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
+   );
+   PORT( 
+      gmii_rx_clk_i    : IN     std_logic;
+      gmii_rx_dv_i     : IN     std_logic;
+      gmii_rx_er_i     : IN     std_logic;
+      gmii_rxd_i       : IN     std_logic_vector (7 DOWNTO 0);
+      ipbr_i           : IN     ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0);  --! IPBus read signals
+      sysclk_n_i       : IN     std_logic;
+      sysclk_p_i       : IN     std_logic;                                   --! 200 MHz xtal clock
+      clocks_locked_o  : OUT    std_logic;
+      gmii_gtx_clk_o   : OUT    std_logic;
+      gmii_tx_en_o     : OUT    std_logic;
+      gmii_tx_er_o     : OUT    std_logic;
+      gmii_txd_o       : OUT    std_logic_vector (7 DOWNTO 0);
+      ipb_clk_o        : OUT    std_logic;                                   --! IPBus clock to slaves
+      ipb_rst_o        : OUT    std_logic;                                   --! IPBus reset to slaves
+      ipbw_o           : OUT    ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0);  --! IBus write signals
+      onehz_o          : OUT    std_logic;
+      phy_rstb_o       : OUT    std_logic;
+      dip_switch_i     : IN     std_logic_vector (3 DOWNTO 0); --! Used to select IP address
+      clk_logic_xtal_o : OUT    std_logic  --! 40MHz clock that can be used for logic if not using external clock
+   );
+
+-- Declarations
+
+END ENTITY IPBusInterface ;
+
+--
+ARCHITECTURE rtl OF IPBusInterface IS
+  
+  --! Number of slaves inside the IPBusInterface block.
+  constant c_NUM_INTERNAL_SLAVES : positive := 1;
+
+  signal clk125,  rst_125, rst_ipb: STD_LOGIC;
+  signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
+  signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
+  signal ipb_master_out : ipb_wbus;
+  signal ipb_master_in : ipb_rbus;
+  signal mac_addr: std_logic_vector(47 downto 0);
+  signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+  signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+
+  signal ip_addr: std_logic_vector(31 downto 0);
+  signal s_ipb_clk : std_logic;
+  signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+  signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+  signal s_sysclk : std_logic;
+  signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
+  
+BEGIN
+
+  -- Connect IPBus clock and reset to output ports.
+  ipb_clk_o <= s_ipb_clk;
+  ipb_rst_o <= rst_ipb;
+
+  --! By default generate a physical MAC
+  generate_physicalmac: if ( BUILD_SIMULATED_ETHERNET /= 1 ) generate
+      
+--	DCM clock generation for internal bus, ethernet
+--	clocks: entity work.clocks_s6_extphy port map(
+--          sysclk_p => sysclk_p_i,
+--          sysclk_n => sysclk_n_i,
+--          clk_logic_xtal_o => clk_logic_xtal_o,
+--          clko_125 => clk125,
+--          clko_ipb => s_ipb_clk,
+--          locked => clocks_locked_o,
+--          rsto_125 => rst_125,
+--          rsto_ipb => rst_ipb,
+--          onehz => onehz_o
+--          );
+    
+    clocks: entity work.clocks_7s_extphy_Se port map(
+        sysclk_p => sysclk_p_i,
+        sysclk_n => sysclk_n_i,
+        clk_logic_xtal_o => clk_logic_xtal_o,
+        clko_125 => clk125,
+        clko_ipb => s_ipb_clk,
+        locked => clocks_locked_o,
+        rsto_125 => rst_125,
+        rsto_ipb => rst_ipb,
+        onehz => onehz_o
+        );
+				
+	-- leds <= ('0', '0', locked, onehz);
+	
+--	Ethernet MAC core and PHY interface
+-- In this version, consists of hard MAC core and GMII interface to external PHY
+-- Can be replaced by any other MAC / PHY combination
+
+--        eth: entity work.eth_s6_gmii port map(
+--          clk125 => clk125,
+--          rst => rst_125,
+--          gmii_gtx_clk => gmii_gtx_clk_o,
+--          gmii_tx_en => gmii_tx_en_o,
+--          gmii_tx_er => gmii_tx_er_o,
+--          gmii_txd => gmii_txd_o,
+--          gmii_rx_clk => gmii_rx_clk_i,
+--          gmii_rx_dv => gmii_rx_dv_i,
+--          gmii_rx_er => gmii_rx_er_i,
+--          gmii_rxd => gmii_rxd_i,
+--          tx_data => mac_tx_data,
+--          tx_valid => mac_tx_valid,
+--          tx_last => mac_tx_last,
+--          tx_error => mac_tx_error,
+--          tx_ready => mac_tx_ready,
+--          rx_data => mac_rx_data,
+--          rx_valid => mac_rx_valid,
+--          rx_last => mac_rx_last,
+--          rx_error => mac_rx_error
+--          );
+          
+      eth: entity work.eth_7s_rgmii port map(
+            clk125 => clk125,
+            rst => rst_125,
+            tx_data => mac_tx_data,
+            tx_valid => mac_tx_valid,
+            tx_last => mac_tx_last,
+            tx_error => mac_tx_error,
+            tx_ready => mac_tx_ready,
+            rx_data => mac_rx_data,
+            rx_valid => mac_rx_valid,
+            rx_last => mac_rx_last,
+            rx_error => mac_rx_error,
+            gmii_gtx_clk => gmii_gtx_clk_o,
+            gmii_tx_en => gmii_tx_en_o,
+            gmii_tx_er => gmii_tx_er_o,
+            gmii_txd => gmii_txd_o,
+            gmii_rx_clk => gmii_rx_clk_i,
+            gmii_rx_dv => gmii_rx_dv_i,
+            gmii_rx_er => gmii_rx_er_i,
+            gmii_rxd => gmii_rxd_i            
+            );
+          	
+  end generate generate_physicalmac;
+
+    --! Set generic BUILD_SIMULATED_ETHERNET to 1 to generate a simulated MAC
+    generate_simulatedmac: if ( BUILD_SIMULATED_ETHERNET = 1 ) generate
+
+      sim_clocks: entity work.clock_sim
+	port map (
+	  clko125 => clk125,
+	  clko25 => s_ipb_clk,
+	  clko40 =>  clk_logic_xtal_o,
+	  nuke   => '0',
+	  rsto   => rst_125
+          );
+      rst_ipb <= rst_125;
+      clocks_locked_o  <= '1';
+      
+      -- clk125 <= sysclk_i; -- *must* run this simulation with 125MHz sysclk...
+      simulated_eth: entity work.eth_mac_sim
+        port map(
+          clk => clk125,
+          rst => rst_125,
+          tx_data => mac_tx_data,
+          tx_valid => mac_tx_valid,
+          tx_last => mac_tx_last,
+          tx_error => mac_tx_error,
+          tx_ready => mac_tx_ready,
+          rx_data => mac_rx_data,
+          rx_valid => mac_rx_valid,
+          rx_last => mac_rx_last,
+          rx_error => mac_rx_error
+          );
+    end generate generate_simulatedmac;
+
+  phy_rstb_o <= '1';
+  
+-- ipbus control logic
+        ipbus: entity work.ipbus_ctrl
+          generic map (
+            BUFWIDTH => 2)
+          port map(
+            mac_clk => clk125,
+            rst_macclk => rst_125,
+            ipb_clk => s_ipb_clk,
+            rst_ipb => rst_ipb,
+            mac_rx_data => mac_rx_data,
+            mac_rx_valid => mac_rx_valid,
+            mac_rx_last => mac_rx_last,
+            mac_rx_error => mac_rx_error,
+            mac_tx_data => mac_tx_data,
+            mac_tx_valid => mac_tx_valid,
+            mac_tx_last => mac_tx_last,
+            mac_tx_error => mac_tx_error,
+            mac_tx_ready => mac_tx_ready,
+            ipb_out => ipb_master_out,
+            ipb_in => ipb_master_in,
+            mac_addr => mac_addr,
+            ip_addr => ip_addr,
+            pkt_rx => pkt_rx,
+            pkt_tx => pkt_tx,
+            pkt_rx_led => pkt_rx_led,
+            pkt_tx_led => pkt_tx_led
+            );
+
+	
+	mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
+	ip_addr   <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
+ 
+  fabric: entity work.ipbus_fabric
+    generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
+    port map(
+      ipb_in => ipb_master_out,
+      ipb_out => ipb_master_in,
+      ipb_to_slaves => s_ipbw_internal,
+      ipb_from_slaves => s_ipbr_internal
+    );
+    
+    ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
+
+    s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
+         
+  -- Slave: firmware ID
+  firmware_id: entity work.ipbus_ver
+    port map(
+      ipbus_in =>  s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
+      ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
+      );
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/Reg_2clks.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/Reg_2clks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df7168fc6283b56b28cef8af2b300d774b576bf7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/Reg_2clks.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    31/07/2012 
+-- Module Name:    Reg_2clks - Behavioral 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 1b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity Reg_2clks is
+  port(
+    clk_i : in std_logic;  --! Synchronous clock
+	 async_i : in std_logic;  --! Asynchronous input data
+	 sync_o : out std_logic   --! Synchronous output data
+	 );
+end Reg_2clks;
+
+--! @brief
+--! @details Synchronize 1 bit of data 
+
+architecture Behavioral of Reg_2clks is
+signal sreg : std_logic_vector(1 downto 0);
+
+attribute TIG : string;
+attribute IOB : string;
+attribute ASYNC_REG : string;
+attribute SHIFT_EXTRACT : string;
+attribute HBLKNM : string;
+
+attribute TIG of async_i : signal is "TRUE";
+attribute IOB of async_i : signal is "FALSE";
+attribute ASYNC_REG of sreg : signal is "TRUE";
+attribute SHIFT_EXTRACT of sreg : signal is "NO";
+attribute HBLKNM of sreg : signal is "sync_reg";
+
+begin
+
+process (clk_i)
+begin
+   if rising_edge(clk_i) then  
+     sync_o <= sreg(1);
+	  sreg <= sreg(0) & async_i;
+   end if;
+end process;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/T0_Shutter_Iface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/T0_Shutter_Iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ef24ee2a7bc35342592fd06c079f0650de54c878
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/T0_Shutter_Iface_rtl.vhd
@@ -0,0 +1,114 @@
+--! @file T0_Shutter_Iface_rtl.vhd
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Simple module to generate T0 and shutter signals under IPBus control
+--! Similar interface to TPx3_iface_rtl.vhd
+--
+--! @details
+--! \n \n IPBus address map:
+--! \li 00 - shutter. Bit 0. Output shutter = value of bit-0
+--! \li 01 - T0 write to pulse T0.
+--
+--! @author David Cussans
+
+entity T0_Shutter_Iface is
+
+  port (
+    clk_4x_i      : in  std_logic;    --! system clock
+    clk_4x_strobe : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    T0_o          : out std_logic;    --! T0 signal retimed onto system clock
+    shutter_o          : out std_logic;    --! shutter signal retimed onto system clock
+
+    ipbus_clk_i            : IN     std_logic; --! IPBus system clock
+    ipbus_i                : IN     ipb_wbus;
+    ipbus_o                : OUT    ipb_rbus
+          
+    );     
+
+end entity T0_Shutter_Iface;
+
+architecture rtl of T0_Shutter_Iface is
+
+  signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+  signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
+  signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+
+  signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+
+  signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+                                                                             
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  
+begin  -- architecture rtl
+
+  --------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_T0_ipbus <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+                when "00" => s_shutter_ipbus <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter
+                when "01" => s_T0_ipbus <= '1';
+                when others => null;
+            end case;
+        end if;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+
+    ------------------
+    p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
+    begin  -- process p_T0_retime
+    if rising_edge(clk_4x_i)  then
+        -- Register IPBus clocked signals onto clk 4x. So clk4x must be faster
+        -- than ipbus_clk for this to work.
+        s_T0_ipbus_d1 <= s_T0_ipbus;
+        s_T0_ipbus_d2 <= s_T0_ipbus_d1;
+        -- Shutter is a DC level, so clock speeds don't matter.
+        s_shutter_ipbus_d1 <= s_shutter_ipbus;
+        s_shutter_ipbus_d2 <= s_shutter_ipbus_d1;
+        -- Stretch T0_i pulse to 4 clock cycles on clk4x
+        if ( s_T0_ipbus_d2 = '1' ) then
+            s_stretch_T0_in <= '1';
+            s_stretch_T0_in_sr <= "111";
+        else
+            s_stretch_T0_in <= s_stretch_T0_in_sr(0);
+            s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
+        end if;
+ 
+        if (clk_4x_strobe  = '1') and ( s_stretch_T0_in = '1' ) then
+            T0_o <= '1';
+            s_T0_out_sr <= "111";
+        else
+            T0_o <= s_T0_out_sr(0);
+            s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
+        end if;
+    end if;
+    end process p_T0_retime;
+    
+  -- Just retime onto the 4x clock. Probably should retime onto 1x clock.
+    p_shutter_retime: process (s_shutter , clk_4x_i) is
+    begin  -- process p_shutter_retime
+    if rising_edge(clk_4x_i)  then
+        s_shutter_d1 <= ( s_shutter_ipbus );
+        s_shutter_d2 <= s_shutter_d1;
+        shutter_o    <= s_shutter_d2;
+    end if;
+    end process p_shutter_retime;
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3Logic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3Logic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e35cfacd18f53ec298aefd1d5f836b05254aa2c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3Logic_rtl.vhd
@@ -0,0 +1,177 @@
+--=============================================================================
+--! @file TPx3Logic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
+--
+--! @brief Produces shutters \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 16:06:19 11/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY TPx3Logic IS
+	GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i      				: IN     std_logic;                                    -- ! Rising edge active
+		Start_T0sync_i			: IN 		std_logic;
+		T0syncLen_i				: IN 		std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+      logic_reset_i       	: IN     std_logic;                                    -- active high. Synchronous with clk_4x_logic
+      Busy_i					: IN     std_logic;
+		Veto_i					: IN     std_logic;
+		Shutter_o				: OUT 	std_logic;
+		T0sync_o 				: OUT 	std_logic
+   );
+	
+
+-- Declarations
+
+END ENTITY TPx3Logic ;
+
+--
+ARCHITECTURE rtl OF TPx3Logic IS
+
+	type state_values is (st0, st1);
+	signal pres_state, next_state: state_values;
+
+	signal s_Enable : std_logic := '0';
+	signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
+	signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
+	signal Rst_T0sync, T0syncT : 		std_logic;   	--Load signal and flag for the T0sync
+	signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for runs
+	
+BEGIN
+
+	-----------------------------------------------------------------------------
+	-- Counters
+	-----------------------------------------------------------------------------
+	--T0sync counter
+	c_T0sync: entity work.CounterDown
+	generic map(
+		MAX_WIDTH => g_IPBUS_WIDTH
+	)
+	port map( 
+		Clk		=> clk_i,
+		Reset		=> '0',
+		Load 		=> Rst_T0sync,
+		InitVal 	=> std_logic_vector(unsigned(T0syncLen_i)-1),
+		Count		=> open,
+		Q 			=> T0syncT
+	);
+  
+  
+  -----------------------------------------------------------------------------
+  -- FSM register
+  -----------------------------------------------------------------------------
+	statereg: process(clk_i)
+	begin
+		if rising_edge(clk_i) then
+			pres_state <= next_state;  --Move to the next state
+		end if;
+	end process statereg;
+	
+	
+	-----------------------------------------------------------------------------
+	-- FSM combinational block
+	-----------------------------------------------------------------------------
+	fsm: process(pres_state, s_Start_T0sync, T0syncT)
+	begin
+		next_state<=pres_state;
+		s_T0sync	<='0';
+		Rst_T0sync <= '1';
+		
+		case pres_state is
+			when st0=>
+				if s_Start_T0sync = '1' then 
+					next_state <= st1; --Next state is "Whait for end of T0sync signal"
+				end if;
+			when st1 =>
+				Rst_T0sync <='0';
+				s_T0sync <='1';
+				if T0syncT = '1' then
+					next_state<=st0; --Next state is "Whait for end of T0-sync counter"
+				end if;
+			when others=>
+				next_state<=st0; --Next state is "Whait for T0sync start"
+		end case;
+	end process fsm;
+
+  
+	-----------------------------------------------------------------------------
+	-- Busy signals
+	-----------------------------------------------------------------------------
+	s_Enable <= not Veto_i;
+	s_Shutter <= not Busy_i and not Veto_i;
+	--Shutter_o <= s_Shutter;
+	--T0sync_o <= s_T0sync;
+  
+	
+	-----------------------------------------------------------------------------
+	-- Count runs and synchronization
+	-----------------------------------------------------------------------------
+	p_run_counter: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Start_T0sync_d1 <= Start_T0sync_i;
+			s_Start_T0sync_d2 <= s_Start_T0sync_d1;
+			s_Start_T0sync_d3 <= s_Start_T0sync_d2;
+			s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3); 
+		
+			s_Shutter_d1 <= s_Shutter;
+		
+			if logic_reset_i = '1' then
+				s_RunNumber <= (others => '0');
+			elsif s_Shutter='1' and s_Shutter_d1='0' then
+				s_RunNumber <= s_RunNumber + 1;
+			end if;
+		end if;
+		-- Signals synchronous with falling edge clock
+		if falling_edge(clk_i) then
+			s_Shutter_d1f <= s_Shutter;
+			Shutter_o <= s_Shutter_d1f;
+			
+			s_T0sync_d1f <= s_T0sync;
+			T0sync_o <= s_T0sync_d1f;
+		end if;
+  end process p_run_counter;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3_iface_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3_iface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f576ac1ba6db98f073e84d5cf6abb1de943fb998
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/TPx3_iface_rtl.vhd
@@ -0,0 +1,160 @@
+--! @file TPx3_iface_rtl.vhd
+--! @brief Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
+--! Accepts T0 sync signal and shutter signal from telescope and re-transmits.
+--! @details
+--! IPBus address map:
+--! 00 - shutter. Bit 0. Output shutter = external shutter XOR ipbus shutter
+--! 01 - T0 write to pulse T0.
+--! @author David Cussans
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+
+entity TPx3_iface is
+
+  port (
+    clk_4x_i      : in  std_logic;    --! system clock
+    clk_4x_strobe : in  std_logic;    --! strobes high for one cycle every 4 of clk_4x
+    T0_p_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_n_i          : in  std_logic;  --! T0 signal from timepix telescope clk/sync system
+    T0_o          : out std_logic;    --! T0 signal retimed onto system clock
+    shutter_p_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_n_i          : in  std_logic;  --! shutter signal from timepix telescope clk/sync system
+    shutter_o          : out std_logic;    --! shutter signal retimed onto system clock
+
+    ipbus_clk_i            : IN     std_logic; --! IPBus system clock
+    ipbus_i                : IN     ipb_wbus;
+    ipbus_o                : OUT    ipb_rbus
+          
+    );     
+
+end entity TPx3_iface;
+
+architecture rtl of TPx3_iface is
+
+  signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+  signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
+  signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+
+  signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0';  -- signal after IBufDS and sampled onto clk_4x
+
+  signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2: std_logic := '0';  -- Signals that get combined with incoming hardware signals from TPIx3 telescope
+  signal s_external_signal_mask : std_logic_vector(ipbus_i.ipb_wdata'range) := ( others => '0'); --! Set bits to mask external signals : 0 to mask external T0 , set bit 1 to mask external shutter
+  signal s_maskExternalShutter , s_maskExternalT0 : std_logic := '0';  -- ! Set to 1 to mask external signals
+                                                                             
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  
+begin  -- architecture rtl
+
+  --------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_T0_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+        case ipbus_i.ipb_addr(1 downto 0) is
+          when "00" => s_shutter_ipbus <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter
+          when "01" => s_T0_ipbus <= '1';
+          when "10" => s_external_signal_mask <= ipbus_i.ipb_wdata;
+          when others => null;
+        end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+
+
+    ------------------
+    
+  cmp_IBUFDS_T0 : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_T0,  -- Buffer output
+        I =>  T0_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => T0_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+        
+    p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
+  begin  -- process p_T0_retime
+    if rising_edge(clk_4x_i)  then
+
+      s_maskExternalShutter <= s_external_signal_mask(1);
+      s_maskExternalT0 <= s_external_signal_mask(0);
+        
+      s_T0_d1 <= s_T0;
+      s_T0_d2 <= s_T0_d1;
+
+      -- Register IPBus clocked signals onto clk 4x. So clk4x must be faster
+      -- than ipbus_clk for this to work.
+      s_T0_ipbus_d1 <= s_T0_ipbus;
+      s_T0_ipbus_d2 <= s_T0_ipbus_d1;
+
+      -- Shutter is a DC level, so clock speeds don't matter.
+      s_shutter_ipbus_d1 <= s_shutter_ipbus;
+      s_shutter_ipbus_d2 <= s_shutter_ipbus_d1;
+      
+      
+      -- Stretch T0_i pulse to 4 clock cycles on clk4x
+      if ( (( s_T0_d2 = '1' ) and ( s_maskExternalT0 = '0')) or ( s_T0_ipbus_d2 = '1' )) then
+        s_stretch_T0_in <= '1';
+        s_stretch_T0_in_sr <= "111";
+      else
+        s_stretch_T0_in <= s_stretch_T0_in_sr(0);
+        s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (clk_4x_strobe  = '1') and ( s_stretch_T0_in = '1' ) then
+        T0_o <= '1';
+        s_T0_out_sr <= "111";
+      else
+        T0_o <= s_T0_out_sr(0);
+        s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
+      end if;
+
+      
+    end if;
+  end process p_T0_retime;
+    
+  cmp_IBUFDS_shutter : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  s_shutter,  -- Buffer output
+        I =>  shutter_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => shutter_n_i -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  -- Just retime onto the 4x clock. Probably should retime onto 1x clock.
+  p_shutter_retime: process (s_shutter , clk_4x_i) is
+  begin  -- process p_shutter_retime
+    if rising_edge(clk_4x_i)  then
+      s_shutter_d1 <= ( ( s_shutter and not s_maskExternalShutter ) xor s_shutter_ipbus );
+      s_shutter_d2 <= s_shutter_d1;
+      shutter_o    <= s_shutter_d2;
+    end if;
+  end process p_shutter_retime;
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ax3_pm3_mTLUvC.xdc b/AIDA_tlu/legacy/TLU_v1e/hdl/ax3_pm3_mTLUvC.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..8ba1064658293761a501e40ee6056de99763e53e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ax3_pm3_mTLUvC.xdc
@@ -0,0 +1,377 @@
+# -------------------------------------------------------------------------------------------------
+# -- Project             : Mars AX3 
+# -- File description    : User Constraint File for Mars PM3 Base Board
+# -- File name           : mars_ax3_pm3.xdc
+# -- Authors             : Kanishk Sugand / Marc Oberholzer
+# -------------------------------------------------------------------------------------------------
+# -- Copyright © 2012 by Enclustra GmbH, Switzerland. All rights are reserved. 
+# -- Unauthorized duplication of this document, in whole or in part, by any means is prohibited
+# -- without the prior written permission of Enclustra GmbH, Switzerland.
+# -- 
+# -- Although Enclustra GmbH believes that the information included in this publication is correct
+# -- as of the date of publication, Enclustra GmbH reserves the right to make changes at any time
+# -- without notice.
+# -- 
+# -- All information in this document may only be published by Enclustra GmbH, Switzerland.
+# -------------------------------------------------------------------------------------------------
+# -- Notes:
+# -- 1. For best I/O timing, it is necessary to set the following options in Xilinx ISE/PlanAhead: 
+# --    map option "Pack I/O registers into IOBs" to "Inputs and Outputs"
+# -- 2. The IO standards for banks 0, 2 and 3 are only valid if VCCO_0/VCCO_2/VCCO_3 = 3.3 V
+# -------------------------------------------------------------------------------------------------
+# -- File history:
+# --
+# -- Version | Date       | Author             | Remarks
+# -- ----------------------------------------------------------------------------------------------
+# -- 1.0     | 11.4.14    | C. Glattfelder     | converted from UCF
+# -------------------------------------------------------------------------------------------------
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: global clock inputs
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN P17 [get_ports {Clk_50}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Clk_50}]
+set_property PACKAGE_PIN L16 [get_ports {Fpga_Emcclk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Fpga_Emcclk}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ddr3 sdram
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[8]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[5]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cas_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[0]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Odt]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[4]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cke]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[2]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_We_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_N]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Ras_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[12]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_P]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[11]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Reset_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN A15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN E15 [get_ports {Ddr3_Dq[3]}]
+set_property PACKAGE_PIN B11 [get_ports {Ddr3_Dq[15]}]
+set_property PACKAGE_PIN B18 [get_ports {Ddr3_Dq[4]}]
+set_property PACKAGE_PIN F14 [get_ports {Ddr3_Dq[14]}]
+set_property PACKAGE_PIN B17 [get_ports {Ddr3_Dq[5]}]
+set_property PACKAGE_PIN A11 [get_ports {Ddr3_Dq[13]}]
+set_property PACKAGE_PIN A16 [get_ports {Ddr3_Dq[6]}]
+set_property PACKAGE_PIN F13 [get_ports {Ddr3_Dq[12]}]
+set_property PACKAGE_PIN B16 [get_ports {Ddr3_Dq[7]}]
+set_property PACKAGE_PIN D14 [get_ports {Ddr3_Dq[11]}]
+set_property PACKAGE_PIN B14 [get_ports {Ddr3_Dq[8]}]
+set_property PACKAGE_PIN B13 [get_ports {Ddr3_Dq[10]}]
+set_property PACKAGE_PIN C14 [get_ports {Ddr3_Dq[9]}]
+set_property PACKAGE_PIN E16 [get_ports {Ddr3_Dq[1]}]
+set_property PACKAGE_PIN A14 [get_ports {Ddr3_Dqs_N[0]}]
+set_property PACKAGE_PIN A18 [get_ports {Ddr3_Dq[0]}]
+set_property PACKAGE_PIN D12 [get_ports {Ddr3_Dm[1]}]
+set_property PACKAGE_PIN D15 [get_ports {Ddr3_Dm[0]}]
+set_property PACKAGE_PIN A13 [get_ports {Ddr3_Dqs_P[0]}]
+set_property PACKAGE_PIN C16 [get_ports Ddr3_Clk_P]
+set_property PACKAGE_PIN C17 [get_ports Ddr3_Clk_N]
+set_property PACKAGE_PIN G14 [get_ports Ddr3_Cke]
+set_property PACKAGE_PIN B12 [get_ports {Ddr3_Dqs_N[1]}]
+set_property PACKAGE_PIN F16 [get_ports Ddr3_Cas_N]
+set_property PACKAGE_PIN K15 [get_ports {Ddr3_Ba[2]}]
+set_property PACKAGE_PIN H14 [get_ports {Ddr3_Ba[1]}]
+set_property PACKAGE_PIN C12 [get_ports {Ddr3_Dqs_P[1]}]
+set_property PACKAGE_PIN D17 [get_ports {Ddr3_Ba[0]}]
+set_property PACKAGE_PIN F18 [get_ports {Ddr3_A[9]}]
+set_property PACKAGE_PIN H17 [get_ports {Ddr3_A[8]}]
+set_property PACKAGE_PIN K16 [get_ports Ddr3_Odt]
+set_property PACKAGE_PIN E18 [get_ports {Ddr3_A[7]}]
+set_property PACKAGE_PIN K13 [get_ports {Ddr3_A[6]}]
+set_property PACKAGE_PIN E17 [get_ports {Ddr3_A[5]}]
+set_property PACKAGE_PIN F15 [get_ports Ddr3_Ras_N]
+set_property PACKAGE_PIN J13 [get_ports {Ddr3_A[4]}]
+set_property PACKAGE_PIN D18 [get_ports {Ddr3_A[3]}]
+set_property PACKAGE_PIN J18 [get_ports {Ddr3_A[2]}]
+set_property PACKAGE_PIN G13 [get_ports Ddr3_Reset_N]
+set_property PACKAGE_PIN G17 [get_ports {Ddr3_A[13]}]
+set_property PACKAGE_PIN H16 [get_ports {Ddr3_A[12]}]
+set_property PACKAGE_PIN G18 [get_ports {Ddr3_A[11]}]
+set_property PACKAGE_PIN J15 [get_ports Ddr3_We_N]
+set_property PACKAGE_PIN G16 [get_ports {Ddr3_A[10]}]
+set_property PACKAGE_PIN J14 [get_ports {Ddr3_A[1]}]
+set_property PACKAGE_PIN J17 [get_ports {Ddr3_A[0]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ethernet
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rst_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Txc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports Eth_Link_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Tx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports Eth_Tx_Ctl]
+set_property PACKAGE_PIN R18 [get_ports {Eth_Txd[0]}]
+set_property PACKAGE_PIN V16 [get_ports {Eth_Rxd[3]}]
+set_property PACKAGE_PIN V15 [get_ports {Eth_Rxd[2]}]
+set_property PACKAGE_PIN V17 [get_ports {Eth_Rxd[1]}]
+set_property PACKAGE_PIN T18 [get_ports {Eth_Txd[1]}]
+set_property PACKAGE_PIN U16 [get_ports {Eth_Rxd[0]}]
+set_property PACKAGE_PIN T14 [get_ports Eth_Rxc]
+set_property PACKAGE_PIN R16 [get_ports Eth_Rx_Ctl]
+set_property PACKAGE_PIN U17 [get_ports {Eth_Txd[2]}]
+set_property PACKAGE_PIN M13 [get_ports Eth_Rst_N]
+set_property PACKAGE_PIN N14 [get_ports Eth_Mdio]
+set_property PACKAGE_PIN P14 [get_ports Eth_Mdc]
+set_property PACKAGE_PIN U18 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN C15 [get_ports Eth_Link_N]
+set_property PACKAGE_PIN N16 [get_ports Eth_Txc]
+set_property PACKAGE_PIN T15 [get_ports Eth_Int_N]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: i2c
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R17 [get_ports I2c_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Int_N]
+set_property PACKAGE_PIN N17 [get_ports I2c_Scl]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Scl]
+set_property PACKAGE_PIN P18 [get_ports I2c_Sda]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Sda]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: spi flash
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN L13 [get_ports Flash_Cs_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Cs_N]
+set_property PACKAGE_PIN K17 [get_ports Flash_Di]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Di]
+set_property PACKAGE_PIN M14 [get_ports Flash_Hold_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Hold_N]
+set_property PACKAGE_PIN L14 [get_ports Flash_Wp_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Wp_N]
+set_property PACKAGE_PIN R10 [get_ports Flash_Clk]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Clk]
+set_property PACKAGE_PIN K18 [get_ports Flash_Do]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Do]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: led		
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN M17 [get_ports {Led_N[1]}]
+set_property PACKAGE_PIN M16 [get_ports {Led_N[0]}]
+set_property PACKAGE_PIN M18 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN L18 [get_ports {Led_N[2]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: system		
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R11 [get_ports Pwr_Good]
+set_property IOSTANDARD LVCMOS33 [get_ports Pwr_Good]
+set_property PACKAGE_PIN N15 [get_ports {Reset_N}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Reset_N}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: fmc lpc connector
+# -------------------------------------------------------------------------------------------------
+set_property PACKAGE_PIN T4 [get_ports {CLK_TO_FPGA_N}]
+set_property PACKAGE_PIN T5 [get_ports {CLK_TO_FPGA_P}]
+set_property PACKAGE_PIN D3 [get_ports {CLK_FROM_FPGA_N}]
+set_property PACKAGE_PIN E3 [get_ports {CLK_FROM_FPGA_P}]
+
+set_property PACKAGE_PIN N5 [get_ports {CLK_GEN_LOL_N}]
+set_property PACKAGE_PIN C1 [get_ports {CLK_GEN_RST_N}]
+set_property PACKAGE_PIN C2 [get_ports {I2C_RESET_N}]
+set_property PACKAGE_PIN F6 [get_ports {GPIO}]
+
+set_property PACKAGE_PIN P5 [get_ports {CONT_TO_FPGA[0]}]
+set_property PACKAGE_PIN P3 [get_ports {CONT_TO_FPGA[1]}]
+set_property PACKAGE_PIN N6 [get_ports {CONT_TO_FPGA[2]}]
+set_property PACKAGE_PIN L5 [get_ports {CONT_TO_FPGA[3]}]
+
+# Warning - can't find CONT_FROM_FPGA[0] in Allegro netlist ....
+set_property PACKAGE_PIN P4 [get_ports {CONT_FROM_FPGA[1]}]
+set_property PACKAGE_PIN M6 [get_ports {CONT_FROM_FPGA[2]}]
+set_property PACKAGE_PIN L6 [get_ports {CONT_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN M1 [get_ports {SPARE_TO_FPGA[0]}]
+set_property PACKAGE_PIN N4 [get_ports {SPARE_TO_FPGA[1]}]
+set_property PACKAGE_PIN N1 [get_ports {SPARE_TO_FPGA[2]}]
+set_property PACKAGE_PIN M2 [get_ports {SPARE_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN L1 [get_ports {SPARE_FROM_FPGA[0]}]
+set_property PACKAGE_PIN M4 [get_ports {SPARE_FROM_FPGA[1]}]
+set_property PACKAGE_PIN N2 [get_ports {SPARE_FROM_FPGA[2]}]
+set_property PACKAGE_PIN M3 [get_ports {SPARE_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN R5 [get_ports {TRIG_TO_FPGA[0]}]
+set_property PACKAGE_PIN R2 [get_ports {TRIG_TO_FPGA[1]}]
+set_property PACKAGE_PIN T1 [get_ports {TRIG_TO_FPGA[2]}]
+set_property PACKAGE_PIN V1 [get_ports {TRIG_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R6 [get_ports {TRIG_FROM_FPGA[0]}]
+set_property PACKAGE_PIN P2 [get_ports {TRIG_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R1 [get_ports {TRIG_FROM_FPGA[2]}]
+set_property PACKAGE_PIN U1 [get_ports {TRIG_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN T6 [get_ports {BUSY_TO_FPGA[0]}]
+set_property PACKAGE_PIN U3 [get_ports {BUSY_TO_FPGA[1]}]
+set_property PACKAGE_PIN T8 [get_ports {BUSY_TO_FPGA[2]}]
+set_property PACKAGE_PIN L4 [get_ports {BUSY_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R7 [get_ports {BUSY_FROM_FPGA[0]}]
+set_property PACKAGE_PIN U4 [get_ports {BUSY_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R8 [get_ports {BUSY_FROM_FPGA[2]}]
+set_property PACKAGE_PIN K5 [get_ports {BUSY_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN L3 [get_ports {DUT_CLK_TO_FPGA[0]}]
+set_property PACKAGE_PIN F3 [get_ports {DUT_CLK_TO_FPGA[1]}]
+set_property PACKAGE_PIN D2 [get_ports {DUT_CLK_TO_FPGA[2]}]
+set_property PACKAGE_PIN G3 [get_ports {DUT_CLK_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN K3 [get_ports {DUT_CLK_FROM_FPGA_P[0]}]
+set_property PACKAGE_PIN F4 [get_ports {DUT_CLK_FROM_FPGA_P[1]}]
+set_property PACKAGE_PIN E2 [get_ports {DUT_CLK_FROM_FPGA_P[2]}]
+set_property PACKAGE_PIN G4 [get_ports {DUT_CLK_FROM_FPGA_P[3]}]
+
+set_property PACKAGE_PIN A1 [get_ports {BEAM_TRIGGER_N[0]}]
+set_property PACKAGE_PIN B1 [get_ports {BEAM_TRIGGER_P[0]}]
+set_property PACKAGE_PIN B4 [get_ports {BEAM_TRIGGER_N[1]}]
+set_property PACKAGE_PIN C4 [get_ports {BEAM_TRIGGER_P[1]}]
+set_property PACKAGE_PIN K1 [get_ports {BEAM_TRIGGER_N[2]}]
+set_property PACKAGE_PIN K2 [get_ports {BEAM_TRIGGER_P[2]}]
+set_property PACKAGE_PIN C5 [get_ports {BEAM_TRIGGER_N[3]}]
+set_property PACKAGE_PIN C6 [get_ports {BEAM_TRIGGER_P[3]}]
+set_property PACKAGE_PIN H4 [get_ports {BEAM_TRIGGER_N[4]}]
+set_property PACKAGE_PIN J4 [get_ports {BEAM_TRIGGER_P[4]}]
+set_property PACKAGE_PIN G1 [get_ports {BEAM_TRIGGER_N[5]}]
+set_property PACKAGE_PIN H1 [get_ports {BEAM_TRIGGER_P[5]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ft232 uart interface
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B3 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B2 [get_ports FTDI_RXD]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ez-usb fx3 interface
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN V2 [get_ports FX3_A1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_A1]
+set_property PACKAGE_PIN V7 [get_ports FX3_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_CLK]
+set_property PACKAGE_PIN U12 [get_ports FX3_DQ0]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ0]
+set_property PACKAGE_PIN R15 [get_ports FX3_DQ1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ1]
+set_property PACKAGE_PIN U9 [get_ports FX3_DQ10]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ10]
+set_property PACKAGE_PIN V5 [get_ports FX3_DQ11]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ11]
+set_property PACKAGE_PIN T3 [get_ports FX3_DQ12]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ12]
+set_property PACKAGE_PIN R3 [get_ports FX3_DQ13]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ13]
+set_property PACKAGE_PIN V4 [get_ports FX3_DQ14]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ14]
+set_property PACKAGE_PIN U7 [get_ports FX3_DQ15]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ15]
+set_property PACKAGE_PIN V12 [get_ports FX3_DQ2]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ2]
+set_property PACKAGE_PIN P15 [get_ports FX3_DQ3]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ3]
+set_property PACKAGE_PIN U11 [get_ports FX3_DQ4]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ4]
+set_property PACKAGE_PIN U13 [get_ports FX3_DQ5]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ5]
+set_property PACKAGE_PIN T13 [get_ports FX3_DQ6]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ6]
+set_property PACKAGE_PIN T11 [get_ports FX3_DQ7]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ7]
+set_property PACKAGE_PIN V9 [get_ports FX3_DQ8]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ8]
+set_property PACKAGE_PIN U6 [get_ports FX3_DQ9]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ9]
+set_property PACKAGE_PIN V6 [get_ports FX3_FLAGA]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGA]
+set_property PACKAGE_PIN U2 [get_ports FX3_FLAGB]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGB]
+set_property PACKAGE_PIN T10 [get_ports FX3_PKTEND_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_PKTEND_N]
+set_property PACKAGE_PIN T9 [get_ports FX3_SLOE_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLOE_N]
+set_property PACKAGE_PIN R12 [get_ports FX3_SLRD_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLRD_N]
+set_property PACKAGE_PIN R13 [get_ports FX3_SLWR_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLWR_N]
+
+# -------------------------------------------------------------------------------------------------
+# timing constraints
+# -------------------------------------------------------------------------------------------------
+
+
+create_clock -name {Clk_50} -period 20.000 [get_ports {Clk_50}]
+
+
+# -------------------------------------------------------------------------------------------------
+# eof
+# -------------------------------------------------------------------------------------------------
+
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clock_sim.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clock_sim.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7a9e09e740105fc390fbad6b54b8a9b81f15070a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clock_sim.vhd
@@ -0,0 +1,47 @@
+-- Behavioural model of clocks for ipbus testing
+--
+-- The clock edges are *not* delta cycle accurate
+-- Do not assume any phase relationship between clk125, clk25
+--
+-- Dave Newbold, March 2011
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clock_sim is
+	port(
+	  clko125: out std_logic;
+	  clko25: out std_logic;
+	  clko40: out std_logic;
+	  nuke: in std_logic;
+	  rsto: out std_logic
+  );
+
+end clock_sim;
+
+architecture behavioural of clock_sim is
+
+  signal clk125, clk25, clk40, nuke_del: std_logic := '0';
+  signal reset_vec: std_logic_vector(3 downto 0) := X"f";
+
+begin
+
+  clk125 <= not clk125 after 4 ns;
+  clk25 <= not clk25 after 20 ns;
+  clk40 <= not clk40 after 12.5ns;
+  
+  clko125 <= clk125;
+  clko25 <= clk25;
+  clko40 <= clk40;
+  
+  process(clk25)
+  begin
+    if rising_edge(clk25) then
+      reset_vec <= '0' & reset_vec(3 downto 1);
+    end if;
+  end process;
+
+  nuke_del <= nuke after 50us;
+  rsto <= reset_vec(0) or nuke_del;
+
+end behavioural;
\ No newline at end of file
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..47c0f3b8be2e66484167147fed8c5fec8f591d97
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy.vhd
@@ -0,0 +1,148 @@
+-- clocks_7s_extphy
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy is
+	port(
+		sysclk_p: in std_logic;
+		sysclk_n: in std_logic;
+		clko_125: out std_logic;
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;
+		rsto_ipb: out std_logic;
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic
+	);
+
+end clocks_7s_extphy;
+
+architecture rtl of clocks_7s_extphy is
+	
+	signal dcm_locked, sysclk, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+	ibufgds0: IBUFGDS port map(
+		i => sysclk_p,
+		ib => sysclk_n,
+		o => sysclk
+	);
+	
+	clko_200 <= sysclk; -- io delay ref clock only, no bufg
+
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clk_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 5.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90,
+			clkout3_divide => 32,
+			clkin1_period => 5.0
+		)
+		port map(
+			clkin1 => sysclk,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk125_90_i,
+			clkout3 => clk_ipb_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk)
+	begin
+		if rising_edge(sysclk) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90c77ffd8e81f354ff8f4bc9b4032b834ee70ce3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se.vhd
@@ -0,0 +1,151 @@
+-- clocks_7s_extphy_se
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 50MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy_Se is
+	port(
+		sysclk: in std_logic;
+		clko_125: out std_logic;
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;
+		rsto_ipb: out std_logic;
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic
+	);
+
+end clocks_7s_extphy_se;
+
+architecture rtl of clocks_7s_extphy_se is
+	
+	signal dcm_locked, sysclk_i, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b, clk_200_i: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+	ibufgds0: IBUFG port map(
+		i => sysclk,
+		o => sysclk_i
+	);
+	
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clko_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	bufg200: BUFG port map(
+		i => clk_200_i,
+		o => clko_200
+	);	
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 20.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90.0,
+			clkout3_divide => 32,
+			clkout4_divide => 5,
+			clkin1_period => 20.0
+		)
+		port map(
+			clkin1 => sysclk_i,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk_125_90_i,
+			clkout3 => clk_ipb_i,
+			clkout4 => clk_200_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk_i,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk_i)
+	begin
+		if rising_edge(sysclk_i) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se_MOD.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se_MOD.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7d67ef7b0a9bb441d1b7c26831c9c5859768fc03
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_7s_extphy_se_MOD.vhd
@@ -0,0 +1,158 @@
+-- clocks_7s_extphy_se
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 50MHz reference
+-- Also an unbuffered 200MHz clock for IO delay calibration block
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_7s_extphy_Se is
+	port(
+		--sysclk: in std_logic;
+		sysclk_p: in std_logic;--
+        sysclk_n: in std_logic;--
+        clko_125: out std_logic;--
+		clko_125_90: out std_logic;
+		clko_200: out std_logic;
+		clko_ipb: out std_logic;
+		locked: out std_logic;--
+		nuke: in std_logic;
+		soft_rst: in std_logic;
+		rsto_125: out std_logic;--
+		rsto_ipb: out std_logic;--
+		rsto_ipb_ctrl: out std_logic;
+		onehz: out std_logic--
+	);
+
+end clocks_7s_extphy_se;
+
+architecture rtl of clocks_7s_extphy_se is
+	
+	signal dcm_locked, sysclk_i, sysclk, clk_ipb_i, clk_125_i, clk_125_90_i, clkfb, clk_ipb_b, clk_125_b, clk_200_i: std_logic;
+	signal d17, d17_d: std_logic;
+	signal nuke_i, nuke_d, nuke_d2: std_logic := '0';
+	signal rst, srst, rst_ipb, rst_125, rst_ipb_ctrl: std_logic := '1';
+	signal rctr: unsigned(3 downto 0) := "0000";
+
+begin
+
+--	ibufgds0: IBUFG port map(
+--		i => sysclk,
+--		o => sysclk_i
+--	);
+    ibufgds0: IBUFGDS port map(
+    i => sysclk_p,
+    ib => sysclk_n,
+    o => sysclk
+    );
+	
+	bufg125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+
+	clko_125 <= clk_125_b;
+
+	bufg125_90: BUFG port map(
+		i => clk_125_90_i,
+		o => clko_125_90
+	);
+	
+	bufgipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	clko_ipb <= clk_ipb_b;
+	
+	bufg200: BUFG port map(
+		i => clk_200_i,
+		o => clko_200
+	);	
+	
+	mmcm: MMCME2_BASE
+		generic map(
+			clkfbout_mult_f => 20.0,
+			clkout1_divide => 8,
+			clkout2_divide => 8,
+			clkout2_phase => 90.0,
+			clkout3_divide => 32,
+			clkout4_divide => 5,
+			clkin1_period => 20.0
+		)
+		port map(
+			clkin1 => sysclk_i,
+			clkfbin => clkfb,
+			clkfbout => clkfb,
+			clkout1 => clk_125_i,
+			clkout2 => clk_125_90_i,
+			clkout3 => clk_ipb_i,
+			clkout4 => clk_200_i,
+			locked => dcm_locked,
+			rst => '0',
+			pwrdwn => '0'
+		);
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => sysclk_i,
+			d17 => d17,
+			d28 => onehz
+		);
+	
+	process(sysclk_i)
+	begin
+		if rising_edge(sysclk_i) then
+			d17_d <= d17;
+			if d17='1' and d17_d='0' then
+				rst <= nuke_d2 or not dcm_locked;
+				nuke_d <= nuke_i; -- Time bomb (allows return packet to be sent)
+				nuke_d2 <= nuke_d;
+			end if;
+		end if;
+	end process;
+		
+	locked <= dcm_locked;
+	srst <= '1' when rctr /= "0000" else '0';
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb <= rst or srst;
+			nuke_i <= nuke;
+			if srst = '1' or soft_rst = '1' then
+				rctr <= rctr + 1;
+			end if;
+		end if;
+	end process;
+	
+	rsto_ipb <= rst_ipb;
+	
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rst_ipb_ctrl <= rst;
+		end if;
+	end process;
+	
+	rsto_ipb_ctrl <= rst_ipb_ctrl;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rst_125 <= rst;
+		end if;
+	end process;
+	
+	rsto_125 <= rst_125;
+			
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_s6_extphy.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_s6_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d823b524a714e4dc09385c67def20a0f3baa83f4
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/clocks/clocks_s6_extphy.vhd
@@ -0,0 +1,137 @@
+--! @file clocks_s6_extphy
+-- 
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+--! Includes reset logic for ipbus
+--
+--! @author Dave Newbold
+--! @date April 2011
+--
+entity clocks_s6_extphy is port(
+	sysclk_p, sysclk_n: in std_logic; --! From on board crystal. By default 200MHz
+	clk_logic_xtal_o : out std_logic; --! Clock for TLU timing logic ( when not using external clock ). sysclk/5 ( i.e. by default 40MHz) 
+	clko_125: out std_logic; --! 125MHz for IPBus logic
+	clko_ipb: out std_logic; --! 32.5MHz for IPBus logic
+	locked: out std_logic;
+	rsto_125: out std_logic;
+	rsto_ipb: out std_logic;
+	onehz: out std_logic
+	);
+
+end clocks_s6_extphy;
+
+architecture rtl of clocks_s6_extphy is
+
+	signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
+        -- signal sysclk_in : std_logic;
+	signal d25, d25_d, dcm_locked: std_logic;
+	signal rst: std_logic := '1';
+	signal s_xtal_dcm_locked: std_logic;
+        signal s_clk_logic_xtal : std_logic;
+	-- signal clk_400: std_logic;
+	
+--	component clock_divider_s6 port(
+--		clk: in std_logic;
+--		d25: out std_logic;
+--		d28: out std_logic
+--	);
+--	end component;
+	
+begin
+
+	ibufgds0: IBUFGDS port map(
+		i => sysclk_p,
+		ib => sysclk_n,
+		o => sysclk
+	);
+
+--        -- Add global clock buffer in sysclk path.
+--        bufg_sysclk : BUFG port map (
+--          i => sysclk_in,
+--          o => sysclk);
+        
+	bufg_125: BUFG port map(
+		i => clk_125_i,
+		o => clk_125_b
+	);
+	
+	clko_125 <= clk_125_b;
+	
+	bufg_ipb: BUFG port map(
+		i => clk_ipb_i,
+		o => clk_ipb_b
+	);
+	
+	bufg_clk_logic_xtal: BUFG port map(
+	  i => s_clk_logic_xtal,
+	  o => clk_logic_xtal_o
+	  );
+	  
+	clko_ipb <= clk_ipb_b;
+
+	dcm0: DCM_CLKGEN
+		generic map(
+			CLKIN_PERIOD => 5.0,
+			CLKFX_MULTIPLY => 5,
+			CLKFX_DIVIDE => 8,
+			CLKFXDV_DIVIDE => 4
+		)
+		port map(
+			clkin => sysclk,
+			clkfx => clk_125_i,
+			clkfxdv => clk_ipb_i,
+			locked => dcm_locked,
+			rst => '0'
+		);
+		
+	clkdiv: entity work.clock_divider_s6 port map(
+--        clkdiv: entity work.clock_div port map(
+		clk => sysclk,
+--                D17 => open,
+		d25 => d25,
+		d28 => onehz
+	);
+	  
+	process(sysclk)
+	begin
+		if rising_edge(sysclk) then
+			d25_d <= d25;
+			if d25='1' and d25_d='0' then
+				rst <= not dcm_locked;
+			end if;
+		end if;
+	end process;
+	
+	locked <= dcm_locked;
+
+	process(clk_ipb_b)
+	begin
+		if rising_edge(clk_ipb_b) then
+			rsto_ipb <= rst;
+		end if;
+	end process;
+	
+	process(clk_125_b)
+	begin
+		if rising_edge(clk_125_b) then
+			rsto_125 <= rst;
+		end if;
+	end process;
+
+        sys40_gen : BUFIO2
+          generic map (
+            DIVIDE => 5,            -- DIVCLK divider (1-8)
+            DIVIDE_BYPASS => FALSE) -- Bypass the divider circuitry (TRUE/FALSE)
+          port map (
+            I => SysClk,        -- 1-bit input: Clock input (connect to IBUFG)
+            DIVCLK =>  s_clk_logic_xtal,   -- 1-bit output: Divided clock output
+            IOCLK => open,          -- 1-bit output: I/O output clock
+            SERDESSTROBE => open);  -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+        
+                
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..217fa22453b724a07f70ef4bf27f159013828499
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl.vhd
@@ -0,0 +1,158 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    --auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_low_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (lowest 32-bits)
+    triggerPattern_high_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with (highest 32-bits)
+    loadPatternHi_i    : in std_logic; --! Pattern (high 32 bits) is loaded when loadPatternHi goes high.
+    loadPatternLo_i    : in  std_logic);  --! Pattern (low 32 bits) is loaded when loadPatternLo goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR_low , s_configEnableSR_low: std_logic_vector( triggerPattern_low_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configDataSR_high , s_configEnableSR_high: std_logic_vector( triggerPattern_high_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit_low, s_configBit_high, s_configEnable_low, s_configEnable_high : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut_low, s_trigOut_high, s_auxTrigOut_low, s_auxTrigOut_high : std_logic := '0';  -- registers for output data. (s_auxTrig high and low should be removed)
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  -- We now need 6 inputs in the LUT and we need to dynamically change it so we merge two 5-inputs together:
+  -- one does the low 32 bits of the address table, the other the high 32 bits.
+  LUT_low : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs (exclude case with no input at all)
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => open ,  -- 4-LUT output
+      O6 => s_trigOut_low, -- 5-LUT output
+      CDI => s_configBit_low, -- Reconfiguration data input
+      CE => s_configEnable_low, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+      );
+   
+   LUT_high : CFGLUT5
+    generic map (
+        INIT => X"FFFFFFFF") --! Default to "OR" of all inputs
+    port map (
+        CDO => open, -- Reconfiguration cascade output
+        O5 => open ,  -- 4-LUT output
+        O6 => s_trigOut_high, -- 5-LUT output
+        CDI => s_configBit_high, -- Reconfiguration data input
+        CE => s_configEnable_high, -- Reconfiguration enable input
+        CLK => configClk_i, -- Clock input
+        I0 => triggers_i(0), -- Logic data input
+        I1 => triggers_i(1), -- Logic data input
+        I2 => triggers_i(2), -- Logic data input
+        I3 => triggers_i(3), -- Logic data input
+        I4 => triggers_i(4) --! Tie high to set O5 and O6 to different functions.
+    );   
+
+  p_controlInitLo: process (configClk_i , triggerPattern_low_i , loadPatternLo_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Control configuration
+      if ( loadPatternLo_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR_low <= triggerPattern_low_i;
+        s_configEnableSR_low <= ( others => '1');
+        s_configBit_low <= '0';
+        s_configEnable_low <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit_low    <= s_configDataSR_low( s_configDataSR_low'left ); --! Shift in MSB first.
+        s_configDataSR_low <= s_configDataSR_low( s_configDataSR_low'left-1 downto 0) & '0'; --! Shift up
+                
+        s_configEnable_low <= s_configEnableSR_low ( s_configEnableSR_low'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR_low <= s_configEnableSR_low( s_configEnableSR_low'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInitLo;
+  
+  -- Add a second control for the secondary LUT introduced when we moved to 6 inputs.
+  p_controlInitHi: process (configClk_i , triggerPattern_high_i,  loadPatternHi_i) is
+    begin  -- process p_controlInit
+  
+      if rising_edge(configClk_i) then
+  
+        -- Control configuration
+        if ( loadPatternHi_i = '1' ) then -- Load pattern into shift register
+          s_configDataSR_high <= triggerPattern_high_i;
+          s_configEnableSR_high <= ( others => '1');
+          s_configBit_high <= '0';
+          s_configEnable_high <= '0';
+        else -- If load isn't active then shift data out.
+          s_configBit_high    <= s_configDataSR_high( s_configDataSR_high'left ); --! Shift in MSB first.
+          s_configDataSR_high <= s_configDataSR_high( s_configDataSR_high'left-1 downto 0) & '0'; --! Shift up
+                  
+          s_configEnable_high <= s_configEnableSR_high ( s_configEnableSR_high'left); --! enable will stay high for as long as there is data in config data SR
+          s_configEnableSR_high <= s_configEnableSR_high( s_configEnableSR_high'left-1 downto 0) & '0'; --! Shift up
+        end if;
+  
+    end if;
+    end process p_controlInitHi;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+        if triggers_i(5) = '0' then -- the LUT has 5 inputs. We use a MUX to considere the 6th one (triggers_i(5)).
+            trigger_o <=  s_trigOut_low;
+            --auxTrigger_o <= s_auxTrigOut_low;
+        else
+            trigger_o <=  s_trigOut_high;
+            --auxTrigger_o <= s_auxTrigOut_high;
+        end if;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..32b57b74f04c1898bbbb6668a1f1f6d6e6e1bee5
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/coincidenceLogic_rtl_BKP.vhd
@@ -0,0 +1,108 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+-- Include UNISIM to get CFGLUT5 definition
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+--! @brief Takes a set of input pulses and produces an output pulse based on trigger
+--! pattern. Defaults to "OR" of all inputs.
+--!
+--! @details If triggers_i matches a pattern in triggerPattern then trigger_o
+--! goes high for one clock cycle of logicClk_o. Load a new pattern by taking loadPattern_i high for one cycle of configClk_i
+--!
+--! @author David Cussans
+--! @date 2014
+-------------------------------------------------------------------------------
+
+entity coincidenceLogic is
+  
+  generic (
+    g_nInputs      : positive := 4;  --! Number of trigger inputs. Must be four for this implementation
+    g_patternWidth : positive := 32);  --! Width of trigger pattern. Must be 32 in this implementation
+
+  port (
+    configClk_i      : in  std_logic;   --! Rising edge active
+    logicClk_i       : in  std_logic;   --! Rising edge active
+    triggers_i       : in  std_logic_vector(g_nInputs-1 downto 0);  --! Array of trigger inputs
+    trigger_o        : out std_logic;  --! Goes high when trigger pattern matched
+    auxTrigger_o     : out std_logic;  --! Goes high when auxillary trigger pattern matched
+    triggerPattern_i : in  std_logic_vector(g_patternWidth-1 downto 0);  --! Pattern to match triggers with
+    loadPattern_i    : in  std_logic);  --! Pattern is loaded when loadPattern goes high.
+
+end entity coincidenceLogic;
+
+architecture rtl of coincidenceLogic is
+
+  signal s_configDataSR , s_configEnableSR: std_logic_vector( triggerPattern_i'range ) := ( others => '0' );  --! shift reg for config data
+  signal s_configBit , s_configEnable : std_logic := '0';  --! Take high to shift in configuration data.
+  signal s_trigOut , s_auxTrigOut : std_logic := '0';  -- registers for output data.
+  
+begin  -- architecture rtl
+
+  --assert g_nInputs /= 4 report "Wrong number of inputs in coincidence logic" severity failure;
+  --assert g_patternWidth /= 32 report "Wrong pattern width in coincidence logic" severity failure;
+
+  -- See Xilinx UG615 ( Spartan-6 Libraries guide for HDL Designs"
+  CFGLUT5_inst : CFGLUT5
+    generic map (
+      INIT => X"FFFEFFFE") --! Default to "OR" of all inputs
+    port map (
+      CDO => open, -- Reconfiguration cascade output
+      O5 => s_trigOut ,  -- 4-LUT output
+      O6 => s_auxTrigOut, -- 5-LUT output
+      CDI => s_configBit, -- Reconfiguration data input
+      CE => s_configEnable, -- Reconfiguration enable input
+      CLK => configClk_i, -- Clock input
+      I0 => triggers_i(0), -- Logic data input
+      I1 => triggers_i(1), -- Logic data input
+      I2 => triggers_i(2), -- Logic data input
+      I3 => triggers_i(3), -- Logic data input
+      I4 => '1' --! Tie high to set O5 and O6 to different functions.
+      );
+
+  p_controlInit: process (configClk_i , triggerPattern_i , loadPattern_i) is
+  begin  -- process p_controlInit
+
+    if rising_edge(configClk_i) then
+
+      -- Contol configuration
+      if ( loadPattern_i = '1' ) then -- Load pattern into shift register
+        s_configDataSR <= triggerPattern_i;
+        s_configEnableSR <= ( others => '1');
+        s_configBit <= '0';
+        s_configEnable <= '0';
+      else -- If load isn't active then shift data out.
+        s_configBit    <= s_configDataSR( s_configDataSR'left ); --! Shift in MSB first.
+        s_configDataSR <= s_configDataSR( s_configDataSR'left-1 downto 0) & '0'; --! Shift up
+        
+        s_configEnable <= s_configEnableSR ( s_configEnableSR'left); --! enable will stay high for as long as there is data in config data SR
+        s_configEnableSR <= s_configEnableSR( s_configEnableSR'left-1 downto 0) & '0'; --! Shift up
+      end if;
+
+  end if;
+  end process p_controlInit;
+
+  --! Register output data
+  p_registerData: process (logicClk_i) is
+  begin  -- process p_registerData
+    if rising_edge(logicClk_i) then
+      trigger_o <=  s_trigOut;
+      auxTrigger_o <= s_auxTrigOut;
+    end if;
+  end process p_registerData;
+  
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/counterDown.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/counterDown.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de1509001a37cdc74e132a60d4201581a96d83aa
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/counterDown.vhd
@@ -0,0 +1,50 @@
+--Counter down
+--Outputs: 	Q<='1' while counting
+--				Q<='0' if not counting
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY CounterDown IS
+	GENERIC(
+		MAX_WIDTH: positive := 32
+	);
+	PORT( 
+		Clk		: in  std_logic; 
+		Reset		: in  std_logic; 
+		Load 		: in  std_logic; 
+		InitVal 	: in std_logic_vector(MAX_WIDTH-1 downto 0);
+		Count		: out Std_logic_vector(MAX_WIDTH-1 downto 0);
+		Q 			: out std_logic
+	);
+END ENTITY CounterDown;
+
+architecture rtl of CounterDown is 
+	signal cnt	: std_logic_vector(MAX_WIDTH-1 downto 0);
+	signal Qtmp	: std_logic;
+  
+begin 
+	Counter: process (Clk, Reset)
+	begin 
+		if (Reset='1') then 
+			cnt <= (others =>'0');
+		elsif rising_edge(Clk) then
+			if (Load='1') then
+				cnt <= InitVal;
+			else
+				if Qtmp='0' then
+					cnt <= std_logic_vector(unsigned(cnt) - 1);
+				end if;
+			end if;
+		end if; 
+	end process;
+      
+	Qtmp <= 	'1' when cnt=(cnt'range=>'0') else
+				'0';
+          
+	Count <= cnt;
+	Q <= Qtmp;
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/counterWithReset_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/counterWithReset_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2512f986b5588355209563d702e313eec3fcd86d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/counterWithReset_rtl.vhd
@@ -0,0 +1,84 @@
+--=============================================================================
+--! @file counterWithReset_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: counterWithReset (counterWithReset / rtl)
+--
+--============================================================================
+--! Entity declaration for counterWithReset
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+--! @brief Simple counter with synchronous reset
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date Feb\2012
+--
+--! @version v0.1
+--
+-------------------------------------------------------------------------------
+--! @details
+--! \n\n<b>Last changes:</b>\n
+--! 5/Mar/12  DGC Changed to use numeric_std\n
+--! 26/Feb/14 DGC Added registers to output to aid timing closure.
+--! 
+
+
+
+ENTITY counterWithReset IS
+  GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
+           g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
+           );
+  PORT
+    (
+      clock_i: 	IN STD_LOGIC;  --! rising edge active clock
+      reset_i:  IN STD_LOGIC;  --! Active high. syncronous with rising clk
+      enable_i: IN STD_LOGIC;  --! counts when enable=1
+      result_o:	OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
+      
+      );
+END counterWithReset;
+
+ARCHITECTURE rtl OF counterWithReset IS
+  type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ;  -- --! Array of arrays for output register...
+  signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0'));  -- --! Output registers.
+  
+BEGIN
+
+  --! Process to count up from zero when enable_i is high.
+  p_counter: PROCESS (clock_i)
+  BEGIN
+    IF rising_edge(clock_i) THEN
+      IF (reset_i = '1') THEN
+        s_output_registers(0) <= (others => '0');
+      ELSIF (enable_i='1') THEN
+        s_output_registers(0) <= s_output_registers(0) + 1;
+      END IF;
+    END IF;
+  END PROCESS p_counter;
+
+  --! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
+  generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
+
+    --! An individual register
+    p_outputRegister: process (clock_i)
+    begin  -- process p_outputRegister
+      if rising_edge(clock_i) then
+        s_output_registers( v_register) <=
+        s_output_registers( v_register-1);
+      end if;
+    end process p_outputRegister;
+    
+  end generate generate_registers;  -- v_register
+
+  --! Copy the (registered) result to the output 
+  result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
+  
+END rtl;		
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_AIDA_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_AIDA_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d6d9ac8002adc97bf9a2cf297bce861c1d6fdd2e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_AIDA_rtl.vhd
@@ -0,0 +1,152 @@
+--=============================================================================
+--! @file DUTInterface_AIDA_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterface_AIDA.rtl
+--
+--------------------------------------------------------------------------------
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+--! @brief "AIDA Style" Interface to a Device Under Test (DUT) connector.
+--! factorized from original DUTInterfaces_rtl.vhd firmware.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 1/Sept/2015
+--!
+--! @version v0.1
+--!
+--! @details
+--
+
+ENTITY DUTInterface_AIDA IS
+   GENERIC( 
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;      --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;      --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;      --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;      --! Goes high to indicate data-taking active. DUTs report busy unless ignore_shutter_veto  flag is set high
+      ignore_shutter_veto_i   : in     std_logic;
+      ignore_dut_busy_i       : in     std_logic;
+      dut_mask_i              : in     std_logic;      --! Set high if DUT is active.
+      busy_o                  : OUT    std_logic;      --! goes high when DUT is busy or vetoed by shutter
+      
+      -- Signals to/from DUT
+      dut_busy_i       : IN     std_logic;     --! BUSY input from DUTs
+      dut_clk_o        : OUT    std_logic;     --! clocks trigger data when in EUDET mode
+      dut_reset_or_clk_o : OUT    std_logic;     --! Either reset line or trigger
+      dut_shutter_o      : OUT    std_logic;     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      dut_trigger_o      : OUT    std_logic     --! Trigger output
+
+   );
+
+-- Declarations
+
+END ENTITY DUTInterface_AIDA ;
+
+--
+ARCHITECTURE rtl OF DUTInterface_AIDA IS
+
+  signal s_strobe_4x_logic_d1 : std_logic;
+  signal s_dut_clk : std_logic := '0';  -- Clock to be sent to DUT connectors ( before final register )
+  signal s_dut_clk_sr : std_logic_vector(2 downto 0) := "001"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
+  signal s_stretch_trig_in : std_logic := '0';  -- ! stretched version of trigger_i 
+  signal s_stretch_trig_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by trigger_i
+  signal s_trigger_out : std_logic := '0';  -- ! trigger shifted to start on strobe_4x_logic
+
+  -- Set length of output trigger here ( output length = length of this vector + 1 ) 
+  signal s_trigger_out_sr : std_logic_vector(2 downto 0) := ( others => '1'); --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic.
+  
+                                                               
+BEGIN
+
+     
+  -- Copy reset/clk signal straight through
+  dut_reset_or_clk_o <= reset_or_clk_to_dut_i;
+
+  dut_shutter_o <= shutter_to_dut_i;
+      
+  -- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
+  -- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_i
+  -- outputs: s_dut_clk
+  p_dut_clk_gen: process (clk_4x_logic_i , strobe_4x_logic_i) is
+  begin  -- process p_dut_clk_gen
+    if rising_edge(clk_4x_logic_i) then
+      if (strobe_4x_logic_i = '1') then
+        s_dut_clk <= '1';
+        s_dut_clk_sr <= "001";
+      else
+        s_dut_clk <= s_dut_clk_sr(0);
+        s_dut_clk_sr <= '0' & s_dut_clk_sr(s_dut_clk_sr'left downto 1);          
+      end if;
+    end if;
+  end process p_dut_clk_gen;
+
+  -- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic 
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
+  -- outputs: s_premask_trigger_to_dut
+  p_dut_trig_retime: process (clk_4x_logic_i , strobe_4x_logic_i , trigger_i) is
+  begin  -- process p_dut_trig_retime
+    if rising_edge(clk_4x_logic_i)  then
+
+      -- Stretch trigger_i pulse to 4 clock cycles on clk4x
+      if trigger_i = '1' then
+        s_stretch_trig_in <= '1';
+        s_stretch_trig_in_sr <= ( others => '1' );
+      else
+        s_stretch_trig_in <= s_stretch_trig_in_sr(0);
+        s_stretch_trig_in_sr <= '0' & s_stretch_trig_in_sr(s_stretch_trig_in_sr'left downto 1);
+      end if;
+
+      -- 
+      if (strobe_4x_logic_i  = '1') and ( s_stretch_trig_in = '1' ) then
+        s_trigger_out <= '1';
+        s_trigger_out_sr <= ( others => '1' );
+      else
+        s_trigger_out <= s_trigger_out_sr(0);
+        s_trigger_out_sr <= '0' & s_trigger_out_sr(s_trigger_out_sr'left downto 1);
+      end if;
+      
+    end if;
+  end process p_dut_trig_retime;
+
+    
+  -- purpose: register for internal signals and output signals
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
+  -- outputs: busy_o
+  register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
+  begin  -- process register_signals
+    if rising_edge(clk_4x_logic_i) then
+
+      s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
+
+      --busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
+      --          ((dut_busy_i and DUT_mask_i ) and (not ignore_dut_busy_i) );
+                
+      busy_o <= ((not ignore_shutter_veto_i ) and (not shutter_to_dut_i)) or
+                ( (dut_busy_i and DUT_mask_i )  );
+
+      dut_clk_o <= s_dut_clk ;
+      dut_trigger_o <= DUT_mask_i and s_trigger_out;
+      
+    end if;
+  end process register_signals;
+
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_EUDET_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_EUDET_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cd56e09b7cfdc60ce8a30055e19c294fa324be12
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterface_EUDET_rtl.vhd
@@ -0,0 +1,277 @@
+--! @file
+-------------------------------------------------------------------------------
+--
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+--! @brief "EUDET style" interfaces to a DUT connection. Outputs TRIGGER and receives DUT_CLK and BUSY
+--! lines. Adapted from Trigger_Signal_Controller from EUDET TLU firmware.
+--!
+--! @author David.Cussans@bristol.ac.uk
+--! @date 1/Sept/2015
+------------------------------------------------------------------------------------
+entity DUTInterface_EUDET is
+  GENERIC( 
+    g_TRIGGER_DATA_WIDTH : positive := 32 -- was32
+   );
+  port (
+    rst_i : in std_logic;                --! asynchronous reset. Active high
+    busy_o : out std_logic;             --! low if FSM is in IDLE state, high otherwise
+    fsm_state_value_o : out std_logic_vector(3 downto 0);  --! detailed status of FSM.
+    trigger_i : in std_logic;        --! Trigger retimed onto system clock.active high. 
+    trigger_counter_i : in std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  --! event number
+    system_clk_i : in std_logic;          --! rising edge active clock from TLU
+    reset_or_clk_to_dut_i   : IN     std_logic;  --! Synchronization signal. Passed to DUT pins
+    shutter_to_dut_i        : IN     std_logic;  --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto flag set high
+    ignore_shutter_veto_i        : in     std_logic;
+    enable_dut_veto_i : in std_logic;      --! If high: if DUT raises dut_busy_i, then  busy_o is raised
+    -- Connections to DUT:
+    dut_clk_i : in std_logic;             --! rising edge active clock from DUT
+    dut_busy_i : in std_logic;            --! from DUT
+    dut_shutter_o      : OUT    std_logic;     --! Shutter output.
+    dut_trigger_o : out std_logic    --! trigger to DUT
+    );
+end DUTInterface_EUDET;
+
+architecture rtl of DUTInterface_EUDET is
+
+-----------------------------------------------------------------------------
+-- Declarations for state machine
+  type state_type is (IDLE , WAIT_FOR_BUSY_HIGH , TRIGGER_DEGLITCH_DELAY1 ,
+                      TRIGGER_DEGLITCH_DELAY2 , WAIT_FOR_BUSY_LOW 
+                     , DUT_INITIATED_VETO );
+--                      );
+  signal state , next_state : state_type;
+
+  -- Xilinx Voodoo for state machine
+  attribute SAFE_IMPLEMENTATION : string;
+  attribute SAFE_IMPLEMENTATION of state : signal is "yes";
+  -- End of Xilinx Voodoo
+
+-----------------------------------------------------------------------------
+
+--  signal internal_clk : std_logic;
+  signal serial_trig_data : std_logic;
+  signal trig_shift_reg : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  
+                                        -- shift register storing parallel trigger data
+--  signal d1_output  :  std_logic;
+--  signal d2_output  :  std_logic;
+  signal dut_rising_edge  :  std_logic;
+  signal shift_reg_ce  :  std_logic;
+
+  signal dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2 : std_logic;  -- ! registered values
+  signal trigger_counter_copy : std_logic_vector(g_TRIGGER_DATA_WIDTH-1 downto 0);  --! registered copy of event number
+  
+begin  -- rtl
+
+
+  dut_shutter_o <= shutter_to_dut_i ; -- for now just pass through.
+  
+  -- purpose: suppress meta-stability by registering input signals.
+  -- type   : combinational
+  -- inputs : dut_busy_r1 , dut_busy_r2 , dut_clk_r1 , dut_clk_r2
+  -- outputs: dut_busy_r2 , dut_clk_r2
+  register_signals: process ( dut_busy_r1 , dut_clk_r1 , system_clk_i )
+  begin  -- process register_signals
+    if rising_edge(system_clk_i) then
+
+      dut_busy_r2 <= dut_busy_r1 ;
+      dut_clk_r2 <= dut_clk_r1;
+      dut_busy_r1 <= dut_busy_i ;
+      dut_clk_r1 <= dut_clk_i;
+      
+    end if;
+  end process register_signals;
+
+
+  
+  rising_edge_pulse: entity work.single_pulse
+    port map (
+      level => dut_clk_i,
+      clk   => system_clk_i,
+      pulse => dut_rising_edge);
+
+  
+-- look for the rising edge of DUT clock and enable CE for one cycle.
+  -- I have a nasty suspicion that meta-stability issues may make this
+  -- go horribly wrong .
+-- Need to add timing constraint that shift_reg_ce must arrive before clock at trig_data_driver
+-- also WAIT_FOR_BUSY_LOW must not mess things up.
+  clk_enable_select: process (state, dut_rising_edge)
+begin  -- process
+  if (state=WAIT_FOR_BUSY_LOW) then
+    shift_reg_ce <= dut_rising_edge;
+  else
+    shift_reg_ce <= '0';
+  end if;
+end process;
+
+  
+   
+  
+  -- purpose: controls the serial_trig_data line
+  -- type   : combinational
+  -- inputs : system_clk_i , trigger_counter_i
+  -- outputs: serial_trig_data
+  trig_data_driver: process (system_clk_i , trigger_counter_copy , shift_reg_ce , trig_shift_reg , state)
+  begin
+    
+    if rising_edge( system_clk_i ) then
+
+      -- if busy is high in response to a trigger shift data out of
+      -- register on rising edge of DUT clock . This is done by having a slow
+      -- DUT clock and setting shift_reg_ce for one cycle of system_clk_i when
+      -- the DUT clock rising edge comes by.
+      if (shift_reg_ce ='1' ) then
+        trig_shift_reg <= '0' & trig_shift_reg(g_TRIGGER_DATA_WIDTH-1 downto 1);
+        serial_trig_data <= trig_shift_reg(0);
+
+      -- otherwise load shift register if we have just had a trigger.
+      elsif (state = WAIT_FOR_BUSY_HIGH ) then        
+	-- only clock out bottom 15 bits of data. 
+        -- (replace fixed width with a mask at some stage ?)
+	trig_shift_reg <=  "00000000000000000" & trigger_counter_copy(14 downto 0);
+        serial_trig_data <= '0';
+      end if;
+
+    end if;
+    
+  end process trig_data_driver;
+
+
+  -- purpose: Determine the next state
+  -- type   : combinational
+  -- inputs : state,Dut_Busy_r2, trigger_i
+  state_logic: process (state,  trigger_i ,  enable_dut_veto_i , dut_clk_r2, dut_busy_r2 )
+  begin  -- process state_logic
+    case state is
+	 
+      when IDLE =>
+        if ( trigger_i = '1') then  -- respond to trigger going high
+          next_state <= WAIT_FOR_BUSY_HIGH;  -- wait for DUT to respond to busy
+          trigger_counter_copy <= trigger_counter_i; -- register the trigger number to shift it out
+
+        elsif ( (dut_clk_r2 = '1') and (enable_dut_veto_i = '1') ) then      -- If DUT asserts DUT_CLK_I then veto triggers
+          next_state <= DUT_INITIATED_VETO;          
+
+        else          
+          next_state <= IDLE;
+        end if;
+
+      when WAIT_FOR_BUSY_HIGH =>
+        if (DUT_Busy_r2 = '1') then
+          next_state <= TRIGGER_DEGLITCH_DELAY1;
+        else
+          next_state <= WAIT_FOR_BUSY_HIGH;
+        end if;
+
+        -- put in a pause to supress glitch in output trigger
+        -- this is an inelegant (to say the least ) way of doing it.
+      when TRIGGER_DEGLITCH_DELAY1 =>
+          next_state <= TRIGGER_DEGLITCH_DELAY2;
+
+      -- delay for two clock cycles.
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        next_state <= WAIT_FOR_BUSY_LOW;
+
+
+
+      when WAIT_FOR_BUSY_LOW =>
+        if (DUT_Busy_r2 = '1')  then
+          next_state <= WAIT_FOR_BUSY_LOW;
+        else
+          next_state <= IDLE;
+        end if;        
+
+      when DUT_INITIATED_VETO =>
+        if (( dut_clk_r2 = '0' ) or ( enable_dut_veto_i = '0')) then
+          next_state <= IDLE;
+        else
+          next_state <= DUT_INITIATED_VETO;
+        end if;
+        
+    end case;
+  end process state_logic;
+
+  -- determine clock select and trigger_mux from FSM state
+
+  
+  -- purpose: Determines the state of the dut_trigger_o output based on the state of the FSM
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: dut_trigger_o
+  output_logic: process (state,serial_trig_data)
+  begin  -- process output_logic
+    if ( state = IDLE ) then
+      -- waiting for external trigger to arrive...
+      dut_trigger_o <= '0';
+    elsif ((state = WAIT_FOR_BUSY_HIGH) or ( state=TRIGGER_DEGLITCH_DELAY1) or (state=TRIGGER_DEGLITCH_DELAY2) ) then
+      -- wait until the BUSY line goes high, then continue to hold TRIGGER high for two clock cycles.
+      dut_trigger_o <= '1';
+    elsif (state = WAIT_FOR_BUSY_LOW) then
+      -- if BUSY is high then connect TRIGGER to serial trigger number register.
+      dut_trigger_o <= serial_trig_data;
+    else
+      dut_trigger_o <= '0';
+    end if;
+  end process output_logic;
+
+    -- purpose: Register that holds the current state of the FSM
+  -- type   : combinational
+  -- inputs : system_clk_i , rst_i
+  -- outputs: state
+  state_register: process (system_clk_i , rst_i)
+  begin  -- process state_register
+    if (rst_i = '1') then
+      state <= IDLE;
+    elsif rising_edge(system_clk_i) then
+      state <= next_state;
+    end if;
+  end process state_register;
+
+
+  -- purpose: sets the value of clock_select based on FSM state
+  -- type   : combinational
+  -- inputs : state
+  -- outputs: clock_select , trigger_muxsel , fsm_state
+  set_busy: process (system_clk_i , state)
+  begin  -- process set_muxsel
+    if rising_edge(system_clk_i) then
+          if (state = IDLE) then
+            busy_o <= '0';
+          else
+            busy_o <= '1';
+          end if;
+    end if;
+ end process set_busy;
+  
+  -- purpose: Sets the fsm_state_value_o vector to a number representing the current state
+  -- type   : combinational
+  -- inputs : system_clk_i , state
+  -- outputs: fsm_state_value_o
+  store_state: process (system_clk_i , state)
+  begin  -- process store_state
+    case state is
+      when IDLE =>
+        fsm_state_value_o <= "0000";
+      when WAIT_FOR_BUSY_HIGH =>
+        fsm_state_value_o <= "0001";
+      when TRIGGER_DEGLITCH_DELAY1 =>
+        fsm_state_value_o <= "0010";
+      when TRIGGER_DEGLITCH_DELAY2 =>
+        fsm_state_value_o <= "0011";
+      when WAIT_FOR_BUSY_LOW =>
+        fsm_state_value_o <= "0100";
+      when DUT_INITIATED_VETO =>
+        fsm_state_value_o <= "0101";
+      when others =>
+        fsm_state_value_o <= "1111";
+    end case;
+  end process store_state;
+
+
+
+  end rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ba5d800c9e4c68c336c308820ddf520fac8ce5a7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl.vhd
@@ -0,0 +1,358 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs (single ended)
+      busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+      clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+      trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      
+      --clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      --reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      --reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+      --trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      --shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      --shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+  
+  signal s_SPILL_delay : std_logic_vector(31 downto 0) := (others => '0');
+  signal s_SPILL_wait : std_logic_vector(31 downto 0) := (others => '0');
+  signal s_SPILL_width : std_logic_vector(31 downto 0) := (others => '0');
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 9;
+  constant c_N_STAT : positive := 9;
+  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                                               
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+------------------------------------------------------------------        
+--    clk_IOBUFDS_inst : IOBUFDS
+--      generic map (
+--        IOSTANDARD => "BLVDS_25")
+--      port map (
+--        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+--        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+--        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+--        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+--        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+--        );
+    
+        clk_to_dut(dut) <= s_clk_to_dut_aida(dut); -- do we need to disable this using T? No, the TLU now has enable signals.
+        s_clk_from_dut_eudet(dut) <= clk_from_dut(dut);
+        
+------------------------------------------------------------------        
+        -- Now the signals are single ended: remove IBUFDS and use IBUF
+--    busy_IBUFDS_inst : IBUFDS
+--      generic map (
+--        DIFF_TERM => TRUE, -- Differential Termination 
+--        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O => s_busy_from_dut(dut),  -- Buffer output
+--        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+--        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+--      );
+
+--    busy_IBUF_inst : IBUF
+--    generic map(
+--        IBUF_LOW_PWR => TRUE,
+--        IOSTANDARD => "DEFAULT"
+--    )
+--    port map(
+--        O => s_busy_from_dut(dut),
+--        I => busy_from_dut(dut)
+--    );
+    s_busy_from_dut(dut) <= busy_from_dut(dut) ;
+------------------------------------------------------------------        
+   
+--    trig_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+--        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+--      );
+
+    trigger_to_dut(dut) <= s_trigger_to_dut(dut);
+------------------------------------------------------------------        
+     
+--    clk_rst_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+--        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+--        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+--      );
+	
+	reset_to_dut(dut) <= s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut); 
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs 
+  dut_shutter_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+--    shutter_OBUFDS_inst : OBUFDS
+--      generic map (
+--        IOSTANDARD => "LVDS_25")
+--      port map (
+--        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+--        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+--        I =>  s_shutter_to_dut(dut) 	
+--        );
+        
+    shutter_to_dut(dut) <= s_shutter_to_dut(dut) ;	  
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs, take into account IGNORE BUSY bit
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or ( s_dut_veto(dut) and (not s_DUT_ignore_busy(dut) ) );
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  veto_o <=  s_intermediate_busy_or(g_NUM_DUTS);
+
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode) ;
+      s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode) ;
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6a19837a51836d597e13f99770e762fc1743831a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTInterfaces_rtl_BKP.vhd
@@ -0,0 +1,328 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- hds interface_start
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+--! @brief Interfaces to Device Under Test (DUT) connectors.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:09:50 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBUS Address map:
+--! \n (Decodes 4 bits)
+--! \li 0x00000000 - DUT mask(write). 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210
+--! \li 0x00000001 - Ignore DUT busy. 1 = ignore BUSY from this connector
+--! \li 0x00000002 - Ignore shutter veto. 0 = raising shutter vetos triggers.
+--! \li 0x00000003 - DUT interface mode, two bits per DUT. Up to 12 inputs  XXXXXXXXBBAA99887766554433221100 mode: 0 = EUDET mode , 1 = synchronous/AIDA ( LHC / Timepix ) , 2,3=reserved
+--! \li 0x00000004 - DUT mode modifier: XXXXXXXXBBAA99887766554433221100 in EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers
+--! \li 0x00000008 - DUT mask ( read )
+--! \li 0x0000000D - EUDET interface FSM status. Packed 4 bits per i/face ( read )
+--!
+--! DUT(0) = RJ45 ( J3 )\n
+--! DUT(1) = HDMI ( J1 ) , furthest from RJ45\n
+--! DUT(2) = HDMI ( J2) , closest to RJ45\n
+--!
+--! <b>Modified by:</b>\n
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+-- todo  Indicate if the DUT works under AIDA/EUDET style
+--
+ENTITY DUTInterfaces IS
+   GENERIC( 
+      g_NUM_DUTS    : positive := 3;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      clk_4x_logic_i          : IN     std_logic;
+      strobe_4x_logic_i       : IN     std_logic;                                    --! goes high every 4th clock cycle
+      trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  --! Number of trigger events since last reset
+      trigger_i               : IN     std_logic;                                    --! goes high when trigger logic issues a trigger
+      reset_or_clk_to_dut_i   : IN     std_logic;                                    --! Synchronization signal. Passed to DUT pins
+      shutter_to_dut_i        : IN     std_logic;                                    --! Goes high to indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+      -- IPBus signals.
+      ipbus_clk_i             : IN     std_logic;
+      ipbus_i                 : IN     ipb_wbus;                                     --! Signals from IPBus core to slave
+      ipbus_reset_i           : IN     std_logic;
+      ipbus_o                 : OUT    ipb_rbus;                                     --! signals from slave to IPBus core
+      -- Signals to/from DUT
+      busy_from_dut_n_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      busy_from_dut_p_i       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input from DUTs
+      clk_to_dut_n_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      clk_to_dut_p_io         : INOUT  std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! clocks trigger data when in EUDET mode
+      reset_or_clk_to_dut_n_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      reset_or_clk_to_dut_p_o : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Either reset line or trigger
+      trigger_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      trigger_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+      shutter_to_dut_n_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output. Output 0 (RJ45) has no shutter signal
+      shutter_to_dut_p_o      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);     --! Shutter output
+      veto_o                  : OUT    std_logic                                     --! goes high when one or more DUT are busy or vetoed by shutter
+   );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+-- hds interface_end
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+  signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0);  -- OR tree
+
+
+  signal s_clk_to_DUT , s_busy_from_dut , s_dut_veto , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_from_dut_eudet , s_busy_from_dut_eudet , s_dut_veto_eudet , s_reset_or_clk_to_dut_eudet , s_trigger_to_dut_eudet , s_shutter_to_dut_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_clk_to_DUT_AIDA , s_busy_from_dut_aida , s_dut_veto_aida , s_reset_or_clk_to_dut_aida , s_trigger_to_dut_aida , s_shutter_to_dut_aida : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');
+  signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');   	--! Mask for the DUTs used. 1 = active
+  signal s_dut_clk_is_output : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! Set low to enable transmission of clock from TLU to DUT
+
+  constant c_NUM_EUDET_FSM_BITS : positive := 4;
+  signal s_dut_fsm_status_eudet : std_logic_vector((c_NUM_EUDET_FSM_BITS*g_NUM_DUTS)-1 downto 0) ; --! Stores status from EUDET interface FSM. Can only support up to 32/4 = 8 DUT interfaces, not 12...
+
+  signal s_DUT_ignore_busy : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0');  --! set bit to 1 for BUSY to be ignored.
+  signal s_DUT_interface_mode : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1'); --! sets AIDA/EUDET/whatever interface.
+  signal s_DUT_aida_eudet_mode : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1');  --! set bit to 1 for AIDA mode, 0 for EUDET
+  signal s_dut_enable_veto_eudet : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '1'); --! set bit high to allow asynchronous veto using DUT_CLK when in EUDET mode
+
+  signal s_DUT_interface_mode_modifier : std_logic_vector((2*g_NUM_DUTS)-1 downto 0) := (others => '1');  
+  signal s_IgnoreShutterVeto : std_logic := '0';  -- --! When high the shutter won't veto triggers when low.
+
+  
+  -- Signal for IPBus
+  constant c_N_CTRL : positive := 8;
+  constant c_N_STAT : positive := 8;
+  signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+                                                               
+BEGIN
+
+  
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  s_DUT_mask                    <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+  s_DUT_ignore_busy             <= s_sync_control_from_ipbus(1)(g_NUM_DUTS-1 downto 0);
+  s_IgnoreShutterVeto           <= s_sync_control_from_ipbus(2)(0);
+  s_DUT_interface_mode          <= s_sync_control_from_ipbus(3)((2*g_NUM_DUTS)-1 downto 0);
+  s_DUT_interface_mode_modifier <= s_sync_control_from_ipbus(4)((2*g_NUM_DUTS)-1 downto 0);
+  
+    -- Map the status registers
+  s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+  s_status_to_ipbus(1) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_ignore_busy;
+  s_status_to_ipbus(2) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-1)) & s_IgnoreShutterVeto;
+  s_status_to_ipbus(3) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode;
+  s_status_to_ipbus(4) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-(2*g_NUM_DUTS))) & s_DUT_interface_mode_modifier;
+  s_status_to_ipbus(5) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-( c_NUM_EUDET_FSM_BITS*g_NUM_DUTS))) & s_dut_fsm_status_eudet ;
+  
+  
+  ------------------------------------------------------------------------------
+  -- Instantiate BUFIODS  
+  ------------------------------------------------------------------------------
+  
+  -- Loop through *all* DUTs ( including RJ45 )
+  dut_clk_busy_trig_rst_io: for dut in 0 to g_NUM_DUTS-1 generate
+
+
+    clk_IOBUFDS_inst : IOBUFDS
+      generic map (
+        IOSTANDARD => "BLVDS_25")
+      port map (
+        O => s_clk_from_dut_eudet(dut), --! Clock *from* DUT
+        IO => clk_to_dut_p_io(dut),  --! Diff_p dut clock I/O (connect directly to top-level port)
+        IOB => clk_to_dut_n_io(dut), --! Diff_n dut clock I/O (connect directly to top-level port)
+        I => s_clk_to_dut_aida(dut), --! Clock generated by TLU to DUT
+        T => s_dut_clk_is_output(dut) --! Set *low* to enable transmission of clock from TLU to DUT
+        );
+    
+    busy_IBUFDS_inst : IBUFDS
+      generic map (
+        DIFF_TERM => TRUE, -- Differential Termination 
+        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O => s_busy_from_dut(dut),  -- Buffer output
+        I => busy_from_dut_p_i(dut),  -- Diff_p buffer input (connect directly to top-level port)
+        IB => busy_from_dut_n_i(dut) -- Diff_n buffer input (connect directly to top-level port)
+      );
+		
+   
+    trig_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  trigger_to_dut_p_o(dut),     						-- Diff_p output (connect directly to top-level port)
+        OB => trigger_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_trigger_to_dut(dut)     -- Buffer input 
+      );
+     
+    clk_rst_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  reset_or_clk_to_dut_p_o(dut),    							-- Diff_p output (connect directly to top-level port)
+        OB => reset_or_clk_to_dut_n_o(dut),   							-- Diff_n output (connect directly to top-level port)
+        I =>  s_reset_or_clk_to_dut(dut) 	--s_reset_or_clk_to_dut(dut) and s_DUT_mask(dut)     -- Buffer input 
+      );
+		 
+  end generate dut_clk_busy_trig_rst_io;
+  
+  -- Loop through DUTs except RJ45  ( which (output 0) doesn't have a shutter
+  -- signal. )
+  dut_shutter_io: for dut in 1 to g_NUM_DUTS-1 generate
+
+    shutter_OBUFDS_inst : OBUFDS
+      generic map (
+        IOSTANDARD => "LVDS_25")
+      port map (
+        O =>  shutter_to_dut_p_o(dut), -- Diff_p output (connect directly to top-level port)
+        OB => shutter_to_dut_n_o(dut), -- Diff_n output (connect directly to top-level port)
+        I =>  s_shutter_to_dut(dut) 	
+        );
+  end generate dut_shutter_io;
+
+
+  ------------------------------------------------------------------------------
+  -- Instantiate interfaces to DUTs  
+  ------------------------------------------------------------------------------
+  dut_interfaces: for dut in 0 to g_NUM_DUTS-1 generate
+
+    --! AIDA style interface
+    aida_dut_interface: ENTITY work.DUTInterface_AIDA
+      generic map (
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+      PORT map ( 
+        clk_4x_logic_i          => clk_4x_logic_i ,
+        strobe_4x_logic_i       => strobe_4x_logic_i ,
+        trigger_counter_i       => trigger_counter_i , 
+        trigger_i               => trigger_i , 
+        reset_or_clk_to_dut_i   => reset_or_clk_to_dut_i,
+        shutter_to_dut_i        => shutter_to_dut_i ,
+        ignore_shutter_veto_i   => s_IgnoreShutterVeto ,
+        ignore_dut_busy_i       => s_DUT_ignore_busy(dut),
+        dut_mask_i              => s_DUT_mask(dut),
+        busy_o                  => s_dut_veto_aida(dut),
+      
+        -- Signals to/from DUT
+        dut_busy_i              => s_busy_from_dut(dut),
+        dut_clk_o               => s_clk_to_dut_aida(dut),
+        dut_reset_or_clk_o      => s_reset_or_clk_to_dut_aida(dut), 
+        dut_shutter_o           => s_shutter_to_dut_aida(dut),
+        dut_trigger_o           => s_trigger_to_dut_aida(dut)
+
+        );
+
+    --! EUDET style interface
+    eudet_dut_interface: entity work.DUTInterface_EUDET
+      GENERIC map ( 
+        g_TRIGGER_DATA_WIDTH => g_IPBUS_WIDTH
+        )
+      port map (
+        rst_i                 => ipbus_reset_i, 
+        busy_o                => s_dut_veto_eudet(dut),
+        fsm_state_value_o     => s_dut_fsm_status_eudet( (c_NUM_EUDET_FSM_BITS*(dut+1)-1) downto c_NUM_EUDET_FSM_BITS*(dut) ),
+        trigger_i             => trigger_i , 
+        trigger_counter_i     => trigger_counter_i , 
+        system_clk_i          => clk_4x_logic_i ,
+        reset_or_clk_to_dut_i => reset_or_clk_to_dut_i,
+        shutter_to_dut_i      => shutter_to_dut_i ,
+        ignore_shutter_veto_i => s_IgnoreShutterVeto ,
+        enable_dut_veto_i     => s_dut_enable_veto_eudet(dut),
+        -- Connections to DUT:
+        dut_clk_i             => s_clk_from_dut_eudet(dut),
+        dut_busy_i            => s_busy_from_dut(dut),
+        dut_shutter_o         => s_shutter_to_dut_eudet(dut),
+        dut_trigger_o         => s_trigger_to_dut_eudet(dut)
+        );
+
+    s_DUT_aida_eudet_mode(dut) <= s_DUT_interface_mode(2*dut);
+    s_dut_enable_veto_eudet(dut) <= s_DUT_interface_mode_modifier(2*dut);
+    
+    -- Produce "OR" of veto/busy signals from DUTs
+    s_intermediate_busy_or(dut+1) <= s_intermediate_busy_or(dut) or s_dut_veto(dut);
+    
+  end generate dut_interfaces;
+
+  s_dut_clk_is_output <= not s_DUT_aida_eudet_mode; -- at the moment can hardwire clk_is_output to mode_is_aida
+                                               
+  s_intermediate_busy_or(0) <= '0';
+  veto_o <=  s_intermediate_busy_or(g_NUM_DUTS);
+
+  -- purpose: Multiplexes signals between EUDET and AIDA interfaces
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i 
+  -- outputs: s_trigger_to_dut , s_reset_or_clk_to_dut , s_shutter_to_dut , s_dut_veto
+  p_signal_mux: process (clk_4x_logic_i ) is
+  begin  -- process p_signal_mux
+    if rising_edge(clk_4x_logic_i) then
+      s_trigger_to_dut <= ( s_trigger_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_trigger_to_dut_aida and  s_DUT_aida_eudet_mode) ;
+      s_dut_veto <= ( s_dut_veto_eudet and (not s_DUT_aida_eudet_mode)) or ( s_dut_veto_aida and  s_DUT_aida_eudet_mode) ;
+      s_shutter_to_dut <= ( s_shutter_to_dut_eudet and (not s_DUT_aida_eudet_mode)) or ( s_shutter_to_dut_aida and  s_DUT_aida_eudet_mode) ; 
+      s_reset_or_clk_to_dut <= ( s_reset_or_clk_to_dut_aida and  s_DUT_aida_eudet_mode) ; --! reset_or_clk line stays low if in EUDET mode
+      
+    end if;
+  end process p_signal_mux;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTs_outputs.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTs_outputs.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5d8974e8731c524196abf56adb50953498cc2ef2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/dut/DUTs_outputs.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 15.02.2017 13:17:26
+-- Design Name: 
+-- Module Name: DUTs_outputs - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity DUTs_outputs is
+    Port ( clk_in : in STD_LOGIC;
+           d_clk_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_trg_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_busy_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_cont_o : out STD_LOGIC_VECTOR (3 downto 0);
+           d_spare_o : out STD_LOGIC_VECTOR (3 downto 0));
+end DUTs_outputs;
+
+architecture Behavioral of DUTs_outputs is
+signal toggleme : std_logic := '0'; 
+begin
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+        
+        if rising_edge(clk_in) then   -- rising clock edge
+            toggleme <= not toggleme;
+            d_clk_o(1) <= toggleme;
+            d_clk_o(2) <= toggleme;
+            d_clk_o(3) <= toggleme;
+            d_trg_o <=  (toggleme & toggleme & toggleme & toggleme);
+            d_busy_o <= (toggleme & toggleme & toggleme & toggleme);
+            d_cont_o <= (toggleme & toggleme & toggleme & toggleme);
+            d_spare_o <=(toggleme & toggleme & toggleme & toggleme);
+        end if;
+        d_clk_o(0) <= clk_in;
+    end process gen_clk;
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/enclustra_ax3_pm3_infra.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/enclustra_ax3_pm3_infra.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df07ba1ef1daed5d435e98f6807ffed65d8c2c7c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/enclustra_ax3_pm3_infra.vhd
@@ -0,0 +1,131 @@
+-- enclustra_ax3_pm3_infra
+--
+-- All board-specific stuff goes here
+--
+-- Dave Newbold, June 2013---
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.ipbus.all;
+
+entity enclustra_ax3_pm3_infra is
+	port(
+		sysclk: in std_logic; -- ??? board crystal clock
+		clk_ipb_o: out std_logic; -- IPbus clock
+		rst_ipb_o: out std_logic;
+		rst_125_o: out std_logic;
+		clk_200_o: out std_logic;
+		--clk_aux_o: out std_logic; -- 40MHz generated clock
+		--rst_aux_o: out std_logic;
+		nuke: in std_logic; -- The signal of doom
+		soft_rst: in std_logic; -- The signal of lesser doom
+		leds: out std_logic_vector(1 downto 0); -- status LEDs
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		mac_addr: in std_logic_vector(47 downto 0); -- MAC address
+		ip_addr: in std_logic_vector(31 downto 0); -- IP address
+		ipb_in: in ipb_rbus; -- ipbus
+		ipb_out: out ipb_wbus
+	);
+
+end enclustra_ax3_pm3_infra;
+
+architecture rtl of enclustra_ax3_pm3_infra is
+
+	signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
+	signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+	signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+	signal led_p: std_logic_vector(0 downto 0);
+	
+begin
+
+--	DCM clock generation for internal bus, ethernet
+
+	clocks: entity work.clocks_7s_extphy_se
+		port map(
+			sysclk => sysclk,
+			clko_125 => clk125,
+			clko_125_90 => clk125_90,
+			clko_200 => clk200,
+			clko_ipb => clk_ipb_i,
+			locked => locked,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			rsto_125 => rst125,
+			rsto_ipb => rst_ipb,
+			rsto_ipb_ctrl => rst_ipb_ctrl,
+			onehz => onehz
+		);
+
+	clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
+	clk_ipb_o <= clk_ipb_i;
+	rst_ipb_o <= rst_ipb;
+	rst_125_o <= rst125;
+	clk_200_o <= clk200;
+	
+	stretch: entity work.led_stretcher
+		generic map(
+			WIDTH => 1
+		)
+		port map(
+			clk => clk125,
+			d(0) => pkt,
+			q => led_p
+		);
+	leds <= (led_p(0), locked and onehz);
+	
+-- Ethernet MAC core and PHY interface
+	
+	eth: entity work.eth_7s_rgmii
+		port map(
+			clk125 => clk125,
+			clk125_90 => clk125_90,
+			clk200 => clk200,
+			rst => rst125,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			tx_data => mac_tx_data,
+			tx_valid => mac_tx_valid,
+			tx_last => mac_tx_last,
+			tx_error => mac_tx_error,
+			tx_ready => mac_tx_ready,
+			rx_data => mac_rx_data,
+			rx_valid => mac_rx_valid,
+			rx_last => mac_rx_last,
+			rx_error => mac_rx_error
+		);
+	
+-- ipbus control logic
+
+	ipbus: entity work.ipbus_ctrl
+		port map(
+			mac_clk => clk125,
+			rst_macclk => rst125,
+			ipb_clk => clk_ipb,
+			rst_ipb => rst_ipb_ctrl,
+			mac_rx_data => mac_rx_data,
+			mac_rx_valid => mac_rx_valid,
+			mac_rx_last => mac_rx_last,
+			mac_rx_error => mac_rx_error,
+			mac_tx_data => mac_tx_data,
+			mac_tx_valid => mac_tx_valid,
+			mac_tx_last => mac_tx_last,
+			mac_tx_error => mac_tx_error,
+			mac_tx_ready => mac_tx_ready,
+			ipb_out => ipb_out,
+			ipb_in => ipb_in,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			pkt => pkt
+		);
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_gmii.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_gmii.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4db967adaed3b9e9240b70ffe1bb8661c5668bc6
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_gmii.vhd
@@ -0,0 +1,183 @@
+-- Contains the instantiation of the Xilinx MAC IP plus the GMII PHY interface
+--
+-- Do not change signal names in here without corresponding alteration to the timing contraints file
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+use work.emac_hostbus_decl.all;
+
+entity eth_7s_gmii is
+	port(
+		clk125: in std_logic;
+		clk200: in std_logic;
+		rst: in std_logic;
+		gmii_gtx_clk: out std_logic;
+		gmii_txd: out std_logic_vector(7 downto 0);
+		gmii_tx_en: out std_logic;
+		gmii_tx_er: out std_logic;
+		gmii_rx_clk: in std_logic;
+		gmii_rxd: in std_logic_vector(7 downto 0);
+		gmii_rx_dv: in std_logic;
+		gmii_rx_er: in std_logic;
+		tx_data: in std_logic_vector(7 downto 0);
+		tx_valid: in std_logic;
+		tx_last: in std_logic;
+		tx_error: in std_logic;
+		tx_ready: out std_logic;
+		rx_data: out std_logic_vector(7 downto 0);
+		rx_valid: out std_logic;
+		rx_last: out std_logic;
+		rx_error: out std_logic;
+		hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
+		hostbus_out: out emac_hostbus_out
+	);
+
+end eth_7s_gmii;
+
+architecture rtl of eth_7s_gmii is
+
+	COMPONENT temac_gbe_v9_0_rgmii
+		PORT (
+			gtx_clk : IN STD_LOGIC;
+			glbl_rstn : IN STD_LOGIC;
+			rx_axi_rstn : IN STD_LOGIC;
+			tx_axi_rstn : IN STD_LOGIC;
+			rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
+			rx_statistics_valid : OUT STD_LOGIC;
+			rx_mac_aclk : OUT STD_LOGIC;
+			rx_reset : OUT STD_LOGIC;
+			rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			rx_axis_mac_tvalid : OUT STD_LOGIC;
+			rx_axis_mac_tlast : OUT STD_LOGIC;
+			rx_axis_mac_tuser : OUT STD_LOGIC;
+			tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			tx_statistics_valid : OUT STD_LOGIC;
+			tx_mac_aclk : OUT STD_LOGIC;
+			tx_reset : OUT STD_LOGIC;
+			tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_axis_mac_tvalid : IN STD_LOGIC;
+			tx_axis_mac_tlast : IN STD_LOGIC;
+			tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+			tx_axis_mac_tready : OUT STD_LOGIC;
+			pause_req : IN STD_LOGIC;
+			pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+			speedis100 : OUT STD_LOGIC;
+			speedis10100 : OUT STD_LOGIC;
+			gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			gmii_tx_en : OUT STD_LOGIC;
+			gmii_tx_er : OUT STD_LOGIC;
+			gmii_tx_clk : OUT STD_LOGIC;
+			gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			gmii_rx_dv : IN STD_LOGIC;
+			gmii_rx_er : IN STD_LOGIC;
+			gmii_rx_clk : IN STD_LOGIC;
+			rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
+			tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT mac_fifo_axi4
+	  PORT (
+		 m_aclk : IN STD_LOGIC;
+		 s_aclk : IN STD_LOGIC;
+		 s_aresetn : IN STD_LOGIC;
+		 s_axis_tvalid : IN STD_LOGIC;
+		 s_axis_tready : OUT STD_LOGIC;
+		 s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 s_axis_tlast : IN STD_LOGIC;
+		 s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		 m_axis_tvalid : OUT STD_LOGIC;
+		 m_axis_tready : IN STD_LOGIC;
+		 m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 m_axis_tlast : OUT STD_LOGIC;
+		 m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+	  );
+	END COMPONENT;
+	
+	signal rx_data_e: std_logic_vector(7 downto 0);
+	signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
+	signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
+
+begin
+
+	idelayctrl0: idelayctrl port map(
+		refclk => clk200,
+		rst => rst
+	);
+
+	rstn <= not rst;
+
+	emac0: temac_gbe_v9_0_rgmii
+		port map(
+			gtx_clk => clk125,
+			glbl_rstn => rstn,
+			rx_axi_rstn => '1',
+			tx_axi_rstn => '1',
+			rx_statistics_vector => open,
+			rx_statistics_valid => open,		
+			rx_mac_aclk => rx_clk_e,
+			rx_reset => rx_rst_e,
+			rx_axis_mac_tdata => rx_data_e,
+			rx_axis_mac_tvalid => rx_valid_e,
+			rx_axis_mac_tlast => rx_last_e,
+			rx_axis_mac_tuser => rx_user_e,
+			tx_ifg_delay => X"00",
+			tx_statistics_vector => open,
+			tx_statistics_valid => open,	
+			tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
+			tx_reset => open,
+			tx_axis_mac_tdata => tx_data,
+			tx_axis_mac_tvalid => tx_valid,
+			tx_axis_mac_tlast => tx_last,
+			tx_axis_mac_tuser(0) => tx_error,
+			tx_axis_mac_tready => tx_ready,
+			pause_req => '0',
+			pause_val => X"0000",
+			speedis100 => open,
+			speedis10100 => open,
+			gmii_txd => gmii_txd,
+			gmii_tx_en => gmii_tx_en,
+			gmii_tx_er => gmii_tx_er,
+			gmii_tx_clk => gmii_gtx_clk,
+			gmii_rxd => gmii_rxd,
+			gmii_rx_dv => gmii_rx_dv,
+			gmii_rx_er => gmii_rx_er,
+			gmii_rx_clk => gmii_rx_clk,
+			rx_configuration_vector => X"0000_0000_0000_0000_0812",
+			tx_configuration_vector => X"0000_0000_0000_0000_0012"
+		);
+	
+	rx_user_ef(0) <= rx_user_e;
+	rx_error <= rx_user_f(0);
+	rx_rst_en <= not rx_rst_e;
+	
+	fifo: mac_fifo_axi4
+		port map(
+			m_aclk => clk125,
+			s_aclk => rx_clk_e,
+			s_aresetn => rx_rst_en,
+			s_axis_tvalid => rx_valid_e,
+			s_axis_tready => open,
+			s_axis_tdata => rx_data_e,
+			s_axis_tlast => rx_last_e,
+			s_axis_tuser => rx_user_ef,
+			m_axis_tvalid => rx_valid,
+			m_axis_tready => '1',
+			m_axis_tdata => rx_data,
+			m_axis_tlast => rx_last,
+			m_axis_tuser => rx_user_f
+		); -- Clock domain crossing FIFO
+
+	hostbus_out.hostrddata <= (others => '0');
+	hostbus_out.hostmiimrdy <= '0';
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_rgmii.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_rgmii.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3e2e16709360b5ebcd8a9337e77cc9e881c516ba
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/eth_7s_rgmii.vhd
@@ -0,0 +1,184 @@
+-- Contains the instantiation of the Xilinx MAC & PHY interface for RGMII
+--
+-- Do not change signal names in here without corresponding alteration to the timing contraints file
+--
+-- Dave Newbold, October 2016
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+use work.emac_hostbus_decl.all;
+
+entity eth_7s_rgmii is
+	port(
+		clk125: in std_logic;
+		clk125_90: in std_logic;
+		clk200: in std_logic;
+		rst: in std_logic;
+		rgmii_txd: out std_logic_vector(3 downto 0);
+		rgmii_tx_ctl: out std_logic;
+		rgmii_txc: out std_logic;
+		rgmii_rxd: in std_logic_vector(3 downto 0);
+		rgmii_rx_ctl: in std_logic;
+		rgmii_rxc: in std_logic;
+		tx_data: in std_logic_vector(7 downto 0);
+		tx_valid: in std_logic;
+		tx_last: in std_logic;
+		tx_error: in std_logic;
+		tx_ready: out std_logic;
+		rx_data: out std_logic_vector(7 downto 0);
+		rx_valid: out std_logic;
+		rx_last: out std_logic;
+		rx_error: out std_logic;
+		hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
+		hostbus_out: out emac_hostbus_out;
+		status: out std_logic_vector(3 downto 0)
+	);
+
+end eth_7s_rgmii;
+
+architecture rtl of eth_7s_rgmii is
+
+	COMPONENT temac_gbe_v9_rgmii
+		PORT (
+			gtx_clk : IN STD_LOGIC;
+			gtx_clk90 : IN STD_LOGIC;
+			glbl_rstn : IN STD_LOGIC;
+			rx_axi_rstn : IN STD_LOGIC;
+			tx_axi_rstn : IN STD_LOGIC;
+			rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
+			rx_statistics_valid : OUT STD_LOGIC;
+			rx_mac_aclk : OUT STD_LOGIC;
+			rx_reset : OUT STD_LOGIC;
+			rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+			rx_axis_mac_tvalid : OUT STD_LOGIC;
+			rx_axis_mac_tlast : OUT STD_LOGIC;
+			rx_axis_mac_tuser : OUT STD_LOGIC;
+			tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+			tx_statistics_valid : OUT STD_LOGIC;
+			tx_mac_aclk : OUT STD_LOGIC;
+			tx_reset : OUT STD_LOGIC;
+			tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+			tx_axis_mac_tvalid : IN STD_LOGIC;
+			tx_axis_mac_tlast : IN STD_LOGIC;
+			tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+			tx_axis_mac_tready : OUT STD_LOGIC;
+			pause_req : IN STD_LOGIC;
+			pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+			speedis100 : OUT STD_LOGIC;
+			speedis10100 : OUT STD_LOGIC;
+			rgmii_txd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_tx_ctl : OUT STD_LOGIC;
+			rgmii_txc : OUT STD_LOGIC;
+			rgmii_rxd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+			rgmii_rx_ctl : IN STD_LOGIC;
+			rgmii_rxc : IN STD_LOGIC;
+			inband_link_status : OUT STD_LOGIC;
+			inband_clock_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+			inband_duplex_status : OUT STD_LOGIC;
+			rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
+			tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT mac_fifo_axi4
+	  PORT (
+		 m_aclk : IN STD_LOGIC;
+		 s_aclk : IN STD_LOGIC;
+		 s_aresetn : IN STD_LOGIC;
+		 s_axis_tvalid : IN STD_LOGIC;
+		 s_axis_tready : OUT STD_LOGIC;
+		 s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 s_axis_tlast : IN STD_LOGIC;
+		 s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		 m_axis_tvalid : OUT STD_LOGIC;
+		 m_axis_tready : IN STD_LOGIC;
+		 m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 m_axis_tlast : OUT STD_LOGIC;
+		 m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+	  );
+	END COMPONENT;
+	
+	signal rx_data_e: std_logic_vector(7 downto 0);
+	signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
+	signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
+	
+begin
+
+	idelayctrl0: idelayctrl port map(
+		refclk => clk200,
+		rst => rst
+	);
+	
+	rstn <= not rst;
+
+	emac0: temac_gbe_v9_rgmii
+		port map(
+			gtx_clk => clk125,
+			gtx_clk90 => clk125_90,
+			glbl_rstn => rstn,
+			rx_axi_rstn => '1',
+			tx_axi_rstn => '1',
+			rx_statistics_vector => open,
+			rx_statistics_valid => open,		
+			rx_mac_aclk => rx_clk_e,
+			rx_reset => rx_rst_e,
+			rx_axis_mac_tdata => rx_data_e,
+			rx_axis_mac_tvalid => rx_valid_e,
+			rx_axis_mac_tlast => rx_last_e,
+			rx_axis_mac_tuser => rx_user_e,
+			tx_ifg_delay => X"00",
+			tx_statistics_vector => open,
+			tx_statistics_valid => open,	
+			tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
+			tx_reset => open,
+			tx_axis_mac_tdata => tx_data,
+			tx_axis_mac_tvalid => tx_valid,
+			tx_axis_mac_tlast => tx_last,
+			tx_axis_mac_tuser(0) => tx_error,
+			tx_axis_mac_tready => tx_ready,
+			pause_req => '0',
+			pause_val => X"0000",
+			speedis100 => open,
+			speedis10100 => open,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			inband_link_status => status(0),
+			inband_clock_speed => status(3 downto 2),
+			inband_duplex_status => status(1),
+			rx_configuration_vector => X"0000_0000_0000_0000_0812",
+			tx_configuration_vector => X"0000_0000_0000_0000_0012"
+		);
+	
+	rx_user_ef(0) <= rx_user_e;
+	rx_error <= rx_user_f(0);
+	rx_rst_en <= not rx_rst_e;
+	
+	fifo: mac_fifo_axi4
+		port map(
+			m_aclk => clk125,
+			s_aclk => rx_clk_e,
+			s_aresetn => rx_rst_en,
+			s_axis_tvalid => rx_valid_e,
+			s_axis_tready => open,
+			s_axis_tdata => rx_data_e,
+			s_axis_tlast => rx_last_e,
+			s_axis_tuser => rx_user_ef,
+			m_axis_tvalid => rx_valid,
+			m_axis_tready => '1',
+			m_axis_tdata => rx_data,
+			m_axis_tlast => rx_last,
+			m_axis_tuser => rx_user_f
+		); -- Clock domain crossing FIFO
+
+	hostbus_out.hostrddata <= (others => '0');
+	hostbus_out.hostmiimrdy <= '0';
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/eventBuffer_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/eventBuffer_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b60fe5149c1e1ba1d78e778aff9edfc72d920eae
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/eventBuffer_rtl.vhd
@@ -0,0 +1,167 @@
+--=============================================================================
+--! @file eventBuffer_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+--! @brief Stores input words (64bits) for readout over IPBus. 
+--! Uses a FIFO ( 64bits at input, 32 bits at output )
+--
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:24:50 11/13/12
+--
+--! @version v0.1
+--
+--! @details
+--! \n\nIPBus Address map:
+--! \li 0x0000 - FIFO data
+--! \li 0x0001 - FIFO fill level
+--! \li 0x0010 - FIFO status/control: (Writing Bit-0 resets pointers, Reading bit-1 returns "prog_full" flag)
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--------------------------------------------------------------------------------
+
+ENTITY eventBuffer IS
+    GENERIC( 
+        g_EVENT_DATA_WIDTH    : positive := 64;
+        g_IPBUS_WIDTH         : positive := 32;
+        g_READ_COUNTER_WIDTH  : positive := 14
+    );
+    PORT( 
+        clk_4x_logic_i    : IN     std_logic;
+        data_strobe_i     : IN     std_logic;                                         -- Indicates data to transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic;
+        ipbus_i           : IN     ipb_wbus;
+        ipbus_reset_i     : IN     std_logic;
+        strobe_4x_logic_i : IN     std_logic;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o			: OUT 	std_logic;														--! rst signal to first level fifos
+        buffer_full_o     : OUT    std_logic;                                         --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus;
+        logic_reset_i     : IN     std_logic                                          -- reset buffers when high. Synch withclk_4x_logic
+    );
+
+-- Declarations
+
+END ENTITY eventBuffer ;
+
+--
+ARCHITECTURE rtl OF eventBuffer IS
+    signal s_rd_data_count    : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
+    signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0');  -- read-counter - 2*write_count
+    signal s_write_strobe    : std_logic := '0';
+    signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0';                             -- ! Take high to reset FIFO pointers.
+    signal s_fifo_prog_full : std_logic := '0';                       -- ! Controlled by programmable-full flag of FIFO core
+    signal s_fifo_rd_en : std_logic := '0';                           -- ! Take high to clock data out of FIFO
+    signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);  -- ! Output from FIFO ( fall-through mode)
+    signal s_fifo_valid : std_logic := '1';                           -- ! High when data in FIFO
+    signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
+    signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0');  -- data registered onto IPBus clock
+    signal s_ack : std_logic := '0';      -- -- IPBus ACK signal
+    COMPONENT tlu_event_fifo
+    PORT (
+        rst : IN STD_LOGIC;
+        wr_clk : IN STD_LOGIC;
+        rd_clk : IN STD_LOGIC;
+        din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+        wr_en : IN STD_LOGIC;
+        rd_en : IN STD_LOGIC;
+        dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+        full : OUT STD_LOGIC;
+        almost_full : OUT STD_LOGIC;
+        empty : OUT STD_LOGIC;
+        almost_empty : OUT STD_LOGIC;
+        rd_data_count : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
+        prog_full : OUT STD_LOGIC
+    );
+    END COMPONENT;
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus IO
+  -----------------------------------------------------------------------------
+
+  --! Generate IPBus ACK 
+    ipbus_ack: process(ipbus_clk_i)
+    begin
+    if rising_edge(ipbus_clk_i) then
+        s_ack <= ipbus_i.ipb_strobe and not s_ack;
+    end if;
+    end process ipbus_ack;
+    ipbus_o.ipb_ack <= s_ack;
+    
+    --! Generate FIFO read enable
+    --! take high for one cycle ( when ipb_strobe goes high but before ACK goes
+    --high to follow it
+    s_fifo_rd_en  <= '1' when
+        ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" and s_ack = '0'
+        else '0';
+    ipbus_o.ipb_err <= '0';
+
+    --! Multiplex output data.
+    with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
+        s_fifo_dout          when "00",
+        s_fifo_fill_level    when "01",
+        s_fifo_status_ipb	 when "10",
+        (others => '1')      when others;
+
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipbus_write
+    if rising_edge(ipbus_clk_i) then
+        s_rst_fifo_ipb <= '0';
+        if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
+            s_rst_fifo_ipb <= '1';
+        end if;
+        -- Register data onto IPBus clock domain to ease timing closure.
+        s_fifo_status_ipb <=  X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+        s_fifo_fill_level <= X"0000" & "00" & s_rd_data_count; 
+    end if;
+    end process ipbus_write;
+  
+    rst_fifo_o <= s_rst_fifo_ipb;
+    s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
+  
+  -----------------------------------------------------------------------------
+  -- FIFO and fill-level calculation
+  -----------------------------------------------------------------------------
+  
+  -- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
+  --event_fifo : entity work.tlu_event_fifo
+    event_fifo : tlu_event_fifo
+    PORT MAP (
+        rst => s_rst_fifo,
+        wr_clk => clk_4x_logic_i,
+        rd_clk => ipbus_clk_i,
+        din => event_data_i,
+        wr_en => data_strobe_i,
+        rd_en => s_fifo_rd_en,
+        dout => s_fifo_dout,
+        full => s_fifo_full,
+        almost_full => s_fifo_almost_full,
+        empty => s_fifo_empty,
+        almost_empty => s_fifo_almost_empty,
+        rd_data_count => s_rd_data_count,
+        prog_full => s_fifo_prog_full
+    );
+    buffer_full_o <= s_fifo_prog_full;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/eventFormatter_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/eventFormatter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c33279ab6feae6a81fe6bd07ef068ec4c9dfc23e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/eventFormatter_rtl.vhd
@@ -0,0 +1,385 @@
+--=============================================================================
+--! @file eventFormatter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.fmcTLU.all;
+USE work.ipbus.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Takes the data delivered on each trigger and turns it into 64-bit
+--!        words to push into event buffer
+--! 
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 15:10:35 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \n\n IPBus address:
+--! \n (Decodes 3 bits)
+--! \li 000 - read/write enable data recording.
+--! \li 001 - write = reset timestamp,
+--! \li 010 - read = current timestamp (low  32-bits)
+--! \li 011 - read = current timestamp (high 16-bits)
+--!
+--! -----------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Modified by: Alvaro Dosil , alvaro.dosil@usc.es \n
+--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
+--!               doesn't like having an if that can take an array out of bounds.
+--! 26/Sept/14 DGC Hacked out shutter etc. Can't figure out bug.
+--!-----------------------------------------------------------------------------
+--! @todo Add more input data: \n
+--! a) shutter signals. One per DUT. ?? \n
+--! b) input levels ( for recording edge data ). Record rising and falling edges\n
+--! c) veto levels. One per DUT. Record rising and falling edges.\n
+--! \n
+--! Add backpressure output if short FIFOs fill up? But many inputs won't
+--! respond - e.g. scintillator inputs. This data will be lost....
+--! some ports are redundant - e.g. trigger counter, others confusingly
+--! labelled. Sort this out..
+--------------------------------------------------------------------------------
+
+
+ENTITY eventFormatter IS
+   GENERIC( 
+      g_EVENT_DATA_WIDTH   : positive := 64;
+      g_IPBUS_WIDTH        : positive := 32;
+      g_COUNTER_TRIG_WIDTH : positive := 32;
+      g_COUNTER_WIDTH      : positive := 12;
+      g_EVTTYPE_WIDTH      : positive := 4; --! Width of the event type word
+      --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+      g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+      g_NUM_TRIG_INPUTS    : positive := 6      --! Number of trigger inputs
+   );
+   PORT( 
+      clk_4x_logic_i         : IN     std_logic;                                           --! Rising edge active
+      ipbus_clk_i            : IN     std_logic;
+      logic_strobe_i         : IN     std_logic;                                           --! Pulses high once every 4 cycles of clk_4x_logic
+      logic_reset_i          : IN     std_logic;                                           --! goes high to reset counters. Synchronous with clk_4x_logic
+      rst_fifo_i             : IN     std_logic;                                           --! Goes high to reset FIFOs
+      buffer_full_i          : IN     std_logic;                                           --! Goes high when output fifo full
+      trigger_i              : IN     std_logic;                                           --! goes high to load trigger data. One cycle of clk_4x_logic
+      trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times ( w.r.t. logic_strobe)
+      trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);     --! high for each input that "fired"
+      trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);  --! Trigger count
+      shutter_i              : IN     std_logic;
+      shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      spill_i                : IN     std_logic;
+      spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+      edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when rising edge
+      edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);     --! High when falling edge
+      edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);   --! Array of edge times ( w.r.t. logic_strobe)
+      ipbus_i                : IN     ipb_wbus;
+      ipbus_o                : OUT    ipb_rbus;
+      data_strobe_o          : OUT    std_logic;                                           --! goes high when data ready to load into event buffer
+      event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+      reset_timestamp_i      : IN     std_logic;                                           --! Taking high causes timestamp to be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+      reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+   );
+
+-- Declarations
+
+END eventFormatter ;
+
+--
+ARCHITECTURE rtl OF eventFormatter IS
+
+  
+  constant c_NUM_INPUT_TYPES     : positive := 3+g_NUM_EDGE_INPUTS;               -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
+  
+--  type t_fifo_io is array(natural range <>) of std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0);
+-- type t_evttype is array(natural range <>) of std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0);
+--  type t_var is array(natural range <>) of std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
+  -- Input types:
+  -- 0 - Trigger
+  -- 1 - Shutter
+  -- 2 - Edge signal
+  -- 3 - Spill
+  
+  --! delayed strobes
+  signal s_event_strobe , s_event_strobe_d1 ,s_event_strobe_d2 ,s_event_strobe_d3 , s_event_strobe_d3_opt : std_logic := '0';
+  signal shutter_i_d1, shutter_i_d2, edge_i_d1, edge_i_d2, spill_i_d1, spill_i_d2 : std_logic := '0';
+  
+--  signal s_evttype : t_evttype(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>(others=>'0'));   -- Event type
+  signal s_evttype : std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0) := ( others => '0');
+  -- 0000 trigger internal
+  -- 0001 trigger external
+  -- 0010 shutter falling
+  -- 0011 shutter rising
+  -- 0100 edge falling
+  -- 0101 edge rising
+  -- 0111 spill on
+  -- 0110 spill off
+  
+  signal s_var        : std_logic_vector(g_COUNTER_WIDTH-1 downto 0) := (others => '0');
+    
+  signal s_data_o        : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);         -- Multiplexed data from FIFOs
+  
+  constant c_COARSE_TIMESTAMP_WIDTH : positive := 48;  -- ! Number of bits in 40MHz timestamp
+  signal s_coarse_timestamp : std_logic_vector(c_COARSE_TIMESTAMP_WIDTH-1 downto 0) := (others => '0');  -- 40MHz timestamp.
+  signal s_coarse_timestamp_ipbus : ipb_reg_v(1 downto 0) := ( others => (others => '0')); --! 40MHz timestamp on IPB clock domain.
+
+--  signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- increment after each post-veto trigger.
+
+  signal s_word0 , s_word1, s_word2 			: std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_p1  : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0');  -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+  signal trigger_times_d1							: t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0')); 
+
+  signal s_reset_timestamp_4x, s_reset_timestamp_4x_ipbus , s_reset_timestamp_4x_external , s_reset_timestamp_4x_external_p1 , s_reset_timestamp_4x_external_p2 : std_logic := '0'; --! Single pulse on 4x domain
+  signal s_reset_timestamp_ipbus : std_logic := '0'; --! Single pulse on IPBus clock domain
+  
+  signal s_ipbus_ack      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+  signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
+  signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
+  signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
+  signal s_enable_spill   : std_logic := '1'; -- Enable spill record
+  signal s_enable_edges   : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
+
+  signal s_rst_fifo_d1 , s_rst_fifo_d2 , s_rst_fifo_clk4x  : std_logic := '0';
+  signal s_buffer_full_d1 , s_buffer_full_d2 , s_buffer_full_clk4x  : std_logic := '0';
+  signal s_trigger : std_logic := '0';  -- pulses on risng edge of triger in
+
+  signal s_captured_trigger_times :  t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);   --! Array of trigger times,captured when trigger
+  
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus write
+  -----------------------------------------------------------------------------
+  ipbus_write: process (ipbus_clk_i)
+  begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+
+      s_reset_timestamp_ipbus <= '0';
+      if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+         case ipbus_i.ipb_addr(2 downto 0) is
+           when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
+           when "001" => s_reset_timestamp_ipbus <= '1';
+           when others => null;
+         end case;
+          
+       end if;
+
+       s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+       
+    end if;
+  end process ipbus_write;
+
+  ipbus_o.ipb_ack <= s_ipbus_ack;
+  ipbus_o.ipb_err <= '0';
+  
+
+  -----------------------------------------------------------------------------
+  -- IPBUS read
+  -----------------------------------------------------------------------------
+  with ipbus_i.ipb_addr(2 downto 0) select
+    ipbus_o.ipb_rdata <=
+      s_enable_record_ipb                     when "000",
+      s_coarse_timestamp_ipbus(0)              when "010",  
+      s_coarse_timestamp_ipbus(1)             when "011",  
+      (others => '1')                         when others;
+
+  cmp_timestampDomainCross : entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => 2 )
+    port map (
+      clk_input_i  => clk_4x_logic_i,
+      data_i       => ( "0000000000000000" & s_coarse_timestamp(s_coarse_timestamp'left downto 32) , s_coarse_timestamp(31 downto 0) ) ,
+      data_o       => s_coarse_timestamp_ipbus, 
+      clk_output_i => ipbus_clk_i
+      );
+
+  -- Move reset timestamp pulse onto clk_4x_logic
+  cmp_resetTimestampDomainCross: entity work.pulseClockDomainCrossing
+    port map (
+      clk_input_i  => ipbus_clk_i,
+      pulse_i      => s_reset_timestamp_ipbus,
+      clk_output_i => clk_4x_logic_i, 
+      pulse_o      => s_reset_timestamp_4x_ipbus
+    );
+
+  -- Combine reset timestamp from IPBus and external source
+  -- purpose: combines resets from IPBus and external source onto clk_4x_logic_i
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: s_reset_timestamp_4x
+  p_combine_reset_timestamps: process (clk_4x_logic_i) is
+  begin  -- process p_combine_reset_timestamps
+    if rising_edge(clk_4x_logic_i) then
+      s_reset_timestamp_4x_external_p2 <= reset_timestamp_i;
+      s_reset_timestamp_4x_external_p1 <= s_reset_timestamp_4x_external_p2 ;
+      s_reset_timestamp_4x_external    <= s_reset_timestamp_4x_external_p1 ;
+      s_reset_timestamp_4x <= s_reset_timestamp_4x_external or s_reset_timestamp_4x_ipbus;
+    end if;
+  end process p_combine_reset_timestamps;
+  
+  reset_timestamp_o <= s_reset_timestamp_4x;
+  
+  -- Change control signals from IPBus clock domain on to clk_4x_logic
+  -- CHANGE ME - use synchronize registers instead.
+  p_signals_clk_domain: process (clk_4x_logic_i )
+  begin  -- process p_internal_triggers
+    if rising_edge(clk_4x_logic_i) then
+      s_enable_record  <= s_enable_record_ipb;
+		
+      s_enable_trigger <= s_enable_record(0);
+      s_enable_shutter <= s_enable_record(1);
+      s_enable_spill <= s_enable_record(2);
+      s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
+
+      -- move  "reset fifo" and "buffer full"  signals onto clock4x domain
+      s_rst_fifo_d1 <= rst_fifo_i;
+      s_rst_fifo_d2 <= s_rst_fifo_d1;
+      s_rst_fifo_clk4x <= s_rst_fifo_d2 ;
+      s_buffer_full_d1 <= buffer_full_i;
+      s_buffer_full_d2 <= s_buffer_full_d1;
+      s_buffer_full_clk4x <= s_buffer_full_d2;  
+      
+    end if;
+  end process p_signals_clk_domain;
+
+  cmp_triggerEdgeDetect: entity work.single_pulse
+    port map (
+      level => trigger_i,
+      clk => clk_4x_logic_i,
+      pulse => s_trigger
+      );
+  
+  -- purpose: generate delayed strobes and write enable flags to the FIFOs
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i , s_FIFO_rd
+  -- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
+  p_ff_rst: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then      
+      if s_rst_fifo_clk4x = '1' then
+        s_event_strobe_d1 <= '0';
+        s_event_strobe_d2 <= '0';
+        s_event_strobe_d3 <= '0';
+		
+      else
+        -- set s_event_strobe high if trigger_i is high and pipeline is empty
+        -- ( i.e. all event_strobe are zero)
+
+        s_event_strobe_d1 <= s_trigger and s_enable_trigger and not buffer_full_i and
+                             (not s_event_strobe_d1 ) and (not s_event_strobe_d2 ) and (not s_event_strobe_d3 );
+        s_event_strobe_d2 <= s_event_strobe_d1;
+        s_event_strobe_d3 <= s_event_strobe_d2;
+		
+      end if;
+    end if;
+  end process p_ff_rst;
+  
+  p_ff: process (clk_4x_logic_i)
+  begin  -- process p_generate_strobes
+    if rising_edge(clk_4x_logic_i) then
+
+		trigger_times_d1 <= trigger_times_i;
+
+        s_word0 <= s_word0_p1;
+		s_word0_d1 <= s_word0;
+		s_word1_d1 <= s_word1;
+		s_word1_d2 <= s_word1_d1;
+		s_word2_d1 <= s_word2;
+		s_word2_d2 <= s_word2_d1;
+		s_word2_d3 <= s_word2_d2;
+		
+	end if;
+  end process;
+	
+  -- If there are more than 4 trigger inputs we need to fill a second word.
+  -- .. do this by having an optional strobe.
+  -- If 4 or fewer trigger inputs, just leave s_event_strobe_d3_opt at zero..
+  gen_strobe_d3: if (g_NUM_TRIG_INPUTS > 4) generate
+    s_event_strobe_d3_opt <= s_event_strobe_d3;
+  end generate;
+
+-------------------------------------------------------------------------------
+-- Trigger event formater
+-------------------------------------------------------------------------------
+  s_evttype <= "0000" when unsigned(trigger_inputs_fired_i) = 0 else "0001";
+
+  --s_var <= trigger_inputs_fired_i & std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS));
+  s_var <= std_logic_vector(to_unsigned(0,s_var'length-g_NUM_TRIG_INPUTS)) & trigger_inputs_fired_i; -- Pad with zeroes on the left.
+
+  s_word0_p1 <= s_evttype & s_var & s_coarse_timestamp;
+  
+  s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
+             "000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
+             trigger_cnt_i;
+				 
+	
+  -- Different number of trigger inputs require packing into s_word2 in
+  -- different ways.
+  -- Do this in a generate since g_NUM_TRIG_INPUTS is static and
+  -- Questasim doesn't like refering to indices outside declared range.
+    gen_word2_init: if (g_NUM_TRIG_INPUTS <= 4) generate
+       s_word2 <= (others=>'0');
+    end generate;
+  --s_word2 <= (others=>'0'); -- Set all bits to zero
+  -- then override with the following assignments....
+    gen_word2: for v_trigInput in 4 to g_NUM_TRIG_INPUTS-1 generate
+        s_word2( (((11-v_trigInput)*8)+c_NUM_TIME_BITS-1) downto ((11-v_trigInput)*8) ) <= trigger_times_i(v_trigInput);
+    end generate;
+  
+      
+  --! Could also output data on trigger_i , but let's use the delayed signals. \n
+  --! The counters are one cycle delayed from the signal generation
+  p_fifo_i : process (clk_4x_logic_i)
+  begin  
+    if rising_edge(clk_4x_logic_i) then
+      data_strobe_o <= s_event_strobe_d1 or s_event_strobe_d2 or s_event_strobe_d3_opt;
+      
+      if s_event_strobe_d1 = '1' then
+        event_data_o <= s_word0_d1;
+      elsif s_event_strobe_d2 = '1' then
+        event_data_o <= s_word1_d2;
+      elsif s_event_strobe_d3_opt = '1' then
+        event_data_o <= s_word2_d3;
+      else
+        event_data_o <= (others=>'0');
+      end if;
+    end if;
+  end process;
+		
+
+  cmp_timeStampCounter: entity work.counterWithReset
+    generic map (
+      g_COUNTER_WIDTH => s_coarse_timestamp'length)
+    port map (
+      clock_i  => clk_4x_logic_i,
+      reset_i  => s_reset_timestamp_4x or logic_reset_i,
+      enable_i => logic_strobe_i,
+      result_o => s_coarse_timestamp);
+    
+ 
+  -- Generate data in format decided at DESY. Put out two strobes for the
+  -- two 64 bit words.
+  -- get trigger inputs to also generate a global time-stamp ??
+  -- add trigger_inputs_active_i array (to indicate which triggers fired)
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..cb6b10104903070a5365064dee8d9d822d64cf42
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg.vhd
@@ -0,0 +1,27 @@
+--=============================================================================
+--! @file fmcTLU_pkg.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:44:31 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE fmcTLU IS
+  
+  constant c_NUM_TIME_BITS : natural := 5;
+  constant c_NUM_TRIG_INPUTS : natural := 4;
+  constant c_EVENT_DATA_WIDTH : natural := 32;
+  constant c_DATA_WIDTH : natural := 32;
+  
+  subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
+  --type    t_triggerTimeArray is array(natural range <>) of t_triggerTime;
+  type    t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+  type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
+  
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg_body.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg_body.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9437776d393daa1b6e790f3d5470fb09344259bc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/fmcTLU_pkg_body.vhd
@@ -0,0 +1,13 @@
+--=============================================================================
+--! @file fmcTLU_pkg_body.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
+--
+--! @author  phdgc
+--! @date  16:45:08 11/08/12         
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+PACKAGE BODY fmcTLU IS
+END fmcTLU;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/handshakes_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/handshakes_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ab893a2a99708784f934579adc8439a2593fe067
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/handshakes_rtl.vhd
@@ -0,0 +1,248 @@
+--=============================================================================
+--! @file handshakes_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
+--
+--! @brief Handshakes between TLU and DUTs. \n
+--
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 12:08:30 25/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY handshakes IS
+   GENERIC( 
+      g_IPBUS_WIDTH         : positive := 32
+   );
+   PORT( 
+      clk_i    			: IN     std_logic;
+		Trigger_i			: IN 		std_logic;
+      ipbus_clk_i       : IN     std_logic;
+      ipbus_i           : IN     ipb_wbus;
+      ipbus_reset_i     : IN     std_logic;
+      ipbus_o           : OUT    ipb_rbus;
+      logic_reset_i     : IN     std_logic;    
+		Busy_i				: IN		std_logic;
+		AIDAhandshake_o	: OUT		std_logic;		-- running an AIDA handshake or the old EUDET handshake
+		Trigger_o			: OUT 	std_logic;
+		rst_or_clk_o		: OUT 	std_logic		-- CONT in schematics
+   );
+
+-- Declarations
+
+END ENTITY handshakes ;
+
+--
+ARCHITECTURE rtl OF handshakes IS
+
+	signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+	signal s_Shutter, s_T0sync : std_logic;
+	signal s_Trigger, s_TrigAux : std_logic := '0';
+	signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
+	
+	signal TPx3_T0syncLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004";   	--! T0-sync length
+	signal TPx3_Start_T0sync 	: std_logic;   																--! Flag to start the T0-sync signal
+
+	signal s_Veto 			: std_logic := '0';
+	signal s_WU				: std_logic := '0';
+	signal s_NMaxPulses 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_SuDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_PulseLen 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_IpDTime 		: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+	signal s_RearmTime 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
+	signal s_PulseDelay 	: std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+	signal s_MaxPulses	: std_logic;
+	signal s_pulse			: std_logic;
+	
+	constant c_N_CTRL : positive := 13;
+	constant c_N_STAT : positive := 13;
+	signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+	signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> '0',--ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  open
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_i,
+      data_i      =>  s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_i);
+		
+	-----------------------------------------------------------------------------
+	-- Logic not ready to use
+	-----------------------------------------------------------------------------
+		
+	--Map the control registers
+	s_handshakeEnabled <= s_sync_control_from_ipbus(0);
+	
+	s_status_to_ipbus(0) <= s_handshakeEnabled;
+
+	
+	-- No handshake registers
+	s_NMaxPulses <= s_sync_control_from_ipbus(5);
+	s_SuDTime <= s_sync_control_from_ipbus(6);
+	s_PulseLen <= s_sync_control_from_ipbus(7);
+	s_IpDTime <= s_sync_control_from_ipbus(8);
+	s_RearmTime <= s_sync_control_from_ipbus(9);
+	s_PulseDelay <= s_sync_control_from_ipbus(10);
+	s_Veto <= s_sync_control_from_ipbus(11)(0);
+	s_WU <= s_sync_control_from_ipbus(11)(1);
+	
+	s_status_to_ipbus(5) <= s_NMaxPulses;
+	s_status_to_ipbus(6) <= s_SuDTime;
+	s_status_to_ipbus(7) <= s_PulseLen;
+	s_status_to_ipbus(8) <= s_IpDTime;
+	s_status_to_ipbus(9) <= s_RearmTime;
+	s_status_to_ipbus(10) <= s_PulseDelay;
+	s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
+	s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
+	
+	-- TPx3 registers
+	TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
+	TPx3_T0syncLen 	<= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
+								s_sync_control_from_ipbus(2);
+  
+	s_status_to_ipbus(1) <= x"0000000" & "000" & TPx3_Start_T0sync;
+	s_status_to_ipbus(2) <= TPx3_T0syncLen;
+  
+  
+	-----------------------------------------------------------------------------
+	-- Synchronization - Rewrite!!!
+	-----------------------------------------------------------------------------
+	p_trigger : process(Trigger_i, s_Trigger)
+	begin
+		if Trigger_i = '1' then
+			s_TrigAux <= '1';
+		elsif s_Trigger = '1' then
+			s_TrigAux <= '0';
+		end if;
+	end process p_trigger;
+	
+	p_sync: process (clk_i )
+	begin  -- process p_run_counter
+		if rising_edge(clk_i) then
+			s_Trigger <= s_TrigAux;
+			
+			s_Busy_d1 <= Busy_i;
+			s_Busy_d2 <= s_Busy_d1;
+			s_Busy_d3 <= s_Busy_d2;
+			s_Busy <= s_Busy_d2;
+		end if;
+  end process p_sync;
+	
+	-----------------------------------------------------------------------------
+	-- I/O
+	-----------------------------------------------------------------------------
+	Trigger_o <= 	s_Trigger when s_handshakeEnabled(1 downto 0) = "00"  and s_Busy = '0' else
+						s_pulse when s_handshakeEnabled(1 downto 0) = "01" else							-- No handshake
+						s_Shutter when s_handshakeEnabled(1 downto 0) = "10" else						-- TPx3 handshake
+						'0';
+	rst_or_clk_o <= 	s_T0sync when s_handshakeEnabled(1 downto 0) = "10" else
+							'0';
+	
+	AIDAhandshake_o <= not s_handshakeEnabled(3); 	-- s_handshakeEnabled = x"00001000" => EUDET handshake.
+																	-- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
+	
+	-- No Handshake (GPP)
+	No_handshake:  entity work.GPP
+	GENERIC MAP( 
+		g_IPBUS_WIDTH => g_IPBUS_WIDTH)
+	PORT MAP( 
+		clk_i       		=> clk_i,
+		Enable_i          => not (s_Busy or s_Veto),
+      Reset_i           => logic_reset_i,
+      RstPulsCnt_i     	=> '0',
+      Trigger_i         => s_Trigger,
+      NMaxPulses_i      => s_NMaxPulses,
+      SuDTime_i         => s_SuDTime,
+      PulsLen_i     		=> s_PulseLen,
+      IpDTime_i         => s_IpDTime,
+		RearmTime_i       => s_RearmTime,
+      Force_PullDown_i  => s_Busy or s_Veto,
+      WU_i              => s_WU,
+      PulseDelay_i      => s_PulseDelay,
+		event_number_o    => open,
+      MaxPulses_o       => s_MaxPulses,
+      Pulse_o           => s_pulse,
+      Pulse_d_o         => open);
+		
+	-- TPx3 Handshake
+	TPx3_logic: entity work.TPx3Logic
+   PORT MAP( 
+      clk_i					=> clk_i,
+		Start_T0sync_i		=> TPx3_Start_T0sync,
+		T0syncLen_i			=> TPx3_T0syncLen,
+      logic_reset_i     => logic_reset_i,
+      Busy_i				=> s_Busy,
+		Veto_i				=> s_Veto,
+		Shutter_o			=> s_Shutter,
+		T0sync_o 			=>	s_T0sync
+   );
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_bit_ctrl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_bit_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0dc4e9af1fdee8b4fccea67129d50fc24fedb46
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_bit_ctrl.vhd
@@ -0,0 +1,492 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------              
+
+
+--/////////////////////////////////////
+--// Bit controller section
+--/////////////////////////////////////
+--//
+--// Translate simple commands into SCL/SDA transitions
+--// Each command has 5 states, A/B/C/D/idle
+--//
+--// start:	SCL	~~~~~~~~~~\____
+--//	SDA	~~~~~~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// repstart	SCL	____/~~~~\___
+--//	SDA	__/~~~\______
+--//		 x | A | B | C | D | i
+--//
+--// stop	SCL	____/~~~~~~~~
+--//	SDA	==\____/~~~~~
+--//		 x | A | B | C | D | i
+--//
+--//- write	SCL	____/~~~~\____
+--//	SDA	==X=========X=
+--//		 x | A | B | C | D | i
+--//
+--//- read	SCL	____/~~~~\____
+--//	SDA	XXXX=====XXXX
+--//		 x | A | B | C | D | i
+--//
+--
+--// Timing:     Normal mode      Fast mode
+--///////////////////////////////////////////////////////////////////////
+--// Fscl        100KHz           400KHz
+--// Th_scl      4.0us            0.6us   High period of SCL
+--// Tl_scl      4.7us            1.3us   Low period of SCL
+--// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+--// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+--// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+--//
+--
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_bit_ctrl is
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+        
+ 
+end;
+
+architecture arch of i2c_master_bit_ctrl is
+
+--attribute UGROUP:string;                                   
+--attribute UGROUP of arch : label is "bit_group"; 
+
+
+signal sSCL, sSDA : std_logic;	-- synchronized SCL and SDA inputs
+signal dscl_oen : std_logic;	-- delayed scl_oen
+signal sda_chk : std_logic;		-- check SDA output (Multi-master arbitration)
+signal clk_en : std_logic;		-- clock generation signals
+signal slave_wait : std_logic;
+
+-- bus status controller signals
+signal dSCL,dSDA : std_logic;
+signal sta_condition : std_logic;
+signal sto_condition : std_logic;
+signal cmd_stop : std_logic;
+
+signal cnt : std_logic_vector(15 downto 0);	-- clock divider counter
+
+signal scl_oen_int : std_logic;
+signal sda_oen_int : std_logic;
+signal busy_int : std_logic;
+signal al_int : std_logic;
+
+-- state machine variable
+signal c_state : std_logic_vector(16 downto 0);
+
+constant idle 		: std_logic_vector(16 downto 0) := "00000000000000000";
+constant start_a 	: std_logic_vector(16 downto 0) := "00000000000000001";
+constant start_b 	: std_logic_vector(16 downto 0) := "00000000000000010";
+constant start_c 	: std_logic_vector(16 downto 0) := "00000000000000100";
+constant start_d 	: std_logic_vector(16 downto 0) := "00000000000001000";
+constant start_e 	: std_logic_vector(16 downto 0) := "00000000000010000";
+constant stop_a 	: std_logic_vector(16 downto 0) := "00000000000100000";
+constant stop_b	 	: std_logic_vector(16 downto 0) := "00000000001000000";
+constant stop_c	 	: std_logic_vector(16 downto 0) := "00000000010000000";
+constant stop_d 	: std_logic_vector(16 downto 0) := "00000000100000000";
+constant rd_a	 	: std_logic_vector(16 downto 0) := "00000001000000000";
+constant rd_b 		: std_logic_vector(16 downto 0) := "00000010000000000";
+constant rd_c 		: std_logic_vector(16 downto 0) := "00000100000000000";
+constant rd_d 		: std_logic_vector(16 downto 0) := "00001000000000000";
+constant wr_a 		: std_logic_vector(16 downto 0) := "00010000000000000";
+constant wr_b 		: std_logic_vector(16 downto 0) := "00100000000000000";
+constant wr_c 		: std_logic_vector(16 downto 0) := "01000000000000000";
+constant wr_d 		: std_logic_vector(16 downto 0) := "10000000000000000";
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+begin
+
+scl_oen <= scl_oen_int;
+sda_oen <= sda_oen_int;
+
+-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+-- delay scl_oen
+process(clk)
+begin
+	if rising_edge(clk) then
+		dscl_oen <= scl_oen_int;
+	end if;
+end process;
+
+slave_wait <= '1' when ((dscl_oen = '1') AND (sSCL = '0')) else '0';
+
+-- generate clk enable signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cnt <= (others => '0');
+		clk_en <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cnt <= (others => '0');
+			clk_en <= '1';
+		elsif ((cnt = "0000000000000000") OR (ena = '0')) then
+			cnt <= clk_cnt;
+			clk_en <= '1';
+		elsif (slave_wait = '1') then
+			cnt <= cnt;
+			clk_en <= '0';
+		else
+			cnt <= cnt - '1';
+			clk_en <= '0';
+		end if;
+	end if;
+end process;
+
+-- synchronize SCL and SDA inputs
+-- reduce metastability risc
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sSCL <= '1';
+		sSDA <= '1';
+		dSCL <= '1';
+		dSDA <= '1';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sSCL <= '1';
+			sSDA <= '1';
+			dSCL <= '1';
+			dSDA <= '1';
+		else
+			dSCL <= sSCL;
+			dSDA <= sSDA;
+                        -- Don't need to treat 'H' if separate I and O
+			-- if ((scl_i = '1') OR (scl_i = 'H')) then
+                        if (scl_i = '1')  then
+				sSCL <= '1';
+			else
+				sSCL <= '0';
+			end if;
+			-- if ((sda_i = '1') OR (sda_i = 'H')) then
+                        if (sda_i = '1')  then
+				sSDA <= '1';
+			else
+				sSDA <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+-- detect start condition => detect falling edge on SDA while SCL is high
+-- detect stop condition => detect rising edge on SDA while SCL is high
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sta_condition <= '0';
+		sto_condition <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sta_condition <= '0';
+			sto_condition <= '0';
+		else
+			sta_condition <= NOT(sSDA) AND dSDA AND sSCL;
+			sto_condition <= sSDA AND NOT(dSDA) AND sSCL;
+		end if;
+	end if;
+end process;
+
+-- generate i2c bus busy signal
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		busy_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			busy_int <= '0';
+		else
+			busy_int <= (sta_condition OR busy_int) AND NOT(sto_condition);
+		end if;
+	end if;
+end process;
+
+busy <= busy_int;
+
+-- generate arbitration lost signal
+-- aribitration lost when:
+-- 1) master drives SDA high, but the i2c bus is low
+-- 2) stop detected while not requested
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		cmd_stop <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			cmd_stop <= '0';
+		elsif (clk_en = '1') then
+			if (cmd = I2C_CMD_STOP) then
+				cmd_stop <= '1';
+			else
+				cmd_stop <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		al_int <= '0';
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			al_int <= '0';
+		else
+			if (((sda_chk = '1') AND (sSDA = '0') AND (sda_oen_int = '1')) OR ((c_state /= idle) AND (sto_condition = '1') AND (cmd_stop = '0'))) then
+				al_int <= '1';
+			else
+				al_int <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+al <= al_int;
+
+
+-- generate dout signal (store SDA on rising edge of SCL)
+process(clk)
+begin
+	if rising_edge(clk) then
+		if ((sSCL = '1') AND (dSCL = '0')) then
+			dout <= sSDA;
+		end if;
+	end if;
+end process;
+
+
+--generate state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		c_state <= idle;
+		cmd_ack <= '0';
+		scl_oen_int <= '1';
+		sda_oen_int <= '1';
+		sda_chk <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (al_int = '1')) then
+			c_state <= idle;
+			cmd_ack <= '0';
+			scl_oen_int <= '1';
+			sda_oen_int <= '1';
+			sda_chk <= '0';
+		else
+			cmd_ack <= '0';	--default no command acknowledge + assert cmd_ack only 1clk cycle
+			if (clk_en = '1') then
+				case (c_state) is
+					when idle =>
+							case (cmd) is
+								when I2C_CMD_START	=> c_state <= start_a;
+								when I2C_CMD_STOP	=> c_state <= stop_a;
+								when I2C_CMD_WRITE	=> c_state <= wr_a;
+								when I2C_CMD_READ	=> c_state <= rd_a;
+								when others			=> c_state <= idle;
+							end case;
+
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= sda_oen_int;  -- keep SDA in same state
+							sda_chk <= '0';              -- don't check SDA output
+					when start_a =>          -- start
+							c_state <= start_b;
+							scl_oen_int <= scl_oen_int;  -- keep SCL in same state
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_b =>
+							c_state <= start_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when start_c =>
+							c_state <= start_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_d =>
+							c_state <= start_e;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when start_e =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_a =>          -- stop
+							c_state <= stop_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '0';          -- set SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_b =>
+							c_state <= stop_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_c =>
+							c_state <= stop_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '0';          -- keep SDA low
+							sda_chk <= '0';              -- don't check SDA output
+					when stop_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- set SDA high
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_a =>          -- read
+							c_state <= rd_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= '1';          -- tri-state SDA
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_b =>
+							c_state <= rd_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_c =>
+							c_state <= rd_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when rd_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= '1';          -- keep SDA tri-stated
+							sda_chk <= '0';              -- don't check SDA output
+					when wr_a =>          -- write
+							c_state <= wr_b;
+							scl_oen_int <= '0';          -- keep SCL low
+							sda_oen_int <= din;          -- set SDA
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when wr_b =>
+							c_state <= wr_c;
+							scl_oen_int <= '1';          -- set SCL high
+							sda_oen_int <= din;          -- keep SDA
+							sda_chk <= '1';              -- check SDA output
+					when wr_c =>
+							c_state <= wr_d;
+							scl_oen_int <= '1';          -- keep SCL high
+							sda_oen_int <= din;
+							sda_chk <= '1';              -- check SDA output
+					when wr_d =>
+							c_state <= idle;
+							cmd_ack <= '1';
+							scl_oen_int <= '0';          -- set SCL low
+							sda_oen_int <= din;
+							sda_chk <= '0';              -- don't check SDA output (SCL low)
+					when others => NULL;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+-- assign scl and sda output (always gnd)
+scl_o <= '0';
+sda_o <= '0';
+
+end arch;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_byte_ctrl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_byte_ctrl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f52195741d35d657cf7dad6d66f708bda9d46b28
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_byte_ctrl.vhd
@@ -0,0 +1,286 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master byte-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-----------------------------------------------------------------------
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                        
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------  
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_byte_ctrl is
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end;
+
+architecture arch of i2c_master_byte_ctrl is
+
+constant I2C_CMD_NOP	: std_logic_vector(3 downto 0) := "0000";
+constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+constant I2C_CMD_STOP	: std_logic_vector(3 downto 0) := "0010";
+constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "0100";
+constant I2C_CMD_READ	: std_logic_vector(3 downto 0) := "1000";
+
+
+constant ST_IDLE	: std_logic_vector(4 downto 0) := "00000";
+constant ST_START	: std_logic_vector(4 downto 0) := "00001";
+constant ST_READ	: std_logic_vector(4 downto 0) := "00010";
+constant ST_WRITE	: std_logic_vector(4 downto 0) := "00100";
+constant ST_ACK		: std_logic_vector(4 downto 0) := "01000";
+constant ST_STOP	: std_logic_vector(4 downto 0) := "10000";
+
+signal c_state : std_logic_vector(4 downto 0);
+
+
+signal go : std_logic;
+signal dcnt : std_logic_vector(2 downto 0);
+signal cnt_done : std_logic;
+
+signal sr : std_logic_vector(7 downto 0); --8bit shift register
+signal shift, ld : std_logic;
+
+signal cmd_ack_int : std_logic;
+
+
+begin
+
+go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
+dout <= sr;
+
+-- generate shift register
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		sr <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			sr <= (others => '0');
+		elsif (ld = '1') then
+			sr <= din;
+		elsif (shift = '1') then
+			sr <= sr(6 downto 0) & core_rxd;
+		end if;
+	end if;
+end process;
+
+-- generate counter
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		dcnt <= (others => '0');
+	elsif rising_edge(clk) then
+		if (rst = '1') then
+			dcnt <= (others => '0');
+		elsif (ld = '1') then
+			dcnt <= "111";
+		elsif (shift = '1') then
+			dcnt <= dcnt - '1';
+		end if;
+	end if;
+end process;
+
+cnt_done <= '1' when (dcnt = "000") else '0';
+
+-- state machine
+process(clk,nReset)
+begin
+	if (nReset = '0') then
+		core_cmd <= I2C_CMD_NOP;
+		core_txd <= '0';
+		shift <= '0';
+		ld <= '0';
+		cmd_ack_int <= '0';
+		c_state <= ST_IDLE;
+		ack_out <= '0';
+	elsif rising_edge(clk) then
+		if ((rst = '1') OR (i2c_al = '1')) then
+			core_cmd <= I2C_CMD_NOP;
+			core_txd <= '0';
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+			c_state <= ST_IDLE;
+			ack_out <= '0';
+		else
+			-- initially reset all signals
+			core_txd <= sr(7);
+			shift <= '0';
+			ld <= '0';
+			cmd_ack_int <= '0';
+
+			case (c_state) is
+				when ST_IDLE =>
+						if (go = '1') then
+							if (start = '1') then
+								c_state <= ST_START;
+								core_cmd <= I2C_CMD_START;
+							elsif (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							elsif (write = '1') then
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_START =>
+						if (core_ack = '1') then
+							if (read = '1') then
+								c_state <= ST_READ;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;
+								core_cmd <= I2C_CMD_WRITE;
+							end if;
+							ld <= '1';
+						end if;
+				when ST_WRITE =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_READ;
+							else
+								c_state <= ST_WRITE;		-- stay in same state
+								core_cmd <= I2C_CMD_WRITE;	-- write next bit
+								shift <= '1';
+							end if;
+						end if;
+				when ST_READ =>
+						if (core_ack = '1') then
+							if (cnt_done = '1') then
+								c_state <= ST_ACK;
+								core_cmd <= I2C_CMD_WRITE;
+							else
+								c_state <= ST_READ;			-- stay in same state
+								core_cmd <= I2C_CMD_READ;	-- read next bit
+								shift <= '1';
+							end if;
+							shift <= '1';
+							core_txd <= ack_in;
+						end if;
+				when ST_ACK =>
+						if (core_ack = '1') then
+							if (stop = '1') then
+								c_state <= ST_STOP;
+								core_cmd <= I2C_CMD_STOP;
+							else
+								c_state <= ST_IDLE;
+								core_cmd <= I2C_CMD_NOP;
+								-- generate command acknowledge signal
+								cmd_ack_int <= '1';
+							end if;
+							-- assign ack_out output to bit_controller_rxd (contains last received bit)
+							ack_out <= core_rxd;
+							core_txd <= '1';
+						else
+							core_txd <= ack_in;
+						end if;
+				when ST_STOP =>
+						if (core_ack = '1') then
+							c_state <= ST_IDLE;
+							core_cmd <= I2C_CMD_NOP;
+							-- generate command acknowledge signal
+							cmd_ack_int <= '1';
+						end if;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+cmd_ack <= cmd_ack_int;
+
+end arch;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_registers.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_registers.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..620e226cd1582dc3f8ed20c3dbd6dd98f42cf127
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_registers.vhd
@@ -0,0 +1,196 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master registers             ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-- --------------------------------------------------------------------    
+-- --------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_registers is
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end;
+
+architecture arch of i2c_master_registers is
+
+
+signal ctr_int : std_logic_vector(7 downto 0);
+signal cr_int : std_logic_vector(7 downto 0);
+
+signal al : std_logic;			-- status register arbitration lost bit
+signal rxack : std_logic;		-- received aknowledge from slave
+signal tip : std_logic;			-- transfer in progress
+signal irq_flag : std_logic;	-- interrupt pending flag
+
+begin
+
+-- generate prescale regisres, control registers, and transmit register
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		prer <= (others => '1');
+		ctr_int <= (others => '0');
+		txr <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			prer <= (others => '1');
+			ctr_int <= (others => '0');
+			txr <= (others => '0');
+		elsif (wb_wacc = '1') then
+			case (wb_adr_i) is
+				when "000" => prer(7 downto 0)	<= wb_dat_i;
+				when "001" => prer(15 downto 8)	<= wb_dat_i;
+				when "010" => ctr_int			<= wb_dat_i;
+				when "011" => txr				<= wb_dat_i;
+				when others => NULL;
+			end case;
+		end if;
+	end if;
+end process;
+
+ctr <= ctr_int;
+
+-- generate command register (special case)
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		cr_int <= (others => '0');
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			cr_int <= (others => '0');
+		elsif (wb_wacc = '1') then
+			if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
+				cr_int <= wb_dat_i;
+			end if;
+		else
+			if ((done = '1') OR (i2c_al = '1')) then
+				cr_int(7 downto 4) <= "0000";	-- clear command b
+			end if;							-- or when aribitr
+			cr_int(2 downto 1) <= "00";			-- reserved bits
+			cr_int(0) <= '0';					-- clear IRQ_ACK b
+		end if;
+	end if;
+end process;
+
+cr <= cr_int;
+
+-- generate status register block + interrupt request signal
+-- each output will be assigned to corresponding sr register locations on top level
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		al 			<= '0';
+		rxack 		<= '0';
+		tip 		<= '0';
+		irq_flag	<= '0';
+	elsif rising_edge(wb_clk_i) then
+		if (wb_rst_i = '1') then
+			al 			<= '0';
+			rxack 		<= '0';
+			tip 		<= '0';
+			irq_flag	<= '0';
+		else
+			al			<= i2c_al OR (al AND NOT(cr_int(7)));
+			rxack		<= irxack;
+			tip			<= (cr_int(5) OR cr_int(4));
+			irq_flag	<= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
+		end if;
+	end if;
+end process;
+
+sr(7)	 		<= rxack;
+sr(6)			<= i2c_busy;
+sr(5)			<= al;
+sr(4 downto 2)	<= "000"; -- reserved
+sr(1)			<= tip;
+sr(0)			<= irq_flag;
+
+
+end arch;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d0bb973aa56b1e35107d8d22fd37574f7e7eed6
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_rtl.vhd
@@ -0,0 +1,97 @@
+--=============================================================================
+--! @file i2c_master_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.i2c_master.rtl
+--
+--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
+--! are bundled together in a record\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 17:22:12 11/30/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY i2c_master IS
+   PORT( 
+      i2c_scl_i     : IN     std_logic;
+      i2c_sda_i     : IN     std_logic;
+      ipbus_clk_i   : IN     std_logic;
+      ipbus_i       : IN     ipb_wbus;    -- Signals from IPBus core to slave
+      ipbus_reset_i : IN     std_logic;
+      i2c_scl_enb_o : OUT    std_logic;
+      i2c_sda_enb_o : OUT    std_logic;
+      ipbus_o       : OUT    ipb_rbus     -- signals from slave to IPBus core
+   );
+
+-- Declarations
+
+END ENTITY i2c_master ;
+
+--
+ARCHITECTURE rtl OF i2c_master IS
+  
+  --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
+  
+BEGIN
+  
+  --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
+  --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
+
+  i2c_interface: entity work.i2c_master_top port map(
+                wb_clk_i => ipbus_clk_i,
+                wb_rst_i => ipbus_reset_i,
+                arst_i => '1',
+                wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
+                wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
+                wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
+                wb_we_i => ipbus_i.ipb_write,
+                wb_stb_i => ipbus_i.ipb_strobe,
+                wb_cyc_i => '1',
+                wb_ack_o => ipbus_o.ipb_ack,
+                wb_inta_o => open,
+                scl_pad_i => i2c_scl_i,
+                scl_pad_o => open,
+                scl_padoen_o => i2c_scl_enb_o,
+                sda_pad_i => i2c_sda_i,
+                sda_pad_o => open,
+                sda_padoen_o => i2c_sda_enb_o
+        );
+        
+  
+  ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
+  ipbus_o.ipb_err <= '0'; -- never return an error.
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_top.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a6f0aabbb39ea9507a6183182169d36ad85039a1
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/i2c/i2c_master_top.vhd
@@ -0,0 +1,344 @@
+----------------------------------------------------------------------
+-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
+----------------------------------------------------------------------
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--//  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+--//                                                             ////
+--//                                                             ////
+--//  Author: Richard Herveille                                  ////
+--//          richard@asics.ws                                   ////
+--//          www.asics.ws                                       ////
+--//                                                             ////
+--//  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+--//                                                             ////
+--// Copyright (C) 2001 Richard Herveille                        ////
+--//                    richard@asics.ws                         ////
+--//                                                             ////
+--// This source file may be used and distributed without        ////
+--// restriction provided that this copyright statement is not   ////
+--// removed from the file and that any derivative work contains ////
+--// the original copyright notice and the associated disclaimer.////
+--//                                                             ////
+--//     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+--// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+--// POSSIBILITY OF SUCH DAMAGE.                                 ////
+--//                                                             ////
+--///////////////////////////////////////////////////////////////////
+-- --------------------------------------------------------------------              
+-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<              
+-- --------------------------------------------------------------------              
+-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation                    
+-- --------------------------------------------------------------------                            
+--                                                                                   
+-- Disclaimer:                                                                       
+--                                                                                   
+-- This VHDL or Verilog source code is intended as a design reference                
+-- which illustrates how these types of functions can be implemented.                
+-- It is the user's responsibility to verify their design for                        
+-- consistency and functionality through the use of formal                           
+-- verification methods. Lattice Semiconductor provides no warranty                  
+-- regarding the use or functionality of this code.                                  
+--                                                                                   
+-- --------------------------------------------------------------------              
+--                                                                                   
+-- Lattice Semiconductor Corporation                                                 
+-- 5555 NE Moore Court                                                               
+-- Hillsboro, OR 97214                                                               
+-- U.S.A                                                                             
+--                                                                                   
+-- TEL: 1-800-Lattice (USA and Canada)                                               
+-- 503-268-8001 (other locations)                                                    
+--                                                                                   
+-- web: http://www.latticesemi.com/                                                  
+-- email: techsupport@latticesemi.com                                                
+--                                                                                   
+-- --------------------------------------------------------------------              
+-- Code Revision History :                                                           
+-- --------------------------------------------------------------------              
+-- Ver: | Author |Mod. Date |Changes Made:                                           
+-- V1.0 |K.P.    | 7/09     | Initial ver for VHDL                                       
+-- 			    | converted from LSC ref design RD1046                   
+-------------------------------------------------------------------------------
+-- Changes at University of bristol:
+-- V1.0A|D.G.C   | 5/11     | Changed name and ports to fit OC original
+-- --------------------------------------------------------------------    
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity i2c_master_top is
+  generic (
+		ARST_LVL : integer := 0
+		);
+  port (
+        wb_clk_i : in  std_logic;
+        wb_rst_i : in  std_logic;
+        arst_i   : in  std_logic;
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_dat_o : out std_logic_vector(7 downto 0);
+        wb_we_i  : in  std_logic;
+        wb_stb_i : in  std_logic;
+        wb_cyc_i : in  std_logic;
+        wb_ack_o : out std_logic;
+        wb_inta_o: out std_logic;
+        scl_pad_i: in std_logic;
+        scl_pad_o: out std_logic;
+        scl_padoen_o: out std_logic;
+        sda_pad_i: in std_logic;
+        sda_pad_o: out std_logic;
+        sda_padoen_o: out std_logic
+--        scl      : inout std_logic;
+--        sda      : inout std_logic
+        );
+end;
+
+architecture arch of i2c_master_top is
+
+component i2c_master_bit_ctrl
+  port (
+        clk      : in  std_logic;
+        rst      : in  std_logic;
+        nReset   : in  std_logic;
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- clock prescale value
+        ena      : in  std_logic;						-- core enable signal
+        cmd      : in  std_logic_vector(3 downto 0);
+        cmd_ack  : out std_logic;						-- command complete acknowledge
+        busy     : out std_logic;						-- i2c bus busy
+        al       : out std_logic;						-- i2c bus arbitration lost
+        din      : in  std_logic;
+        dout     : out std_logic;
+        scl_i    : in  std_logic;						-- i2c clock line input
+        scl_o    : out std_logic;						-- i2c clock line output
+        scl_oen  : out std_logic;						-- i2c clock line output enable (active low)
+        sda_i    : in  std_logic;						-- i2c data line input
+        sda_o    : out std_logic;						-- i2c data line output
+        sda_oen  : out std_logic						-- i2c data line output enable (active low)
+        );
+end component;
+
+component i2c_master_byte_ctrl
+  port (
+        clk      : in  std_logic;						-- master clock
+        rst      : in  std_logic;						-- synchronous active high reset
+        nReset   : in  std_logic;						-- asynchronous active low reset
+        clk_cnt  : in  std_logic_vector(15 downto 0);	-- 4x SCL
+		-- control inputs
+        start    : in  std_logic;
+        stop     : in  std_logic;
+        read     : in  std_logic;
+        write    : in  std_logic;
+        ack_in   : in  std_logic;
+        din      : in  std_logic_vector(7 downto 0);
+		-- status outputs
+        cmd_ack  : out std_logic;
+        ack_out  : out std_logic;						-- i2c clock line input
+        dout     : out std_logic_vector(7 downto 0);
+        i2c_al   : in  std_logic;
+		-- signals for bit_controller
+		core_cmd : out std_logic_vector(3 downto 0);
+		core_txd : out std_logic;
+		core_rxd : in  std_logic;
+		core_ack : in  std_logic
+        );
+end component;
+
+component i2c_master_registers
+  port (
+        wb_clk_i : in  std_logic;
+        rst_i    : in  std_logic;
+        wb_rst_i : in  std_logic;
+        wb_dat_i : in  std_logic_vector(7 downto 0);
+        wb_adr_i : in  std_logic_vector(2 downto 0);
+        wb_wacc  : in  std_logic;
+        i2c_al   : in  std_logic;
+        i2c_busy : in  std_logic;
+        done     : in  std_logic;
+        irxack   : in  std_logic;
+        prer     : out std_logic_vector(15 downto 0);	-- clock prescale register
+        ctr      : out std_logic_vector(7 downto 0);	-- control register
+        txr      : out std_logic_vector(7 downto 0);	-- transmit register
+        cr       : out std_logic_vector(7 downto 0);	-- command register
+        sr       : out std_logic_vector(7 downto 0)		-- status register
+        );
+end component;
+
+
+signal prer : std_logic_vector(15 downto 0);
+signal ctr : std_logic_vector(7 downto 0);
+signal txr : std_logic_vector(7 downto 0);
+signal rxr : std_logic_vector(7 downto 0);
+signal cr : std_logic_vector(7 downto 0);
+signal sr : std_logic_vector(7 downto 0);
+
+signal done : std_logic;
+signal core_en : std_logic;
+signal ien : std_logic;
+signal irxack : std_logic;
+signal irq_flag : std_logic;
+signal i2c_busy : std_logic;
+signal i2c_al : std_logic;
+
+signal core_cmd : std_logic_vector(3 downto 0);
+signal core_txd : std_logic;
+signal core_ack, core_rxd : std_logic;
+
+-- Don't need these signals, since passing them through
+-- component interface
+--signal scl_pad_i : std_logic;
+--signal scl_pad_o : std_logic;
+--signal scl_padoen_o : std_logic;
+--
+--signal sda_pad_i : std_logic;
+--signal sda_pad_o : std_logic;
+--signal sda_padoen_o : std_logic;
+
+signal rst_i : std_logic;
+
+signal sta : std_logic;
+signal sto : std_logic;
+signal rd : std_logic;
+signal wr : std_logic;
+signal ack : std_logic;
+signal iack : std_logic;
+
+signal wb_ack_o_int : std_logic;
+
+signal wb_wacc : std_logic;
+signal acki : std_logic;
+
+begin
+
+  -- Don't need to copy these signal - passing through
+  -- component interface
+--scl_pad_i <= scl;
+--sda_pad_i <= sda;
+
+rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
+
+wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
+
+sta <= cr(7);
+sto <= cr(6);
+rd <= cr(5);
+wr <= cr(4);
+ack <= cr(3);
+acki <= cr(0);
+
+core_en <= ctr(7);
+ien <= ctr(6);
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
+	end if;
+end process;
+
+wb_ack_o <= wb_ack_o_int;
+
+process(wb_clk_i)
+begin
+	if rising_edge(wb_clk_i) then
+		case (wb_adr_i) is
+			when "000" => wb_dat_o <= prer(7 downto 0);
+			when "001" => wb_dat_o <= prer(15 downto 8);
+			when "010" => wb_dat_o <= ctr;
+			when "011" => wb_dat_o <= rxr;
+			when "100" => wb_dat_o <= sr;
+			when "101" => wb_dat_o <= txr;
+			when "110" => wb_dat_o <= cr;
+			when "111" => wb_dat_o <= "00000000";
+			when others => NULL;
+		end case;
+	end if;
+end process;
+
+process(wb_clk_i,rst_i)
+begin
+	if (rst_i = '0') then
+		wb_inta_o <= '0';
+	elsif rising_edge(wb_clk_i) then
+		wb_inta_o <= sr(0) AND ien;
+	end if;
+end process;
+
+
+
+byte_controller: i2c_master_byte_ctrl port map(
+	clk 		=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	clk_cnt		=> prer,
+	start		=> sta,
+	stop		=> sto,
+	read		=> rd,
+	write		=> wr,
+	ack_in		=> ack,
+	din			=> txr,
+	cmd_ack		=> done,
+	ack_out		=> irxack,
+	dout		=> rxr,
+	i2c_al		=> i2c_al,
+	core_cmd	=> core_cmd,
+	core_ack	=> core_ack,
+	core_txd	=> core_txd,
+	core_rxd	=> core_rxd);
+
+bit_controller: i2c_master_bit_ctrl port map(
+	clk			=> wb_clk_i,
+	rst			=> wb_rst_i,
+	nReset		=> rst_i,
+	ena			=> core_en,
+	clk_cnt		=> prer,
+	cmd			=> core_cmd,
+	cmd_ack		=> core_ack,
+	busy		=> i2c_busy,
+	al			=> i2c_al,
+	din			=> core_txd,
+	dout		=> core_rxd,
+	scl_i		=> scl_pad_i,
+	scl_o		=> scl_pad_o,
+	scl_oen		=> scl_padoen_o,
+	sda_i		=> sda_pad_i,
+	sda_o		=> sda_pad_o,
+	sda_oen		=> sda_padoen_o);
+
+registers: i2c_master_registers port map(
+	wb_clk_i	=> wb_clk_i,
+	rst_i		=> rst_i,
+	wb_rst_i	=> wb_rst_i,
+	wb_dat_i	=> wb_dat_i,
+	wb_wacc		=> wb_wacc,
+	wb_adr_i	=> wb_adr_i,
+	i2c_al		=> i2c_al,
+	i2c_busy	=> i2c_busy,
+	done		=> done,
+	irxack		=> irxack,
+	prer		=> prer,
+	ctr			=> ctr,
+	txr			=> txr,
+	cr			=> cr,
+	sr			=> sr);
+
+
+-- edited from Lattice original to pass uni-directional signals
+--scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
+--sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
+
+end arch;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_addr_decode.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_addr_decode.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dc630e87a5945dbbdfb05c850418867e503ddf39
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_addr_decode.vhd
@@ -0,0 +1,50 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+  function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+    variable sel : integer;
+  begin
+		if    std_match(addr, "-----------------------0001-----") then
+			sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
+		elsif std_match(addr, "-----------------------0010-----") then
+			sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
+		elsif std_match(addr, "-----------------------0011-----") then
+			sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
+		elsif std_match(addr, "-----------------------0100-----") then
+			sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
+		elsif std_match(addr, "-----------------------0101-----") then
+			sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
+		elsif std_match(addr, "-----------------------0110-----") then
+			sel := 5; -- i2c_master / base 000000c0 / mask 00000007
+		elsif std_match(addr, "-----------------------1010-----") then
+                        sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
+                elsif std_match(addr, "-----------------------1011-----") then
+                        sel := 7; -- TPix3_iface   / base 00000160 / mask 0000001f
+		elsif std_match(addr, "-----------------------0000-----") then
+			sel := 8; -- version / base 00000000 / mask 00000000
+		else
+			sel := 99;
+		end if;
+		return sel;
+	end ipbus_addr_sel;
+ 
+end ipbus_addr_decode;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_ipbus_example.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a315ed0358c7662662ddd26e751043300ed6937c
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_ipbus_example.vhd
@@ -0,0 +1,69 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+-- 
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_ipbus_example is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_ipbus_example;
+
+package body ipbus_decode_ipbus_example is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "-----------------000----------0-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "-----------------000----------1-") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    --elsif std_match(addr, "-----------------001------------") then
+      --sel := ipbus_sel_t(to_unsigned(N_SLV_RAM, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    --elsif std_match(addr, "-----------------010----------0-") then
+     -- sel := ipbus_sel_t(to_unsigned(N_SLV_PRAM, IPBUS_SEL_WIDTH)); -- pram / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "-----------------011------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "-----------------100------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- i2c / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "-----------------101------------") then
+      sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- i2c / base 0x00005000 / mask 0x00003002
+-- END automatically generated VHDL
+
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_ipbus_example;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_tlu.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_tlu.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..114da4012cbed8bf184566ff856f82576a074ff7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_decode_tlu.vhd
@@ -0,0 +1,73 @@
+-- Address decode logic for ipbus fabric
+-- 
+-- 
+-- 
+-- Paolo Baesso, February 2017
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+package ipbus_decode_tlu is
+
+  constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
+  subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+  constant N_SLV_CTRL_REG: integer := 0; --for tests
+  constant N_SLV_REG: integer := 1; -- for tests
+  constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
+  constant N_SLV_DUT: integer :=3;
+  constant N_SLV_SHUT: integer :=4;
+  constant N_SLV_EVBUF: integer :=5;
+  constant N_SLV_EVFMT: integer :=6;
+  constant N_SLV_TRGIN: integer :=7;
+  constant N_SLV_TRGLGC: integer :=8;
+  constant N_SLV_LGCCLK: integer :=9;
+    
+  constant N_SLAVES: integer := 10; --Total number of IPBus slaves
+-- END automatically generated VHDL
+  --constant N_I2C_CORES: integer := 3; --How many I2C cores
+    
+end ipbus_decode_tlu;
+
+package body ipbus_decode_tlu is
+
+  function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
+    variable sel: ipbus_sel_t;
+  begin
+
+-- START automatically  generated VHDL the Fri Oct  7 12:10:31 2016 
+    if    std_match(addr, "----------------0000----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
+    elsif std_match(addr, "----------------0000----------1-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
+    elsif std_match(addr, "----------------0001------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
+    elsif std_match(addr, "----------------0010----------0-") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_SHUT, IPBUS_SEL_WIDTH)); -- shutter / base 0x00002000 / mask 0x00003002
+    elsif std_match(addr, "----------------0011------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
+    elsif std_match(addr, "----------------0100------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVBUF, IPBUS_SEL_WIDTH)); -- event buffer / base 0x00004000 / mask 0x00003002
+    elsif std_match(addr, "----------------0101------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_EVFMT, IPBUS_SEL_WIDTH)); -- event formatter / base 0x00005000 / mask 0x00003002
+    elsif std_match(addr, "----------------0110------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- trigger inputs / base 0x00006000 / mask 0x00003002
+    elsif std_match(addr, "----------------0111------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_TRGLGC, IPBUS_SEL_WIDTH)); -- trigger logic / base 0x00007000 / mask 0x00003002
+    elsif std_match(addr, "----------------1000------------") then
+        sel := ipbus_sel_t(to_unsigned(N_SLV_LGCCLK, IPBUS_SEL_WIDTH)); -- logic clocks / base 0x00008000 / mask 0x00003002
+-- END automatically generated VHDL
+ 
+    else
+        sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
+    end if;
+
+    return sel;
+
+  end function ipbus_sel_ipbus_example;
+
+end ipbus_decode_tlu;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_example.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_example.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..5cc5f12c11b018fd6cbf7c022792e71ff24b06da
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_example.vhd
@@ -0,0 +1,174 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_example is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_example;
+
+architecture rtl of ipbus_example is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+       COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+
+	slave4: entity work.ipbus_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_RAM),
+			ipbus_out => ipbr(N_SLV_RAM)
+		);
+	
+-- Slave 3: peephole RAM
+
+	slave5: entity work.ipbus_peephole_ram
+		generic map(ADDR_WIDTH => 10)
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_PRAM),
+			ipbus_out => ipbr(N_SLV_PRAM)
+		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_fabric_sel.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_fabric_sel.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..86d2fa7ad9b120d636c28ad9fe3de5a35eaa0d51
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_fabric_sel.vhd
@@ -0,0 +1,61 @@
+-- The ipbus bus fabric, address select logic, data multiplexers
+--
+-- This version selects the addressed slave depending on the state
+-- of incoming control lines
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+
+entity ipbus_fabric_sel is
+  generic(
+    NSLV: positive;
+    STROBE_GAP: boolean := false;
+    SEL_WIDTH: positive
+   );
+  port(
+  	sel: in std_logic_vector(SEL_WIDTH - 1 downto 0);
+    ipb_in: in ipb_wbus;
+    ipb_out: out ipb_rbus;
+    ipb_to_slaves: out ipb_wbus_array(NSLV - 1 downto 0);
+    ipb_from_slaves: in ipb_rbus_array(NSLV - 1 downto 0) := (others => IPB_RBUS_NULL)
+   );
+
+end ipbus_fabric_sel;
+
+architecture rtl of ipbus_fabric_sel is
+
+	signal sel_i: integer range 0 to NSLV := 0;
+	signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
+	signal qstrobe: std_logic;
+
+begin
+
+	sel_i <= to_integer(unsigned(sel));
+
+	ored_ack(NSLV) <= '0';
+	ored_err(NSLV) <= '0';
+	
+	qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
+	 ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
+
+	busgen: for i in NSLV-1 downto 0 generate
+	begin
+
+		ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
+		ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
+		ipb_to_slaves(i).ipb_strobe <= qstrobe when sel_i = i else '0';
+		ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
+		ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
+		ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;		
+
+	end generate;
+
+  ipb_out.ipb_rdata <= ipb_from_slaves(sel_i).ipb_rdata when sel_i /= NSLV else (others => '0');
+  ipb_out.ipb_ack <= ored_ack(0);
+  ipb_out.ipb_err <= ored_err(0);
+  
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_slaves.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_slaves.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0ee08ffa82d15f637cdba389211c81b5a7c47c7
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_slaves.vhd
@@ -0,0 +1,170 @@
+-- ipbus_example
+--
+-- selection of different IPBus slaves without actual function,
+-- just for performance evaluation of the IPbus/uhal system
+--
+-- Kristian Harder, March 2014
+-- based on code by Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use work.ipbus_decode_ipbus_example.all;
+
+entity ipbus_slaves is
+	port(
+		ipb_clk: in std_logic;
+		ipb_rst: in std_logic;
+		ipb_in: in ipb_wbus;
+		ipb_out: out ipb_rbus;
+		nuke: out std_logic;
+		soft_rst: out std_logic;
+		--i2c_scl_b: INOUT  std_logic;
+        --i2c_sda_b: INOUT  std_logic;
+        
+        --i2c_sda_i: IN std_logic;
+        --i2c_scl_i: IN std_logic;
+        --i2c_scl_enb_o: OUT std_logic;
+        --i2c_sda_enb_o: OUT std_logic;
+                
+        i2c_sda_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_i: IN std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_scl_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        i2c_sda_enb_o: OUT std_logic_vector(N_I2C_CORES - 1 downto 0);
+        userled: out std_logic
+	);
+
+end ipbus_slaves;
+
+architecture rtl of ipbus_slaves is
+
+	signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
+	signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+           
+    -->P
+    COMPONENT i2c_master
+    PORT (
+       i2c_scl_i     : IN     std_logic;
+       i2c_sda_i     : IN     std_logic;
+       ipbus_clk_i   : IN     std_logic;
+       ipbus_i       : IN     ipb_wbus;
+       ipbus_reset_i : IN     std_logic;
+       i2c_scl_enb_o : OUT    std_logic;
+       i2c_sda_enb_o : OUT    std_logic;
+       ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+begin
+
+-- ipbus address decode
+    --i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    --i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+		
+	fabric: entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_in,
+      ipb_out => ipb_out,
+      sel => ipbus_sel_ipbus_example(ipb_in.ipb_addr),
+      ipb_to_slaves => ipbw,
+      ipb_from_slaves => ipbr
+    );
+
+-- Slave 0: id / rst reg
+
+	slave0: entity work.ipbus_ctrlreg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_CTRL_REG),
+			ipbus_out => ipbr(N_SLV_CTRL_REG),
+			d => stat,
+			q => ctrl
+		);
+		stat(0) <= X"abcdfedc";
+		soft_rst <= ctrl(0)(0);
+		nuke <= ctrl(0)(1);
+
+-- Slave 1: register
+	slave1: entity work.ipbus_reg_v
+		port map(
+			clk => ipb_clk,
+			reset => ipb_rst,
+			ipbus_in => ipbw(N_SLV_REG),
+			ipbus_out => ipbr(N_SLV_REG),
+			q => open
+		);
+
+-- Slave 2: 1kword RAM
+--	slave4: entity work.ipbus_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_RAM),
+--			ipbus_out => ipbr(N_SLV_RAM)
+--		);
+	
+-- Slave 3: peephole RAM
+--	slave5: entity work.ipbus_peephole_ram
+--		generic map(ADDR_WIDTH => 10)
+--		port map(
+--			clk => ipb_clk,
+--			reset => ipb_rst,
+--			ipbus_in => ipbw(N_SLV_PRAM),
+--			ipbus_out => ipbr(N_SLV_PRAM)
+--		);
+--    slave6 : i2c_master
+--    PORT MAP (
+--         i2c_scl_i     => i2c_scl_b,
+--         i2c_sda_i     => i2c_sda_b,
+--         ipbus_clk_i   => ipb_clk,
+--         ipbus_i       => ipbw(N_SLV_I2C),
+--         ipbus_reset_i => ipb_rst,
+--         i2c_scl_enb_o => s_i2c_scl_enb,
+--         i2c_sda_enb_o => s_i2c_sda_enb,
+--         ipbus_o       => ipbr(N_SLV_I2C)
+--    );
+
+    -- Instantiate a I2C core for the EEPROM
+    slave6 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(0),
+         i2c_sda_i     => i2c_sda_i(0),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_0),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(0),
+         i2c_sda_enb_o => i2c_sda_enb_o(0),
+         ipbus_o       => ipbr(N_SLV_I2C_0)
+    );
+    slave7 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(1),
+         i2c_sda_i     => i2c_sda_i(1),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_1),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(1),
+         i2c_sda_enb_o => i2c_sda_enb_o(1),
+         ipbus_o       => ipbr(N_SLV_I2C_1)
+    );
+    slave8 : i2c_master
+    PORT MAP (
+         i2c_scl_i     => i2c_scl_i(2),
+         i2c_sda_i     => i2c_sda_i(2),
+         ipbus_clk_i   => ipb_clk,
+         ipbus_i       => ipbw(N_SLV_I2C_2),
+         ipbus_reset_i => ipb_rst,
+         i2c_scl_enb_o => i2c_scl_enb_o(2),
+         i2c_sda_enb_o => i2c_sda_enb_o(2),
+         ipbus_o       => ipbr(N_SLV_I2C_2)
+    );
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_ver.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_ver.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..068f126f8c11346b8a47aeed7e018fb70274f6a1
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/ipbus_ver.vhd
@@ -0,0 +1,46 @@
+--=============================================================================
+--! @file  ipbus_ver.vhd
+--=============================================================================
+
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+--! @brief IPBus fixed register returning Firmware version number
+entity ipbus_ver is
+	port(
+		ipbus_in: in ipb_wbus;
+		ipbus_out: out ipb_rbus
+	);
+	
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+  ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+  ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+  ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/led_stretcher.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/led_stretcher.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c8af6c6890d6b0e50669a1527c6f09ad18ae46b4
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/led_stretcher.vhd
@@ -0,0 +1,74 @@
+-- stretcher
+--
+-- Stretches a single clock pulse so it's visible on an LED
+--
+-- Dave Newbold, January 2013
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity led_stretcher is
+	generic(
+		WIDTH: positive := 1
+	);
+	port(
+		clk: in std_logic; -- Assumed to be 125MHz ipbus clock
+		d: in std_logic_vector(WIDTH - 1 downto 0); -- Input (edge detected)
+		q: out std_logic_vector(WIDTH - 1 downto 0) -- LED output, ~250ms pulse
+	);
+
+end led_stretcher;
+
+architecture rtl of led_stretcher is
+
+	signal d17, d17_d: std_logic;
+	
+begin
+	
+	clkdiv: entity work.ipbus_clock_div
+		port map(
+			clk => clk,
+			d17 => d17
+		);
+
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			d17_d <= d17;
+		end if;
+	end process;
+	
+	lgen: for i in WIDTH - 1 downto 0 generate
+	
+		signal s, sd, e, e_d, sl: std_logic;
+		signal scnt: unsigned(6 downto 0);
+	
+	begin
+	
+		process(clk)
+		begin
+			if rising_edge(clk) then
+				s <= d(i); -- Possible clock domain crossing from slower clock (sync not important)
+				sd <= s;
+				e <= (e or (s and not sd)) and not e_d;
+				if d17 = '1' and d17_d = '0' then
+					e_d <= e;
+					if e = '1' then
+						scnt <= "0000001";
+					elsif sl = '0' then
+						scnt <= scnt + 1;
+					end if;					
+				end if;
+			end if;
+		end process;
+
+		sl <= '1' when scnt = "0000000" else '0';
+		
+		q(i) <= not sl;
+		
+	end generate;
+	
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/logic_clocks_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/logic_clocks_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..631007a5684f7176cbd027035ecfa6235abfcc21
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/logic_clocks_rtl.vhd
@@ -0,0 +1,344 @@
+--=============================================================================
+--! @file logic_clocks_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
+-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
+-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________40.000____________0.010
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock.
+--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock.
+--! Can also output clock to external clock pins.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 14:20:26 11/14/12
+--
+--! @version v0.1
+--
+--! @details
+--! \br <b> IPBus Address map:</b>
+--! \br (decode 2 bits)
+--! \li 0x00000000 - control/status register:
+--! \li             bit-0 - PLL locked ( 1 = locked )
+--! \li              bit-1 - buff-PLL locked ( 1 = locked )
+--! \li             bit-2 - use xtal for logic ( 1 = xtal , 0= external)
+--! \li             bit-3 - clock connector is an input ( 1=input , 0 = output)
+--! \li 0x00000001 - reset logic. Write to bit-zero to send reset.
+--!
+--!
+ENTITY logic_clocks IS
+    GENERIC( 
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT( 
+        ipbus_clk_i           : IN     std_logic;
+        ipbus_i               : IN     ipb_wbus;
+        ipbus_reset_i         : IN     std_logic;
+        Reset_i               : IN     std_logic;
+        clk_logic_xtal_i      : IN     std_logic;   --! 40MHz clock derived from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic;   --! 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic;   --! 160MHz clock
+        ipbus_o               : OUT    ipb_rbus;
+        strobe_8x_logic_o    : OUT    std_logic;   --! strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic;   --! one pulse every 4 cycles of clk_4x
+        DUT_clk_o             : OUT    std_logic;   --! 40MHz to DUTs
+        logic_clocks_locked_o : OUT    std_logic;   --! Goes high if clocks locked.
+        logic_reset_o         : OUT    std_logic    --! Goes high to reset counters etc. Sync with clk_4x_logic
+    );
+
+-- Declarations
+END ENTITY logic_clocks ;
+
+--
+ARCHITECTURE rtl OF logic_clocks IS
+    signal s_clk40 , s_clk40_internal : std_logic;
+    signal s_clk160 ,s_clk160_internal : std_logic;
+    signal ryanclock : std_logic;
+    signal s_clk320 , s_clk320_internal : std_logic;
+    signal s_clk40_out : std_logic;       -- Clock generated by DDR register to feed out of chip.
+    signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
+                                                             -- input from ext
+    --  signal s_logic_clk_rst : std_logic := '0';
+    signal s_locked_pll, s_locked_bufpll : std_logic;
+    
+    signal s_clk : std_logic;
+    signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
+    signal s_extclk, s_extclkG : std_logic;
+    -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic  : std_logic;
+    signal s_clkfbout_buf , s_clkfbout : std_logic;
+    
+    signal s_strobe_generator  : std_logic_vector(3 downto 0) := "1000";  -- ! Store state of ring buffer to generate strobe
+    signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100";  --! Stores state of 40MHz "clock"
+    --signal s_strobe_generator  : std_logic_vector(15 downto 0) := "1111000000000000";  -- ! Store state of ring buffer to generate strobe
+    --signal s_logic_clk_generator : std_logic_vector(15 downto 0) := "1111111100000000";  --! Stores state of 40MHz "clock"
+    signal s_strobe160 :std_logic_vector(15 downto 0) := "1000000000000000"; -- 160 strobe ring
+    signal s_strobe_fb : std_logic := '0';
+    
+    signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';  
+                                        -- ! Reset signal in IPBus clock domain
+    signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 , s_logic_reset_d4 : std_logic := '0';  
+                                        -- ! reset signal clocked onto logic-clock domain.
+    attribute SHREG_EXTRACT: string;
+    attribute SHREG_EXTRACT of s_logic_reset_d1: signal is "no"; -- Synchroniser not to be optimised into shre
+    attribute SHREG_EXTRACT of s_logic_reset_d2: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d3: signal is "no"; -- Synchroniser not to be optimised into shreg
+    attribute SHREG_EXTRACT of s_logic_reset_d4: signal is "no"; -- Synchroniser not to be optimised into shreg
+    signal s_ipbus_ack : std_logic := '0';
+    signal s_reset_pll : std_logic := '0';
+    
+    
+    -- ! Global Reset signal
+    signal  s_extclk_internal  : std_logic := '0';
+    signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range );   --! Hold status of clocks
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus write
+    -----------------------------------------------------------------------------
+    ipbus_write: process (ipbus_clk_i)
+    begin  -- process ipb_clk_i
+    if rising_edge(ipbus_clk_i) then
+        s_logic_reset_ipb <= '0';
+        if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+            case ipbus_i.ipb_addr(1 downto 0) is
+            when "00" =>
+             s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
+             
+            when "01" =>
+             s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
+            when others => null;
+            end case;
+       end if;
+
+        -- register reset signal to aid timing.
+        s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
+        s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+        -- register the clock status signals onto IPBus domain.
+        --s_clock_status_ipb <=  x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+        s_clock_status_ipb <=  x"0000000" & '0' & '0' & '0' & s_locked_pll; -- The only useful bit is not the PLL lock status. 
+    end if;
+    end process ipbus_write;
+
+    ipbus_o.ipb_ack <= s_ipbus_ack;
+    ipbus_o.ipb_err <= '0';
+
+    -----------------------------------------------------------------------------
+    -- IPBUS read
+    -----------------------------------------------------------------------------
+    with ipbus_i.ipb_addr(1 downto 0) select
+    ipbus_o.ipb_rdata <=
+        s_clock_status_ipb  when "00",
+        (others => '1')      when others;
+
+
+    -----------------------------------------------------------------------------
+    -- Generate reset signal on logic-clock domain
+    -- This relies on the IPBus clock being much slower than the 4x logic clock.
+    -----------------------------------------------------------------------------
+    p_reset: process (s_clk160_internal)
+    begin  -- process p_reset
+    if rising_edge(s_clk160_internal) then
+        s_logic_reset_d1 <= s_logic_reset_ipb_d1;
+        s_logic_reset_d2 <= s_logic_reset_d1;
+        s_logic_reset_d3 <= s_logic_reset_d2;
+        s_logic_reset_d4 <= s_logic_reset_d2 and ( not s_logic_reset_d3); 
+        s_logic_reset <= s_logic_reset_d4;
+    end if;
+    end process p_reset;
+    
+    logic_reset_o <= s_logic_reset;
+    logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+
+    -- Use Generate, since can't figure out how BUFGMUX works    
+    --  gen_extclk_input: if ( g_USE_EXTERNAL_CLK = 1) generate
+    --    s_DUT_Clk <= s_extclkG; -- Hard wire for now.    
+    --  end generate gen_extclk_input;
+    --  gen_intclk_input: if ( g_USE_EXTERNAL_CLK = 0) generate
+    s_DUT_Clk <= clk_logic_xtal_i; 
+    --  end generate gen_intclk_input;  
+  
+
+  
+    --! Clocking primitive
+    -------------------------------------
+    --! Instantiation of the PLL primitive
+    pll_base_inst : PLL_BASE
+    generic map
+       (BANDWIDTH            => "OPTIMIZED",
+        --CLK_FEEDBACK         => "CLKOUT0", --"CLKFBOUT",
+        CLK_FEEDBACK         => "CLKFBOUT",
+        COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+        DIVCLK_DIVIDE        => 1,
+        CLKFBOUT_MULT        => 16,
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE       => 2, -- 1-->2 move from 640 to 320
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => 4, -- 4-->8 move from 160 to 80
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKOUT2_DIVIDE       => 16, -- 16--> 32 move from 40 to 20
+        CLKOUT2_PHASE        => 0.000,
+        CLKOUT2_DUTY_CYCLE   => 0.500,
+        CLKIN_PERIOD         => 25.000,
+        REF_JITTER           => 0.010)
+    port map(
+        -- Output clocks
+        CLKFBOUT            => s_clkfbout,
+        CLKOUT0             => s_clk320,
+        CLKOUT1             => s_clk160,
+        CLKOUT2             => s_clk40,
+        CLKOUT3             => open,
+        CLKOUT4             => open,
+        CLKOUT5             => open,
+        -- Status and control signals
+        LOCKED              => s_locked_pll,
+        --    RST                 => s_logic_clk_rst,
+        RST                 => s_reset_pll,
+        -- Input clock control
+        --    CLKFBIN             => s_clkfbout_buf,
+        CLKFBIN             => s_clkfbout,
+        CLKIN               => s_DUT_clk);
+        --      CLKIN               => clk_logic_xtal_i);
+
+    s_reset_pll <= Reset_i or s_logic_reset; 
+
+-----------------------------------------------
+--BUFPLL not supported by 7 Series. We need to replace it with BUFIO+BUFR 
+  -- Buffer the 16x clock and generate the ISERDES strobe signal
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK  => s_clk640_internal,          -- 1-bit output: Output I/O clock
+--      LOCK   => s_locked_bufpll,            -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => strobe_16x_logic_O,   -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK   => s_clk160_internal,          -- 1-bit input: BUFG clock input
+--      LOCKED => s_locked_pll,               -- 1-bit input: LOCKED input from PLL
+--      PLLIN  => s_clk640                    -- 1-bit input: Clock input from PLL
+--   );
+
+    BUFG_inst: BUFG
+    port map (
+        I => s_clk320,
+        O => s_clk320_internal    
+    );
+    
+--    BUFR_inst: BUFR
+--    generic map (
+--        BUFR_DIVIDE => "4"
+--    )
+--    port map (
+--        I   => s_clk160_internal,
+--        CE  => '1',
+--        CLR => '0',
+--        O   => ryanclock
+--    );
+    
+--    BUFG_inst2: BUFG
+--    port map (
+--        I => ryanclock,
+--        O => strobe_16x_logic_O    -- Not sure this is actually a strobe... Check
+--    );
+-----------------------------------------------
+
+	clk_8x_logic_o <= s_clk320_internal;
+	DUT_clk_o <= s_DUT_clk;
+
+
+  
+  -- Generate a strobe signal every 4 clocks. 
+  -- Can't use a clock signal as a combinatorial signal. Hence the baroque
+  -- method of generating a strobe. Add a mechanism to restart if the '1' gets
+  -- lost ....
+    
+    ------------------
+    generate_4x_strobe: process (s_clk160_internal)-- , s_clk40_out)
+    begin  -- process generate_4x_strobe
+    if rising_edge(s_clk160_internal) then
+        if s_logic_reset = '1' then
+            s_strobe_generator <= "1000";
+            s_logic_clk_generator <= "1100";
+            --s_strobe160 <= "1000000000000000";
+        elsif (s_locked_pll ='1') then
+            s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3); -- <- bit shift left      
+            s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3); -- <- bit shift left 
+            --s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+        end if;
+    end if;
+    end process generate_4x_strobe;
+    strobe_4x_logic_o <=  s_strobe_generator(3); -- Every 4 clocks this gets to 1 for one pulse
+    s_clk40_out <= s_logic_clk_generator(3); -- Every 4 clocks this gets to 1 for two pulses (so half F of the original clock? But then it is a clk80 not clk40.) Not used it seems.
+    ---------------
+    
+    generate_8x_strobe: process (s_clk320_internal)
+    begin
+    if rising_edge(s_clk320_internal) then
+        if s_logic_reset = '1' then
+            s_strobe160 <= "1000000000000000"; 
+            --s_strobe_generator <= "1111000000000000";--
+            --s_logic_clk_generator <= "1111111100000000";--
+        elsif (s_locked_pll ='1') then
+            s_strobe160 <= s_strobe160(14 downto 0) & s_strobe160(15);
+            --s_strobe_generator <= s_strobe_generator(14 downto 0) & s_strobe_generator(15); --       
+            --s_logic_clk_generator <= s_logic_clk_generator(14 downto 0) & s_logic_clk_generator(15); -- <- bit shift left
+        end if;
+    end if;
+    end process generate_8x_strobe;
+    strobe_8x_logic_O <= s_strobe160(15);
+    --strobe_4x_logic_o <=  s_strobe_generator(15); -- 
+    --s_clk40_out <= s_logic_clk_generator(15); -- 
+        
+
+  -- buffer 160MHz (4x) clock
+  --------------------------------------
+    clk160_o_buf : BUFG
+    port map(
+        O   => s_clk160_internal,
+        I   => s_clk160);
+    
+    clk_4x_logic_o <= s_clk160_internal;
+ 
+--   -- buffer 40MHz (1x) clock
+--  --------------------------------------
+--  clk40_o_buf : BUFG
+--  port map(
+--    O   => s_clk40_internal,
+--    I   => s_clk40);
+
+--  clk_logic_o <= s_clk40_out;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/pulseClockDomainCrossing_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/pulseClockDomainCrossing_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..663cac3b9e4476ee3146730afc6efc5d79225de3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/pulseClockDomainCrossing_rtl.vhd
@@ -0,0 +1,100 @@
+--=============================================================================
+--! @file pulseClockDomainCrossing_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
+--
+--! @brief Takes a pulse synchronized with one clock and produces a
+--! pulse synchronized to another clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date September/2012
+--
+--! @version v0.1
+--
+--! @details A "ring" of D-type flip-flops is used to transfer a strobe
+--! from the input clock domain to the output clock domain and then back again.
+--! The time taken to transit from input to output is approximately
+--! two clock cycles of clock_output_i .
+--! After an additional two cycles of clk_input_i another pulse can be sent
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulseClockDomainCrossing is
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    pulse_i     : in std_logic;         --! input pulse. Active high
+    clk_output_i: in std_logic;         --! clock for output
+    pulse_o     : out std_logic         --! Single cycle pulse synchronized to clock_output_i
+    );
+
+end pulseClockDomainCrossing;
+
+architecture rtl of pulseClockDomainCrossing is
+
+  signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
+  
+begin  -- rtl
+
+  -- purpose: registers and flip-flop on clk_input_i
+  p_input_clock_logic: process (clk_input_i)
+  begin  
+    if rising_edge(clk_input_i) then
+
+      -- Register signals coming from output clock domain back to the
+      -- input clock domain
+      s_pulse_back_d1 <= s_pulse_out_d2;
+      s_pulse_back_d2 <= s_pulse_back_d1;
+
+      -- JK flip-flop
+      if (s_pulse_back_d2 = '1')  then
+        s_pulse_out <= '0';
+      elsif (pulse_i = '1')  then
+        s_pulse_out <= '1';
+      end if;
+
+    end if;
+  end process p_input_clock_logic;
+
+  -- purpose: registers and flip-flop on clk_output_o
+  p_output_clock_logic: process (clk_output_i)
+  begin  
+    if rising_edge(clk_output_i) then
+
+      -- Register signal on input clock domain onto output clock domain
+      s_pulse_out_d1 <= s_pulse_out;
+      s_pulse_out_d2 <= s_pulse_out_d1;
+
+      s_pulse_out_d3 <= s_pulse_out_d2;
+      s_pulse_out_d4 <= s_pulse_out_d3;
+
+      -- Generate single clock-cycle pulse on pulse_o
+      pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
+
+    end if;
+  end process p_output_clock_logic;
+
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/registerCounter_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/registerCounter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de5587cd9ab98905a3da88d0eb2cd5a3c8a279ee
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/registerCounter_rtl.vhd
@@ -0,0 +1,113 @@
+--=============================================================================
+--! @file registerCounter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.registerCounter.rtl
+--
+--! @brief Regularly transfers the input to the output.\n
+--! One clock for input , one clock for output\n
+--! Can't just put entire bus through a couple of register stages,\n
+--! Since this will just swap meta-stability issues for race issues.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 24/Nov/12
+--
+--! @version v0.1
+--
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! We could use gray-scale and put through registers, but this method
+--! should work well enough at the expense of latency.\n
+--! \n
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity registerCounter is
+  
+  generic (
+    g_DATA_WIDTH : positive := 15);     -- ! Width of counter
+
+  port (
+    clk_input_i : in std_logic;         -- ! clock for input
+    data_i      : in std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! data to transfer to output
+    data_o     : out std_logic_vector(g_DATA_WIDTH-1 downto 0);  -- ! Data now in clk_read_i domain
+    clk_output_i  : in std_logic);        -- ! clock for output
+
+end registerCounter;
+
+architecture rtl of registerCounter is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0');  -- ! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  -- ! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2;  --! Generate a strobe with
+                                                --width one clk_read_i
+  
+  -- purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5;  --! Generate a strobe
+                                                  --
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/serdes_1_to_n_SDR.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/serdes_1_to_n_SDR.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0a119e3cb6fd53afcdc50779d0affc9703b57ce
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/serdes_1_to_n_SDR.vhd
@@ -0,0 +1,235 @@
+------------------------------------------------------------------------------/
+-- Copyright (c) 2009 Xilinx, Inc.
+-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
+------------------------------------------------------------------------------/
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor: Xilinx
+-- \   \   \/    Version: 1.0
+--  \   \        Filename: top_nto1_ddr_diff_rx.vhd
+--  /   /        Date Last Modified:  November 5 2009
+-- /___/   /\    Date Created: June 1 2009
+-- \   \  /  \
+--  \___\/\___\
+-- 
+--Device:   Spartan 6
+--Purpose:    Example differential input receiver for DDR clock and data using 2 x BUFIO2
+--    Serdes factor and number of data lines are set by constants in the code
+--Reference:
+--    
+--Revision History:
+--    Rev 1.0 - First created (nicks)
+--
+------------------------------------------------------------------------------/
+--
+--  Disclaimer: 
+--
+--    This disclaimer is not a license and does not grant any rights to the materials 
+--              distributed herewith. Except as otherwise provided in a valid license issued to you 
+--              by Xilinx, and to the maximum extent permitted by applicable law: 
+--              (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, 
+--              AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, 
+--              INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR 
+--              FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract 
+--              or tort, including negligence, or under any other theory of liability) for any loss or damage 
+--              of any kind or nature related to, arising under or in connection with these materials, 
+--              including for any direct, or any indirect, special, incidental, or consequential loss 
+--              or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered 
+--              as a result of any action brought by a third party) even if such damage or loss was 
+--              reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+--
+--  Critical Applications:
+--
+--    Xilinx products are not designed or intended to be fail-safe, or for use in any application 
+--    requiring fail-safe performance, such as life-support or safety devices or systems, 
+--    Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+--    or any other applications that could lead to death, personal injury, or severe property or 
+--    environmental damage (individually and collectively, "Critical Applications"). Customer assumes 
+--    the sole risk and liability of any use of Xilinx products in Critical Applications, subject only 
+--    to applicable laws and signalulations governing limitations on product liability.
+--
+--  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Serdes 1 to n SDR
+--! @author Alvaro Dosil
+-------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all ;
+
+library unisim ;
+use unisim.vcomponents.all ;
+
+entity serdes_1_to_n_SDR is 
+generic ( g_S : integer := 4);       --! Parameter to set the serdes factor 1..8
+port( clk_i  : in std_logic;         --! Fast clock to sample data (640MHz)
+      hclk_i   : in std_logic;       --! A quarter frequency clock (160MHz)
+      reset_i  : in std_logic;       --! reset signal
+      Data_i   : in std_logic;       --! 1-Bit Input data
+      strobe_i : in std_logic;       --! Iserdes strobe_i
+      Data_o   : out std_logic_vector(2*g_S-1 downto 0)  --! data output
+		);
+    
+end serdes_1_to_n_SDR;
+
+
+architecture Behavioral of serdes_1_to_n_SDR is
+
+signal s_Data_i_d_m  : std_logic;     -- Data_i delayed master
+signal s_Data_i_d_2m : std_logic;     -- Data_i delayed master second signal
+signal s_Data_i_d_s  : std_logic;     -- Data_i delayed slave
+signal s_Data_i_d_2s : std_logic;     -- Data_i delayed slave second signal
+signal s_Data_o      : std_logic_vector(2*g_S-1 downto 0);
+
+--signal s_clk_b       : std_logic;
+--signal s_ISERDES_STROBE : std_logic;
+
+begin
+	
+---- Generate the ISERDES strobe signal
+--
+--   BUFPLL_inst : BUFPLL
+--   generic map (
+--      DIVIDE => 4)
+--   port map (
+--      IOCLK => s_clk_b,                -- 1-bit output: Output I/O clock
+--      LOCK => open,                     -- 1-bit output: Synchronized LOCK output
+--      SERDESSTROBE => s_ISERDES_STROBE, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+--      GCLK => hclk_i,                     -- 1-bit input: BUFG clock input
+--      LOCKED => locked_pll_i,                  -- 1-bit input: LOCKED input from PLL
+--      PLLIN => clk_i                -- 1-bit input: Clock input from PLL
+--   );
+	
+
+  IODELAY2_M : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",     -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",         -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",          -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE     => 0,                -- Amount of taps for fixed input delay (0-255)
+    IDELAY2_VALUE    => 0,                -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE     => 0,                -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE      => "NONE"            -- "NONE", "MASTER" or "SLAVE" 
+--    SIM_TAPDELAY_VALUE=> 43                -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,          -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_m,     -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2m,    -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,          -- 1-bit output: Delayed data output
+    TOUT     => open,          -- 1-bit output: Delayed 3-state output
+    CAL      => '0',           -- 1-bit input: Initiate calibration input
+    CE       => '0',           -- 1-bit input: Enable INC input
+    CLK      => '0',           -- 1-bit input: Clock input
+    IDATAIN  => Data_i,        -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',           -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',           -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',           -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',           -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,         -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'            -- 1-bit input: 3-state input signal
+   );
+
+
+  IODELAY2_S : IODELAY2
+  generic map (
+    COUNTER_WRAPAROUND => "WRAPAROUND",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+    DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+    DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+    IDELAY_MODE        => "NORMAL",      -- "NORMAL" or "PCI" 
+    IDELAY_TYPE        => "FIXED",       -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" 
+                              --  or "DIFF_PHASE_DETECTOR" 
+    IDELAY_VALUE       => 10,--29,            -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
+    IDELAY2_VALUE      => 0,             -- Delay value when IDELAY_MODE="PCI" (0-255)
+    ODELAY_VALUE       => 0,             -- Amount of taps fixed output delay (0-255)
+    SERDES_MODE        => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+    --SIM_TAPDELAY_VALUE => 43              -- Per tap delay used for simulation in ps
+   )
+  port map (
+    BUSY     => open,             -- 1-bit output: Busy output after CAL
+    DATAOUT  => s_Data_i_d_s,        -- 1-bit output: Delayed data output to ISERDES/input register
+    DATAOUT2 => s_Data_i_d_2s,       -- 1-bit output: Delayed data output to general FPGA fabric
+    DOUT     => open,             -- 1-bit output: Delayed data output
+    TOUT     => open,             -- 1-bit output: Delayed 3-state output
+    CAL      => '0',              -- 1-bit input: Initiate calibration input
+    CE       => '0',              -- 1-bit input: Enable INC input
+    CLK      => '0',              -- 1-bit input: Clock input
+    IDATAIN  => Data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+    INC      => '0',              -- 1-bit input: Increment / decrement input
+    IOCLK0   => '0',              -- 1-bit input: Input from the I/O clock network
+    IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+    ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+    RST      => reset_i,            -- 1-bit input: reset_i to zero or 1/2 of total delay period
+    T        => '0'               -- 1-bit input: 3-state input signal
+   );
+
+
+  ISERDES2_M : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(1),
+    Q2     => s_Data_o(3),
+    Q3     => s_Data_o(5),
+    Q4     => s_Data_o(7), 
+    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,                 -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+    CE0     => '1',                  -- 1-bit input Clock enable input
+	 CLK0    => clk_i,                -- 1-bit input I/O clock network input
+    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,               -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_m,         -- 1-bit input Input data
+    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+  ISERDES2_S : ISERDES2
+  generic map (
+    BITSLIP_ENABLE => FALSE,          -- Enable Bitslip Functionality (TRUE/FALSE)
+    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+    DATA_WIDTH     => g_S,             -- Parallel data width selection (2-8)
+    INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+    SERDES_MODE    => "NONE"          -- "NONE", "MASTER" or "SLAVE" 
+   )
+  port map (
+    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+    Q1     => s_Data_o(0),
+    Q2     => s_Data_o(2),
+    Q3     => s_Data_o(4),
+    Q4     => s_Data_o(6),
+    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+    VALID   => open,               -- 1-bit output Output status of the phase detector
+    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+    CE0     => '1',                -- 1-bit input Clock enable input
+	 CLK0    => clk_i,              -- 1-bit input I/O clock network input
+    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+    CLKDIV  => hclk_i,             -- 1-bit input FPGA logic domain clock input
+    D       => s_Data_i_d_s,       -- 1-bit input Input data
+    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+   );
+
+reg_out : process(hclk_i)
+begin
+  if rising_edge(hclk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/single_pulse_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/single_pulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e5da6214a380987ce7b7f9d4969ead408ebbafee
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/single_pulse_rtl.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--! @file
+-------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-------------------------------------------------------------------------------
+--
+-- VHDL for producing a single clock low-high-low pulse on the rising edge
+-- of input signal (LEVEL)
+--
+-- David Cussans, Ocala, April 2005
+--
+-- LEVEL (input) - when LEVEL goes high, PULSE goes high for one clock cycle
+--               - on next rising edge of CLK
+-- CLK (input)   - rising edge active
+-- PULSE         - changes on rising edge of clk
+--
+--! @brief gives a single cycle pulse ( high active) following the rising edge of LEVEL
+
+entity single_pulse is
+  generic (
+    g_PRE_REGISTER  : boolean := false;  -- --! Set true to put a register before rising edge detect
+    g_POST_REGISTER : boolean := false);  -- --! Set tru to put a register after rising edge detect
+  port (
+    level : in  std_logic; --! When LEVEL goes high, PULSE goes high for one clock cycle
+    clk : in  std_logic; --! rising edge active
+    pulse : out  std_logic              --! Pulses high for one cycle
+    );
+end entity single_pulse;
+
+architecture rtl of single_pulse is
+
+  signal pre_level, pre_pulse , x, v : std_logic;
+  
+begin  -- architecture rtl
+
+  -----------------------------------------------
+  -- Optional register on input
+  -----------------------------------------------
+  gen_pre_ff: if g_PRE_REGISTER=true generate
+    ffpre: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pre_level <= level;
+      end if;
+    end process ffpre;
+  end generate gen_pre_ff;
+
+  gen_no_pre_ff: if g_PRE_REGISTER=false generate
+    pre_level <= level;
+  end generate gen_no_pre_ff;
+
+  -----------------------------------------------
+  -- Register signal
+  -----------------------------------------------  
+  ff1: process (clk , level) is
+  begin  -- process ff1
+    if rising_edge(clk) then
+      x <= pre_level;
+    end if;
+  end process ff1;
+
+  -----------------------------------------------
+  -- Edge detection logic
+  -----------------------------------------------  
+  ff2: process (clk , x) is
+  begin  -- process ff2
+    if rising_edge(clk) then
+      v <= not x;
+    end if;
+  end process ff2;                           
+                           
+  pre_pulse <= ( x and v );
+
+
+  -----------------------------------------------
+  -- Optional register on output
+  -----------------------------------------------
+  gen_post_ff: if g_POST_REGISTER=true generate
+    ffpost: process (clk , level) is
+    begin  -- process ff1
+      if rising_edge(clk) then
+        pulse <= pre_pulse;
+      end if;
+    end process ffpost;
+  end generate gen_post_ff;
+
+  gen_no_post_ff: if g_POST_REGISTER=false generate
+    pulse <= pre_pulse;
+  end generate gen_no_post_ff;
+  
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/stretchPulse_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/stretchPulse_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..957a4c6d4164aa9b2b58dea19e86a068aa8f84de
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/stretchPulse_rtl.vhd
@@ -0,0 +1,92 @@
+--=============================================================================
+--! @file stretchPulse_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+--! @brief Takes a pulse on input, stretches it and delays it.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! Definition of trigger time
+USE work.fmcTLU.all;                    
+
+entity stretchPulse is
+  
+  generic (
+    g_PARAM_WIDTH : positive := 5);  --! number of bits in parameters (width,  delay)
+
+  port (
+    clk_i        : in  std_logic;       --! Active high
+    pulse_i      : in  std_logic;       --! Active high
+    pulse_o      : out std_logic;       --! delayed and stretched
+    triggerTime_i : in t_triggerTime;   --! 5-bit time
+    triggerTime_o : out t_triggerTime;  --! Delayed by same amount as pulse
+    
+    pulseWidth_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0);  --! Minimum pulse width ( in clock cycles )
+    pulseDelay_i : in  std_logic_vector(g_PARAM_WIDTH-1 downto 0) --! Delay is pulseDelay_i +1 clock cycles
+    );      
+
+end entity stretchPulse;
+
+-- For now just delay the pulse.
+architecture rtl of stretchPulse is
+
+  signal s_delaySR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate delay
+  signal s_stretchSR : std_logic_vector( (2**g_PARAM_WIDTH) -1 downto 0) := ( others => '0' );  -- --! Shift register to generate stretch
+  signal s_delayedPulse : std_logic := '0';  -- delayed pulse before stretch
+
+  signal s_triggerTimeSR : t_triggerTimeArray ( (2**g_PARAM_WIDTH)-1 downto 0) := ( others => ( others => '0'));  -- array of trigger times
+  signal s_triggerTime_d1 : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  signal s_stretchedTriggerTime : t_triggerTime := ( others => '0');  -- shim out by one more clock cycle...
+  
+begin  -- architecture rtl
+
+  
+  --! Delay pulse
+  p_delayPulse: process (clk_i , pulse_i) is
+  begin  -- process p_delayPulse
+    if rising_edge(clk_i) then
+      s_delaySR <= s_delaySR( (s_delaySR'left -1) downto 0 ) & pulse_i;
+      s_delayedPulse <= s_delaySR( to_integer(unsigned(pulseDelay_i)) );
+
+      -- delay the trigger time to match trigger delay
+      s_triggerTimeSR <=  s_triggerTimeSR( (s_triggerTimeSR'left -1)  downto 0 ) & triggerTime_i;
+      s_triggerTime_d1 <=  s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) ); 
+--      triggerTime_o <= s_triggerTime_d1 ;
+      
+    end if;
+  end process p_delayPulse;
+
+  --! Stretch pulse. the output pulse is always at least as long as the input pulse
+  p_stretchPulse: process (clk_i , pulse_i) is
+  begin  -- process p_stretchPulse
+    if rising_edge(clk_i) then
+      if s_delayedPulse = '1' then
+        s_stretchSR <= ( others => '1' ) ;
+        pulse_o <= s_delayedPulse ;
+      else
+        s_stretchSR <= s_stretchSR( (s_stretchSR'left -1) downto 0 ) & '0';
+        pulse_o <= s_stretchSR( to_integer(unsigned(pulseWidth_i)) );
+      end if;
+
+      if s_stretchSR( to_integer(unsigned(pulseWidth_i)) ) = '0' then
+        --s_stretchedTriggerTime <= s_triggerTimeSR( to_integer(unsigned(pulseDelay_i)) );
+        triggerTime_o <= s_triggerTime_d1;
+      end if;
+      --triggerTime_o <= s_stretchedTriggerTime ;
+      
+    end if;
+  end process p_stretchPulse;
+
+end architecture rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/sychronizedIPBusCtrlRegV_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/sychronizedIPBusCtrlRegV_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e1d751261317129227224e221add93ff745a83e
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/sychronizedIPBusCtrlRegV_rtl.vhd
@@ -0,0 +1,83 @@
+--=============================================================================
+--! @file 
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+--! @brief IPBus registers synchronzied onto logic clock
+--!
+--! @details Uses DMN ipbus_ctrlreg_v - originally tried to use
+--! ipbus_ctrlreg_sync, but had poor results and added own synchronzier.
+
+entity synchronizedIPBusCtrlRegV_rtl is
+	generic(
+		N_CTRL: positive := 1;
+		N_STAT: positive := 1
+	);
+	port(
+		ipbus_clk_i: in std_logic;
+		ipbus_reset_i: in std_logic;
+		ipbus_i: in ipb_wbus;
+		ipbus_o: out ipb_rbus;
+                logic_clk_i: in std_logic;
+		status_to_ipbus_i: in ipb_reg_v(N_STAT - 1 downto 0); --! Synchronized to logic_clk_i       
+		sync_control_from_ipbus_o: out ipb_reg_v(N_CTRL - 1 downto 0); --! Synchronized to logic_clk_i
+		stb_o: out std_logic_vector(N_CTRL - 1 downto 0) --! high when change made to a control register. Broken ( needs to be retimed )
+	);
+	
+end synchronizedIPBusCtrlRegV_rtl;
+
+
+architecture rtl of synchronizedIPBusCtrlRegV_rtl is
+
+  signal s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus   : ipb_reg_v(c_N_CTRL-1 downto 0);
+ 
+begin  -- architecture rtl
+
+  
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  stb_o
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  status_to_ipbus_i,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => sync_control_from_ipbus_o,
+      clk_output_i => clk_4x_logic_i);
+
+end architecture rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/sync_reg.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/sync_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e88eb54b67be346b7398099036524bcd023f6c9d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/sync_reg.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+-- 
+-- Create Date:    15/08/2012 
+-- Module Name:    Conf_Regs - Behavioral 
+-- Revision 1.00 - File Created
+-- Additional Comments: 
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 32b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity sync_reg is
+  generic(g_Data_width : positive := 32);
+  port(
+    clk_i : in std_logic;  --! synchronous clock
+    Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
+	 Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
+  
+end sync_reg;
+
+--! @brief
+--! @details Synchronize words (n bits)of data 
+
+architecture Behavioral of sync_reg is
+
+signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
+signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
+begin
+  
+loop0: for i in 0 to g_Data_width-1 generate
+  begin
+  reg: entity work.Reg_2clks
+    port map(
+	   clk_i => clk_i,
+		async_i => s_async_i(i),
+		sync_o => s_sync_o(i));
+  end generate;
+ 
+s_async_i <= Async_i; 
+Sync_o <= s_sync_o;
+
+end Behavioral;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_fifo.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_fifo.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ebae77b4608297df1d02232d5891e1c0aa2cd7a9
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_fifo.vhd
@@ -0,0 +1,110 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+
+
+entity synchronizeRegisters_fifo is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters_fifo;
+
+architecture rtl of synchronizeRegisters_fifo is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+  COMPONENT sync_fifo
+    PORT (
+      rst : IN STD_LOGIC;
+      wr_clk : IN STD_LOGIC;
+      rd_clk : IN STD_LOGIC;
+      din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_en : IN STD_LOGIC;
+      rd_en : IN STD_LOGIC;
+      dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      full : OUT STD_LOGIC;
+      empty : OUT STD_LOGIC
+    );
+  END COMPONENT;
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  gen_syncReg: for v_reg in 0 to g_NUM_REGISTERS-1 generate
+      mySynchReg : sync_fifo
+        PORT MAP (
+          rst => '0',
+          wr_clk => clk_input_i,
+          rd_clk => clk_output_i,
+          din => data_i(v_reg),
+          wr_en => '1',
+          rd_en => '1',
+          dout => data_o(v_reg),
+          full => open,
+          empty => open
+        );
+  end generate gen_syncReg;
+  
+--  p_gen_capture_strobe: process (clk_input_i)
+--  begin  -- process p_gen_capture_strobe
+--    if rising_edge(clk_input_i) then
+--      s_ring_d0 <= not s_ring_d5;
+--      s_ring_d1 <= s_ring_d0;
+--      s_ring_d2 <= s_ring_d1;
+
+--      if s_read_strobe = '1' then
+--        s_registered_data <= data_i;
+--      end if;
+--    end if;    
+--  end process p_gen_capture_strobe;
+
+--  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+--  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+--  -- type   : combinational
+--  -- inputs : clk_output_i
+--  -- outputs: 
+--  p_gen_output_strobe: process (clk_output_i)
+--  begin  -- process p_gen_output_strobe
+--    if rising_edge(clk_output_i) then
+--      s_ring_d3 <= s_ring_d2;
+--      s_ring_d4 <= s_ring_d3;
+--      s_ring_d5 <= s_ring_d4;
+
+--      if s_write_strobe = '1' then
+--        data_o <= s_registered_data;
+--      end if;
+--    end if;    
+--  end process p_gen_output_strobe;
+
+--  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bb7d59a7e8d748cb160690d37e4e2225ffaf9e5a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/synchronizeRegisters_rtl.vhd
@@ -0,0 +1,103 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.ipbus_reg_types.all;
+
+--! @brief Regularly transfers the input to the output.
+--! One clock for input , one clock for output
+--! Can't just put entire bus through a couple of register stages,
+--! Since this will just swap meta-stability issues for race issues.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 24/Nov/12
+--!
+--! @version v0.1
+--!
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--! Based on registerCounters
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+
+entity synchronizeRegisters is
+  
+  generic (
+    --g_DATA_WIDTH : positive := 15;
+    g_NUM_REGISTERS : positive := 1);     --! Number of registers to synchronize
+
+  port (
+    clk_input_i : in std_logic;         --! clock for input
+    data_i      : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! array of registers to transfer to output
+    data_o     : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0);  --! Data now in clk_output_i domain
+    clk_output_i  : in std_logic);        --! clock for output
+
+end synchronizeRegisters;
+
+architecture rtl of synchronizeRegisters is
+  signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0';  -- stages in "ring oscillator" used to generate strobes
+  signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0'));  --! Register to store data between clock domains
+
+  signal s_read_strobe , s_write_strobe : std_logic := '0';  --! Strobes high to register data from input and to output
+  
+begin  -- rtl
+
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_read_i
+  -- outputs: 
+  p_gen_capture_strobe: process (clk_input_i)
+  begin  -- process p_gen_capture_strobe
+    if rising_edge(clk_input_i) then
+      s_ring_d0 <= not s_ring_d5;
+      s_ring_d1 <= s_ring_d0;
+      s_ring_d2 <= s_ring_d1;
+
+      if s_read_strobe = '1' then
+        s_registered_data <= data_i;
+      end if;
+    end if;    
+  end process p_gen_capture_strobe;
+
+  s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe (with width one clk_read_i) that captures data at input
+  
+  --! purpose: part of "ring oscillator" transfering strobe between clock domains
+  -- type   : combinational
+  -- inputs : clk_output_i
+  -- outputs: 
+  p_gen_output_strobe: process (clk_output_i)
+  begin  -- process p_gen_output_strobe
+    if rising_edge(clk_output_i) then
+      s_ring_d3 <= s_ring_d2;
+      s_ring_d4 <= s_ring_d3;
+      s_ring_d5 <= s_ring_d4;
+
+      if s_write_strobe = '1' then
+        data_o <= s_registered_data;
+      end if;
+    end if;    
+  end process p_gen_output_strobe;
+
+  s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate the strobe that causes data to be written to output
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/test_inToOut.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/test_inToOut.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..91b60eec700141731d07a95e72c903a597e4e6ef
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/test_inToOut.vhd
@@ -0,0 +1,106 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 14:45:31
+-- Design Name: 
+-- Module Name: test_inToOut - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inToOut is
+    Generic(
+        DUT_TOGGLE : integer  :=1; --HDMI that toggles
+        DUT_OUT : integer := 2; --HDMI used as input
+        DUT_IN : integer := 0; --HDMI used as output
+        DUT_DULL : integer := 3 --HDMI not used
+    );
+    Port ( clk_in : in STD_LOGIC;
+           busy_in : in STD_LOGIC_VECTOR (3 downto 0);
+           control_in : in STD_LOGIC_VECTOR (3 downto 0);
+           trig_in : in STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_in : in STD_LOGIC_VECTOR (3 downto 0);
+           spare_in : in STD_LOGIC_VECTOR (3 downto 0);
+           busy_out : out STD_LOGIC_VECTOR (3 downto 0);
+           control_out : out STD_LOGIC_VECTOR (3 downto 0);
+           trig_out : out STD_LOGIC_VECTOR (3 downto 0);
+           clkDut_out : out STD_LOGIC_VECTOR (3 downto 0);
+           spare_out : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inToOut;
+
+architecture Behavioral of test_inToOut is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(4 downto 0);
+    signal clk_slow_i : std_logic_vector(4 downto 0);
+    signal placeholder: std_logic_vector(4 downto 0);
+
+begin
+
+    gen_clk : process (clk_in)
+    begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+        clk_slow_i(4) <= outcounter(4);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+      
+      clkDut_out(DUT_TOGGLE) <= clk_slow_i(0);
+      busy_out(DUT_TOGGLE) <= clk_slow_i(1);
+      control_out(DUT_TOGGLE) <= clk_slow_i(2);
+      trig_out(DUT_TOGGLE) <= clk_slow_i(3);
+      spare_out(DUT_TOGGLE) <= clk_slow_i(4);
+  
+      clkDut_out(DUT_OUT) <= clkDut_in(DUT_IN);
+      busy_out(DUT_OUT) <= busy_in(DUT_IN);
+      control_out(DUT_OUT) <= control_in(DUT_IN);
+      trig_out(DUT_OUT) <= trig_in(DUT_IN);
+      spare_out(DUT_OUT) <= spare_in(DUT_IN);
+      
+      clkDut_out(DUT_DULL) <= '0';
+      busy_out(DUT_DULL) <= '0';
+      control_out(DUT_DULL) <= '0';
+      trig_out(DUT_DULL) <= '0';
+      spare_out(DUT_DULL) <= '0';
+    end if;
+    end process gen_clk;
+    
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/test_inputToOutput.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/test_inputToOutput.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b8cbb1d914de2e1c84d446bd3236885b24f318fc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/test_inputToOutput.vhd
@@ -0,0 +1,53 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09.02.2017 12:54:36
+-- Design Name: 
+-- Module Name: test_inputToOutput - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity test_inputToOutput is
+    Port ( clk_i : in STD_LOGIC;
+           test_i : in STD_LOGIC_VECTOR (3 downto 0);
+           test_o : out STD_LOGIC_VECTOR (3 downto 0));
+end test_inputToOutput;
+
+architecture Behavioral of test_inputToOutput is
+    signal synch_lines : std_logic_vector(3 downto 0);
+begin
+    synch_io : process (clk_i)
+    begin
+        if rising_edge(clk_i) then
+            synch_lines <= test_i;
+            test_o(1) <= synch_lines(0);
+            test_o(3) <= synch_lines(2);
+            test_o(0) <= '0';
+            test_o(2) <= '1';
+        end if;
+    end process synch_io;
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/test_toggleLines.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/test_toggleLines.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed585cdb02aabf04b00bff39d8962d0c7a571b74
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/test_toggleLines.vhd
@@ -0,0 +1,70 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 06.02.2017 10:09:26
+-- Design Name: 
+-- Module Name: test_toggleLines - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity test_toggleLines is
+    Port (
+        clk_in : in STD_LOGIC;
+        toggle_o : out std_logic_vector(3 downto 0)
+        );
+end test_toggleLines;
+
+architecture Behavioral of test_toggleLines is
+
+    signal prescaler : unsigned(23 downto 0);
+    signal outcounter: unsigned(3 downto 0);
+    signal clk_slow_i : std_logic_vector(3 downto 0);
+    
+begin
+
+  gen_clk : process (clk_in)
+  begin  -- process gen_clk
+    if rising_edge(clk_in) then   -- rising clock edge
+      if prescaler = X"30D40" then     -- 200 000 in hex
+        prescaler   <= (others => '0');
+        --clk_slow_i   <= not clk_slow_i;
+        outcounter <= outcounter +1;
+        clk_slow_i(0) <= outcounter(0);
+        clk_slow_i(1) <= outcounter(1);
+        clk_slow_i(2) <= outcounter(2);
+        clk_slow_i(3) <= outcounter(3);
+      else
+        prescaler <= prescaler + "1";
+      end if;
+    end if;
+  end process gen_clk;
+
+  toggle_o <= clk_slow_i;
+
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_clocks.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_clocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..052b220c4e4e5e7b7d354731525a4e935a289d6f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_clocks.vhd
@@ -0,0 +1,43 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:26:56
+-- Design Name: 
+-- Module Name: testbench_clocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity testbench_clocks is
+--  Port ( );
+end testbench_clocks;
+
+architecture Behavioral of testbench_clocks is
+
+begin
+
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_myclocks.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_myclocks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c17c7db550bad4f2ee74c868331b64ae7a9cd80b
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/testbench_myclocks.vhd
@@ -0,0 +1,99 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 17.02.2017 11:31:53
+-- Design Name: 
+-- Module Name: testbench_myclocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+
+entity testbench_myclocks is
+end testbench_myclocks;
+
+architecture Behavioral of testbench_myclocks is
+
+ COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    SIGNAL sysclk_40         : std_logic := '0';
+    SIGNAL clk_8x_logic         : std_logic := '0';
+    SIGNAL clk_4x_logic         : std_logic := '0';
+    SIGNAL strobe_8x_logic         : std_logic := '0';
+    SIGNAL strobe_4x_logic         : std_logic := '0';
+    SIGNAL logic_reset         : std_logic := '0';
+    signal ipbus_i_const             : ipb_wbus;
+
+
+begin
+    
+      ipbus_i_const.ipb_strobe <= '0';
+      ipbus_i_const.ipb_write <= '0';
+      ipbus_i_const.ipb_wdata <= (others => '0');
+    
+        I3_Clocks : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => '0',
+        ipbus_i               => ipbus_i_const,
+        ipbus_reset_i         => '0',
+        Reset_i               => '0',
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => open,
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => open,
+        logic_reset_o         => logic_reset
+    );  
+
+end Behavioral;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_ax3_pm3.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_ax3_pm3.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..589be2f2d67563dad293f528c9c23c1589e4927a
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_ax3_pm3.vhd
@@ -0,0 +1,173 @@
+-- Top-level design for ipbus demo
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top is
+    generic(
+    g_NUM_DUTS  : positive := 3;
+    g_NUM_TRIG_INPUTS   :positive := 4;
+    g_NUM_EXT_SLAVES    :positive :=8;
+    g_EVENT_DATA_WIDTH  :positive := 64;
+    g_IPBUS_WIDTH   :positive := 32;
+    g_NUM_EDGE_INPUTS   :positive := 4;
+    g_SPILL_COUNTER_WIDTH   :positive := 12;
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+        sysclk: in std_logic;
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        i2c_scl_b: inout std_logic_vector(2 downto 0);
+        i2c_sda_b: inout std_logic_vector(2 downto 0);
+        phy_rstn: out std_logic; --default example ends here
+        busy_n_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        busy_p_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);
+        cfd_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        cfd_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        gpio_hdr: out std_logic_vector(3 downto 0);
+        reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 1);
+        shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 1)
+        );
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	SIGNAL s_i2c_scl_enb         : std_logic_vector(2 downto 0);
+    SIGNAL s_i2c_sda_enb         : std_logic_vector(2 downto 0);
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b(0) <= '0' when (s_i2c_scl_enb(0) = '0') else 'Z';
+    i2c_sda_b(0) <= '0' when (s_i2c_sda_enb(0) = '0') else 'Z';
+    i2c_scl_b(1) <= '0' when (s_i2c_scl_enb(1) = '0') else 'Z';
+    i2c_sda_b(1) <= '0' when (s_i2c_sda_enb(1) = '0') else 'Z';
+    i2c_scl_b(2) <= '0' when (s_i2c_scl_enb(2) = '0') else 'Z';
+    i2c_sda_b(2) <= '0' when (s_i2c_sda_enb(2) = '0') else 'Z';
+-- Infrastructure
+
+
+
+
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => sysclk,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	leds <= not ('0' & userled & inf_leds);
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151f"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81f"; -- 192.168.200.16+n
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+--	slaves: entity work.ipbus_example
+--		port map(
+--			ipb_clk => clk_ipb,
+--			ipb_rst => rst_ipb,
+--			ipb_in => ipb_out,
+--			ipb_out => ipb_in,
+--			nuke => nuke,
+--			soft_rst => soft_rst,
+--			i2c_scl_b => i2c_scl_b,
+--            i2c_sda_b => i2c_sda_b,
+--			userled => userled
+--		);
+    --OBUFT: Single-ended 3-state Output Buffer
+--7 Series
+-- Xilinx HDL Libraries Guide, version 2012.2
+
+--OBUFT_inst_scl : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_scl_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_scl_enb, -- 3-state enable input
+--    O =>  s_i2c_scl_i
+--); -- End of OBUFT_inst instantiation
+
+--OBUFT_inst_sda : IOBUF
+--generic map (
+--	DRIVE => 12,
+--	IOSTANDARD => "DEFAULT",
+--	SLEW => "SLOW")
+--port map (
+--    IO => i2c_sda_b, -- Buffer output (connect directly to top-level port)
+--    I => '0', -- Buffer input
+--    T => s_i2c_sda_enb, -- 3-state enable input
+--    O =>  s_i2c_sda_i
+--); -- End of OBUFT_inst instantiation
+    
+    slaves: entity work.ipbus_example
+    port map(
+        ipb_clk => clk_ipb,
+        ipb_rst => rst_ipb,
+        ipb_in => ipb_out,
+        ipb_out => ipb_in,
+        nuke => nuke,
+        soft_rst => soft_rst,
+        --i2c_scl_i => s_i2c_scl_i,
+        --i2c_sda_i => s_i2c_sda_i,
+        i2c_sda_i => i2c_sda_b,
+        i2c_scl_i => i2c_scl_b,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        userled => userled
+    );
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_tlu_v1e.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_tlu_v1e.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4c270159b391069879d031e0612d3566d49462a4
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/top_enclustra_tlu_v1e.vhd
@@ -0,0 +1,758 @@
+-- Top-level design for TLU v1E
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Dave Newbold, 4/10/16--
+
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fmcTLU.all;
+use work.ipbus_decode_tlu.all;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use UNISIM.vcomponents.all;
+
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top_tlu_v1e is
+    generic(
+    constant FW_VERSION : unsigned(31 downto 0):= X"1e000008"; -- Firmware revision. Remember to change this as needed.
+    g_NUM_DUTS  : positive := 4; -- <- was 3
+    g_NUM_TRIG_INPUTS   :positive := 6;-- <- was 4
+    g_NUM_EDGE_INPUTS   :positive := 6;--  <-- was 4
+    g_NUM_EXT_SLAVES    :positive :=8;--  <-- ??
+    g_EVENT_DATA_WIDTH  :positive := 64;--  <-- ??
+    g_IPBUS_WIDTH   :positive := 32;--  <-- was 32 
+    g_SPILL_COUNTER_WIDTH   :positive := 12;--  <-- ??
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+    --Clock
+        --sysclk: in std_logic; --50 MHz clock input from FPGA
+        clk_enclustra: in std_logic; --Enclustra onboard oscillator 40 MHz. Used for the IPBus block
+        sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_40_i_p: in std_logic;
+        sysclk_40_i_n: in std_logic;
+    --Misc
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        dip_sw: in std_logic_vector(3 downto 0); -- switches
+        gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
+    --RGMII interface signals
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        phy_rstn: out std_logic; 
+    --I2C bus
+        i2c_scl_b: inout std_logic;
+        i2c_sda_b: inout std_logic;
+        i2c_reset: out std_logic; --Reset line for the expander serial lines
+    --Clock generator controls
+        clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low)
+        --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0>
+    --TLU signals for DUTs
+        busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA)
+        busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA)
+        cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs
+        cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs
+        spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs
+        spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs
+        triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs
+        triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs
+        dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs
+        dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock to DUTs
+        
+        --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal
+        --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output
+        --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+                
+     --TLU trigger inputs   
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0)
+        --gpio_hdr: out std_logic_vector(3 downto 0);
+        --extclk_n_b: inout std_logic; --External clock in or clock output
+        --extclk_p_b: inout std_logic
+    );
+
+end top_tlu_v1e;
+
+architecture rtl of top_tlu_v1e is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	signal s_i2c_scl_enb         : std_logic;
+    signal s_i2c_sda_enb         : std_logic;
+    signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input)
+    
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	------------------------------------------
+	-- Internal signal declarations
+    SIGNAL T0_o                  : std_logic;
+    SIGNAL buffer_full_o         : std_logic;                                             --! Goes high when event buffer almost full
+    SIGNAL clk_8x_logic         : std_logic;                                             -- 320MHz clock
+    SIGNAL clk_4x_logic          : std_logic;                                             --! normally 160MHz
+    SIGNAL clk_logic_xtal        : std_logic;                                             -- ! 40MHz clock from onboard xtal
+    SIGNAL data_strobe           : std_logic;                                             -- goes high when data ready to load into event buffer
+    SIGNAL dout                  : std_logic;
+    SIGNAL dout1                 : std_logic;
+    SIGNAL event_data            : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+    signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
+    signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+    SIGNAL logic_clocks_reset    : std_logic;                                             -- Goes high to reset counters etc. Sync with clk_4x_logic
+    SIGNAL logic_reset           : std_logic;
+    SIGNAL overall_trigger       : std_logic;                                             --! goes high to load trigger data
+    SIGNAL overall_veto          : std_logic;                                             --! Halts triggers when high
+    SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL postVetotrigger       : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        -- ! High when trigger from input connector active and enabled
+    --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+    SIGNAL rst_fifo_o            : std_logic;                                             --! rst signal to first level fifos
+    SIGNAL s_edge_fall_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_falling        : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when falling edge
+    SIGNAL s_edge_rise_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_rising         : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when rising edge
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+    SIGNAL s_shutter             : std_logic;                                             --! shutter signal from TimePix, retimed onto local clock
+    SIGNAL s_triggerLogic_reset  : std_logic;
+    SIGNAL shutter_cnt_i         : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL shutter_i             : std_logic;
+    SIGNAL spill_cnt_i           : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL spill_i               : std_logic;
+    SIGNAL strobe_8x_logic      : std_logic;                                             --! Pulses one cycle every 4 of 16x clock.
+    SIGNAL strobe_4x_logic       : std_logic;                                             -- one pulse every 4 cycles of clk_4x
+    SIGNAL trigger_count         : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+    SIGNAL trigger_times         : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL triggers              : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+    SIGNAL veto_o                : std_logic;                                             --! goes high when one or more DUT are busy
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+	--My signals
+	--SIGNAL busy_toggle_o         : std_logic_vector(g_NUM_DUTS-1 downto 0);
+	
+----------------------------------------------
+----------------------------------------------
+    component DUTInterfaces
+    generic(
+	   g_NUM_DUTS : positive := 4;-- <- was 3
+	   g_IPBUS_WIDTH : positive := 32
+	   );
+    port (
+        clk_4x_logic_i          : IN     std_logic ;
+        strobe_4x_logic_i       : IN     std_logic ;                                  --! goes high every 4th clock cycle
+        trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
+        trigger_i               : IN     std_logic ;                                  --! goes high when trigger logic issues a trigger
+        reset_or_clk_to_dut_i   : IN     std_logic ;                                  --! Synchronization signal. Passed TO DUT pins
+        shutter_to_dut_i        : IN     std_logic ;                                  --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+        -- IPBus signals.
+        ipbus_clk_i             : IN     std_logic ;
+        ipbus_i                 : IN     ipb_wbus ;                                   --! Signals from IPBus core TO slave
+        ipbus_reset_i           : IN     std_logic ;
+        ipbus_o                 : OUT    ipb_rbus ;                                   --! signals from slave TO IPBus core
+        -- Signals to/from DUT
+        busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+        busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+        clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+        trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+        shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+        veto_o                  : OUT    std_logic   
+    );
+    end component DUTInterfaces;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT T0_Shutter_Iface
+    PORT (
+        clk_4x_i      : IN     std_logic;
+        clk_4x_strobe : IN     std_logic;
+        ipbus_clk_i   : IN     std_logic;
+        ipbus_i       : IN     ipb_wbus;
+        T0_o          : OUT    std_logic;
+        ipbus_o       : OUT    ipb_rbus;
+        shutter_o     : OUT    std_logic
+    );
+    END COMPONENT T0_Shutter_Iface;
+----------------------------------------------
+----------------------------------------------
+
+   COMPONENT eventBuffer
+   GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_READ_COUNTER_WIDTH : positive := 16
+   );
+   PORT (
+        clk_4x_logic_i    : IN     std_logic ;
+        data_strobe_i     : IN     std_logic ;                                     -- Indicates data TO transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic ;
+        ipbus_i           : IN     ipb_wbus ;
+        ipbus_reset_i     : IN     std_logic ;
+        strobe_4x_logic_i : IN     std_logic ;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o        : OUT    std_logic ;                                     --! rst signal TO first level fifos
+        buffer_full_o     : OUT    std_logic ;                                     --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus ;
+        logic_reset_i     : IN     std_logic                                       -- reset buffers when high. Synch withclk_4x_logic
+   );
+   END COMPONENT eventBuffer;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT eventFormatter
+    GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_COUNTER_TRIG_WIDTH : positive := 32;
+        g_COUNTER_WIDTH      : positive := 12;
+        g_EVTTYPE_WIDTH      : positive := 4;      --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    : positive := 6       --! Number of trigger inputs (POSSIBLY WRONG!)
+    );
+    PORT (
+        clk_4x_logic_i         : IN     std_logic ;                                         --! Rising edge active
+        ipbus_clk_i            : IN     std_logic ;
+        logic_strobe_i         : IN     std_logic ;                                         --! Pulses high once every 4 cycles of clk_4x_logic
+        logic_reset_i          : IN     std_logic ;                                         --! goes high TO reset counters. Synchronous with clk_4x_logic
+        rst_fifo_i             : IN     std_logic ;                                         --! Goes high TO reset FIFOs
+        buffer_full_i          : IN     std_logic ;                                         --! Goes high when output fifo full
+        trigger_i              : IN     std_logic ;                                         --! goes high TO load trigger data. One cycle of clk_4x_logic
+        trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);  --! Array of trigger times ( w.r.t. logic_strobe)
+        trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);    --! high for each input that "fired"
+        trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
+        shutter_i              : IN     std_logic ;
+        shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        spill_i                : IN     std_logic ;
+        spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when rising edge
+        edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when falling edge
+        edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        ipbus_i                : IN     ipb_wbus ;
+        ipbus_o                : OUT    ipb_rbus ;
+        data_strobe_o          : OUT    std_logic ;                                         --! goes high when data ready TO load into event buffer
+        event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        reset_timestamp_i      : IN     std_logic ;                                         --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+        reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+    );
+    END COMPONENT eventFormatter;   
+----------------------------------------------
+----------------------------------------------
+    COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerInputs_newTLU
+    GENERIC (
+        g_NUM_INPUTS  : natural  := 1;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Inputs from constant-fraction discriminators
+        --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Input from CFD
+        clk_4x_logic         : IN     std_logic ;                                        --! Rising edge active. By default = 4*40MHz = 160MHz
+        clk_200_i : IN     std_logic ;
+        strobe_4x_logic_i    : IN     std_logic ;                                        --! Pulses high once every 4 cycles of clk_4x_logic
+        threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        reset_i              : IN     std_logic ;
+        trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+        trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+        --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+        edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when rising edge. Syncronous with clk_4x_logic_i
+        edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when falling edge
+        ipbus_clk_i          : IN     std_logic ;
+        ipbus_reset_i        : IN     std_logic ;
+        ipbus_i              : IN     ipb_wbus ;                                         --! Signals from IPBus core TO slave
+        ipbus_o              : OUT    ipb_rbus ;                                         --! signals from slave TO IPBus core
+        clk_8x_logic_i      : IN     std_logic ;                                        --! 640MHz clock ( 16x 40MHz )
+        strobe_8x_logic_i   : IN     std_logic                                          --! Pulses one cycle every 4 of 8x clock.
+    );
+    END COMPONENT triggerInputs_newTLU;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerLogic
+    GENERIC (
+        g_NUM_INPUTS  : positive := 4;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        clk_4x_logic_i      : IN     std_logic ;                                   -- ! Rising edge active
+        ipbus_clk_i         : IN     std_logic ;
+        ipbus_i             : IN     ipb_wbus ;                                    -- Signals from IPBus core TO slave
+        ipbus_reset_i       : IN     std_logic ;
+        logic_reset_i       : IN     std_logic ;                                   -- active high. Synchronous with clk_4x_logic
+        logic_strobe_i      : IN     std_logic ;                                   -- ! Pulses high once every 4 cycles of clk_4x_logic
+        trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active
+        trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        veto_i              : IN     std_logic ;                                   -- ! Halts triggers when high
+        trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active and enabled
+        trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  -- starts at one. Increments for each post_veto_trigger
+        ipbus_o             : OUT    ipb_rbus ;                                    -- signals from slave TO IPBus core
+        post_veto_trigger_o : OUT    std_logic ;                                   -- ! goes high when trigger passes
+        pre_veto_trigger_o  : OUT    std_logic ;
+        trigger_active_o    : OUT    std_logic                                     --! Goes high when triggers are active ( ie. not veoted)
+    );
+    END COMPONENT triggerLogic;
+    
+    COMPONENT i2c_master
+        PORT (
+           i2c_scl_i     : IN     std_logic;
+           i2c_sda_i     : IN     std_logic;
+           ipbus_clk_i   : IN     std_logic;
+           ipbus_i       : IN     ipb_wbus;
+           ipbus_reset_i : IN     std_logic;
+           i2c_scl_enb_o : OUT    std_logic;
+           i2c_sda_enb_o : OUT    std_logic;
+           ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    
+    component clk_wiz_0
+    port
+     (-- Clock in ports
+      clk_in1           : in     std_logic;
+      -- Clock out ports
+      clk_out1          : out    std_logic;
+      -- Status and control signals
+      reset             : in     std_logic;
+      locked            : out    std_logic
+     );
+    end component;
+    
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+    --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+    FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
+    FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+    FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    FOR ALL : triggerInputs_newTLU USE ENTITY work.triggerInputs_newTLU;
+    FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+    -- pragma synthesis_on 
+      	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+    
+    
+    -- Infrastructure
+    -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+    logic_clocks_reset <= '0';
+    -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+    spill_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+    spill_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+    shutter_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+    shutter_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
+    dout1 <= '0';
+    -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
+    dout <= '0';
+    -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
+    --gpio_hdr <= dout1 & dout & s_shutter & T0_o;
+    -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+    overall_veto <= buffer_full_o OR veto_o;
+    -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
+    s_triggerLogic_reset <= logic_reset OR T0_o;
+
+    i2c_reset <= '1';
+    clk_gen_rst <= '1';
+    ---gpio <= strobe_8x_logic;---
+    gpio <= veto_o;---
+    --gpio <= busy_i(1);---
+    
+    --Set diff clock out to 0 because we cannot have the correct differential voltage output
+    sysclk_50_o_p <= '0';
+    sysclk_50_o_n <= '0';
+    --Set busy_o to 0 for now
+    busy_o <= std_logic_vector(to_unsigned(0,    busy_o'length));
+    --sysclk_40_o_p <= sysclk;
+
+------------------------------------------
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => clk_encl_buf,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst_125_o => phy_rst_e,
+			clk_200_o => clk_200,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	--leds <= not ('0' & userled & inf_leds); -- Check this.
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & dip_sw; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & dip_sw; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151e"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81e"; -- 192.168.200.16+n
+
+------------------------------------------
+    I1 : entity work.ipbus_ctrlreg_v
+    port map(
+        clk => clk_ipb,
+        reset => rst_ipb,
+        ipbus_in => ipbww(N_SLV_CTRL_REG),
+        ipbus_out => ipbrr(N_SLV_CTRL_REG),
+        d => stat,
+        q => ctrl
+    );
+    stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
+    soft_rst <= ctrl(0)(0);
+    nuke <= ctrl(0)(1);
+    
+------------------------------------------
+	I2 : entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_out,
+      ipb_out => ipb_in,
+      sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
+      ipb_to_slaves => ipbww,
+      ipb_from_slaves => ipbrr
+    );
+
+------------------------------------------
+    I3 : i2c_master
+    PORT MAP (
+        i2c_scl_i     => i2c_scl_b,
+        i2c_sda_i     => i2c_sda_b,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_I2C_0),
+        ipbus_reset_i => rst_ipb,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        ipbus_o       => ipbrr(N_SLV_I2C_0)
+    );
+    
+----------------------------------------------
+    I4 : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => clk_ipb,
+        ipbus_i               => ipbww(N_SLV_LGCCLK),
+        ipbus_reset_i         => rst_ipb,
+        Reset_i               => logic_clocks_reset,
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => ipbrr(N_SLV_LGCCLK),
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => leds(3),
+        logic_reset_o         => logic_reset
+    );    
+
+----------------------------------------------
+    I5 : triggerInputs_newTLU 
+    GENERIC MAP (
+        g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+        g_IPBUS_WIDTH => 32
+    )
+    PORT MAP (
+        clk_4x_logic         => clk_4x_logic,
+        clk_200_i => clk_200,
+        strobe_4x_logic_i    => strobe_4x_logic,
+        threshold_discr_p_i  => threshold_discr_p_i,
+        threshold_discr_n_i  => threshold_discr_n_i,
+        reset_i              => logic_reset,
+        trigger_times_o      => trigger_times,
+        trigger_o            => triggers,
+        --trigger_debug_o      => OPEN,
+        edge_rising_times_o  => s_edge_rise_times,
+        edge_falling_times_o => s_edge_fall_times,
+        edge_rising_o        => s_edge_rising,
+        edge_falling_o       => s_edge_falling,
+        ipbus_clk_i          => clk_ipb,
+        ipbus_reset_i        => rst_ipb,
+        ipbus_i              => ipbww(N_SLV_TRGIN),
+        ipbus_o              => ipbrr(N_SLV_TRGIN),
+        clk_8x_logic_i      => clk_8x_logic,
+        strobe_8x_logic_i   => strobe_8x_logic
+    );
+
+------------------------------------------      
+    I6 : eventFormatter
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+        g_COUNTER_WIDTH      => 12,
+        g_EVTTYPE_WIDTH      => 4,                         --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    => g_NUM_EDGE_INPUTS,         --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    => g_NUM_TRIG_INPUTS          --! Number of trigger inputs
+    )
+    PORT MAP (
+        clk_4x_logic_i         => clk_4x_logic,
+        ipbus_clk_i            => clk_ipb,
+        logic_strobe_i         => strobe_4x_logic,
+        logic_reset_i          => logic_reset,
+        rst_fifo_i             => rst_fifo_o,
+        buffer_full_i          => buffer_full_o,
+        trigger_i              => overall_trigger,
+        trigger_times_i        => postVetoTrigger_times,
+        trigger_inputs_fired_i => postVetotrigger,
+        trigger_cnt_i          => trigger_count,
+        shutter_i              => shutter_i,
+        shutter_cnt_i          => shutter_cnt_i,
+        spill_i                => spill_i,
+        spill_cnt_i            => spill_cnt_i,
+        edge_rise_i            => s_edge_rising,
+        edge_fall_i            => s_edge_falling,
+        edge_rise_time_i       => s_edge_rise_times,
+        edge_fall_time_i       => s_edge_fall_times,
+        ipbus_i                => ipbww(N_SLV_EVFMT),
+        ipbus_o                => ipbrr(N_SLV_EVFMT),
+        data_strobe_o          => data_strobe,
+        event_data_o           => event_data,
+        reset_timestamp_i      => T0_o,
+        reset_timestamp_o      => OPEN
+    );
+
+------------------------------------------
+    I7 : eventBuffer
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_READ_COUNTER_WIDTH => 14
+        
+    )
+    PORT MAP (
+        clk_4x_logic_i    => clk_4x_logic,
+        data_strobe_i     => data_strobe,
+        event_data_i      => event_data,
+        ipbus_clk_i       => clk_ipb,
+        ipbus_i           => ipbww(N_SLV_EVBUF),
+        ipbus_reset_i     => rst_ipb,
+        strobe_4x_logic_i => strobe_4x_logic,
+        rst_fifo_o        => rst_fifo_o,
+        buffer_full_o     => buffer_full_o,
+        ipbus_o           => ipbrr(N_SLV_EVBUF),
+        logic_reset_i     => logic_reset
+    );
+    
+------------------------------------------
+    I8 : T0_Shutter_Iface
+    PORT MAP (
+        clk_4x_i      => clk_4x_logic,
+        clk_4x_strobe => strobe_4x_logic,
+        T0_o          => T0_o,
+        shutter_o     => s_shutter,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_SHUT),
+        ipbus_o       => ipbrr(N_SLV_SHUT)
+    );
+
+------------------------------------------
+    I9 : DUTInterfaces
+    GENERIC MAP (
+        g_NUM_DUTS    => g_NUM_DUTS,
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+    )
+    PORT MAP (
+         clk_4x_logic_i          => clk_4x_logic,
+         strobe_4x_logic_i       => strobe_4x_logic,
+         trigger_counter_i       => trigger_count,
+         trigger_i               => overall_trigger,
+         reset_or_clk_to_dut_i   => T0_o,
+         shutter_to_dut_i        => s_shutter,
+         ipbus_clk_i             => clk_ipb,
+         ipbus_i                 => ipbww(N_SLV_DUT),
+         ipbus_reset_i           => rst_ipb,
+         ipbus_o                 => ipbrr(N_SLV_DUT),
+         busy_from_dut       => busy_i,
+         busy_to_dut        => open,
+         clk_from_dut => dut_clk_i,
+         clk_to_dut => dut_clk_o,
+         --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+         --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+         reset_to_dut => spare_o,
+         trigger_to_dut => triggers_o,
+         --shutter_to_dut_n_o      => shutter_to_dut_n_o,
+         --shutter_to_dut_p_o      => shutter_to_dut_p_o,
+         shutter_to_dut  => cont_o,
+         veto_o                  => veto_o
+    );
+    
+------------------------------------------ 
+        I10 : triggerLogic
+        GENERIC MAP (
+            g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+            g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+        PORT MAP (
+            clk_4x_logic_i      => clk_4x_logic,
+            ipbus_clk_i         => clk_ipb,
+            ipbus_i             => ipbww(N_SLV_TRGLGC),
+            ipbus_reset_i       => rst_ipb,
+            logic_reset_i       => s_triggerLogic_reset,
+            logic_strobe_i      => strobe_4x_logic,
+            trigger_i           => triggers,
+            trigger_times_i     => trigger_times,
+            veto_i              => overall_veto,
+            trigger_o           => postVetotrigger,
+            trigger_times_o     => postVetoTrigger_times,
+            event_number_o      => trigger_count,
+            ipbus_o             => ipbrr(N_SLV_TRGLGC),
+            post_veto_trigger_o => overall_trigger,
+            pre_veto_trigger_o  => OPEN,
+            trigger_active_o    => leds(2)
+        );     
+         
+-------------TEST AREA------------    
+--    test0: entity work.test_inToOut
+--    port map(
+--        clk_in => clk_200,
+--        busy_in=> busy_i,
+--        control_in=> cont_i,
+--        trig_in=> triggers_i,
+--        clkDut_in=> dut_clk_i,
+--        spare_in=> spare_i,
+--        busy_out=> busy_o,
+--        control_out=> cont_o,
+--        trig_out=> triggers_o,
+--        clkDut_out=> dut_clk_o,
+--        spare_out=> spare_o
+--    );
+
+--    dutout0: entity work.DUTs_outputs
+--    port map(
+--        clk_in => clk_encl_buf, 
+--       d_clk_o => open, --dut_clk_o,
+--        d_trg_o => open, --triggers_o,
+--        d_busy_o => busy_o,
+--        d_cont_o => open, --cont_o,
+--        d_spare_o => open --spare_o
+--    );
+   
+--    clk50_o_fromEnclustra : clk_wiz_0
+--       port map ( 
+--       -- Clock in ports
+--       clk_in1 => clk_encl_buf, --sysclk_40,
+--      -- Clock out ports  
+--       clk_out1 => encl_clock50,
+--      -- Status and control signals                
+--       reset => '0',
+--       locked =>  open          
+--     );
+
+    
+----------------------------------------------
+
+
+
+
+
+
+
+
+
+
+    
+
+------------------------------------------      
+
+
+------------------------------------------
+    IBUFGDS_inst: IBUFGDS
+    generic map (
+        IBUF_LOW_PWR=> false
+    )
+    port map (
+        O => sysclk_40,
+        I => sysclk_40_i_p,
+        IB => sysclk_40_i_n
+    );
+    
+------------------------------------------
+    IBUFG_inst: IBUFG
+    port map (
+        O => clk_encl_buf,
+        I => clk_enclustra--sysclk
+    );    
+
+------------------------------------------
+-- Do not use this: we need differential 3.3 V, not available.
+--    OBUFDS_inst : OBUFDS
+--    generic map (
+--        SLEW => "FAST") -- Specify the output slew rate
+--    port map (
+--        O => sysclk_50_o_p, -- Diff_p output (connect directly to top-level port)
+--        OB => sysclk_50_o_n, -- Diff_n output (connect directly to top-level port)
+--        I => encl_clock50 -- Buffer input
+--    );
+    -- This might not work: these are just two single ended. If we remove R coupling maybe?
+    --sysclk_50_o_p <= encl_clock50;
+    --sysclk_50_o_n <= not encl_clock50;
+
+      
+
+
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/IODELAYCal_FSM_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/IODELAYCal_FSM_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d69931d3dd04bfae2a5f4876c7984d6ebf0e28f
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/IODELAYCal_FSM_rtl.vhd
@@ -0,0 +1,102 @@
+--=============================================================================
+--! @file IODELAYCal_FSM_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- UoB , USC
+-- --
+------------------------------------------------------------------------------- --
+--
+--! @brief Finite-state machine to control calibration and reset signals to
+--! Iserdes, IDelay
+--! based on code by Alvaro Dosil\n
+--
+--! @author  Alvaro Dosil 
+--
+--! @date 22/Feb/2014
+--
+--! @version v0.1
+--
+--! @details
+--
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--! <another thing to do> \n
+
+  LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity IODELAYCal_FSM is
+	port (
+		clk_i 		: in std_logic;		--! Global clock
+		startcal_i 	: in std_logic;      --! Start calibration
+		busy_i 		: in std_logic;     	--! Status of the IDELAY component
+		calibrate_o : out std_logic;     --! Calibration signals to IODELAY
+		reset_o 		: out std_logic  		--! Reset to IODELAY component
+    );
+end entity IODELAYCal_FSM;
+
+architecture rtl of IODELAYCal_FSM is
+
+  --! Calibration FSM state values
+  type state_values is (st0, st1, st2, st3);
+  signal pres_state, next_state: state_values := st0;
+  
+	signal s_cal_FSM      : std_logic := '0';         -- IODELAY reset
+  signal s_rst_FSM      : std_logic := '0';         -- IODELAY reset
+  
+begin  -- rtl
+
+  --! Calibration FSM register
+  statereg: process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      pres_state <= next_state;     -- Move to next state
+      
+    end if;
+  end process statereg;
+
+
+  --! Calibration FSM combinational block
+  fsm: process(pres_state, startcal_i, busy_i)
+  begin
+    next_state <= pres_state;
+    -- Default values
+    s_Rst_FSM <= '0';
+    s_cal_FSM <= '0';
+    
+    case pres_state is
+      
+      -- st0 - IDLE
+      when st0=>
+        if ( startcal_i = '1') then 
+          next_state <= st1;            -- Next state is "st1 - SEND CALIBRATION SIGNAL"
+        end if;
+        
+      -- st1 - SEND CALIBRATION SIGNAL
+      when st1=>
+        s_cal_FSM <= '1';
+		  next_state <= st2;            -- Next state is "st2 - WAIT BUSY = '0'"
+        
+      -- st2 - WAIT BUSY = '0'
+      when st2=>
+        if busy_i = '0' then 
+          next_state <= st3;            -- Next state is "st3 - RESET STATE"
+        end if;
+        
+        -- st3 - RESET STATE
+      when st3=>
+        s_Rst_FSM <= '1';
+		  next_state <= st0;              -- Next state is "st0 - IDLE"
+		
+    end case;
+    
+  end process fsm;
+
+  calibrate_o <= s_cal_FSM;
+  reset_o <= s_Rst_FSM;
+                
+end rtl;
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/arrivalTimeLUT_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/arrivalTimeLUT_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f1b1acc0fb60c0741bc98fc83a2b8acf194ebddc
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/arrivalTimeLUT_rtl.vhd
@@ -0,0 +1,187 @@
+--=============================================================================
+--! @file arrivalTimeLUT_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.ArivalTimeLUT.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+--! @brief Uses a look-up-table to convert the eight bits from the two 1:4 deserializers\n
+--! into a 5-bit time ( 3 bits from the position in 8-bit deserialized data \n
+--! plus two bits from position w.r.t. the strobe_4x_logic_i signal ( one pulse
+--! every 4 cycles of clk_4x_logic_i 
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:46:34 11/21/12
+--
+--! @version v0.1
+--
+--! @details
+--! Rising and falling edge times encoded as a LUT. Contents:
+--! MRFrrrfff
+--! \li M = multiple edges present ( more than one rising or falling edge)
+--! \li R = at least one rising edge present
+--! \li F = at least one falling edge present.
+--! \li rrr = time of first rising edge
+--! \li fff = time of first falling edge
+ENTITY arrivalTimeLUT IS
+   GENERIC( 
+      g_NUM_FINE_BITS   : positive := 3;
+      g_NUM_COARSE_BITS : positive := 2
+   );
+   PORT( 
+      clk_4x_logic_i           : IN     std_logic;                                                        --! Rising edge active
+      strobe_4x_logic_i        : IN     std_logic;                                                        --! Pulses high once every 4 cycles of clk_4x_logic
+      deserialized_data_i      : IN     std_logic_vector (8 DOWNTO 0);                                    --! Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data
+      first_rising_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      last_falling_edge_time_o : OUT    std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0);  --! Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+      rising_edge_o            : OUT    std_logic;                                                        --! goes high if there is a rising edge in the data. Clocked by clk_4x_logic_i
+      falling_edge_o           : OUT    std_logic;                                                        --! goes high if there is a falling edge in the data.Clocked by clk_4x_logic_i
+      multiple_edges_o         : OUT    std_logic                                                         --! there is more than one rising or falling edge transition.
+   );
+
+-- Declarations
+
+END ENTITY arrivalTimeLUT ;
+
+--
+ARCHITECTURE rtl OF arrivalTimeLUT IS
+
+  constant c_FALLING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS;  --! Bit position of bit set when falling edge detected
+  constant c_RISING_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+1;  --! Bit position of bit set when rising edge detected
+  constant c_MULTI_EDGE_BIT : positive :=  2*g_NUM_FINE_BITS+2;  --! Bit position of bit set when rising edge detected
+
+
+  signal s_coarse_bits : std_logic_vector(g_NUM_COARSE_BITS-1 downto 0) := "00";  --! phase w.r.t. strobe
+
+  signal s_LUT_ENTRY : std_logic_vector(g_NUM_FINE_BITS*2 +3-1 downto 0);  -- stores intermediate LUT value.
+  
+  type t_LUT is array (natural range <>) of std_logic_vector(g_NUM_FINE_BITS*2 + 3 -1 downto 0);
+  --! Lookup table for arrival time and rising/falling edge detection (3bits
+  --! for position in 9-bit deserialized data plus two bits for rising/falling 
+  constant c_LUT : t_LUT(0 to 511) := (
+    "000000000", "001000000", "011000001", "001000001", "011001010", "011001010", "011000010", "001000010", --0 [0, 7]
+    "011010011", "011010011", "111000011", "011010011", "011001011", "011001011", "011000011", "001000011", --1 [8, 15]
+    "011011100", "011011100", "111000100", "011011100", "111001100", "111001100", "111000100", "011011100", --2 [16, 23]
+    "011010100", "011010100", "111000100", "011010100", "011001100", "011001100", "011000100", "001000100", --3 [24, 31]
+    "011100101", "011100101", "111000101", "011100101", "111001101", "111001101", "111000101", "011100101", --4 [32, 39]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011100101", --5 [40, 47]
+    "011011101", "011011101", "111000101", "011011101", "111001101", "111001101", "111000101", "011011101", --6 [48, 55]
+    "011010101", "011010101", "111000101", "011010101", "011001101", "011001101", "011000101", "001000101", --7 [56, 63]
+    "011101110", "011101110", "111000110", "011101110", "111001110", "111001110", "111000110", "011101110", --8 [64, 71]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --9 [72, 79]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --10 [80, 87]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110", --11 [88, 95]
+    "011100110", "011100110", "111000110", "011100110", "111001110", "111001110", "111000110", "011100110", --12 [96, 103]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011100110", --13 [104, 111]
+    "011011110", "011011110", "111000110", "011011110", "111001110", "111001110", "111000110", "011011110", --14 [112, 119]
+    "011010110", "011010110", "111000110", "011010110", "011001110", "011001110", "011000110", "001000110", --15 [120, 127]
+    "011110111", "011110111", "111000111", "011110111", "111001111", "111001111", "111000111", "011110111", --16 [128, 135]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --17 [136, 143]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --18 [144, 152]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --19 [152, 159]
+    "111100111", "111100111", "111000111", "111100111", "111001111", "111001111", "111000111", "111100111", --20 [160, 167]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "111100111", --21 [168, 175]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --22 [176, 183]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111", --23 [184, 191]
+    "011101111", "011101111", "111000111", "011101111", "111001111", "111001111", "111000111", "011101111", --24 [192, 199]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --25 [200, 207]
+    "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111", --26 [208, 215]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111", --27 [216, 223]
+    "011100111", "011100111", "111000111", "011100111", "111001111", "111001111", "111000111", "011100111", --28 [224, 231]
+    "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011100111", --29 [232, 239]
+    "011011111", "011011111", "111000111", "011011111", "111001111", "111001111", "111000111", "011011111", --30 [240, 247]
+    "011010111", "011010111", "111000111", "011010111", "011001111", "011001111", "011000111", "001000111", --31 [248, 255]
+    "010111000", "011111000", "111000001", "011111001", "111001010", "111001010", "111000010", "011111010", --32 [256, 263]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011111011", --33 [264, 271]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --34 [272, 279]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011111100", --35 [280, 287]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --36 [288, 295]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --37 [296, 303]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --38 [304, 311]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011111101", --39 [312, 319]
+    "111101110", "111101110", "111000110", "111101110", "111001110", "111001110", "111000110", "111101110", --40 [320, 327]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --41 [328, 333]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --42 [336, 343]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110", --43 [344, 351]
+    "111100110", "111100110", "111000110", "111100110", "111001110", "111001110", "111000110", "111100110", --44 [352, 359]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111100110", --45 [360, 367]
+    "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110", --46 [368, 375]
+    "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011111110", --47 [376, 383]
+    "010110000", "011110000", "111000001", "011110001", "111001010", "111001010", "111000010", "011110010", --48 [384, 391]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011110011", --49 [392, 399]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --50 [400, 407]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011110100", --51 [408, 415]
+    "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101", --52 [416, 423]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101", --53 [424, 431]
+    "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101", --54 [432, 439]
+    "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011110101", --55 [440, 447]
+    "010101000", "011101000", "111000001", "011101001", "111001010", "111001010", "111000010", "011101010", --56 [448, 455]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011101011", --57 [456, 463]
+    "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100", --58 [464, 471]
+    "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011101100", --59 [472, 479]
+    "010100000", "011100000", "111000001", "011100001", "111001010", "111001010", "111000010", "011100010", --60 [480, 487]
+    "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011100011", --61 [488, 495]
+    "010011000", "011011000", "111000001", "011011001", "111001010", "111001010", "111000010", "011011010", --62 [496, 503]
+    "010010000", "011010000", "111000001", "011010001", "010001000", "011001000", "010000000", "000000000" -- 63 [504, 511]
+    );  
+  
+BEGIN
+
+  -- purpose: uses the deserialized data as a index into
+  --          a lookup table holding the position of the first rising edge (if any)
+  --          and if there is a rising or falling edge
+  -- type   : combinational
+  -- inputs : clk_4x_logic_i
+  -- outputs: arrival_time_o , rising_edge_o , falling_edge_o
+  examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
+--    variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0);  --! Entry in LUT pointed to by deserialized data
+  begin  -- process examine_lut
+    
+--    v_LUT_entry := c_LUT(to_integer(unsigned(deserialized_data_i)));
+
+    if rising_edge(clk_4x_logic_i) then
+      s_LUT_ENTRY <= c_LUT(to_integer(unsigned(deserialized_data_i)));
+      first_rising_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS*2-1 downto g_NUM_FINE_BITS);
+      last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
+      rising_edge_o  <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
+      falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
+      multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT); 
+    end if;
+
+  end process examine_lut;
+  
+  --! Coarse time stamp. Phase w.r.t. strobe
+--	c_coarse_ts : entity work.CounterUp
+--   PORT MAP (
+--     clk   => clk_4x_logic_i,
+--     ce    => '1',
+--     sinit => strobe_4x_logic_i, --'0',
+--	  q(31 downto 2) => open,
+--     q(1 downto 0)  => s_coarse_bits
+--	);
+--  
+  	c_coarse_ts : entity work.CounterWithReset
+  	GENERIC MAP (
+  	  g_COUNTER_WIDTH => 2 )
+   PORT MAP (
+     clock_i   => clk_4x_logic_i,
+     enable_i   => '1',
+     reset_i => strobe_4x_logic_i,        -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
+     result_o => s_coarse_bits
+	);
+	
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/dualSERDES_1to4_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/dualSERDES_1to4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..dd090f4a5f79647ace4788bde06ab9fd167acc0d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/dualSERDES_1to4_rtl.vhd
@@ -0,0 +1,421 @@
+--=============================================================================
+--! @file dualSERDES_1to4_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.dualSERDES_1to4.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other
+--! based on TDC by Alvaro Dosil
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:06:53 11/16/12
+--
+--! @version v0.1
+--
+--! @details
+--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--
+--------------------------------------------------------------------------------
+
+ENTITY dualSERDES_1to4 IS
+   PORT( 
+      reset_i        : IN     std_logic;                      --! Resets  IODELAY
+      --calibrate_i    : IN     std_logic;                      --! Starts IODELAY calibration.
+      --data_i         : IN     std_logic;                      --! from input buffer.
+      data_i_pos     : IN     std_logic;                      --! from positive differential input pin 
+      data_i_neg     : IN     std_logic;                      --! from negative differential input pin 
+      fastClk_i      : IN     std_logic;                      --! 2x fabric clock. e.g. 320MHz
+      fabricClk_i    : IN     std_logic;                      --! clock for output to FPGA. e.g. 160MHz
+      strobe_i       : IN     std_logic;                      --! Strobes once every 4 cycles of fastClk
+      data_o         : OUT    std_logic_vector (7 DOWNTO 0);  --! Deserialized data. Interleaved between prompt and delayed  serdes.
+                                                              --! data_o(0) is the oldest data
+      status_o       : OUT    std_logic_vector(1 downto 0)    --! outputs from IODELAY "busy" 0=prompt,1=delayed
+   );
+
+-- Declarations
+
+
+END ENTITY dualSERDES_1to4 ;
+
+--
+ARCHITECTURE rtl OF dualSERDES_1to4 IS
+
+    constant c_S : positive := 4;                     -- ! SERDES division ratio
+
+    signal s_Data_i_d_p   : std_logic;
+    signal s_Data_i_d_d   : std_logic;
+    signal s_busy_idelay_p  : std_logic;              -- Busy from iodelay.
+    signal s_busy_idelay_d  : std_logic;              -- Busy from iodelay.
+    signal s_busy			  : std_logic;              -- Busy from the two iodelays.
+    signal s_data_o       : std_logic_vector(7 downto 0);  --! Deserialized data
+	signal s_cal			 : std_logic := '0'; 				--! Calibration signal
+	signal s_rst_cal		: std_logic := '0'; 				--! reset after calibration process
+    signal delay_val :std_logic_vector(4 downto 0);
+    signal prompt_val :std_logic_vector(4 downto 0);
+    signal delayed_out: std_logic_vector(4 downto 0);
+    signal prompt_out: std_logic_vector(4 downto 0);
+---------------------------------------------
+    component delayIO
+    generic
+    (-- width of the data for the system
+    SYS_W       : integer := 1;
+    -- width of the data for the device
+    DEV_W       : integer := 1);
+    port
+        (
+        -- From the system into the device
+        data_in_from_pins_p     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_from_pins_n     : in    std_logic_vector(SYS_W-1 downto 0);
+        data_in_to_device       : out   std_logic_vector(DEV_W-1 downto 0);
+        
+        -- Input, Output delay control signals
+        delay_clk               : in    std_logic;
+        in_delay_reset          : in    std_logic;                    -- Active high synchronous reset for input delay
+        in_delay_data_ce        : in    std_logic_vector(SYS_W -1 downto 0);                    -- Enable signal for delay 
+        in_delay_data_inc       : in    std_logic_vector(SYS_W -1 downto 0);                    -- Delay increment (high), decrement (low) signal
+        delay_locked            : out   std_logic;                    -- Locked signal from IDELAYCTRL
+        ref_clock               : in    std_logic;                    -- Reference Clock for IDELAYCTRL. Has to come from BUFG.
+        
+        -- Clock and reset signals
+        clk_in                  : in    std_logic;                    -- Fast clock from PLL/MMCM 
+        clock_enable            : in    std_logic;
+        io_reset                : in    std_logic);                   -- Reset signal for IO circuit
+    end component;
+
+  
+BEGIN
+ 
+	-- IODELAYs calibration FSM
+	IODELAYCal: entity work.IODELAYCal_FSM
+    port map (
+        clk_i       => fabricClk_i,
+        startcal_i  => reset_i,
+        busy_i		=> s_busy,
+        calibrate_o     => s_cal,
+        reset_o         => s_rst_cal
+    );
+
+
+-----------------------------------------------------
+--    iodelay_prompt : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_p,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        io_reset => s_rst_cal
+--    );
+    prompt_val <= "00000";
+
+    IDELAY2_Prompt : IDELAYE2
+    generic map (
+        IDELAY_TYPE => "VARIABLE",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> prompt_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_p,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> prompt_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+        IDATAIN => not data_i_neg, --- THIS MUST BE INVERTED!!!!
+        --IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '0',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+    
+
+
+----IODELAY2 no longer valid. Replaced using IP delay (SelectIO interface wizard generated)
+--  IODELAY2_Prompt : IODELAY2
+--    generic map (
+--      COUNTER_WRAPAROUND => "STAY_AT_LIMIT" ,  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--      DATA_RATE          => "SDR",            -- "SDR" or "DDR" 
+--      DELAY_SRC          => "IDATAIN",        -- "IO", "ODATAIN" or "IDATAIN" 
+--      SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--      IDELAY_TYPE        => "VARIABLE_FROM_ZERO",
+--      IDELAY_VALUE     	=> 0                -- Amount of taps for fixed input delay (0-255)
+--      --SIM_TAPDELAY_VALUE=> 10               -- Per tap delay used for simulation in ps
+--      )
+--    port map (
+--      BUSY     => s_busy_idelay_p,      -- 1-bit output: Busy output after CAL
+--      DATAOUT  => s_Data_i_d_p,     -- 1-bit output: Delayed data output to ISERDES/input register
+--      DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--      DOUT     => open,             -- 1-bit output: Delayed data output
+--      TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--      CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--      CE       => '0',              -- 1-bit input: Enable INC input
+--      CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--      IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--      INC      => '0',              -- 1-bit input: Increment / decrement input
+--      IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--      IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--      ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--      RST      => s_rst_cal,            -- 1-bit input: reset_i to 1/2 of total delay period
+--      T        => '1'               -- 1-bit input: 3-state input signal
+--      );
+    
+    s_busy_idelay_p <= (prompt_val(0) XOR  prompt_out(0)) OR (prompt_val(1) XOR  prompt_out(1)) OR (prompt_val(2) XOR  prompt_out(2)) OR (prompt_val(3) XOR  prompt_out(3)) OR (prompt_val(4) XOR  prompt_out(4));
+	status_o(1) <= s_busy_idelay_p;
+
+--    iodelay_delay : delayIO
+--    port map 
+--    ( 
+--        data_in_from_pins_p(0) => data_i_pos,
+--        data_in_from_pins_n(0) => data_i_neg,
+--        data_in_to_device(0) => s_Data_i_d_d,
+--        delay_clk => fabricClk_i,
+--        in_delay_reset => '0',                    
+--        in_delay_data_ce(0) => '1',      
+--        in_delay_data_inc(0) => '0',     
+        
+--        delay_locked => open,                      
+--        ref_clock => fabricClk_i,                         
+--        clk_in => fastClk_i,                            
+--        clock_enable => '1',
+--        clk_out => open,
+--        io_reset => s_rst_cal
+--    );
+
+    -- This should be configurable via IPBus. For now fixed value. The tap value is 200 MHz (5 ns). We want
+    -- a quarter of the 320 MHz clock (3.125 ns) so 0.78125 ns, corresponding to 6 taps.
+    delay_val <= "00110";
+    --delay_val <= "00000";
+    
+    IDELAY2_Delayed : IDELAYE2
+    generic map (
+        --IDELAY_TYPE => "VARIABLE",
+        IDELAY_TYPE => "VAR_LOAD",
+        DELAY_SRC => "IDATAIN",
+        SIGNAL_PATTERN => "DATA"
+    )
+    port map (
+        CNTVALUEOUT=> delayed_out,--5-bitoutput:Countervalueoutput
+        DATAOUT=> s_Data_i_d_d,    --1-bitoutput:Delayeddataoutput
+        C=> fabricClk_i,    --1-bitinput:Clockinput
+        CE=> '0',    --1-bitinput:Activehighenableincrement/decrementinput
+        CINVCTRL=> '0' ,--1-bitinput:Dynamicclockinversioninput
+        CNTVALUEIN=> delay_val,--5-bitinput:Countervalueinput
+        DATAIN=> '0',    --1-bitinput:Internaldelaydatainput
+--        IDATAIN=> data_i,    --1-bitinput:DatainputfromtheI/O
+        IDATAIN => data_i_pos,
+        INC=> '0',    --1-bitinput:Increment/Decrementtapdelayinput
+        LD=> '1',    --1-bitinput:LoadIDELAY_VALUEinput
+        LDPIPEEN=> '0',--1-bitinput:EnablePIPELINEregistertoloaddatainput
+        REGRST=> s_rst_cal    --1-bitinput:Active-highresettap-delayinput
+    );
+        
+
+--    IODELAY2_Delayed : IODELAY2
+--    generic map (
+--        COUNTER_WRAPAROUND => "STAY_AT_LIMIT",  -- "STAY_AT_LIMIT" or "WRAPAROUND" 
+--        DATA_RATE          => "SDR",         -- "SDR" or "DDR" 
+--        DELAY_SRC          => "IDATAIN",     -- "IO", "ODATAIN" or "IDATAIN" 
+--        SERDES_MODE        => "NONE", 			-- <NONE>, MASTER, SLAVE
+--        IDELAY_TYPE        => "VARIABLE_FROM_HALF_MAX",
+--        IDELAY_VALUE       => 0,             -- Amount of taps for fixed input delay (0-255)
+--        IDELAY2_VALUE      => 0             	-- Delay value when IDELAY_MODE="PCI" (0-255)
+--    --SIM_TAPDELAY_VALUE => 10              -- Per tap delay used for simulation in ps
+--    )
+--    port map (
+--        BUSY     => s_busy_idelay_d,      -- 1-bit output: Busy output after CAL
+--        DATAOUT  => s_Data_i_d_d,     -- 1-bit output: Delayed data output to ISERDES/input register
+--        DATAOUT2 => open,             -- 1-bit output: Delayed data output to general FPGA fabric
+--        DOUT     => open,             -- 1-bit output: Delayed data output
+--        TOUT     => open,             -- 1-bit output: Delayed 3-state output
+--        CAL      => s_cal,      		-- 1-bit input: Initiate calibration input
+--        CE       => '0',              -- 1-bit input: Enable INC input
+--        CLK      => fabricClk_i,      -- 1-bit input: Clock input
+--        IDATAIN  => data_i,           -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+--        INC      => '0',              -- 1-bit input: Increment / decrement input
+--        IOCLK0   => fastClk_i,        -- 1-bit input: Input from the I/O clock network
+--        IOCLK1   => '0',              -- 1-bit input: Input from the I/O clock network
+--        ODATAIN  => '0',              -- 1-bit input: Output data input from output register or OSERDES2.
+--        RST      => s_rst_cal,          -- 1-bit input: reset_i to zero
+--        T        => '1'               -- 1-bit input: 3-state input signal
+--    );
+
+
+    --I must check that the CNTVALUEOUT and CNTVALUEIN are the same. TO DO
+	--status_o(0) <= s_busy_idelay_d;
+	s_busy_idelay_d <= (delay_val(0) XOR  delayed_out(0)) OR (delay_val(1) XOR  delayed_out(1)) OR (delay_val(2) XOR  delayed_out(2)) OR (delay_val(3) XOR  delayed_out(3)) OR (delay_val(4) XOR  delayed_out(4));
+	status_o(0) <= s_busy_idelay_d;
+	s_busy <= s_busy_idelay_p or s_busy_idelay_d;
+
+
+-----------------------------------------------------
+--ISERDES2 replaced by ISERDESE2 in Series 7
+--  ISERDES2_Prompt : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,         -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",         -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,           -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",     -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"         -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--    -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(1),         -- Oldest data
+--    Q2     => s_Data_o(3),
+--    Q3     => s_Data_o(5),
+--    Q4     => s_Data_o(7),         -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,       -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,                 -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                  -- 1-bit input Bitslip enable input
+--    CE0     => '1',                  -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,            -- 1-bit input I/O clock network input
+--    CLK1    => '0',                  -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,          -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_p,         -- 1-bit input Input data
+--    IOCE    => strobe_i,             -- 1-bit input Data strobe_i input
+--    RST     => reset_i,              -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                   -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+
+    ISERDESE2_Prompt: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+    generic map (
+        DATA_RATE => "DDR",
+        DATA_WIDTH => 4,
+        INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+        IOBDELAY => "BOTH", --same as above
+        SERDES_MODE => "MASTER",
+        NUM_CE => 1
+    )
+    port map (
+        O => open,
+        Q4     => s_Data_o(1), -- Oldest data
+        Q3     => s_Data_o(3),
+        Q2     => s_Data_o(5),
+        Q1     => s_Data_o(7),
+        BITSLIP => '0',
+        CE1 => '1',
+        CE2 => '1',
+        CLKDIVP => '0',
+        CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+        CLKB  => not fastClk_i, --should be a unique phase shifted clock
+        CLKDIV => fabricClk_i,
+        DDLY=> s_Data_i_d_p,
+        D=> '0', -- data_i
+        RST=> reset_i,
+        SHIFTIN1 => '0',
+        SHIFTIN2 => '0',
+        DYNCLKDIVSEL=> '0',
+        DYNCLKSEL=> '0', 
+        --OCLK => strobe_i,
+        OCLK => '0',
+        OCLKB => '0',
+        OFB=> '0'
+    );
+
+--  ISERDES2_Delayed : ISERDES2
+--  generic map (
+--    BITSLIP_ENABLE => FALSE,       -- Enable Bitslip Functionality (TRUE/FALSE)
+--    DATA_RATE      => "SDR",       -- Data-rate ("SDR" or "DDR")
+--    DATA_WIDTH     => 4,         -- Parallel data width selection (2-8)
+--    INTERFACE_TYPE => "RETIMED",   -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED" 
+--    SERDES_MODE    => "NONE"       -- "NONE", "MASTER" or "SLAVE" 
+--   )
+--  port map (
+--	-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+--    Q1     => s_Data_o(0),           -- oldest data
+--    Q2     => s_Data_o(2),
+--    Q3     => s_Data_o(4),
+--    Q4     => s_Data_o(6),           -- most recent data
+--    --SHIFTOUT => SHIFTOUTsig,     -- 1-bit output Cascade output signal for master/slave I/O
+--    VALID   => open,               -- 1-bit output Output status of the phase detector
+--    BITSLIP => '0',                -- 1-bit input Bitslip enable input
+--    CE0     => '1',                -- 1-bit input Clock enable input
+--    CLK0    => fastClk_i,          -- 1-bit input I/O clock network input
+--    CLK1    => '0',                -- 1-bit input Secondary I/O clock network input
+--    CLKDIV  => fabricClk_i,        -- 1-bit input FPGA logic domain clock input
+--    D       => s_Data_i_d_d,       -- 1-bit input Input data
+--    IOCE    => strobe_i,           -- 1-bit input Data strobe_i input
+--    RST     => reset_i,            -- 1-bit input Asynchronous reset_i input
+--    SHIFTIN => '0'                 -- 1-bit input Cascade input signal for master/slave I/O
+--   );
+   
+   
+   ISERDESE2_Delayed: ISERDESE2 --Used to replace ISERDES2. Best of luck with it.
+       generic map (
+           DATA_RATE => "DDR",
+           DATA_WIDTH => 4,
+           INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
+           IOBDELAY => "BOTH", --same as above
+           SERDES_MODE => "MASTER",
+           NUM_CE => 1
+       )
+       port map (
+           O => open,
+           Q4     => s_Data_o(0),           -- oldest data
+           Q3     => s_Data_o(2),
+           Q2     => s_Data_o(4),
+           Q1     => s_Data_o(6), 
+           BITSLIP => '0',
+           CE1 => '1',
+           CE2 => '1',
+           CLKDIVP => '0',
+           CLK  => fastClk_i,            -- 1-bit input I/O clock network input
+           CLKB  => not fastClk_i, --should be a unique phase shifted clock
+           CLKDIV => fabricClk_i,
+           DDLY=> s_Data_i_d_d,
+           D=> '0', -- data_i
+           RST=> reset_i,
+           SHIFTIN1 => '0',
+           SHIFTIN2 => '0',
+           DYNCLKDIVSEL=> '0',
+           DYNCLKSEL=> '0', 
+           OCLK => strobe_i,
+           OCLKB => '0',
+           OFB=> '0'
+       );
+-----------------------------------------------------
+
+
+
+reg_out : process(fabricClk_i)
+begin
+  if rising_edge(fabricClk_i) then
+    Data_o <= s_Data_o;
+  end if;
+end process;
+
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4443faf09d8ea7b4404309f8a38526f389ade458
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl.vhd
@@ -0,0 +1,291 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    -- Instantiate one for each trigger input of the TLU
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        -- Differential buffer. Receives differential trigger input and produces a buffered differential signal.
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+        
+        -- Deserialize the trigger input    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            --data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+        
+        -- Add last bit from previous word to the new deserialized data.        
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        -- Use a LUT to determine the leading/trailing edges of the trigger input
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..106e7703ceb450d9081a1a68b86aafbc3ec4aa01
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_BKP.vhd
@@ -0,0 +1,335 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            data_i_pos     => threshold_discr_p_i(triggerInput),
+            data_i_neg     => threshold_discr_n_i(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+--REMOVE CFD        
+--        CFDInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_CFD_discr_input(triggerInput),
+--            I  => CFD_discr_p_i(triggerInput),
+--            IB => CFD_discr_n_i(triggerInput)
+--            );
+    
+--        CFDDeserializer: entity work.dualSERDES_1to4
+--          port map (
+--            reset_i => s_rst_iserdes,
+--            --calibrate_i => s_calibrate_idelay,
+--            data_i         => s_CFD_discr_input(triggerInput),
+--            fastClk_i      => clk_16x_logic_i,
+--            fabricClk_i    => clk_4x_logic,
+--            strobe_i       => strobe_16x_logic_i,
+--            data_o         => s_deserialized_CFD_data(triggerInput),
+--            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+--            );
+--        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+--        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+--        CFDLUT : entity work.arrivalTimeLUT
+--          port map (
+--            clk_4x_logic_i      => clk_4x_logic,
+--            strobe_4x_logic_i   => strobe_4x_logic_i,
+--            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+--            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+--            last_falling_edge_time_o => open, 
+--            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+--            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+--            multiple_edges_o    => open
+--            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              
+            --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9e3a01e19f1004dfd39bad1c31b25d478a4091df
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_newTLU_rtl_fastClock.vhd
@@ -0,0 +1,301 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.ipbus.all;
+USE work.ipbus_reg_types.all;
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs_newTLU IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;--1
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      clk_200_i : IN     std_logic;
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_8x_logic_i      : IN     std_logic;                                          --! 320MHz clock ( 8x 40MHz )
+      strobe_8x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 8x clock.
+   );
+
+-- Declarations
+END triggerInputs_newTLU ;
+
+--
+ARCHITECTURE rtl OF triggerInputs_newTLU IS
+  
+    signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+    signal s_threshold_discr_input , s_thr_in_p, s_thr_in_n : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+    type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+    signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+    type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+    signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+    --signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+    --signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    --signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+    signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    --signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+    signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+    signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+    signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+    signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+    constant c_N_CTRL : positive := 1;
+    constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+    signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+    --  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+    -----------------------------------------------------------------------------
+    -- IPBus interface 
+    -----------------------------------------------------------------------------
+
+    -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+    -- by synchronizer.
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+        N_STAT =>  c_N_STAT )
+    port map(
+        clk=> ipbus_clk_i,
+        reset => ipbus_reset_i ,
+        ipbus_in =>  ipbus_i,
+        ipbus_out => ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb => open
+        );
+
+    -- sync data from I/O logic to IPBus
+    sync_registers: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic,
+        data_i      => s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- sync data from I/O logic to IPBus
+    sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      => s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic);
+
+    -- Map the control registers...
+    -- Register that controls IODELAY and ISERDES reset is at address 0
+    s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+    s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+    s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+    s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+    s_status_to_ipbus(0)(1) <= s_counter_reset;
+    s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+    -- Connect up unused lines in status regiser to 0.
+    s_status_to_ipbus(0)(3) <= '0';
+    s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+    -----------------------------------------------------------------------------
+    -- Connect up trigger inputs to deserializers and a LUT to determine
+    -- arrival time
+    -----------------------------------------------------------------------------
+    idelaytriggers0: idelayctrl port map(
+          refclk => clk_200_i,
+          rst => reset_i
+    );
+ 
+    --BEGIN FOR LOOP
+    trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+--        thresholdInputBuffer: IBUFDS
+--          generic map (
+--            DIFF_TERM        => true,
+--            IBUF_LOW_PWR     => false,
+--            IOSTANDARD       => "LVDS_25")
+--          port map (
+--            O  => s_threshold_discr_input(triggerInput),
+--            I  => threshold_discr_p_i(triggerInput),
+--            IB => threshold_discr_n_i(triggerInput)
+--            );
+    
+        IBUFDS_DIFF_OUT_inst : IBUFDS_DIFF_OUT
+        generic map (
+            IBUF_LOW_PWR => false,
+            IOSTANDARD       => "LVDS_25"
+        )
+        port map (
+            O => s_thr_in_p(triggerInput),
+            OB => s_thr_in_n(triggerInput),
+            I => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+        );
+            
+        thresholdDeserializer: entity work.dualSERDES_1to4
+        port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            --data_i         => s_threshold_discr_input(triggerInput),
+            data_i         => '0',
+            data_i_pos     => s_thr_in_p(triggerInput),
+            data_i_neg     => s_thr_in_n(triggerInput),
+            fastClk_i      => clk_8x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_8x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+        );
+                  
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+            
+        thresholdLUT : entity work.arrivalTimeLUT
+        port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+        );
+        
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+            
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+            if rising_edge(clk_4x_logic) then
+                s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+                --s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+                -- Monitor output of serdes - just look at one per serdes
+                -- Don't care about latency so put a couple of registers in to aid
+                -- timing closure.
+                s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+                --s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+            end if ; 
+        end process;
+        
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+        generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+            clock_i  => clk_4x_logic,
+            reset_i  => s_counter_reset,
+            enable_i => s_edge_rising(triggerInput),
+            result_o => s_status_to_ipbus(triggerInput+1)
+        );
+    end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3d83e3d60baa144ef7e6b9a53cd86f97a08dfafd
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerInputs_rtl.vhd
@@ -0,0 +1,338 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--------------------------------------------------------------------------------
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) 
+--! Based on TDC code by Alvaro Dosil
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--!
+--! @date 15:43:57 11/08/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \li IPBus address 0 = control and status
+--!  \li bit0 = reset serdes
+--!  \li bit1 = reset counter
+--!  \li bit2 = calibrate IDELAYs
+--!  \li bit3 = not connected
+--!  \li bit4 = Thresh discr  IDelay(0) status prompt
+--!  \li bit5 = Thresh discr  IDelay(0) status delayed
+--!  \li bit6 = Thresh discr  IDelay(1) status prompt
+--!  \li bit7 = Thresh discr  IDelay(1) status delayed
+--!  \li bit8 = Thresh discr  IDelay(2) status prompt
+--!  \li bit9 = Thresh discr  IDelay(2) status delayed
+--!  \li bit10= Thresh discr  IDelay(3) status prompt
+--!  \li bit11= Thresh discr  IDelay(3) status delayed
+--!  \li bit12= CFD discr  IDelay(0) status prompt
+--!  \li bit13= CFD discr  IDelay(0) status delayed
+--!  \li bit14= CFD discr  IDelay(1) status prompt
+--!  \li bit15= CFD discr  IDelay(1) status delayed
+--!  \li bit16= CFD discr  IDelay(2) status prompt
+--!  \li bit17= CFD discr  IDelay(2) status delayed
+--!  \li bit18= CFD discr  IDelay(3) status prompt
+--!  \li bit19= CFD discr  IDelay(3) status delayed
+--!  \li bit20= Thresh deserialized data monitor(0)
+--!  \li bit21= Thresh deserialized data monitor(1)
+--!  \li bit22= Thresh deserialized data monitor(2)
+--!  \li bit23= Thresh deserialized data monitor(3)
+--!  \li bit24= CFD deserialized data monitor(0)
+--!  \li bit25= CFD deserialized data monitor(1)
+--!  \li bit26= CFD deserialized data monitor(2)
+--!  \li bit27= CFD deserialized data monitor(3)
+--!
+--! \li IPBus address 1 = edge rising(0) counter
+--! \li IPBus address 2 = edge rising(1) counter
+--! \li IPBus address 3 = edge rising(2) counter
+--! \li IPBus address 4 = edge rising(3) counter
+--!
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author: 
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence 
+--
+
+ENTITY triggerInputs IS
+   GENERIC( 
+      g_NUM_INPUTS  : natural  := 1;
+      g_IPBUS_WIDTH : positive := 32
+   );
+   PORT( 
+      cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Inputs from constant-fraction discriminators
+      cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! Input from CFD
+      clk_4x_logic         : IN     std_logic;                                          --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i    : IN     std_logic;                                          --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! inputs from threshold comparators
+      reset_i              : IN     std_logic;
+      trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);  --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);       --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);         --! High when falling edge
+      ipbus_clk_i          : IN     std_logic;
+      ipbus_reset_i        : IN     std_logic;
+      ipbus_i              : IN     ipb_wbus;                                           --! Signals from IPBus core to slave
+      ipbus_o              : OUT    ipb_rbus;                                           --! signals from slave to IPBus core
+      clk_16x_logic_i      : IN     std_logic;                                          --! 640MHz clock ( 16x 40MHz )
+      strobe_16x_logic_i   : IN     std_logic                                           --! Pulses one cycle every 4 of 16x clock.
+   );
+
+-- Declarations
+
+END triggerInputs ;
+
+--
+ARCHITECTURE rtl OF triggerInputs IS
+  
+  signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+  
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
+
+  type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+  signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+  type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+  signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+  signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+  
+  signal s_CFD_rising_edge                : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  signal s_CFD_falling_edge               : std_logic_vector(g_NUM_INPUTS-1 downto 0); 
+  
+  signal s_threshold_previous_late_bit    : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
+  
+  signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+
+  constant c_N_CTRL : positive := 1;
+  constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+  signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+--  signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+  signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+
+  -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+  -- by synchronizer.
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map (
+      N_STAT =>  c_N_STAT )
+    port map(
+      clk=> ipbus_clk_i,
+      reset => ipbus_reset_i ,
+      ipbus_in =>  ipbus_i,
+      ipbus_out => ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb => open
+      );
+
+  -- sync data from I/O logic to IPBus
+  sync_registers: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic,
+      data_i      => s_status_to_ipbus,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+  -- sync data from I/O logic to IPBus
+  sync_ipbus: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      => s_control_from_ipbus,
+      data_o      => s_sync_control_from_ipbus,
+      clk_output_i => clk_4x_logic);
+
+  -- Map the control registers...
+  -- Register that controls IODELAY and ISERDES reset is at address 0
+  s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+  s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+  s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+  
+  s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+  s_status_to_ipbus(0)(1) <= s_counter_reset;
+  s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+  -- Connect up unused lines in status regiser to 0.
+  s_status_to_ipbus(0)(3) <= '0';
+  s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+  -----------------------------------------------------------------------------
+  -- Connect up trigger inputs to deserializers and a LUT to determine
+  -- arrival time
+  -----------------------------------------------------------------------------
+ 
+  --BEGIN FOR LOOP
+  trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+        thresholdInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_threshold_discr_input(triggerInput),
+            I  => threshold_discr_p_i(triggerInput),
+            IB => threshold_discr_n_i(triggerInput)
+            );
+    
+        thresholdDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i 			=> s_rst_iserdes,
+            --calibrate_i 		=> s_calibrate_idelay,
+            data_i         => s_threshold_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_threshold_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+            );
+              
+          --s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
+        s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+        thresholdLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+            first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+            last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+            rising_edge_o       => s_edge_rising(triggerInput), 
+            falling_edge_o      => s_edge_falling(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        -- The leading edge may be a high-->low or a low-->high transition (
+        -- depending on polarity of input signal. ). For now assume that leading
+        -- edge is low-->high and connect trigger times and trigger output accordingly.
+        -- In the future have this selectable.
+        edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+        edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+        edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+        trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+        trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+        
+        
+        CFDInputBuffer: IBUFDS
+          generic map (
+            DIFF_TERM        => true,
+            IBUF_LOW_PWR     => false,
+            IOSTANDARD       => "LVDS_25")
+          port map (
+            O  => s_CFD_discr_input(triggerInput),
+            I  => CFD_discr_p_i(triggerInput),
+            IB => CFD_discr_n_i(triggerInput)
+            );
+    
+        CFDDeserializer: entity work.dualSERDES_1to4
+          port map (
+            reset_i => s_rst_iserdes,
+            --calibrate_i => s_calibrate_idelay,
+            data_i         => s_CFD_discr_input(triggerInput),
+            fastClk_i      => clk_16x_logic_i,
+            fabricClk_i    => clk_4x_logic,
+            strobe_i       => strobe_16x_logic_i,
+            data_o         => s_deserialized_CFD_data(triggerInput),
+            status_o       => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+            );
+        --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+          
+        s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+        CFDLUT : entity work.arrivalTimeLUT
+          port map (
+            clk_4x_logic_i      => clk_4x_logic,
+            strobe_4x_logic_i   => strobe_4x_logic_i,
+            deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+            first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+            last_falling_edge_time_o => open, 
+            rising_edge_o       => s_CFD_rising_edge(triggerInput),
+            falling_edge_o      => s_CFD_falling_edge(triggerInput),
+            multiple_edges_o    => open
+            );
+    
+        p_register_delayed_bits : process ( clk_4x_logic ) 
+        begin 
+          if rising_edge(clk_4x_logic) then
+            s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+              --s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
+            s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+    
+            -- Monitor output of serdes - just look at one per serdes
+            -- Don't care about latency so put a couple of registers in to aid
+            -- timing closure.
+            s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+            s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+        
+          end if ; 
+        end process;
+    
+        --! Instantiate counter for output triggers.
+        --! Input I is connected to address I+1
+        cmp_inputTriggerCounter : entity work.counterWithReset
+          generic map (
+            g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+        port map (
+          clock_i  => clk_4x_logic,
+          reset_i  => s_counter_reset,
+          enable_i => s_edge_rising(triggerInput),
+          result_o => s_status_to_ipbus(triggerInput+1));
+    
+  end generate trigger_input_loop;
+  --END FOR LOOP
+  
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
+  --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+  --! Monitor output of deserializer
+  -- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_status_to_ipbus(0)(23 downto 20);
+  --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <=  s_edge_rising;
+  trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+  trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <=  s_edge_rising;
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerLogic_rtl.vhd b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2ff175d3ccf6b58d7699686491eb531962146051
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/hdl/trigger/triggerLogic_rtl.vhd
@@ -0,0 +1,355 @@
+--=============================================================================
+--! @file triggerLogic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+-- 
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+--! @brief Produces triggers from either trigger inputs or internal generator
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--! @date 16:06:19 11/09/12
+--!
+--! @version v0.1
+--!
+--! @details
+--! \br IPBus address map:
+--! \li 0x00000000 RO - Number of triggers issued since last reset.
+--! \li 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)
+--! \li 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i
+--! \li 0x00000011 RW - trigger pattern - value that gets loaded into CFGLUT5
+--! \li 0x00000100 RW - bit-0 - internal trigger veto. Set high to halt triggers.
+--! \li 0x00000101 RO - state of external veto
+--! \li 0x00000110 RW - stretch of pulses. Additional width = 0-31 clock cycles.
+--! \li 0x00000111 RW - delay of pulses. 0-31 clock cycles.
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+--! Add stretchPulse and coincidenceLogic entities. May/15 , David Cussans
+-------------------------------------------------------------------------------
+ENTITY triggerLogic IS
+   GENERIC( 
+      g_NUM_INPUTS  : positive := 4; 
+      g_IPBUS_WIDTH : positive := 32 
+   );
+   PORT( 
+      clk_4x_logic_i      : IN     std_logic;                                     -- ! Rising edge active
+      ipbus_clk_i         : IN     std_logic;
+      ipbus_i             : IN     ipb_wbus;                                      -- Signals from IPBus core to slave
+      ipbus_reset_i       : IN     std_logic;
+      logic_reset_i       : IN     std_logic;                                     -- active high. Synchronous with clk_4x_logic
+      logic_strobe_i      : IN     std_logic;                                     -- ! Pulses high once every 4 cycles of clk_4x_logic
+      trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active
+      trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      veto_i              : IN     std_logic;                                     -- ! Halts triggers when high
+      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger from input connector active and enabled
+      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time
+      event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);   -- starts at one. Increments for each post_veto_trigger
+      ipbus_o             : OUT    ipb_rbus;                                      -- signals from slave to IPBus core
+      post_veto_trigger_o : OUT    std_logic;                                     -- ! goes high when trigger passes
+      pre_veto_trigger_o  : OUT    std_logic;
+      trigger_active_o    : OUT    std_logic                                      --! Goes high when triggers are active ( ie. not veoted)
+   );
+
+-- Declarations
+
+END triggerLogic ;
+
+--
+ARCHITECTURE rtl OF triggerLogic IS
+
+    --! vector that stores trigger output for each combination of trigger inputs.
+    signal s_trigger_inputs_enabled , s_trigger_inputs_enabled_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := x"00000001";--(others=>'1');  
+    signal s_external_trigger_p , s_external_trigger_l , s_auxTrigger , s_internal_veto , s_internal_veto_ipb : std_logic := '0';
+    signal s_internal_trigger_interval: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- setting s_internal_trigger_interval to zero means no internal triggers
+    signal s_pre_veto_trigger_counter , s_post_veto_trigger_counter , s_aux_trigger_counter: unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto
+    signal s_pre_veto_trigger_counter_ipb , s_post_veto_trigger_counter_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- ! counters for triggers before and after veto, on ipbus clock domain
+    
+    signal s_triggers : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) := (others=>'0');
+    signal s_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) := (others=>(others=>'0'));
+    signal s_internal_trigger, s_internal_trigger_d : std_logic := '0';  -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
+    --  signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation
+    signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  -- counter for internal trigger generation and counter delay
+    signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0';  -- ! Goes high when internal trigger is running.
+    
+    --  signal s_logic_reset ,  s_logic_reset_ipb : std_logic := '0';  -- ! Take high to reset counters etc.
+    signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0';  -- ! Can't read from an output port so keep internal copy
+    
+    signal s_TriggerPattern_low : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (low 32-bits)
+    signal s_TriggerPattern_high : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Pattern to load into LUT for trigger generation (high 32-bits)
+    
+    signal s_PulseStretchWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseWidthWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --! Length of trigger pulses
+    signal s_PulseDelayWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');  --!number of cycles to delay trigger pulses.
+    signal s_TriggerHoldOffWord : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! minimum number of clock cycles between triggers
+    
+    constant c_PARAM_WIDTH : positive := 5;    -- length of pulse width and delay.
+    constant c_BYTE_WIDTH : positive := 5;    --Length of padded field for parameters. This should be at least equal to c_PARAM_WIDTH.
+                                              --If c_BYTE_WIDTH= 8 then the values are aligned to bytes in the 32-bit word (but we cannot store 6 of them...)
+                                              --If c_BYTE_WIDTH=5 then all the values are one after the other.
+    
+    constant c_N_CTRL : positive := 16;
+    constant c_N_STAT : positive := 16;
+    signal s_controlRegStrobes : std_logic_vector(c_N_CTRL-1 downto 0) := ( others => '0') ; --!
+                                                                             --Bit strobes when control reg is loaded
+    signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+    signal s_control_from_ipbus,s_sync_control_from_ipbus  : ipb_reg_v(c_N_CTRL-1 downto 0);
+    signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+    signal s_loadTriggerPattern , s_loadTriggerPattern_p1 : std_logic := '0';  -- take high to load trigger pattern
+    signal s_loadTriggerPatternHi , s_loadTriggerPatternHi_p1 : std_logic := '0';  -- take high to load trigger pattern
+    
+    signal s_delayedTriggerTimes, s_delayedTriggerTimes_d1, s_delayedTriggerTimes_d2 : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! Array of std_logic_vectors
+    signal s_stretchedTriggers ,  s_stretchedTriggers_d1 ,  s_stretchedTriggers_d2 : std_logic_vector( trigger_i'range) := (others => '0');  -- --! Triggers after stretch and delay
+    
+    COMPONENT internalTriggerGenerator
+    PORT (
+        CLK : IN STD_LOGIC;
+        CE : IN STD_LOGIC;
+        LOAD : IN STD_LOGIC;
+        L : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+        Q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    END COMPONENT;
+  
+BEGIN
+  -----------------------------------------------------------------------------
+  -- IPBus interface 
+  -----------------------------------------------------------------------------
+    ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+        N_CTRL => c_N_CTRL,
+        N_STAT => c_N_STAT
+    )
+    port map(
+        clk => ipbus_clk_i,
+        reset=> '0',--ipbus_reset_i ,
+        ipbus_in=>  ipbus_i,
+        ipbus_out=> ipbus_o,
+        d=>  s_sync_status_to_ipbus,
+        q=>  s_control_from_ipbus,
+        stb=> s_controlRegStrobes
+    );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_STAT )
+    port map (
+        clk_input_i => clk_4x_logic_i,
+        data_i      =>  s_status_to_ipbus,
+        data_o      => s_sync_status_to_ipbus,
+        clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+        g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+        clk_input_i => ipbus_clk_i,
+        data_i      =>  s_control_from_ipbus,
+        data_o      => s_sync_control_from_ipbus,
+        clk_output_i => clk_4x_logic_i);
+
+  -- Map the control registers
+  -- workaround to match the number of clock cycles with the configured interval
+    s_internal_trigger_interval <= x"00000000" when s_sync_control_from_ipbus(2)<x"00000005" else
+										std_logic_vector(unsigned(s_sync_control_from_ipbus(2))-2);
+										
+    --s_TriggerPattern_low <= s_control_from_ipbus(3);
+    s_LoadTriggerPattern_p1 <= s_controlRegStrobes(10);
+    s_LoadTriggerPatternHi_p1 <= s_controlRegStrobes(11);
+    s_veto_word <= s_sync_control_from_ipbus(4);
+    s_internal_veto <= s_veto_word(0);
+    s_PulseWidthWord <= s_sync_control_from_ipbus(6);
+    s_PulseDelayWord <= s_sync_control_from_ipbus(7);
+    s_TriggerHoldOffWord <= s_sync_control_from_ipbus(8);
+    s_TriggerPattern_low <= s_control_from_ipbus(10);
+    s_TriggerPattern_high <= s_control_from_ipbus(11);
+    --s_PulseWidthWord <=s_sync_control_from_ipbus(10);
+    
+    s_external_veto_word(0) <= veto_i;
+    s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
+    
+    -- Map the status registers
+    s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
+    s_status_to_ipbus(1) <= std_logic_vector(s_pre_veto_trigger_counter);
+    s_status_to_ipbus(2) <= s_internal_trigger_interval;
+    --s_status_to_ipbus(3) <= s_TriggerPattern_low;
+    s_status_to_ipbus(4) <= s_veto_word;
+    s_status_to_ipbus(5) <= s_external_veto_word;
+    s_status_to_ipbus(6) <= s_PulseWidthWord; 
+    s_status_to_ipbus(7) <= s_PulseDelayWord; --fixed in addr. map
+    s_status_to_ipbus(8) <= s_TriggerHoldOffWord;
+    s_status_to_ipbus(9) <= std_logic_vector(s_aux_trigger_counter);-- not used and never updated. Remove at some point.
+    s_status_to_ipbus(10) <= s_TriggerPattern_low;
+    s_status_to_ipbus(11) <= s_TriggerPattern_high;
+
+    -- purpose: Delay pulse that loads trigger pattern by one cycle of IPBus clk.
+    -- type   : combinational
+    -- inputs : ipbus_clk_i
+    -- outputs: 
+    p_delayLoadPulse: process (ipbus_clk_i) is
+    begin  -- process p_delayLoadPulse
+    if rising_edge(ipbus_clk_i) then
+        s_LoadTriggerPattern <= s_LoadTriggerPattern_p1;
+        s_LoadTriggerPatternHi <= s_LoadTriggerPatternHi_p1;
+    end if;
+    end process p_delayLoadPulse;
+
+  -- Stretch and delay pulses.
+  --D Put in delay for trigger times as well.
+  
+    --
+    gen_stretchVals: for v_inputNumber in 0 to g_NUM_INPUTS-1 generate
+        cmp_stretchPulse: entity work.stretchPulse
+        generic map (
+            g_PARAM_WIDTH => c_PARAM_WIDTH)
+        port map (
+            clk_i         => clk_4x_logic_i,
+            pulse_i       => trigger_i(v_inputNumber),
+            pulse_o       => s_stretchedTriggers(v_inputNumber),
+            triggerTime_i => trigger_times_i(v_inputNumber),
+            triggerTime_o => s_delayedTriggerTimes(v_inputNumber),
+    --        pulsewidth_i  => s_PulseStretchWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulsewidth_i  => s_PulseWidthWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH ),
+            pulseDelay_i  => s_PulseDelayWord( (v_inputNumber*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto v_inputNumber*c_BYTE_WIDTH )
+    --        pulsewidth_i  => s_PulseStretchWord( (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH ),
+    --        pulseDelay_i  => s_PulseDelayWord(   (0*c_BYTE_WIDTH) + c_PARAM_WIDTH -1 downto 0*c_BYTE_WIDTH )
+            );
+    end generate gen_stretchVals;
+
+  --! Trigger coincidence logic 
+    cmp_coincidence_logic : entity work.coincidenceLogic
+    generic map(
+        g_nInputs	=> g_NUM_INPUTS,
+        g_patternWidth => g_IPBUS_WIDTH
+    )
+    Port map( 
+        configClk_i 	=> ipbus_clk_i, --! No point in moving off IPBus clock
+        logicClk_i        => clk_4x_logic_i,
+        triggers_i 	=> s_stretchedTriggers,
+        trigger_o         => s_external_trigger_l,
+        --auxTrigger_o      => s_auxTrigger,
+        -- Control ports...
+        triggerPattern_low_i  => s_TriggerPattern_low,
+        triggerPattern_high_i  => s_TriggerPattern_high,
+        loadPatternHi_i     => s_loadTriggerPatternHi,
+        loadPatternLo_i     => s_loadTriggerPattern
+        );
+	
+  --! just look for the rising edge ( with long stretch can get multiple clock
+  --! cycle triggers )
+    cmp_triggerRisingEdge : entity work.single_pulse
+    port map (
+        level => s_external_trigger_l,
+        clk => clk_4x_logic_i,
+        pulse => s_external_trigger_p
+        );
+  
+  --! Produce triggers....
+    trigGen : process  ( clk_4x_logic_i ) 
+    begin 
+        if rising_edge(clk_4x_logic_i)  then 
+            s_post_veto_trigger <= (s_external_trigger_p or s_internal_trigger) and (not ( s_internal_veto or veto_i) );
+            s_pre_veto_trigger <= (s_external_trigger_p or s_internal_trigger);
+    
+            -- delay output of which input triggers fired so that they go high at the
+            -- same time as the pre/post veto trigger signals.
+            s_stretchedTriggers_d1 <= s_stretchedTriggers;
+            s_stretchedTriggers_d2 <= s_stretchedTriggers_d1;
+                                                            
+            s_delayedTriggerTimes_d1 <= s_delayedTriggerTimes;
+            s_delayedTriggerTimes_d2 <= s_delayedTriggerTimes_d1;
+             
+            trigger_o <= s_stretchedTriggers_d2;
+            trigger_times_o <= s_delayedTriggerTimes_d2; -- trigger_times_i;  -- put delayed version of trigger times here
+        end if;
+    end process;
+	
+
+    pre_veto_trigger_o <= s_pre_veto_trigger ;
+    post_veto_trigger_o <= s_post_veto_trigger;
+    trigger_active_o <= s_post_veto_trigger;
+
+	
+	--! Internal trigger generator
+    p_internal_triggers: process (clk_4x_logic_i )
+    begin  -- process p_internal_triggers
+        if rising_edge(clk_4x_logic_i) then
+            if (s_internal_trigger_interval = x"00000000") then
+                s_internal_trigger_active <= '0';
+            else
+                s_internal_trigger_active <= '1';
+            end if;
+        
+            s_internal_trigger_active_d <= s_internal_trigger_active;    -- signal delayed
+            s_internal_trigger_timer_d <= s_internal_trigger_timer;      -- Signal delayed
+        end if;
+    end process p_internal_triggers;
+  
+    s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" )) else '0';
+				
+				
+				
+    -- Use a coregen counter to allow timing constraints to be met.
+    --c_internal_triggers: entity work.internalTriggerGenerator
+    c_internal_triggers: internalTriggerGenerator
+    PORT MAP (
+        clk => clk_4x_logic_i,
+        ce => s_internal_trigger_active,
+        load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
+        l => s_internal_trigger_interval,
+        q => s_internal_trigger_timer
+    );
+  
+  -----------------------------------------------------------------------------
+  -- Count triggers
+  -----------------------------------------------------------------------------
+    p_trigger_counter: process (clk_4x_logic_i )
+    begin  -- process p_trigger_counter
+        if rising_edge(clk_4x_logic_i) then
+            if logic_reset_i = '1' then
+                s_post_veto_trigger_counter <= ( others => '0');
+            elsif s_post_veto_trigger = '1' then
+                s_post_veto_trigger_counter <= s_post_veto_trigger_counter + 1;
+            end if;
+            
+            if logic_reset_i = '1' then
+                s_pre_veto_trigger_counter <= ( others => '0');
+            elsif s_pre_veto_trigger = '1' then
+                s_pre_veto_trigger_counter <= s_pre_veto_trigger_counter + 1;
+            end if;
+            
+            --if logic_reset_i = '1' then
+            --    s_aux_trigger_counter <= ( others => '0');
+            --elsif s_auxTrigger = '1' then
+            --    s_aux_trigger_counter <= s_aux_trigger_counter + 1;
+            --end if;
+        end if;
+    end process p_trigger_counter;
+ 
+    event_number_o <= std_logic_vector(s_post_veto_trigger_counter);
+  
+END ARCHITECTURE rtl;
+
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/AIDA_testScript.py b/AIDA_tlu/legacy/TLU_v1e/scripts/AIDA_testScript.py
new file mode 100644
index 0000000000000000000000000000000000000000..4a8f6bf931dab3e56bc375f6b24d542e12d755ce
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/AIDA_testScript.py
@@ -0,0 +1,183 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0xFF)# 0= normal
+IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(0, 0xFF)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x4F)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/TLU_v1e.py b/AIDA_tlu/legacy/TLU_v1e/scripts/TLU_v1e.py
new file mode 100644
index 0000000000000000000000000000000000000000..9f45a4f35b5dc2cd202bbad0ad6b0e8df2a91888
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/TLU_v1e.py
@@ -0,0 +1,898 @@
+# -*- coding: utf-8 -*-
+import uhal;
+import pprint;
+import ConfigParser
+#from FmcTluI2c import *
+import threading
+from ROOT import TFile, TTree, gROOT, AddressOf
+from ROOT import *
+import time
+
+from I2CuHal import I2CCore
+from si5345 import si5345 # Library for clock chip
+from AD5665R import AD5665R # Library for DAC
+from PCA9539PW import PCA9539PW # Library for serial line expander
+
+class TLU:
+    """docstring for TLU"""
+    def __init__(self, dev_name, man_file, parsed_cfg):
+
+        self.isRunning= False
+
+        section_name= "Producer.fmctlu"
+        self.dev_name = dev_name
+
+        #man_file= parsed_cfg.get(section_name, "ConnectionFile")
+        self.manager= uhal.ConnectionManager(man_file)
+        self.hw = self.manager.getDevice(self.dev_name)
+
+        # #Get Verbose setting
+        self.verbose= parsed_cfg.getint(section_name, "verbose")
+
+        #self.nDUTs= 4 #Number of DUT connectors
+        self.nDUTs= parsed_cfg.getint(section_name, "nDUTs")
+
+        #self.nChannels= 6 #Number of trigger inputs
+        self.nChannels= parsed_cfg.getint(section_name, "nTrgIn")
+
+        #self.VrefInt= 2.5 #Internal DAC voltage reference
+        self.VrefInt= parsed_cfg.getfloat(section_name, "VRefInt")
+
+        #self.VrefExt= 1.3 #External DAC voltage reference
+        self.VrefExt= parsed_cfg.getfloat(section_name, "VRefExt")
+
+        #self.intRefOn= False #Internal reference is OFF by default
+        self.intRefOn= int(parsed_cfg.get(section_name, "intRefOn"))
+
+
+        self.fwVersion = self.hw.getNode("version").read()
+        self.hw.dispatch()
+        print "TLU V1E FIRMWARE VERSION= " , hex(self.fwVersion)
+
+        # Instantiate a I2C core to configure components
+        self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
+        #self.TLU_I2C.state()
+
+        enableCore= True #Only need to run this once, after power-up
+        self.enableCore()
+
+        # Instantiate clock chip and configure it (if necessary)
+        #self.zeClock=si5345(self.TLU_I2C, 0x68)
+        clk_addr= int(parsed_cfg.get(section_name, "I2C_CLK_Addr"), 16)
+        self.zeClock=si5345(self.TLU_I2C, clk_addr)
+        res= self.zeClock.getDeviceVersion()
+        if (int(parsed_cfg.get(section_name, "CONFCLOCK"), 16)):
+            #clkRegList= self.zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+            clkRegList= self.zeClock.parse_clk(parsed_cfg.get(section_name, "CLOCK_CFG_FILE"))
+            self.zeClock.writeConfiguration(clkRegList)######
+
+        self.zeClock.checkDesignID()
+
+        # Instantiate DACs and configure them to use reference based on TLU setting
+        #self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
+        #self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
+        dac_addr1= int(parsed_cfg.get(section_name, "I2C_DAC1_Addr"), 16)
+        self.zeDAC1=AD5665R(self.TLU_I2C, dac_addr1)
+        dac_addr2= int(parsed_cfg.get(section_name, "I2C_DAC2_Addr"), 16)
+        self.zeDAC2=AD5665R(self.TLU_I2C, dac_addr2)
+        self.zeDAC1.setIntRef(self.intRefOn, self.verbose)
+        self.zeDAC2.setIntRef(self.intRefOn, self.verbose)
+
+        # Instantiate the serial line expanders and configure them to default values
+        #self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
+        exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1_Addr"), 16)
+        self.IC6=PCA9539PW(self.TLU_I2C, exp1_addr)
+        self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(0, 0xFF)# If output, set to XX
+
+        self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(1, 0xFF)# If output, set to XX
+
+        #self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
+        exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2_Addr"), 16)
+        self.IC7=PCA9539PW(self.TLU_I2C, exp2_addr)
+        self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(0, 0x00)# If output, set to XX
+
+        self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(1, 0xB0)# If output, set to XX
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def DUTOutputs_old(self, dutN, enable=False, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+        ## NOTE: This version changes all the pins together. Use DUTOutputs to control individual pins.
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "to", enable
+        if (verbose > 1):
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getOutputs(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newStatus= oldStatus & (~mask)
+        if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
+            newStatus |= mask
+        self.IC6.setOutputs(bank, newStatus)
+
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        return newStatus
+
+    def DUTOutputs(self, dutN, enable=0x7, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "pins status to", hex(enable)
+        if (verbose > 1):
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getOutputs(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newnibble= (enable & 0xF) << 4*nibble # bits we want to change are marked with 1
+        newStatus= (oldStatus & (~mask)) | (newnibble & mask)
+
+        self.IC6.setOutputs(bank, newStatus)
+
+        if (verbose > 0):
+            self.getDUTOutpus(dutN, verbose)
+        if (verbose > 1):
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+
+        return newStatus
+
+    def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
+        ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
+        ## clkSrc= 0: clock disabled
+        ## clkSrc= 1: clock from Si5345
+        ## clkSrc=2: clock from FPGA
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        if (clkSrc < 0) | (clkSrc> 2):
+            print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
+            return -1
+        bank=0
+        maskLow= 1 << (1* dutN) #CLK FROM FPGA
+        maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
+        mask= maskLow | maskHigh
+        res= self.IC7.getOutputs(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask #set both bits to zero
+        outStat= ""
+        if clkSrc==0:
+            newStatus = newStatus | mask
+            outStat= "disabled"
+        elif clkSrc==1:
+            newStatus = newStatus | maskLow
+            outStat= "Si5435"
+        elif clkSrc==2:
+            newStatus= newStatus | maskHigh
+            outStat= "FPGA"
+        print "  Setting DUT:", dutN, "clock source to", outStat
+        if (verbose > 1):
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setOutputs(bank, newStatus)
+        return newStatus
+
+    def enableClkLEMO(self, enable= False, verbose= False):
+        ## Enable or disable the output clock to the differential LEMO output
+        bank=1
+        mask= 0x10
+        res= self.IC7.getOutputs(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask
+        outStat= "enabled"
+        if (not enable): #A 0 activates the output. A 1 disables it.
+            newStatus= newStatus | mask
+            outStat= "disabled"
+        print "  Clk LEMO", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setOutputs(bank, newStatus)
+        return newStatus
+
+    def enableCore(self):
+        ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
+        ## This function enables the lines. It is only required once.
+        mystop=True
+        print "  Enabling I2C bus (expect 127):"
+        myslave= 0x21
+        mycmd= [0x01, 0x7F]
+        nwords= 1
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+
+        mystop=False
+        mycmd= [0x01]
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tPost RegDir: ", res
+
+    def getDUTOutpus(self, dutN, verbose=0):
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        res= self.IC6.getOutputs(bank)
+        dut_status= res[0]
+        dut_lines= ["CONT", "SPARE", "TRIG", "BUSY"]
+        dut_status= 0x0F & (dut_status >> (4*nibble))
+
+        if verbose > 0:
+            for idx, iLine in enumerate(dut_lines):
+                this_bit= 0x1 & (dut_status  >> idx)
+                if this_bit:
+                    this_status= "ENABLED"
+                else:
+                    this_status= "DISABLED"
+                print "\t", iLine, "output is", this_status
+
+        if verbose > 1:
+            print "\tDUT CURRENT:", hex(dut_status), "Nibble:", nibble, "Bank:", bank
+
+        return dut_status
+
+    def getAllChannelsCounts(self):
+        chCounts=[]
+        for ch in range (0,self.nChannels):
+            chCounts.append(int(self.getChCount(ch)))
+        return chCounts
+
+    def getChStatus(self):
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\tTRIGGER COUNTERS status= " , hex(inputStatus)
+        return inputStatus
+
+    def getChCount(self, channel):
+        regString= "triggerInputs.ThrCount"+ str(channel)+"R"
+        count = self.hw.getNode(regString).read()
+        self.hw.dispatch()
+        print "\tCh", channel, "Count:" , count
+        return count
+
+    def getClockStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "  CLOCK STATUS [expected 1]"
+        print "\t", hex(clockStatus)
+        if ( clockStatus == 0 ):
+            "ERROR: Clocks in TLU FPGA are not locked."
+        return clockStatus
+
+    def getDUTmask(self):
+        DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
+        self.hw.dispatch()
+        print "\tDUTMask read back as:" , hex(DUTMaskR)
+        return DUTMaskR
+
+    def getExternalVeto(self):
+        extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tEXTERNAL Veto read back as:", hex(extVeto)
+        return extVeto
+
+    def getFifoData(self, nWords):
+    	#fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
+    	fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
+    	self.hw.dispatch()
+    	#print "\tFIFO Data:", hex(fifoData)
+    	return fifoData
+
+    def getFifoLevel(self, verbose= 0):
+        FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
+        self.hw.dispatch()
+        if (verbose > 0):
+            print "\tFIFO level read back as:", hex(FifoFill)
+        return FifoFill
+
+    def getFifoCSR(self):
+        FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
+        self.hw.dispatch()
+        print "\tFIFO CSR read back as:", hex(FifoCSR)
+        return FifoCSR
+
+    def getFifoFlags(self):
+        # Useless?
+        FifoFLAG= self.hw.getNode("eventBuffer.EventFifoFillLevelFlags").read()
+        self.hw.dispatch()
+        print "\tFIFO FLAGS read back as:", hex(FifoFLAG)
+        return FifoFLAG
+
+    def getInternalTrg(self):
+        trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\tInternal interval read back as:", trigIntervalR
+        return trigIntervalR
+
+    def getMode(self):
+        DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
+        self.hw.dispatch()
+        print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
+        return DUTInterfaceModeR
+
+    def getModeModifier(self):
+        DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
+        self.hw.dispatch()
+        print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
+        return DUTInterfaceModeModifierR
+
+    def getSN(self):
+        epromcontent=self.readEEPROM(0xfa, 6)
+        print "  FMC-TLU serial number (EEPROM):"
+        result="\t"
+        for iaddr in epromcontent:
+            result+="%02x "%(iaddr)
+        print result
+        return epromcontent
+
+    def getPostVetoTrg(self):
+        triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
+        self.hw.dispatch()
+        print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
+        return triggerN
+
+    def getPulseDelay(self):
+        pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
+        self.hw.dispatch()
+        print "\tPulse delay read back as:", hex(pulseDelayR)
+        return pulseDelayR
+
+    def getPulseStretch(self):
+        pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
+        self.hw.dispatch()
+        print "\tPulse stretch read back as:", hex(pulseStretchR)
+        return pulseStretchR
+
+    def getRecordDataStatus(self):
+        RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
+        self.hw.dispatch()
+        print "\tData recording:", RecordStatus
+        return RecordStatus
+
+    def getTriggerVetoStatus(self):
+        trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tTrigger veto status read back as:", trgVetoStatus
+        return trgVetoStatus
+
+    def getTrgPattern(self):
+        triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
+        triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
+        self.hw.dispatch()
+        print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
+        return triggerPattern_low, triggerPattern_high
+
+    def getVetoDUT(self):
+        IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
+        self.hw.dispatch()
+        print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
+        return IgnoreDUTBusyR
+
+    def getVetoShutters(self):
+        IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
+        self.hw.dispatch()
+        print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
+        return IgnoreShutterVeto
+
+    def pulseT0(self):
+        cmd = int("0x1",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tPulsing T0"
+
+    def readEEPROM(self, startadd, bytes):
+        mystop= 1
+        time.sleep(0.1)
+        myaddr= [startadd]#0xfa
+        self.TLU_I2C.write( 0x50, [startadd], mystop)
+        res= self.TLU_I2C.read( 0x50, bytes)
+        return res
+
+    def resetClock(self):
+        # Set the RST pin from the PLL to 1
+        print "  Clocks reset"
+        cmd = int("0x1",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def resetClocks(self):
+        #Reset clock PLL
+        self.resetClock()
+        #Get clock status after reset
+        self.getClockStatus()
+        #Restore clock PLL
+        self.restoreClock()
+        #Get clock status after restore
+        self.getClockStatus()
+        #Get serdes status
+        self.getChStatus()
+
+    def resetCounters(self):
+    	cmd = int("0x2", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	cmd = int("0x0", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	#print "Trigger Reset: 0x%X" % restatus
+    	print "\tTrigger counters reset"
+
+    def resetSerdes(self):
+        cmd = int("0x3",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during reset = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after reset = " , hex(inputStatus)
+
+        cmd = int("0x4",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during calibration = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after calibration = " , hex(inputStatus)
+
+    def restoreClock(self):
+        # Set the RST pin from the PLL to 0
+        print "  Clocks restore"
+        cmd = int("0x0",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def setChStatus(self, cmd):
+        self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "  INPUT STATUS SET TO= " , hex(inputStatus)
+
+    def setClockStatus(self, cmd):
+        # Only use this for testing. The clock source is actually selected in the Si5345.
+        self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
+        self.hw.dispatch()
+
+    def setDUTmask(self, DUTMask):
+        print "  DUT MASK ENABLING: Mask= " , hex(DUTMask)
+        self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
+        self.hw.dispatch()
+        self.getDUTmask()
+
+    def setFifoCSR(self, cmd):
+        self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
+        self.hw.dispatch()
+        self.getFifoCSR()
+
+    def setInternalTrg(self, triggerInterval):
+        print "  TRIGGERS INTERNAL:"
+        if triggerInterval == 0:
+            internalTriggerFreq = 0
+            print "\tdisabled"
+        else:
+            internalTriggerFreq = 160000000.0/triggerInterval
+            print "\tRequired internal trigger frequency:", triggerInterval, "Hz"
+            print "\tSetting internal interval to:", internalTriggerFreq
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
+        self.hw.dispatch()
+        self.getInternalTrg()
+
+    def setMode(self, mode):
+        print "  DUT MODE SET TO: ", hex(mode)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
+        self.hw.dispatch()
+        self.getMode()
+
+    def setModeModifier(self, modifier):
+        print "  DUT MODE MODIFIER:", hex(modifier)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
+        self.hw.dispatch()
+        self.getModeModifier()
+
+    def setPulseDelay(self, inArray):
+        print "  TRIGGER DELAY SET TO", inArray, "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
+        pulseDelay= self.packBits(inArray)
+        self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
+        self.hw.dispatch()
+        self.getPulseDelay()
+
+    def setPulseStretch(self, inArray):
+        print "  INPUT COINCIDENCE WINDOW SET TO", inArray ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
+        pulseStretch= self.packBits(inArray)
+        self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
+        self.hw.dispatch()
+        self.getPulseStretch()
+
+    def setRecordDataStatus(self, status=False):
+        print "  Data recording set:"
+        self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
+        self.hw.dispatch()
+        self.getRecordDataStatus()
+
+    def setTriggerVetoStatus(self, status=False):
+        self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
+        self.hw.dispatch()
+        self.getTriggerVetoStatus()
+
+    def setTrgPattern(self, triggerPatternH, triggerPatternL):
+        triggerPatternL &= 0xffffffff
+        triggerPatternH &= 0xffffffff
+        print "  TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
+        self.hw.dispatch()
+        self.getTrgPattern()
+
+    def setVetoDUT(self, ignoreDUTBusy):
+        print "  VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
+        self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
+        self.hw.dispatch()
+        self.getVetoDUT()
+
+    def setVetoShutters(self, newState):
+        if newState:
+            print "  IgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
+            cmd= int("0x0",16)
+        else:
+            print "  IgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
+            cmd= int("0x1",16)
+        self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
+        self.hw.dispatch()
+        self.getVetoShutters()
+
+    def writeThreshold(self, DACtarget, Vtarget, channel, verbose=False):
+        #Writes the threshold. The DAC voltage differs from the threshold voltage because
+        #the range is shifted to be symmetrical around 0V.
+
+        #Check if the DACs are using the internal reference
+        if (self.intRefOn):
+            Vref= self.VrefInt
+        else:
+            Vref= self.VrefExt
+
+        #Calculate offset voltage (because of the following shifter)
+        Vdac= ( Vtarget + Vref ) / 2
+        print"  THRESHOLD setting:"
+        if channel==7:
+            print "\tCH: ALL"
+        else:
+            print "\tCH:", channel
+        print "\tTarget V:", Vtarget
+        dacValue = 0xFFFF * (Vdac / Vref)
+        DACtarget.writeDAC(int(dacValue), channel, verbose)
+
+    def packBits(self, raw_values):
+        packed_bits= 0
+        if (len(raw_values) != self.nChannels):
+            print "Error (packBits): wrong number of elements in array"
+        else:
+            for idx, iCh in enumerate(raw_values):
+                tmpint= iCh << idx*5
+                packed_bits= packed_bits | tmpint
+        print "\tPacked =", hex(packed_bits)
+        return packed_bits
+
+    def parseFifoData(self, fifoData, nEvents, mystruct, root_tree, verbose):
+        #for index in range(0, len(fifoData)-1, 6):
+        outList= []
+        for index in range(0, (nEvents)*6, 6):
+            word0= (fifoData[index] << 32) + fifoData[index + 1]
+            word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
+            word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
+            evType= (fifoData[index] & 0xF0000000) >> 28
+            inTrig= (fifoData[index] & 0x0FFF0000) >> 16
+            tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
+            fineTs= fifoData[index + 2]
+            evNum= fifoData[index + 3]
+            fineTsList=[-1]*12
+            fineTsList[3]= (fineTs & 0x000000FF)
+            fineTsList[2]= (fineTs & 0x0000FF00) >> 8
+            fineTsList[1]= (fineTs & 0x00FF0000) >> 16
+            fineTsList[0]= (fineTs & 0xFF000000) >> 24
+            fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
+            fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
+            fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
+            fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
+            fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
+            fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
+            fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
+            fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
+            if verbose:
+                print "====== EVENT", evNum, "================================================="
+                print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
+                print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
+                print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
+                print fineTsList
+            fineTsList.insert(0, tStamp)
+            fineTsList.insert(0, evNum)
+            if (root_tree != None):
+                highWord= word0
+                lowWord= word1
+                extWord= word2
+                timeStamp= tStamp
+                bufPos= 0
+                evtNumber= evNum
+                evtType= evType
+                trigsFired= inTrig
+                mystruct.raw0= fifoData[index]
+                mystruct.raw1= fifoData[index+1]
+                mystruct.raw2= fifoData[index+2]
+                mystruct.raw3= fifoData[index+3]
+                mystruct.raw4= fifoData[index+4]
+                mystruct.raw5= fifoData[index+5]
+                mystruct.evtNumber= evNum
+                mystruct.tluTimeStamp= tStamp
+                mystruct.tluEvtType= evType
+                mystruct.tluTrigFired= inTrig
+                root_tree.Fill()
+
+            outList.insert(len(outList), fineTsList)
+        #print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
+        #print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
+        #pprint.pprint(outList)
+        return outList
+
+    def plotFifoData(self, outList):
+        import matplotlib.pyplot as plt
+        import numpy as np
+        import matplotlib.mlab as mlab
+
+        coarseColumn= [row[1] for row in outList]
+        fineColumn= [row[2] for row in outList]
+        timeStamp= [sum(x) for x in zip(coarseColumn, fineColumn)]
+        correctTs= [-1]*len(coarseColumn)
+        coarseVal= 0.000000025 #coarse time value (40 Mhz, 25 ns)
+        fineVal=   0.00000000078125 #fine time value (1280 MHz, 0.78125 ns)
+        for iTs in range(0, len(coarseColumn)):
+            correctTs[iTs]= coarseColumn[iTs]*coarseVal + fineColumn[iTs]*fineVal
+            #if iTs:
+                #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
+
+        xdiff = np.diff(correctTs)
+        np.all(xdiff[0] == xdiff)
+        P= 1000000000 #display in ns
+        nsDeltas = [x * P for x in xdiff]
+        #centerRange= np.mean(nsDeltas)
+        centerRange= 476
+        windowsns= 30
+        minRange= centerRange-windowsns
+        maxRange= centerRange+windowsns
+        plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+        #plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+        #plt.xlim((min(nsDeltas), max(nsDeltas)))
+        plt.xlabel('Time (ns)')
+        plt.ylabel('Entries')
+        plt.title('Histogram DeltaTime')
+        plt.grid(True)
+
+        #Superimpose Gauss
+        mean = np.mean(nsDeltas)
+        variance = np.var(nsDeltas)
+        sigma = np.sqrt(variance)
+        x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+        plt.plot(x, mlab.normpdf(x, mean, sigma))
+
+        #Display plot
+        plt.show()
+
+    def saveFifoData(self, outList):
+        import csv
+        with open("output.csv", "wb") as f:
+            writer = csv.writer(f)
+            writer.writerows(outList)
+
+##################################################################################################################################
+##################################################################################################################################
+    def acquire(self, mystruct, root_tree= None):
+        print "STARTING ACQUIRE LOOP"
+        print "Run#" , self.runN, "\n"
+        self.isRunning= True
+        index=0
+        while (self.isRunning == True):
+            eventFifoFillLevel= self.getFifoLevel(0)
+            nFifoWords= int(eventFifoFillLevel)
+            if (nFifoWords > 0):
+                fifoData= self.getFifoData(nFifoWords)
+                outList= self.parseFifoData(fifoData, nFifoWords/6, mystruct, root_tree, False)
+
+            time.sleep(0.1)
+            index= index + nFifoWords/6
+        print "STOPPING ACQUIRE LOOP:", index, "events collected"
+        return index
+
+    def configure(self, parsed_cfg):
+        print "\nTLU INITIALIZING..."
+        section_name= "Producer.fmctlu"
+
+        #READ CONTENT OF EPROM VIA I2C
+        self.getSN()
+
+        print "  Turning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        # #Get Verbose setting
+        self.verbose= parsed_cfg.getint(section_name, "verbose")
+
+
+        # #SET DACs
+        self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold0"), 1, self.verbose)
+        self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold1"), 0, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold2"), 3, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold3"), 2, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold4"), 1, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold5"), 0, self.verbose)
+
+        #
+        # #ENABLE/DISABLE HDMI OUTPUTS
+        self.DUTOutputs(0, int(parsed_cfg.get(section_name, "HDMI1_set"), 16) , self.verbose)
+        self.DUTOutputs(1, int(parsed_cfg.get(section_name, "HDMI2_set"), 16) , self.verbose)
+        self.DUTOutputs(2, int(parsed_cfg.get(section_name, "HDMI3_set"), 16) , self.verbose)
+        self.DUTOutputs(3, int(parsed_cfg.get(section_name, "HDMI4_set"), 16) , self.verbose)
+
+        # #SELECT CLOCK SOURCE TO HDMI
+        self.DUTClkSrc(0, int(parsed_cfg.get(section_name, "HDMI1_clk"), 16) , self.verbose)
+        self.DUTClkSrc(1, int(parsed_cfg.get(section_name, "HDMI2_clk"), 16) , self.verbose)
+        self.DUTClkSrc(2, int(parsed_cfg.get(section_name, "HDMI3_clk"), 16) , self.verbose)
+        self.DUTClkSrc(3, int(parsed_cfg.get(section_name, "HDMI4_clk"), 16) , self.verbose)
+
+        # #ENABLE/DISABLE LEMO CLOCK OUTPUT
+        self.enableClkLEMO(parsed_cfg.getint(section_name, "LEMOclk"), False)
+
+        #
+        # #Check clock status
+        self.getClockStatus()
+
+        resetClocks = 0
+        resetSerdes = 0
+        resetCounters= 0
+        if resetClocks:
+            self.resetClocks()
+            self.getClockStatus()
+        if resetSerdes:
+            self.resetSerdes()
+        if resetCounters:
+	    self.resetCounters()
+
+        # # Get inputs status and counters
+        self.getChStatus()
+        self.getAllChannelsCounts()
+
+        # # Stop internal triggers until setup complete
+        cmd = int("0x0",16)
+        self.setInternalTrg(cmd)
+
+        # # Set pulse stretches
+        str0= parsed_cfg.getint(section_name, "in0_STR")
+        str1= parsed_cfg.getint(section_name, "in1_STR")
+        str2= parsed_cfg.getint(section_name, "in2_STR")
+        str3= parsed_cfg.getint(section_name, "in3_STR")
+        str4= parsed_cfg.getint(section_name, "in4_STR")
+        str5= parsed_cfg.getint(section_name, "in5_STR")
+        self.setPulseStretch([str0, str1, str2, str3, str4, str5])
+
+        # # Set pulse delays
+        del0= parsed_cfg.getint(section_name, "in0_DEL")
+        del1= parsed_cfg.getint(section_name, "in1_DEL")
+        del2= parsed_cfg.getint(section_name, "in2_DEL")
+        del3= parsed_cfg.getint(section_name, "in3_DEL")
+        del4= parsed_cfg.getint(section_name, "in4_DEL")
+        del5= parsed_cfg.getint(section_name, "in5_DEL")
+        self.setPulseDelay([del0, del1, del2, del3, del4, del5])
+
+        # # Set trigger pattern
+        triggerPattern_low= int(parsed_cfg.get(section_name, "trigMaskLo"), 16)
+        triggerPattern_high= int(parsed_cfg.get(section_name, "trigMaskHi"), 16)
+        self.setTrgPattern(triggerPattern_high, triggerPattern_low)
+
+        # # Set active DUTs
+        DUTMask= int(parsed_cfg.get(section_name, "DutMask"), 16)
+        self.setDUTmask(DUTMask)
+
+        # # Set mode (AIDA, EUDET)
+        DUTMode= int(parsed_cfg.get(section_name, "DUTMaskMode"), 16)
+        self.setMode(DUTMode)
+
+        # # Set modifier
+        modifier = int(parsed_cfg.get(section_name, "DUTMaskModeModifier"), 16)
+        self.setModeModifier(modifier)
+
+        # # Set veto shutter
+        setVetoShutters = int(parsed_cfg.get(section_name, "DUTIgnoreShutterVeto"), 16)
+        self.setVetoShutters(setVetoShutters)
+
+        # # Set veto by DUT
+        ignoreDUTBusy = int(parsed_cfg.get(section_name, "DUTIgnoreBusy"), 16)
+        self.setVetoDUT(ignoreDUTBusy)
+
+        print "  Check external veto:"
+        self.getExternalVeto()
+
+        # # Set trigger interval (use 0 to disable internal triggers)
+        triggerInterval= parsed_cfg.getint(section_name, "InternalTriggerFreq")
+        self.setInternalTrg(triggerInterval)
+
+        print "TLU INITIALIZED"
+
+##################################################################################################################################
+##################################################################################################################################
+    def start(self, logtimestamps=False, runN=0, mystruct= None, root_tree= None):
+        print "TLU STARTING..."
+        self.runN= runN
+
+        print "  FIFO RESET:"
+        FIFOcmd= 0x2
+        self.setFifoCSR(FIFOcmd)
+        eventFifoFillLevel= self.getFifoLevel()
+        #cmd = int("0x000",16)
+        #self.setInternalTrg(cmd)
+
+        if logtimestamps:
+            self.setRecordDataStatus(True)
+        else:
+            self.setRecordDataStatus(False)
+
+        # Pulse T0
+        self.pulseT0()
+
+        print "  Turning off software trigger veto"
+        self.setTriggerVetoStatus( int("0x0",16) )
+
+        print "TLU STARTED"
+
+        nEvents= self.acquire(mystruct, root_tree)
+        return
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def stop(self, saveD= False, plotD= False):
+        print "TLU STOPPING..."
+
+        self.getPostVetoTrg()
+        eventFifoFillLevel= self.getFifoLevel()
+        self.getFifoFlags()
+        self.getFifoCSR()
+        print "  Turning on software trigger veto"
+        self.setTriggerVetoStatus( int("0x1",16) )
+
+        nFifoWords= int(eventFifoFillLevel)
+        fifoData= self.getFifoData(nFifoWords)
+
+        outList= self.parseFifoData(fifoData, nFifoWords/6, None, None, True)
+        if saveD:
+            self.saveFifoData(outList)
+        if plotD:
+            self.plotFifoData(outList)
+        #outFile = open('./test.txt', 'w')
+        #for iData in range (0, 30):
+    	#    outFile.write("%s\n" % fifoData[iData])
+        #    print hex(fifoData[iData])
+        print "TLU STOPPED"
+        return
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/TLUaddrmap.xml b/AIDA_tlu/legacy/TLU_v1e/scripts/TLUaddrmap.xml
new file mode 100644
index 0000000000000000000000000000000000000000..65fb5340f2155f8c5c92d96a2ef66d8dcb209d41
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/TLUaddrmap.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/TLUconnection.xml b/AIDA_tlu/legacy/TLU_v1e/scripts/TLUconnection.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fca67f50d932c760c77aa5553bfa983ca8fff249
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/TLUconnection.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="tlu" uri="ipbusudp-2.0://192.168.200.30:50001"
+   address_table="file://./TLUaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/datafiles/20171020_122611_tluData_1.root b/AIDA_tlu/legacy/TLU_v1e/scripts/datafiles/20171020_122611_tluData_1.root
new file mode 100644
index 0000000000000000000000000000000000000000..71ed872acceb600852a81aea7df130f7b8c8590d
Binary files /dev/null and b/AIDA_tlu/legacy/TLU_v1e/scripts/datafiles/20171020_122611_tluData_1.root differ
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/initTLU.py b/AIDA_tlu/legacy/TLU_v1e/scripts/initTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/initTLU.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/localClock.txt b/AIDA_tlu/legacy/TLU_v1e/scripts/localClock.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0a7b2d94878a6766e41c9b39bfd4fa2a2ebc9e95
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/localClock.txt
@@ -0,0 +1,394 @@
+# Si538x/4x Registers Export
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
+# Design ID: TLU1E_01
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
+# Created On: 2017-08-24 13:37:41 GMT+01:00
+Address,Data
+0x0B24,0xD8
+0x0B25,0x00
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0x88
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x07
+0x002D,0x15
+0x002E,0x37
+0x002F,0x00
+0x0030,0x37
+0x0031,0x00
+0x0032,0x37
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x37
+0x0037,0x00
+0x0038,0x37
+0x0039,0x00
+0x003A,0x37
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x77
+0x0040,0x04
+0x0041,0x0C
+0x0042,0x0C
+0x0043,0x0C
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x32
+0x0048,0x32
+0x0049,0x00
+0x004A,0x32
+0x004B,0x32
+0x004C,0x32
+0x004D,0x00
+0x004E,0x55
+0x004F,0x05
+0x0051,0x03
+0x0052,0x03
+0x0053,0x03
+0x0054,0x00
+0x0055,0x03
+0x0056,0x03
+0x0057,0x03
+0x0058,0x00
+0x0059,0x3F
+0x005A,0xCC
+0x005B,0xCC
+0x005C,0xCC
+0x005D,0x00
+0x005E,0xCC
+0x005F,0xCC
+0x0060,0xCC
+0x0061,0x00
+0x0062,0xCC
+0x0063,0xCC
+0x0064,0xCC
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x30
+0x009D,0x00
+0x009E,0x20
+0x00A0,0x00
+0x00A2,0x02
+0x00A8,0x89
+0x00A9,0x70
+0x00AA,0x07
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x01
+0x013B,0xCC
+0x013C,0x00
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x14
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x14
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x01
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x14
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x01
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x54
+0x026C,0x4C
+0x026D,0x55
+0x026E,0x31
+0x026F,0x45
+0x0270,0x5F
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x14
+0x0509,0x23
+0x050A,0x0C
+0x050B,0x0B
+0x050C,0x03
+0x050D,0x3F
+0x050E,0x17
+0x050F,0x2B
+0x0510,0x09
+0x0511,0x08
+0x0512,0x03
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xA4
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x05
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x42
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x08
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x07
+0x094A,0x07
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x00
+0x0B48,0x08
+0x0B4A,0x1E
+0x0514,0x01
+0x001C,0x01
+0x0B24,0xDB
+0x0B25,0x02
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/localConf.conf b/AIDA_tlu/legacy/TLU_v1e/scripts/localConf.conf
new file mode 100644
index 0000000000000000000000000000000000000000..dc4f66f16ef825dfb3cdc912352d71bb88bc8af0
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/localConf.conf
@@ -0,0 +1,86 @@
+[Producer.fmctlu]
+verbose= 1
+confid= 20170626
+delayStart= 1000
+
+# HDMI pin direction:
+# 4-bits to determine direction of HDMI pins
+# 1-bit for the clock pair
+# 0= pins are not driving signals, 1 pins drive signals (outputs)
+HDMI1_set= 0x7
+HDMI2_set= 0x7
+HDMI3_set= 0x7
+HDMI4_set= 0x7
+HDMI1_clk = 1
+HDMI2_clk = 1
+HDMI3_clk = 1
+HDMI4_clk = 1
+
+# Enable/disable differential LEMO CLOCK
+LEMOclk = 1
+
+# Set delay and stretch for trigger pulses
+in0_STR = 1
+in0_DEL = 0
+in1_STR = 1
+in1_DEL = 0
+in2_STR = 1
+in2_DEL = 0
+in3_STR = 1
+in3_DEL = 0
+in4_STR = 1
+in4_DEL = 0
+in5_STR = 1
+in5_DEL = 0
+#
+trigMaskHi = 0x00000000
+trigMaskLo = 0x00000002
+#
+#### DAC THRESHOLD
+DACThreshold0 = -0.12
+DACThreshold1 = -0.12
+DACThreshold2 = -0.12
+DACThreshold3 = -0.12
+DACThreshold4 = -0.12
+DACThreshold5 = -0.12
+
+# Define which DUTs are ON
+DutMask = 1
+
+# Define mode of DUT (00 EUDET, 11 AIDA)
+DUTMaskMode= 0xFFFFFFFF
+
+# Allow asynchronous veto
+DUTMaskModeModifier= 0x0
+
+# Ignore busy from a specific DUT
+DUTIgnoreBusy = 0x0
+
+# Ignore the SHUTTER veto on a specific DUT
+DUTIgnoreShutterVeto = 0x0
+
+# Generate internal triggers (in Hz, 0= no triggers)
+InternalTriggerFreq = 10
+
+
+
+[LogCollector.log]
+# Currently, all LogCollectors have a hardcoded runtime name: log
+# nothing
+
+
+[DataCollector.my_dc]
+EUDAQ_MON=my_mon
+# send assambled event to the monitor with runtime name my_mon;
+EUDAQ_FW=native
+# the format of data file
+EUDAQ_FW_PATTERN=$12D_run$6R$X
+# the name pattern of data file
+# the $12D will be converted a data/time string with 12 digits.
+# the $6R will be converted a run number string with 6 digits.
+# the $X will be converted the suffix name of data file.
+
+[Monitor.my_mon]
+EX0_ENABLE_PRINT=0
+EX0_ENABLE_STD_PRINT=0
+EX0_ENABLE_STD_CONVERTER=1
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/localIni.ini b/AIDA_tlu/legacy/TLU_v1e/scripts/localIni.ini
new file mode 100644
index 0000000000000000000000000000000000000000..4592056461043ea1888451819c4c133fba7bf6f3
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/localIni.ini
@@ -0,0 +1,43 @@
+[Producer.fmctlu]
+initid= 20170703
+verbose = 1
+ConnectionFile= "file://./../user/eudet/misc/fmctlu_connection.xml"
+DeviceName="fmctlu.udp"
+TLUmod= "1e"
+# number of HDMI inputs, leave 4 even if you only use fewer inputs
+nDUTs = 4
+nTrgIn = 6
+# 0= False (Internal Reference OFF), 1= True
+intRefOn = 0
+VRefInt = 2.5
+VRefExt = 1.3
+# I2C address of the bus expander on Enclustra FPGA
+I2C_COREEXP_Addr = 0x21
+# I2C address of the Si5345
+I2C_CLK_Addr = 0x68
+# I2C address of 1st AD5665R
+I2C_DAC1_Addr = 0x13
+# I2C address of 2nd AD5665R
+I2C_DAC2_Addr = 0x1F
+# address of unique Id number EEPROM
+I2C_ID_Addr = 0x50
+#I2C address of 1st expander PCA9539PW
+I2C_EXP1_Addr = 0x74
+#I2C address of 2st expander PCA9539PW
+I2C_EXP2_Addr = 0x75
+
+##CONFCLOCK 0= skip clock configuration, 1= configure si5345
+CONFCLOCK= 0
+CLOCK_CFG_FILE = /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localClock.txt
+
+
+[LogCollector.log]
+# Currently, all LogCollectors have a hardcoded runtime name: log
+EULOG_GUI_LOG_FILE_PATTERN = myexample_$12D.log
+# the $12D will be converted a data/time string with 12 digits.
+
+[DataCollector.my_dc]
+# nothing
+
+[Monitor.my_mon]
+# nothing
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.py b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.py
new file mode 100644
index 0000000000000000000000000000000000000000..1961e0176f8bd9aa76373975ede0a7280971e007
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.py
@@ -0,0 +1,235 @@
+# -*- coding: utf-8 -*-
+# miniTLU test script
+
+#from PyChipsUser import *
+#from FmcTluI2c import *
+import uhal
+import sys
+import time
+from datetime import datetime
+import threading
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from TLU_v1e import TLU
+# Use to have interactive shell
+import cmd
+
+# Use to have config file parser
+import ConfigParser
+
+# Use root
+from ROOT import TFile, TTree, gROOT, AddressOf
+from ROOT import *
+import numpy as numpy
+
+
+## Define class that creates the command user inteface
+class MyPrompt(cmd.Cmd):
+
+    # def do_initialise(self, args):
+    #     """Processes the INI file and writes its values to the TLU. To use a specific file type:\n
+    #     parseIni path/to/filename.ini\n
+    #     (without quotation marks)"""
+    # 	print "COMMAND RECEIVED: PARSE INI"
+    # 	parsed_cfg= self.open_cfg_file(args, "/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localIni.ini")
+    #     try:
+    #         theID = parsed_cfg.getint("Producer.fmctlu", "initid")
+    #         print theID
+    #         theSTRING= parsed_cfg.get("Producer.fmctlu", "ConnectionFile")
+    #         print theSTRING
+    #         #TLU= TLU("tlu", theSTRING, parsed_cfg)
+    #     except IOError:
+    #         print "\t Could not retrieve INI data."
+    #         return
+
+
+    def do_configure(self, args):
+        """Processes the CONF file and writes its values to the TLU. To use a specific file type:\n
+        parseIni path/to/filename.conf\n
+        (without quotation marks)"""
+    	print "==== COMMAND RECEIVED: PARSE CONFIG"
+    	#self.testme()
+        parsed_cfg= self.open_cfg_file(args, "./localConf.conf")
+        try:
+            theID = parsed_cfg.getint("Producer.fmctlu", "confid")
+            print "\t", theID
+            TLU.configure(parsed_cfg)
+        except IOError:
+            print "\t Could not retrieve CONF data."
+            return
+
+    def do_id(self, args):
+        """Interrogates the TLU and prints it unique ID on screen"""
+        TLU.getSN()
+        return
+
+    def do_triggers(self, args):
+        """Interrogates the TLU and prints the number of triggers seen by the input discriminators"""
+        TLU.getChStatus()
+        TLU.getAllChannelsCounts()
+        TLU.getPostVetoTrg()
+        return
+
+    def do_startRun(self, args):
+        """Starts the TLU run. If a number is specified, this number will be appended to the file name as Run_#"""
+    	print "==== COMMAND RECEIVED: STARTING TLU RUN"
+    	#startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno run# specified, using 1"
+            runN= 1
+        else:
+            runN= arglist[0]
+
+        logdata= True
+
+        #TLU.start(logdata)
+        if (TLU.isRunning): #Prevent double start
+            print "  Run already in progress"
+            return
+        else:
+            now = datetime.now().strftime('%Y%m%d_%H%M%S')
+            default_filename = "./datafiles/"+ now + "_tluData_" + str(runN) + ".root"
+            rootFname= default_filename
+            print "OPENING ROOT FILE:", rootFname
+            self.root_file = TFile( rootFname, 'RECREATE' )
+            # Create a root "tree"
+            root_tree = TTree( 'T', 'TLU Data' )
+            #highWord =0
+            #lowWord =0
+            #evtNumber=0
+            #timeStamp=0
+            #evtType=0
+            #trigsFired=0
+            #bufPos = 0
+
+            #https://root-forum.cern.ch/t/long-integer/1961/2
+            gROOT.ProcessLine(
+            "struct MyStruct {\
+               UInt_t     raw0;\
+               UInt_t     raw1;\
+               UInt_t     raw2;\
+               UInt_t     raw3;\
+               UInt_t     raw4;\
+               UInt_t     raw5;\
+               UInt_t     evtNumber;\
+               ULong64_t     tluTimeStamp;\
+               UChar_t     tluEvtType;\
+               UChar_t     tluTrigFired;\
+            };" );
+
+            mystruct= MyStruct()
+
+
+            # Create a branch for each piece of data
+            root_tree.Branch('EVENTS', mystruct, 'raw0/i:raw1/i:raw2/i:raw3/i:raw4/i:raw5/i:evtNumber/i:tluTimeStamp/l:tluEvtType/b:tluTrigFired/b' )
+            # root_tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+            # root_tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+            # root_tree.Branch( 'tluExtWord'   , extWord   , "ExtWord/l")
+            # root_tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+            # root_tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+            # root_tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+            # root_tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+            # root_tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+            #self.root_file.Write()
+
+            daq_thread= threading.Thread(target = TLU.start, args=(logdata, runN, mystruct, root_tree))
+            daq_thread.start()
+
+    def do_endRun(self, args):
+    	"""Stops the TLU run"""
+    	print "==== COMMAND RECEIVED: STOP TLU RUN"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+        else:
+            print "  No run to stop"
+
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "==== COMMAND RECEIVED: QUITTING TLU CONSOLE"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+            print "Terminating run"
+	return True
+
+    def testme(self):
+        print "This is a test"
+
+    def open_cfg_file(self, args, default_file):
+        # Parse the user arguments, attempts to opent the file and performs a (minimal)
+        # check to verify the file exists (but not that its content is correct)
+
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno file specified, using default"
+            fileName= default_file
+            print "\t", fileName
+        else:
+            fileName= arglist[0]
+        if len(arglist) > 1:
+            print "\tinvalid: too many arguments. Max 1."
+            return
+
+        parsed_file = ConfigParser.RawConfigParser()
+        try:
+            with open(fileName) as f:
+                parsed_file.readfp(f)
+                print "\t", parsed_file.sections()
+        except IOError:
+            print "\t Error while parsing the specified file."
+            return
+        return parsed_file
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    print "TLU v1E MAIN"
+    prompt = MyPrompt()
+    prompt.prompt = '>> '
+
+    parsed_ini= prompt.open_cfg_file("", "./localIni.ini")
+    TLU= TLU("tlu", "file://./TLUconnection.xml", parsed_ini)
+
+    ###TLU.configure(parsed_cfg)
+    ###logdata= True
+    ###TLU.start(logdata)
+    ###time.sleep(5)
+    ###TLU.stop(False, False)
+
+    # Start interactive prompt
+    print "=+=================================================================="
+    print "==========================TLU TEST CONSOLE=========================="
+    print "+==================================================================="
+    prompt.cmdloop("Type 'help' for a list of commands.")
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.sh b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.sh
new file mode 100644
index 0000000000000000000000000000000000000000..f0bb38725bea4fdb33de6cb44f65cab9a3980d6d
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v1e.sh
@@ -0,0 +1,25 @@
+#!/bin/bash
+
+echo "=========================="
+CURRENT_DIR=${0%/*}
+echo "CURRENT DIRECTORY: " $CURRENT_DIR
+
+echo "============"
+echo "SETTING PATHS"
+#export PYTHONPATH=$CURRENT_DIR/../../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+#export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+export PYTHONPATH=../../packages:$PYTHONPATH
+echo "PYTHON PATH= " $PYTHONPATH
+export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
+echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
+export PATH=/usr/bin/:/opt/cactus/bin:$PATH
+echo "PATH= " $PATH
+
+cd $CURRENT_DIR
+
+echo "============"
+echo "STARTING PYTHON SCRIPT FOR TLU"
+#python $CURRENT_DIR/startTLU_v8.py $@
+
+python startTLU_v1e.py $@
+#python testTLU_script.py
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v6.py b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v6.py
new file mode 100644
index 0000000000000000000000000000000000000000..b7948f204682346e898a3126ac22b3e8aaa310a8
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/startTLU_v6.py
@@ -0,0 +1,232 @@
+#
+# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
+#
+# David Cussans, December 2012
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+
+import time
+
+from datetime import datetime
+
+from optparse import OptionParser
+
+# For single character non-blocking input:
+import select
+import tty
+import termios
+
+from initTLU import *
+
+def isData():
+    return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
+
+now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+default_filename = 'tluData_' + now + '.root'
+parser = OptionParser()
+
+parser.add_option('-r','--rootFname',dest='rootFname',
+                       default=default_filename,help='Path of output file')
+parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
+                       default="True",help='Set True to write timestamps to ROOT file')
+parser.add_option('-p','--printTimestamps',dest='printTimestamps',
+                       default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
+parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
+                       default=False,help='Set True to veto triggers when shutter goes high')
+parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
+                       default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
+parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
+                       default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
+parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
+                       default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
+parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
+                       default=0x01,help='Three-bit mask selecting which DUTs are active.')
+parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
+                       default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
+parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
+                       default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
+parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
+                       default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
+
+(options, args) = parser.parse_args(sys.argv[1:])
+
+from ROOT import TFile, TTree
+from ROOT import gROOT
+
+print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+
+# Point to board in uHAL
+manager = uhal.ConnectionManager("file://./connection.xml")
+hw = manager.getDevice("minitlu")
+device_id = hw.id()
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+# Assume DIP-switch controlled address. Switches at 2
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Open Root file
+print "OPENING ROOT FILE:", options.rootFname
+f = TFile( options.rootFname, 'RECREATE' )
+
+# Create a root "tree"
+tree = TTree( 'T', 'TLU Data' )
+highWord =0
+lowWord =0
+evtNumber=0
+timeStamp=0
+evtType=0
+trigsFired=0
+bufPos = 0
+
+# Create a branch for each piece of data
+tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+
+# Initialize TLU registers
+initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
+
+loopWait = 0.1
+oldEvtNumber = 0
+
+oldPreVetotriggerCount = board.read("PreVetoTriggersR")
+oldPostVetotriggerCount = board.read("PostVetoTriggersR")
+
+oldThresholdCounter0 =0
+oldThresholdCounter1 =0
+oldThresholdCounter2 =0
+oldThresholdCounter3 =0
+
+print "STARTING POLLING LOOP"
+
+eventFifoFillLevel = 0
+loopRunning = True
+runStarted = False
+
+oldTime = time.time()
+
+# Save old terminal settings
+oldTermSettings = termios.tcgetattr(sys.stdin)
+tty.setcbreak(sys.stdin.fileno())
+
+while loopRunning:
+
+    if isData():
+        c = sys.stdin.read(1)
+        print "\tGOT INPUT:", c
+        if c == 't':
+            loopRunning = False
+            print "\tTERMINATING LOOP"
+        elif c == 'c':
+            runStarted = True
+            print "\tSTARTING RUN"
+            startTLU( uhalDevice = hw, pychipsBoard = board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        elif c == 'f':
+            # runStarted = True
+            print "\tSTOPPING TRIGGERS"
+            stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+
+    if runStarted:
+
+        eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
+
+        preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
+        postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
+
+        timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
+        timestampLow  = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+
+        thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
+        thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
+        thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
+        thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
+
+        hw.dispatch()
+
+        newTime = time.time()
+        timeDelta = newTime - oldTime
+        oldTime = newTime
+        #print "time delta = " , timeDelta
+        preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
+        postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
+        oldPreVetotriggerCount = preVetotriggerCount
+        oldPostVetotriggerCount = postVetotriggerCount
+
+        deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
+        oldThresholdCounter0 = thresholdCounter0
+        deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
+        oldThresholdCounter1 = thresholdCounter1
+        deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
+        oldThresholdCounter2 = thresholdCounter2
+        deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
+        oldThresholdCounter3 = thresholdCounter3
+
+        print "pre , post  veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
+
+        print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
+
+        print "Input counts 0,1,2,3 = "      , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
+        print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
+
+        nEvents = int(eventFifoFillLevel)//4  # only read out whole events ( 4 x 32-bit words )
+        wordsToRead =  nEvents*4
+
+        print "FIFO FILL LEVEL= " , eventFifoFillLevel
+
+        print "# EVENTS IN FIFO = ",nEvents
+        print "WORDS TO READ FROM FIFO  = ",wordsToRead
+
+        # get timestamp data and fifo fill in same outgoing packet.
+        timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
+
+        hw.dispatch()
+
+    #    print timestampData
+        for bufPos in range (0, nEvents ):
+            lowWord  = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
+
+            highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
+            evtNumber = timestampData[bufPos*4 + 3]
+
+            if evtNumber != ( oldEvtNumber + 1 ):
+                print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ",  evtNumber , oldEvtNumber
+
+            oldEvtNumber = evtNumber
+
+            timeStamp = lowWord & 0xFFFFFFFFFFFF
+
+            evtType = timestampData[ (bufPos*4) + 0] >> 28
+
+            trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
+
+            if (options.printTimestamps == "True" ):
+                print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
+
+            # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
+            tree.Fill()
+
+    time.sleep( loopWait)
+
+# Fixme - at the moment infinite loop.
+preVetotriggerCount = board.read("PreVetoTriggersR")
+postVetotriggerCount = board.read("PostVetoTriggersR")
+print "EXIT POLLING LOOP"
+print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
+
+termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
+f.Write()
+f.Close()
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/test.py b/AIDA_tlu/legacy/TLU_v1e/scripts/test.py
new file mode 100644
index 0000000000000000000000000000000000000000..ac68201827840fbba1f2dad4c1c9596cba6ea9eb
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/test.py
@@ -0,0 +1,34 @@
+import matplotlib.pyplot as plt
+import numpy as np
+import matplotlib.mlab as mlab
+
+print "TEST.py"
+myFile= "./500ns_23ns.txt"
+
+with open(myFile) as f:
+    nsDeltas = map(float, f)
+
+P= 1000000000 #display in ns
+nsDeltas = [x * P for x in nsDeltas]
+centerRange= 25
+windowsns= 5
+minRange= centerRange-windowsns
+maxRange= centerRange+windowsns
+plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+#plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+#plt.xlim((min(nsDeltas), max(nsDeltas)))
+plt.xlabel('Time (ns)')
+plt.ylabel('Entries')
+plt.title('Histogram DeltaTime')
+plt.grid(True)
+
+#Superimpose Gauss
+mean = np.mean(nsDeltas)
+variance = np.var(nsDeltas)
+sigma = np.sqrt(variance)
+x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+plt.plot(x, mlab.normpdf(x, mean, sigma))
+print (mean, sigma)
+
+#Display plot
+plt.show()
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/testTLU_script.py b/AIDA_tlu/legacy/TLU_v1e/scripts/testTLU_script.py
new file mode 100644
index 0000000000000000000000000000000000000000..9d8b334bb4a6fd01050c3d622f54847616fce208
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/testTLU_script.py
@@ -0,0 +1,79 @@
+# miniTLU test script
+
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+from I2CuHal import I2CCore
+from miniTLU import MiniTLU
+from datetime import datetime
+
+if __name__ == "__main__":
+    print "\tTEST TLU SCRIPT"
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    #(self, target, wclk, i2cclk, name="i2c", delay=None)
+    TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
+    TLU_I2C.state()
+
+
+    #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
+    mystop= 1
+    time.sleep(0.1)
+    myaddr= [0xfa]
+    TLU_I2C.write( 0x50, myaddr, mystop)
+    res=TLU_I2C.read( 0x50, 6)
+    print "Checkin EEPROM:"
+    result="\t"
+    for iaddr in res:
+        result+="%02x "%(iaddr)
+    print result
+
+    #SCAN I2C ADDRESSES
+    #WRITE PROM
+    #WRITE DAC
+
+
+    #Convert required threshold voltage to DAC code
+    #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+    print("Writing DAC setting:")
+    Vref= 1.300
+    desiredVoltage= 3.3
+    channel= 0
+    i2cSlaveAddrDac = 0x1F
+    vrefOn= 0
+    Vdaq = ( desiredVoltage + Vref ) / 2
+    dacCode = 0xFFFF * Vdaq / Vref
+    dacCode= 0x391d
+    print "\tVreq:", desiredVoltage
+    print "\tDAC code:"  , dacCode
+    print "\tCH:", channel
+    print "\tIntRef:", vrefOn
+
+    #Set DAC value
+    #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+    if channel<0 or channel>7:
+        print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+        ##return -1
+    if dacCode<0 or dacCode>0xFFFF:
+        print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
+        ##return -1
+    # AD5665R chip with A0,A1 tied to ground
+    #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+
+    # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+    # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+    # # if we want to enable internal voltage reference:
+
+    if vrefOn:
+        # enter vref-on mode:
+        print "\tTurning internal reference ON"
+        #dac.write([0x38,0x00,0x01])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
+    else:
+        print "\tTurning internal reference OFF"
+        #dac.write([0x38,0x00,0x00])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
+    # Now set the actual value
+    sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+    print "\tWriting byte sequence:", sequence
+    TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/AIDA_tlu/legacy/TLU_v1e/scripts/test_T0.py b/AIDA_tlu/legacy/TLU_v1e/scripts/test_T0.py
new file mode 100644
index 0000000000000000000000000000000000000000..cf81b33d0fcac1767da1923d9abb62634a5885a2
--- /dev/null
+++ b/AIDA_tlu/legacy/TLU_v1e/scripts/test_T0.py
@@ -0,0 +1,92 @@
+#
+# Script to exercise AIDA mini-TLU
+#
+# David Cussans, December 2012
+# 
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+# Assume DIP-switch controlled address. Switches at 2 
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+firmwareID=board.read("FirmwareId")
+
+print "Firmware (from PyChips) = " , hex(firmwareID)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+ 
+
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+    print "Resetting clocks"
+    board.write("LogicRst", 1 )
+
+    clockStatus = board.read("LogicClocksCSR")
+    print "Clock status after reset = " , hex(clockStatus)
+
+
+board.write("InternalTriggerIntervalW",0)
+
+print "Enabling DUT 0 and 1"
+board.write("DUTMaskW",3)
+DUTMask = board.read("DUTMaskR")
+print "DUTMaskR = " , DUTMask
+
+print "Ignore veto on DUT 0 and 1"
+board.write("IgnoreDUTBusyW",3)
+IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
+print "IgnoreDUTBusyR = " , IgnoreDUTBusy
+
+print "Turning off software trigger veto"
+board.write("TriggerVetoW",0)
+
+print "Reseting FIFO"
+board.write("EventFifoCSR",0x2)
+eventFifoFillLevel = board.read("EventFifoFillLevel")
+print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
+
+print "Enabling data recording"
+board.write("Enable_Record_Data",1)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+#TriggerInterval = 400000
+TriggerInterval = 0
+print "Setting internal trigger interval to " , TriggerInterval
+board.write("InternalTriggerIntervalW",TriggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+trigInterval = board.read("InternalTriggerIntervalR")
+print "Trigger interval read back as ", trigInterval
+
+print "Setting TPix_maskexternal to ignore external shutter and T0"
+board.write("TPix_maskexternal",0x0003)
+
+numLoops = 500000
+oldEvtNumber = 0
+
+for iLoop in range(0,numLoops):
+
+    board.write("TPix_T0", 0x0001)
+
+#   time.sleep( 1.0)
diff --git a/AIDA_tlu/legacy/miniTLU/.ftpconfig b/AIDA_tlu/legacy/miniTLU/.ftpconfig
new file mode 100644
index 0000000000000000000000000000000000000000..100a040507b05e81df7a786375fef0437a548b8f
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/.ftpconfig
@@ -0,0 +1,20 @@
+{
+    "protocol": "sftp",
+    "host": "fortis.phy.bris.ac.uk",
+    "port": 22,
+    "user": "phpgb",
+    "pass": "",
+    "promptForPass": true,
+    "remote": "/users/phpgb/worklib/fmc-mtlu/firmware/scripts/",
+    "local": "",
+    "agent": "",
+    "privatekey": "",
+    "passphrase": "",
+    "hosthash": "",
+    "ignorehost": true,
+    "connTimeout": 10000,
+    "keepalive": 10000,
+    "keyboardInteractive": false,
+    "watch": [],
+    "watchTimeout": 500
+}
diff --git a/AIDA_tlu/legacy/miniTLU/FmcTluI2c.py b/AIDA_tlu/legacy/miniTLU/FmcTluI2c.py
new file mode 100644
index 0000000000000000000000000000000000000000..04bf5985fbde260c2668c587628b8919f8080508
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/FmcTluI2c.py
@@ -0,0 +1,132 @@
+import time
+#from PyChipsUser import *
+from I2cBusProperties import *
+from RawI2cAccess import *
+
+
+class FmcTluI2c:
+
+
+    ############################
+    ### configure i2c connection
+    ############################
+    def __init__(self,board):
+        self.board = board
+        i2cClockPrescale = 0x30
+        self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
+        return
+
+
+    ##########################
+    ### scan all i2c addresses
+    ##########################
+    def i2c_scan(self):
+        list=[]
+        for islave in range(128):
+            i2cscan = RawI2cAccess(self.i2cBusProps, islave)
+            try:
+                i2cscan.write([0x00])
+                device="slave address "+hex(islave)+" "
+                if islave==0x1f:
+                    device+="(DAC)"
+                elif islave==0x50:
+                    device+="(serial number PROM)"
+                elif islave>=0x54 and islave<=0x57:
+                    device+="(sp601 onboard EEPROM)"
+                else:
+                    device+="(???)"
+                    pass
+                list.append(device)
+                pass
+            except:
+                pass
+            pass
+        return list
+
+
+    ###################
+    ### write to EEPROM
+    ###################
+    def eeprom_write(self,address,value):
+        if address<0 or address>127:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        if value<0 or value>255:
+            print "eeprom_write ERROR: value",value,"not in range 0-255"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address,value])
+        time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
+        return
+
+
+    ####################
+    ### read from EEPROM
+    ####################
+    def eeprom_read(self,address):
+        if address<0 or address>255:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address])
+        return prom.read(1)[0]
+
+
+    ######################
+    ### read serial number
+    ######################
+    def get_serial_number(self):
+        result=""
+        for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
+            result+="%02x "%(self.eeprom_read(iaddr))
+            pass
+        return result
+
+
+    #################
+    ### set DAC value
+    #################
+    def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+        if channel<0 or channel>7:
+            print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            return -1
+        if value<0 or value>0xFFFF:
+            print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
+            return -1
+        # AD5665R chip with A0,A1 tied to ground
+        #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+        print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+        dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+        # if we want to enable internal voltage reference:
+        if vrefOn:
+            # enter vref-on mode:
+	    print "Turning internal reference ON"
+            dac.write([0x38,0x00,0x01])
+        else:
+	    print "Turning internal reference OFF"
+            dac.write([0x38,0x00,0x00])
+        # now set the actual value
+        sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
+        print sequence
+        dac.write(sequence)
+
+
+
+    ##################################################
+    ### convert required threshold voltage to DAC code
+    ##################################################
+    def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+        Vdaq = ( desiredVoltage + Vref ) / 2
+        dacCode = 0xFFFF * Vdaq / Vref
+        return int(dacCode)
+
+
+    ##################################################
+    ### calculate the DAC code required and set DAC
+    ##################################################
+    def set_threshold_voltage(self, channel , voltage ):
+        dacCode = self.convert_voltage_to_dac(voltage)
+        print " requested voltage, calculated DAC code = " , voltage , dacCode
+        self.set_dac(channel , dacCode)
diff --git a/AIDA_tlu/legacy/miniTLU/I2CuHal.py b/AIDA_tlu/legacy/miniTLU/I2CuHal.py
new file mode 100644
index 0000000000000000000000000000000000000000..694c9efc5e6143333e6c399a0348284f01308a9c
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/I2CuHal.py
@@ -0,0 +1,1000 @@
+"""
+solidfpa.py provides functionality to control the front end boards currently
+being prototyped.
+
+For the ADC:
+    One or more LTM9007 ADCs can be controlled via the IPbus SPI block.
+    Each chip is really two four channel ADCs, with each controlled with a
+    separate chip select line. Bank A is channels 1, 4, 5, 8.
+    Bank B is 2, 3, 6, 7.
+
+    Control is via a simple SPI interface where 16 bits are transferred.
+    b0 is read/!write
+    b7:1 are the register address
+    b15:b8 are the data sent to/from the ADC
+
+    If the ADC.cehckwrite flag is True then all write commands will immediately
+    be confirmed by a read command to the same address.
+"""
+
+import time
+
+import uhal
+
+verbose = True
+"""
+class SoLidFPGA:
+
+    def __init__(self, board, nadc=4, verbose=False, minversion=None):
+        cm = uhal.ConnectionManager("file://solidfpga.xml")
+        self.target = cm.getDevice(board)
+        #self.config()
+        self.offsets = TimingOffsets(self.target)
+        self.trigger = Trigger(self.target)
+        self.databuffer = OutputBuffer(self.target)
+        self.spi = SPICore(self.target, 31.25e6, 100e3)
+        self.clock_i2c = I2CCore(self.target, 31.25e6, 40e3, "io.clock_i2c")
+        self.analog_i2c = I2CCore(self.target, 31.25e6, 40e3, "io.analog_i2c")
+        self.clockchip = Si5326(self.clock_i2c)
+        self.adcs = []
+        for i in range(1):
+            self.adcs.append(ADCLTM9007(self.spi, 2 * i, 2 * i + 1))
+        # For board Wim sent to Bristol for testing the MCP4725 address seems
+        # to be 0b1100001, whereas for the first test board the address was
+        # 0b1100111.
+        self.gdac = DACMCP4725(self.analog_i2c, 0b1100001, 4.45)
+        self.trimdacs = [
+                DACMCP4728(self.analog_i2c, 0b1100011, 4.45),
+                DACMCP4728(self.analog_i2c, 0b1100101, 4.45)
+        ]
+        self.temp = TempMCP9808(self.analog_i2c)
+        self.firmwareversion = None
+        self.minversion = minversion
+        self.config(7, 16)
+
+    def config(self, slip, tap):
+        # check ID
+        boardid = self.target.getNode("ctrl_reg.id").read()
+        stat = self.target.getNode("ctrl_reg.stat").read()
+        self.target.dispatch()
+        if verbose:
+            print "ID = 0x%x, stat = 0x%x" % (boardid, stat)
+        self.id = (boardid & 0xffff0000) >> 16
+        self.firmwareversion = boardid & 0x0000ffff
+        if self.minversion is not None:
+            msg = "Old version of firmware (v%d) running, require >= v%d." % (
+                    self.firmwareversion, self.minversion)
+            assert self.firmwareversion >= self.minversion, msg
+        self.spi.config()
+        self.clock_i2c.config()
+        self.analog_i2c.config()
+        # Check for 40 MHz clock lock
+        lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
+        self.target.dispatch()
+        #assert lock == 1, "No 40 MHz clock clock, code not yet moved to frontend.py"
+        if lock != 1:
+            # Config clock chip
+            self.clockchip.config("siclock/si5326.txt")
+            time.sleep(1.0)
+        lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
+        self.target.dispatch()
+        assert lock == 1, "No 40 MHz clock clock, Si53266 configuration must have failed."
+        # Reset clock
+        timing_rst = self.target.getNode("timing.csr.ctrl.rst")
+        timing_rst.write(0x1)
+        self.target.dispatch()
+        timing_rst.write(0x0)
+        self.target.dispatch()
+        lock = False
+        while not lock:
+            lock = self.target.getNode("ctrl_reg.stat.mmcm_locked").read()
+            self.target.dispatch()
+        clkcount = self.target.getNode("io.freq_ctr.freq.count").read()
+        self.target.dispatch()
+        freq = int(clkcount) / 8388.608 # not sure why, from Lukas
+        if verbose:
+            print "Frequency = %g MHz" % freq
+        assert freq > 39 and freq < 41
+        # Configure trigger block
+        self.trigger.config()
+        # Set timing offset on inputs from ADC
+        self.offsets.setoffset(slip, tap)
+        for adc in self.adcs:
+            adc.config()
+        print "Analog board temperature = %g C." % self.temp.temp()
+
+    def reset(self, slip=7, tap=16):
+        if verbose:
+            print "Resetting board."
+        # Soft reset
+        soft_rst = self.target.getNode("ctrl_reg.ctrl.soft_rst")
+        soft_rst.write(1)
+        soft_rst.write(0)
+        self.target.dispatch()
+        time.sleep(1.0)
+        if verbose:
+            print "Reset complete."
+        self.config(slip, tap)
+
+    def readvoltages(self):
+        bias = self.gdac.readbias()
+        print "Global bias = %g V" %  bias
+        trims = "Channel trims:\n"
+        ichan = 0
+        for dac in self.trimdacs:
+            voltages = dac.readvoltages()
+            for v in voltages:
+                trims += "    Chan %d, v = %g V\n" % (ichan, v)
+                ichan += 1
+        print trims
+
+    def bias(self, bias):
+        self.gdac.setbias(bias)
+
+    def trim(self, trim):
+        for i in range(4):
+            for trimdac in self.trimdacs:
+                trimdac.setvoltage(i, trim)
+
+    def trims(self, trims):
+        for chan in trims:
+            trim = trims[chan]
+            ndac = chan / 4
+            nchan = chan % 4
+            self.trimdacs[ndac].setvoltage(nchan, trim)
+
+# IPbus blocks
+class TimingOffsets:
+    #Timing offsets for the ADC data deserialisation.
+
+    def __init__(self, target):
+        self.target = target
+
+    def setoffset(self, slip=7, tap=16):
+        if verbose:
+            print "Setting timing offset with channel slip = %d and %d taps." % (slip, tap)
+        chan_slip = self.target.getNode("timing.csr.ctrl.chan_slip")
+        for i in range(slip):
+            chan_slip.write(1)
+            self.target.dispatch()
+        chan_slip.write(0)
+        self.target.dispatch()
+        chan_inc = self.target.getNode("timing.csr.ctrl.chan_inc")
+        for i in range(tap):
+            chan_inc.write(1)
+            self.target.dispatch()
+        chan_inc.write(0)
+        self.target.dispatch()
+
+class Trigger:
+
+    def __init__(self, target, nsamples=0x800):
+        self.target = target
+        self.nsamples = nsamples
+        self.capture = target.getNode("timing.csr.ctrl.chan_cap")
+        self.chanselect = target.getNode("ctrl_reg.ctrl.chan")
+        self.fifo = target.getNode("chan.fifo")
+
+    def config(self):
+        # Set up channels
+        for i in range(8):
+            self.target.getNode("ctrl_reg.ctrl.chan").write(i)
+            self.target.getNode("chan.csr.ctrl.en_sync").write(1)
+        self.target.dispatch()
+
+    def trigger(self):
+        data = []
+        self.capture.write(1)
+        self.capture.write(0)
+        self.target.dispatch()
+        for i in range(8):
+            self.chanselect.write(i)
+            wf = self.fifo.readBlock(self.nsamples)
+            self.target.dispatch()
+            data.append(wf)
+        return data
+
+class OutputBuffer:
+    #Output data block.
+
+    def __init__(self, target):
+        self.target = target
+"""
+
+
+################################################################################
+# /*
+#        I2C CORE
+# */
+################################################################################
+
+
+
+"""
+I2C core XML:
+
+<node description="I2C master controller" fwinfo="endpoint;width=3">
+    <node id="ps_lo" address="0x0" description="Prescale low byte"/>
+    <node id="ps_hi" address="0x1" description="Prescale low byte"/>
+    <node id="ctrl" address="0x2" description="Control"/>
+    <node id="data" address="0x3" description="Data"/>
+    <node id="cmd_stat" address="0x4" description="Command / status"/>
+</node>
+
+"""
+class I2CCore:
+    """I2C communication block."""
+
+    # Define bits in cmd_stat register
+    startcmd = 0x1 << 7
+    stopcmd = 0x1 << 6
+    readcmd = 0x1 << 5
+    writecmd = 0x1 << 4
+    ack = 0x1 << 3
+    intack = 0x1
+
+    recvdack = 0x1 << 7
+    busy = 0x1 << 6
+    arblost = 0x1 << 5
+    inprogress = 0x1 << 1
+    interrupt = 0x1
+
+    def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
+        self.target = target
+        self.name = name
+        self.delay = delay
+        self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
+        self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
+        self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
+        self.data = self.target.getNode("%s.i2c_rxtx" % name)
+        self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
+        self.wishboneclock = wclk
+        self.i2cclock = i2cclk
+        self.config()
+
+    def state(self):
+        status = {}
+        status["ps_low"] = self.prescale_low.read()
+        status["ps_hi"] = self.prescale_high.read()
+        status["ctrl"] = self.ctrl.read()
+        status["data"] = self.data.read()
+        status["cmd_stat"] = self.cmd_stat.read()
+        self.target.dispatch()
+        status["prescale"] = status["ps_hi"] << 8
+        status["prescale"] |= status["ps_low"]
+        for reg in status:
+            val = status[reg]
+            bval = bin(int(val))
+            if verbose:
+                print "reg %s = %d, 0x%x, %s" % (reg, val, val, bval)
+
+    def clearint(self):
+        self.ctrl.write(0x1)
+        self.target.dispatch()
+
+    def config(self):
+        #INITIALIZATION OF THE I2S MASTER CORE
+        #Disable core
+        self.ctrl.write(0x0 << 7)
+        self.target.dispatch()
+        #Write pre-scale register
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
+        prescale = 0x30 #FOR NOW HARDWIRED, TO BE MODIFIED
+        self.prescale_low.write(prescale & 0xff)
+        self.prescale_high.write((prescale & 0xff00) >> 8)
+        #Enable core
+        self.ctrl.write(0x1 << 7)
+        self.target.dispatch()
+
+    def checkack(self):
+        inprogress = True
+        ack = False
+        while inprogress:
+            cmd_stat = self.cmd_stat.read()
+            self.target.dispatch()
+            inprogress = (cmd_stat & I2CCore.inprogress) > 0
+            ack = (cmd_stat & I2CCore.recvdack) == 0
+        return ack
+
+    def delayorcheckack(self):
+        ack = True
+        if self.delay is None:
+            ack = self.checkack()
+        else:
+            time.sleep(self.delay)
+            ack = self.checkack()#Remove this?
+        return ack
+
+################################################################################
+# /*
+#        I2C WRITE
+# */
+################################################################################
+
+
+
+    def write(self, addr, data, stop=True):
+        """Write data to the device with the given address."""
+        # Start transfer with 7 bit address and write bit (0)
+        nwritten = -1
+        addr &= 0x7f
+        addr = addr << 1
+        startcmd = 0x1 << 7
+        stopcmd = 0x1 << 6
+        writecmd = 0x1 << 4
+        #Set transmit register (write operation, LSB=0)
+        self.data.write(addr)
+        #Set Command Register to 0x90 (write, start)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return nwritten
+        nwritten += 1
+        for val in data:
+            val &= 0xff
+            #Write slave memory address
+            self.data.write(val)
+            #Set Command Register to 0x10 (write)
+            self.cmd_stat.write(I2CCore.writecmd)
+            self.target.dispatch()
+            ack = self.delayorcheckack()
+            if not ack:
+                self.cmd_stat.write(I2CCore.stopcmd)
+                self.target.dispatch()
+                return nwritten
+            nwritten += 1
+        if stop:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+        return nwritten
+
+################################################################################
+# /*
+#        I2C READ
+# */
+################################################################################
+
+
+
+    def read(self, addr, n):
+        """Read n bytes of data from the device with the given address."""
+        # Start transfer with 7 bit address and read bit (1)
+        data = []
+        addr &= 0x7f
+        addr = addr << 1
+        addr |= 0x1 # read bit
+        self.data.write(addr)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return data
+        for i in range(n):
+            self.cmd_stat.write(I2CCore.readcmd)
+            self.target.dispatch()
+            ack = self.delayorcheckack()
+            val = self.data.read()
+            self.target.dispatch()
+            data.append(val & 0xff)
+        self.cmd_stat.write(I2CCore.stopcmd)
+        self.target.dispatch()
+        return data
+
+################################################################################
+# /*
+#        I2C WRITE-READ
+# */
+################################################################################
+
+
+
+    def writeread(self, addr, data, n):
+        """Write data to device, then read n bytes back from it."""
+        nwritten = self.write(addr, data, stop=False)
+        readdata = []
+        if nwritten == len(data):
+            readdata = self.read(addr, n)
+        return nwritten, readdata
+
+"""
+SPI core XML:
+
+<node description="SPI master controller" fwinfo="endpoint;width=3">
+    <node id="d0" address="0x0" description="Data reg 0"/>
+    <node id="d1" address="0x1" description="Data reg 1"/>
+    <node id="d2" address="0x2" description="Data reg 2"/>
+    <node id="d3" address="0x3" description="Data reg 3"/>
+    <node id="ctrl" address="0x4" description="Control reg"/>
+    <node id="divider" address="0x5" description="Clock divider reg"/>
+    <node id="ss" address="0x6" description="Slave select reg"/>
+</node>
+"""
+class SPICore:
+
+    go_busy = 0x1 << 8
+    rising = 1
+    falling = 0
+
+
+    def __init__(self, target, wclk, spiclk, basename="io.spi"):
+        self.target = target
+        # Only a single data register is required since all transfers are
+        # 16 bit long
+        self.data = target.getNode("%s.d0" % basename)
+        self.control = target.getNode("%s.ctrl" % basename)
+        self.control_val = 0b0
+        self.divider = target.getNode("%s.divider" % basename)
+        self.slaveselect = target.getNode("%s.ss" % basename)
+        self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
+        self.divider_val = 0x7f
+        self.configured = False
+
+    def config(self):
+        "Configure SPI interace for communicating with ADCs."
+        self.divider_val = int(self.divider_val) % 0xffff
+        if verbose:
+            print "Configuring SPI core, divider = 0x%x" % self.divider_val
+        self.divider.write(self.divider_val)
+        self.target.dispatch()
+        self.control_val = 0x0
+        self.control_val |= 0x0 << 13 # Automatic slave select
+        self.control_val |= 0x0 << 12 # No interrupt
+        self.control_val |= 0x0 << 11 # MSB first
+        # ADC samples data on rising edge of SCK
+        self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
+        # ADC changes output shortly after falling edge of SCK
+        self.control_val |= 0x0 << 9 # read input on rising edge
+        self.control_val |= 0x10 # 16 bit transfers
+        if verbose:
+            print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
+        self.configured = True
+
+    def transmit(self, chip, value):
+        if not self.configured:
+            self.config()
+        assert chip >= 0 and chip < 8
+        value &= 0xffff
+        self.data.write(value)
+        checkdata = self.data.read()
+        self.target.dispatch()
+        assert checkdata == value
+        self.control.write(self.control_val)
+        self.slaveselect.write(0xff ^ (0x1 << chip))
+        self.target.dispatch()
+        self.control.write(self.control_val | SPICore.go_busy)
+        self.target.dispatch()
+        busy = True
+        while busy:
+            status = self.control.read()
+            self.target.dispatch()
+            busy = status & SPICore.go_busy > 0
+        self.slaveselect.write(0xff)
+        data = self.data.read()
+        ss = self.slaveselect.read()
+        status = self.control.read()
+        self.target.dispatch()
+        #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
+        return data
+"""
+        print "Data to send: 0x%x = %s" % (checkdata, bin(int(checkdata)))
+        ss = 0x1 << chip
+        nss = ss ^ 0xffff
+        print "chip = %d, nSS = 0x%x = %s" % (chip, nss, bin(nss))
+        ctrl = self.control.read()
+        self.target.dispatch()
+        busy = (ctrl & SPICore.go_busy) > 0
+        while busy:
+            ctrl = self.control.read()
+            self.target.dispatch()
+            busy = (ctrl & SPICore.go_busy) > 0
+        self.slaveselect.write(nss)
+        self.target.dispatch()
+        self.control.write(self.control_val)
+        self.target.dispatch()
+        self.control.write(self.control_val | SPICore.go_busy)
+        self.target.dispatch()
+        time.sleep(0.1)
+        ncheck = 0
+        finished = False
+        while not finished:
+            ctrl = self.control.read()
+            self.target.dispatch()
+            # Check if transfer is complete by reading the GO_BSY bit of CTRL
+            finished = (ctrl & SPICore.go_busy) == 0
+            ncheck += 1
+        #    assert ncheck < 10, "ctrl = 0x%x, %s finished = %s" % (ctrl, bin(int(ctrl)), str(finished))
+        #    time.sleep(0.1)
+        print "%d checks before busy not asserted." % ncheck
+        self.slaveselect.write(0xffff)
+        self.target.dispatch()
+        ss = self.slaveselect.read()
+        data = self.data.read()
+        self.target.dispatch()
+        print "After transmit, ss = 0x%x" % ss
+        print "Received 0x%x = %s" % (data, bin(int(data)))
+        time.sleep(0.1)
+        return data
+"""
+
+# External chips
+
+class Si5326:
+
+    def __init__(self, i2c, slaveaddr=0b1101000):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    def config(self, fn):
+        if verbose:
+            print "Loading Si5326 configuration from %s" % fn
+        inp = open(fn, "r")
+        inmap = False
+        regvals = {}
+        for line in inp:
+            if inmap:
+                if "END_REGISTER_MAP" in line:
+                    inmap = False
+                    continue
+                line = line.split(",")
+                reg = int(line[0])
+                val = line[1].strip().replace("h", "")
+                val = int(val, 16)
+                regvals[reg] = val
+            if "#REGISTER_MAP" in line:
+                inmap = True
+        inp.close()
+        if verbose:
+            print "Register map: %s" % str(regvals)
+        for reg in regvals:
+            n = self.i2c.write(self.slaveaddr, [reg, regvals[reg]])
+            assert n == 2, "Only wrote %d of 2 bytes over I2C." % n
+        if verbose:
+            print "Clock configured"
+
+lvdscurrents = {
+        3.5: 0b000,
+        4.0: 0b001,
+        4.5: 0b010,
+        3.0: 0b100,
+        2.5: 0b101,
+        2.1: 0b110,
+        1.75: 0b111
+}
+
+napchannels = {
+        1: 0b0001,
+        2: 0b0001,
+        3: 0b0010,
+        4: 0b0010,
+        5: 0b0100,
+        6: 0b0100,
+        7: 0b1000,
+        8: 0b1000
+}
+
+class ADCLTM9007:
+
+    def __init__(self, spicore, csA, csB, checkwrite=False):
+        self.checkwrite = checkwrite
+        self.spicore = spicore
+        self.csA = csA
+        self.csB = csB
+
+    def config(self):
+        self.reset()
+        self.testpattern(False)
+        self.setoutputmode(3.5, False, True, 1, 14)
+        self.setformat(False, False)
+
+    def writereg(self, bank, addr, data):
+        value = 0x0
+        value |= 0x0 << 15 # write bit
+        value |= (addr & 0x7f) << 8
+        value |= data & 0xff
+        #print "writereg sending 0x%x = %s" % (value, bin(value))
+        assert bank in ["A", "B"]
+        if bank == "A":
+            reply = self.spicore.transmit(self.csA, value)
+        else:
+            reply = self.spicore.transmit(self.csB, value)
+        if self.checkwrite:
+            readdata = self.readreg(bank, addr)
+            msg = "Incorrect data from bank %s register 0x%x: " (bank, addr)
+            msg += " after writing 0x%x, read 0x%x.\n" % (data, readdata)
+            assert readdata == data, msg
+
+
+    def writerega(self, addr, data):
+        self.writereg("A", addr, data)
+
+    def writeregb(self, addr, data):
+        self.writereg("B", addr, data)
+
+    def readreg(self, bank, addr):
+        value = 0x0
+        value |= 0x1 << 15
+        value |= (addr & 0x7f) << 8
+        #print "readreg sending 0x%x = %s" % (value, bin(value))
+        assert bank in ["A", "B"]
+        if bank == "A":
+            reply = self.spicore.transmit(self.csA, value)
+        else:
+            reply = self.spicore.transmit(self.csB, value)
+        reply16 = 0xff & reply
+        #print "Reply = 0x%x -> 0x%x" % (reply, reply16)
+        return reply16
+
+    def readrega(self, addr):
+        return self.readreg("A", addr)
+
+    def readregb(self, addr):
+        return self.readreg("B", addr)
+
+    def reset(self, bank=None):
+        """Reset ADC bank(s)."""
+        if verbose:
+            print "Resetting ADC."
+        rstcmd  = 0x1 << 7
+        if bank == "A" or bank is None:
+            if verbose:
+                print "Reset A"
+            self.writerega(0x0, rstcmd)
+            time.sleep(0.5)
+        if bank == "B" or bank is None:
+            if verbose:
+                print "Reset B"
+            self.writeregb(0x0, rstcmd)
+            time.sleep(0.5)
+
+    def testpattern(self, on, pattern=0x0, bank=None):
+        """Set bank(s)'s test pattern and en/disable it."""
+        pattern = int(pattern) & 0x3fff
+        if verbose:
+            if on:
+                print "Setting ADC test pattern = 0x%x = %s." % (pattern, bin(pattern))
+            else:
+                print "Setting ADC test pattern off."
+        msb = 0x0
+        if on:
+            msb = 0x1 << 7
+        msb |= ((pattern & 0x3f00) >> 8)
+        lsb = pattern & 0xff
+        if verbose:
+            print "msb = 0x%x = %s, lsb = 0x%x = %s" % (msb, bin(msb), lsb, bin(lsb))
+        if bank is None or bank == "A":
+            self.writerega(0x4, lsb)
+            self.writerega(0x3, msb)
+        if bank is None or bank == "B":
+            self.writeregb(0x4, lsb)
+            self.writeregb(0x3, msb)
+
+    def gettestpattern(self):
+        valA = self.readrega(0x3) << 8
+        valA |= self.readrega(0x4)
+        print "Test pattern on bank A: 0x%x, %s" % (valA, bin(valA))
+        valB = self.readregb(0x3) << 8
+        valB |= self.readregb(0x4)
+        print "Test pattern on bank B: 0x%x, %s" % (valB, bin(valB))
+
+    def getstatus(self):
+        print "Bank A:"
+        for reg in range(5):
+            val = self.readrega(reg)
+            print "    reg%d = 0x%x = %s" % (reg, val, bin(val))
+        print "Bank B:"
+        for reg in range(5):
+            val = self.readregb(reg)
+            print "    reg%d = 0x%x = %s" % (reg, val, bin(val))
+
+    def setoutputmode(self, lvdscurrent, lvdstermination, outenable, lanes, bits, bank=None):
+        """Configure bank(s)'s output mode."""
+        if verbose:
+            print "Setting ADC output mode."
+        mode = 0x0
+        assert lanes in [1, 2] and bits in [12, 14, 16]
+        if lanes == 1:
+            if bits == 12:
+                mode |= 0b110
+            elif bits == 14:
+                mode |= 0b101
+            else: # bits = 16
+                mode |= 0b111
+        else:   # lanes = 2
+            if bits == 12:
+                mode |= 0b010
+            elif bits == 14:
+                mode |= 001
+            else: # bits = 16
+                mode |= 0b111
+        if not outenable:
+            mode |= 0b1000
+        if lvdstermination:
+            mode |= (0x1 << 4)
+        mode |= (lvdscurrents[lvdscurrent] << 5)
+        if bank is None or bank == "A":
+            self.writerega(0x2, mode)
+        if bank is None or bank == "B":
+            self.writeregb(0x2, mode)
+
+    def setformat(self, randomiser, twoscomp, stabiliser=True, bank=None):
+        """Configure bank(s)'s output format."""
+        if verbose:
+            print "Setting ADC format."
+        if bank is None or bank == "A":
+            data = self.readrega(0x1)
+            if twoscomp:
+                data |= (0x1 << 5)
+            else:
+                data &= 0xff ^ (0x1 << 5)
+            if randomiser:
+                data |= (0x1 << 6)
+            else:
+                data &= 0xff ^ (0x1 << 6)
+            if not stabiliser:
+                data |= (0x1 << 7)
+            else:
+                data &= 0xff ^ (0x1 << 7)
+            self.writerega(0x1, data)
+        if bank is None or bank == "B":
+            data = self.readregb(0x1)
+            if twoscomp:
+                data |= (0x1 << 5)
+            else:
+                data &= 0xff ^ (0x1 << 5)
+            if randomiser:
+                data |= (0x1 << 6)
+            else:
+                data &= 0xff ^ (0x1 << 6)
+            if not stabiliser:
+                data |= (0x1 << 7)
+            else:
+                data &= 0xff ^ (0x1 << 7)
+            self.writeregb(0x1, data)
+
+    def setsleep(self, sleep, bank=None):
+        """Put ADC bank(s) to sleep."""
+        if verbose:
+            print "Setting ADC sleep mode"
+        if bank is None or bank == "A":
+            data = self.readrega(0x1)
+            if sleep:
+                data |= (0x1 << 4)
+            else:
+                data &= 0xff ^ (0x1 << 4)
+            self.writerega(0x1, data)
+        if bank is None or bank == "B":
+            data = self.readregb(0x1)
+            if sleep:
+                data |= (0x1 << 4)
+            else:
+                data &= 0xff ^ (0x1 << 4)
+            self.writeregb(0x1, data)
+
+    def nap(self, channels):
+        """Provide a list of channels to put down for a nap, all others will be not napping."""
+        if verbose:
+            print "Setting ADC channel nap."
+        dataa = self.readrega(0x1)
+        dataa &= 0xf0
+        datab = self.readregb(0x1)
+        datab &= 0xf0
+        for chan in channels:
+            assert chan < 9 and chan > 0
+            if chan in [1, 4, 5, 8]:
+                dataa |= napchannels[chan]
+            else:
+                datab |= napchannels[chan]
+        self.writerega(0x1, dataa)
+        self.writeregb(0x1, datab)
+
+class MCP472XPowerMode:
+
+    on = 0b00
+    off1k = 0b01
+    off100k = 0b10
+    off500k = 0b11
+
+class DACMCP4725:
+    """Global trim DAC"""
+
+    # Write modes
+    fast = 0b00
+    writeDAC = 0b10
+    writeDACEEPROM = 0b11
+
+    def __init__(self, i2ccore, addr=0b1100111, vdd=5.0):
+        self.i2ccore = i2ccore
+        self.slaveaddr = addr & 0x7f
+        self.vdd = float(vdd)
+
+    def setbias(self, bias):
+        # DAC voltage goes through potential divider to HV chip, where it is scaled up
+        r1 = 1.0
+        r2 = 2.4
+        divider = r2 / (r1 + r2)
+        voltage = bias / 30.0 / divider
+        self.setvoltage(voltage)
+
+    def setvoltage(self, voltage, powerdown=MCP472XPowerMode.on):
+        if voltage > self.vdd:
+            print "Overriding MCP4725 voltage: %g -> %g V (max of range)" % (voltage, self.vdd)
+            voltage = self.vdd
+        value = int(voltage / float(self.vdd) * 4096)
+        #print "%g -> %d" % (voltage, value)
+        self.setvalue(value, powerdown, self.writeDACEEPROM)
+
+    def setvalue(self, value, powerdown, mode):
+        value = int(value)
+        value &= 0xfff
+        if mode == self.fast:
+            data = []
+            data.append((powerdown << 4) | ((value & 0xf00) >> 8))
+            data.append(value & 0x0ff)
+            self.i2ccore.write(self.slaveaddr, data)
+        else:
+            data = []
+            data.append((mode << 5) | (powerdown << 1))
+            data.append((value & 0xff0) >> 4)
+            data.append((value & 0x00f) << 4)
+            #print "Writing %s" % str(data)
+            self.i2ccore.write(self.slaveaddr, data)
+
+    def status(self):
+        data = self.i2ccore.read(self.slaveaddr, 5)
+        assert len(data) == 5, "Only recieved %d of 5 expected bytes from MCP4725." % len(data)
+        dx = "0x"
+        db = ""
+        for val in data:
+            dx += "%02x" % val
+            db += "%s " % bin(val)
+        #print dx, db
+        ready = (data[0] & (0x1 << 7)) > 0
+        por = (data[0] & (0x1 << 6)) > 0 # power on reset?
+        powerdown = (data[0] & 0b110) >> 1
+        dacvalue = data[1] << 4
+        dacvalue |= (data[2] & 0xf0) >> 4
+        voltage = self.vdd * dacvalue / 2**12
+        #print dacvalue, voltage
+        return dacvalue, voltage, ready, por, powerdown
+
+    def readvoltage(self):
+        vals = self.status()
+        return vals[1]
+
+    def readbias(self):
+        v = self.readvoltage()
+        r1 = 1.0
+        r2 = 2.4
+        divider = r2 / (r1 + r2)
+        bias = v * 30.0 * divider
+        return bias
+
+# class MCP4728ChanStatus:
+#
+#     def __init__(self, data):
+#         assert len(data) == 3
+#         s = "0x"
+#         for val in data:
+#             s += "%02x" % val
+#         #print data, s
+#         self.ready = (data[0] & (0x1 << 7)) > 0
+#         self.por = (data[0] & (0x1 << 6)) > 0
+#         self.chan = (data[0] & (0b11 << 4)) >> 4
+#         self.addr = data[0] & 0x0f
+#         self.vref = (data[1] & (0b1 << 7)) > 0
+#         self.powerdown = (data[1] & (0b11 << 5)) >> 5
+#         self.gain = (data[1] & (0b1 << 4)) > 0
+#         self.value = (data[1] & 0x0f) << 8
+#         self.value |= data[2]
+#
+#     def __repr__(self):
+#         return "chan %d: vref = %s, powerdown = %d, value = %d" % (self.chan, str(self.vref), self.powerdown, self.value)
+
+# class MCP4728Channel:
+#
+#     def __init__(self, data):
+#         assert len(data) == 6
+#         self.output = MCP4728ChanStatus(data[:3])
+#         self.EEPROM = MCP4728ChanStatus(data[3:])
+#         self.chan = self.EEPROM.chan
+#         #print self.output
+
+# class DACMCP4728:
+#     """Channel trim DAC"""
+#
+#     # Commands
+#     writeDACEEPROM = 0b010
+#
+#     # write functions
+#     multiwrite = 0b00
+#     sequentialwrite = 0b10
+#     singlewrite = 0b11
+#
+#     # stuff
+#     vref = 0b0 << 7 # Uses external reference, ie Vdd
+#
+#     def __init__(self, i2ccore, addr, vdd=5.0):
+#         self.i2ccore = i2ccore
+#         self.slaveaddr = addr & 0x7f
+#         self.vdd = float(vdd)
+#
+#     def setvoltage(self, channel, voltage, powerdown=MCP472XPowerMode.on):
+#         value = int(voltage / self.vdd * 2**12)
+#         #print "%g V -> %d" % (voltage, value)
+#         self.setvalue(channel, value, powerdown)
+#
+#     def setvalue(self, channel, value, powerdown=MCP472XPowerMode.on):
+#         value = int(value) & 0xfff
+#         data = [] # data is an empty array that gets filled as below
+#         cmd = DACMCP4728.writeDACEEPROM << 5
+#         cmd |= DACMCP4728.singlewrite << 3
+#         cmd |= (channel & 0b11) << 1
+#         data.append(cmd) data gets appende the cmd string
+#         val = DACMCP4728.vref | ((powerdown & 0b11) << 5)
+#         val |= (value & 0xf00) >> 8
+#         data.append(val)
+#         data.append(value & 0xff)
+#         sx = "0x"
+#         sb = ""
+#         for val in data:
+#             sx += "%02x" % val
+#             sb += "%s " % bin(val)
+#         #print "Writing data to %s value: " % bin(self.slaveaddr), data, sx, sb
+#         nwritten = self.i2ccore.write(self.slaveaddr, data)
+#         assert nwritten == len(data), "Only wrote %d of %d bytes setting MCP4728." % (nwritten, len(data))
+#         time.sleep(0.2)
+#
+#     def status(self):
+#         data = self.i2ccore.read(self.slaveaddr, 24)
+#         assert len(data) == 24, "Only read %d of 24 bytes getting MCP4728 status." % len(data)
+#         #print data
+#         chans = []
+#         for chan in range(4):
+#             i = chan * 6
+#             chans.append(MCP4728Channel(data[i:i+6]))
+#         return chans
+#
+#     def readvoltages(self):
+#         chans = self.status()
+#         voltages = []
+#         for chan in chans:
+#             value = float(chan.output.value)
+#             voltage = self.vdd * value / 2**12
+#             voltages.append(voltage)
+#         return voltages
+
+class TempMCP9808:
+    """Temperture chip on analog board."""
+
+    regTemp = 0x5
+
+    def __init__(self, i2ccore, addr=0b0011000):
+        self.i2ccore = i2ccore
+        self.slaveaddr = addr & 0x7f
+# Here the chip needs a specific register written as a command before it knows
+# where to write to, which is the regaddr byte that is passed upself.
+
+    def readreg(self, regaddr):
+        n, data = self.i2ccore.writeread(self.slaveaddr, [regaddr], 2)
+        assert n == 1 # this is the one byte address for the registry
+        assert len(data) == 2 # this is teh length of the data read from the chip
+        val = data[0] << 8
+        val |= data[1]
+        return val
+
+    def temp(self):
+        val = self.readreg(TempMCP9808.regTemp)
+        return self.u16todeg(val)
+
+    def u16todeg(self, val):
+        val &= 0x1fff
+        neg = val & 0x1000 > 0
+        val &= 0x0fff
+        if neg:
+            return -float(0xfff - val) / 16.0
+        return float(val) / 16.0
diff --git a/AIDA_tlu/legacy/miniTLU/I2cBusProperties.py b/AIDA_tlu/legacy/miniTLU/I2cBusProperties.py
new file mode 100644
index 0000000000000000000000000000000000000000..a23f30cd537987907774b0a11869026ec5feb96d
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/I2cBusProperties.py
@@ -0,0 +1,122 @@
+##########################################################
+#  I2cBusProperties - simple encapsulation of all items
+#                     required to control an I2C bus.
+#
+#  Carl Jeske, July 2010
+#  Refactored by Robert Frazier, May 2011
+##########################################################
+
+
+class I2cBusProperties(object):
+    """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
+
+    Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
+    value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
+    registers that define/control the bus (assuming these names are not the defaults specified
+    in the constructor below).  The seven registers consist of the two clock pre-scaling
+    registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
+    COMMAND and STATUS).
+
+    Usage:  You'll need to create an instance of this class to give to a concrete I2C bus instance, such
+            as OpenCoresI2cBus.  This I2cBusProperties class is simply a container to hold the properties
+            that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
+
+            Access the items stored by this class via these (deliberately compact) variable names:
+
+                chipsBus     -- the ChipsBus device hosting the I2C core
+                preHiVal     -- the top byte of the clock prescale value
+                preLoVal     -- the bottom byte of the clock prescale value
+                preHiReg     -- the register the top byte of the clk prescale value (preHiVal) gets written to
+                preLoReg     -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
+                ctrlReg      -- the I2C Control register
+                txReg        -- the I2C Transmit register
+                rxReg        -- the I2C Receive register
+                cmdReg       -- the I2C Command register
+                statusReg    -- the I2C Status register
+
+
+    Compatibility Notes: The seven register names are the registers typically required to operate an
+                         OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
+                         the same way as the OpenCores one). This software is not compatible with your
+                         I2C bus master if it doesn't use this register interface.
+    """
+
+    def __init__(self,
+                 chipsBusDevice,
+                 clkPrescaleU16,
+                 clkPrescaleLoByteReg = "i2c_pre_lo",
+                 clkPrescaleHiByteReg = "i2c_pre_hi",
+                 controlReg           = "i2c_ctrl",
+                 transmitReg          = "i2c_tx",
+                 receiveReg           = "i2c_rx",
+                 commandReg           = "i2c_cmd",
+                 statusReg            = "i2c_status"):
+
+        """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
+
+        chipsBusDevice:  Provide a ChipsBus instance to the device where the I2C bus is being
+                controlled. The address table for this device must contain the five registers
+                that control the bus, as declared next...
+
+        clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
+                master-clock.  This value gets split into two 8-bit values and ultimately will
+                get written to the two I2C clock-prescale registers as declared below.  See
+                the OpenCores or Lattice Semiconductor I2C documentation for more details.
+
+        clkPrescaleLoByteReg:  The register where the lower byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_lo".
+
+        clkPrescaleHiByteReg:  The register where the higher byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_hi"
+
+        controlReg:  The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
+                usually read and write accessible. The default name for this register is "i2c_ctrl".
+
+        transmitReg:  The TRANSMIT register, used for holding the data to be transmitted via I2C, etc.  This
+                typically shares the same address as the RECEIVE register, but has write-only access.  The default
+                name for this register is "i2c_tx".
+
+        receiveReg:  The RECEIVE register - allows access to the byte received over the I2C bus.  This
+                typically shares the same address as the TRANSMIT register, but has read-only access.  The
+                default name for this register is "i2c_rx".
+
+        commandReg:  The COMMAND register - stores the command for the next I2C operation.  This typically
+                shares the same address as the STATUS register, but has write-only access.  The default name for
+                this register is "i2c_cmd".
+
+        statusReg:  The STATUS register - allows monitoring of the I2C operations.  This typically shares
+                the same address as the COMMAND register, but has read-only access.  The default name for this
+                register is "i2c_status".
+        """
+
+        object.__init__(self)
+        self.chipsBus = chipsBusDevice
+        self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
+        self.preLoVal = (clkPrescaleU16 & 0xff)
+        
+        # Check to see all the registers are in the address table
+        registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
+        for reg in registers:
+            if not self.chipsBus.addrTable.checkItem(reg):
+                raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
+
+        # Check that the registers we'll need to write to are indeed writable
+        writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
+        for wReg in writableRegisters:
+            if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
+                raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
+
+        # Check that the registers we'll need to read from are indeed readable
+        readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
+        for rReg in readableRegisters:
+            if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
+                raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
+
+        # Store the various register name strings
+        self.preHiReg = clkPrescaleHiByteReg
+        self.preLoReg = clkPrescaleLoByteReg
+        self.ctrlReg = controlReg
+        self.txReg = transmitReg
+        self.rxReg = receiveReg
+        self.cmdReg = commandReg
+        self.statusReg = statusReg
diff --git a/AIDA_tlu/legacy/miniTLU/RawI2cAccess.py b/AIDA_tlu/legacy/miniTLU/RawI2cAccess.py
new file mode 100644
index 0000000000000000000000000000000000000000..284613299f372f0718001f996fa083befc68113b
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/RawI2cAccess.py
@@ -0,0 +1,261 @@
+# Created on Sep 10, 2012
+# @author: Kristian Harder, based on code by Carl Jeske
+
+from I2cBusProperties import I2cBusProperties
+from ChipsBus import ChipsBus
+from ChipsLog import chipsLog
+from ChipsException import ChipsException
+
+
+class RawI2cAccess:
+
+    def __init__(self, i2cBusProps, slaveAddr):
+
+        # For performing read/writes over an OpenCores-compatible I2C bus master
+        #
+        # An instance of this class is required to communicate with each
+        # I2C slave on the I2C bus.
+        #
+        # i2cBusProps: an instance of the class I2cBusProperties that contains
+        #    the relevant ChipsBus host and the I2C bus-master registers (if
+        #    they differ from the defaults specified by the I2cBusProperties
+        #    class).
+        #
+        #slaveAddr: The address of the I2C slave you wish to communicate with.
+        #
+
+        self._i2cProps = i2cBusProps   # The I2C Bus Properties
+        self._slaveAddr = 0x7f & slaveAddr  # 7-bit slave address
+
+
+    def resetI2cBus(self):
+
+        # Resets the I2C bus
+        #
+        # This function does the following:
+        #        1) Disables the I2C core
+        #        2) Sets the clock prescale registers
+        #        3) Enables the I2C core
+        #        4) Sets all writable bus-master registers to default values
+
+        try:
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
+            #self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
+            self._chipsBus().queueWrite(self._i2cProps.preHiReg,
+                                        self._i2cProps.preHiVal)
+            self._chipsBus().queueWrite(self._i2cProps.preLoReg,
+                                        self._i2cProps.preLoVal)
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
+            self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
+            self._chipsBus().queueRun()
+        except ChipsException, err:
+            raise ChipsException("I2C reset error:\n\t" + str(err))
+
+
+    def read(self, numBytes):
+
+        # Performs an I2C read. Returns the 8-bit read result(s).
+        #
+        # numBytes: number of bytes expected as response
+        #
+
+        try:
+            result = self._privateRead(numBytes)
+        except ChipsException, err:
+            raise ChipsException("I2C read error:\n\t" + str(err))
+        return result
+
+
+    def write(self, listDataU8):
+
+        # Performs an 8-bit I2C write.
+        #
+        # listDataU8:  The 8-bit data values to be written.
+        #
+
+        try:
+            self._privateWrite(listDataU8)
+        except ChipsException, err:
+            raise ChipsException("I2C write error:\n\t" + str(err))
+        return
+
+
+    def _chipsBus(self):
+
+        # Returns the instance of the ChipsBus device that's hosting
+        # the I2C bus master
+
+        return self._i2cProps.chipsBus
+
+
+    def _privateRead(self, numBytes):
+
+        # I2C read implementation.
+        #
+        #  Fast I2C read implementation,
+        # i.e. done with the fewest packets possible.
+
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        #        '1' = reading from slave
+        #        '0' = writing to slave
+
+        # command reg definitions
+        # bit 7:   Generate start condition
+        # bit 6:   Generate stop condition
+        # bit 5:   Read from slave
+        # bit 4:   Write to slave
+        # bit 3:   0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0:   Interrupt acknowledge. When set, clears a pending interrupt
+
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero
+        # (i.e. we're writing an address to the bus)
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) | 0x01)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        result=[]
+        for ibyte in range(numBytes):
+            if ibyte==numBytes-1:
+                stop_bit=0x40
+                ack_bit=0x08
+            else:
+                stop_bit=0
+                ack_bit=0
+                pass
+            # Set read bit, acknowledge and stop bit in command reg
+            self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
+            # Wait for transaction to finish.
+            # Don't expect an ACK, do expect bus free at finish.
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = False)
+                pass
+            result.append(self._chipsBus().read(self._i2cProps.rxReg))
+
+        return result
+
+
+    def _privateWrite(self, listDataU8):
+
+        # I2C write implementation.
+        #
+        #  Fast I2C write implementation,
+        # i.e. done with the fewest packets possible.
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        # '1' = reading from slave
+        # '0' = writing to slave
+
+        # command reg definitions
+        # bit 7: Generate start condition
+        # bit 6: Generate stop condition
+        # bit 5: Read from slave
+        # bit 4: Write to slave
+        # bit 3: 0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) & 0xfe)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        for ibyte in range(len(listDataU8)):
+            dataU8 = listDataU8[ibyte]
+            if ibyte==len(listDataU8)-1:
+                stop_bit=0x40
+            else:
+                stop_bit=0x00
+                pass
+            # Set data to be written in transmit reg
+            self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
+            # Set write and stop bit in command reg
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
+            # Run the queue
+            self._chipsBus().queueRun()
+            # Wait for transaction to finish.
+            # Do expect an ACK and do expect bus to be free at finish
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = False)
+                pass
+            pass
+
+        return
+
+
+    def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
+                              requireBusIdleAtEnd = False):
+
+        # Ensures the current bus transaction has finished successfully
+        # before allowing further I2C bus transactions
+
+        # This method monitors the status register
+        # and will not allow execution to continue until the
+        # I2C bus has completed properly.  It will throw an exception
+        # if it picks up bus problems or a bus timeout occurs.
+
+        maxRetry = 20
+        attempt = 1
+        while attempt <= maxRetry:
+
+            # Get the status
+            i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
+
+            receivedAcknowledge = not bool(i2c_status & 0x80)
+            busy = bool(i2c_status & 0x40)
+            arbitrationLost = bool(i2c_status & 0x20)
+            transferInProgress = bool(i2c_status & 0x02)
+            interruptFlag = bool(i2c_status & 0x01)
+
+            if arbitrationLost:  # This is an instant error at any time
+                raise ChipsException("I2C error: Arbitration lost!")
+
+            if not transferInProgress:
+                break  # The transfer looks to have completed successfully, pending further checks
+
+            attempt += 1
+
+        # At this point, we've either had too many retries, or the
+        # Transfer in Progress (TIP) bit went low.  If the TIP bit
+        # did go low, then we do a couple of other checks to see if
+        # the bus operated as expected:
+
+        if attempt > maxRetry:
+            raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
+
+        if requireAcknowledgement and not receivedAcknowledge:
+            raise ChipsException("I2C error: No acknowledge received!")
+
+        if requireBusIdleAtEnd and busy:
+            raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/AIDA_tlu/legacy/miniTLU/aida_mini_tlu_addr_map.txt b/AIDA_tlu/legacy/miniTLU/aida_mini_tlu_addr_map.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1f4693a4e4e66256c1729daf059ec85744b14f64
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/aida_mini_tlu_addr_map.txt
@@ -0,0 +1,72 @@
+*RegName                RegAddr        RegMask       R    W
+*-------------------------------------------------------------
+FirmwareId              0x00000000     0xffffffff    1    0
+*
+* DUT interfaces base = 0x020
+DUTMaskW		0x00000020     0xffffffff    0    1
+IgnoreDUTBusyW		0x00000021     0xffffffff    0    1
+IgnoreShutterVetoW	0x00000022     0xffffffff    0    1
+DUTInterfaceModeW	0x00000023     0xffffffff    0    1
+DUTInterfaceModeModifierW 0x00000024     0xffffffff    0    1
+DUTMaskR		0x00000028     0xffffffff    1    0
+IgnoreDUTBusyR		0x00000029     0xffffffff    1    0
+IgnoreShutterVetoR	0x0000002A     0xffffffff    1    0
+DUTInterfaceModeR 	0x0000002B     0xffffffff    1    0
+DUTInterfaceModeModifierR 0x0000002C     0xffffffff    1    0
+*
+* trigger inputs = 0x040
+SerdesRstW               0x00000040     0xffffffff    0    1
+SerdesRstR               0x00000048     0xffffffff    1    0
+ThrCount0R               0x00000049     0xffffffff    1    0
+ThrCount1R               0x0000004a     0xffffffff    1    0
+ThrCount2R               0x0000004b     0xffffffff    1    0
+ThrCount3R               0x0000004c     0xffffffff    1    0
+*
+* trigger logic = 0x060  **Note the different read and write directions
+
+InternalTriggerIntervalW	0x00000062     0xffffffff    0    1
+TriggerPatternW 		0x00000063     0xffffffff    0    1
+TriggerVetoW 			0x00000064     0xffffffff    0    1
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+TriggerHoldOffW			0x00000068     0xffffffff    0    1
+
+PostVetoTriggersR       	0x00000070     0xffffffff    1    0
+PreVetoTriggersR        	0x00000071     0xffffffff    1    0
+InternalTriggerIntervalR	0x00000072     0xffffffff    1    0
+TriggerPatternR 		0x00000073     0xffffffff    1    0
+TriggerVetoR 			0x00000074     0xffffffff    1    0
+ExternalTriggerVetoR		0x00000075     0xffffffff    1    0
+PulseStretchR			0x00000076     0xffffffff    1    0
+PulseDelayR 			0x00000077     0xffffffff    1    0
+TriggerHoldOffR			0x00000078     0xffffffff    1    0
+AuxTriggerCountR 		0x00000079     0xffffffff    1    0
+*
+* event buffer = 0x080
+EventFifoData		0x00000080     0xffffffff    1    0
+EventFifoFillLevel	0x00000081     0xffffffff    1    0
+EventFifoCSR		0x00000082     0xffffffff    1    1
+EventFifoFillLevelFlags	0x00000083     0xffffffff    1    0
+*
+* logic clocks = 0x0A0
+LogicClocksCSR          0x000000A0     0xffffffff    1    1
+LogicRst                0x000000A1     0xffffffff    0    1
+*
+* I2C = 0x0C0
+i2c_pre_lo                0x000000C0     0x000000ff    1    1
+i2c_pre_hi                0x000000C1     0x000000ff    1    1
+i2c_ctrl                  0x000000C2     0x000000ff    1    1
+i2c_tx                    0x000000C3     0x000000ff    0    1
+i2c_rx                    0x000000C3     0x000000ff    1    0
+i2c_cmd                   0x000000C4     0x000000ff    0    1
+i2c_status                0x000000C4     0x000000ff    1    0
+*
+* Event formatter = 0x140
+Enable_Record_Data	0x00000140     0xffffffff    1    1
+ResetTimestampW		0x00000141     0xffffffff    0    1
+CurrentTimestampLR	0x00000142     0xffffffff    1    0
+CurrentTimestampHR	0x00000143     0xffffffff    1    0
+*
+* Shutter/T0 control = 0x160
+ShutterStateW			0x00000160     0xffffffff    0    1
+PulseT0				0x00000161     0xffffffff    0    1
diff --git a/AIDA_tlu/legacy/miniTLU/connection.xml b/AIDA_tlu/legacy/miniTLU/connection.xml
new file mode 100644
index 0000000000000000000000000000000000000000..647c1ad332a1dd6aaff563025ae1c64fa5456723
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/connection.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="minitlu" uri="ipbusudp-2.0://192.168.200.32:50001" 
+   address_table="file://./miniTLU.xml" />
+</connections>
diff --git a/AIDA_tlu/legacy/miniTLU/initTLU.py b/AIDA_tlu/legacy/miniTLU/initTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/initTLU.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/legacy/miniTLU/miniTLU.py b/AIDA_tlu/legacy/miniTLU/miniTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..e874a6f58621d9367d17d5e8fdffb88fdfdc63e7
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/miniTLU.py
@@ -0,0 +1,462 @@
+import uhal;
+from FmcTluI2c import *
+from I2CuHal import I2CCore
+
+class MiniTLU:
+    """docstring for miniTLU"""
+    def __init__(self, dev_name, man_file):
+        self.dev_name = dev_name
+        self.manager= uhal.ConnectionManager(man_file)
+        self.hw = self.manager.getDevice(self.dev_name)
+        self.nChannels= 4
+        self.VrefInt= 2.5 #Internal DAC voltage reference
+        self.VrefExt= 1.3 #External DAC voltage reference
+        self.intRefOn= False #Internal reference is OFF by default
+
+        self.fwVersion = self.hw.getNode("version").read()
+        self.hw.dispatch()
+        print "uHAL VERSION= " , hex(self.fwVersion)
+
+        # Instantiate a I2C core to configure the DACs
+        self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
+        self.TLU_I2C.state()
+
+
+    def initialize(self):
+        print "miniTLU INITIALIZING..."
+        # We need to pass it listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage
+
+        print "\tTurning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        #READ CONTENT OF EPROM VIA I2C
+        self.getSN()
+
+        #SET DACs
+        targetV= 1.1
+        intRef= False
+        self.setDACintRef(intRef)
+        DACchannel= 7
+        self.writeThreshold(targetV, DACchannel)
+
+        #Check clock status
+        self.checkClkStatus()
+
+        resetClocks = 0
+        resetSerdes = 0
+        if resetClocks:
+            self.resetClocks()
+        if resetSerdes:
+            self.resetSerdes()
+
+        # Get inputs status and counters
+        self.getChStatus()
+        self.getAllChannelsCounts()
+
+        # Stop internal triggers until setup complete
+        cmd = int("0x0",16)
+        self.setInternalTrg(cmd)
+
+        # Set pulse stretch
+        pulseStretch= 0x000FFFFF
+        self.setPulseStretch(pulseStretch)
+
+        # Set pulse delay
+        pulseDelay= 0x0
+        #self.setPulseDelay(pulseDelay) #NEED TO FIX ADDRESS TABLE
+
+        # Set trigger pattern
+        triggerPattern= 0x0
+        self.setTrgPattern(triggerPattern)
+
+        # Set DUTs
+        DUTMask= 0x1
+        self.setDUTmask(DUTMask)
+
+        # # Set mode
+        DUTMode= 0x0
+        self.setMode(DUTMode)
+
+        # # Set modifier
+        modifier = int("0xFF",16) 
+        self.setModeModifier(modifier)
+
+        # Set veto shutter
+        setVetoShutters=0
+        self.setVetoShutters(setVetoShutters)
+
+        # Set veto by DUT
+        ignoreDUTBusy=0x0
+        self.setVetoDUT(ignoreDUTBusy)
+
+        # Set trigger interval (use 0 to disable internal triggers)
+        triggerInterval=0
+        self.setInternalTrg(triggerInterval)
+
+        print "miniTLU INITIALIZED"
+
+    def setModeModifier(self, modifier):
+        print "\tDUT MODE MODIFIER:",modifier
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
+        self.hw.dispatch()
+        self.getModeModifier()
+
+    def getModeModifier(self):
+        DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
+        self.hw.dispatch()
+        print "\t  DUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
+        return DUTInterfaceModeModifierR
+
+    def resetClock(self):
+        print "\tClocks reset"
+        cmd = int("0x1",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def getClockStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "\t  Clock status=" , hex(clockStatus)
+        return clockStatus
+
+    def readEEPROM(self, startadd, bytes):
+        mystop= 1
+        time.sleep(0.1)
+        myaddr= [startadd]#0xfa
+        self.TLU_I2C.write( 0x50, [startadd], mystop)
+        res= self.TLU_I2C.read( 0x50, bytes)
+        return res
+
+    def getSN(self):
+        epromcontent=self.readEEPROM(0xfa, 6)
+        print "\tFMC-TLU serial number (EEPROM):"
+        result="\t  "
+        for iaddr in epromcontent:
+            result+="%02x "%(iaddr)
+        print result
+        return epromcontent
+
+    def writeThreshold(self, Vtarget, channel):
+        #Writes the threshold. The DAC voltage differs from the threshold voltage because
+        #the range is shifted to be symmetrical around 0V.
+
+        #Check if the DACs are using the internal reference
+        if (self.intRefOn):
+            Vref= self.VrefInt
+        else:
+            Vref= self.VrefExt
+
+        #Calculate offset voltage (because of the following shifter)
+        Vdac= ( Vtarget + Vref ) / 2
+        print"\tTHRESHOLD setting:"
+        if channel==7:
+            print "\t  CH: ALL"
+        else:
+            print "\t  CH:", channel
+        print "\t  Target V:", Vtarget
+        dacValue = 0xFFFF * Vtarget / Vref
+        self.writeDAC(int(dacValue), channel)
+
+    def writeDAC(self, dacCode, channel):
+        #Vtarget is the required voltage, channel is the DAC channel to target
+        #intRef indicates whether to use the external voltage reference (True)
+        #or the internal one (False).
+
+        i2cSlaveAddrDac = 0x1F
+
+        print "\t  DAC value:"  , dacCode
+        if channel<0 or channel>7:
+            print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            ##return -1
+        if dacCode<0:
+            print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
+            dacCode=0
+        elif dacCode>0xFFFF :
+            print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
+            dacCode=0xFFFF
+
+        sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+        print "\t  Writing DAC string:", sequence
+        self.TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
+
+    # def readDAC(self, channel):
+    #     #TO BE DONE
+    #     i2cSlaveAddrDac = 0x1F
+    #     bytes= 3
+    #     if channel<0 or channel>7:
+    #         print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
+    #         ##return -1
+    #     cmdDAC=[( 0x18 + ( channel &0x7 ) ) ]
+    #     self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
+    #     res= self.TLU_I2C.read( i2cSlaveAddrDac, bytes)
+    #     print res
+
+    def setDACintRef(self, intRef=False):
+        i2cSlaveAddrDac = 0x1F
+        self.intRefOn= intRef
+        if intRef:
+            print "\tDAC internal reference ON"
+            cmdDAC= [0x38,0x00,0x01]
+        else:
+            print "\tDAC internal reference OFF"
+            cmdDAC= [0x38,0x00,0x00]
+        self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
+
+    # def getDACintRef(self):
+    #     #TO BE FIXED!
+    #     bytes= 3
+    #     i2cSlaveAddrDac = 0x1F
+    #     cmdDAC= [0x78]
+    #     self.TLU_I2C.write( i2cSlaveAddrDac, cmdDAC, 0)
+    #     res= self.TLU_I2C.read( i2cSlaveAddrDac, bytes)
+    #     print res
+
+    def setTrgPattern(self, triggerPattern):
+        triggerPattern &= 0xffffffff
+        print "\tTRIGGER PATTERN (for external triggers) SET TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+        self.hw.getNode("triggerLogic.TriggerPatternW").write(triggerPattern)
+        self.hw.dispatch()
+        self.getTrgPattern()
+
+    def getTrgPattern(self):
+        triggerPatternR = self.hw.getNode("triggerLogic.TriggerPatternR").read()
+        self.hw.dispatch()
+        print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+        return triggerPatternR
+
+    def setDUTmask(self, DUTMask):
+        print "\tDUT MASK ENABLING: Mask= " , hex(DUTMask)
+        self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
+        self.hw.dispatch()
+        self.getDUTmask()
+
+    def getDUTmask(self):
+        DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
+        self.hw.dispatch()
+        print "\t  DUTMask read back as:" , hex(DUTMaskR)
+        return DUTMaskR
+
+    def setVetoShutters(self, newState):
+        if newState:
+            print "\tIgnoreShutterVetoW SET TO LISTEN FOR VETO FROM SHUTTER"
+            cmd= int("0x0",16)
+        else:
+            print "\tIgnoreShutterVetoW SET TO IGNORE VETO FROM SHUTTER"
+            cmd= int("0x1",16)
+        self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
+        self.hw.dispatch()
+        self.getVetoShutters()
+
+    def getVetoShutters(self):
+        IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
+        self.hw.dispatch()
+        print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+        return IgnoreShutterVeto
+
+    def setVetoDUT(self, ignoreDUTBusy):
+        print "\tVETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
+        self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
+        self.hw.dispatch()
+        self.getVetoDUT()
+
+    def getVetoDUT(self):
+        IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
+        self.hw.dispatch()
+        print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
+        return IgnoreDUTBusyR
+
+    def setInternalTrg(self, triggerInterval):
+        print "\tTRIGGERS INTERNAL:"
+        if triggerInterval == 0:
+            internalTriggerFreq = 0
+            print "\t  disabled"
+        else:
+            internalTriggerFreq = 160000.0/triggerInterval
+            print "\t  Setting:", internalTriggerFreq, "Hz"
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
+        self.hw.dispatch()
+        self.getInternalTrg()
+
+    def getInternalTrg(self):
+        trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\t  Trigger frequency read back as:", trigIntervalR, "Hz"
+        return trigIntervalR
+
+    def checkClkStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "\tCLOCK STATUS [expected 3]"
+        print "\t ", hex(clockStatus)
+        assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+        return clockStatus
+
+    def setPulseStretch(self, pulseStretch):
+        print "\tINPUT COINCIDENCE WINDOW SET TO", hex(pulseStretch) ,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(pulseStretch)
+        self.hw.dispatch()
+        self.getPulseStretch()
+
+    def getPulseStretch(self):
+        pulseStretchR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+        return pulseStretchR
+
+    def getChCount(self, channel):
+        regString= "triggerInputs.ThrCount"+ str(channel)+"R"
+        count = self.hw.getNode(regString).read()
+        self.hw.dispatch()
+        print "\t  Ch", channel, "Count:" , count
+        return count
+
+    def getChStatus(self):
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\t  Input status= " , hex(inputStatus)
+        return inputStatus
+
+    def setChStatus(self, cmd):
+        self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\tINPUT STATUS SET TO= " , hex(inputStatus)
+
+    def resetSerdes(self):
+        cmd = int("0x3",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during reset = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after reset = " , hex(inputStatus)
+
+        cmd = int("0x4",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during calibration = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after calibration = " , hex(inputStatus)
+
+    def resetClocks(self):
+        #Reset clocks
+        self.resetClock()
+        #Get clock status after reset
+        self.getClockStatus()
+        #Get serdes status
+        self.getChStatus()
+
+    def getAllChannelsCounts(self):
+        chCounts=[]
+        for ch in range (0,self.nChannels):
+            chCounts.append(int(self.getChCount(ch)))
+        return chCounts
+
+    def setPulseDelay(self, pulseDelay):
+        print "\tTRIGGER DELAY SET TO", pulseDelay, "[Units= 160MHz clock, Four 5-bit values (one per input) packed in to 32-bit word]"
+        self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
+        self.hw.dispatch()
+        self.getPulseDelay()
+
+    def getPulseDelay(self):
+        pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
+        self.hw.dispatch()
+        print "\t  Pulse delay read back as:", hex(pulseDelayR)
+        return pulseDelayR
+
+    def setMode(self, mode):
+        print "\tDUT MODE SET TO: ", mode
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
+        self.hw.dispatch()
+        self.getMode()
+
+    def getMode(self):
+        DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
+        self.hw.dispatch()
+        print "\t  DUT mode read back as:" , DUTInterfaceModeR
+        return DUTInterfaceModeR
+
+    def setFifoCSR(self, cmd):
+        self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
+        self.hw.dispatch()
+        self.getFifoCSR()
+
+    def getFifoCSR(self):
+        FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
+        self.hw.dispatch()
+        print "\t  FIFO CSR read back as:", hex(FifoCSR)
+        return FifoCSR
+
+    def getFifoLevel(self):
+        FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
+        self.hw.dispatch()
+        print "\t  FIFO level read back as:", hex(FifoFill)
+        return FifoFill
+
+    def setRecordDataStatus(self, status=False):
+        self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
+        self.hw.dispatch()
+        self.getRecordDataStatus()
+
+    def getRecordDataStatus(self):
+        RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
+        self.hw.dispatch()
+        print "\t  Data recording:", RecordStatus
+        return RecordStatus
+
+    def pulseT0(self):
+        cmd = int("0x1",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tPulsing T0"
+
+    def setTriggerVetoStatus(self, status=False):
+        self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
+        self.hw.dispatch()
+        self.getTriggerVetoStatus()
+
+    def getTriggerVetoStatus(self):
+        trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
+        self.hw.dispatch()
+        print "\t  Trigger veto status read back as:", trgVetoStatus
+        return trgVetoStatus
+
+    def start(self, logtimestamps=False):
+        print "miniTLU STARTING..."
+
+        print "\tFIFO RESET:"
+        FIFOcmd= 0x2
+        self.setFifoCSR(FIFOcmd)
+
+        eventFifoFillLevel= self.getFifoLevel()
+
+        if logtimestamps:
+            print "\tData recording set: ON"
+            self.setRecordDataStatus(True)
+        else:
+            print "\tData recording set: OFF"
+            self.setRecordDataStatus(False)
+
+        # Pulse T0
+        self.pulseT0()
+
+        print "\tTurning off software trigger veto"
+        cmd = int("0x0",16)
+        self.setTriggerVetoStatus(cmd)
+
+        print "miniTLU RUNNING"
+
+    def stop(self):
+        print "miniTLU STOPPING..."
+
+        print "\tTurning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        print "miniTLU STOPPED"
diff --git a/AIDA_tlu/legacy/miniTLU/miniTLU.xml b/AIDA_tlu/legacy/miniTLU/miniTLU.xml
new file mode 100644
index 0000000000000000000000000000000000000000..78196f08373185f74acb0672e025b3f106b2bf9b
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/miniTLU.xml
@@ -0,0 +1,87 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="miniTLU">
+
+<node id="DUTInterfaces" address="0x020" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="triggerInputs" address="0x040" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+</node>
+
+<!--PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+<node id="triggerLogic" address="0x060" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <node id="TriggerPatternW" address="0x3" permission="w" description="" />
+  <node id="TriggerPatternR" address="0x13" permission="r" description="" />
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" />
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+</node>
+
+<node id="eventBuffer" address="0x080" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+
+
+<node id="logic_clocks" address="0x0A0" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="i2c_master"      address="0x0C0" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+
+<node id="Event_Formatter"      address="0x140" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x160" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+
+<node id="version" address="0x0" description="firmware version" permission="r">
+</node>
+
+
+</node>
diff --git a/AIDA_tlu/legacy/miniTLU/miniTLU_old.xml b/AIDA_tlu/legacy/miniTLU/miniTLU_old.xml
new file mode 100644
index 0000000000000000000000000000000000000000..ec0373c4a420e9255232fe99480c8c29268984f9
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/miniTLU_old.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="miniTLU">
+
+<node id="DUTInterfaces" address="0x020" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DutMaskR"           address="0x4" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x5" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0x6" permission="r" description="" />
+</node>
+
+<node id="triggerInputs" address="0x040" description="Inputs configuration">
+  <node id="SerdesRst" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+</node>
+
+<node id="triggerLogic" address="0x060" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <node id="TriggerPatternW" address="0x3" permission="w" description="" />
+  <node id="TriggerPatternR" address="0x13" permission="r" description="" />
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" />
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="r" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+</node>
+
+<node id="eventBuffer" address="0x080" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+
+<node id="logic_clocks" address="0x0A0" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="i2c_master" address="0x0C0" description="I2C Master interface">
+  <node id="i2c_pre_lo" address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi" address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl" address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx" address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+
+
+
+<node id="Event_Formatter" address="0x140" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW" address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+
+<node id="version" address="0x0" description="firmware version" permission="r">
+</node>
+
+
+</node>
diff --git a/AIDA_tlu/legacy/miniTLU/startTLU_v6.py b/AIDA_tlu/legacy/miniTLU/startTLU_v6.py
new file mode 100644
index 0000000000000000000000000000000000000000..b7948f204682346e898a3126ac22b3e8aaa310a8
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/startTLU_v6.py
@@ -0,0 +1,232 @@
+#
+# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
+#
+# David Cussans, December 2012
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+
+import time
+
+from datetime import datetime
+
+from optparse import OptionParser
+
+# For single character non-blocking input:
+import select
+import tty
+import termios
+
+from initTLU import *
+
+def isData():
+    return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
+
+now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+default_filename = 'tluData_' + now + '.root'
+parser = OptionParser()
+
+parser.add_option('-r','--rootFname',dest='rootFname',
+                       default=default_filename,help='Path of output file')
+parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
+                       default="True",help='Set True to write timestamps to ROOT file')
+parser.add_option('-p','--printTimestamps',dest='printTimestamps',
+                       default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
+parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
+                       default=False,help='Set True to veto triggers when shutter goes high')
+parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
+                       default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
+parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
+                       default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
+parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
+                       default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
+parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
+                       default=0x01,help='Three-bit mask selecting which DUTs are active.')
+parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
+                       default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
+parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
+                       default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
+parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
+                       default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
+
+(options, args) = parser.parse_args(sys.argv[1:])
+
+from ROOT import TFile, TTree
+from ROOT import gROOT
+
+print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+
+# Point to board in uHAL
+manager = uhal.ConnectionManager("file://./connection.xml")
+hw = manager.getDevice("minitlu")
+device_id = hw.id()
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+# Assume DIP-switch controlled address. Switches at 2
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Open Root file
+print "OPENING ROOT FILE:", options.rootFname
+f = TFile( options.rootFname, 'RECREATE' )
+
+# Create a root "tree"
+tree = TTree( 'T', 'TLU Data' )
+highWord =0
+lowWord =0
+evtNumber=0
+timeStamp=0
+evtType=0
+trigsFired=0
+bufPos = 0
+
+# Create a branch for each piece of data
+tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+
+# Initialize TLU registers
+initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
+
+loopWait = 0.1
+oldEvtNumber = 0
+
+oldPreVetotriggerCount = board.read("PreVetoTriggersR")
+oldPostVetotriggerCount = board.read("PostVetoTriggersR")
+
+oldThresholdCounter0 =0
+oldThresholdCounter1 =0
+oldThresholdCounter2 =0
+oldThresholdCounter3 =0
+
+print "STARTING POLLING LOOP"
+
+eventFifoFillLevel = 0
+loopRunning = True
+runStarted = False
+
+oldTime = time.time()
+
+# Save old terminal settings
+oldTermSettings = termios.tcgetattr(sys.stdin)
+tty.setcbreak(sys.stdin.fileno())
+
+while loopRunning:
+
+    if isData():
+        c = sys.stdin.read(1)
+        print "\tGOT INPUT:", c
+        if c == 't':
+            loopRunning = False
+            print "\tTERMINATING LOOP"
+        elif c == 'c':
+            runStarted = True
+            print "\tSTARTING RUN"
+            startTLU( uhalDevice = hw, pychipsBoard = board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        elif c == 'f':
+            # runStarted = True
+            print "\tSTOPPING TRIGGERS"
+            stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+
+    if runStarted:
+
+        eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
+
+        preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
+        postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
+
+        timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
+        timestampLow  = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+
+        thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
+        thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
+        thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
+        thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
+
+        hw.dispatch()
+
+        newTime = time.time()
+        timeDelta = newTime - oldTime
+        oldTime = newTime
+        #print "time delta = " , timeDelta
+        preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
+        postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
+        oldPreVetotriggerCount = preVetotriggerCount
+        oldPostVetotriggerCount = postVetotriggerCount
+
+        deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
+        oldThresholdCounter0 = thresholdCounter0
+        deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
+        oldThresholdCounter1 = thresholdCounter1
+        deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
+        oldThresholdCounter2 = thresholdCounter2
+        deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
+        oldThresholdCounter3 = thresholdCounter3
+
+        print "pre , post  veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
+
+        print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
+
+        print "Input counts 0,1,2,3 = "      , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
+        print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
+
+        nEvents = int(eventFifoFillLevel)//4  # only read out whole events ( 4 x 32-bit words )
+        wordsToRead =  nEvents*4
+
+        print "FIFO FILL LEVEL= " , eventFifoFillLevel
+
+        print "# EVENTS IN FIFO = ",nEvents
+        print "WORDS TO READ FROM FIFO  = ",wordsToRead
+
+        # get timestamp data and fifo fill in same outgoing packet.
+        timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
+
+        hw.dispatch()
+
+    #    print timestampData
+        for bufPos in range (0, nEvents ):
+            lowWord  = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
+
+            highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
+            evtNumber = timestampData[bufPos*4 + 3]
+
+            if evtNumber != ( oldEvtNumber + 1 ):
+                print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ",  evtNumber , oldEvtNumber
+
+            oldEvtNumber = evtNumber
+
+            timeStamp = lowWord & 0xFFFFFFFFFFFF
+
+            evtType = timestampData[ (bufPos*4) + 0] >> 28
+
+            trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
+
+            if (options.printTimestamps == "True" ):
+                print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
+
+            # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
+            tree.Fill()
+
+    time.sleep( loopWait)
+
+# Fixme - at the moment infinite loop.
+preVetotriggerCount = board.read("PreVetoTriggersR")
+postVetotriggerCount = board.read("PostVetoTriggersR")
+print "EXIT POLLING LOOP"
+print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
+
+termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
+f.Write()
+f.Close()
diff --git a/AIDA_tlu/legacy/miniTLU/startTLU_v6.sh b/AIDA_tlu/legacy/miniTLU/startTLU_v6.sh
new file mode 100755
index 0000000000000000000000000000000000000000..beef09b12cfe802268810552788568e28e8c5e58
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/startTLU_v6.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+
+echo "=========================="
+CURRENT_DIR=${0%/*}
+echo "CURRENT DIRECTORY: " $CURRENT_DIR
+
+echo "============"
+echo "SETTING PATHS"
+#export PYTHONPATH=$CURRENT_DIR/../../../../PyChips_1_5_0_pre2A/src
+export PYTHONPATH=$CURRENT_DIR/../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+echo "PYTHON PATH= " $PYTHONPATH
+export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
+echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
+export PATH=/usr/bin/:/opt/cactus/bin:$PATH
+echo "PATH= " $PATH
+
+cd $CURRENT_DIR
+
+echo "============"
+echo "STARTING PYTHON SCRIPT"
+#python $CURRENT_DIR/startTLU_v8.py $@
+
+python startTLU_v8.py $@
+#python testTLU_script.py
diff --git a/AIDA_tlu/legacy/miniTLU/startTLU_v8.py b/AIDA_tlu/legacy/miniTLU/startTLU_v8.py
new file mode 100644
index 0000000000000000000000000000000000000000..2ad4aace350a08f673fa462769afc79548bc5094
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/startTLU_v8.py
@@ -0,0 +1,70 @@
+# miniTLU test script
+
+#from PyChipsUser import *
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from miniTLU import MiniTLU
+# Use to have interactive shell
+import cmd
+
+class MyPrompt(cmd.Cmd):
+
+
+    def do_startRun(self, args):
+	"""Starts the TLU run"""
+	print "COMMAND RECEIVED: STARTING TLU RUN"
+	startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+	#print self.hw
+
+    def do_stopRun(self, args):
+	"""Stops the TLU run"""
+	print "COMMAND RECEIVED: STOP TLU RUN"
+	#stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "COMMAND RECEIVED: QUITTING SCRIPT."
+        #raise SystemExit
+	return True
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    miniTLU.initialize()
+
+    logdata= False
+    miniTLU.start(logdata)
+    miniTLU.stop()
+    # prompt = MyPrompt()
+    # prompt.prompt = '>> '
+    # prompt.cmdloop("Welcome to miniTLU test console.\nType HELP for a list of commands.")
diff --git a/AIDA_tlu/legacy/miniTLU/testTLU_script.py b/AIDA_tlu/legacy/miniTLU/testTLU_script.py
new file mode 100644
index 0000000000000000000000000000000000000000..9d8b334bb4a6fd01050c3d622f54847616fce208
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/testTLU_script.py
@@ -0,0 +1,79 @@
+# miniTLU test script
+
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+from I2CuHal import I2CCore
+from miniTLU import MiniTLU
+from datetime import datetime
+
+if __name__ == "__main__":
+    print "\tTEST TLU SCRIPT"
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    #(self, target, wclk, i2cclk, name="i2c", delay=None)
+    TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
+    TLU_I2C.state()
+
+
+    #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
+    mystop= 1
+    time.sleep(0.1)
+    myaddr= [0xfa]
+    TLU_I2C.write( 0x50, myaddr, mystop)
+    res=TLU_I2C.read( 0x50, 6)
+    print "Checkin EEPROM:"
+    result="\t"
+    for iaddr in res:
+        result+="%02x "%(iaddr)
+    print result
+
+    #SCAN I2C ADDRESSES
+    #WRITE PROM
+    #WRITE DAC
+
+
+    #Convert required threshold voltage to DAC code
+    #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+    print("Writing DAC setting:")
+    Vref= 1.300
+    desiredVoltage= 3.3
+    channel= 0
+    i2cSlaveAddrDac = 0x1F
+    vrefOn= 0
+    Vdaq = ( desiredVoltage + Vref ) / 2
+    dacCode = 0xFFFF * Vdaq / Vref
+    dacCode= 0x391d
+    print "\tVreq:", desiredVoltage
+    print "\tDAC code:"  , dacCode
+    print "\tCH:", channel
+    print "\tIntRef:", vrefOn
+
+    #Set DAC value
+    #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+    if channel<0 or channel>7:
+        print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+        ##return -1
+    if dacCode<0 or dacCode>0xFFFF:
+        print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
+        ##return -1
+    # AD5665R chip with A0,A1 tied to ground
+    #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+
+    # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+    # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+    # # if we want to enable internal voltage reference:
+
+    if vrefOn:
+        # enter vref-on mode:
+        print "\tTurning internal reference ON"
+        #dac.write([0x38,0x00,0x01])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
+    else:
+        print "\tTurning internal reference OFF"
+        #dac.write([0x38,0x00,0x00])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
+    # Now set the actual value
+    sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+    print "\tWriting byte sequence:", sequence
+    TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/AIDA_tlu/legacy/miniTLU/test_T0.py b/AIDA_tlu/legacy/miniTLU/test_T0.py
new file mode 100644
index 0000000000000000000000000000000000000000..cf81b33d0fcac1767da1923d9abb62634a5885a2
--- /dev/null
+++ b/AIDA_tlu/legacy/miniTLU/test_T0.py
@@ -0,0 +1,92 @@
+#
+# Script to exercise AIDA mini-TLU
+#
+# David Cussans, December 2012
+# 
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+# Assume DIP-switch controlled address. Switches at 2 
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+firmwareID=board.read("FirmwareId")
+
+print "Firmware (from PyChips) = " , hex(firmwareID)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+ 
+
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+    print "Resetting clocks"
+    board.write("LogicRst", 1 )
+
+    clockStatus = board.read("LogicClocksCSR")
+    print "Clock status after reset = " , hex(clockStatus)
+
+
+board.write("InternalTriggerIntervalW",0)
+
+print "Enabling DUT 0 and 1"
+board.write("DUTMaskW",3)
+DUTMask = board.read("DUTMaskR")
+print "DUTMaskR = " , DUTMask
+
+print "Ignore veto on DUT 0 and 1"
+board.write("IgnoreDUTBusyW",3)
+IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
+print "IgnoreDUTBusyR = " , IgnoreDUTBusy
+
+print "Turning off software trigger veto"
+board.write("TriggerVetoW",0)
+
+print "Reseting FIFO"
+board.write("EventFifoCSR",0x2)
+eventFifoFillLevel = board.read("EventFifoFillLevel")
+print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
+
+print "Enabling data recording"
+board.write("Enable_Record_Data",1)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+#TriggerInterval = 400000
+TriggerInterval = 0
+print "Setting internal trigger interval to " , TriggerInterval
+board.write("InternalTriggerIntervalW",TriggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+trigInterval = board.read("InternalTriggerIntervalR")
+print "Trigger interval read back as ", trigInterval
+
+print "Setting TPix_maskexternal to ignore external shutter and T0"
+board.write("TPix_maskexternal",0x0003)
+
+numLoops = 500000
+oldEvtNumber = 0
+
+for iLoop in range(0,numLoops):
+
+    board.write("TPix_T0", 0x0001)
+
+#   time.sleep( 1.0)
diff --git a/AIDA_tlu/legacy/packages/AD5665R.py b/AIDA_tlu/legacy/packages/AD5665R.py
new file mode 100644
index 0000000000000000000000000000000000000000..d7d507deeef43c352caf7443cda2700cc72c4334
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/AD5665R.py
@@ -0,0 +1,45 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+
+class AD5665R:
+    #Class to configure the DAC modules
+
+    def __init__(self, i2c, slaveaddr=0x1F):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def setIntRef(self, intRef=False, verbose=False):
+        mystop=True
+        if intRef:
+            cmdDAC= [0x38,0x00,0x01]
+        else:
+            cmdDAC= [0x38,0x00,0x00]
+        self.i2c.write( self.slaveaddr, cmdDAC, mystop)
+        if verbose:
+            print "DAC int ref:", intRef
+
+
+    def writeDAC(self, dacCode, channel, verbose=False):
+        #Vtarget is the required voltage, channel is the DAC channel to target
+        #intRef indicates whether to use the external voltage reference (True)
+        #or the internal one (False).
+
+        print "\tDAC value:"  , hex(dacCode)
+        if channel<0 or channel>7:
+            print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            return -1
+        if dacCode<0:
+            print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
+            dacCode=0
+        elif dacCode>0xFFFF :
+            print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
+            dacCode=0xFFFF
+
+        sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+        print "\tWriting DAC string:", sequence
+        mystop= False
+        self.i2c.write( self.slaveaddr, sequence, mystop)
diff --git a/AIDA_tlu/legacy/packages/E24AA025E48T.py b/AIDA_tlu/legacy/packages/E24AA025E48T.py
new file mode 100644
index 0000000000000000000000000000000000000000..32cc429c6310b7cd25bf4bc43092a66c04e43714
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/E24AA025E48T.py
@@ -0,0 +1,20 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class E24AA025E48T:
+    #Class to configure the EEPROM
+
+    def __init__(self, i2c, slaveaddr=0x50):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def readEEPROM(self, startadd, nBytes):
+        #Read EEPROM memory locations
+        mystop= False
+        myaddr= [startadd]#0xfa
+        self.i2c.write( self.slaveaddr, [startadd], mystop)
+        res= self.i2c.read( self.slaveaddr, nBytes)
+        return res
diff --git a/AIDA_tlu/legacy/packages/FmcTluI2c.py b/AIDA_tlu/legacy/packages/FmcTluI2c.py
new file mode 100644
index 0000000000000000000000000000000000000000..04bf5985fbde260c2668c587628b8919f8080508
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/FmcTluI2c.py
@@ -0,0 +1,132 @@
+import time
+#from PyChipsUser import *
+from I2cBusProperties import *
+from RawI2cAccess import *
+
+
+class FmcTluI2c:
+
+
+    ############################
+    ### configure i2c connection
+    ############################
+    def __init__(self,board):
+        self.board = board
+        i2cClockPrescale = 0x30
+        self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
+        return
+
+
+    ##########################
+    ### scan all i2c addresses
+    ##########################
+    def i2c_scan(self):
+        list=[]
+        for islave in range(128):
+            i2cscan = RawI2cAccess(self.i2cBusProps, islave)
+            try:
+                i2cscan.write([0x00])
+                device="slave address "+hex(islave)+" "
+                if islave==0x1f:
+                    device+="(DAC)"
+                elif islave==0x50:
+                    device+="(serial number PROM)"
+                elif islave>=0x54 and islave<=0x57:
+                    device+="(sp601 onboard EEPROM)"
+                else:
+                    device+="(???)"
+                    pass
+                list.append(device)
+                pass
+            except:
+                pass
+            pass
+        return list
+
+
+    ###################
+    ### write to EEPROM
+    ###################
+    def eeprom_write(self,address,value):
+        if address<0 or address>127:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        if value<0 or value>255:
+            print "eeprom_write ERROR: value",value,"not in range 0-255"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address,value])
+        time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
+        return
+
+
+    ####################
+    ### read from EEPROM
+    ####################
+    def eeprom_read(self,address):
+        if address<0 or address>255:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address])
+        return prom.read(1)[0]
+
+
+    ######################
+    ### read serial number
+    ######################
+    def get_serial_number(self):
+        result=""
+        for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
+            result+="%02x "%(self.eeprom_read(iaddr))
+            pass
+        return result
+
+
+    #################
+    ### set DAC value
+    #################
+    def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+        if channel<0 or channel>7:
+            print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            return -1
+        if value<0 or value>0xFFFF:
+            print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
+            return -1
+        # AD5665R chip with A0,A1 tied to ground
+        #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+        print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+        dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+        # if we want to enable internal voltage reference:
+        if vrefOn:
+            # enter vref-on mode:
+	    print "Turning internal reference ON"
+            dac.write([0x38,0x00,0x01])
+        else:
+	    print "Turning internal reference OFF"
+            dac.write([0x38,0x00,0x00])
+        # now set the actual value
+        sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
+        print sequence
+        dac.write(sequence)
+
+
+
+    ##################################################
+    ### convert required threshold voltage to DAC code
+    ##################################################
+    def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+        Vdaq = ( desiredVoltage + Vref ) / 2
+        dacCode = 0xFFFF * Vdaq / Vref
+        return int(dacCode)
+
+
+    ##################################################
+    ### calculate the DAC code required and set DAC
+    ##################################################
+    def set_threshold_voltage(self, channel , voltage ):
+        dacCode = self.convert_voltage_to_dac(voltage)
+        print " requested voltage, calculated DAC code = " , voltage , dacCode
+        self.set_dac(channel , dacCode)
diff --git a/AIDA_tlu/legacy/packages/I2CuHal.py b/AIDA_tlu/legacy/packages/I2CuHal.py
new file mode 100644
index 0000000000000000000000000000000000000000..b51169a7df0bada9ceb75f5daeae03b7fab9841d
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/I2CuHal.py
@@ -0,0 +1,281 @@
+# -*- coding: utf-8 -*-
+"""
+
+"""
+
+import time
+
+import uhal
+
+verbose = True
+
+
+
+################################################################################
+# /*
+#        I2C CORE
+# */
+################################################################################
+
+
+
+
+class I2CCore:
+    """I2C communication block."""
+
+    # Define bits in cmd_stat register
+    startcmd = 0x1 << 7
+    stopcmd = 0x1 << 6
+    readcmd = 0x1 << 5
+    writecmd = 0x1 << 4
+    ack = 0x1 << 3
+    intack = 0x1
+
+    recvdack = 0x1 << 7
+    busy = 0x1 << 6
+    arblost = 0x1 << 5
+    inprogress = 0x1 << 1
+    interrupt = 0x1
+
+    def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
+        self.target = target
+        self.name = name
+        self.delay = delay
+        self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
+        self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
+        self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
+        self.data = self.target.getNode("%s.i2c_rxtx" % name)
+        self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
+        self.wishboneclock = wclk
+        self.i2cclock = i2cclk
+        self.config()
+
+    def state(self):
+        status = {}
+        status["ps_low"] = self.prescale_low.read()
+        status["ps_hi"] = self.prescale_high.read()
+        status["ctrl"] = self.ctrl.read()
+        status["data"] = self.data.read()
+        status["cmd_stat"] = self.cmd_stat.read()
+        self.target.dispatch()
+        status["prescale"] = status["ps_hi"] << 8
+        status["prescale"] |= status["ps_low"]
+        for reg in status:
+            val = status[reg]
+            bval = bin(int(val))
+            if verbose:
+                print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
+
+    def clearint(self):
+        self.ctrl.write(0x1)
+        self.target.dispatch()
+
+    def config(self):
+        #INITIALIZATION OF THE I2S MASTER CORE
+        #Disable core
+        self.ctrl.write(0x0 << 7)
+        self.target.dispatch()
+        #Write pre-scale register
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
+        prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
+        #prescale = 0x2710 #FOR NOW HARDWIRED, TO BE MODIFIED
+        self.prescale_low.write(prescale & 0xff)
+        self.prescale_high.write((prescale & 0xff00) >> 8)
+        #Enable core
+        self.ctrl.write(0x1 << 7)
+        self.target.dispatch()
+
+    def checkack(self):
+        inprogress = True
+        ack = False
+        while inprogress:
+            cmd_stat = self.cmd_stat.read()
+            self.target.dispatch()
+            inprogress = (cmd_stat & I2CCore.inprogress) > 0
+            ack = (cmd_stat & I2CCore.recvdack) == 0
+        return ack
+
+    def delayorcheckack(self):
+        ack = True
+        if self.delay is None:
+            ack = self.checkack()
+        else:
+            time.sleep(self.delay)
+            ack = self.checkack()#Remove this?
+        return ack
+
+################################################################################
+# /*
+#        I2C WRITE
+# */
+################################################################################
+
+
+
+    def write(self, addr, data, stop=True):
+        """Write data to the device with the given address."""
+        # Start transfer with 7 bit address and write bit (0)
+        nwritten = -1
+        addr &= 0x7f
+        addr = addr << 1
+        startcmd = 0x1 << 7
+        stopcmd = 0x1 << 6
+        writecmd = 0x1 << 4
+        #Set transmit register (write operation, LSB=0)
+        self.data.write(addr)
+        #Set Command Register to 0x90 (write, start)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return nwritten
+        nwritten += 1
+        for val in data:
+            val &= 0xff
+            #Write slave memory address
+            self.data.write(val)
+            #Set Command Register to 0x10 (write)
+            self.cmd_stat.write(I2CCore.writecmd)
+            self.target.dispatch()
+            ack = self.delayorcheckack()
+            if not ack:
+                self.cmd_stat.write(I2CCore.stopcmd)
+                self.target.dispatch()
+                return nwritten
+            nwritten += 1
+        if stop:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+        return nwritten
+
+################################################################################
+# /*
+#        I2C READ
+# */
+################################################################################
+    def read(self, addr, n):
+        """Read n bytes of data from the device with the given address."""
+        # Start transfer with 7 bit address and read bit (1)
+        data = []
+        addr &= 0x7f
+        addr = addr << 1
+        addr |= 0x1 # read bit
+        self.data.write(addr)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return data
+        for i in range(n):
+            if i < (n-1):
+                self.cmd_stat.write(I2CCore.readcmd) # <---
+            else:
+                self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
+	        self.target.dispatch()
+            ack = self.delayorcheckack()
+            val = self.data.read()
+            self.target.dispatch()
+            data.append(val & 0xff)
+        #self.cmd_stat.write(I2CCore.stopcmd)
+        #self.target.dispatch()
+        return data
+
+################################################################################
+# /*
+#        I2C WRITE-READ
+# */
+################################################################################
+
+
+
+    # def writeread(self, addr, data, n):
+    #     """Write data to device, then read n bytes back from it."""
+    #     nwritten = self.write(addr, data, stop=False)
+    #     readdata = []
+    #     if nwritten == len(data):
+    #         readdata = self.read(addr, n)
+    #     return nwritten, readdata
+
+"""
+SPI core XML:
+
+<node description="SPI master controller" fwinfo="endpoint;width=3">
+    <node id="d0" address="0x0" description="Data reg 0"/>
+    <node id="d1" address="0x1" description="Data reg 1"/>
+    <node id="d2" address="0x2" description="Data reg 2"/>
+    <node id="d3" address="0x3" description="Data reg 3"/>
+    <node id="ctrl" address="0x4" description="Control reg"/>
+    <node id="divider" address="0x5" description="Clock divider reg"/>
+    <node id="ss" address="0x6" description="Slave select reg"/>
+</node>
+"""
+class SPICore:
+
+    go_busy = 0x1 << 8
+    rising = 1
+    falling = 0
+
+
+    def __init__(self, target, wclk, spiclk, basename="io.spi"):
+        self.target = target
+        # Only a single data register is required since all transfers are
+        # 16 bit long
+        self.data = target.getNode("%s.d0" % basename)
+        self.control = target.getNode("%s.ctrl" % basename)
+        self.control_val = 0b0
+        self.divider = target.getNode("%s.divider" % basename)
+        self.slaveselect = target.getNode("%s.ss" % basename)
+        self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
+        self.divider_val = 0x7f
+        self.configured = False
+
+    def config(self):
+        "Configure SPI interace for communicating with ADCs."
+        self.divider_val = int(self.divider_val) % 0xffff
+        if verbose:
+            print "Configuring SPI core, divider = 0x%x" % self.divider_val
+        self.divider.write(self.divider_val)
+        self.target.dispatch()
+        self.control_val = 0x0
+        self.control_val |= 0x0 << 13 # Automatic slave select
+        self.control_val |= 0x0 << 12 # No interrupt
+        self.control_val |= 0x0 << 11 # MSB first
+        # ADC samples data on rising edge of SCK
+        self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
+        # ADC changes output shortly after falling edge of SCK
+        self.control_val |= 0x0 << 9 # read input on rising edge
+        self.control_val |= 0x10 # 16 bit transfers
+        if verbose:
+            print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
+        self.configured = True
+
+    def transmit(self, chip, value):
+        if not self.configured:
+            self.config()
+        assert chip >= 0 and chip < 8
+        value &= 0xffff
+        self.data.write(value)
+        checkdata = self.data.read()
+        self.target.dispatch()
+        assert checkdata == value
+        self.control.write(self.control_val)
+        self.slaveselect.write(0xff ^ (0x1 << chip))
+        self.target.dispatch()
+        self.control.write(self.control_val | SPICore.go_busy)
+        self.target.dispatch()
+        busy = True
+        while busy:
+            status = self.control.read()
+            self.target.dispatch()
+            busy = status & SPICore.go_busy > 0
+        self.slaveselect.write(0xff)
+        data = self.data.read()
+        ss = self.slaveselect.read()
+        status = self.control.read()
+        self.target.dispatch()
+        #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
+        return data
diff --git a/AIDA_tlu/legacy/packages/I2cBusProperties.py b/AIDA_tlu/legacy/packages/I2cBusProperties.py
new file mode 100644
index 0000000000000000000000000000000000000000..a23f30cd537987907774b0a11869026ec5feb96d
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/I2cBusProperties.py
@@ -0,0 +1,122 @@
+##########################################################
+#  I2cBusProperties - simple encapsulation of all items
+#                     required to control an I2C bus.
+#
+#  Carl Jeske, July 2010
+#  Refactored by Robert Frazier, May 2011
+##########################################################
+
+
+class I2cBusProperties(object):
+    """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
+
+    Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
+    value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
+    registers that define/control the bus (assuming these names are not the defaults specified
+    in the constructor below).  The seven registers consist of the two clock pre-scaling
+    registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
+    COMMAND and STATUS).
+
+    Usage:  You'll need to create an instance of this class to give to a concrete I2C bus instance, such
+            as OpenCoresI2cBus.  This I2cBusProperties class is simply a container to hold the properties
+            that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
+
+            Access the items stored by this class via these (deliberately compact) variable names:
+
+                chipsBus     -- the ChipsBus device hosting the I2C core
+                preHiVal     -- the top byte of the clock prescale value
+                preLoVal     -- the bottom byte of the clock prescale value
+                preHiReg     -- the register the top byte of the clk prescale value (preHiVal) gets written to
+                preLoReg     -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
+                ctrlReg      -- the I2C Control register
+                txReg        -- the I2C Transmit register
+                rxReg        -- the I2C Receive register
+                cmdReg       -- the I2C Command register
+                statusReg    -- the I2C Status register
+
+
+    Compatibility Notes: The seven register names are the registers typically required to operate an
+                         OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
+                         the same way as the OpenCores one). This software is not compatible with your
+                         I2C bus master if it doesn't use this register interface.
+    """
+
+    def __init__(self,
+                 chipsBusDevice,
+                 clkPrescaleU16,
+                 clkPrescaleLoByteReg = "i2c_pre_lo",
+                 clkPrescaleHiByteReg = "i2c_pre_hi",
+                 controlReg           = "i2c_ctrl",
+                 transmitReg          = "i2c_tx",
+                 receiveReg           = "i2c_rx",
+                 commandReg           = "i2c_cmd",
+                 statusReg            = "i2c_status"):
+
+        """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
+
+        chipsBusDevice:  Provide a ChipsBus instance to the device where the I2C bus is being
+                controlled. The address table for this device must contain the five registers
+                that control the bus, as declared next...
+
+        clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
+                master-clock.  This value gets split into two 8-bit values and ultimately will
+                get written to the two I2C clock-prescale registers as declared below.  See
+                the OpenCores or Lattice Semiconductor I2C documentation for more details.
+
+        clkPrescaleLoByteReg:  The register where the lower byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_lo".
+
+        clkPrescaleHiByteReg:  The register where the higher byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_hi"
+
+        controlReg:  The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
+                usually read and write accessible. The default name for this register is "i2c_ctrl".
+
+        transmitReg:  The TRANSMIT register, used for holding the data to be transmitted via I2C, etc.  This
+                typically shares the same address as the RECEIVE register, but has write-only access.  The default
+                name for this register is "i2c_tx".
+
+        receiveReg:  The RECEIVE register - allows access to the byte received over the I2C bus.  This
+                typically shares the same address as the TRANSMIT register, but has read-only access.  The
+                default name for this register is "i2c_rx".
+
+        commandReg:  The COMMAND register - stores the command for the next I2C operation.  This typically
+                shares the same address as the STATUS register, but has write-only access.  The default name for
+                this register is "i2c_cmd".
+
+        statusReg:  The STATUS register - allows monitoring of the I2C operations.  This typically shares
+                the same address as the COMMAND register, but has read-only access.  The default name for this
+                register is "i2c_status".
+        """
+
+        object.__init__(self)
+        self.chipsBus = chipsBusDevice
+        self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
+        self.preLoVal = (clkPrescaleU16 & 0xff)
+        
+        # Check to see all the registers are in the address table
+        registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
+        for reg in registers:
+            if not self.chipsBus.addrTable.checkItem(reg):
+                raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
+
+        # Check that the registers we'll need to write to are indeed writable
+        writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
+        for wReg in writableRegisters:
+            if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
+                raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
+
+        # Check that the registers we'll need to read from are indeed readable
+        readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
+        for rReg in readableRegisters:
+            if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
+                raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
+
+        # Store the various register name strings
+        self.preHiReg = clkPrescaleHiByteReg
+        self.preLoReg = clkPrescaleLoByteReg
+        self.ctrlReg = controlReg
+        self.txReg = transmitReg
+        self.rxReg = receiveReg
+        self.cmdReg = commandReg
+        self.statusReg = statusReg
diff --git a/AIDA_tlu/legacy/packages/PCA9539PW.py b/AIDA_tlu/legacy/packages/PCA9539PW.py
new file mode 100644
index 0000000000000000000000000000000000000000..723b0ad43ca312e9edd8f4d10b10eaff321cdc3c
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/PCA9539PW.py
@@ -0,0 +1,94 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class PCA9539PW:
+    #Class to configure the expander modules
+
+    def __init__(self, i2c, slaveaddr=0x74):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def writeReg(self, regN, regContent, verbose=False):
+        #Basic functionality to write to register.
+        if (regN < 0) | (regN > 7):
+            print "PCA9539PW - ERROR: register number should be in range [0:7]"
+            return
+        regContent= regContent & 0xFF
+        mystop=True
+        cmd= [regN, regContent]
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+
+    def readReg(self, regN, nwords, verbose=False):
+        #Basic functionality to read from register.
+        if (regN < 0) | (regN > 7):
+            print "PCA9539PW - ERROR: register number should be in range [0:7]"
+            return
+        mystop=False
+        self.i2c.write( self.slaveaddr, [regN], mystop)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+
+
+    def setInvertReg(self, regN, polarity= 0x00):
+        #Set the content of register 4 or 5 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        polarity = polarity & 0xFF
+        self.writeReg(regN+4, polarity)
+
+    def getInvertReg(self, regN):
+        #Read the content of register 4 or 5 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        res= self.readReg(regN+4, 1)
+        return res
+
+    def setIOReg(self, regN, direction= 0xFF):
+        #Set the content of register 6 or 7 which determine the direction of the
+        #ports (0= output, 1= input).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        direction = direction & 0xFF
+        self.writeReg(regN+6, direction)
+
+    def getIOReg(self, regN):
+        #Read the content of register 6 or 7 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        res= self.readReg(regN+6, 1)
+        return res
+
+    def getInputs(self, bank):
+        #Read the incoming values of the pins for one of the two 8-bit banks.
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        res= self.readReg(bank, 1)
+        return res
+
+    def setOutputs(self, bank, values= 0x00):
+        #Set the content of the output flip-flops.
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        values = values & 0xFF
+        self.writeReg(bank+2, values)
+
+    def getOutputs(self, bank):
+        #Read the state of the outputs (i.e. what value is being written to them)
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        res= self.readReg(bank+2, 1)
+        return res
diff --git a/AIDA_tlu/legacy/packages/RawI2cAccess.py b/AIDA_tlu/legacy/packages/RawI2cAccess.py
new file mode 100644
index 0000000000000000000000000000000000000000..284613299f372f0718001f996fa083befc68113b
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/RawI2cAccess.py
@@ -0,0 +1,261 @@
+# Created on Sep 10, 2012
+# @author: Kristian Harder, based on code by Carl Jeske
+
+from I2cBusProperties import I2cBusProperties
+from ChipsBus import ChipsBus
+from ChipsLog import chipsLog
+from ChipsException import ChipsException
+
+
+class RawI2cAccess:
+
+    def __init__(self, i2cBusProps, slaveAddr):
+
+        # For performing read/writes over an OpenCores-compatible I2C bus master
+        #
+        # An instance of this class is required to communicate with each
+        # I2C slave on the I2C bus.
+        #
+        # i2cBusProps: an instance of the class I2cBusProperties that contains
+        #    the relevant ChipsBus host and the I2C bus-master registers (if
+        #    they differ from the defaults specified by the I2cBusProperties
+        #    class).
+        #
+        #slaveAddr: The address of the I2C slave you wish to communicate with.
+        #
+
+        self._i2cProps = i2cBusProps   # The I2C Bus Properties
+        self._slaveAddr = 0x7f & slaveAddr  # 7-bit slave address
+
+
+    def resetI2cBus(self):
+
+        # Resets the I2C bus
+        #
+        # This function does the following:
+        #        1) Disables the I2C core
+        #        2) Sets the clock prescale registers
+        #        3) Enables the I2C core
+        #        4) Sets all writable bus-master registers to default values
+
+        try:
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
+            #self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
+            self._chipsBus().queueWrite(self._i2cProps.preHiReg,
+                                        self._i2cProps.preHiVal)
+            self._chipsBus().queueWrite(self._i2cProps.preLoReg,
+                                        self._i2cProps.preLoVal)
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
+            self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
+            self._chipsBus().queueRun()
+        except ChipsException, err:
+            raise ChipsException("I2C reset error:\n\t" + str(err))
+
+
+    def read(self, numBytes):
+
+        # Performs an I2C read. Returns the 8-bit read result(s).
+        #
+        # numBytes: number of bytes expected as response
+        #
+
+        try:
+            result = self._privateRead(numBytes)
+        except ChipsException, err:
+            raise ChipsException("I2C read error:\n\t" + str(err))
+        return result
+
+
+    def write(self, listDataU8):
+
+        # Performs an 8-bit I2C write.
+        #
+        # listDataU8:  The 8-bit data values to be written.
+        #
+
+        try:
+            self._privateWrite(listDataU8)
+        except ChipsException, err:
+            raise ChipsException("I2C write error:\n\t" + str(err))
+        return
+
+
+    def _chipsBus(self):
+
+        # Returns the instance of the ChipsBus device that's hosting
+        # the I2C bus master
+
+        return self._i2cProps.chipsBus
+
+
+    def _privateRead(self, numBytes):
+
+        # I2C read implementation.
+        #
+        #  Fast I2C read implementation,
+        # i.e. done with the fewest packets possible.
+
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        #        '1' = reading from slave
+        #        '0' = writing to slave
+
+        # command reg definitions
+        # bit 7:   Generate start condition
+        # bit 6:   Generate stop condition
+        # bit 5:   Read from slave
+        # bit 4:   Write to slave
+        # bit 3:   0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0:   Interrupt acknowledge. When set, clears a pending interrupt
+
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero
+        # (i.e. we're writing an address to the bus)
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) | 0x01)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        result=[]
+        for ibyte in range(numBytes):
+            if ibyte==numBytes-1:
+                stop_bit=0x40
+                ack_bit=0x08
+            else:
+                stop_bit=0
+                ack_bit=0
+                pass
+            # Set read bit, acknowledge and stop bit in command reg
+            self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
+            # Wait for transaction to finish.
+            # Don't expect an ACK, do expect bus free at finish.
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = False)
+                pass
+            result.append(self._chipsBus().read(self._i2cProps.rxReg))
+
+        return result
+
+
+    def _privateWrite(self, listDataU8):
+
+        # I2C write implementation.
+        #
+        #  Fast I2C write implementation,
+        # i.e. done with the fewest packets possible.
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        # '1' = reading from slave
+        # '0' = writing to slave
+
+        # command reg definitions
+        # bit 7: Generate start condition
+        # bit 6: Generate stop condition
+        # bit 5: Read from slave
+        # bit 4: Write to slave
+        # bit 3: 0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) & 0xfe)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        for ibyte in range(len(listDataU8)):
+            dataU8 = listDataU8[ibyte]
+            if ibyte==len(listDataU8)-1:
+                stop_bit=0x40
+            else:
+                stop_bit=0x00
+                pass
+            # Set data to be written in transmit reg
+            self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
+            # Set write and stop bit in command reg
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
+            # Run the queue
+            self._chipsBus().queueRun()
+            # Wait for transaction to finish.
+            # Do expect an ACK and do expect bus to be free at finish
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = False)
+                pass
+            pass
+
+        return
+
+
+    def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
+                              requireBusIdleAtEnd = False):
+
+        # Ensures the current bus transaction has finished successfully
+        # before allowing further I2C bus transactions
+
+        # This method monitors the status register
+        # and will not allow execution to continue until the
+        # I2C bus has completed properly.  It will throw an exception
+        # if it picks up bus problems or a bus timeout occurs.
+
+        maxRetry = 20
+        attempt = 1
+        while attempt <= maxRetry:
+
+            # Get the status
+            i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
+
+            receivedAcknowledge = not bool(i2c_status & 0x80)
+            busy = bool(i2c_status & 0x40)
+            arbitrationLost = bool(i2c_status & 0x20)
+            transferInProgress = bool(i2c_status & 0x02)
+            interruptFlag = bool(i2c_status & 0x01)
+
+            if arbitrationLost:  # This is an instant error at any time
+                raise ChipsException("I2C error: Arbitration lost!")
+
+            if not transferInProgress:
+                break  # The transfer looks to have completed successfully, pending further checks
+
+            attempt += 1
+
+        # At this point, we've either had too many retries, or the
+        # Transfer in Progress (TIP) bit went low.  If the TIP bit
+        # did go low, then we do a couple of other checks to see if
+        # the bus operated as expected:
+
+        if attempt > maxRetry:
+            raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
+
+        if requireAcknowledgement and not receivedAcknowledge:
+            raise ChipsException("I2C error: No acknowledge received!")
+
+        if requireBusIdleAtEnd and busy:
+            raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/AIDA_tlu/legacy/packages/TLU_v1e/output.csv b/AIDA_tlu/legacy/packages/TLU_v1e/output.csv
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/AIDA_tlu/legacy/packages/TLUaddrmap_BKP.xml b/AIDA_tlu/legacy/packages/TLUaddrmap_BKP.xml
new file mode 100644
index 0000000000000000000000000000000000000000..65fb5340f2155f8c5c92d96a2ef66d8dcb209d41
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/TLUaddrmap_BKP.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/legacy/packages/TLUconnection_BKP.xml b/AIDA_tlu/legacy/packages/TLUconnection_BKP.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fca67f50d932c760c77aa5553bfa983ca8fff249
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/TLUconnection_BKP.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="tlu" uri="ipbusudp-2.0://192.168.200.30:50001"
+   address_table="file://./TLUaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/legacy/packages/si5345.py b/AIDA_tlu/legacy/packages/si5345.py
new file mode 100644
index 0000000000000000000000000000000000000000..a1072df00203b62cf8db91231be3753b768506c0
--- /dev/null
+++ b/AIDA_tlu/legacy/packages/si5345.py
@@ -0,0 +1,140 @@
+import time
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+import csv
+
+class si5345:
+    #Class to configure the Si5344 clock generator
+
+    def __init__(self, i2c, slaveaddr=0x68):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+        #self.configList=
+
+    #def writeReg(self, address, data):
+
+    def readRegister(self, myaddr, nwords, verbose= False):
+        ### Read a specific register on the Si5344 chip. There is not check on the validity of the address but
+        ### the code sets the correct page before reading.
+
+        #First make sure we are on the correct page
+        currentPg= self.getPage()
+        requirePg= (myaddr & 0xFF00) >> 8
+        if verbose:
+            print "REG", hex(myaddr), "CURR PG" , hex(currentPg[0]), "REQ PG", hex(requirePg)
+        if currentPg[0] != requirePg:
+            self.setPage(requirePg)
+        #Now read from register.
+        addr=[]
+        addr.append(myaddr)
+        mystop=False
+        self.i2c.write( self.slaveaddr, addr, mystop)
+        # time.sleep(0.1)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+
+    def writeRegister(self, myaddr, data, verbose=False):
+        ### Write a specific register on the Si5344 chip. There is not check on the validity of the address but
+        ### the code sets the correct page before reading.
+        ### myaddr is an int
+        ### data is a list of ints
+
+        #First make sure we are on the correct page
+        myaddr= myaddr & 0xFFFF
+        currentPg= self.getPage()
+        requirePg= (myaddr & 0xFF00) >> 8
+        #print "REG", hex(myaddr), "CURR PG" , currentPg, "REQ PG", hex(requirePg)
+        if currentPg[0] != requirePg:
+            self.setPage(requirePg)
+        #Now write to register.
+        data.insert(0, myaddr)
+        if verbose:
+            print "  Writing: "
+            result="\t  "
+            for iaddr in data:
+                result+="%#02x "%(iaddr)
+            print result
+        self.i2c.write( self.slaveaddr, data)
+        #time.sleep(0.01)
+
+    def setPage(self, page, verbose=False):
+        #Configure the chip to perform operations on the specified address page.
+        mystop=True
+        myaddr= [0x01, page]
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        #time.sleep(0.01)
+        if verbose:
+            print "  Si5345 Set Reg Page:", page
+
+    def getPage(self, verbose=False):
+        #Read the current address page
+        mystop=False
+        myaddr= [0x01]
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        rPage= self.i2c.read( self.slaveaddr, 1)
+        #time.sleep(0.1)
+        if verbose:
+            print "\tPage read:", rPage
+        return rPage
+
+    def getDeviceVersion(self):
+        #Read registers containing chip information
+        mystop=False
+        nwords=2
+        myaddr= [0x02 ]#0xfa
+        self.setPage(0)
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        #time.sleep(0.1)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        print "  Si5345 EPROM: "
+        result="\t"
+        for iaddr in reversed(res):
+            result+="%#02x "%(iaddr)
+        print result
+        return res
+
+    def parse_clk(self, filename, verbose= False):
+        #Parse the configuration file produced by Clockbuilder Pro (Silicon Labs)
+    	deletedcomments=""""""
+        if verbose:
+    	       print "\tParsing file", filename
+    	with open(filename, 'rb') as configfile:
+    		for i, line in enumerate(configfile):
+    		    if not line.startswith('#') :
+    		      if not line.startswith('Address'):
+    			deletedcomments+=line
+    	csvfile = StringIO.StringIO(deletedcomments)
+    	cvr= csv.reader(csvfile, delimiter=',', quotechar='|')
+    	#print "\tN elements  parser:", sum(1 for row in cvr)
+    	#return [addr_list,data_list]
+        # for item in cvr:
+        #     print "rere"
+        #     regAddr= int(item[0], 16)
+        #     regData[0]= int(item[1], 16)
+        #     print "\t  ", hex(regAddr), hex(regData[0])
+        #self.configList= cvr
+        regSettingList= list(cvr)
+        if verbose:
+            print "\t  ", len(regSettingList), "elements"
+        return regSettingList
+
+    def writeConfiguration(self, regSettingList):
+        print "  Si5345 Writing configuration:"
+        #regSettingList= list(regSettingCsv)
+        counter=0
+        for item in regSettingList:
+            regAddr= int(item[0], 16)
+            regData=[0]
+            regData[0]= int(item[1], 16)
+            print "\t", counter, "Reg:", hex(regAddr), "Data:", regData
+            counter += 1
+            self.writeRegister(regAddr, regData, False)
+
+    def checkDesignID(self):
+        regAddr= 0x026B
+        res= self.readRegister(regAddr, 8)
+        result= "  Si5345 design Id:\n\t"
+        for iaddr in res:
+            result+=chr(iaddr)
+        print result
diff --git a/AIDA_tlu/projects/TLU_v1e/addr_table/TLUaddrmap.xml b/AIDA_tlu/projects/TLU_v1e/addr_table/TLUaddrmap.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e9a79500fe0ed58b37fa4aaeee2214fee772772d
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/addr_table/TLUaddrmap.xml
@@ -0,0 +1,111 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers" fwinfo="endpoint;width=4">
+  <node id="DUTMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4">
+  <node id="ControlRW"               address="0x0" permission="rw" description="Bit-0 controls if shutter pulses are active. 1 = active"/>
+  <node id="ShutterSelectRW"         address="0x1" permission="rw" description="Selects which input is used to trigger shutter"/>
+  <node id="InternalShutterPeriodRW" address="0x2" permission="rw" description="Internal trig generator period ( units = number of strobe pulses)"/>
+  <node id="ShutterOnTimeRW"         address="0x3" permission="rw" description="Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)"/>
+  <node id="ShutterVetoOffTimeRW"         address="0x4" permission="rw" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
+  <node id="ShutterOffTimeRW"         address="0x5" permission="rw" description="time between input trigger and time at which shutter de-asserted and veto reasserted(T3) ( units = number of strobe pulses)"/>  
+  <node id="RunActiveRW"                address="0x6" permission="rw" description="Writing '1' to Bit-0 of this register raises the run_active line and causes sync line to pulse for one strobe-pulse interval"/>
+</node>
+
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer" fwinfo="endpoint;width=2">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration" fwinfo="endpoint;width=3">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration" fwinfo="endpoint;width=4">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration" fwinfo="endpoint;width=4">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration" fwinfo="endpoint;width=2">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r" fwinfo="endpoint;width=0">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep
new file mode 100644
index 0000000000000000000000000000000000000000..d65f77c759595580d133820fab5514dad97cbc61
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep
@@ -0,0 +1,19 @@
+@device_family = "artix7"
+@device_name = "xc7a35t"
+@device_package = "csg324"
+@device_speed = "-2"
+@boardname = "enclustra_ax3_pm3"
+
+setup settings_v7.tcl
+include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
+src -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth --cd ../ucf enclustra_ax3_pm3.tcl
+
+#
+src top_enclustra_tlu_v1e.vhd
+# src --cd ../ucf enclustra_ax3_pm3.tcl
+src --cd ../ucf I2C_constr.xdc
+src --cd ../ucf TLU_enclustra_v1e.xdc
+
+#include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep
+
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep
new file mode 100644
index 0000000000000000000000000000000000000000..188aaf404248fdd7db4104dd29430f647674f1ef
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep
@@ -0,0 +1,12 @@
+@device_family = "artix7"
+@device_name = "xc7a50t"
+@device_package = "csg324"
+@device_speed = "-2"
+@boardname = "enclustra_ax3_pm3"
+
+setup settings_v7.tcl
+# src top_enclustra_ax3_pm3.vhd
+include -c boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
+src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
+src -c components/pdts --cd ../ucf pc053_ax3_pm3.tcl
+src -c boards/enclustra_ax3_pm3/base_fw/synth --cd ../ucf enclustra_ax3_pm3.tcl
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3513a7057a5b4f2a97c220ec31b8bcd0f625a0be
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/set_top.tcl
@@ -0,0 +1,2 @@
+set_property top top_tlu_v1e [current_fileset]
+exit
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/settings_v7.tcl b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/settings_v7.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c4ddcf2915f6a754cbc6dfebc59c9d6091d3689b
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/settings_v7.tcl
@@ -0,0 +1,5 @@
+set obj [get_projects top]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "source_mgmt_mode" "DisplayOnly" $obj
+set_property "target_language" "VHDL" $obj
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/tlu_1e.dep b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
new file mode 100644
index 0000000000000000000000000000000000000000..4b212e4c26abd397840b1922b2824cf321cc1e95
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
@@ -0,0 +1,60 @@
+# Entity payload is in tlu_1e.vhd
+# src tlu_1e.vhd
+
+addrtab -t TLUaddrmap.xml
+
+src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
+src -c ipbus-firmware:components/ipbus_slaves ipbus_syncreg_v.vhd
+src -c ipbus-firmware:components/ipbus_slaves syncreg_w.vhd
+src -c ipbus-firmware:components/ipbus_slaves syncreg_r.vhd
+src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
+
+src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
+
+src -c components/tlu fmcTLU_pkg.vhd
+src -c components/tlu fmcTLU_pkg_body.vhd
+
+src -c components/tlu eventBuffer_rtl.vhd
+src -c components/tlu logic_clocks_rtl.vhd
+src -c components/tlu trigger/triggerInputs_newTLU_rtl.vhd
+src -c components/tlu eventFormatter_rtl.vhd
+src -c components/tlu T0_Shutter_Iface_rtl.vhd
+src -c components/tlu SyncGenerator_rtl.vhd
+src -c components/tlu counterWithResetPreset_rtl.vhd
+src -c components/tlu counterDownGated_rtl.vhd
+src -c components/tlu delayPulse4x_rtl.vhd
+src -c components/tlu stretchPulse4x_rtl.vhd
+
+src -c components/tlu dut/DUTInterfaces_rtl.vhd
+src -c components/tlu dut/DUTInterface_AIDA_rtl.vhd
+src -c components/tlu dut/DUTInterface_EUDET_rtl.vhd
+src -c components/tlu trigger/triggerLogic_rtl.vhd
+
+src -c components/tlu synchronizeRegisters_rtl.vhd
+src -c components/tlu trigger/arrivalTimeLUT_rtl.vhd
+src -c components/tlu counterWithReset_rtl.vhd
+src -c components/tlu trigger/dualSERDES_1to4_rtl.vhd
+src -c components/tlu trigger/IODELAYCal_FSM_rtl.vhd
+src -c components/tlu pulseClockDomainCrossing_rtl.vhd
+src -c components/tlu single_pulse_rtl.vhd
+src -c components/tlu stretchPulse_rtl.vhd
+src -c components/tlu coincidenceLogic_rtl.vhd
+
+# IPBus address map generated from XML file
+src -c projects/TLU_v1e ipbus_decode_TLUaddrmap.vhd
+
+
+# Include I2C components
+src -c components/external/opencores_i2c i2c_master_top.vhd 
+src -c components/external/opencores_i2c i2c_master_bit_ctrl.vhd
+src -c components/external/opencores_i2c i2c_master_byte_ctrl.vhd
+src -c components/external/opencores_i2c i2c_master_registers.vhd
+src -c components/external/opencores_i2c i2c_master_rtl.vhd
+
+# Inclide IP ( *.xci files )
+src -c components/tlu --cd ../cgn tlu_event_fifo.xci
+src -c components/tlu --cd ../cgn internalTriggerGenerator.xci
+
+
+
+
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep
new file mode 100644
index 0000000000000000000000000000000000000000..612b72c2eb1b4ab79e914b04fc370c8aa47d7c4b
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep
@@ -0,0 +1,2 @@
+include enclustra_ax3_pm3_a35.dep
+include tlu_1e.dep
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a50.dep b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a50.dep
new file mode 100644
index 0000000000000000000000000000000000000000..25b08f2383c343300077369cc138ccee3948f5ff
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a50.dep
@@ -0,0 +1,2 @@
+include -c projects/master enclustra_ax3_pm3_a50.dep
+include master.dep
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd b/AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b2f81e4b11827f9e7e7c4cc13f1996aebfec4104
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
@@ -0,0 +1,774 @@
+-- Top-level design for TLU v1E
+--
+-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+-- Modified by merging IPBus Emclustra template written by Dave Newbold, 4/10/16--
+-- and AIDA miniTLU code 
+-- Paolo Baesso 2017
+
+library IEEE;
+library UNISIM;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.fmcTLU.all;
+use work.ipbus_decode_TLUaddrmap.all;
+use work.ipbus.all;
+use work.ipbus_reg_types.all;
+use UNISIM.vcomponents.all;
+
+--Library UNISIM;
+--use UNISIM.vcomponents.all;
+
+use work.ipbus.ALL;
+
+entity top is
+    generic(
+    constant FW_VERSION : unsigned(31 downto 0):= X"1e000014"; -- Firmware revision. Remember to change this as needed.
+    g_NUM_DUTS  : positive := 4; -- <- was 3
+    g_NUM_TRIG_INPUTS   :positive := 6;-- <- was 4
+    g_NUM_EDGE_INPUTS   :positive := 6;--  <-- was 4
+    g_NUM_EXT_SLAVES    :positive :=8;--  <-- ??
+    g_EVENT_DATA_WIDTH  :positive := 64;--  <-- ??
+    g_IPBUS_WIDTH   :positive := 32;--  <-- was 32 
+    g_SPILL_COUNTER_WIDTH   :positive := 12;--  <-- ??
+    g_BUILD_SIMULATED_MAC   :integer := 0
+    );
+    port(
+    --Clock
+        sysclk: in std_logic; --50 MHz clock input from FPGA
+        --clk_enclustra: in std_logic; --Enclustra onboard oscillator 50 MHz. Used for the IPBus block
+        sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
+        sysclk_40_i_p: in std_logic;
+        sysclk_40_i_n: in std_logic;
+    --Misc
+        leds: out std_logic_vector(3 downto 0); -- status LEDs
+        --dip_sw: in std_logic_vector(3 downto 0); -- switches
+        --cfg: in std_logic_vector(3 downto 0); -- switches
+        gpio: out std_logic; -- gpio pin on J1 (eventually make it inout)
+    --RGMII interface signals
+        rgmii_txd: out std_logic_vector(3 downto 0);
+        rgmii_tx_ctl: out std_logic;
+        rgmii_txc: out std_logic;
+        rgmii_rxd: in std_logic_vector(3 downto 0);
+        rgmii_rx_ctl: in std_logic;
+        rgmii_rxc: in std_logic;
+        phy_rstn: out std_logic; 
+    --I2C bus
+        i2c_scl_b: inout std_logic;
+        i2c_sda_b: inout std_logic;
+        i2c_reset: out std_logic; --Reset line for the expander serial lines
+    --Clock generator controls
+        clk_gen_rst: out std_logic; --Reset line for the Si5345 clock generator (active low)
+        --clk_gen_lol: in std_logic; --LOL signal. Do not use for now as it is connected to CONT_FROM_FPGA<0>
+    --TLU signals for DUTs
+        busy_i: in std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines from DUTs (active high) (busy to FPGA)
+        busy_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);-- Busy lines to DUTs (active high) (busy from FPGA)
+        cont_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines from DUTs
+        cont_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Control lines to DUTs
+        spare_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines from DUTs
+        spare_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Spare lines to DUTs
+        triggers_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines from DUTs
+        triggers_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Trigger lines to DUTs
+        dut_clk_i: in std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock from DUTs
+        dut_clk_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Clock to DUTs
+        
+        --reset_or_clk_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --T0 synchronization signal
+        --reset_or_clk_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+        --shutter_to_dut_n_o: out std_logic_vector(g_NUM_DUTS-1 downto 0); --Shutter output
+        --shutter_to_dut_p_o: out std_logic_vector(g_NUM_DUTS-1 downto 0);
+                
+     --TLU trigger inputs   
+        threshold_discr_n_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0);
+        threshold_discr_p_i: in std_logic_vector(g_NUM_TRIG_INPUTS-1 downto 0)
+        --gpio_hdr: out std_logic_vector(3 downto 0);
+        --extclk_n_b: inout std_logic; --External clock in or clock output
+        --extclk_p_b: inout std_logic
+    );
+
+end top;
+
+architecture rtl of top is
+
+	signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, clk_200, sysclk_40, clk_encl_buf, userled: std_logic;
+	signal mac_addr: std_logic_vector(47 downto 0);
+	signal ip_addr: std_logic_vector(31 downto 0);
+	signal ipb_out: ipb_wbus;
+	signal ipb_in: ipb_rbus;
+	signal inf_leds: std_logic_vector(1 downto 0);
+	signal s_i2c_scl_enb         : std_logic;
+    signal s_i2c_sda_enb         : std_logic;
+    signal encl_clock50: std_logic; -- This is a 50 MHz clock generated from the Enclustra onboard oscillator (rather than the clock input)
+    
+	--signal s_i2c_sda_i : std_logic;
+	--signal s_i2c_scl_i : std_logic;
+	------------------------------------------
+	-- Internal signal declarations
+    SIGNAL s_T0                  : std_logic;
+    SIGNAL buffer_full_o         : std_logic;                                             --! Goes high when event buffer almost full
+    SIGNAL clk_8x_logic         : std_logic;                                             -- 320MHz clock
+    SIGNAL clk_4x_logic          : std_logic;                                             --! normally 160MHz
+    SIGNAL clk_logic_xtal        : std_logic;                                             -- ! 40MHz clock from onboard xtal
+    SIGNAL data_strobe           : std_logic;                                             -- goes high when data ready to load into event buffer
+    SIGNAL dout                  : std_logic;
+    SIGNAL dout1                 : std_logic;
+    SIGNAL event_data            : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+    signal ipbww: ipb_wbus_array(N_SLAVES - 1 downto 0);
+    signal ipbrr: ipb_rbus_array(N_SLAVES - 1 downto 0);
+    SIGNAL logic_clocks_reset    : std_logic;                                             -- Goes high to reset counters etc. Sync with clk_4x_logic
+    SIGNAL logic_reset           : std_logic;
+    SIGNAL overall_trigger       : std_logic;                                             --! goes high to load trigger data
+    SIGNAL overall_veto          : std_logic;                                             --! Halts triggers when high
+    SIGNAL postVetoTrigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      -- ! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL postVetotrigger       : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        -- ! High when trigger from input connector active and enabled
+    --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+    SIGNAL rst_fifo_o            : std_logic;                                             --! rst signal to first level fifos
+    SIGNAL s_edge_fall_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_falling        : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when falling edge
+    SIGNAL s_edge_rise_times     : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0);      -- Array of edge times ( w.r.t. logic_strobe)
+    SIGNAL s_edge_rising         : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0);        -- ! High when rising edge
+    --SIGNAL s_i2c_scl_enb         : std_logic;
+    --SIGNAL s_i2c_sda_enb         : std_logic;
+    SIGNAL s_shutter             : std_logic;                                             --! shutter signal from TimePix, retimed onto local clock
+    signal s_run_active          : std_logic;    --! Goes high when run is active.
+    SIGNAL s_triggerLogic_reset  : std_logic;
+    SIGNAL shutter_cnt_i         : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL shutter_i             : std_logic;
+    SIGNAL spill_cnt_i           : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+    SIGNAL spill_i               : std_logic;
+    SIGNAL strobe_8x_logic      : std_logic;                                             --! Pulses one cycle every 4 of 16x clock.
+    SIGNAL strobe_4x_logic       : std_logic;                                             -- one pulse every 4 cycles of clk_4x
+    SIGNAL trigger_count         : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+    SIGNAL trigger_times         : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+    SIGNAL triggers              : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);        --! Rising edge of trigger inputs
+    SIGNAL s_veto                : std_logic;                                             --! goes high when one or more DUT are busy
+    signal s_shutter_veto        : std_logic;  --! Goes high when triggers should be vetoed by shutter
+	signal ctrl, stat: ipb_reg_v(0 downto 0);
+	--My signals
+	--SIGNAL busy_toggle_o         : std_logic_vector(g_NUM_DUTS-1 downto 0);
+	
+----------------------------------------------
+----------------------------------------------
+    component DUTInterfaces
+    generic(
+	   g_NUM_DUTS : positive := 4;-- <- was 3
+	   g_IPBUS_WIDTH : positive := 32
+	   );
+    port (
+        clk_4x_logic_i          : IN     std_logic ;
+        strobe_4x_logic_i       : IN     std_logic ;                                  --! goes high every 4th clock cycle
+        trigger_counter_i       : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Number of trigger events since last reset
+        trigger_i               : IN     std_logic ;                                  --! goes high when trigger logic issues a trigger
+        reset_or_clk_to_dut_i   : IN     std_logic ;                                  --! Synchronization signal. Passed TO DUT pins
+        shutter_to_dut_i        : IN     std_logic ;                                  --! Goes high TO indicate data-taking active. DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+        shutter_veto_i          : IN     std_logic;                                    --! WHen high DUTs report busy unless ignoreShutterVeto IPBus flag is set high
+        -- IPBus signals.
+        ipbus_clk_i             : IN     std_logic ;
+        ipbus_i                 : IN     ipb_wbus ;                                   --! Signals from IPBus core TO slave
+        ipbus_reset_i           : IN     std_logic ;
+        ipbus_o                 : OUT    ipb_rbus ;                                   --! signals from slave TO IPBus core
+        -- Signals to/from DUT
+        busy_from_dut       : IN     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);    --! BUSY input from DUTs
+        busy_to_dut       : OUT     std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! BUSY input to DUTs (single ended)
+        clk_from_dut  : IN std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        clk_to_dut : OUT std_logic_vector(g_NUM_DUTS-1 DOWNTO 0); --new signal for TLU, replace differential I/O
+        reset_to_dut: OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Replaces reset_or_clk_to_dut
+        trigger_to_dut : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Trigger output
+        shutter_to_dut      : OUT    std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);     --! Shutter output
+        veto_o                  : OUT    std_logic   
+    );
+    end component DUTInterfaces;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT T0_Shutter_Iface
+      generic (
+        g_NUM_ACCELERATOR_SIGNALS: positive := 6
+        );
+    PORT (
+        clk_4x_i      : IN     std_logic;
+        clk_4x_strobe_i : IN     std_logic;
+        ipbus_clk_i   : IN     std_logic;
+        ipbus_i       : IN     ipb_wbus;
+        T0_o          : OUT    std_logic;
+        run_active_o  : out    std_logic;
+        accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 DOWNTO 0);  
+        ipbus_o       : OUT    ipb_rbus;
+        shutter_veto_o: out    std_logic;
+        shutter_o     : OUT    std_logic
+    );
+    END COMPONENT T0_Shutter_Iface;
+----------------------------------------------
+----------------------------------------------
+
+   COMPONENT eventBuffer
+   GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_READ_COUNTER_WIDTH : positive := 16
+   );
+   PORT (
+        clk_4x_logic_i    : IN     std_logic ;
+        data_strobe_i     : IN     std_logic ;                                     -- Indicates data TO transfer
+        event_data_i      : IN     std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        ipbus_clk_i       : IN     std_logic ;
+        ipbus_i           : IN     ipb_wbus ;
+        ipbus_reset_i     : IN     std_logic ;
+        strobe_4x_logic_i : IN     std_logic ;
+        --trigger_count_i   : IN     std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+        rst_fifo_o        : OUT    std_logic ;                                     --! rst signal TO first level fifos
+        buffer_full_o     : OUT    std_logic ;                                     --! Goes high when event buffer almost full
+        ipbus_o           : OUT    ipb_rbus ;
+        logic_reset_i     : IN     std_logic                                       -- reset buffers when high. Synch withclk_4x_logic
+   );
+   END COMPONENT eventBuffer;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT eventFormatter
+    GENERIC (
+        g_EVENT_DATA_WIDTH   : positive := 64;
+        g_IPBUS_WIDTH        : positive := 32;
+        g_COUNTER_TRIG_WIDTH : positive := 32;
+        g_COUNTER_WIDTH      : positive := 12;
+        g_EVTTYPE_WIDTH      : positive := 4;      --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    : positive := 4;      --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    : positive := 6       --! Number of trigger inputs (POSSIBLY WRONG!)
+    );
+    PORT (
+        clk_4x_logic_i         : IN     std_logic ;                                         --! Rising edge active
+        ipbus_clk_i            : IN     std_logic ;
+        logic_strobe_i         : IN     std_logic ;                                         --! Pulses high once every 4 cycles of clk_4x_logic
+        logic_reset_i          : IN     std_logic ;                                         --! goes high TO reset counters. Synchronous with clk_4x_logic
+        rst_fifo_i             : IN     std_logic ;                                         --! Goes high TO reset FIFOs
+        buffer_full_i          : IN     std_logic ;                                         --! Goes high when output fifo full
+        trigger_i              : IN     std_logic ;                                         --! goes high TO load trigger data. One cycle of clk_4x_logic
+        trigger_times_i        : IN     t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0);  --! Array of trigger times ( w.r.t. logic_strobe)
+        trigger_inputs_fired_i : IN     std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);    --! high for each input that "fired"
+        trigger_cnt_i          : IN     std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0); --! Trigger count
+        shutter_i              : IN     std_logic ;
+        shutter_cnt_i          : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        spill_i                : IN     std_logic ;
+        spill_cnt_i            : IN     std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+        edge_rise_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when rising edge
+        edge_fall_i            : IN     std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0);    --! High when falling edge
+        edge_rise_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        edge_fall_time_i       : IN     t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0);  --! Array of edge times ( w.r.t. logic_strobe)
+        ipbus_i                : IN     ipb_wbus ;
+        ipbus_o                : OUT    ipb_rbus ;
+        data_strobe_o          : OUT    std_logic ;                                         --! goes high when data ready TO load into event buffer
+        event_data_o           : OUT    std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+        reset_timestamp_i      : IN     std_logic ;                                         --! Taking high causes timestamp TO be reset. Combined with internal timestmap reset and written to reset_timestamp_o
+        reset_timestamp_o      : OUT    std_logic                                           --! Goes high for one clock cycle of clk_4x_logic when timestamp reset
+    );
+    END COMPONENT eventFormatter;   
+----------------------------------------------
+----------------------------------------------
+    COMPONENT logic_clocks
+    GENERIC (
+        g_USE_EXTERNAL_CLK : integer := 1
+    );
+    PORT (
+        ipbus_clk_i           : IN     std_logic ;
+        ipbus_i               : IN     ipb_wbus ;
+        ipbus_reset_i         : IN     std_logic ;
+        Reset_i               : IN     std_logic ;
+        clk_logic_xtal_i      : IN     std_logic ; -- ! 40MHz clock from onboard xtal
+        clk_8x_logic_o       : OUT    std_logic ; -- 640MHz clock
+        clk_4x_logic_o        : OUT    std_logic ; -- 160MHz clock
+        ipbus_o               : OUT    ipb_rbus ;
+        strobe_8x_logic_o    : OUT    std_logic ; -- strobes once every 4 cycles of clk_16x
+        strobe_4x_logic_o     : OUT    std_logic ; -- one pulse every 4 cycles of clk_4x
+        --extclk_p_b            : INOUT  std_logic ; -- either external clock in, or a clock being driven out
+        --extclk_n_b            : INOUT  std_logic ;
+        DUT_clk_o             : OUT    std_logic ;
+        logic_clocks_locked_o : OUT    std_logic ;
+        logic_reset_o         : OUT    std_logic   -- Goes high TO reset counters etc. Sync with clk_4x_logic
+    );
+    END COMPONENT logic_clocks;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerInputs_newTLU
+    GENERIC (
+        g_NUM_INPUTS  : natural  := 1;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        --cfd_discr_p_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Inputs from constant-fraction discriminators
+        --cfd_discr_n_i        : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! Input from CFD
+        clk_4x_logic         : IN     std_logic ;                                        --! Rising edge active. By default = 4*40MHz = 160MHz
+        clk_200_i : IN     std_logic ;
+        strobe_4x_logic_i    : IN     std_logic ;                                        --! Pulses high once every 4 cycles of clk_4x_logic
+        threshold_discr_p_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        threshold_discr_n_i  : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! inputs from threshold comparators
+        reset_i              : IN     std_logic ;
+        trigger_times_o      : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! trigger arrival time ( w.r.t. logic_strobe)
+        trigger_o            : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+        --trigger_debug_o      : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+        edge_rising_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_falling_times_o : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);      --! edge arrival time ( w.r.t. logic_strobe)
+        edge_rising_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when rising edge. Syncronous with clk_4x_logic_i
+        edge_falling_o       : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);        --! High when falling edge
+        ipbus_clk_i          : IN     std_logic ;
+        ipbus_reset_i        : IN     std_logic ;
+        ipbus_i              : IN     ipb_wbus ;                                         --! Signals from IPBus core TO slave
+        ipbus_o              : OUT    ipb_rbus ;                                         --! signals from slave TO IPBus core
+        clk_8x_logic_i      : IN     std_logic ;                                        --! 640MHz clock ( 16x 40MHz )
+        strobe_8x_logic_i   : IN     std_logic                                          --! Pulses one cycle every 4 of 8x clock.
+    );
+    END COMPONENT triggerInputs_newTLU;
+----------------------------------------------
+----------------------------------------------
+    COMPONENT triggerLogic
+    GENERIC (
+        g_NUM_INPUTS  : positive := 4;
+        g_IPBUS_WIDTH : positive := 32
+    );
+    PORT (
+        clk_4x_logic_i      : IN     std_logic ;                                   -- ! Rising edge active
+        ipbus_clk_i         : IN     std_logic ;
+        ipbus_i             : IN     ipb_wbus ;                                    -- Signals from IPBus core TO slave
+        ipbus_reset_i       : IN     std_logic ;
+        logic_reset_i       : IN     std_logic ;                                   -- active high. Synchronous with clk_4x_logic
+        logic_strobe_i      : IN     std_logic ;                                   -- ! Pulses high once every 4 cycles of clk_4x_logic
+        trigger_i           : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active
+        trigger_times_i     : IN     t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        veto_i              : IN     std_logic ;                                   -- ! Halts triggers when high
+        trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);   -- ! High when trigger from input connector active and enabled
+        trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+        event_number_o      : OUT    std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);  -- starts at one. Increments for each post_veto_trigger
+        ipbus_o             : OUT    ipb_rbus ;                                    -- signals from slave TO IPBus core
+        post_veto_trigger_o : OUT    std_logic ;                                   -- ! goes high when trigger passes
+        pre_veto_trigger_o  : OUT    std_logic ;
+        trigger_active_o    : OUT    std_logic                                     --! Goes high when triggers are active ( ie. not veoted)
+    );
+    END COMPONENT triggerLogic;
+    
+    COMPONENT i2c_master
+        PORT (
+           i2c_scl_i     : IN     std_logic;
+           i2c_sda_i     : IN     std_logic;
+           ipbus_clk_i   : IN     std_logic;
+           ipbus_i       : IN     ipb_wbus;
+           ipbus_reset_i : IN     std_logic;
+           i2c_scl_enb_o : OUT    std_logic;
+           i2c_sda_enb_o : OUT    std_logic;
+           ipbus_o       : OUT    ipb_rbus
+    );
+    END COMPONENT i2c_master;
+    
+    component clk_wiz_0
+    port
+     (-- Clock in ports
+      clk_in1           : in     std_logic;
+      -- Clock out ports
+      clk_out1          : out    std_logic;
+      -- Status and control signals
+      reset             : in     std_logic;
+      locked            : out    std_logic
+     );
+    end component;
+    
+
+    -- Optional embedded configurations
+    -- pragma synthesis_off
+    FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+    --FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+    FOR ALL : T0_Shutter_Iface USE ENTITY work.T0_Shutter_Iface;
+    FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+    FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+    FOR ALL : i2c_master USE ENTITY work.i2c_master;--<P
+    FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+    FOR ALL : triggerInputs_newTLU USE ENTITY work.triggerInputs_newTLU;
+    FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+    -- pragma synthesis_on 
+      	
+begin
+    
+--led_iic_test <= iic_test;
+
+--Implicit instantiation of output tristate buffers.
+    i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+    i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+    
+    
+    -- Infrastructure
+    -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+    logic_clocks_reset <= '0';
+    -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+    spill_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+    spill_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+    shutter_i <= '0';
+    -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+    shutter_cnt_i <= (OTHERS => '0');
+    -- ModuleWare code(v1.12) for instance 'I17' of 'gnd'
+    dout1 <= '0';
+    -- ModuleWare code(v1.12) for instance 'I18' of 'gnd'
+    dout <= '0';
+    -- ModuleWare code(v1.12) for instance 'I19' of 'merge'
+    --gpio_hdr <= dout1 & dout & s_shutter & T0_o;
+    -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+    overall_veto <= buffer_full_o OR s_veto or s_shutter_veto when rising_edge(clk_4x_logic);
+    -- ModuleWare code(v1.12) for instance 'I16' of 'sor'
+    s_triggerLogic_reset <= logic_reset OR s_T0;
+
+    i2c_reset <= '1';
+    clk_gen_rst <= '1';
+    ---gpio <= strobe_8x_logic;---
+    gpio <= s_veto;---
+    --gpio <= busy_i(1);---
+    
+    --Set diff clock out to 0 because we cannot have the correct differential voltage output
+    sysclk_50_o_p <= '0';
+    sysclk_50_o_n <= '0';
+    --Set busy_o to 0 for now
+    busy_o <= std_logic_vector(to_unsigned(0,    busy_o'length));
+    --sysclk_40_o_p <= sysclk;
+
+------------------------------------------
+	infra: entity work.enclustra_ax3_pm3_infra
+		port map(
+			sysclk => clk_encl_buf,
+			clk_ipb_o => clk_ipb,
+			rst_ipb_o => rst_ipb,
+			rst125_o => phy_rst_e,
+			clk_200_o => clk_200,
+			nuke => nuke,
+			soft_rst => soft_rst,
+			leds => inf_leds,
+			rgmii_txd => rgmii_txd,
+			rgmii_tx_ctl => rgmii_tx_ctl,
+			rgmii_txc => rgmii_txc,
+			rgmii_rxd => rgmii_rxd,
+			rgmii_rx_ctl => rgmii_rx_ctl,
+			rgmii_rxc => rgmii_rxc,
+			mac_addr => mac_addr,
+			ip_addr => ip_addr,
+			ipb_in => ipb_in,
+			ipb_out => ipb_out
+		);
+		
+	--leds <= not ('0' & userled & inf_leds); -- Check this.
+	phy_rstn <= not phy_rst_e;
+		
+--	mac_addr <= X"020ddba1151" & cfg; -- Careful here, arbitrary addresses do not always work
+--	ip_addr <= X"c0a8c81" & cfg; -- 192.168.200.16+n
+	mac_addr <= X"020ddba1151e"; -- Careful here, arbitrary addresses do not always work
+	ip_addr <= X"c0a8c81e"; -- 192.168.200.16+n
+
+------------------------------------------
+    I1 : entity work.ipbus_ctrlreg_v
+    port map(
+        clk => clk_ipb,
+        reset => rst_ipb,
+        ipbus_in => ipbww(N_SLV_VERSION),
+        ipbus_out => ipbrr(N_SLV_VERSION),
+        d => stat,
+        q => ctrl
+    );
+    stat(0) <= std_logic_vector(FW_VERSION);-- <-Let's use this as firmware revision number
+    soft_rst <= ctrl(0)(0);
+    nuke <= ctrl(0)(1);
+    
+------------------------------------------
+	I2 : entity work.ipbus_fabric_sel
+    generic map(
+    	NSLV => N_SLAVES,
+    	SEL_WIDTH => IPBUS_SEL_WIDTH)
+    port map(
+      ipb_in => ipb_out,
+      ipb_out => ipb_in,
+      sel => ipbus_sel_TLUaddrmap(ipb_out.ipb_addr),
+      ipb_to_slaves => ipbww,
+      ipb_from_slaves => ipbrr
+    );
+
+------------------------------------------
+    I3 : i2c_master
+    PORT MAP (
+        i2c_scl_i     => i2c_scl_b,
+        i2c_sda_i     => i2c_sda_b,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_I2C_MASTER),
+        ipbus_reset_i => rst_ipb,
+        i2c_scl_enb_o => s_i2c_scl_enb,
+        i2c_sda_enb_o => s_i2c_sda_enb,
+        ipbus_o       => ipbrr(N_SLV_I2C_MASTER)
+    );
+    
+----------------------------------------------
+    I4 : logic_clocks
+    GENERIC MAP (
+        g_USE_EXTERNAL_CLK => 0
+    )
+    PORT MAP (
+        ipbus_clk_i           => clk_ipb,
+        ipbus_i               => ipbww(N_SLV_LOGIC_CLOCKS),
+        ipbus_reset_i         => rst_ipb,
+        Reset_i               => logic_clocks_reset,
+        clk_logic_xtal_i      => sysclk_40, -- Not sure this is correct
+        clk_8x_logic_o       => clk_8x_logic,
+        clk_4x_logic_o        => clk_4x_logic,
+        ipbus_o               => ipbrr(N_SLV_LOGIC_CLOCKS),
+        strobe_8x_logic_o    => strobe_8x_logic,
+        strobe_4x_logic_o     => strobe_4x_logic,
+        DUT_clk_o             => open,
+        logic_clocks_locked_o => leds(3),
+        logic_reset_o         => logic_reset
+    );    
+
+----------------------------------------------
+    I5 : triggerInputs_newTLU 
+    GENERIC MAP (
+        g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+        g_IPBUS_WIDTH => 32
+    )
+    PORT MAP (
+        clk_4x_logic         => clk_4x_logic,
+        clk_200_i => clk_200,
+        strobe_4x_logic_i    => strobe_4x_logic,
+        threshold_discr_p_i  => threshold_discr_p_i,
+        threshold_discr_n_i  => threshold_discr_n_i,
+        reset_i              => logic_reset,
+        trigger_times_o      => trigger_times,
+        trigger_o            => triggers,
+        --trigger_debug_o      => OPEN,
+        edge_rising_times_o  => s_edge_rise_times,
+        edge_falling_times_o => s_edge_fall_times,
+        edge_rising_o        => s_edge_rising,
+        edge_falling_o       => s_edge_falling,
+        ipbus_clk_i          => clk_ipb,
+        ipbus_reset_i        => rst_ipb,
+        ipbus_i              => ipbww(N_SLV_TRIGGERINPUTS),
+        ipbus_o              => ipbrr(N_SLV_TRIGGERINPUTS),
+        clk_8x_logic_i      => clk_8x_logic,
+        strobe_8x_logic_i   => strobe_8x_logic
+    );
+
+------------------------------------------      
+    I6 : eventFormatter
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+        g_COUNTER_WIDTH      => 12,
+        g_EVTTYPE_WIDTH      => 4,                         --! Width of the event type word
+        --g_NUM_INPUT_TYPES     : positive := 4;               -- Number of different input types (trigger, shutter, edge...)
+        g_NUM_EDGE_INPUTS    => g_NUM_EDGE_INPUTS,         --! Number of edge inputs
+        g_NUM_TRIG_INPUTS    => g_NUM_TRIG_INPUTS          --! Number of trigger inputs
+    )
+    PORT MAP (
+        clk_4x_logic_i         => clk_4x_logic,
+        ipbus_clk_i            => clk_ipb,
+        logic_strobe_i         => strobe_4x_logic,
+        logic_reset_i          => logic_reset,
+        rst_fifo_i             => rst_fifo_o,
+        buffer_full_i          => buffer_full_o,
+        trigger_i              => overall_trigger,
+        trigger_times_i        => postVetoTrigger_times,
+        trigger_inputs_fired_i => postVetotrigger,
+        trigger_cnt_i          => trigger_count,
+        shutter_i              => shutter_i,
+        shutter_cnt_i          => shutter_cnt_i,
+        spill_i                => spill_i,
+        spill_cnt_i            => spill_cnt_i,
+        edge_rise_i            => s_edge_rising,
+        edge_fall_i            => s_edge_falling,
+        edge_rise_time_i       => s_edge_rise_times,
+        edge_fall_time_i       => s_edge_fall_times,
+        ipbus_i                => ipbww(N_SLV_EVENT_FORMATTER),
+        ipbus_o                => ipbrr(N_SLV_EVENT_FORMATTER),
+        data_strobe_o          => data_strobe,
+        event_data_o           => event_data,
+        reset_timestamp_i      => s_T0,
+        reset_timestamp_o      => OPEN
+    );
+
+------------------------------------------
+    I7 : eventBuffer
+    GENERIC MAP (
+        g_EVENT_DATA_WIDTH   => g_EVENT_DATA_WIDTH,
+        g_IPBUS_WIDTH        => g_IPBUS_WIDTH,
+        g_READ_COUNTER_WIDTH => 14
+        
+    )
+    PORT MAP (
+        clk_4x_logic_i    => clk_4x_logic,
+        data_strobe_i     => data_strobe,
+        event_data_i      => event_data,
+        ipbus_clk_i       => clk_ipb,
+        ipbus_i           => ipbww(N_SLV_EVENTBUFFER),
+        ipbus_reset_i     => rst_ipb,
+        strobe_4x_logic_i => strobe_4x_logic,
+        rst_fifo_o        => rst_fifo_o,
+        buffer_full_o     => buffer_full_o,
+        ipbus_o           => ipbrr(N_SLV_EVENTBUFFER),
+        logic_reset_i     => logic_reset
+    );
+    
+------------------------------------------
+    I8 : T0_Shutter_Iface
+    PORT MAP (
+        clk_4x_i      => clk_4x_logic,
+        clk_4x_strobe_i => strobe_4x_logic,
+        accelerator_signals_i => triggers,
+        T0_o          => s_T0,
+        run_active_o  => s_run_active,
+        shutter_o     => s_shutter,
+        shutter_veto_o => s_shutter_veto,
+        ipbus_clk_i   => clk_ipb,
+        ipbus_i       => ipbww(N_SLV_SHUTTER),
+        ipbus_o       => ipbrr(N_SLV_SHUTTER)
+    );
+
+------------------------------------------
+    I9 : DUTInterfaces
+    GENERIC MAP (
+        g_NUM_DUTS    => g_NUM_DUTS,
+        g_IPBUS_WIDTH => g_IPBUS_WIDTH
+    )
+    PORT MAP (
+         clk_4x_logic_i          => clk_4x_logic,
+         strobe_4x_logic_i       => strobe_4x_logic,
+         trigger_counter_i       => trigger_count,
+         trigger_i               => overall_trigger,
+         reset_or_clk_to_dut_i   => s_T0,
+         shutter_to_dut_i        => s_shutter,
+         shutter_veto_i          => s_shutter_veto,
+         ipbus_clk_i             => clk_ipb,
+         ipbus_i                 => ipbww(N_SLV_DUTINTERFACES),
+         ipbus_reset_i           => rst_ipb,
+         ipbus_o                 => ipbrr(N_SLV_DUTINTERFACES),
+         busy_from_dut       => busy_i,
+         busy_to_dut        => open,
+         clk_from_dut => dut_clk_i,
+         clk_to_dut => dut_clk_o,
+         --reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+         --reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+         reset_to_dut => spare_o,
+         trigger_to_dut => triggers_o,
+         --shutter_to_dut_n_o      => shutter_to_dut_n_o,
+         --shutter_to_dut_p_o      => shutter_to_dut_p_o,
+         shutter_to_dut  => cont_o,
+         veto_o                  => s_veto
+    );
+    
+------------------------------------------ 
+        I10 : triggerLogic
+        GENERIC MAP (
+            g_NUM_INPUTS  => g_NUM_TRIG_INPUTS,
+            g_IPBUS_WIDTH => g_IPBUS_WIDTH
+        )
+        PORT MAP (
+            clk_4x_logic_i      => clk_4x_logic,
+            ipbus_clk_i         => clk_ipb,
+            ipbus_i             => ipbww(N_SLV_TRIGGERLOGIC),
+            ipbus_reset_i       => rst_ipb,
+            logic_reset_i       => s_triggerLogic_reset,
+            logic_strobe_i      => strobe_4x_logic,
+            trigger_i           => triggers,
+            trigger_times_i     => trigger_times,
+            veto_i              => overall_veto,
+            trigger_o           => postVetotrigger,
+            trigger_times_o     => postVetoTrigger_times,
+            event_number_o      => trigger_count,
+            ipbus_o             => ipbrr(N_SLV_TRIGGERLOGIC),
+            post_veto_trigger_o => overall_trigger,
+            pre_veto_trigger_o  => OPEN,
+            trigger_active_o    => leds(2)
+        );     
+         
+-------------TEST AREA------------    
+--    test0: entity work.test_inToOut
+--    port map(
+--        clk_in => clk_200,
+--        busy_in=> busy_i,
+--        control_in=> cont_i,
+--        trig_in=> triggers_i,
+--        clkDut_in=> dut_clk_i,
+--        spare_in=> spare_i,
+--        busy_out=> busy_o,
+--        control_out=> cont_o,
+--        trig_out=> triggers_o,
+--        clkDut_out=> dut_clk_o,
+--        spare_out=> spare_o
+--    );
+
+--    dutout0: entity work.DUTs_outputs
+--    port map(
+--        clk_in => clk_encl_buf, 
+--       d_clk_o => open, --dut_clk_o,
+--        d_trg_o => open, --triggers_o,
+--        d_busy_o => busy_o,
+--        d_cont_o => open, --cont_o,
+--        d_spare_o => open --spare_o
+--    );
+   
+--    clk50_o_fromEnclustra : clk_wiz_0
+--       port map ( 
+--       -- Clock in ports
+--       clk_in1 => clk_encl_buf, --sysclk_40,
+--      -- Clock out ports  
+--       clk_out1 => encl_clock50,
+--      -- Status and control signals                
+--       reset => '0',
+--       locked =>  open          
+--     );
+
+    
+----------------------------------------------
+
+
+
+
+
+
+
+
+
+
+    
+
+------------------------------------------      
+
+
+------------------------------------------
+    IBUFGDS_inst: IBUFGDS
+    generic map (
+        IBUF_LOW_PWR=> false
+    )
+    port map (
+        O => sysclk_40,
+        I => sysclk_40_i_p,
+        IB => sysclk_40_i_n
+    );
+    
+------------------------------------------
+    IBUFG_inst: IBUFG
+    port map (
+        O => clk_encl_buf,
+        I => sysclk -- clk_enclustra
+    );    
+
+------------------------------------------
+-- Do not use this: we need differential 3.3 V, not available.
+--    OBUFDS_inst : OBUFDS
+--    generic map (
+--        SLEW => "FAST") -- Specify the output slew rate
+--    port map (
+--        O => sysclk_50_o_p, -- Diff_p output (connect directly to top-level port)
+--        OB => sysclk_50_o_n, -- Diff_n output (connect directly to top-level port)
+--        I => encl_clock50 -- Buffer input
+--    );
+    -- This might not work: these are just two single ended. If we remove R coupling maybe?
+    --sysclk_50_o_p <= encl_clock50;
+    --sysclk_50_o_n <= not encl_clock50;
+
+      
+
+
+end rtl;
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc b/AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..a075e04b03b2d820f98ae39bc65c71c01d109b78
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
@@ -0,0 +1,26 @@
+#set_property IOSTANDARD LVCMOS33 [get_ports i2c_reset]
+set_property IOSTANDARD LVCMOS25 [get_ports i2c_reset]
+set_property PACKAGE_PIN C2 [get_ports i2c_reset]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
+set_property IOSTANDARD LVCMOS25 [get_ports i2c_scl_b]
+set_property PACKAGE_PIN N17 [get_ports i2c_scl_b]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
+set_property IOSTANDARD LVCMOS25 [get_ports i2c_sda_b]
+set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
+
+# -------------------------------------------------------------------------------------------------
+
+
+#DEBUG PROBES
+
+
+
+
+
+
+
+
+
+
diff --git a/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc b/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..3285439d438c0f3976ad0ec90c5ba30a87f549b8
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
@@ -0,0 +1,212 @@
+## Trigger inputs
+
+#set_property IOSTANDARD LVCMOS18 [get_ports {threshold_discr_p_i[*]}]
+#set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+
+set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
+set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
+set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
+set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
+set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
+set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
+set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
+set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
+set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
+set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
+set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
+
+## Miscellaneous I/O
+set_property IOSTANDARD LVCMOS25 [get_ports clk_gen_rst]
+set_property PACKAGE_PIN C1 [get_ports clk_gen_rst]
+set_property IOSTANDARD LVCMOS25 [get_ports gpio]
+set_property PACKAGE_PIN F6 [get_ports gpio]
+
+
+## Crystal clock
+set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
+set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
+set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
+
+## Output clock (currently not working so set to 0)
+set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_p]
+set_property PACKAGE_PIN E3 [get_ports sysclk_50_o_p]
+set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_n]
+set_property PACKAGE_PIN D3 [get_ports sysclk_50_o_n]
+
+## Inputs/Outputs for DUTs
+set_property IOSTANDARD LVCMOS25 [get_ports {busy_o[*]}]
+set_property PACKAGE_PIN R7 [get_ports {busy_o[0]}]
+set_property PACKAGE_PIN U4 [get_ports {busy_o[1]}]
+set_property PACKAGE_PIN R8 [get_ports {busy_o[2]}]
+set_property PACKAGE_PIN K5 [get_ports {busy_o[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {triggers_o[*]}]
+set_property PACKAGE_PIN R6 [get_ports {triggers_o[0]}]
+set_property PACKAGE_PIN P2 [get_ports {triggers_o[1]}]
+set_property PACKAGE_PIN R1 [get_ports {triggers_o[2]}]
+set_property PACKAGE_PIN U1 [get_ports {triggers_o[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {cont_o[*]}]
+set_property PACKAGE_PIN N5 [get_ports {cont_o[0]}]
+set_property PACKAGE_PIN P4 [get_ports {cont_o[1]}]
+set_property PACKAGE_PIN M6 [get_ports {cont_o[2]}]
+set_property PACKAGE_PIN L6 [get_ports {cont_o[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {spare_o[*]}]
+set_property PACKAGE_PIN L1 [get_ports {spare_o[0]}]
+set_property PACKAGE_PIN M4 [get_ports {spare_o[1]}]
+set_property PACKAGE_PIN N2 [get_ports {spare_o[2]}]
+set_property PACKAGE_PIN M3 [get_ports {spare_o[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_o[*]}]
+set_property PACKAGE_PIN K3 [get_ports {dut_clk_o[0]}]
+set_property PACKAGE_PIN F4 [get_ports {dut_clk_o[1]}]
+set_property PACKAGE_PIN E2 [get_ports {dut_clk_o[2]}]
+set_property PACKAGE_PIN G4 [get_ports {dut_clk_o[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {cont_i[*]}]
+set_property PACKAGE_PIN P5 [get_ports {cont_i[0]}]
+set_property PACKAGE_PIN P3 [get_ports {cont_i[1]}]
+set_property PACKAGE_PIN N6 [get_ports {cont_i[2]}]
+set_property PACKAGE_PIN L5 [get_ports {cont_i[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {spare_i[*]}]
+set_property PACKAGE_PIN M1 [get_ports {spare_i[0]}]
+set_property PACKAGE_PIN N4 [get_ports {spare_i[1]}]
+set_property PACKAGE_PIN N1 [get_ports {spare_i[2]}]
+set_property PACKAGE_PIN M2 [get_ports {spare_i[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {triggers_i[*]}]
+set_property PACKAGE_PIN R5 [get_ports {triggers_i[0]}]
+set_property PACKAGE_PIN R2 [get_ports {triggers_i[1]}]
+set_property PACKAGE_PIN T1 [get_ports {triggers_i[2]}]
+set_property PACKAGE_PIN V1 [get_ports {triggers_i[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {busy_i[*]}]
+set_property PACKAGE_PIN T6 [get_ports {busy_i[0]}]
+set_property PACKAGE_PIN U3 [get_ports {busy_i[1]}]
+set_property PACKAGE_PIN T8 [get_ports {busy_i[2]}]
+set_property PACKAGE_PIN L4 [get_ports {busy_i[3]}]
+
+set_property IOSTANDARD LVCMOS25 [get_ports {dut_clk_i[*]}]
+set_property PACKAGE_PIN L3 [get_ports {dut_clk_i[0]}]
+set_property PACKAGE_PIN F3 [get_ports {dut_clk_i[1]}]
+set_property PACKAGE_PIN D2 [get_ports {dut_clk_i[2]}]
+set_property PACKAGE_PIN G3 [get_ports {dut_clk_i[3]}]
+
+# -------------------------------------------------------------------------------------------------
+
+
+
+#Define clock groups and make them asynchronous with each other
+#set_clock_groups -asynchronous -group {sysclk I I_1 mmcm_n_10 mmcm_n_6 mmcm_n_8 clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
+# What has gone wrong ....
+# FIXME
+#set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
+#set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p s_clk160}
+#set_clock_groups -asynchronous -group { [get_nets sysclk] } -group { [get_nets *sysclk_40_i*]}
+
+
+
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+
+# -false_path
+
+#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {sysclk clk_ipb_i}] -group [get_clocks -include_generated_clocks {s_clk160 sysclk_40_i_p}]
+
+#set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks [get_ports sysclk]] -group [get_clocks -include_generated_clocks [get_ports sysclk_40_i_p]]
+# set_false_path -from [get_clocks sysclk] -to [get_clocks sysclk_40_i_p]
+#set_clock_groups -asynchronous -group {[get_clocks sysclk]} -group {[get_clocks sysclk_40_i_p]}
+#set_clock_groups -asynchronous -group [get_clocks sysclk] -group [get_clocks sysclk_40_i_p]
+
+
+
+
+create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
+set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
+connect_debug_port u_ila_0/probe13 [get_nets [list shutter_veto_o]]
+connect_debug_port u_ila_0/probe16 [get_nets [list veto_i]]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 4 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {I9/s_DUT_ignore_busy[0]} {I9/s_DUT_ignore_busy[1]} {I9/s_DUT_ignore_busy[2]} {I9/s_DUT_ignore_busy[3]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 6 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 6 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {I10/trigger_o[0]} {I10/trigger_o[1]} {I10/trigger_o[2]} {I10/trigger_o[3]} {I10/trigger_o[4]} {I10/trigger_o[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 6 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {triggers[0]} {triggers[1]} {triggers[2]} {triggers[3]} {triggers[4]} {triggers[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list buffer_full_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list I9/s_IgnoreShutterVeto]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list I10/s_post_veto_trigger0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list I10/s_post_veto_trigger1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list I10/s_pre_veto_trigger_reg_n_0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list I8/cmp_SyncGen/s_shutter]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list s_shutter]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list I8/cmp_SyncGen/s_trigger]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list I6/s_trigger]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list I6/trigger_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+set_property port_width 1 [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+set_property port_width 1 [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list I9/veto_o]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk_4x_logic]
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AD5665R.py b/AIDA_tlu/projects/TLU_v1e/scripts/AD5665R.py
new file mode 120000
index 0000000000000000000000000000000000000000..57e57fb0cfc8236b30eca34ccb75d57d867ec931
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AD5665R.py
@@ -0,0 +1 @@
+packages/AD5665R.py
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testPower.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testPower.py
new file mode 100644
index 0000000000000000000000000000000000000000..9c13ba6af09634d1a346baf2e6f4b9cc4e53819e
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testPower.py
@@ -0,0 +1,85 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+
+
+#
+# #######################################
+enableCore= False #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+
+
+#DAC CONFIGURATION BEGIN
+if (False):
+   zeDAC1=AD5665R(master_I2C, 0x1C)
+   zeDAC1.setIntRef(intRef= False, verbose= True)
+   zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+if (True):
+   # #I2C EXPANDER CONFIGURATION BEGIN
+   IC6=PCA9539PW(master_I2C, 0x76)
+   #BANK 0
+   IC6.setInvertReg(0, 0x00)# 0= normal
+   IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+   IC6.setOutputs(0, 0x00)
+   res= IC6.getInputs(0)
+   print "IC6 read back bank 0: 0x%X" % res[0]
+   #
+   #BANK 1
+   IC6.setInvertReg(1, 0x00)# 0= normal
+   IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+   IC6.setOutputs(1, 0x00)
+   res= IC6.getInputs(1)
+   print "IC6 read back bank 1: 0x%X" % res[0]
+
+   # # #
+   IC7=PCA9539PW(master_I2C, 0x77)
+   #BANK 0
+   IC7.setInvertReg(0, 0x00)# 0= normal
+   IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+   IC7.setOutputs(0, 0x00)
+   res= IC7.getInputs(0)
+   print "IC7 read back bank 0: 0x%X" % res[0]
+   #
+   #BANK 1
+   IC7.setInvertReg(1, 0x00)# 0= normal
+   IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+   IC7.setOutputs(1, 0x00)
+   res= IC7.getInputs(1)
+   print "IC7 read back bank 1: 0x%X" % res[0]
+   # #I2C EXPANDER CONFIGURATION END
+
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript.py
new file mode 100644
index 0000000000000000000000000000000000000000..b8fbcfa93ca45214083cbdad3727fe938f1e5da7
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript.py
@@ -0,0 +1,185 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+#clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+clkRegList= zeClock.parse_clk("./localClock.txt")
+
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0xFF)# 0= normal
+IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(0, 0xFF)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x4F)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx1_tx2.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx1_tx2.py
new file mode 100644
index 0000000000000000000000000000000000000000..e5a85434ac13f3f686cd2b82eca32bd98ddffc57
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx1_tx2.py
@@ -0,0 +1,188 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tluLoop")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(0, 0x77)
+IC6.setOutputs(0, 0x0F)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(1, 0x77)
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0x00)# 0= normal
+IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(0, 0x00)
+IC7.setOutputs(0, 0x0D)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+# LEDs and HDMI power
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(1, 0xB0)
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx2_tx1.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx2_tx1.py
new file mode 100644
index 0000000000000000000000000000000000000000..bd82bb11b4c151fc2a392de8d8f2c3ae29dbf34a
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx2_tx1.py
@@ -0,0 +1,188 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(0, 0x77)
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(1, 0x77)
+IC6.setOutputs(1, 0xF0)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0x00)# 0= normal
+IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(0, 0x00)
+IC7.setOutputs(0, 0x0B)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+# LEDs and HDMI power
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(1, 0xB0)
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx3_tx1.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx3_tx1.py
new file mode 100644
index 0000000000000000000000000000000000000000..7e005c242387d095708e8b635f6f050123b34627
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx0_rx3_tx1.py
@@ -0,0 +1,188 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(0, 0x77)
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(1, 0x77)
+IC6.setOutputs(1, 0x0F)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0x00)# 0= normal
+IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(0, 0x00)
+IC7.setOutputs(0, 0x07)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+# LEDs and HDMI power
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(1, 0xB0)
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx1_rx0_tx2.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx1_rx0_tx2.py
new file mode 100644
index 0000000000000000000000000000000000000000..02d0bf55271fb423db41062afedd4abb37c88f4f
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testScript_tx1_rx0_tx2.py
@@ -0,0 +1,188 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "CHECK REG= ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+
+
+# Plug cable into 1-->2 ( HDMI0-->1 ) look at 3 ( HDMI3 )
+
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+# #######################################
+#
+# time.sleep(0.1)
+# #Read the EPROM
+# mystop=False
+# nwords=6
+# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
+# myaddr= [0xfa]#0xfa
+# master_I2C.write( myslave, myaddr, mystop)
+# #res= master_I2C.read( 0x50, 6)
+# res= master_I2C.read( myslave, nwords)
+# print "  PCB EPROM: "
+# result="\t  "
+# for iaddr in res:
+#    result+="%02x "%(iaddr)
+# print result
+# #######################################
+
+
+#Second I2C core
+#print ("Instantiating SFP I2C core:")
+#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
+#clock_I2C.state()
+
+# #Third I2C core
+# print ("Instantiating clock I2C core:")
+# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
+# clock_I2C.state()
+
+
+# #time.sleep(0.01)
+# #Read the EPROM
+# mystop=False
+# nwords=2
+# myslave= 0x68 #DUNE CLOCK CHIP 0x68
+# myaddr= [0x02 ]#0xfa
+# clock_I2C.write( myslave, myaddr, mystop)
+# #time.sleep(0.1)
+# res= clock_I2C.read( myslave, nwords)
+# print "  CLOCK EPROM: "
+# result="\t  "
+# for iaddr in res:
+#     result+="%02x "%(iaddr)
+# print result
+
+#
+
+#CLOCK CONFIGURATION BEGIN
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(0, 0x77)
+IC6.setOutputs(0, 0xF0)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC6.setOutputs(1, 0x77)
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0x00)# 0= normal
+IC7.setIOReg(0, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(0, 0x00)
+IC7.setOutputs(0, 0x0E)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+# LEDs and HDMI power
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x00)# 0= output <<<<<<<<<<<<<<<<<<<
+#IC7.setOutputs(1, 0xB0)
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# #Reset counters
+#cmd = int("0x0", 16) #write 0x2 to reset
+#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
+#hw.dispatch()
+#print "Trigger Reset: 0x%X" % restatus
+## #Read trigger inputs
+#myreg= [-1, -1, -1, -1, -1, -1]
+#for inputN in range(0, 6):
+#  regString= "triggerInputs.ThrCount%dR" % inputN
+#  myreg[inputN]= hw.getNode(regString).read()
+#  hw.dispatch()
+#  print regString, myreg[inputN]
+
+## Read ev formatter
+#cmd = int("0x0", 16) #
+##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
+#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+#hw.dispatch()
+#print "Event Formatter Record: 0x%X" % efstatus
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testShutter.py b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testShutter.py
new file mode 100644
index 0000000000000000000000000000000000000000..c429f05ccdc335da5e705c8f10a815a0ad771f45
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/AIDA_testShutter.py
@@ -0,0 +1,141 @@
+# -*- coding: utf-8 -*-
+#
+# Sets up AIDA-2020 TLU to produce shutter signals.
+# After running this script there should be shutter signals on all DUT interfaces
+#
+import uhal
+from I2CuHal import I2CCore
+import time
+#import miniTLU
+from si5345 import si5345
+from AD5665R import AD5665R
+from PCA9539PW import PCA9539PW
+from E24AA025E48T import E24AA025E48T
+
+manager = uhal.ConnectionManager("file://./TLUconnection.xml")
+hw = manager.getDevice("tlu")
+
+# hw.getNode("A").write(255)
+reg = hw.getNode("version").read()
+hw.dispatch()
+print "Firmware Version Number = ", hex(reg)
+
+
+# #First I2C core
+print ("Instantiating master I2C core:")
+master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
+master_I2C.state()
+#
+# #######################################
+enableCore= True #Only need to run this once, after power-up
+if (enableCore):
+   mystop=True
+   print "  Write RegDir to set I/O[7] to output:"
+   myslave= 0x21
+   mycmd= [0x01, 0x7F]
+   nwords= 1
+   master_I2C.write(myslave, mycmd, mystop)
+
+
+   mystop=False
+   mycmd= [0x01]
+   master_I2C.write(myslave, mycmd, mystop)
+   res= master_I2C.read( myslave, nwords)
+   print "\tPost RegDir: ", res
+
+
+#CLOCK CONFIGURATION BEGIN
+print "Setting up clock"
+zeClock=si5345(master_I2C, 0x68)
+res= zeClock.getDeviceVersion()
+zeClock.checkDesignID()
+#zeClock.setPage(0, True)
+#zeClock.getPage(True)
+#clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+clkRegList= zeClock.parse_clk("./localClock.txt")
+
+zeClock.writeConfiguration(clkRegList)######
+zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
+zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
+zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
+iopower= zeClock.readRegister(0x0949, 1)
+print "  Clock IO power: 0x%X" % iopower[0]
+lol= zeClock.readRegister(0x000E, 1)
+print "  Clock LOL (0x000E): 0x%X" % lol[0]
+los= zeClock.readRegister(0x000D, 1)
+print "  Clock LOS (0x000D): 0x%X" % los[0]
+#CLOCK CONFIGURATION END
+
+#DAC CONFIGURATION BEGIN
+zeDAC1=AD5665R(master_I2C, 0x13)
+zeDAC1.setIntRef(intRef= False, verbose= True)
+zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
+
+zeDAC2=AD5665R(master_I2C, 0x1F)
+zeDAC2.setIntRef(intRef= False, verbose= True)
+zeDAC2.writeDAC(0x2fff, 3, verbose= True)
+#DAC CONFIGURATION END
+
+#EEPROM BEGIN
+zeEEPROM= E24AA025E48T(master_I2C, 0x50)
+res=zeEEPROM.readEEPROM(0xfa, 6)
+result="  EEPROM ID:\n\t"
+for iaddr in res:
+    result+="%02x "%(iaddr)
+print result
+#EEPROM END
+
+# #I2C EXPANDER CONFIGURATION BEGIN
+IC6=PCA9539PW(master_I2C, 0x74)
+#BANK 0
+IC6.setInvertReg(0, 0x00)# 0= normal
+IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(0, 0xFF)
+res= IC6.getInputs(0)
+print "IC6 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC6.setInvertReg(1, 0x00)# 0= normal
+IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
+IC6.setOutputs(1, 0xFF)
+res= IC6.getInputs(1)
+print "IC6 read back bank 1: 0x%X" % res[0]
+
+# # #
+IC7=PCA9539PW(master_I2C, 0x75)
+#BANK 0
+IC7.setInvertReg(0, 0xFF)# 0= normal
+IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(0, 0xFF)
+res= IC7.getInputs(0)
+print "IC7 read back bank 0: 0x%X" % res[0]
+#
+#BANK 1
+IC7.setInvertReg(1, 0x00)# 0= normal
+IC7.setIOReg(1, 0x4F)# 0= output <<<<<<<<<<<<<<<<<<<
+IC7.setOutputs(1, 0xFF)
+res= IC7.getInputs(1)
+print "IC7 read back bank 1: 0x%X" % res[0]
+# #I2C EXPANDER CONFIGURATION END
+
+
+# Set up shutter registers
+print "Setting up shutter registers"
+shutterPeriod = 1024
+T1 = 100
+T2 = 200
+T3 = 300
+hw.getNode("Shutter.InternalShutterPeriodW").write(shutterPeriod)
+hw.getNode("Shutter.ShutterOnTimeW").write(T1)
+hw.getNode("Shutter.VetoOffTimeW").write(T2)
+hw.getNode("Shutter.ShutterOffTimeW").write(T3)
+# Enable shutter signal and internal sequence generator
+hw.getNode("Shutter.ControlW").write(2)
+
+# Enable DUT intefaces
+hw.getNode("DUTInterfaces.DutMaskW").write(0xF)
+hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(0xF)
+
+hw.dispatch()
+
+print "All done"
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/E24AA025E48T.py b/AIDA_tlu/projects/TLU_v1e/scripts/E24AA025E48T.py
new file mode 120000
index 0000000000000000000000000000000000000000..d7fe7bd0ff7417cdd436ee16eda87959c5083319
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/E24AA025E48T.py
@@ -0,0 +1 @@
+packages/E24AA025E48T.py
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/I2CuHal.py b/AIDA_tlu/projects/TLU_v1e/scripts/I2CuHal.py
new file mode 120000
index 0000000000000000000000000000000000000000..334e4f2cf044defdf3291ae5e4666349b32b4a98
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/I2CuHal.py
@@ -0,0 +1 @@
+./packages/I2CuHal.py
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/PCA9539PW.py b/AIDA_tlu/projects/TLU_v1e/scripts/PCA9539PW.py
new file mode 120000
index 0000000000000000000000000000000000000000..36fda8171c9e0215c59ac3965128e70896798ceb
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/PCA9539PW.py
@@ -0,0 +1 @@
+packages/PCA9539PW.py
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/README b/AIDA_tlu/projects/TLU_v1e/scripts/README
new file mode 100644
index 0000000000000000000000000000000000000000..e83b348a5b25c4ec4e8bf665786b86f9e247ae71
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/README
@@ -0,0 +1 @@
+copied "as is" from timing firmware. CHANGE ME !!
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/SI5344 b/AIDA_tlu/projects/TLU_v1e/scripts/SI5344
new file mode 120000
index 0000000000000000000000000000000000000000..fc3bcc8eb2b296675693366009fa0df3d848b29e
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/SI5344
@@ -0,0 +1 @@
+../../../../components/pdts/software/SI5344
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/TLU_v1e.py b/AIDA_tlu/projects/TLU_v1e/scripts/TLU_v1e.py
new file mode 100644
index 0000000000000000000000000000000000000000..08078bcbf041790efc7cb844c466dcec386d427c
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/TLU_v1e.py
@@ -0,0 +1,1074 @@
+# -*- coding: utf-8 -*-
+import uhal;
+import pprint;
+import ConfigParser
+#from FmcTluI2c import *
+import threading
+from ROOT import TFile, TTree, gROOT, AddressOf
+from ROOT import *
+import time
+
+from I2CuHal import I2CCore
+from si5345 import si5345 # Library for clock chip
+from AD5665R import AD5665R # Library for DAC
+from PCA9539PW import PCA9539PW # Library for serial line expander
+from I2CDISP import CFA632 #Library for display
+from TLU_powermodule import PWRLED
+from ATSHA204A import ATSHA204A
+
+class TLU:
+    """docstring for TLU"""
+    def __init__(self, dev_name, man_file, parsed_cfg):
+
+        uhal.setLogLevelTo(uhal.LogLevel.NOTICE) ## Get rid of initial flood of IPBUS messages
+        self.isRunning= False
+
+        section_name= "Producer.fmctlu"
+        self.dev_name = dev_name
+
+        #man_file= parsed_cfg.get(section_name, "ConnectionFile")
+        self.manager= uhal.ConnectionManager(man_file)
+        self.hw = self.manager.getDevice(self.dev_name)
+
+        # #Get Verbose setting
+        self.verbose= parsed_cfg.getint(section_name, "verbose")
+
+        #self.nDUTs= 4 #Number of DUT connectors
+        self.nDUTs= parsed_cfg.getint(section_name, "nDUTs")
+
+        #self.nChannels= 6 #Number of trigger inputs
+        self.nChannels= parsed_cfg.getint(section_name, "nTrgIn")
+
+        #self.VrefInt= 2.5 #Internal DAC voltage reference
+        self.VrefInt= parsed_cfg.getfloat(section_name, "VRefInt")
+
+        #self.VrefExt= 1.3 #External DAC voltage reference
+        self.VrefExt= parsed_cfg.getfloat(section_name, "VRefExt")
+
+        #self.intRefOn= False #Internal reference is OFF by default
+        self.intRefOn= int(parsed_cfg.get(section_name, "intRefOn"))
+
+
+        self.fwVersion = self.hw.getNode("version").read()
+        self.hw.dispatch()
+        print "TLU V1E FIRMWARE VERSION= " , hex(self.fwVersion)
+
+        # Instantiate a I2C core to configure components
+        self.TLU_I2C= I2CCore(self.hw, 10, 5, "i2c_master", None)
+        #self.TLU_I2C.state()
+
+        enableCore= True #Only need to run this once, after power-up
+        self.enableCore()
+        ####### EEPROM AX3 testing
+        doAtmel= False
+        if doAtmel:
+            self.ax3eeprom= ATSHA204A(self.TLU_I2C, 0x64)
+            print "shiftR\tdatBit\tcrcBit\tcrcReg \n", self.ax3eeprom._CalculateCrc([255, 12, 54, 28, 134, 89], 3)
+            self.ax3eeprom._wake(True, True)
+            print self.ax3eeprom._GetCommandPacketSize(8)
+            #self.eepromAX3read()
+        ####### EEPROM AX3 testing end
+
+        # Instantiate clock chip and configure it (if necessary)
+        #self.zeClock=si5345(self.TLU_I2C, 0x68)
+        clk_addr= int(parsed_cfg.get(section_name, "I2C_CLK_Addr"), 16)
+        self.zeClock=si5345(self.TLU_I2C, clk_addr)
+        res= self.zeClock.getDeviceVersion()
+        if (int(parsed_cfg.get(section_name, "CONFCLOCK"), 16)):
+            #clkRegList= self.zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
+            clkRegList= self.zeClock.parse_clk(parsed_cfg.get(section_name, "CLOCK_CFG_FILE"))
+            self.zeClock.writeConfiguration(clkRegList, self.verbose)######
+
+        self.zeClock.checkDesignID()
+
+        # Instantiate DACs and configure them to use reference based on TLU setting
+        #self.zeDAC1=AD5665R(self.TLU_I2C, 0x13)
+        #self.zeDAC2=AD5665R(self.TLU_I2C, 0x1F)
+        dac_addr1= int(parsed_cfg.get(section_name, "I2C_DAC1_Addr"), 16)
+        self.zeDAC1=AD5665R(self.TLU_I2C, dac_addr1)
+        dac_addr2= int(parsed_cfg.get(section_name, "I2C_DAC2_Addr"), 16)
+        self.zeDAC2=AD5665R(self.TLU_I2C, dac_addr2)
+        self.zeDAC1.setIntRef(self.intRefOn, self.verbose)
+        self.zeDAC2.setIntRef(self.intRefOn, self.verbose)
+
+        # Instantiate the serial line expanders and configure them to default values
+        #self.IC6=PCA9539PW(self.TLU_I2C, 0x74)
+        exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1_Addr"), 16)
+        self.IC6=PCA9539PW(self.TLU_I2C, exp1_addr)
+        self.IC6.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(0, 0xFF)# If output, set to XX
+
+        self.IC6.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC6.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC6.setOutputs(1, 0xFF)# If output, set to XX
+
+        #self.IC7=PCA9539PW(self.TLU_I2C, 0x75)
+        exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2_Addr"), 16)
+        self.IC7=PCA9539PW(self.TLU_I2C, exp2_addr)
+        self.IC7.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(0, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(0, 0x00)# If output, set to XX
+
+        self.IC7.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.IC7.setIOReg(1, 0x00)# 0= output, 1= input
+        self.IC7.setOutputs(1, 0xB0)# If output, set to XX
+
+        #Instantiate Display
+        self.DISP=CFA632(self.TLU_I2C, 0x2A) #
+
+        #Instantiate Power/Led Module
+        dac_addr_module= int(parsed_cfg.get(section_name, "I2C_DACModule_Addr"), 16)
+        exp1_addr= int(parsed_cfg.get(section_name, "I2C_EXP1Module_Addr"), 16)
+        exp2_addr= int(parsed_cfg.get(section_name, "I2C_EXP2Module_Addr"), 16)
+        pmtCtrVMax= parsed_cfg.getfloat(section_name, "PMT_vCtrlMax")
+
+        self.pwdled= PWRLED(self.TLU_I2C, dac_addr_module, pmtCtrVMax, exp1_addr, exp2_addr)
+
+        #self.pwdled.setIndicatorRGB(1, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(2, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(3, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(4, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(5, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(6, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(7, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(8, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(9, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(10, [0, 0, 1])
+        #self.pwdled.setIndicatorRGB(11, [0, 0, 1])
+
+        self.pwdled.allGreen()
+        time.sleep(0.1)
+        self.pwdled.allBlue()
+        time.sleep(0.1)
+        self.pwdled.allBlack()
+        time.sleep(0.1)
+        #self.pwdled.kitt()
+        time.sleep(0.1)
+        #self.pwdled.allBlack()
+        #self.pwdled.allRed()
+        #time.sleep(0.1)
+        self.pwdled.allWhite()
+
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def DUTOutputs_old(self, dutN, enable=False, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+        ## NOTE: This version changes all the pins together. Use DUTOutputs to control individual pins.
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "to", enable
+        if (verbose > 1):
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getOutputs(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newStatus= oldStatus & (~mask)
+        if (not enable): # we want to write 0 to activate the outputs so check opposite of "enable"
+            newStatus |= mask
+        self.IC6.setOutputs(bank, newStatus)
+
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        return newStatus
+
+    def DUTOutputs(self, dutN, enable=0x7, verbose=False):
+        ## Set the status of the transceivers for a specific HDMI connector. When enable= False the transceivers are disabled and the
+        ## connector cannot send signals from FPGA to the outside world. When enable= True then signals from the FPGA will be sent out to the HDMI.
+        ## NOTE: the other direction is always enabled, i.e. signals from the DUTs are always sent to the FPGA.
+        ## NOTE: CLK direction must be defined separately using DUTClkSrc
+
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        print "  Setting DUT:", dutN, "pins status to", hex(enable)
+        if (verbose > 1):
+            print "\tBank", bank, "Nibble", nibble
+        res= self.IC6.getOutputs(bank)
+        oldStatus= res[0]
+        mask= 0xF << 4*nibble
+        newnibble= (enable & 0xF) << 4*nibble # bits we want to change are marked with 1
+        newStatus= (oldStatus & (~mask)) | (newnibble & mask)
+
+        self.IC6.setOutputs(bank, newStatus)
+
+        if (verbose > 0):
+            self.getDUTOutpus(dutN, verbose)
+        if (verbose > 1):
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+
+        return newStatus
+
+    def DUTClkSrc(self, dutN, clkSrc=0, verbose= False):
+        ## Allows to choose the source of the clock signal sent to the DUTs over HDMI
+        ## clkSrc= 0: clock disabled
+        ## clkSrc= 1: clock from Si5345
+        ## clkSrc=2: clock from FPGA
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTClkSrc. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        if (clkSrc < 0) | (clkSrc> 2):
+            print "\tERROR: DUTClkSrc. clkSrc can only be 0 (disabled), 1 (Si5345) or 2 (FPGA)"
+            return -1
+        bank=0
+        maskLow= 1 << (1* dutN) #CLK FROM FPGA
+        maskHigh= 1<< (1* dutN +4) #CLK FROM Si5345
+        mask= maskLow | maskHigh
+        res= self.IC7.getOutputs(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask #set both bits to zero
+        outStat= ""
+        if clkSrc==0:
+#--- ./TLU_v1e.py 183
+#            newStatus = newStatus | mask
+#+++ /users/phdgc/firmware_AIDA_PaoloGB/firmware_AIDA/TLU_v1e/scripts/TLU_v1e.py 233
+            newStatus = newStatus
+            outStat= "disabled"
+        elif clkSrc==1:
+            newStatus = newStatus | maskLow
+            outStat= "Si5435"
+        elif clkSrc==2:
+            newStatus= newStatus | maskHigh
+            outStat= "FPGA"
+        print "  Setting DUT:", dutN, "clock source to", outStat
+        if (verbose > 1):
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setOutputs(bank, newStatus)
+        return newStatus
+
+    def eepromAX3read(self):
+        mystop=True
+        print "  Reading AX3 eeprom (not working 100% yet):"
+        myslave= 0x64
+        self.TLU_I2C.write(myslave, [0x02, 0x00])
+        nwords= 5
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tAX3 awake: ", res
+        mystop=True
+        nwords= 7
+        #mycmd= [0x03, 0x07, 0x02, 0x00, 0x00, 0x00, 0x1e, 0x2d]#conf 0?
+        mycmd= [0x03, 0x07, 0x02, 0x00, 0x01, 0x00, 0x17, 0xad]#conf 1 <<< seems to reply with correct error code (0)
+        #mycmd= [0x03, 0x07, 0x02, 0x02, 0x00, 0x00, 0x1d, 0xa8]#data 0?
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tAX3 EEPROM: ", res
+
+    def enableClkLEMO(self, enable= False, verbose= False):
+        ## Enable or disable the output clock to the differential LEMO output
+        bank=1
+        mask= 0x10
+        res= self.IC7.getOutputs(bank)
+        oldStatus= res[0]
+        newStatus= oldStatus & ~mask
+        outStat= "enabled"
+        if (not enable): #A 0 activates the output. A 1 disables it.
+            newStatus= newStatus | mask
+            outStat= "disabled"
+        print "  Clk LEMO", outStat
+        if verbose:
+            print "\tOldStatus= ", "{0:#0{1}x}".format(oldStatus,4), "Mask=" , hex(mask), "newStatus=", "{0:#0{1}x}".format(newStatus,4)
+        self.IC7.setOutputs(bank, newStatus)
+        return newStatus
+
+    def enableCore(self):
+        ## At power up the Enclustra I2C lines are disabled (tristate buffer is off).
+        ## This function enables the lines. It is only required once.
+        mystop=True
+        print "  Enabling I2C bus (expect 127):"
+        myslave= 0x21
+        mycmd= [0x01, 0x7F]
+        nwords= 1
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+
+        mystop=False
+        mycmd= [0x01]
+        self.TLU_I2C.write(myslave, mycmd, mystop)
+        res= self.TLU_I2C.read( myslave, nwords)
+        print "\tPost RegDir: ", res
+
+    def getDUTOutpus(self, dutN, verbose=0):
+        if (dutN < 0) | (dutN> (self.nDUTs-1)):
+            print "\tERROR: DUTOutputs. The DUT number must be comprised between 0 and ", self.nDUTs-1
+            return -1
+        bank= dutN//2 # DUT0 and DUT1 are on bank 0. DUT2 and DUT3 on bank 1
+        nibble= dutN%2 # DUT0 and DUT2 are on nibble 0. DUT1 and DUT3 are on nibble 1
+        res= self.IC6.getOutputs(bank)
+        dut_status= res[0]
+        dut_lines= ["CONT", "SPARE", "TRIG", "BUSY"]
+        dut_status= 0x0F & (dut_status >> (4*nibble))
+
+        if verbose > 0:
+            for idx, iLine in enumerate(dut_lines):
+                this_bit= 0x1 & (dut_status  >> idx)
+                if this_bit:
+                    this_status= "ENABLED"
+                else:
+                    this_status= "DISABLED"
+                print "\t", iLine, "output is", this_status
+
+        if verbose > 1:
+            print "\tDUT CURRENT:", hex(dut_status), "Nibble:", nibble, "Bank:", bank
+
+        return dut_status
+
+    def getAllChannelsCounts(self):
+        chCounts=[]
+        for ch in range (0,self.nChannels):
+            chCounts.append(int(self.getChCount(ch)))
+        return chCounts
+
+    def getChStatus(self):
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "\tTRIGGER COUNTERS status= " , hex(inputStatus)
+        return inputStatus
+
+    def getChCount(self, channel):
+        regString= "triggerInputs.ThrCount"+ str(channel)+"R"
+        count = self.hw.getNode(regString).read()
+        self.hw.dispatch()
+        print "\tCh", channel, "Count:" , count
+        return count
+
+    def getClockStatus(self):
+        clockStatus = self.hw.getNode("logic_clocks.LogicClocksCSR").read()
+        self.hw.dispatch()
+        print "  CLOCK STATUS [expected 1]"
+        print "\t", hex(clockStatus)
+        if ( clockStatus == 0 ):
+            "ERROR: Clocks in TLU FPGA are not locked."
+        return clockStatus
+
+    def getDUTmask(self):
+        DUTMaskR = self.hw.getNode("DUTInterfaces.DutMaskR").read()
+        self.hw.dispatch()
+        print "\tDUTMask read back as:" , hex(DUTMaskR)
+        return DUTMaskR
+
+    def getExternalVeto(self):
+        extVeto= self.hw.getNode("triggerLogic.ExternalTriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tEXTERNAL Veto read back as:", hex(extVeto)
+        return extVeto
+
+    def getFifoData(self, nWords):
+    	#fifoData= self.hw.getNode("eventBuffer.EventFifoData").read()
+    	fifoData= self.hw.getNode("eventBuffer.EventFifoData").readBlock (nWords);
+    	self.hw.dispatch()
+    	#print "\tFIFO Data:", hex(fifoData)
+    	return fifoData
+
+    def getFifoLevel(self, verbose= 0):
+        FifoFill= self.hw.getNode("eventBuffer.EventFifoFillLevel").read()
+        self.hw.dispatch()
+        if (verbose > 0):
+            print "\tFIFO level read back as:", hex(FifoFill)
+        return FifoFill
+
+    def getFifoCSR(self):
+        FifoCSR= self.hw.getNode("eventBuffer.EventFifoCSR").read()
+        self.hw.dispatch()
+        print "\tFIFO CSR read back as:", hex(FifoCSR)
+        return FifoCSR
+
+    def getFifoFlags(self):
+        # Useless?
+        FifoFLAG= self.hw.getNode("eventBuffer.EventFifoFillLevelFlags").read()
+        self.hw.dispatch()
+        print "\tFIFO FLAGS read back as:", hex(FifoFLAG)
+        return FifoFLAG
+
+    def getInternalTrg(self):
+        trigIntervalR = self.hw.getNode("triggerLogic.InternalTriggerIntervalR").read()
+        self.hw.dispatch()
+        print "\tInternal interval read back as:", trigIntervalR
+        return trigIntervalR
+
+    def getMode(self):
+        DUTInterfaceModeR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeR").read()
+        self.hw.dispatch()
+        print "\tDUT mode read back as:" , hex(DUTInterfaceModeR)
+        return DUTInterfaceModeR
+
+    def getModeModifier(self):
+        DUTInterfaceModeModifierR = self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierR").read()
+        self.hw.dispatch()
+        print "\tDUT mode modifier read back as:" , hex(DUTInterfaceModeModifierR)
+        return DUTInterfaceModeModifierR
+
+    def getSN(self):
+        epromcontent=self.readEEPROM(0xfa, 6)
+        print "  FMC-TLU serial number (EEPROM):"
+        result="\t"
+        for iaddr in epromcontent:
+            result+="%02x "%(iaddr)
+        print result
+        return epromcontent
+
+    def getPostVetoTrg(self):
+        triggerN = self.hw.getNode("triggerLogic.PostVetoTriggersR").read()
+        self.hw.dispatch()
+        print "\tPOST VETO TRIGGER NUMBER:", (triggerN)
+        return triggerN
+
+    def getPulseDelay(self):
+        pulseDelayR = self.hw.getNode("triggerLogic.PulseDelayR").read()
+        self.hw.dispatch()
+        print "\tPulse delay read back as:", hex(pulseDelayR)
+        return pulseDelayR
+
+    def getPulseStretch(self):
+        pulseStretchR = self.hw.getNode("triggerLogic.PulseStretchR").read()
+        self.hw.dispatch()
+        print "\tPulse stretch read back as:", hex(pulseStretchR)
+        return pulseStretchR
+
+    def getRecordDataStatus(self):
+        RecordStatus= self.hw.getNode("Event_Formatter.Enable_Record_Data").read()
+        self.hw.dispatch()
+        print "\tData recording:", RecordStatus
+        return RecordStatus
+
+    def getTriggerVetoStatus(self):
+        trgVetoStatus= self.hw.getNode("triggerLogic.TriggerVetoR").read()
+        self.hw.dispatch()
+        print "\tTrigger veto status read back as:", trgVetoStatus
+        return trgVetoStatus
+
+    def getTrgPattern(self):
+        triggerPattern_low = self.hw.getNode("triggerLogic.TriggerPattern_lowR").read()
+        triggerPattern_high = self.hw.getNode("triggerLogic.TriggerPattern_highR").read()
+        self.hw.dispatch()
+        print "\tTrigger pattern read back as: 0x%08X 0x%08X" %(triggerPattern_high, triggerPattern_low)
+        return triggerPattern_low, triggerPattern_high
+
+    def getVetoDUT(self):
+        IgnoreDUTBusyR = self.hw.getNode("DUTInterfaces.IgnoreDUTBusyR").read()
+        self.hw.dispatch()
+        print "\tIgnoreDUTBusy read back as:" , hex(IgnoreDUTBusyR)
+        return IgnoreDUTBusyR
+
+    def getVetoShutters(self):
+        IgnoreShutterVeto = self.hw.getNode("DUTInterfaces.IgnoreShutterVetoR").read()
+        self.hw.dispatch()
+        print "\tIgnoreShutterVeto read back as:" , IgnoreShutterVeto
+        return IgnoreShutterVeto
+
+    def getShutterControl(self):
+        shutterControl = self.hw.getNode("Shutter.ControlW").read()
+        self.hw.dispatch()
+        print "\tShutter control read back as:" , hex(shutterControl)
+        return shutterControl
+
+    def getShutterSource(self):
+        shutterSource = self.hw.getNode("Shutter.ShutterSelectW").read()
+        self.hw.dispatch()
+        print "\tShutter source read back as:" , shutterSource
+        return shutterSource
+
+    def getShutterInternalInterval(self):
+        shutterInternalInterval = self.hw.getNode("Shutter.InternalShutterPeriodW").read()
+        self.hw.dispatch()
+        print "\tShutter internal inverval read back as:" , shutterInternalInterval
+        return shutterInternalInterval    
+    
+    def getShutterOnTime(self):
+        shutterontime = self.hw.getNode("Shutter.ShutterOnTimeW").read()
+        self.hw.dispatch()
+        print "\tShutter on time:" , shutterontime
+        return shutterontime
+
+    def getShutterOffTime(self):
+        shutterofftime = self.hw.getNode("Shutter.ShutterOffTimeW").read()
+        self.hw.dispatch()
+        print "\tShutter off time:" , shutterofftime
+        return shutterofftime
+
+    def getShutterVetoOffTime(self):
+        vetoofftime = self.hw.getNode("Shutter.VetoOffTimeW").read()
+        self.hw.dispatch()
+        print "\tVeto off time:" , vetoofftime
+        return vetoofftime
+        
+    def setRunActive(self):
+        cmd = int("0x1",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tSet run active (pulsing T0)"
+
+    def setRunInactive(self):
+        cmd = int("0x0",16)
+        self.hw.getNode("Shutter.PulseT0").write(cmd)
+        self.hw.dispatch()
+        print "\tSet run inactive"
+
+    def readEEPROM(self, startadd, bytes):
+        mystop= 1
+        time.sleep(0.1)
+        myaddr= [startadd]#0xfa
+        self.TLU_I2C.write( 0x50, [startadd], mystop)
+        res= self.TLU_I2C.read( 0x50, bytes)
+        return res
+
+    def resetClock(self):
+        # Set the RST pin from the PLL to 1
+        print "  Clocks reset"
+        cmd = int("0x1",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def resetClocks(self):
+        #Reset clock PLL
+        self.resetClock()
+        #Get clock status after reset
+        self.getClockStatus()
+        #Restore clock PLL
+        self.restoreClock()
+        #Get clock status after restore
+        self.getClockStatus()
+        #Get serdes status
+        self.getChStatus()
+
+    def resetCounters(self):
+    	cmd = int("0x2", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	cmd = int("0x0", 16) #write 0x2 to reset
+    	self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+    	restatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+    	self.hw.dispatch()
+    	#print "Trigger Reset: 0x%X" % restatus
+    	print "\tTrigger counters reset"
+
+    def resetSerdes(self):
+        cmd = int("0x3",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during reset = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after reset = " , hex(inputStatus)
+
+        cmd = int("0x4",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status during calibration = " , hex(inputStatus)
+
+        cmd = int("0x0",16)
+        self.setChStatus(cmd)
+        inputStatus= self.getChStatus()
+        print "\t  Input status after calibration = " , hex(inputStatus)
+
+    def restoreClock(self):
+        # Set the RST pin from the PLL to 0
+        print "  Clocks restore"
+        cmd = int("0x0",16)
+        self.hw.getNode("logic_clocks.LogicRst").write(cmd)
+        self.hw.dispatch()
+
+    def setChStatus(self, cmd):
+        self.hw.getNode("triggerInputs.SerdesRstW").write(cmd)
+        inputStatus= self.hw.getNode("triggerInputs.SerdesRstR").read()
+        self.hw.dispatch()
+        print "  INPUT STATUS SET TO= " , hex(inputStatus)
+
+    def setClockStatus(self, cmd):
+        # Only use this for testing. The clock source is actually selected in the Si5345.
+        self.hw.getNode("logic_clocks.LogicClocksCSR").write(cmd)
+        self.hw.dispatch()
+
+    def setDUTmask(self, DUTMask):
+        print "  DUT MASK ENABLING: Mask= " , hex(DUTMask)
+        self.hw.getNode("DUTInterfaces.DutMaskW").write(DUTMask)
+        self.hw.dispatch()
+        self.getDUTmask()
+
+    def setFifoCSR(self, cmd):
+        self.hw.getNode("eventBuffer.EventFifoCSR").write(cmd)
+        self.hw.dispatch()
+        self.getFifoCSR()
+
+    def setInternalTrg(self, triggerInterval):
+        print "  TRIGGERS INTERNAL:"
+        if triggerInterval == 0:
+            internalTriggerFreq = 0
+            print "\tdisabled"
+        else:
+            internalTriggerFreq = 160000000.0/triggerInterval
+            print "\tRequired internal trigger frequency:", triggerInterval, "Hz"
+            print "\tSetting internal interval to:", internalTriggerFreq
+        self.hw.getNode("triggerLogic.InternalTriggerIntervalW").write(int(internalTriggerFreq))
+        self.hw.dispatch()
+        self.getInternalTrg()
+
+    def setMode(self, mode):
+        print "  DUT MODE SET TO: ", hex(mode)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeW").write(mode)
+        self.hw.dispatch()
+        self.getMode()
+
+    def setModeModifier(self, modifier):
+        print "  DUT MODE MODIFIER:", hex(modifier)
+        self.hw.getNode("DUTInterfaces.DUTInterfaceModeModifierW").write(modifier)
+        self.hw.dispatch()
+        self.getModeModifier()
+
+    def setShutterControl(self, controlWord):
+        print "  SHUTTER CONTROL:", hex(controlWord)
+        self.hw.getNode("Shutter.ControlW").write(controlWord)
+        self.hw.dispatch()
+        self.getShutterControl()
+
+    def setShutterSource(self, source):
+        print "  SHUTTER SOURCE:", hex(source)
+        self.hw.getNode("Shutter.ShutterSelectW").write(source)
+        self.hw.dispatch()
+        self.getShutterSource()
+
+    def setShutterInternalInterval(self, interval):
+        print "  SHUTTER INTERNAL INTERVAL:", interval
+        self.hw.getNode("Shutter.InternalShutterPeriodW").write(interval)
+        self.hw.dispatch()
+        self.getShutterInternalInterval()
+        
+    def setShutterOnTime(self, cycles):
+        print "  SHUTTER ON TIME:", cycles
+        self.hw.getNode("Shutter.ShutterOnTimeW").write(cycles)
+        self.hw.dispatch()
+        self.getShutterOnTime()
+
+    def setShutterOffTime(self, cycles):
+        print "  SHUTTER OFF TIME:", cycles
+        self.hw.getNode("Shutter.ShutterOffTimeW").write(cycles)
+        self.hw.dispatch()
+        self.getShutterOffTime()
+        
+    def setShutterVetoOffTime(self, cycles):
+        print "  SHUTTER VETO OFF:", cycles
+        self.hw.getNode("Shutter.VetoOffTimeW").write(cycles)
+        self.hw.dispatch()
+        self.getShutterVetoOffTime()
+        
+    def setPulseDelay(self, inArray):
+        print "  TRIGGER DELAY SET TO", inArray, "[Units= 160MHz clock, 5-bit values (one per input) packed in to 32-bit word]"
+        pulseDelay= self.packBits(inArray)
+        self.hw.getNode("triggerLogic.PulseDelayW").write(pulseDelay)
+        self.hw.dispatch()
+        self.getPulseDelay()
+
+    def setPulseStretch(self, inArray):
+        print "  INPUT COINCIDENCE WINDOW SET TO", inArray ,"[Units= 160MHz clock cycles, 5-bit values (one per input) packed in to 32-bit word]"
+        pulseStretch= self.packBits(inArray)
+        self.hw.getNode("triggerLogic.PulseStretchW").write(pulseStretch)
+        self.hw.dispatch()
+        self.getPulseStretch()
+
+    def setRecordDataStatus(self, status=False):
+        print "  Data recording set:"
+        self.hw.getNode("Event_Formatter.Enable_Record_Data").write(status)
+        self.hw.dispatch()
+        self.getRecordDataStatus()
+
+    def setTriggerVetoStatus(self, status=False):
+        self.hw.getNode("triggerLogic.TriggerVetoW").write(status)
+        self.hw.dispatch()
+        self.getTriggerVetoStatus()
+
+    def setTrgPattern(self, triggerPatternH, triggerPatternL):
+        triggerPatternL &= 0xffffffff
+        triggerPatternH &= 0xffffffff
+        print "  TRIGGER PATTERN (for external triggers) SET TO 0x%08X 0x%08X. Two 32-bit words." %(triggerPatternH, triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_lowW").write(triggerPatternL)
+        self.hw.getNode("triggerLogic.TriggerPattern_highW").write(triggerPatternH)
+        self.hw.dispatch()
+        self.getTrgPattern()
+
+    def setVetoDUT(self, ignoreDUTBusy):
+        print "  VETO IGNORE BY DUT BUSY MASK SET TO" , hex(ignoreDUTBusy)
+        self.hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(ignoreDUTBusy)
+        self.hw.dispatch()
+        self.getVetoDUT()
+
+    def setVetoShutters(self, newState):
+        cmd = int(newState)
+        print " Setting IgnoreShutterVetoW to ", hex(newState)
+        self.hw.getNode("DUTInterfaces.IgnoreShutterVetoW").write(cmd)
+        self.hw.dispatch()
+        self.getVetoShutters()
+
+    def writeThreshold(self, DACtarget, Vtarget, channel, verbose=False):
+        #Writes the threshold. The DAC voltage differs from the threshold voltage because
+        #the range is shifted to be symmetrical around 0V.
+
+        #Check if the DACs are using the internal reference
+        if (self.intRefOn):
+            Vref= self.VrefInt
+        else:
+            Vref= self.VrefExt
+
+        #Calculate offset voltage (because of the following shifter)
+        Vdac= ( Vtarget + Vref ) / 2
+        print"  THRESHOLD setting:"
+        if channel==7:
+            print "\tCH: ALL"
+        else:
+            print "\tCH:", channel
+        print "\tTarget V:", Vtarget
+        dacValue = 0xFFFF * (Vdac / Vref)
+        DACtarget.writeDAC(int(dacValue), channel, verbose)
+
+    def packBits(self, raw_values):
+        packed_bits= 0
+        if (len(raw_values) != self.nChannels):
+            print "Error (packBits): wrong number of elements in array"
+        else:
+            for idx, iCh in enumerate(raw_values):
+                tmpint= iCh << idx*5
+                packed_bits= packed_bits | tmpint
+        print "\tPacked =", hex(packed_bits)
+        return packed_bits
+
+    def parseFifoData(self, fifoData, nEvents, mystruct, root_tree, verbose):
+        #for index in range(0, len(fifoData)-1, 6):
+        outList= []
+        for index in range(0, (nEvents)*6, 6):
+            word0= (fifoData[index] << 32) + fifoData[index + 1]
+            word1= (fifoData[index + 2] << 32) + fifoData[index + 3]
+            word2= (fifoData[index + 4] << 32) + fifoData[index + 5]
+            evType= (fifoData[index] & 0xF0000000) >> 28
+            inTrig= (fifoData[index] & 0x0FFF0000) >> 16
+            tStamp= ((fifoData[index] & 0x0000FFFF) << 32) + fifoData[index + 1]
+            fineTs= fifoData[index + 2]
+            evNum= fifoData[index + 3]
+            fineTsList=[-1]*12
+            fineTsList[3]= (fineTs & 0x000000FF)
+            fineTsList[2]= (fineTs & 0x0000FF00) >> 8
+            fineTsList[1]= (fineTs & 0x00FF0000) >> 16
+            fineTsList[0]= (fineTs & 0xFF000000) >> 24
+            fineTsList[7]= (fifoData[index + 4] & 0x000000FF)
+            fineTsList[6]= (fifoData[index + 4] & 0x0000FF00) >> 8
+            fineTsList[5]= (fifoData[index + 4] & 0x00FF0000) >> 16
+            fineTsList[4]= (fifoData[index + 4] & 0xFF000000) >> 24
+            fineTsList[11]= (fifoData[index + 5] & 0x000000FF)
+            fineTsList[10]= (fifoData[index + 5] & 0x0000FF00) >> 8
+            fineTsList[9]= (fifoData[index + 5] & 0x00FF0000) >> 16
+            fineTsList[8]= (fifoData[index + 5] & 0xFF000000) >> 24
+            if verbose:
+                print "====== EVENT", evNum, "================================================="
+                print "[", hex(word0), "]", "\t TYPE", hex(evType), "\t TRIGGER", hex(inTrig), "\t TIMESTAMP", (tStamp)
+                print "[",hex(word1), "]", "\tEV NUM", evNum, "\tFINETS[0,3]", hex(fineTs)
+                print "[",hex(word2), "]", "\tFINETS[4,11]", hex(word2)
+                print fineTsList
+            fineTsList.insert(0, tStamp)
+            fineTsList.insert(0, evNum)
+            if (root_tree != None):
+                highWord= word0
+                lowWord= word1
+                extWord= word2
+                timeStamp= tStamp
+                bufPos= 0
+                evtNumber= evNum
+                evtType= evType
+                trigsFired= inTrig
+                mystruct.raw0= fifoData[index]
+                mystruct.raw1= fifoData[index+1]
+                mystruct.raw2= fifoData[index+2]
+                mystruct.raw3= fifoData[index+3]
+                mystruct.raw4= fifoData[index+4]
+                mystruct.raw5= fifoData[index+5]
+                mystruct.evtNumber= evNum
+                mystruct.tluTimeStamp= tStamp
+                mystruct.tluEvtType= evType
+                mystruct.tluTrigFired= inTrig
+                root_tree.Fill()
+
+            outList.insert(len(outList), fineTsList)
+        #print "=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-="
+        #print "EN#\tCOARSE_TS\tFINE_TS0...FINE_TS11"
+        #pprint.pprint(outList)
+        return outList
+
+    def plotFifoData(self, outList):
+        import matplotlib.pyplot as plt
+        import numpy as np
+        import matplotlib.mlab as mlab
+
+        coarseColumn= [row[1] for row in outList]
+        fineColumn= [row[2] for row in outList]
+        timeStamp= [sum(x) for x in zip(coarseColumn, fineColumn)]
+        correctTs= [-1]*len(coarseColumn)
+        coarseVal= 0.000000025 #coarse time value (40 Mhz, 25 ns)
+        fineVal=   0.00000000078125 #fine time value (1280 MHz, 0.78125 ns)
+        for iTs in range(0, len(coarseColumn)):
+            correctTs[iTs]= coarseColumn[iTs]*coarseVal + fineColumn[iTs]*fineVal
+            #if iTs:
+                #print correctTs[iTs]-correctTs[iTs-1], "\t ", correctTs[iTs], "\t", coarseColumn[iTs], "\t", fineColumn[iTs]
+
+        xdiff = np.diff(correctTs)
+        np.all(xdiff[0] == xdiff)
+        P= 1000000000 #display in ns
+        nsDeltas = [x * P for x in xdiff]
+        #centerRange= np.mean(nsDeltas)
+        centerRange= 476
+        windowsns= 30
+        minRange= centerRange-windowsns
+        maxRange= centerRange+windowsns
+        plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+        #plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+        #plt.xlim((min(nsDeltas), max(nsDeltas)))
+        plt.xlabel('Time (ns)')
+        plt.ylabel('Entries')
+        plt.title('Histogram DeltaTime')
+        plt.grid(True)
+
+        #Superimpose Gauss
+        mean = np.mean(nsDeltas)
+        variance = np.var(nsDeltas)
+        sigma = np.sqrt(variance)
+        x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+        plt.plot(x, mlab.normpdf(x, mean, sigma))
+
+        #Display plot
+        plt.show()
+
+    def saveFifoData(self, outList):
+        import csv
+        with open("output.csv", "wb") as f:
+            writer = csv.writer(f)
+            writer.writerows(outList)
+
+##################################################################################################################################
+##################################################################################################################################
+    def acquire(self, mystruct, root_tree= None):
+        print "STARTING ACQUIRE LOOP"
+        print "Run#" , self.runN, "\n"
+        self.isRunning= True
+        index=0
+        while (self.isRunning == True):
+            eventFifoFillLevel= self.getFifoLevel(0)
+            nFifoWords= int(eventFifoFillLevel)
+            if (nFifoWords > 0):
+                fifoData= self.getFifoData(nFifoWords)
+                outList= self.parseFifoData(fifoData, nFifoWords/6, mystruct, root_tree, False)
+
+            time.sleep(0.1)
+            index= index + nFifoWords/6
+        print "STOPPING ACQUIRE LOOP:", index, "events collected"
+        return index
+
+    def configure(self, parsed_cfg):
+        print "\nTLU INITIALIZING..."
+        section_name= "Producer.fmctlu"
+
+        #READ CONTENT OF EPROM VIA I2C
+        self.getSN()
+
+        print "  Turning on software trigger veto"
+        cmd = int("0x1",16)
+        self.setTriggerVetoStatus(cmd)
+
+        # #Get Verbose setting
+        self.verbose= parsed_cfg.getint(section_name, "verbose")
+
+
+        # #SET DACs
+        self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold0"), 1, self.verbose)
+        self.writeThreshold(self.zeDAC1, parsed_cfg.getfloat(section_name, "DACThreshold1"), 0, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold2"), 3, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold3"), 2, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold4"), 1, self.verbose)
+        self.writeThreshold(self.zeDAC2, parsed_cfg.getfloat(section_name, "DACThreshold5"), 0, self.verbose)
+
+        #
+        # #ENABLE/DISABLE HDMI OUTPUTS
+        self.DUTOutputs(0, int(parsed_cfg.get(section_name, "HDMI1_set"), 16) , self.verbose)
+        self.DUTOutputs(1, int(parsed_cfg.get(section_name, "HDMI2_set"), 16) , self.verbose)
+        self.DUTOutputs(2, int(parsed_cfg.get(section_name, "HDMI3_set"), 16) , self.verbose)
+        self.DUTOutputs(3, int(parsed_cfg.get(section_name, "HDMI4_set"), 16) , self.verbose)
+
+        # #SELECT CLOCK SOURCE TO HDMI
+        self.DUTClkSrc(0, int(parsed_cfg.get(section_name, "HDMI1_clk"), 16) , self.verbose)
+        self.DUTClkSrc(1, int(parsed_cfg.get(section_name, "HDMI2_clk"), 16) , self.verbose)
+        self.DUTClkSrc(2, int(parsed_cfg.get(section_name, "HDMI3_clk"), 16) , self.verbose)
+        self.DUTClkSrc(3, int(parsed_cfg.get(section_name, "HDMI4_clk"), 16) , self.verbose)
+
+        # #ENABLE/DISABLE LEMO CLOCK OUTPUT
+        self.enableClkLEMO(parsed_cfg.getint(section_name, "LEMOclk"), False)
+
+        #
+        # #Check clock status
+        self.getClockStatus()
+
+        resetClocks = 0
+        resetSerdes = 0
+        resetCounters= 0
+        if resetClocks:
+            self.resetClocks()
+            self.getClockStatus()
+        if resetSerdes:
+            self.resetSerdes()
+        if resetCounters:
+	    self.resetCounters()
+
+        # # Get inputs status and counters
+        self.getChStatus()
+        self.getAllChannelsCounts()
+
+        # # Stop internal triggers until setup complete
+        cmd = int("0x0",16)
+        self.setInternalTrg(cmd)
+
+        # # Set the control voltages for the PMTs
+        PMT1_V= parsed_cfg.getfloat(section_name, "PMT1_V")
+        PMT2_V= parsed_cfg.getfloat(section_name, "PMT2_V")
+        PMT3_V= parsed_cfg.getfloat(section_name, "PMT3_V")
+        PMT4_V= parsed_cfg.getfloat(section_name, "PMT4_V")
+        self.pwdled.setVch(0, PMT1_V, True)
+        self.pwdled.setVch(1, PMT2_V, True)
+        self.pwdled.setVch(2, PMT3_V, True)
+        self.pwdled.setVch(3, PMT4_V, True)
+
+        # # Set pulse stretches
+        str0= parsed_cfg.getint(section_name, "in0_STR")
+        str1= parsed_cfg.getint(section_name, "in1_STR")
+        str2= parsed_cfg.getint(section_name, "in2_STR")
+        str3= parsed_cfg.getint(section_name, "in3_STR")
+        str4= parsed_cfg.getint(section_name, "in4_STR")
+        str5= parsed_cfg.getint(section_name, "in5_STR")
+        self.setPulseStretch([str0, str1, str2, str3, str4, str5])
+
+        # # Set pulse delays
+        del0= parsed_cfg.getint(section_name, "in0_DEL")
+        del1= parsed_cfg.getint(section_name, "in1_DEL")
+        del2= parsed_cfg.getint(section_name, "in2_DEL")
+        del3= parsed_cfg.getint(section_name, "in3_DEL")
+        del4= parsed_cfg.getint(section_name, "in4_DEL")
+        del5= parsed_cfg.getint(section_name, "in5_DEL")
+        self.setPulseDelay([del0, del1, del2, del3, del4, del5])
+
+        # # Set trigger pattern
+        triggerPattern_low= int(parsed_cfg.get(section_name, "trigMaskLo"), 16)
+        triggerPattern_high= int(parsed_cfg.get(section_name, "trigMaskHi"), 16)
+        self.setTrgPattern(triggerPattern_high, triggerPattern_low)
+
+        # # Set active DUTs
+        DUTMask= int(parsed_cfg.get(section_name, "DutMask"), 16)
+        self.setDUTmask(DUTMask)
+
+        # # Set mode (AIDA, EUDET)
+        DUTMode= int(parsed_cfg.get(section_name, "DUTMaskMode"), 16)
+        self.setMode(DUTMode)
+
+        # # Set modifier
+        modifier = int(parsed_cfg.get(section_name, "DUTMaskModeModifier"), 16)
+        self.setModeModifier(modifier)
+
+        # # Set veto shutter
+        setVetoShutters = int(parsed_cfg.get(section_name, "DUTIgnoreShutterVeto"), 16)
+        self.setVetoShutters(setVetoShutters)
+
+        # # Set veto by DUT
+        ignoreDUTBusy = int(parsed_cfg.get(section_name, "DUTIgnoreBusy"), 16)
+        self.setVetoDUT(ignoreDUTBusy)
+
+        print "  Check external veto:"
+        self.getExternalVeto()
+
+        # # Set trigger interval (use 0 to disable internal triggers)
+        triggerInterval= parsed_cfg.getint(section_name, "InternalTriggerFreq")
+        self.setInternalTrg(triggerInterval)
+
+        shutterSource  = int(parsed_cfg.get(section_name, "ShutterSource"), 16)
+        self.setShutterSource(shutterSource)
+
+        shutterControl = int(parsed_cfg.get(section_name, "ShutterControl"), 16)
+        self.setShutterControl(shutterControl)
+
+        shutterInternalInterval =  int(parsed_cfg.get(section_name, "InternalShutterInterval"), 10)
+        self.setShutterInternalInterval(shutterInternalInterval)
+
+        shutterOnTime = int(parsed_cfg.get(section_name, "ShutterOnTime"), 10)
+        self.setShutterOnTime(shutterOnTime)
+        
+        shutterVetoOffTime = int(parsed_cfg.get(section_name, "ShutterVetoOffTime"), 10)
+        self.setShutterVetoOffTime(shutterVetoOffTime)
+        
+        shutterOffTime = int(parsed_cfg.get(section_name, "ShutterOffTime"), 10)
+        self.setShutterOffTime(shutterOffTime)
+        
+        print "TLU INITIALIZED"
+
+##################################################################################################################################
+##################################################################################################################################
+    def start(self, logtimestamps=False, runN=0, mystruct= None, root_tree= None):
+        print "TLU STARTING..."
+        self.runN= runN
+
+        print "  FIFO RESET:"
+        FIFOcmd= 0x2
+        self.setFifoCSR(FIFOcmd)
+        eventFifoFillLevel= self.getFifoLevel()
+        #cmd = int("0x000",16)
+        #self.setInternalTrg(cmd)
+
+        if logtimestamps:
+            self.setRecordDataStatus(True)
+        else:
+            self.setRecordDataStatus(False)
+
+        # Pulse T0
+        #self.pulseT0()
+        self.setRunActive()
+
+        print "  Turning off software trigger veto"
+        self.setTriggerVetoStatus( int("0x0",16) )
+
+        print "TLU STARTED"
+
+        nEvents= self.acquire(mystruct, root_tree)
+        return
+
+
+##################################################################################################################################
+##################################################################################################################################
+    def stop(self, saveD= False, plotD= False):
+        print "TLU STOPPING..."
+
+        self.getPostVetoTrg()
+        eventFifoFillLevel= self.getFifoLevel()
+        self.getFifoFlags()
+        self.getFifoCSR()
+        print "  Turning on software trigger veto"
+        self.setTriggerVetoStatus( int("0x1",16) )
+
+        print "Turning off shutter (setting run inactive)"
+        self.setRunInactive()
+
+        nFifoWords= int(eventFifoFillLevel)
+        fifoData= self.getFifoData(nFifoWords)
+
+        outList= self.parseFifoData(fifoData, nFifoWords/6, None, None, True)
+        if saveD:
+            self.saveFifoData(outList)
+        if plotD:
+            self.plotFifoData(outList)
+        #outFile = open('./test.txt', 'w')
+        #for iData in range (0, 30):
+    	#    outFile.write("%s\n" % fifoData[iData])
+        #    print hex(fifoData[iData])
+        print "TLU STOPPED"
+        return
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml b/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml
new file mode 120000
index 0000000000000000000000000000000000000000..40fa0333de76c24acb42ac3b3eca426aa434851e
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml
@@ -0,0 +1 @@
+../addr_table/TLUaddrmap.xml
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml.old b/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml.old
new file mode 100644
index 0000000000000000000000000000000000000000..65fb5340f2155f8c5c92d96a2ef66d8dcb209d41
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/TLUaddrmap.xml.old
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/TLUconnection.xml b/AIDA_tlu/projects/TLU_v1e/scripts/TLUconnection.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fca67f50d932c760c77aa5553bfa983ca8fff249
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/TLUconnection.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="tlu" uri="ipbusudp-2.0://192.168.200.30:50001"
+   address_table="file://./TLUaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/initTLU.py b/AIDA_tlu/projects/TLU_v1e/scripts/initTLU.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/initTLU.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/initTLU_merged.py b/AIDA_tlu/projects/TLU_v1e/scripts/initTLU_merged.py
new file mode 100644
index 0000000000000000000000000000000000000000..eb1ae650c8df5060c77fcf06503d581cfee02b07
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/initTLU_merged.py
@@ -0,0 +1,184 @@
+#
+# Function to initialize TLU
+#
+# David Cussans, October 2015
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+import time
+
+def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
+
+    print "RESETTING FIFO"
+    pychipsBoard.write("EventFifoCSR",0x2)
+    eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
+    print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
+
+
+    if writeTimestamps:
+        print "ENABLING DATA RECORDING"
+        pychipsBoard.write("Enable_Record_Data",1)
+    else:
+        print "Disabling data recording"
+        pychipsBoard.write("Enable_Record_Data",0)
+
+    print "Pulsing T0"
+    pychipsBoard.write("PulseT0",1)
+
+    print "Turning off software trigger veto"
+    pychipsBoard.write("TriggerVetoW",0)
+
+    print "TLU is running"
+
+
+def stopTLU( uhalDevice , pychipsBoard ):
+
+    print "Turning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    print "TLU triggers are stopped"
+
+def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
+
+    print "SETTING UP AIDA TLU"
+
+    fwVersion = uhalDevice.getNode("version").read()
+    uhalDevice.dispatch()
+    print "\tVersion (uHAL)= " , hex(fwVersion)
+
+    print "\tTurning on software trigger veto"
+    pychipsBoard.write("TriggerVetoW",1)
+
+    # Check the bus for I2C devices
+    pychipsBoardi2c = FmcTluI2c(pychipsBoard)
+
+    print "\tScanning I2C bus:"
+    scanResults = pychipsBoardi2c.i2c_scan()
+    #print scanResults
+    print '\t', ', '.join(scanResults), '\n'
+
+    boardId = pychipsBoardi2c.get_serial_number()
+    print "\tFMC-TLU serial number= " , boardId
+
+    resetClocks = 0
+    resetSerdes = 0
+
+# set DACs to -200mV
+    print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
+    pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
+
+    clockStatus = pychipsBoard.read("LogicClocksCSR")
+    print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
+    assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
+
+    if resetClocks:
+        print "Resetting clocks"
+        pychipsBoard.write("LogicRst", 1 )
+
+        clockStatus = pychipsBoard.read("LogicClocksCSR")
+        print "Clock status after reset = " , hex(clockStatus)
+
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status = " , hex(inputStatus)
+
+    if resetSerdes:
+        pychipsBoard.write("SerdesRstW", 0x00000003 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after reset = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000004 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status during calibration = " , hex(inputStatus)
+
+        pychipsBoard.write("SerdesRstW", 0x00000000 )
+        inputStatus = pychipsBoard.read("SerdesRstR")
+        print "Input status after calibration = " , hex(inputStatus)
+
+
+    inputStatus = pychipsBoard.read("SerdesRstR")
+    print "\tINPUT STATUS= " , hex(inputStatus)
+
+    count0 = pychipsBoard.read("ThrCount0R")
+    print "\t  Count 0= " , count0
+
+    count1 = pychipsBoard.read("ThrCount1R")
+    print "\t  Count 1= " , count1
+
+    count2 = pychipsBoard.read("ThrCount2R")
+    print "\t  Count 2= " , count2
+
+    count3 = pychipsBoard.read("ThrCount3R")
+    print "\t  Count 3= " , count3
+
+# Stop internal triggers until setup complete
+    pychipsBoard.write("InternalTriggerIntervalW",0)
+
+    print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseStretchW",int(pulseStretch))
+    pulseStretchR = pychipsBoard.read("PulseStretchR")
+    print "\t  Pulse stretch read back as:", hex(pulseStretchR)
+ #   assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
+
+    print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
+    pychipsBoard.write("PulseDelayW",int(pulseDelay))
+    pulseDelayR = pychipsBoard.read("PulseDelayR")
+    print "\t  Pulse delay read back as:", hex(pulseDelayR)
+
+    print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word  " %(triggerPattern)
+    pychipsBoard.write("TriggerPatternW",int(triggerPattern))
+    triggerPatternR = pychipsBoard.read("TriggerPatternR")
+    print "\t  Trigger pattern read back as: 0x%08X " % (triggerPatternR)
+
+    print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
+    pychipsBoard.write("DUTMaskW",int(DUTMask))
+    DUTMaskR = pychipsBoard.read("DUTMaskR")
+    print "\t  DUTMask read back as:" , hex(DUTMaskR)
+
+    print "\tSETTING ALL DUTs IN AIDA MODE"
+    pychipsBoard.write("DUTInterfaceModeW", 0xFF)
+    DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
+    print "\t  DUT mode read back as:" , DUTInterfaceModeR
+
+    print "\tSET DUT MODE MODIFIER"
+    pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
+    DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
+    print "\t  DUT mode modifier read back as:" , DUTInterfaceModeModifierR
+
+    if listenForTelescopeShutter:
+        print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",0)
+    else:
+        print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
+        pychipsBoard.write("IgnoreShutterVetoW",1)
+    IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
+    print "\t  IgnoreShutterVeto read back as:" , IgnoreShutterVeto
+
+    print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
+    pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
+    IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
+    print "\t  IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+
+    print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
+    if triggerInterval == 0:
+        internalTriggerFreq = 0
+    else:
+        internalTriggerFreq = 160000.0/triggerInterval
+    print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
+    pychipsBoard.write("InternalTriggerIntervalW",triggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+    trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
+    print "\t  Trigger interval read back as:", trigIntervalR
+    print "AIDA TLU SETUP COMPLETED"
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/localClock.txt b/AIDA_tlu/projects/TLU_v1e/scripts/localClock.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0a7b2d94878a6766e41c9b39bfd4fa2a2ebc9e95
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/localClock.txt
@@ -0,0 +1,394 @@
+# Si538x/4x Registers Export
+# 
+# Part: Si5345
+# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
+# Design ID: TLU1E_01
+# Includes Pre/Post Download Control Register Writes: Yes
+# Die Revision: A2
+# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
+# Created On: 2017-08-24 13:37:41 GMT+01:00
+Address,Data
+0x0B24,0xD8
+0x0B25,0x00
+0x000B,0x68
+0x0016,0x02
+0x0017,0x1C
+0x0018,0x88
+0x0019,0xDD
+0x001A,0xDF
+0x002B,0x02
+0x002C,0x07
+0x002D,0x15
+0x002E,0x37
+0x002F,0x00
+0x0030,0x37
+0x0031,0x00
+0x0032,0x37
+0x0033,0x00
+0x0034,0x00
+0x0035,0x00
+0x0036,0x37
+0x0037,0x00
+0x0038,0x37
+0x0039,0x00
+0x003A,0x37
+0x003B,0x00
+0x003C,0x00
+0x003D,0x00
+0x003F,0x77
+0x0040,0x04
+0x0041,0x0C
+0x0042,0x0C
+0x0043,0x0C
+0x0044,0x00
+0x0045,0x0C
+0x0046,0x32
+0x0047,0x32
+0x0048,0x32
+0x0049,0x00
+0x004A,0x32
+0x004B,0x32
+0x004C,0x32
+0x004D,0x00
+0x004E,0x55
+0x004F,0x05
+0x0051,0x03
+0x0052,0x03
+0x0053,0x03
+0x0054,0x00
+0x0055,0x03
+0x0056,0x03
+0x0057,0x03
+0x0058,0x00
+0x0059,0x3F
+0x005A,0xCC
+0x005B,0xCC
+0x005C,0xCC
+0x005D,0x00
+0x005E,0xCC
+0x005F,0xCC
+0x0060,0xCC
+0x0061,0x00
+0x0062,0xCC
+0x0063,0xCC
+0x0064,0xCC
+0x0065,0x00
+0x0066,0x00
+0x0067,0x00
+0x0068,0x00
+0x0069,0x00
+0x0092,0x00
+0x0093,0x00
+0x0095,0x00
+0x0096,0x00
+0x0098,0x00
+0x009A,0x02
+0x009B,0x30
+0x009D,0x00
+0x009E,0x20
+0x00A0,0x00
+0x00A2,0x02
+0x00A8,0x89
+0x00A9,0x70
+0x00AA,0x07
+0x00AB,0x00
+0x00AC,0x00
+0x0102,0x01
+0x0108,0x06
+0x0109,0x09
+0x010A,0x33
+0x010B,0x00
+0x010D,0x06
+0x010E,0x09
+0x010F,0x33
+0x0110,0x00
+0x0112,0x06
+0x0113,0x09
+0x0114,0x33
+0x0115,0x00
+0x0117,0x06
+0x0118,0x09
+0x0119,0x33
+0x011A,0x00
+0x011C,0x06
+0x011D,0x09
+0x011E,0x33
+0x011F,0x00
+0x0121,0x06
+0x0122,0x09
+0x0123,0x33
+0x0124,0x00
+0x0126,0x06
+0x0127,0x09
+0x0128,0x33
+0x0129,0x00
+0x012B,0x06
+0x012C,0x09
+0x012D,0x33
+0x012E,0x00
+0x0130,0x06
+0x0131,0x09
+0x0132,0x33
+0x0133,0x00
+0x013A,0x01
+0x013B,0xCC
+0x013C,0x00
+0x013D,0x00
+0x013F,0x00
+0x0140,0x00
+0x0141,0x40
+0x0142,0xFF
+0x0202,0x00
+0x0203,0x00
+0x0204,0x00
+0x0205,0x00
+0x0206,0x00
+0x0208,0x14
+0x0209,0x00
+0x020A,0x00
+0x020B,0x00
+0x020C,0x00
+0x020D,0x00
+0x020E,0x01
+0x020F,0x00
+0x0210,0x00
+0x0211,0x00
+0x0212,0x14
+0x0213,0x00
+0x0214,0x00
+0x0215,0x00
+0x0216,0x00
+0x0217,0x00
+0x0218,0x01
+0x0219,0x00
+0x021A,0x00
+0x021B,0x00
+0x021C,0x14
+0x021D,0x00
+0x021E,0x00
+0x021F,0x00
+0x0220,0x00
+0x0221,0x00
+0x0222,0x01
+0x0223,0x00
+0x0224,0x00
+0x0225,0x00
+0x0226,0x00
+0x0227,0x00
+0x0228,0x00
+0x0229,0x00
+0x022A,0x00
+0x022B,0x00
+0x022C,0x00
+0x022D,0x00
+0x022E,0x00
+0x022F,0x00
+0x0231,0x01
+0x0232,0x01
+0x0233,0x01
+0x0234,0x01
+0x0235,0x00
+0x0236,0x00
+0x0237,0x00
+0x0238,0x00
+0x0239,0xA9
+0x023A,0x00
+0x023B,0x00
+0x023C,0x00
+0x023D,0x00
+0x023E,0xA0
+0x024A,0x00
+0x024B,0x00
+0x024C,0x00
+0x024D,0x00
+0x024E,0x00
+0x024F,0x00
+0x0250,0x00
+0x0251,0x00
+0x0252,0x00
+0x0253,0x00
+0x0254,0x00
+0x0255,0x00
+0x0256,0x00
+0x0257,0x00
+0x0258,0x00
+0x0259,0x00
+0x025A,0x00
+0x025B,0x00
+0x025C,0x00
+0x025D,0x00
+0x025E,0x00
+0x025F,0x00
+0x0260,0x00
+0x0261,0x00
+0x0262,0x00
+0x0263,0x00
+0x0264,0x00
+0x0268,0x00
+0x0269,0x00
+0x026A,0x00
+0x026B,0x54
+0x026C,0x4C
+0x026D,0x55
+0x026E,0x31
+0x026F,0x45
+0x0270,0x5F
+0x0271,0x30
+0x0272,0x31
+0x0302,0x00
+0x0303,0x00
+0x0304,0x00
+0x0305,0x80
+0x0306,0x54
+0x0307,0x00
+0x0308,0x00
+0x0309,0x00
+0x030A,0x00
+0x030B,0x80
+0x030C,0x00
+0x030D,0x00
+0x030E,0x00
+0x030F,0x00
+0x0310,0x00
+0x0311,0x00
+0x0312,0x00
+0x0313,0x00
+0x0314,0x00
+0x0315,0x00
+0x0316,0x00
+0x0317,0x00
+0x0318,0x00
+0x0319,0x00
+0x031A,0x00
+0x031B,0x00
+0x031C,0x00
+0x031D,0x00
+0x031E,0x00
+0x031F,0x00
+0x0320,0x00
+0x0321,0x00
+0x0322,0x00
+0x0323,0x00
+0x0324,0x00
+0x0325,0x00
+0x0326,0x00
+0x0327,0x00
+0x0328,0x00
+0x0329,0x00
+0x032A,0x00
+0x032B,0x00
+0x032C,0x00
+0x032D,0x00
+0x032E,0x00
+0x032F,0x00
+0x0330,0x00
+0x0331,0x00
+0x0332,0x00
+0x0333,0x00
+0x0334,0x00
+0x0335,0x00
+0x0336,0x00
+0x0337,0x00
+0x0338,0x00
+0x0339,0x1F
+0x033B,0x00
+0x033C,0x00
+0x033D,0x00
+0x033E,0x00
+0x033F,0x00
+0x0340,0x00
+0x0341,0x00
+0x0342,0x00
+0x0343,0x00
+0x0344,0x00
+0x0345,0x00
+0x0346,0x00
+0x0347,0x00
+0x0348,0x00
+0x0349,0x00
+0x034A,0x00
+0x034B,0x00
+0x034C,0x00
+0x034D,0x00
+0x034E,0x00
+0x034F,0x00
+0x0350,0x00
+0x0351,0x00
+0x0352,0x00
+0x0353,0x00
+0x0354,0x00
+0x0355,0x00
+0x0356,0x00
+0x0357,0x00
+0x0358,0x00
+0x0359,0x00
+0x035A,0x00
+0x035B,0x00
+0x035C,0x00
+0x035D,0x00
+0x035E,0x00
+0x035F,0x00
+0x0360,0x00
+0x0361,0x00
+0x0362,0x00
+0x0487,0x00
+0x0502,0x01
+0x0508,0x14
+0x0509,0x23
+0x050A,0x0C
+0x050B,0x0B
+0x050C,0x03
+0x050D,0x3F
+0x050E,0x17
+0x050F,0x2B
+0x0510,0x09
+0x0511,0x08
+0x0512,0x03
+0x0513,0x3F
+0x0515,0x00
+0x0516,0x00
+0x0517,0x00
+0x0518,0x00
+0x0519,0xA4
+0x051A,0x02
+0x051B,0x00
+0x051C,0x00
+0x051D,0x00
+0x051E,0x00
+0x051F,0x80
+0x0521,0x21
+0x052A,0x05
+0x052B,0x01
+0x052C,0x0F
+0x052D,0x03
+0x052E,0x19
+0x052F,0x19
+0x0531,0x00
+0x0532,0x42
+0x0533,0x03
+0x0534,0x00
+0x0535,0x00
+0x0536,0x08
+0x0537,0x00
+0x0538,0x00
+0x0539,0x00
+0x0802,0x35
+0x0803,0x05
+0x0804,0x00
+0x090E,0x02
+0x0943,0x00
+0x0949,0x07
+0x094A,0x07
+0x0A02,0x00
+0x0A03,0x01
+0x0A04,0x01
+0x0A05,0x01
+0x0B44,0x2F
+0x0B46,0x00
+0x0B47,0x00
+0x0B48,0x08
+0x0B4A,0x1E
+0x0514,0x01
+0x001C,0x01
+0x0B24,0xDB
+0x0B25,0x02
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/localConf.conf b/AIDA_tlu/projects/TLU_v1e/scripts/localConf.conf
new file mode 100644
index 0000000000000000000000000000000000000000..c3c6038235387f2898f0d086ea198b6fc28480fb
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/localConf.conf
@@ -0,0 +1,101 @@
+[Producer.fmctlu]
+verbose= 1
+confid= 20170626
+delayStart= 1000
+
+# HDMI pin direction:
+# 4-bits to determine direction of HDMI pins
+# 1-bit for the clock pair
+# 0= pins are not driving signals, 1 pins drive signals (outputs)
+HDMI1_set= 0x7
+HDMI2_set= 0x7
+HDMI3_set= 0x7
+HDMI4_set= 0x7
+HDMI1_clk = 1
+HDMI2_clk = 1
+HDMI3_clk = 1
+HDMI4_clk = 1
+
+# Control voltages for the PMTs				      <
+PMT1_V= 0.5
+PMT2_V= 0.7
+PMT3_V= 0.9
+PMT4_V= 1
+
+
+# Enable/disable differential LEMO CLOCK
+LEMOclk = 1
+
+# Set delay and stretch for trigger pulses
+in0_STR = 1
+in0_DEL = 0
+in1_STR = 1
+in1_DEL = 0
+in2_STR = 1
+in2_DEL = 0
+in3_STR = 1
+in3_DEL = 0
+in4_STR = 1
+in4_DEL = 0
+in5_STR = 1
+in5_DEL = 0
+#
+trigMaskHi = 0x00000000
+trigMaskLo = 0x00000002
+#
+#### DAC THRESHOLD
+DACThreshold0 = -0.12
+DACThreshold1 = -0.12
+DACThreshold2 = -0.12
+DACThreshold3 = -0.12
+DACThreshold4 = -0.12
+DACThreshold5 = -0.12
+
+# Define which DUTs are ON
+DutMask = 0xF
+
+# Define mode of DUT (00 EUDET, 11 AIDA)
+DUTMaskMode= 0xFFFFFFFF
+
+# Allow asynchronous veto
+DUTMaskModeModifier= 0x0
+
+# Ignore busy from a specific DUT
+DUTIgnoreBusy = 0xF
+
+# Ignore the SHUTTER veto 
+DUTIgnoreShutterVeto = 0x0
+
+# Generate internal triggers (in Hz, 0= no triggers)
+InternalTriggerFreq = 1000000
+#InternalTriggerFreq = 0
+
+# Bit-0 of shutter control = enable shutter. Bit-1 = enable internal shutter generator
+ShutterControl = 3
+
+ShutterSource = 5
+InternalShutterInterval = 1024
+ShutterOnTime = 200
+ShutterVetoOffTime = 300
+ShutterOffTime = 400
+
+[LogCollector.log]
+# Currently, all LogCollectors have a hardcoded runtime name: log
+# nothing
+
+
+[DataCollector.my_dc]
+EUDAQ_MON=my_mon
+# send assambled event to the monitor with runtime name my_mon;
+EUDAQ_FW=native
+# the format of data file
+EUDAQ_FW_PATTERN=$12D_run$6R$X
+# the name pattern of data file
+# the $12D will be converted a data/time string with 12 digits.
+# the $6R will be converted a run number string with 6 digits.
+# the $X will be converted the suffix name of data file.
+
+[Monitor.my_mon]
+EX0_ENABLE_PRINT=0
+EX0_ENABLE_STD_PRINT=0
+EX0_ENABLE_STD_CONVERTER=1
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/localIni.ini b/AIDA_tlu/projects/TLU_v1e/scripts/localIni.ini
new file mode 100644
index 0000000000000000000000000000000000000000..d703b9fe8eaa8aed8cd7d300ddab194e1840444e
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/localIni.ini
@@ -0,0 +1,52 @@
+[Producer.fmctlu]
+initid= 20170703
+verbose = 1
+ConnectionFile= "file://./../user/eudet/misc/fmctlu_connection.xml"
+DeviceName="fmctlu.udp"
+TLUmod= "1e"
+# number of HDMI inputs, leave 4 even if you only use fewer inputs
+nDUTs = 4
+nTrgIn = 6
+# 0= False (Internal Reference OFF), 1= True
+intRefOn = 0
+VRefInt = 2.5
+VRefExt = 1.3
+# I2C address of the bus expander on Enclustra FPGA
+I2C_COREEXP_Addr = 0x21
+# I2C address of the Si5345
+I2C_CLK_Addr = 0x68
+# I2C address of 1st AD5665R
+I2C_DAC1_Addr = 0x13
+# I2C address of 2nd AD5665R
+I2C_DAC2_Addr = 0x1F
+# address of unique Id number EEPROM
+I2C_ID_Addr = 0x50
+#I2C address of 1st expander PCA9539PW
+I2C_EXP1_Addr = 0x74
+#I2C address of 2st expander PCA9539PW
+I2C_EXP2_Addr = 0x75
+#I2C address of AD5665R on powermodule
+I2C_DACModule_Addr = 0x1C
+# Max value for control voltage on PMTs (usually 1 V)
+PMT_vCtrlMax= 1.0
+#I2C address of 1st expander PCA9539PW on powermodule
+I2C_EXP1Module_Addr = 0x76
+#I2C address of 2nd expander PCA9539PW on powermodule
+I2C_EXP2Module_Addr = 0x77
+
+
+##CONFCLOCK 0= skip clock configuration, 1= configure si5345
+CONFCLOCK= 1
+CLOCK_CFG_FILE = ./localClock.txt
+
+
+[LogCollector.log]
+# Currently, all LogCollectors have a hardcoded runtime name: log
+EULOG_GUI_LOG_FILE_PATTERN = myexample_$12D.log
+# the $12D will be converted a data/time string with 12 digits.
+
+[DataCollector.my_dc]
+# nothing
+
+[Monitor.my_mon]
+# nothing
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/AD5665R.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/AD5665R.py
new file mode 100644
index 0000000000000000000000000000000000000000..6ce206d1cf01c009554cdee1291326455b49cfa4
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/AD5665R.py
@@ -0,0 +1,46 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+
+class AD5665R:
+    #Class to configure the DAC modules
+
+    def __init__(self, i2c, slaveaddr=0x1F):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def setIntRef(self, intRef=False, verbose=False):
+        mystop=True
+        if intRef:
+            cmdDAC= [0x38,0x00,0x01]
+        else:
+            cmdDAC= [0x38,0x00,0x00]
+        self.i2c.write( self.slaveaddr, cmdDAC, mystop)
+        if verbose:
+            print "  AD5665R"
+            print "\tDAC int ref:", intRef
+
+
+    def writeDAC(self, dacCode, channel, verbose=False):
+        #Vtarget is the required voltage, channel is the DAC channel to target
+        #intRef indicates whether to use the external voltage reference (True)
+        #or the internal one (False).
+
+        print "\tDAC value:"  , hex(dacCode)
+        if channel<0 or channel>7:
+            print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            return -1
+        if dacCode<0:
+            print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
+            dacCode=0
+        elif dacCode>0xFFFF :
+            print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
+            dacCode=0xFFFF
+
+        sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+        print "\tWriting DAC string:", sequence
+        mystop= False
+        self.i2c.write( self.slaveaddr, sequence, mystop)
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/ADN2814ACPZ.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/ADN2814ACPZ.py
new file mode 100644
index 0000000000000000000000000000000000000000..31b3dc6d40aa398799d8b546773649b94f99ac91
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/ADN2814ACPZ.py
@@ -0,0 +1,144 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+import math
+
+class ADN2814ACPZ:
+    #Class to configure the ADN2814 clock and data recovery chip (CDR)
+    # The I2C address can either be 0x40 or 0x60
+
+    def __init__(self, i2c, slaveaddr=0x40):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+        self.regDictionary= {'freq0': 0x0, 'freq1': 0x1, 'freq2': 0x2, 'rate': 0x3, 'misc': 0x4, 'ctrla': 0x8, 'ctrlb': 0x9, 'ctrlc': 0x11}
+
+    def writeReg(self, regN, regContent, verbose=False):
+        #Basic functionality to write to register.
+        regContent= regContent & 0xFF
+        mystop=True
+        cmd= [regN, regContent]
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+
+    def readReg(self, regN, nwords, verbose=False):
+        #Basic functionality to read from register.
+        mystop=False
+        self.i2c.write( self.slaveaddr, [regN], mystop)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+
+    def readf0(self, verbose=False):
+        res= self.readReg(self.regDictionary['freq0'], 1, False)
+        if verbose:
+            print "\tfreq0 is", res[0]
+        return res[0]
+
+    def readf1(self, verbose=False):
+        res= self.readReg(self.regDictionary['freq1'], 1, False)
+        if verbose:
+            print "\tfreq1 is", res[0]
+        return res[0]
+
+    def readf2(self, verbose=False):
+        res= self.readReg(self.regDictionary['freq2'], 1, False)
+        if verbose:
+            print "\tfreq2 is", res[0]
+        return res[0]
+
+    def readFrequency(self, verbose=False):
+        # write 1 to CTRLA[1]
+        # reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]
+        # read back MISC[2], if 0 the measurement is not complete (typ 80 ms). If 1 the data rate can be read by reading FREQ[22:0]
+        # read FREQ2, FREQ1, FREQ0
+        # rate= (FREQ[22:0]xFrefclk)/2^(14+SEL_RATE)
+
+        return
+
+    def readLOLstatus(self, verbose=False):
+        # return the status of the LOL bit MISC[3] and the STATIC LOL MISC[4]
+        # the STATIC LOL is asserted if a LOL condition occurred and remains asserted
+        # until cleared by writing 1 followed by 0 to the CTRLB[6] bit
+        misc= self.readReg(self.regDictionary['misc'], 1, False)[0]
+        staticLOL= (misc & 0x10000) >> 4
+        LOL= (misc & 0x1000) >> 3
+        if verbose:
+            print "MISC=", misc, "LOL=", LOL, "StaticLOL=", staticLOL
+        return [LOL, staticLOL]
+
+    def readRate(self, verbose=False):
+        rate_msb= self.readReg(self.regDictionary['rate'], 1, False)[0]
+        rate_lsb= self.readReg(self.regDictionary['misc'], 1, False)[0]
+        rate_lsb= 0x1 & rate_lsb
+        rate= (rate_msb << 1) | rate_lsb
+        if verbose:
+            print "\tcoarse rate is", rate
+        return rate
+
+    def _writeCTRLA(self, fRef, dataRatio, measureDataRate, lockToRef, verbose=False):
+        #write content to register CTRLA:
+        # fRef: reference frequency in MHz; range is [10 : 160]
+        # dataRatio: integer in range [0 : 8] equal to Data Rate/Div_FREF Ratio
+        # measureDataRate: set to 1 to measure data rate
+        # lockToRef= 0 > lock to input data; 1 > lock to reference clock
+        regContent= 0x0
+        if fRef < 10:
+            print "fRef must be comprised between 10 and 160. Coherced to 10"
+            fRef = 10
+        if fRef > 160:
+            print "fRef must be comprised between 10 and 160. Coherced to 160"
+            fRef = 160
+        fRefRange={
+           10<= fRef <20 : 0x00,
+           20<= fRef <40 : 0x01,
+           40<= fRef <80 : 0x02,
+           80<= fRef <=160 : 0x03,
+           }[1]
+        fRefRange= fRefRange << 6
+        regContent= regContent | fRefRange
+
+        if ((1 <= dataRatio <= 256) & (isinstance(dataRatio, (int, long) )) ):
+            ratioValue= math.log(dataRatio, 2)
+            ratioValue= int(ratioValue)
+        else:
+            print "  dataRatio should be an integer in the form 2^n with 0<= n <= 8. Coherced to 0"
+            ratioValue= 0
+        if verbose:
+            print "\tratioValue=", ratioValue
+        ratioValue = ratioValue << 2
+        regContent= regContent | ratioValue
+
+        measureDataRate= (measureDataRate & 0x1) << 1
+        lockToRef= lockToRef & 0x1
+        regContent= regContent | measureDataRate | lockToRef
+
+        self.writeReg( self.regDictionary['ctrla'], regContent, verbose=False)
+        return
+
+    def _writeCTRLB(self, confLOL, rstMisc4, systemReset, rstMisc2, verbose=False):
+        #write content to register CTRLB:
+        # confLOL=0 > LOL pin normal operation; 1 > LOL pin is static LOL
+        # rstMisc4= Write a 1 followed by 0 to reset MISC[4] (staticLOL)
+        # systemReset= Write 1 followed by 0 to reset ADN2814
+        # rsttMisc2= Write a 1 followed by 0 to reset MISC[2] (data read measure complete)
+        regContent= 0x0
+        confLOL= (confLOL & 0x1) << 7
+        rstMisc4= (rstMisc4 & 0x1) << 6
+        systemReset= (systemReset & 0x1) << 5
+        rstMisc2= (rstMisc2 & 0x1) << 3
+        regContent= regContent | confLOL | rstMisc4 | systemReset | rstMisc2
+        self.writeReg( self.regDictionary['ctrlb'], regContent, verbose=False)
+        return
+
+    def _writeCTRLC(self, confLOS, squelch, outBoost, verbose=False):
+        #write content to register CTRLC:
+        # confLOS= 0 > active high LOS; 1 > active low LOS
+        # squelch= 0 > squelch CLK and DATA; 1 > squelch CLK or DATA
+        # outBoost= 0 > default swing; boost output swing
+        regContent= 0x0
+        confLOS= (confLOS & 0x1) << 2
+        squelch= (squelch & 0x1) << 1
+        outBoost= (outBoost & 0x1)
+        regContent= regContent | confLOS | squelch | outBoost
+        self.writeReg( self.regDictionary['ctrlc'], regContent, verbose=False)
+        return
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/ATSHA204A.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/ATSHA204A.py
new file mode 100644
index 0000000000000000000000000000000000000000..8bf9fc09559acbd2eef36bfffef850b2a6b08f7c
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/ATSHA204A.py
@@ -0,0 +1,115 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+import numpy as np
+
+
+class ATSHA204A:
+    #Class for Atmel ATSHA204A eeprom
+
+    def __init__(self, i2c, slaveaddr= 0x64):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    #Slot size, in bytes.
+        self.SLOT_SIZE_BYTES = 32;
+    #Word size, in bytes. This is the base unit for all reads and writes.
+        self.WORD_SIZE_BYTES = 4;
+    #Maximum word offset per slot
+        self.MAX_WORD_OFFSET = 7;
+    #Size of the configuration zone, in bytes
+        self.CONFIGURATION_ZONE_SIZE_BYTES = 88;
+    #Number of slots in the configuration zone
+        self.CONFIGURATION_ZONE_SIZE_SLOTS = 3;
+    #Slot 3 in the configuration zone is only 24 bytes rather than 32, so the max word offset is limited to 5.
+        self.CONFIGURATION_ZONE_SLOT_2_MAX_WORD_OFFSET = 5;
+    #Size of the OTP zone, in bytes
+        self.OTP_ZONE_SIZE_BYTES = 64;
+    #Number of slots in the OTP zone
+        self.OTP_ZONE_SIZE_SLOTS = 2;
+    #Size of the data zone, in bytes
+        self.DATA_ZONE_SIZE_BYTES = 512;
+    #Number of slots in the data zone
+        self.DATA_ZONE_SIZE_SLOTS = 16;
+    #The data slot used for module configuration data
+        self.DATA_ZONE_SLOT_MODULE_CONFIGURATION = 0;
+    #Byte index of the OTP mode byte within its configuration word.
+        self.OTP_MODE_WORD_BYTE_INDEX = 2;
+
+#-------------------------------------------------------------------------------------------------
+# Command packets and I/O
+#-------------------------------------------------------------------------------------------------
+    #Command execution status response block size
+        self.STATUS_RESPONSE_BLOCK_SIZE_BYTES = 4;
+    #Byte index of count in response block
+        self.STATUS_RESPONSE_COUNT_BYTE_INDEX = 0;
+    #Byte index of status code in response block
+        self.STATUS_RESPONSE_STATUS_BYTE_INDEX = 1;
+    #Checksum size
+        self.CHECKSUM_LENGTH_BYTES = 2;
+    #Index of the count byte in a command packet
+        self.COMMAND_PACKET_COUNT_BYTE_INDEX = 0;
+    #Size of count in a command packet
+        self.COMMAND_PACKET_COUNT_SIZE_BYTES = 1;
+    #Index of the opcode byte in a command packet
+        self.COMMAND_PACKET_OPCODE_BYTE_INDEX = 1;
+    #Size of the opcode byte in a command packet
+        self.COMMAND_PACKET_OPCODE_LENGTH_BYTES = 1;
+    #Index of param 1 in a command packet
+        self.COMMAND_PACKET_PARAM1_BYTE_INDEX = 2;
+    #Size of param 1 in a command packet
+        self.COMMAND_PACKET_PARAM1_SIZE_BYTES = 1;
+    #Index of param 2 in a command packet
+        self.COMMAND_PACKET_PARAM2_BYTE_INDEX = 3;
+    #Size of param 2 in a command packet
+        self.COMMAND_PACKET_PARAM2_SIZE_BYTES = 2;
+
+    def _CalculateCrc(self, pData, dataLengthBytes):
+        # Calculate a CRC-16 used when communicating with the device. Code taken from Atmel's library.
+        #The Atmel documentation only specifies that the CRC algorithm used on the ATSHA204A is CRC-16 with polynomial
+        #0x8005; compared to a standard CRC-16, however, the used algorithm doesn't use remainder reflection.
+        #@param pData				The data to calculate the CRC for
+        #@param dataLengthBytes	The number of bytes to process
+        #@return					The CRC
+        polynomial = 0x8005
+        crcRegister = 0
+        if not pData:
+            print "_CalculateCrc: No data to process"
+            return 0
+        for counter in range(0, dataLengthBytes):
+            shiftRegister= 0x01
+            for iShift in range(0, 8):
+                if (pData[counter] & shiftRegister) :
+                    dataBit= 1
+                else:
+                    dataBit=0
+                crcBit= ((crcRegister) >> 15)
+                crcRegister <<= 1
+                crcRegister= crcRegister & 0xffff
+                #print shiftRegister, "\t", dataBit, "\t", crcBit, "\t", crcRegister
+                shiftRegister=  shiftRegister << 1
+                if (dataBit != crcBit):
+                    #print "poly"
+                    crcRegister ^= polynomial;
+        return crcRegister
+
+    def _wake(self, verifyDeviceIsAtmelAtsha204a, debug):
+        dummyWriteData = 0x00
+        mystop=True
+        self.i2c.write( self.slaveaddr, [dummyWriteData], mystop)
+
+        if (verifyDeviceIsAtmelAtsha204a):
+            expectedStatusBlock= [ 0x04, 0x11, 0x33, 0x43 ];
+            nwords= 4
+            res= self.i2c.read( self.slaveaddr, nwords)
+            if (res != expectedStatusBlock):
+                print "Attempt to awake Atmel ATSHA204A failed"
+            print res
+
+    def _GetCommandPacketSize(self, additionalDataLengthBytes):
+        packetSizeBytes = self.COMMAND_PACKET_COUNT_SIZE_BYTES + self.COMMAND_PACKET_OPCODE_LENGTH_BYTES  \
+                          + self.COMMAND_PACKET_PARAM1_SIZE_BYTES + self.COMMAND_PACKET_PARAM2_SIZE_BYTES \
+                          + additionalDataLengthBytes + self.CHECKSUM_LENGTH_BYTES;
+
+        return packetSizeBytes
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/E24AA025E48T.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/E24AA025E48T.py
new file mode 100644
index 0000000000000000000000000000000000000000..32cc429c6310b7cd25bf4bc43092a66c04e43714
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/E24AA025E48T.py
@@ -0,0 +1,20 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class E24AA025E48T:
+    #Class to configure the EEPROM
+
+    def __init__(self, i2c, slaveaddr=0x50):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def readEEPROM(self, startadd, nBytes):
+        #Read EEPROM memory locations
+        mystop= False
+        myaddr= [startadd]#0xfa
+        self.i2c.write( self.slaveaddr, [startadd], mystop)
+        res= self.i2c.read( self.slaveaddr, nBytes)
+        return res
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/FmcTluI2c.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/FmcTluI2c.py
new file mode 100644
index 0000000000000000000000000000000000000000..04bf5985fbde260c2668c587628b8919f8080508
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/FmcTluI2c.py
@@ -0,0 +1,132 @@
+import time
+#from PyChipsUser import *
+from I2cBusProperties import *
+from RawI2cAccess import *
+
+
+class FmcTluI2c:
+
+
+    ############################
+    ### configure i2c connection
+    ############################
+    def __init__(self,board):
+        self.board = board
+        i2cClockPrescale = 0x30
+        self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
+        return
+
+
+    ##########################
+    ### scan all i2c addresses
+    ##########################
+    def i2c_scan(self):
+        list=[]
+        for islave in range(128):
+            i2cscan = RawI2cAccess(self.i2cBusProps, islave)
+            try:
+                i2cscan.write([0x00])
+                device="slave address "+hex(islave)+" "
+                if islave==0x1f:
+                    device+="(DAC)"
+                elif islave==0x50:
+                    device+="(serial number PROM)"
+                elif islave>=0x54 and islave<=0x57:
+                    device+="(sp601 onboard EEPROM)"
+                else:
+                    device+="(???)"
+                    pass
+                list.append(device)
+                pass
+            except:
+                pass
+            pass
+        return list
+
+
+    ###################
+    ### write to EEPROM
+    ###################
+    def eeprom_write(self,address,value):
+        if address<0 or address>127:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        if value<0 or value>255:
+            print "eeprom_write ERROR: value",value,"not in range 0-255"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address,value])
+        time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
+        return
+
+
+    ####################
+    ### read from EEPROM
+    ####################
+    def eeprom_read(self,address):
+        if address<0 or address>255:
+            print "eeprom_write ERROR: address",address,"not in range 0-127"
+            return
+        i2cSlaveAddr = 0x50   # seven bit address, binary 1010000
+        prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+        prom.write([address])
+        return prom.read(1)[0]
+
+
+    ######################
+    ### read serial number
+    ######################
+    def get_serial_number(self):
+        result=""
+        for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
+            result+="%02x "%(self.eeprom_read(iaddr))
+            pass
+        return result
+
+
+    #################
+    ### set DAC value
+    #################
+    def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+        if channel<0 or channel>7:
+            print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+            return -1
+        if value<0 or value>0xFFFF:
+            print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
+            return -1
+        # AD5665R chip with A0,A1 tied to ground
+        #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+        print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+        dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+        # if we want to enable internal voltage reference:
+        if vrefOn:
+            # enter vref-on mode:
+	    print "Turning internal reference ON"
+            dac.write([0x38,0x00,0x01])
+        else:
+	    print "Turning internal reference OFF"
+            dac.write([0x38,0x00,0x00])
+        # now set the actual value
+        sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
+        print sequence
+        dac.write(sequence)
+
+
+
+    ##################################################
+    ### convert required threshold voltage to DAC code
+    ##################################################
+    def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+        Vdaq = ( desiredVoltage + Vref ) / 2
+        dacCode = 0xFFFF * Vdaq / Vref
+        return int(dacCode)
+
+
+    ##################################################
+    ### calculate the DAC code required and set DAC
+    ##################################################
+    def set_threshold_voltage(self, channel , voltage ):
+        dacCode = self.convert_voltage_to_dac(voltage)
+        print " requested voltage, calculated DAC code = " , voltage , dacCode
+        self.set_dac(channel , dacCode)
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CDISP.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CDISP.py
new file mode 100644
index 0000000000000000000000000000000000000000..78650951117f88b44de22bd10a0b6e892a3d5740
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CDISP.py
@@ -0,0 +1,103 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal2 import I2CCore
+import StringIO
+import time
+
+class CFA632:
+    #Class to configure the CFA632 display
+
+    def __init__(self, i2c, slaveaddr=0x2A):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    def test(self):
+        print "Testing the display"
+        return
+    
+    def writeSomething(self, i2ccmd):
+        mystop= True
+        print "Write to CFA632"
+        print "\t", i2ccmd
+        #myaddr= [int(i2ccmd)]
+        self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+	return
+	
+class LCD09052:
+    #Class to configure the LCD09052 display
+
+    def __init__(self, i2c, slaveaddr=0x3A):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    def test(self):
+        print "\tTesting display (LCD09052)"
+        self.clear()
+        self.setBrightness(0)
+        time.sleep(0.2)
+        self.setBrightness(250)
+        time.sleep(0.2)
+        self.setBrightness(0)
+        time.sleep(0.2)
+        self.setBrightness(250)
+        for ipos in range(1, 18):
+            self.writeChar(33)
+            self.posCursor(1, ipos-1)
+            time.sleep(0.1)
+            self.writeChar(254)
+        self.posCursor(2, 1)
+        for ipos in range(1, 18):
+            self.writeChar(33)
+            self.posCursor(2, ipos-1)
+            time.sleep(0.1)
+            self.writeChar(254)
+        return
+        
+    def clear(self):
+    ### Clears the display and locates the curson on position (1,1), i.e. top left
+        i2ccmd= [4]
+        mystop= True
+        self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+        
+    def posCursor(self, line, pos):
+    ### Position the cursor on a specific location
+    ##  line can be 1 (top) or 2 (bottom)
+    ##  pos can be [1, 16}
+        if ((line==1) or (line==2) and (1 <= pos <= 16)):
+            i2ccmd= [2, line, pos]
+            mystop= True
+            self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+        else:
+            print "Cursor line can only be 1 or 2, position must be in range [1, 16]"
+    
+    
+    def setBrightness(self, value= 250):
+    ### Sets the brightness level of the backlight.
+    ##  Value is an integer in range [0, 250]. 0= no light, 250= maximum light.
+        if value < 0:
+            print "setBrightness: minimum value= 0. Coherced to 0"
+            value = 0
+        if value > 250:
+            print "setBrightness: maximum value= 250. Coherced to 250"
+            value = 250
+        i2ccmd= [7, value]
+        mystop= True
+        self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+        
+    
+    def writeChar(self, value):
+    ### Writes a char in the current cursor position
+    ##  The curso is then shifted right one position
+    ##  value must be an integer corresponding to the ascii code of the character
+        i2ccmd= [1, value]
+        mystop= True
+        self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+    
+    def writeSomething(self, i2ccmd):
+        mystop= True
+        print "Write to LCD09052"
+        print "\t", i2ccmd
+        #myaddr= [int(i2ccmd)]
+        self.i2c.write( self.slaveaddr, i2ccmd, mystop)
+	return
+
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal.py
new file mode 100644
index 0000000000000000000000000000000000000000..2729219e9dcdfb343d22462b817bec4bc317ce92
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal.py
@@ -0,0 +1,281 @@
+# -*- coding: utf-8 -*-
+"""
+
+"""
+
+import time
+
+import uhal
+
+verbose = True
+
+
+
+################################################################################
+# /*
+#        I2C CORE
+# */
+################################################################################
+
+
+
+
+class I2CCore:
+    """I2C communication block."""
+
+    # Define bits in cmd_stat register
+    startcmd = 0x1 << 7
+    stopcmd = 0x1 << 6
+    readcmd = 0x1 << 5
+    writecmd = 0x1 << 4
+    ack = 0x1 << 3
+    intack = 0x1
+
+    recvdack = 0x1 << 7
+    busy = 0x1 << 6
+    arblost = 0x1 << 5
+    inprogress = 0x1 << 1
+    interrupt = 0x1
+
+    def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
+        self.target = target
+        self.name = name
+        self.delay = delay
+        self.prescale_low = self.target.getNode("%s.i2c_pre_lo" % name)
+        self.prescale_high = self.target.getNode("%s.i2c_pre_hi" % name)
+        self.ctrl = self.target.getNode("%s.i2c_ctrl" % name)
+        self.data = self.target.getNode("%s.i2c_rxtx" % name)
+        self.cmd_stat = self.target.getNode("%s.i2c_cmdstatus" % name)
+        self.wishboneclock = wclk
+        self.i2cclock = i2cclk
+        self.config()
+
+    def state(self):
+        status = {}
+        status["ps_low"] = self.prescale_low.read()
+        status["ps_hi"] = self.prescale_high.read()
+        status["ctrl"] = self.ctrl.read()
+        status["data"] = self.data.read()
+        status["cmd_stat"] = self.cmd_stat.read()
+        self.target.dispatch()
+        status["prescale"] = status["ps_hi"] << 8
+        status["prescale"] |= status["ps_low"]
+        for reg in status:
+            val = status[reg]
+            bval = bin(int(val))
+            if verbose:
+                print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
+
+    def clearint(self):
+        self.ctrl.write(0x1)
+        self.target.dispatch()
+
+    def config(self):
+        #INITIALIZATION OF THE I2S MASTER CORE
+        #Disable core
+        self.ctrl.write(0x0 << 7)
+        self.target.dispatch()
+        #Write pre-scale register
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) 
+        prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
+        self.prescale_low.write(prescale & 0xff)
+        self.prescale_high.write((prescale & 0xff00) >> 8)
+        #Enable core
+        self.ctrl.write(0x1 << 7)
+        self.target.dispatch()
+
+    def checkack(self):
+        inprogress = True
+        ack = False
+        while inprogress:
+            cmd_stat = self.cmd_stat.read()
+            self.target.dispatch()
+            inprogress = (cmd_stat & I2CCore.inprogress) > 0
+            ack = (cmd_stat & I2CCore.recvdack) == 0
+        return ack
+
+    def delayorcheckack(self):
+        ack = True
+        if self.delay is None:
+            ack = self.checkack()
+        else:
+            time.sleep(self.delay)
+            ack = self.checkack()#Remove this?
+        return ack
+
+################################################################################
+# /*
+#        I2C WRITE
+# */
+################################################################################
+
+
+
+    def write(self, addr, data, stop=True):
+        """Write data to the device with the given address."""
+        # Start transfer with 7 bit address and write bit (0)
+        nwritten = -1
+        addr &= 0x7f
+        addr = addr << 1
+        startcmd = 0x1 << 7
+        stopcmd = 0x1 << 6
+        writecmd = 0x1 << 4
+        #Set transmit register (write operation, LSB=0)
+        self.data.write(addr)
+        #Set Command Register to 0x90 (write, start)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return nwritten
+        nwritten += 1
+        for val in data:
+            val &= 0xff
+            #Write slave memory address
+            self.data.write(val)
+            #Set Command Register to 0x10 (write)
+            self.cmd_stat.write(I2CCore.writecmd)
+            self.target.dispatch()
+            ack = self.delayorcheckack()
+            if not ack:
+                self.cmd_stat.write(I2CCore.stopcmd)
+                self.target.dispatch()
+                return nwritten
+            nwritten += 1
+        if stop:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+        return nwritten
+
+################################################################################
+# /*
+#        I2C READ
+# */
+################################################################################
+    def read(self, addr, n):
+        """Read n bytes of data from the device with the given address."""
+        # Start transfer with 7 bit address and read bit (1)
+        data = []
+        addr &= 0x7f
+        addr = addr << 1
+        addr |= 0x1 # read bit
+        self.data.write(addr)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return data
+        for i in range(n):
+            if i < (n-1):
+                self.cmd_stat.write(I2CCore.readcmd) # <---
+            else:
+                self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
+	        self.target.dispatch()
+            ack = self.delayorcheckack()
+            val = self.data.read()
+            self.target.dispatch()
+            data.append(val & 0xff)
+        #self.cmd_stat.write(I2CCore.stopcmd)
+        #self.target.dispatch()
+        return data
+
+################################################################################
+# /*
+#        I2C WRITE-READ
+# */
+################################################################################
+
+
+
+    # def writeread(self, addr, data, n):
+    #     """Write data to device, then read n bytes back from it."""
+    #     nwritten = self.write(addr, data, stop=False)
+    #     readdata = []
+    #     if nwritten == len(data):
+    #         readdata = self.read(addr, n)
+    #     return nwritten, readdata
+
+"""
+SPI core XML:
+
+<node description="SPI master controller" fwinfo="endpoint;width=3">
+    <node id="d0" address="0x0" description="Data reg 0"/>
+    <node id="d1" address="0x1" description="Data reg 1"/>
+    <node id="d2" address="0x2" description="Data reg 2"/>
+    <node id="d3" address="0x3" description="Data reg 3"/>
+    <node id="ctrl" address="0x4" description="Control reg"/>
+    <node id="divider" address="0x5" description="Clock divider reg"/>
+    <node id="ss" address="0x6" description="Slave select reg"/>
+</node>
+"""
+class SPICore:
+
+    go_busy = 0x1 << 8
+    rising = 1
+    falling = 0
+
+
+    def __init__(self, target, wclk, spiclk, basename="io.spi"):
+        self.target = target
+        # Only a single data register is required since all transfers are
+        # 16 bit long
+        self.data = target.getNode("%s.d0" % basename)
+        self.control = target.getNode("%s.ctrl" % basename)
+        self.control_val = 0b0
+        self.divider = target.getNode("%s.divider" % basename)
+        self.slaveselect = target.getNode("%s.ss" % basename)
+        self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
+        self.divider_val = 0x7f
+        self.configured = False
+
+    def config(self):
+        "Configure SPI interace for communicating with ADCs."
+        self.divider_val = int(self.divider_val) % 0xffff
+        if verbose:
+            print "Configuring SPI core, divider = 0x%x" % self.divider_val
+        self.divider.write(self.divider_val)
+        self.target.dispatch()
+        self.control_val = 0x0
+        self.control_val |= 0x0 << 13 # Automatic slave select
+        self.control_val |= 0x0 << 12 # No interrupt
+        self.control_val |= 0x0 << 11 # MSB first
+        # ADC samples data on rising edge of SCK
+        self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
+        # ADC changes output shortly after falling edge of SCK
+        self.control_val |= 0x0 << 9 # read input on rising edge
+        self.control_val |= 0x10 # 16 bit transfers
+        if verbose:
+            print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
+        self.configured = True
+
+    def transmit(self, chip, value):
+        if not self.configured:
+            self.config()
+        assert chip >= 0 and chip < 8
+        value &= 0xffff
+        self.data.write(value)
+        checkdata = self.data.read()
+        self.target.dispatch()
+        assert checkdata == value
+        self.control.write(self.control_val)
+        self.slaveselect.write(0xff ^ (0x1 << chip))
+        self.target.dispatch()
+        self.control.write(self.control_val | SPICore.go_busy)
+        self.target.dispatch()
+        busy = True
+        while busy:
+            status = self.control.read()
+            self.target.dispatch()
+            busy = status & SPICore.go_busy > 0
+        self.slaveselect.write(0xff)
+        data = self.data.read()
+        ss = self.slaveselect.read()
+        status = self.control.read()
+        self.target.dispatch()
+        #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
+        return data
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal2.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal2.py
new file mode 100644
index 0000000000000000000000000000000000000000..1d1f0b47d73759587ad05a192ced19530cfdb4b3
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2CuHal2.py
@@ -0,0 +1,282 @@
+# -*- coding: utf-8 -*-
+"""
+
+"""
+
+import time
+
+import uhal
+
+verbose = True
+
+
+
+################################################################################
+# /*
+#        I2C CORE
+# */
+################################################################################
+
+### Same as the class defined in I2CuHal.py but the register names are changed to
+### comply with D. Newbold's notation. To be used in the Dune SFP Fanout (pc059a)
+
+class I2CCore:
+    """I2C communication block."""
+
+    # Define bits in cmd_stat register
+    startcmd = 0x1 << 7
+    stopcmd = 0x1 << 6
+    readcmd = 0x1 << 5
+    writecmd = 0x1 << 4
+    ack = 0x1 << 3
+    intack = 0x1
+
+    recvdack = 0x1 << 7
+    busy = 0x1 << 6
+    arblost = 0x1 << 5
+    inprogress = 0x1 << 1
+    interrupt = 0x1
+
+    def __init__(self, target, wclk, i2cclk, name="i2c", delay=None):
+        self.target = target
+        self.name = name
+        self.delay = delay
+        self.prescale_low = self.target.getNode("%s.ps_lo" % name)
+        self.prescale_high = self.target.getNode("%s.ps_hi" % name)
+        self.ctrl = self.target.getNode("%s.ctrl" % name)
+        self.data = self.target.getNode("%s.data" % name)
+        self.cmd_stat = self.target.getNode("%s.cmd_stat" % name)
+        self.wishboneclock = wclk
+        self.i2cclock = i2cclk
+        self.config()
+
+    def state(self):
+        status = {}
+        status["ps_low"] = self.prescale_low.read()
+        status["ps_hi"] = self.prescale_high.read()
+        status["ctrl"] = self.ctrl.read()
+        status["data"] = self.data.read()
+        status["cmd_stat"] = self.cmd_stat.read()
+        self.target.dispatch()
+        status["prescale"] = status["ps_hi"] << 8
+        status["prescale"] |= status["ps_low"]
+        for reg in status:
+            val = status[reg]
+            bval = bin(int(val))
+            if verbose:
+                print "\treg %s = %d, 0x%x, %s" % (reg, val, val, bval)
+
+    def clearint(self):
+        self.ctrl.write(0x1)
+        self.target.dispatch()
+
+    def config(self):
+        #INITIALIZATION OF THE I2S MASTER CORE
+        #Disable core
+        self.ctrl.write(0x0 << 7)
+        self.target.dispatch()
+        #Write pre-scale register
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock)) - 1
+        #prescale = int(self.wishboneclock / (5.0 * self.i2cclock))
+        prescale = 0x0100 #FOR NOW HARDWIRED, TO BE MODIFIED
+        self.prescale_low.write(prescale & 0xff)
+        self.prescale_high.write((prescale & 0xff00) >> 8)
+        #Enable core
+        self.ctrl.write(0x1 << 7)
+        self.target.dispatch()
+
+    def checkack(self):
+        inprogress = True
+        ack = False
+        while inprogress:
+            cmd_stat = self.cmd_stat.read()
+            self.target.dispatch()
+            inprogress = (cmd_stat & I2CCore.inprogress) > 0
+            ack = (cmd_stat & I2CCore.recvdack) == 0
+        return ack
+
+    def delayorcheckack(self):
+        ack = True
+        if self.delay is None:
+            ack = self.checkack()
+        else:
+            time.sleep(self.delay)
+            ack = self.checkack()#Remove this?
+        return ack
+
+################################################################################
+# /*
+#        I2C WRITE
+# */
+################################################################################
+
+
+
+    def write(self, addr, data, stop=True):
+        """Write data to the device with the given address."""
+        # Start transfer with 7 bit address and write bit (0)
+        nwritten = -1
+        addr &= 0x7f
+        addr = addr << 1
+        startcmd = 0x1 << 7
+        stopcmd = 0x1 << 6
+        writecmd = 0x1 << 4
+        #Set transmit register (write operation, LSB=0)
+        self.data.write(addr)
+        #Set Command Register to 0x90 (write, start)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            print "no ack from I2C address", hex(addr>>1)
+            return nwritten
+        nwritten += 1
+        for val in data:
+            val &= 0xff
+            #Write slave memory address
+            self.data.write(val)
+            #Set Command Register to 0x10 (write)
+            self.cmd_stat.write(I2CCore.writecmd)
+            self.target.dispatch()
+            ack = self.delayorcheckack()
+            if not ack:
+                self.cmd_stat.write(I2CCore.stopcmd)
+                self.target.dispatch()
+                return nwritten
+            nwritten += 1
+        if stop:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+        return nwritten
+
+################################################################################
+# /*
+#        I2C READ
+# */
+################################################################################
+    def read(self, addr, n):
+        """Read n bytes of data from the device with the given address."""
+        # Start transfer with 7 bit address and read bit (1)
+        data = []
+        addr &= 0x7f
+        addr = addr << 1
+        addr |= 0x1 # read bit
+        self.data.write(addr)
+        self.cmd_stat.write(I2CCore.startcmd | I2CCore.writecmd)
+        self.target.dispatch()
+        ack = self.delayorcheckack()
+        if not ack:
+            self.cmd_stat.write(I2CCore.stopcmd)
+            self.target.dispatch()
+            return data
+        for i in range(n):
+            if i < (n-1):
+                self.cmd_stat.write(I2CCore.readcmd) # <---
+            else:
+                self.cmd_stat.write(I2CCore.readcmd | I2CCore.ack | I2CCore.stopcmd) # <--- This tells the slave that it is the last word
+	        self.target.dispatch()
+            ack = self.delayorcheckack()
+            val = self.data.read()
+            self.target.dispatch()
+            data.append(val & 0xff)
+        #self.cmd_stat.write(I2CCore.stopcmd)
+        #self.target.dispatch()
+        return data
+
+################################################################################
+# /*
+#        I2C WRITE-READ
+# */
+################################################################################
+
+
+
+    # def writeread(self, addr, data, n):
+    #     """Write data to device, then read n bytes back from it."""
+    #     nwritten = self.write(addr, data, stop=False)
+    #     readdata = []
+    #     if nwritten == len(data):
+    #         readdata = self.read(addr, n)
+    #     return nwritten, readdata
+
+"""
+SPI core XML:
+
+<node description="SPI master controller" fwinfo="endpoint;width=3">
+    <node id="d0" address="0x0" description="Data reg 0"/>
+    <node id="d1" address="0x1" description="Data reg 1"/>
+    <node id="d2" address="0x2" description="Data reg 2"/>
+    <node id="d3" address="0x3" description="Data reg 3"/>
+    <node id="ctrl" address="0x4" description="Control reg"/>
+    <node id="divider" address="0x5" description="Clock divider reg"/>
+    <node id="ss" address="0x6" description="Slave select reg"/>
+</node>
+"""
+class SPICore:
+
+    go_busy = 0x1 << 8
+    rising = 1
+    falling = 0
+
+
+    def __init__(self, target, wclk, spiclk, basename="io.spi"):
+        self.target = target
+        # Only a single data register is required since all transfers are
+        # 16 bit long
+        self.data = target.getNode("%s.d0" % basename)
+        self.control = target.getNode("%s.ctrl" % basename)
+        self.control_val = 0b0
+        self.divider = target.getNode("%s.divider" % basename)
+        self.slaveselect = target.getNode("%s.ss" % basename)
+        self.divider_val = int(wclk / spiclk / 2.0 - 1.0)
+        self.divider_val = 0x7f
+        self.configured = False
+
+    def config(self):
+        "Configure SPI interace for communicating with ADCs."
+        self.divider_val = int(self.divider_val) % 0xffff
+        if verbose:
+            print "Configuring SPI core, divider = 0x%x" % self.divider_val
+        self.divider.write(self.divider_val)
+        self.target.dispatch()
+        self.control_val = 0x0
+        self.control_val |= 0x0 << 13 # Automatic slave select
+        self.control_val |= 0x0 << 12 # No interrupt
+        self.control_val |= 0x0 << 11 # MSB first
+        # ADC samples data on rising edge of SCK
+        self.control_val |= 0x1 << 10 # change ouput on falling edge of SCK
+        # ADC changes output shortly after falling edge of SCK
+        self.control_val |= 0x0 << 9 # read input on rising edge
+        self.control_val |= 0x10 # 16 bit transfers
+        if verbose:
+            print "SPI control val = 0x%x = %s" % (self.control_val, bin(self.control_val))
+        self.configured = True
+
+    def transmit(self, chip, value):
+        if not self.configured:
+            self.config()
+        assert chip >= 0 and chip < 8
+        value &= 0xffff
+        self.data.write(value)
+        checkdata = self.data.read()
+        self.target.dispatch()
+        assert checkdata == value
+        self.control.write(self.control_val)
+        self.slaveselect.write(0xff ^ (0x1 << chip))
+        self.target.dispatch()
+        self.control.write(self.control_val | SPICore.go_busy)
+        self.target.dispatch()
+        busy = True
+        while busy:
+            status = self.control.read()
+            self.target.dispatch()
+            busy = status & SPICore.go_busy > 0
+        self.slaveselect.write(0xff)
+        data = self.data.read()
+        ss = self.slaveselect.read()
+        status = self.control.read()
+        self.target.dispatch()
+        #print "Received data: 0x%x, status = 0x%x, ss = 0x%x" % (data, status, ss)
+        return data
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2cBusProperties.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2cBusProperties.py
new file mode 100644
index 0000000000000000000000000000000000000000..a23f30cd537987907774b0a11869026ec5feb96d
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/I2cBusProperties.py
@@ -0,0 +1,122 @@
+##########################################################
+#  I2cBusProperties - simple encapsulation of all items
+#                     required to control an I2C bus.
+#
+#  Carl Jeske, July 2010
+#  Refactored by Robert Frazier, May 2011
+##########################################################
+
+
+class I2cBusProperties(object):
+    """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
+
+    Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
+    value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
+    registers that define/control the bus (assuming these names are not the defaults specified
+    in the constructor below).  The seven registers consist of the two clock pre-scaling
+    registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
+    COMMAND and STATUS).
+
+    Usage:  You'll need to create an instance of this class to give to a concrete I2C bus instance, such
+            as OpenCoresI2cBus.  This I2cBusProperties class is simply a container to hold the properties
+            that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
+
+            Access the items stored by this class via these (deliberately compact) variable names:
+
+                chipsBus     -- the ChipsBus device hosting the I2C core
+                preHiVal     -- the top byte of the clock prescale value
+                preLoVal     -- the bottom byte of the clock prescale value
+                preHiReg     -- the register the top byte of the clk prescale value (preHiVal) gets written to
+                preLoReg     -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
+                ctrlReg      -- the I2C Control register
+                txReg        -- the I2C Transmit register
+                rxReg        -- the I2C Receive register
+                cmdReg       -- the I2C Command register
+                statusReg    -- the I2C Status register
+
+
+    Compatibility Notes: The seven register names are the registers typically required to operate an
+                         OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
+                         the same way as the OpenCores one). This software is not compatible with your
+                         I2C bus master if it doesn't use this register interface.
+    """
+
+    def __init__(self,
+                 chipsBusDevice,
+                 clkPrescaleU16,
+                 clkPrescaleLoByteReg = "i2c_pre_lo",
+                 clkPrescaleHiByteReg = "i2c_pre_hi",
+                 controlReg           = "i2c_ctrl",
+                 transmitReg          = "i2c_tx",
+                 receiveReg           = "i2c_rx",
+                 commandReg           = "i2c_cmd",
+                 statusReg            = "i2c_status"):
+
+        """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
+
+        chipsBusDevice:  Provide a ChipsBus instance to the device where the I2C bus is being
+                controlled. The address table for this device must contain the five registers
+                that control the bus, as declared next...
+
+        clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
+                master-clock.  This value gets split into two 8-bit values and ultimately will
+                get written to the two I2C clock-prescale registers as declared below.  See
+                the OpenCores or Lattice Semiconductor I2C documentation for more details.
+
+        clkPrescaleLoByteReg:  The register where the lower byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_lo".
+
+        clkPrescaleHiByteReg:  The register where the higher byte of the clock prescale value is set.  The default
+                name for this register is "i2c_pre_hi"
+
+        controlReg:  The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
+                usually read and write accessible. The default name for this register is "i2c_ctrl".
+
+        transmitReg:  The TRANSMIT register, used for holding the data to be transmitted via I2C, etc.  This
+                typically shares the same address as the RECEIVE register, but has write-only access.  The default
+                name for this register is "i2c_tx".
+
+        receiveReg:  The RECEIVE register - allows access to the byte received over the I2C bus.  This
+                typically shares the same address as the TRANSMIT register, but has read-only access.  The
+                default name for this register is "i2c_rx".
+
+        commandReg:  The COMMAND register - stores the command for the next I2C operation.  This typically
+                shares the same address as the STATUS register, but has write-only access.  The default name for
+                this register is "i2c_cmd".
+
+        statusReg:  The STATUS register - allows monitoring of the I2C operations.  This typically shares
+                the same address as the COMMAND register, but has read-only access.  The default name for this
+                register is "i2c_status".
+        """
+
+        object.__init__(self)
+        self.chipsBus = chipsBusDevice
+        self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
+        self.preLoVal = (clkPrescaleU16 & 0xff)
+        
+        # Check to see all the registers are in the address table
+        registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
+        for reg in registers:
+            if not self.chipsBus.addrTable.checkItem(reg):
+                raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
+
+        # Check that the registers we'll need to write to are indeed writable
+        writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
+        for wReg in writableRegisters:
+            if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
+                raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
+
+        # Check that the registers we'll need to read from are indeed readable
+        readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
+        for rReg in readableRegisters:
+            if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
+                raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
+
+        # Store the various register name strings
+        self.preHiReg = clkPrescaleHiByteReg
+        self.preLoReg = clkPrescaleLoByteReg
+        self.ctrlReg = controlReg
+        self.txReg = transmitReg
+        self.rxReg = receiveReg
+        self.cmdReg = commandReg
+        self.statusReg = statusReg
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/NHDC0220Biz.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/NHDC0220Biz.py
new file mode 100644
index 0000000000000000000000000000000000000000..acb265b2845284c583d269ef527adacfbdd4f8d5
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/NHDC0220Biz.py
@@ -0,0 +1,23 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class NHDC0220Biz:
+    #Class to configure the EEPROM
+
+    def __init__(self, i2c, slaveaddr=0x3c):
+        self.i2c = i2c
+        self.slaveaddr = 0x2a#slaveaddr
+
+    def test(self):
+	print "Testing the display"
+	return
+    
+    def writeSomething(self):
+	mystop= True
+	print "Write random stuff"
+	myaddr= [0x08, 0x38]
+	self.i2c.write( self.slaveaddr, myaddr, mystop)
+	
+	return
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9539PW.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9539PW.py
new file mode 100644
index 0000000000000000000000000000000000000000..723b0ad43ca312e9edd8f4d10b10eaff321cdc3c
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9539PW.py
@@ -0,0 +1,94 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class PCA9539PW:
+    #Class to configure the expander modules
+
+    def __init__(self, i2c, slaveaddr=0x74):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+
+    def writeReg(self, regN, regContent, verbose=False):
+        #Basic functionality to write to register.
+        if (regN < 0) | (regN > 7):
+            print "PCA9539PW - ERROR: register number should be in range [0:7]"
+            return
+        regContent= regContent & 0xFF
+        mystop=True
+        cmd= [regN, regContent]
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+
+    def readReg(self, regN, nwords, verbose=False):
+        #Basic functionality to read from register.
+        if (regN < 0) | (regN > 7):
+            print "PCA9539PW - ERROR: register number should be in range [0:7]"
+            return
+        mystop=False
+        self.i2c.write( self.slaveaddr, [regN], mystop)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+
+
+    def setInvertReg(self, regN, polarity= 0x00):
+        #Set the content of register 4 or 5 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        polarity = polarity & 0xFF
+        self.writeReg(regN+4, polarity)
+
+    def getInvertReg(self, regN):
+        #Read the content of register 4 or 5 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        res= self.readReg(regN+4, 1)
+        return res
+
+    def setIOReg(self, regN, direction= 0xFF):
+        #Set the content of register 6 or 7 which determine the direction of the
+        #ports (0= output, 1= input).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        direction = direction & 0xFF
+        self.writeReg(regN+6, direction)
+
+    def getIOReg(self, regN):
+        #Read the content of register 6 or 7 which determine the polarity of the
+        #ports (0= normal, 1= inverted).
+        if (regN < 0) | (regN > 1):
+            print "PCA9539PW - ERROR: regN should be 0 or 1"
+            return
+        res= self.readReg(regN+6, 1)
+        return res
+
+    def getInputs(self, bank):
+        #Read the incoming values of the pins for one of the two 8-bit banks.
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        res= self.readReg(bank, 1)
+        return res
+
+    def setOutputs(self, bank, values= 0x00):
+        #Set the content of the output flip-flops.
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        values = values & 0xFF
+        self.writeReg(bank+2, values)
+
+    def getOutputs(self, bank):
+        #Read the state of the outputs (i.e. what value is being written to them)
+        if (bank < 0) | (bank > 1):
+            print "PCA9539PW - ERROR: bank should be 0 or 1"
+            return
+        res= self.readReg(bank+2, 1)
+        return res
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9548ADW.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9548ADW.py
new file mode 100644
index 0000000000000000000000000000000000000000..adb6742ee523449b4a9ccbd4fd0b08a2a6202387
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/PCA9548ADW.py
@@ -0,0 +1,51 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+
+class PCA9548ADW:
+    #Class to configure the I2C multiplexer
+
+    def __init__(self, i2c, slaveaddr=0x74):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    def disableAllChannels(self, verbose=False):
+        #Disable all channels so that none of the MUX outputs is visible
+        # to the upstream I2C bus
+        mystop=True
+        cmd= [0x0]
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+    def getChannelStatus(self, verbose=False):
+        #Basic functionality to read the status of the control register and determine
+        # which channel is currently enabled.
+        mystop=False
+        cmd= []
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+        res= self.i2c.read( self.slaveaddr, 1)
+        return res[0]
+
+    def setActiveChannel(self, channel, verbose=False):
+        #Basic functionality to activate one channel
+        # In principle multiple channels can be active at the same time (see
+        # function "setMultipleChannels")
+        if (channel < 0) | (channel > 7):
+            print "PCA9539PW - ERROR: channel number should be in range [0:7]"
+            return
+        mystop=True
+        cmd= [0x1 << channel]
+        #print "\tChannel is ", channel, "we write ", cmd
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+    def setMultipleChannels(self, channels, verbose=False):
+        #Basic functionality to activate multiple channels
+        # channels is a byte: each bit set to one will set the corresponding channels
+        # as active. The slave connected to that channel will be visible on the I2C bus.
+        # NOTE: this can lead to address clashes!
+        channels = channels & 0xFF
+        mystop=True
+        cmd= [channels]
+        #print "\tChannel is ", channel, "we write ", cmd
+        self.i2c.write( self.slaveaddr, cmd, mystop)
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/RawI2cAccess.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/RawI2cAccess.py
new file mode 100644
index 0000000000000000000000000000000000000000..284613299f372f0718001f996fa083befc68113b
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/RawI2cAccess.py
@@ -0,0 +1,261 @@
+# Created on Sep 10, 2012
+# @author: Kristian Harder, based on code by Carl Jeske
+
+from I2cBusProperties import I2cBusProperties
+from ChipsBus import ChipsBus
+from ChipsLog import chipsLog
+from ChipsException import ChipsException
+
+
+class RawI2cAccess:
+
+    def __init__(self, i2cBusProps, slaveAddr):
+
+        # For performing read/writes over an OpenCores-compatible I2C bus master
+        #
+        # An instance of this class is required to communicate with each
+        # I2C slave on the I2C bus.
+        #
+        # i2cBusProps: an instance of the class I2cBusProperties that contains
+        #    the relevant ChipsBus host and the I2C bus-master registers (if
+        #    they differ from the defaults specified by the I2cBusProperties
+        #    class).
+        #
+        #slaveAddr: The address of the I2C slave you wish to communicate with.
+        #
+
+        self._i2cProps = i2cBusProps   # The I2C Bus Properties
+        self._slaveAddr = 0x7f & slaveAddr  # 7-bit slave address
+
+
+    def resetI2cBus(self):
+
+        # Resets the I2C bus
+        #
+        # This function does the following:
+        #        1) Disables the I2C core
+        #        2) Sets the clock prescale registers
+        #        3) Enables the I2C core
+        #        4) Sets all writable bus-master registers to default values
+
+        try:
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
+            #self._chipsBus().getNode(self._i2cProps.ctrlReg).write(0)
+            self._chipsBus().queueWrite(self._i2cProps.preHiReg,
+                                        self._i2cProps.preHiVal)
+            self._chipsBus().queueWrite(self._i2cProps.preLoReg,
+                                        self._i2cProps.preLoVal)
+            self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
+            self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
+            self._chipsBus().queueRun()
+        except ChipsException, err:
+            raise ChipsException("I2C reset error:\n\t" + str(err))
+
+
+    def read(self, numBytes):
+
+        # Performs an I2C read. Returns the 8-bit read result(s).
+        #
+        # numBytes: number of bytes expected as response
+        #
+
+        try:
+            result = self._privateRead(numBytes)
+        except ChipsException, err:
+            raise ChipsException("I2C read error:\n\t" + str(err))
+        return result
+
+
+    def write(self, listDataU8):
+
+        # Performs an 8-bit I2C write.
+        #
+        # listDataU8:  The 8-bit data values to be written.
+        #
+
+        try:
+            self._privateWrite(listDataU8)
+        except ChipsException, err:
+            raise ChipsException("I2C write error:\n\t" + str(err))
+        return
+
+
+    def _chipsBus(self):
+
+        # Returns the instance of the ChipsBus device that's hosting
+        # the I2C bus master
+
+        return self._i2cProps.chipsBus
+
+
+    def _privateRead(self, numBytes):
+
+        # I2C read implementation.
+        #
+        #  Fast I2C read implementation,
+        # i.e. done with the fewest packets possible.
+
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        #        '1' = reading from slave
+        #        '0' = writing to slave
+
+        # command reg definitions
+        # bit 7:   Generate start condition
+        # bit 6:   Generate stop condition
+        # bit 5:   Read from slave
+        # bit 4:   Write to slave
+        # bit 3:   0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0:   Interrupt acknowledge. When set, clears a pending interrupt
+
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero
+        # (i.e. we're writing an address to the bus)
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) | 0x01)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        result=[]
+        for ibyte in range(numBytes):
+            if ibyte==numBytes-1:
+                stop_bit=0x40
+                ack_bit=0x08
+            else:
+                stop_bit=0
+                ack_bit=0
+                pass
+            # Set read bit, acknowledge and stop bit in command reg
+            self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
+            # Wait for transaction to finish.
+            # Don't expect an ACK, do expect bus free at finish.
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = False,
+                                           requireBusIdleAtEnd = False)
+                pass
+            result.append(self._chipsBus().read(self._i2cProps.rxReg))
+
+        return result
+
+
+    def _privateWrite(self, listDataU8):
+
+        # I2C write implementation.
+        #
+        #  Fast I2C write implementation,
+        # i.e. done with the fewest packets possible.
+
+        # transmit reg definitions
+        # bits 7-1: 7-bit slave address during address transfer
+        #           or first 7 bits of byte during data transfer
+        # bit 0: RW flag during address transfer or LSB during data transfer.
+        # '1' = reading from slave
+        # '0' = writing to slave
+
+        # command reg definitions
+        # bit 7: Generate start condition
+        # bit 6: Generate stop condition
+        # bit 5: Read from slave
+        # bit 4: Write to slave
+        # bit 3: 0 when acknowledgement is received
+        # bit 2:1: Reserved
+        # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
+        # Reset bus before beginning
+        self.resetI2cBus()
+
+        # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
+        self._chipsBus().queueWrite(self._i2cProps.txReg,
+                                    (self._slaveAddr << 1) & 0xfe)
+        # Set start and write bit in command reg
+        self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+        # Run the queue
+        self._chipsBus().queueRun()
+        # Wait for transaction to finish.
+        self._i2cWaitUntilFinished()
+
+        for ibyte in range(len(listDataU8)):
+            dataU8 = listDataU8[ibyte]
+            if ibyte==len(listDataU8)-1:
+                stop_bit=0x40
+            else:
+                stop_bit=0x00
+                pass
+            # Set data to be written in transmit reg
+            self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
+            # Set write and stop bit in command reg
+            self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
+            # Run the queue
+            self._chipsBus().queueRun()
+            # Wait for transaction to finish.
+            # Do expect an ACK and do expect bus to be free at finish
+            if stop_bit:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = True)
+            else:
+                self._i2cWaitUntilFinished(requireAcknowledgement = True,
+                                           requireBusIdleAtEnd = False)
+                pass
+            pass
+
+        return
+
+
+    def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
+                              requireBusIdleAtEnd = False):
+
+        # Ensures the current bus transaction has finished successfully
+        # before allowing further I2C bus transactions
+
+        # This method monitors the status register
+        # and will not allow execution to continue until the
+        # I2C bus has completed properly.  It will throw an exception
+        # if it picks up bus problems or a bus timeout occurs.
+
+        maxRetry = 20
+        attempt = 1
+        while attempt <= maxRetry:
+
+            # Get the status
+            i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
+
+            receivedAcknowledge = not bool(i2c_status & 0x80)
+            busy = bool(i2c_status & 0x40)
+            arbitrationLost = bool(i2c_status & 0x20)
+            transferInProgress = bool(i2c_status & 0x02)
+            interruptFlag = bool(i2c_status & 0x01)
+
+            if arbitrationLost:  # This is an instant error at any time
+                raise ChipsException("I2C error: Arbitration lost!")
+
+            if not transferInProgress:
+                break  # The transfer looks to have completed successfully, pending further checks
+
+            attempt += 1
+
+        # At this point, we've either had too many retries, or the
+        # Transfer in Progress (TIP) bit went low.  If the TIP bit
+        # did go low, then we do a couple of other checks to see if
+        # the bus operated as expected:
+
+        if attempt > maxRetry:
+            raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
+
+        if requireAcknowledgement and not receivedAcknowledge:
+            raise ChipsException("I2C error: No acknowledge received!")
+
+        if requireBusIdleAtEnd and busy:
+            raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/SFPI2C.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/SFPI2C.py
new file mode 100644
index 0000000000000000000000000000000000000000..2dad8d4560e4b386047176e7c57788076f1aa517
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/SFPI2C.py
@@ -0,0 +1,91 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+
+class SFPI2C:
+    #Class to configure the EEPROM
+
+    def __init__(self, i2c, slaveaddr=0x50):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+
+    """def readEEPROM(self, startadd, nBytes):
+        #Read EEPROM memory locations
+        mystop= False
+        myaddr= [startadd]#0xfa
+        self.i2c.write( self.slaveaddr, [startadd], mystop)
+        res= self.i2c.read( self.slaveaddr, nBytes)
+        return res"""
+        
+    def _listToString(self, mylist):
+        mystring= ""
+        for iChar in mylist:
+          mystring= mystring + str(unichr(iChar))
+        return mystring
+
+    def writeReg(self, regN, regContent, verbose=False):
+        #Basic functionality to write to register.
+        if (regN < 0) | (regN > 7):
+            print "PCA9539PW - ERROR: register number should be in range [0:7]"
+            return
+        regContent= regContent & 0xFF
+        mystop=True
+        cmd= [regN, regContent]
+        self.i2c.write( self.slaveaddr, cmd, mystop)
+
+    def readReg(self, regN, nwords, verbose=False):
+        #Basic functionality to read from register.
+        mystop=False
+        self.i2c.write( self.slaveaddr, [regN], mystop)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+        
+    def getConnector(self):
+        """Code for connector type (table 3.4)"""
+        conntype= self.readReg(2, 1, False)[0]
+        print "Connector type:", hex(conntype)
+        return conntype
+        
+    def getDiagnosticsType(self):
+        """Types of diagnostics available (table 3.9)"""
+        diaType= self.readReg(92, 1, False)[0]
+        print "Available Diagnostics:", hex(diaType)
+        return diaType
+        
+    def getEncoding(self):
+        encoding= self.readReg(11, 1, False)[0]
+        print "Encoding", encoding
+        return encoding
+        
+    def getEnhancedOpt(self):
+        enOpt= self.readReg(93, 1, False)[0]
+        print "Enhanced Options:", enOpt
+        return enOpt
+        
+    def getTransceiver(self):
+        res= self.readReg(3, 8, False)
+        return res
+
+    def getVendorId(self):
+        """ Returns the OUI vendor id"""
+        vendID= self.readReg(37, 3, False)
+        return vendID
+        
+    def getVendorName(self):
+        res= self.readReg( 20 , 16, False)
+        mystring= self._listToString(res)
+        return mystring
+    
+    def getVendorPN(self):
+        """ Returns the part number defined by the vendor"""
+        pn=[]
+        mystring= ""
+        res= self.readReg( 40 , 16, False)
+        mystring= self._listToString(res)
+        return mystring
+
+    def scanI2C(self):
+        mystop=True
+        for iAddr in range (0, 128):
+            self.i2c.write( iAddr, [], mystop)
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLU_powermodule.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLU_powermodule.py
new file mode 100644
index 0000000000000000000000000000000000000000..6e5dc1eacdb6a0c145576ca5b9ae047a33562430
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLU_powermodule.py
@@ -0,0 +1,481 @@
+# -*- coding: utf-8 -*-
+import uhal
+from I2CuHal import I2CCore
+#import StringIO
+from AD5665R import AD5665R # Library for DAC
+from PCA9539PW import PCA9539PW # Library for serial line expander
+
+class PWRLED:
+    #Class to configure the EEPROM
+
+    def __init__(self, i2ccore, DACaddr=0x1C, PMTmaxV= 1, Exp1Add= 0x76, Exp2Add= 0x77):
+        print "  TLU POWERMODULE Initializing..."
+        self.TLU_I2C = i2ccore
+        self.pwraddr = DACaddr
+        self.exp1addr= Exp1Add
+        self.exp2addr= Exp2Add
+        self.intRefOn= 0
+        self.vCtrlMax= PMTmaxV
+        self.verbose= True
+        #Map indicator color based on their position on the expanders: 0-15 are on expander 2, 16 to 31 on expander 1. One indicator is missing the blue component, hence
+        #the "-1" value.
+        #self.indicatorXYZ= [(1, 0, -1), (3, 2, 4), (6, 5, 7), (9, 8, 10), (12, 11, 13), (15, 14, 16), (18, 17, 19), (21, 20, 22), (24, 23, 25), (27, 26, 28), (30, 29, 31)]
+        self.indicatorXYZ= [(30, 29, 31), (27, 26, 28), (24, 23, 25), (21, 20, 22), (18, 17, 19), (15, 14, 16), (12, 11, 13), (9, 8, 10), (6, 5, 7), (3, 2, 4), (1, 0, -1)]
+
+        self.zeDAC_pwr=AD5665R(self.TLU_I2C, self.pwraddr)
+        self.zeDAC_pwr.setIntRef(self.intRefOn, self.verbose)
+        self.zeDAC_pwr.writeDAC(int(0), 7, self.verbose)
+
+        self.ledExp1=PCA9539PW(self.TLU_I2C, self.exp1addr)
+        self.ledExp1.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.ledExp1.setIOReg(0, 0x00)# 0= output, 1= input
+        self.ledExp1.setOutputs(0, 0xDA)# If output, set to XX
+
+        self.ledExp1.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.ledExp1.setIOReg(1, 0x00)# 0= output, 1= input
+        self.ledExp1.setOutputs(1, 0xB6)# If output, set to XX
+
+        self.ledExp2=PCA9539PW(self.TLU_I2C, self.exp2addr)
+        self.ledExp2.setInvertReg(0, 0x00)# 0= normal, 1= inverted
+        self.ledExp2.setIOReg(0, 0x00)# 0= output, 1= input
+        self.ledExp2.setOutputs(0, 0x6D)# If output, set to XX
+
+        self.ledExp2.setInvertReg(1, 0x00)# 0= normal, 1= inverted
+        self.ledExp2.setIOReg(1, 0x00)# 0= output, 1= input
+        self.ledExp2.setOutputs(1, 0xDB)# If output, set to XX
+        print "  TLU POWERMODULE Ready"
+
+    def test(self):
+	    print "Testing the powermodule"
+	    return
+
+    def setVch(self, channel, voltage, verbose=False):
+        # Note: the channel here is the DAC channel.
+        # The mapping with the power module is not one-to-one
+        if (verbose):
+            print "  PWRModule: CONFIGURING VOLTAGE FOR PMT", channel+1
+            print "\tVcontrol=", voltage
+        if ((channel < 0) | (3 < channel )):
+            print "\tPWRModule: channel should be comprised between 0 and 3"
+        else:
+            if (voltage < 0):
+                print "\tPWRModule: voltage cannot be negative. Coherced to 0 V."
+                voltage = 0
+            if (voltage > self.vCtrlMax):
+                print "\tPWRModule: voltage cannot exceed vCtrlMax. Coherced to vCtrlMax."
+                print "\tPWRModule: vCtrlMax=", self.vCtrlMax, "V. See config file to change this value."
+                voltage = self.vCtrlMax
+            dacValue= voltage*65535/self.vCtrlMax
+            self.zeDAC_pwr.writeDAC(int(dacValue), channel, verbose)
+        return
+
+    def setIndicatorRGB(self, indicator, RGB=[0, 0, 0], verbose=False):
+        # Indicator is one of the 11 LEDs on the front panels, labeled from 0 to 10
+        # RGB allows to switch on (True) or off (False) the corresponding component for that Led
+        # Note that one LED only has 2 components connected
+        #print self.indicatorXYZ[indicator-1][2]
+        if (1 <= indicator <= 11):
+            nowStatus= []
+            nowStatus.extend(self.ledExp1.getOutputs(0))
+            nowStatus.extend(self.ledExp1.getOutputs(1))
+            nowStatus.extend(self.ledExp2.getOutputs(0))
+            nowStatus.extend(self.ledExp2.getOutputs(1))
+            nowWrd= 0x00000000
+            nowWrd= nowWrd | nowStatus[0]
+            nowWrd= nowWrd | (nowStatus[1] << 8)
+            nowWrd= nowWrd | (nowStatus[2] << 16)
+            nowWrd= nowWrd | (nowStatus[3] << 24)
+            nextWrd= nowWrd
+            for iComp in range(0,3):
+                indexComp= self.indicatorXYZ[indicator-1][iComp]
+                valueComp= not bool(RGB[iComp])
+                nextWrd= self._set_bit(nextWrd, indexComp, int(valueComp), False)
+                if verbose:
+                    print "n=", iComp, "INDEX=", indexComp, "VALUE=", int(valueComp), "NEXTWORD=", bin(nextWrd)
+            if verbose:
+                print "NOW  ", bin(nowWrd)
+                print "NEXT ", bin(nextWrd)
+            nextStatus= [0xFF & nextWrd, 0xFF & (nextWrd >> 8), 0xFF & (nextWrd >> 16), 0xFF & (nextWrd >> 24) ]
+            #print "  NOW", nowStatus
+            #print "  NEXT ", nextStatus
+            if nowStatus[0] != nextStatus[0]:
+                self.ledExp1.setOutputs(0, nextStatus[0])
+            if nowStatus[1] != nextStatus[1]:
+                self.ledExp1.setOutputs(1, nextStatus[1])
+            if nowStatus[2] != nextStatus[2]:
+                self.ledExp2.setOutputs(0, nextStatus[2])
+            if nowStatus[3] != nextStatus[3]:
+                self.ledExp2.setOutputs(1, nextStatus[3])
+
+        return
+
+
+    def _set_bit(self, v, index, x, verbose= False):
+        """Set the index:th bit of v to 1 if x is truthy, else to 0, and return the new value."""
+        if (index == -1):
+            if (verbose):
+              print "  SETBIT: Index= -1 will be ignored"
+        else:
+            mask = 1 << index   # Compute mask, an integer with just bit 'index' set.
+            v &= ~mask          # Clear the bit indicated by the mask (if x is False)
+            if x:
+                v |= mask         # If x was True, set the bit indicated by the mask.
+        return v
+
+    def allGreen(self):
+        #self.setIndicatorRGB(1, [0, 1, 0])
+        #self.setIndicatorRGB(2, [0, 1, 0])
+        #self.setIndicatorRGB(3, [0, 1, 0])
+        #self.setIndicatorRGB(4, [0, 1, 0])
+        #self.setIndicatorRGB(5, [0, 1, 0])
+        #self.setIndicatorRGB(6, [0, 1, 0])
+        #self.setIndicatorRGB(7, [0, 1, 0])
+        #self.setIndicatorRGB(8, [0, 1, 0])
+        #self.setIndicatorRGB(9, [0, 1, 0])
+        #self.setIndicatorRGB(10, [0, 1, 0])
+        #self.setIndicatorRGB(11, [0, 1, 0])
+        self.ledExp1.setOutputs(0, 218)
+        self.ledExp1.setOutputs(1, 182)
+        self.ledExp2.setOutputs(0, 109)
+        self.ledExp2.setOutputs(1, 219)
+
+    def allRed(self):
+        self.ledExp1.setOutputs(0, 181)
+        self.ledExp1.setOutputs(1, 109)
+        self.ledExp2.setOutputs(0, 219)
+        self.ledExp2.setOutputs(1, 182)
+
+    def allBlue(self):
+        self.ledExp1.setOutputs(0, 111)
+        self.ledExp1.setOutputs(1, 219)
+        self.ledExp2.setOutputs(0, 182)
+        self.ledExp2.setOutputs(1, 109)
+
+    def allBlack(self):
+        self.ledExp1.setOutputs(0, 255)
+        self.ledExp1.setOutputs(1, 255)
+        self.ledExp2.setOutputs(0, 255)
+        self.ledExp2.setOutputs(1, 255)
+
+    def allWhite(self):
+        self.ledExp1.setOutputs(0, 0)
+        self.ledExp1.setOutputs(1, 0)
+        self.ledExp2.setOutputs(0, 0)
+        self.ledExp2.setOutputs(1, 0)
+
+    def kitt(self):
+        #self.allBlack()
+        print "\tWait while LEDs are tested..."
+        self.setIndicatorRGB(1, [1, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [1, 0, 0])
+        self.setIndicatorRGB(2, [1, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [1, 0, 0])
+        self.setIndicatorRGB(3, [1, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [1, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [1, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [1, 0, 0])
+
+        #mid point
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [1, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [1, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [1, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [1, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [1, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [1, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [1, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [1, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [1, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [1, 0, 0])
+        self.setIndicatorRGB(4, [1, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [0, 0, 0])
+        self.setIndicatorRGB(2, [1, 0, 0])
+        self.setIndicatorRGB(3, [1, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [1, 0, 0])
+        self.setIndicatorRGB(2, [1, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [1, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+
+        self.setIndicatorRGB(1, [1, 0, 0])
+        self.setIndicatorRGB(2, [0, 0, 0])
+        self.setIndicatorRGB(3, [0, 0, 0])
+        self.setIndicatorRGB(4, [0, 0, 0])
+        self.setIndicatorRGB(5, [0, 0, 0])
+        self.setIndicatorRGB(6, [0, 0, 0])
+        self.setIndicatorRGB(7, [0, 0, 0])
+        self.setIndicatorRGB(8, [0, 0, 0])
+        self.setIndicatorRGB(9, [0, 0, 0])
+        self.setIndicatorRGB(10, [0, 0, 0])
+        self.setIndicatorRGB(11, [0, 0, 0])
+        print "\tLED test completed"
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLU_v1e/output.csv b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLU_v1e/output.csv
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUaddrmap_BKP.xml b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUaddrmap_BKP.xml
new file mode 100644
index 0000000000000000000000000000000000000000..65fb5340f2155f8c5c92d96a2ef66d8dcb209d41
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUaddrmap_BKP.xml
@@ -0,0 +1,105 @@
+<?xml version="1.0" encoding="ISO-8859-1"?>
+
+<node id="TLU">
+
+<!-- Registers for the DUTs. These should be correct -->
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+  <node id="DutMaskW"           address="0x0" permission="w" description="" />
+  <node id="IgnoreDUTBusyW"     address="0x1" permission="w" description="" />
+  <node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
+  <node id="DUTInterfaceModeW"  address="0x3" permission="w" description="" />
+  <node id="DUTInterfaceModeModifierW"  address="0x4" permission="w" description="" />
+  <node id="DUTInterfaceModeR"  address="0xB" permission="r" description="" />
+  <node id="DUTInterfaceModeModifierR"  address="0xC" permission="r" description="" />
+  <node id="DutMaskR"           address="0x8" permission="r" description="" />
+  <node id="IgnoreDUTBusyR"     address="0x9" permission="r" description="" />
+  <node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
+</node>
+
+<node id="Shutter"    address="0x2000" description="Shutter/T0 control">
+  <node id="ShutterStateW" address="0x0" permission="w" description=""/>
+  <node id="PulseT0"  address="0x1" permission="w" description=""/>
+</node>
+<!-- I2C registers. Tested ok.-->
+<node id="i2c_master"      address="0x3000" description="I2C Master interface">
+  <node id="i2c_pre_lo"    address="0x0" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_pre_hi"    address="0x1" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_ctrl"      address="0x2" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_rxtx"      address="0x3" mask="0x000000ff" permission="rw" description="" />
+  <node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
+</node>
+<!-- Not sure about the FillLevelFlags register -->
+<node id="eventBuffer" address="0x4000" description="Event buffer">
+  <node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
+  <node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
+  <node id="EventFifoCSR" address="0x2" permission="rw" description="" />
+  <node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
+</node>
+<!-- Event formatter registers. Should be ok -->
+<node id="Event_Formatter"      address="0x5000" description="Event formatter configuration">
+  <node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
+  <node id="ResetTimestampW"    address="0x1" permission="w" description="" />
+  <node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
+  <node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
+</node>
+<!-- This needs checking. The counters work, not sure about the reset -->
+<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+  <node id="SerdesRstW" address="0x0" permission="w" description="" />
+  <node id="SerdesRstR" address="0x8" permission="r" description="" />
+  <node id="ThrCount0R" address="0x9" permission="r" description="" />
+  <node id="ThrCount1R" address="0xa" permission="r" description="" />
+  <node id="ThrCount2R" address="0xb" permission="r" description="" />
+  <node id="ThrCount3R" address="0xc" permission="r" description="" />
+  <node id="ThrCount4R" address="0xd" permission="r" description="" />
+  <node id="ThrCount5R" address="0xe" permission="r" description="" />
+</node>
+<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+  <node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
+  <node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
+  <node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
+  <node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
+  <!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
+  <!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
+  <node id="TriggerVetoW" address="0x4" permission="w" description="" />
+  <node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
+  <node id="PulseStretchW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x16" permission="r" description="" />
+  <node id="PulseDelayW" address="0x7" permission="w" description="" />
+  <node id="PulseDelayR" address="0x17" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+  <node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
+  <node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
+  <node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
+  <node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
+
+  <!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+  <!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
+
+  <!--
+  <node id="ResetCountersW" address="0x6" permission="w" description="" />
+  <node id="PulseStretchR" address="0x17" permission="r" description="" />
+  <node id="PulseStretchW" address="0x7" permission="w" description="" />
+  <node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
+  <node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
+  <node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
+-->
+</node>
+
+<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+  <node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
+  <node id="LogicRst" address="0x1" permission="w" description="" />
+</node>
+
+<node id="version" address="0x1" description="firmware version" permission="r">
+</node>
+
+<!--
+PulseStretchW			0x00000066     0xffffffff    0    1
+PulseDelayW 			0x00000067     0xffffffff    0    1
+PulseDelayR 			0x00000077     0xffffffff    1    0
+-->
+</node>
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUconnection_BKP.xml b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUconnection_BKP.xml
new file mode 100644
index 0000000000000000000000000000000000000000..fca67f50d932c760c77aa5553bfa983ca8fff249
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/TLUconnection_BKP.xml
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<connections>
+  <connection id="tlu" uri="ipbusudp-2.0://192.168.200.30:50001"
+   address_table="file://./TLUaddrmap.xml" />
+</connections>
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/packages/si5345.py b/AIDA_tlu/projects/TLU_v1e/scripts/packages/si5345.py
new file mode 100644
index 0000000000000000000000000000000000000000..6638d0871eb85280d9255ef4afb5e90f8e76a76f
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/packages/si5345.py
@@ -0,0 +1,152 @@
+import time
+import uhal
+from I2CuHal import I2CCore
+import StringIO
+import csv
+import sys
+
+class si5345:
+    #Class to configure the Si5344 clock generator
+
+    def __init__(self, i2c, slaveaddr=0x68):
+        self.i2c = i2c
+        self.slaveaddr = slaveaddr
+        #self.configList=
+
+    #def writeReg(self, address, data):
+
+    def readRegister(self, myaddr, nwords, verbose= False):
+        ### Read a specific register on the Si5344 chip. There is not check on the validity of the address but
+        ### the code sets the correct page before reading.
+
+        #First make sure we are on the correct page
+        currentPg= self.getPage()
+        requirePg= (myaddr & 0xFF00) >> 8
+        if verbose:
+            print "REG", hex(myaddr), "CURR PG" , hex(currentPg[0]), "REQ PG", hex(requirePg)
+        if currentPg[0] != requirePg:
+            self.setPage(requirePg)
+        #Now read from register.
+        addr=[]
+        addr.append(myaddr)
+        mystop=False
+        self.i2c.write( self.slaveaddr, addr, mystop)
+        # time.sleep(0.1)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        return res
+
+    def writeRegister(self, myaddr, data, verbose=False):
+        ### Write a specific register on the Si5344 chip. There is not check on the validity of the address but
+        ### the code sets the correct page before reading.
+        ### myaddr is an int
+        ### data is a list of ints
+
+        #First make sure we are on the correct page
+        myaddr= myaddr & 0xFFFF
+        currentPg= self.getPage()
+        requirePg= (myaddr & 0xFF00) >> 8
+        #print "REG", hex(myaddr), "CURR PG" , currentPg, "REQ PG", hex(requirePg)
+        if currentPg[0] != requirePg:
+            self.setPage(requirePg)
+        #Now write to register.
+        data.insert(0, myaddr)
+        if verbose:
+            print "  Writing: "
+            result="\t  "
+            for iaddr in data:
+                result+="%#02x "%(iaddr)
+            print result
+        self.i2c.write( self.slaveaddr, data)
+        #time.sleep(0.01)
+
+    def setPage(self, page, verbose=False):
+        #Configure the chip to perform operations on the specified address page.
+        mystop=True
+        myaddr= [0x01, page]
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        #time.sleep(0.01)
+        if verbose:
+            print "  Si5345 Set Reg Page:", page
+
+    def getPage(self, verbose=False):
+        #Read the current address page
+        mystop=False
+        myaddr= [0x01]
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        rPage= self.i2c.read( self.slaveaddr, 1)
+        #time.sleep(0.1)
+        if verbose:
+            print "\tPage read:", rPage
+        return rPage
+
+    def getDeviceVersion(self):
+        #Read registers containing chip information
+        mystop=False
+        nwords=2
+        myaddr= [0x02 ]#0xfa
+        self.setPage(0)
+        self.i2c.write( self.slaveaddr, myaddr, mystop)
+        #time.sleep(0.1)
+        res= self.i2c.read( self.slaveaddr, nwords)
+        print "  Si5345 EEPROM: "
+        result="\t"
+        for iaddr in reversed(res):
+            result+="%#02x "%(iaddr)
+        print result
+        return res
+
+    def parse_clk(self, filename, verbose= False):
+        #Parse the configuration file produced by Clockbuilder Pro (Silicon Labs)
+    	deletedcomments=""""""
+        if verbose:
+    	       print "\tParsing file", filename
+    	with open(filename, 'rb') as configfile:
+    		for i, line in enumerate(configfile):
+    		    if not line.startswith('#') :
+    		      if not line.startswith('Address'):
+    			deletedcomments+=line
+    	csvfile = StringIO.StringIO(deletedcomments)
+    	cvr= csv.reader(csvfile, delimiter=',', quotechar='|')
+    	#print "\tN elements  parser:", sum(1 for row in cvr)
+    	#return [addr_list,data_list]
+        # for item in cvr:
+        #     print "rere"
+        #     regAddr= int(item[0], 16)
+        #     regData[0]= int(item[1], 16)
+        #     print "\t  ", hex(regAddr), hex(regData[0])
+        #self.configList= cvr
+        regSettingList= list(cvr)
+        if verbose:
+            print "\t  ", len(regSettingList), "elements"
+        return regSettingList
+
+    def writeConfiguration(self, regSettingList, verbose= 0):
+        print "  Si5345 Writing configuration:"
+        toolbar_width = 38
+        if (verbose==1):
+            sys.stdout.write("  [%s]" % (" " * toolbar_width))
+            sys.stdout.flush()
+            sys.stdout.write("\b" * (toolbar_width+1)) # return to start of line, after '['
+        #regSettingList= list(regSettingCsv)
+        counter=0
+        for item in regSettingList:
+            regAddr= int(item[0], 16)
+            regData=[0]
+            regData[0]= int(item[1], 16)
+            if (verbose > 1):
+                print "\t", counter, "Reg:", hex(regAddr), "Data:", regData
+            counter += 1
+            self.writeRegister(regAddr, regData, False)
+            if (not(counter % 10) and (verbose==1)):
+                sys.stdout.write("-")
+                sys.stdout.flush()
+        sys.stdout.write("\n")
+        print "\tSi5345 configuration done"
+
+    def checkDesignID(self):
+        regAddr= 0x026B
+        res= self.readRegister(regAddr, 8)
+        result= "  Si5345 design Id:\n\t"
+        for iaddr in res:
+            result+=chr(iaddr)
+        print result
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/si5345.py b/AIDA_tlu/projects/TLU_v1e/scripts/si5345.py
new file mode 120000
index 0000000000000000000000000000000000000000..6763abd80112ebc1f66518a399f8c94feb2b0375
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/si5345.py
@@ -0,0 +1 @@
+./packages/si5345.py
\ No newline at end of file
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.py b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.py
new file mode 100644
index 0000000000000000000000000000000000000000..b06c173e81034fbb9308c5216a2bc7a21bdd78ed
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.py
@@ -0,0 +1,236 @@
+# -*- coding: utf-8 -*-
+# miniTLU test script
+
+#from PyChipsUser import *
+#from FmcTluI2c import *
+import uhal
+import sys
+import time
+from datetime import datetime
+import threading
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from TLU_v1e import TLU
+# Use to have interactive shell
+import cmd
+
+# Use to have config file parser
+import ConfigParser
+
+# Use root
+from ROOT import TFile, TTree, gROOT, AddressOf
+from ROOT import *
+import numpy as numpy
+
+
+## Define class that creates the command user inteface
+class MyPrompt(cmd.Cmd):
+
+    # def do_initialise(self, args):
+    #     """Processes the INI file and writes its values to the TLU. To use a specific file type:\n
+    #     parseIni path/to/filename.ini\n
+    #     (without quotation marks)"""
+    # 	print "COMMAND RECEIVED: PARSE INI"
+    # 	parsed_cfg= self.open_cfg_file(args, "/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localIni.ini")
+    #     try:
+    #         theID = parsed_cfg.getint("Producer.fmctlu", "initid")
+    #         print theID
+    #         theSTRING= parsed_cfg.get("Producer.fmctlu", "ConnectionFile")
+    #         print theSTRING
+    #         #TLU= TLU("tlu", theSTRING, parsed_cfg)
+    #     except IOError:
+    #         print "\t Could not retrieve INI data."
+    #         return
+
+
+    def do_configure(self, args):
+        """Processes the CONF file and writes its values to the TLU. To use a specific file type:\n
+        parseIni path/to/filename.conf\n
+        (without quotation marks)"""
+    	print "==== COMMAND RECEIVED: PARSE CONFIG"
+    	#self.testme()
+        parsed_cfg= self.open_cfg_file(args, "./localConf.conf")
+        try:
+            theID = parsed_cfg.getint("Producer.fmctlu", "confid")
+            print "\t", theID
+            TLU.configure(parsed_cfg)
+        except IOError:
+            print "\t Could not retrieve CONF data."
+            return
+
+    def do_id(self, args):
+        """Interrogates the TLU and prints it unique ID on screen"""
+        TLU.getSN()
+        return
+
+    def do_triggers(self, args):
+        """Interrogates the TLU and prints the number of triggers seen by the input discriminators"""
+        TLU.getChStatus()
+        TLU.getAllChannelsCounts()
+        TLU.getPostVetoTrg()
+        return
+
+    def do_startRun(self, args):
+        """Starts the TLU run. If a number is specified, this number will be appended to the file name as Run_#"""
+    	print "==== COMMAND RECEIVED: STARTING TLU RUN"
+    	#startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno run# specified, using 1"
+            runN= 1
+        else:
+            runN= arglist[0]
+
+        logdata= True
+#        logdata= False
+
+        #TLU.start(logdata)
+        if (TLU.isRunning): #Prevent double start
+            print "  Run already in progress"
+            return
+        else:
+            now = datetime.now().strftime('%Y%m%d_%H%M%S')
+            default_filename = "./datafiles/"+ now + "_tluData_" + str(runN) + ".root"
+            rootFname= default_filename
+            print "OPENING ROOT FILE:", rootFname
+            self.root_file = TFile( rootFname, 'RECREATE' )
+            # Create a root "tree"
+            root_tree = TTree( 'T', 'TLU Data' )
+            #highWord =0
+            #lowWord =0
+            #evtNumber=0
+            #timeStamp=0
+            #evtType=0
+            #trigsFired=0
+            #bufPos = 0
+
+            #https://root-forum.cern.ch/t/long-integer/1961/2
+            gROOT.ProcessLine(
+            "struct MyStruct {\
+               UInt_t     raw0;\
+               UInt_t     raw1;\
+               UInt_t     raw2;\
+               UInt_t     raw3;\
+               UInt_t     raw4;\
+               UInt_t     raw5;\
+               UInt_t     evtNumber;\
+               ULong64_t     tluTimeStamp;\
+               UChar_t     tluEvtType;\
+               UChar_t     tluTrigFired;\
+            };" );
+
+            mystruct= MyStruct()
+
+
+            # Create a branch for each piece of data
+            root_tree.Branch('EVENTS', mystruct, 'raw0/i:raw1/i:raw2/i:raw3/i:raw4/i:raw5/i:evtNumber/i:tluTimeStamp/l:tluEvtType/b:tluTrigFired/b' )
+            # root_tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+            # root_tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+            # root_tree.Branch( 'tluExtWord'   , extWord   , "ExtWord/l")
+            # root_tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+            # root_tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+            # root_tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+            # root_tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+            # root_tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+            #self.root_file.Write()
+
+            daq_thread= threading.Thread(target = TLU.start, args=(logdata, runN, mystruct, root_tree))
+            daq_thread.start()
+
+    def do_endRun(self, args):
+    	"""Stops the TLU run"""
+    	print "==== COMMAND RECEIVED: STOP TLU RUN"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+        else:
+            print "  No run to stop"
+
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "==== COMMAND RECEIVED: QUITTING TLU CONSOLE"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+            print "Terminating run"
+	return True
+
+    def testme(self):
+        print "This is a test"
+
+    def open_cfg_file(self, args, default_file):
+        # Parse the user arguments, attempts to opent the file and performs a (minimal)
+        # check to verify the file exists (but not that its content is correct)
+
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno file specified, using default"
+            fileName= default_file
+            print "\t", fileName
+        else:
+            fileName= arglist[0]
+        if len(arglist) > 1:
+            print "\tinvalid: too many arguments. Max 1."
+            return
+
+        parsed_file = ConfigParser.RawConfigParser()
+        try:
+            with open(fileName) as f:
+                parsed_file.readfp(f)
+                print "\t", parsed_file.sections()
+        except IOError:
+            print "\t Error while parsing the specified file."
+            return
+        return parsed_file
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    print "TLU v1E MAIN"
+    prompt = MyPrompt()
+    prompt.prompt = '>> '
+
+    parsed_ini= prompt.open_cfg_file("", "./localIni.ini")
+    TLU= TLU("tlu", "file://./TLUconnection.xml", parsed_ini)
+
+    ###TLU.configure(parsed_cfg)
+    ###logdata= True
+    ###TLU.start(logdata)
+    ###time.sleep(5)
+    ###TLU.stop(False, False)
+
+    # Start interactive prompt
+    print "=+=================================================================="
+    print "==========================TLU TEST CONSOLE=========================="
+    print "+==================================================================="
+    prompt.cmdloop("Type 'help' for a list of commands.")
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.sh b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.sh
new file mode 100644
index 0000000000000000000000000000000000000000..7bdac31c298a95654e8da0a457a9fcd82a7a30cf
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e.sh
@@ -0,0 +1,26 @@
+#!/bin/bash
+
+echo "=========================="
+CURRENT_DIR=${0%/*}
+echo "CURRENT DIRECTORY: " $CURRENT_DIR
+
+echo "============"
+echo "SETTING PATHS"
+#export PYTHONPATH=$CURRENT_DIR/../../../../../Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+#export PYTHONPATH=~/Python_Scripts/PyChips_1_5_0_pre2A/src:$PYTHONPATH
+#export PYTHONPATH=../../packages:$PYTHONPATH
+export PYTHONPATH=./packages:$PYTHONPATH
+echo "PYTHON PATH= " $PYTHONPATH
+export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
+echo "LD_LIBRARY_PATH= " $LD_LIBRARY_PATH
+export PATH=/usr/bin/:/opt/cactus/bin:$PATH
+echo "PATH= " $PATH
+
+cd $CURRENT_DIR
+
+echo "============"
+echo "STARTING PYTHON SCRIPT FOR TLU"
+#python $CURRENT_DIR/startTLU_v8.py $@
+
+python startTLU_v1e.py $@
+#python testTLU_script.py
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e_merged.py b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e_merged.py
new file mode 100644
index 0000000000000000000000000000000000000000..487b01d917a5fda811536acb765638679ed0ea20
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v1e_merged.py
@@ -0,0 +1,246 @@
+# -*- coding: utf-8 -*-
+# miniTLU test script
+
+#from PyChipsUser import *
+#from FmcTluI2c import *
+import uhal
+import sys
+import time
+from datetime import datetime
+import threading
+# from ROOT import TFile, TTree
+# from ROOT import gROOT
+from datetime import datetime
+
+from TLU_v1e import TLU
+# Use to have interactive shell
+import cmd
+
+# Use to have config file parser
+import ConfigParser
+
+# Use root
+from ROOT import TFile, TTree, gROOT, AddressOf
+from ROOT import *
+import numpy as numpy
+
+
+## Define class that creates the command user inteface
+class MyPrompt(cmd.Cmd):
+
+    # def do_initialise(self, args):
+    #     """Processes the INI file and writes its values to the TLU. To use a specific file type:\n
+    #     parseIni path/to/filename.ini\n
+    #     (without quotation marks)"""
+    # 	print "COMMAND RECEIVED: PARSE INI"
+    # 	parsed_cfg= self.open_cfg_file(args, "/users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localIni.ini")
+    #     try:
+    #         theID = parsed_cfg.getint("Producer.fmctlu", "initid")
+    #         print theID
+    #         theSTRING= parsed_cfg.get("Producer.fmctlu", "ConnectionFile")
+    #         print theSTRING
+    #         #TLU= TLU("tlu", theSTRING, parsed_cfg)
+    #     except IOError:
+    #         print "\t Could not retrieve INI data."
+    #         return
+
+
+    def do_configure(self, args):
+        """Processes the CONF file and writes its values to the TLU. To use a specific file type:\n
+        parseIni path/to/filename.conf\n
+        (without quotation marks)"""
+    	print "==== COMMAND RECEIVED: PARSE CONFIG"
+    	#self.testme()
+        parsed_cfg= self.open_cfg_file(args, "./localConf.conf")
+        try:
+            theID = parsed_cfg.getint("Producer.fmctlu", "confid")
+            print "\t", theID
+            TLU.configure(parsed_cfg)
+        except IOError:
+            print "\t Could not retrieve CONF data."
+            return
+
+    def do_i2c(self, args):
+	arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno command specified"
+        else:
+            i2ccmd= arglist[0]
+            results = list(map(int, arglist))
+	    TLU.DISP.writeSomething(results)
+	    print "Sending i2c command to display"
+	return
+
+    def do_id(self, args):
+        """Interrogates the TLU and prints it unique ID on screen"""
+        TLU.getSN()
+        return
+
+    def do_triggers(self, args):
+        """Interrogates the TLU and prints the number of triggers seen by the input discriminators"""
+        TLU.getChStatus()
+        TLU.getAllChannelsCounts()
+        TLU.getPostVetoTrg()
+        return
+
+    def do_startRun(self, args):
+        """Starts the TLU run. If a number is specified, this number will be appended to the file name as Run_#"""
+    	print "==== COMMAND RECEIVED: STARTING TLU RUN"
+    	#startTLU( uhalDevice = self.hw, pychipsBoard = self.board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno run# specified, using 1"
+            runN= 1
+        else:
+            runN= arglist[0]
+
+        logdata= True
+
+        #TLU.start(logdata)
+        if (TLU.isRunning): #Prevent double start
+            print "  Run already in progress"
+            return
+        else:
+            now = datetime.now().strftime('%Y%m%d_%H%M%S')
+            default_filename = "./datafiles/"+ now + "_tluData_" + str(runN) + ".root"
+            rootFname= default_filename
+            print "OPENING ROOT FILE:", rootFname
+            self.root_file = TFile( rootFname, 'RECREATE' )
+            # Create a root "tree"
+            root_tree = TTree( 'T', 'TLU Data' )
+            #highWord =0
+            #lowWord =0
+            #evtNumber=0
+            #timeStamp=0
+            #evtType=0
+            #trigsFired=0
+            #bufPos = 0
+
+            #https://root-forum.cern.ch/t/long-integer/1961/2
+            gROOT.ProcessLine(
+            "struct MyStruct {\
+               UInt_t     raw0;\
+               UInt_t     raw1;\
+               UInt_t     raw2;\
+               UInt_t     raw3;\
+               UInt_t     raw4;\
+               UInt_t     raw5;\
+               UInt_t     evtNumber;\
+               ULong64_t     tluTimeStamp;\
+               UChar_t     tluEvtType;\
+               UChar_t     tluTrigFired;\
+            };" );
+
+            mystruct= MyStruct()
+
+
+            # Create a branch for each piece of data
+            root_tree.Branch('EVENTS', mystruct, 'raw0/i:raw1/i:raw2/i:raw3/i:raw4/i:raw5/i:evtNumber/i:tluTimeStamp/l:tluEvtType/b:tluTrigFired/b' )
+            # root_tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+            # root_tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+            # root_tree.Branch( 'tluExtWord'   , extWord   , "ExtWord/l")
+            # root_tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+            # root_tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+            # root_tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+            # root_tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+            # root_tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+            #self.root_file.Write()
+
+            daq_thread= threading.Thread(target = TLU.start, args=(logdata, runN, mystruct, root_tree))
+            daq_thread.start()
+
+    def do_endRun(self, args):
+    	"""Stops the TLU run"""
+    	print "==== COMMAND RECEIVED: STOP TLU RUN"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+        else:
+            print "  No run to stop"
+
+
+    def do_quit(self, args):
+        """Quits the program."""
+        print "==== COMMAND RECEIVED: QUITTING TLU CONSOLE"
+        if TLU.isRunning:
+            TLU.isRunning= False
+            TLU.stop(False, False)
+            self.root_file.Write()
+            self.root_file.Close()
+            print "Terminating run"
+	return True
+
+    def testme(self):
+        print "This is a test"
+
+    def open_cfg_file(self, args, default_file):
+        # Parse the user arguments, attempts to opent the file and performs a (minimal)
+        # check to verify the file exists (but not that its content is correct)
+
+        arglist = args.split()
+        if len(arglist) == 0:
+            print "\tno file specified, using default"
+            fileName= default_file
+            print "\t", fileName
+        else:
+            fileName= arglist[0]
+        if len(arglist) > 1:
+            print "\tinvalid: too many arguments. Max 1."
+            return
+
+        parsed_file = ConfigParser.RawConfigParser()
+        try:
+            with open(fileName) as f:
+                parsed_file.readfp(f)
+                print "\t", parsed_file.sections()
+        except IOError:
+            print "\t Error while parsing the specified file."
+            return
+        return parsed_file
+
+# # Override methods in Cmd object ##
+#     def preloop(self):
+#         """Initialization before prompting user for commands.
+#            Despite the claims in the Cmd documentaion, Cmd.preloop() is not a stub.
+#         """
+#         cmd.Cmd.preloop(self)  # # sets up command completion
+#         self._hist = []  # # No history yet
+#         self._locals = {}  # # Initialize execution namespace for user
+#         self._globals = {}
+#         print "\nINITIALIZING"
+#         now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+#         default_filename = './rootfiles/tluData_' + now + '.root'
+#         print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+#         self.manager = uhal.ConnectionManager("file://./connection.xml")
+#         self.hw = self.manager.getDevice("minitlu")
+#         self.device_id = self.hw.id()
+#
+#         # Point to TLU in Pychips
+#         self.bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+#
+#         # Assume DIP-switch controlled address. Switches at 2
+#         self.board = ChipsBusUdp(self.bAddrTab,"192.168.200.32",50001)
+
+
+#################################################
+if __name__ == "__main__":
+    print "TLU v1E MAIN"
+    prompt = MyPrompt()
+    prompt.prompt = '>> '
+
+    parsed_ini= prompt.open_cfg_file("", "./localIni.ini")
+    TLU= TLU("tlu", "file://./TLUconnection.xml", parsed_ini)
+
+    ###TLU.configure(parsed_cfg)
+    ###logdata= True
+    ###TLU.start(logdata)
+    ###time.sleep(5)
+    ###TLU.stop(False, False)
+
+    # Start interactive prompt
+    print "===================================================================="
+    print "==========================TLU TEST CONSOLE=========================="
+    print "===================================================================="
+    prompt.cmdloop("Type 'help' for a list of commands.")
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v6.py b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v6.py
new file mode 100644
index 0000000000000000000000000000000000000000..b7948f204682346e898a3126ac22b3e8aaa310a8
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/startTLU_v6.py
@@ -0,0 +1,232 @@
+#
+# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
+#
+# David Cussans, December 2012
+#
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import uhal
+
+import sys
+
+import time
+
+from datetime import datetime
+
+from optparse import OptionParser
+
+# For single character non-blocking input:
+import select
+import tty
+import termios
+
+from initTLU import *
+
+def isData():
+    return select.select([sys.stdin], [], [], 0) == ([sys.stdin], [], [])
+
+now = datetime.now().strftime('%Y-%m-%dT%H_%M_%S')
+default_filename = 'tluData_' + now + '.root'
+parser = OptionParser()
+
+parser.add_option('-r','--rootFname',dest='rootFname',
+                       default=default_filename,help='Path of output file')
+parser.add_option('-o','--writeTimestamps',dest='writeTimestamps',
+                       default="True",help='Set True to write timestamps to ROOT file')
+parser.add_option('-p','--printTimestamps',dest='printTimestamps',
+                       default="True",help='Set True to print timestamps to screen (nothing printed unless also output to file) ')
+parser.add_option('-s','--listenForTelescopeShutter',dest='listenForTelescopeShutter',
+                       default=False,help='Set True to veto triggers when shutter goes high')
+parser.add_option('-d','--pulseDelay',dest='pulseDelay', type=int,
+                       default=0x00,help='Delay added to input triggers. Four 5-bit numbers packed into 32-bt word, Units of 6.125ns')
+parser.add_option('-w','--pulseStretch',dest='pulseStretch',type=int,
+                       default=0x00,help='Width added to input triggers. Four 5-bit numbers packed into 32-bt word. Units of 6.125ns')
+parser.add_option('-t','--triggerPattern',dest='triggerPattern',type=int,
+                       default=0xFFFEFFFE,help='Pattern match to generate trigger. Two 16-bit words packed into 32-bit word.')
+parser.add_option('-m','--DUTMask',dest='DUTMask',type=int,
+                       default=0x01,help='Three-bit mask selecting which DUTs are active.')
+parser.add_option('-y','--ignoreDUTBusy',dest='ignoreDUTBusy',type=int,
+                       default=0x0F,help='Three-bit mask selecting which DUTs can veto triggers by setting BUSY high. Low = can veto, high = ignore busy.')
+parser.add_option('-i','--triggerInterval',dest='triggerInterval',type=int,
+                       default=0,help='Interval between internal trigers ( in units of 6.125ns ). Set to zero to turn off internal triggers')
+parser.add_option('-v','--thresholdVoltage',dest='thresholdVoltage',type=float,
+                       default=-0.2,help='Threshold voltage for TLU inputs ( units of volts)')
+
+(options, args) = parser.parse_args(sys.argv[1:])
+
+from ROOT import TFile, TTree
+from ROOT import gROOT
+
+print "SETTING UP AIDA TLU TO SUPPLY CLOCK AND TRIGGER TO TORCH READOUT\n"
+
+# Point to board in uHAL
+manager = uhal.ConnectionManager("file://./connection.xml")
+hw = manager.getDevice("minitlu")
+device_id = hw.id()
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+# Assume DIP-switch controlled address. Switches at 2
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Open Root file
+print "OPENING ROOT FILE:", options.rootFname
+f = TFile( options.rootFname, 'RECREATE' )
+
+# Create a root "tree"
+tree = TTree( 'T', 'TLU Data' )
+highWord =0
+lowWord =0
+evtNumber=0
+timeStamp=0
+evtType=0
+trigsFired=0
+bufPos = 0
+
+# Create a branch for each piece of data
+tree.Branch( 'tluHighWord'  , highWord  , "HighWord/l")
+tree.Branch( 'tluLowWord'   , lowWord   , "LowWord/l")
+tree.Branch( 'tluTimeStamp' , timeStamp , "TimeStamp/l")
+tree.Branch( 'tluBufPos'    , bufPos    , "Bufpos/s")
+tree.Branch( 'tluEvtNumber' , evtNumber , "EvtNumber/i")
+tree.Branch( 'tluEvtType'   , evtType   , "EvtType/b")
+tree.Branch( 'tluTrigFired' , trigsFired, "TrigsFired/b")
+
+# Initialize TLU registers
+initTLU( uhalDevice = hw, pychipsBoard = board, listenForTelescopeShutter = options.listenForTelescopeShutter, pulseDelay = options.pulseDelay, pulseStretch = options.pulseStretch, triggerPattern = options.triggerPattern , DUTMask = options.DUTMask, ignoreDUTBusy = options.ignoreDUTBusy , triggerInterval = options.triggerInterval, thresholdVoltage = options.thresholdVoltage )
+
+loopWait = 0.1
+oldEvtNumber = 0
+
+oldPreVetotriggerCount = board.read("PreVetoTriggersR")
+oldPostVetotriggerCount = board.read("PostVetoTriggersR")
+
+oldThresholdCounter0 =0
+oldThresholdCounter1 =0
+oldThresholdCounter2 =0
+oldThresholdCounter3 =0
+
+print "STARTING POLLING LOOP"
+
+eventFifoFillLevel = 0
+loopRunning = True
+runStarted = False
+
+oldTime = time.time()
+
+# Save old terminal settings
+oldTermSettings = termios.tcgetattr(sys.stdin)
+tty.setcbreak(sys.stdin.fileno())
+
+while loopRunning:
+
+    if isData():
+        c = sys.stdin.read(1)
+        print "\tGOT INPUT:", c
+        if c == 't':
+            loopRunning = False
+            print "\tTERMINATING LOOP"
+        elif c == 'c':
+            runStarted = True
+            print "\tSTARTING RUN"
+            startTLU( uhalDevice = hw, pychipsBoard = board,  writeTimestamps = ( options.writeTimestamps == "True" ) )
+        elif c == 'f':
+            # runStarted = True
+            print "\tSTOPPING TRIGGERS"
+            stopTLU( uhalDevice = hw, pychipsBoard = board )
+
+
+    if runStarted:
+
+        eventFifoFillLevel = hw.getNode("eventBuffer.EventFifoFillLevel").read()
+
+        preVetotriggerCount = hw.getNode("triggerLogic.PreVetoTriggersR").read()
+        postVetotriggerCount = hw.getNode("triggerLogic.PostVetoTriggersR").read()
+
+        timestampHigh = hw.getNode("Event_Formatter.CurrentTimestampHR").read()
+        timestampLow  = hw.getNode("Event_Formatter.CurrentTimestampLR").read()
+
+        thresholdCounter0 = hw.getNode("triggerInputs.ThrCount0R").read()
+        thresholdCounter1 = hw.getNode("triggerInputs.ThrCount1R").read()
+        thresholdCounter2 = hw.getNode("triggerInputs.ThrCount2R").read()
+        thresholdCounter3 = hw.getNode("triggerInputs.ThrCount3R").read()
+
+        hw.dispatch()
+
+        newTime = time.time()
+        timeDelta = newTime - oldTime
+        oldTime = newTime
+        #print "time delta = " , timeDelta
+        preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/timeDelta
+        postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/timeDelta
+        oldPreVetotriggerCount = preVetotriggerCount
+        oldPostVetotriggerCount = postVetotriggerCount
+
+        deltaCounts0 = thresholdCounter0 - oldThresholdCounter0
+        oldThresholdCounter0 = thresholdCounter0
+        deltaCounts1 = thresholdCounter1 - oldThresholdCounter1
+        oldThresholdCounter1 = thresholdCounter1
+        deltaCounts2 = thresholdCounter2 - oldThresholdCounter2
+        oldThresholdCounter2 = thresholdCounter2
+        deltaCounts3 = thresholdCounter3 - oldThresholdCounter3
+        oldThresholdCounter3 = thresholdCounter3
+
+        print "pre , post  veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
+
+        print "CURRENT TIMESTAMP HIGH, LOW (hex) = " , hex(timestampHigh) , hex(timestampLow)
+
+        print "Input counts 0,1,2,3 = "      , thresholdCounter0 , thresholdCounter1 , thresholdCounter2 , thresholdCounter3
+        print "Input freq (Hz) 0,1,2,3 = " , deltaCounts0/timeDelta , deltaCounts1/timeDelta , deltaCounts2/timeDelta , deltaCounts3/timeDelta
+
+        nEvents = int(eventFifoFillLevel)//4  # only read out whole events ( 4 x 32-bit words )
+        wordsToRead =  nEvents*4
+
+        print "FIFO FILL LEVEL= " , eventFifoFillLevel
+
+        print "# EVENTS IN FIFO = ",nEvents
+        print "WORDS TO READ FROM FIFO  = ",wordsToRead
+
+        # get timestamp data and fifo fill in same outgoing packet.
+        timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(wordsToRead)
+
+        hw.dispatch()
+
+    #    print timestampData
+        for bufPos in range (0, nEvents ):
+            lowWord  = timestampData[bufPos*4 + 1] + 0x100000000* timestampData[ (bufPos*4) + 0] # timestamp
+
+            highWord = timestampData[bufPos*4 + 3] + 0x100000000* timestampData[ (bufPos*4) + 2] # evt number
+            evtNumber = timestampData[bufPos*4 + 3]
+
+            if evtNumber != ( oldEvtNumber + 1 ):
+                print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ",  evtNumber , oldEvtNumber
+
+            oldEvtNumber = evtNumber
+
+            timeStamp = lowWord & 0xFFFFFFFFFFFF
+
+            evtType = timestampData[ (bufPos*4) + 0] >> 28
+
+            trigsFired = (timestampData[ (bufPos*4) + 0] >> 16) & 0xFFF
+
+            if (options.printTimestamps == "True" ):
+                print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x %03x" % ( bufPos , highWord , lowWord, evtNumber , timeStamp , evtType , trigsFired)
+
+            # Fill root branch - see example in http://wlav.web.cern.ch/wlav/pyroot/tpytree.html : write raw data and decoded data for now.
+            tree.Fill()
+
+    time.sleep( loopWait)
+
+# Fixme - at the moment infinite loop.
+preVetotriggerCount = board.read("PreVetoTriggersR")
+postVetotriggerCount = board.read("PostVetoTriggersR")
+print "EXIT POLLING LOOP"
+print "\nTRIGGER COUNT AT THE END OF RUN [pre, post]:" , preVetotriggerCount , postVetotriggerCount
+
+termios.tcsetattr(sys.stdin, termios.TCSADRAIN, oldTermSettings)
+f.Write()
+f.Close()
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/test.py b/AIDA_tlu/projects/TLU_v1e/scripts/test.py
new file mode 100644
index 0000000000000000000000000000000000000000..ac68201827840fbba1f2dad4c1c9596cba6ea9eb
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/test.py
@@ -0,0 +1,34 @@
+import matplotlib.pyplot as plt
+import numpy as np
+import matplotlib.mlab as mlab
+
+print "TEST.py"
+myFile= "./500ns_23ns.txt"
+
+with open(myFile) as f:
+    nsDeltas = map(float, f)
+
+P= 1000000000 #display in ns
+nsDeltas = [x * P for x in nsDeltas]
+centerRange= 25
+windowsns= 5
+minRange= centerRange-windowsns
+maxRange= centerRange+windowsns
+plt.hist(nsDeltas, 60, range=[minRange, maxRange], facecolor='blue', align='mid', alpha= 0.75)
+#plt.hist(nsDeltas, 100, normed=True, facecolor='blue', align='mid', alpha=0.75)
+#plt.xlim((min(nsDeltas), max(nsDeltas)))
+plt.xlabel('Time (ns)')
+plt.ylabel('Entries')
+plt.title('Histogram DeltaTime')
+plt.grid(True)
+
+#Superimpose Gauss
+mean = np.mean(nsDeltas)
+variance = np.var(nsDeltas)
+sigma = np.sqrt(variance)
+x = np.linspace(min(nsDeltas), max(nsDeltas), 100)
+plt.plot(x, mlab.normpdf(x, mean, sigma))
+print (mean, sigma)
+
+#Display plot
+plt.show()
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/testTLU_script.py b/AIDA_tlu/projects/TLU_v1e/scripts/testTLU_script.py
new file mode 100644
index 0000000000000000000000000000000000000000..9d8b334bb4a6fd01050c3d622f54847616fce208
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/testTLU_script.py
@@ -0,0 +1,79 @@
+# miniTLU test script
+
+from FmcTluI2c import *
+import uhal
+import sys
+import time
+from I2CuHal import I2CCore
+from miniTLU import MiniTLU
+from datetime import datetime
+
+if __name__ == "__main__":
+    print "\tTEST TLU SCRIPT"
+    miniTLU= MiniTLU("minitlu", "file://./connection.xml")
+    #(self, target, wclk, i2cclk, name="i2c", delay=None)
+    TLU_I2C= I2CCore(miniTLU.hw, 10, 5, "i2c_master", None)
+    TLU_I2C.state()
+
+
+    #READ CONTENT OF EEPROM ON 24AA02E48 (0xFA - 0XFF)
+    mystop= 1
+    time.sleep(0.1)
+    myaddr= [0xfa]
+    TLU_I2C.write( 0x50, myaddr, mystop)
+    res=TLU_I2C.read( 0x50, 6)
+    print "Checkin EEPROM:"
+    result="\t"
+    for iaddr in res:
+        result+="%02x "%(iaddr)
+    print result
+
+    #SCAN I2C ADDRESSES
+    #WRITE PROM
+    #WRITE DAC
+
+
+    #Convert required threshold voltage to DAC code
+    #def convert_voltage_to_dac(self, desiredVoltage, Vref=1.300):
+    print("Writing DAC setting:")
+    Vref= 1.300
+    desiredVoltage= 3.3
+    channel= 0
+    i2cSlaveAddrDac = 0x1F
+    vrefOn= 0
+    Vdaq = ( desiredVoltage + Vref ) / 2
+    dacCode = 0xFFFF * Vdaq / Vref
+    dacCode= 0x391d
+    print "\tVreq:", desiredVoltage
+    print "\tDAC code:"  , dacCode
+    print "\tCH:", channel
+    print "\tIntRef:", vrefOn
+
+    #Set DAC value
+    #def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+    if channel<0 or channel>7:
+        print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+        ##return -1
+    if dacCode<0 or dacCode>0xFFFF:
+        print "set_dac ERROR: value",dacCode ,"not in range 0-0xFFFF"
+        ##return -1
+    # AD5665R chip with A0,A1 tied to ground
+    #i2cSlaveAddrDac = 0x1F   # seven bit address, binary 00011111
+
+    # print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+    # dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+    # # if we want to enable internal voltage reference:
+
+    if vrefOn:
+        # enter vref-on mode:
+        print "\tTurning internal reference ON"
+        #dac.write([0x38,0x00,0x01])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x01], 0)
+    else:
+        print "\tTurning internal reference OFF"
+        #dac.write([0x38,0x00,0x00])
+        TLU_I2C.write( i2cSlaveAddrDac, [0x38,0x00,0x00], 0)
+    # Now set the actual value
+    sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
+    print "\tWriting byte sequence:", sequence
+    TLU_I2C.write( i2cSlaveAddrDac, sequence, 0)
diff --git a/AIDA_tlu/projects/TLU_v1e/scripts/test_T0.py b/AIDA_tlu/projects/TLU_v1e/scripts/test_T0.py
new file mode 100644
index 0000000000000000000000000000000000000000..cf81b33d0fcac1767da1923d9abb62634a5885a2
--- /dev/null
+++ b/AIDA_tlu/projects/TLU_v1e/scripts/test_T0.py
@@ -0,0 +1,92 @@
+#
+# Script to exercise AIDA mini-TLU
+#
+# David Cussans, December 2012
+# 
+# Nasty hack - use both PyChips and uHAL ( for block read ... )
+
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+
+# Point to TLU in Pychips
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+# Assume DIP-switch controlled address. Switches at 2 
+board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+firmwareID=board.read("FirmwareId")
+
+print "Firmware (from PyChips) = " , hex(firmwareID)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+ 
+
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+    print "Resetting clocks"
+    board.write("LogicRst", 1 )
+
+    clockStatus = board.read("LogicClocksCSR")
+    print "Clock status after reset = " , hex(clockStatus)
+
+
+board.write("InternalTriggerIntervalW",0)
+
+print "Enabling DUT 0 and 1"
+board.write("DUTMaskW",3)
+DUTMask = board.read("DUTMaskR")
+print "DUTMaskR = " , DUTMask
+
+print "Ignore veto on DUT 0 and 1"
+board.write("IgnoreDUTBusyW",3)
+IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
+print "IgnoreDUTBusyR = " , IgnoreDUTBusy
+
+print "Turning off software trigger veto"
+board.write("TriggerVetoW",0)
+
+print "Reseting FIFO"
+board.write("EventFifoCSR",0x2)
+eventFifoFillLevel = board.read("EventFifoFillLevel")
+print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
+
+print "Enabling data recording"
+board.write("Enable_Record_Data",1)
+
+#print "Enabling handshake: No-handshake"
+#board.write("HandshakeTypeW",1)
+
+#TriggerInterval = 400000
+TriggerInterval = 0
+print "Setting internal trigger interval to " , TriggerInterval
+board.write("InternalTriggerIntervalW",TriggerInterval)  #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+trigInterval = board.read("InternalTriggerIntervalR")
+print "Trigger interval read back as ", trigInterval
+
+print "Setting TPix_maskexternal to ignore external shutter and T0"
+board.write("TPix_maskexternal",0x0003)
+
+numLoops = 500000
+oldEvtNumber = 0
+
+for iLoop in range(0,numLoops):
+
+    board.write("TPix_T0", 0x0001)
+
+#   time.sleep( 1.0)
diff --git a/AIDA_tlu/scripts/build_tlu_firmware.sh b/AIDA_tlu/scripts/build_tlu_firmware.sh
new file mode 100755
index 0000000000000000000000000000000000000000..15f5fdf6328c43ac34ebafcd9dcc01eb9eace7d2
--- /dev/null
+++ b/AIDA_tlu/scripts/build_tlu_firmware.sh
@@ -0,0 +1,51 @@
+#!/bin/sh
+mkdir work
+cd work
+git clone git@github.com:ipbus/ipbb.git 
+# ( ... or curl -L https://github.com/ipbus/ipbb/archive/v0.2.5.tar.gz | tar xvz )
+source ipbb/env.sh
+ipbb init build
+cd build
+ipbb add git https://github.com/ipbus/ipbus-firmware.git -b enhancement/28
+ipbb add git git@github.com:DavidCussans/firmware_AIDA.git
+
+
+# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
+echo "Generating address table VHDL from XML file"
+pushd src/firmware_AIDA/projects/TLU_v1e/addr_table
+pwd
+/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
+#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/firmware_AIDA/projects/TLU_v1e/firmware/hdl/
+cp ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
+popd
+
+# Edit the files in the IPBus repostitory to expose the 200MHz clock
+echo "BUILD: Editing enclustra_ax3_pm3_infra.vhd to add 200MHz clock port"
+sed -i 's/onehz);/onehz); clk_200_o<=clk200;/' src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
+
+echo "BUILD: Editing enclustra_ax3_pm3_infra.vhd to add signals"
+sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
+
+# Comment out the cfg signals in the IPBus constraints file enclustra_ax3_pm3.tcl
+echo "BUILD: patching /enclustra_ax3_pm3.patch"
+pushd src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf
+patch  <  ../../../../../../../firmware_AIDA/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
+popd
+
+echo "BUILD: ipbb proj create"
+ipbb proj create vivado TLU_1e firmware_AIDA:projects/TLU_v1e -t top_tlu_1e_a35.dep
+cd proj/TLU_1e
+
+ipbb vivado project
+# Set correct file as design "top"
+#echo "BUILD: Setting the correct design as top"
+#vivado -mode tcl -nojournal -nolog -notrace -source ../../src/firmware_AIDA/projects/TLU_v1e/firmware/cfg/set_top.tcl top/top.xpr
+
+
+echo "BUILD: ipbb impl"
+ipbb vivado impl
+echo "BUILD: ipbb bitfile"
+ipbb vivado bitfile
+echo "BUILD: ipbb package"
+ipbb vivado package
+deactivate