diff --git a/firmware/minitlu/Introduction.markdown b/firmware/minitlu/Introduction.markdown
new file mode 100644
index 0000000000000000000000000000000000000000..474bbb1d17c1503015d63378c3131b97ec900e69
--- /dev/null
+++ b/firmware/minitlu/Introduction.markdown
@@ -0,0 +1,50 @@
+Introduction to AIDA FMC Mini-TLU {#mainpage}
+=================================
+
+The TLU provides different parts of a Particle Physics Beam-Test
+system with the information they need to synchronize data taken with
+different detectors. The detectors are also refered to as Devices
+Under Test (DUT).
+
+Functions of TLU
+----------------
+
+- Trigger.
+
+ The TLU can combine signals from detectors in the beam-line ( often
+ scintillation detectors ) to produce a trigger that is sent to the
+ different DUT. Each DUT can indicate to the TLU that it is busy and
+ unable to take any further data.
+
+- Particle Timestamping
+
+ The arrival time of every pulse from the beam-detectors is recorded.
+
+- Clock and Synchronization Signals.
+
+ The TLU produces clock and synchronization signals that allow the
+ internal counters of different DUT to be sychronized.
+
+N.B. Not all the functions of the TLU may be used in a given beam-test
+system. For example, it is common to only use the Trigger/Busy
+function of the TLU.
+
+Firmare Structure
+-----------------
+
+The firmware is almost exclusively written in VHDL. The top level
+entitity is [top_extphy](top_extphy_struct)
+
+The HDL-Designer package by Mentor graphics has been used to develop
+some of the code, mainly the top-level structure. However, is is not
+necessary to use HDL-Designer to build the firmware. In fact the VHDL
+files produced by HDL-Designer can also be edited "by hand" without
+using the tool.
+
+A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
+
+Building Firmware
+-----------------
+
+Instructions on building the firmware are found
+[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
diff --git a/firmware/minitlu/config/ise14/sp601/build_bitstream.tcl b/firmware/minitlu/config/ise14/sp601/build_bitstream.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..baa74278a84639be4bba32f41963e341c0040bb3
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp601/build_bitstream.tcl
@@ -0,0 +1,21 @@
+project open fmc-mtlu
+
+puts "Regenerating cores"
+cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
+catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
+catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
+
+catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
+catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
+# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
+
+
+process run "Synthesize"
+process run "Translate"
+process run "Map"
+process run "Place & Route"
+
+process run "Generate Programming File"
+
+project close
diff --git a/firmware/minitlu/config/ise14/sp601/coregen.cgp b/firmware/minitlu/config/ise14/sp601/coregen.cgp
new file mode 100644
index 0000000000000000000000000000000000000000..cf20ca969f275f32ff9f8d2d7182d3d6d367b2a6
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp601/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx16
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = csg324
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
diff --git a/firmware/minitlu/config/ise14/sp601/file_list b/firmware/minitlu/config/ise14/sp601/file_list
new file mode 100644
index 0000000000000000000000000000000000000000..48333c9339b119e5a8f6028e441ec12f327613d7
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp601/file_list
@@ -0,0 +1,5 @@
+hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
+include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
+include ipbus/firmware/ipbus_core/cfg/file_list
+
+
diff --git a/firmware/minitlu/config/ise14/sp601/setup_project.tcl b/firmware/minitlu/config/ise14/sp601/setup_project.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..32dac7e1fadaae7acb7c9d13e932b617f92f0856
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp601/setup_project.tcl
@@ -0,0 +1,151 @@
+project new fmc-mtlu
+project set family spartan6
+project set device xc6slx16
+project set package csg324
+project set speed -3
+
+project set "Enable Multi-Threading" "2" -process "Map"
+project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
+project set "Enable Multi-Threading" "2" -process "Place & Route"
+project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
+project set "Preferred Language" "VHDL"
+
+# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
+
+# Just list files by hand for now. Can't get addfiles.tcl to work.
+
+#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
+# IPBus Ethernet for gig_eth_pcs_pma_v11_5
+xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+
+puts "Adding and Regenerating Ethernet cores"
+# Add cores for Ethernet
+exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
+exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
+xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
+xfile add ipcore_dir/mac_fifo_axi4.xco
+
+# Don't regenerate cores for now...
+#cd ipcore_dir
+#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
+#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
+#cd ..
+
+puts "Adding IPBus files"
+# Xilinx ISE setup fragment for ipbus core
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
+
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
+#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+
+# Add Opencores files for i2c interface
+xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
+xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
+xfile add external/opencores_i2c/i2c_master_registers.vhd
+xfile add external/opencores_i2c/i2c_master_top.vhd
+
+# Add TLU cores....
+# Add cores for Ethernet
+
+puts "Adding and Regenerating TLU cores"
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
+
+xfile add ipcore_dir/tlu_event_fifo.xco
+xfile add ipcore_dir/FIFO.xco
+# xfile add ipcore_dir/CounterUp.xco
+xfile add ipcore_dir/internalTriggerGenerator.xco
+
+# Don't regenerate cores for now...
+#cd ipcore_dir
+#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
+#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
+#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
+#cd ..
+
+puts "Adding TLU Files "
+# Add FMC-MTLU files. First the hand-written VHDL
+xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
+xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+# xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
+xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
+
+# Then add the HDL-Designer generated files..
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+
+
+
+# Add user constraints file
+# UCF for TLU with FMC connector wrong way round.
+#xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU.ucf
+# bug-fixed TLU:
+xfile add fmc-mtlu/firmware/ucf/sp601_FMC_mTLU_v1a.ucf
+
+project close
+
+puts "Successfully finished building project file"
diff --git a/firmware/minitlu/config/ise14/sp605/build_bitstream.tcl b/firmware/minitlu/config/ise14/sp605/build_bitstream.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..baa74278a84639be4bba32f41963e341c0040bb3
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp605/build_bitstream.tcl
@@ -0,0 +1,21 @@
+project open fmc-mtlu
+
+puts "Regenerating cores"
+cd $::env(FW_WORKSPACE)/workspace/ipcore_dir
+catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
+catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
+
+catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
+catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
+# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
+
+
+process run "Synthesize"
+process run "Translate"
+process run "Map"
+process run "Place & Route"
+
+process run "Generate Programming File"
+
+project close
diff --git a/firmware/minitlu/config/ise14/sp605/coregen.cgp b/firmware/minitlu/config/ise14/sp605/coregen.cgp
new file mode 100644
index 0000000000000000000000000000000000000000..620061f25204f155090e2690ebb41585830e44ee
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp605/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = fgg484
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
diff --git a/firmware/minitlu/config/ise14/sp605/file_list b/firmware/minitlu/config/ise14/sp605/file_list
new file mode 100644
index 0000000000000000000000000000000000000000..48333c9339b119e5a8f6028e441ec12f327613d7
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp605/file_list
@@ -0,0 +1,5 @@
+hdl ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
+include ipbus/firmware/ethernet/cfg/file_list_s6_extphy
+include ipbus/firmware/ipbus_core/cfg/file_list
+
+
diff --git a/firmware/minitlu/config/ise14/sp605/setup_project.tcl b/firmware/minitlu/config/ise14/sp605/setup_project.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bd2aa6d3766ef9e42ae154d1742d6ff6a65c8aa2
--- /dev/null
+++ b/firmware/minitlu/config/ise14/sp605/setup_project.tcl
@@ -0,0 +1,153 @@
+project new fmc-mtlu
+project set family spartan6
+project set device xc6slx45t
+project set package fgg484
+project set speed -3
+
+project set "Enable Multi-Threading" "2" -process "Map"
+project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" -process "Map"
+project set "Enable Multi-Threading" "2" -process "Place & Route"
+project set "Enable BitStream Compression" TRUE -process "Generate Programming File"
+project set "Preferred Language" "VHDL"
+project set "Set SPI Configuration Bus Width spartan6" 4
+
+# source $::env(REPOS_FW_DIR)/firmware/example_designs/scripts/addfiles.tcl
+
+# Just list files by hand for now. Can't get addfiles.tcl to work.
+
+#xfile add ipbus/firmware/example_designs/hdl/clocks_s6_extphy.vhd
+# IPBus Ethernet for gig_eth_pcs_pma_v11_5
+xfile add ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+xfile add ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+
+puts "Adding and Regenerating Ethernet cores"
+# Add cores for Ethernet
+exec cp ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco ipcore_dir
+exec cp ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco ipcore_dir
+xfile add ipcore_dir/tri_mode_eth_mac_v5_4.xco
+xfile add ipcore_dir/mac_fifo_axi4.xco
+
+# Don't regenerate cores for now...
+#cd ipcore_dir
+#catch {exec coregen -r -b tri_mode_eth_mac_v5_4.xco -p coregen.cgp}
+#catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
+#cd ..
+
+puts "Adding IPBus files"
+# Xilinx ISE setup fragment for ipbus core
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
+
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
+#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+
+# Add Opencores files for i2c interface
+xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
+xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
+xfile add external/opencores_i2c/i2c_master_registers.vhd
+xfile add external/opencores_i2c/i2c_master_top.vhd
+
+# Add TLU cores....
+# Add cores for Ethernet
+
+puts "Adding and Regenerating TLU cores"
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
+exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
+
+xfile add ipcore_dir/tlu_event_fifo.xco
+xfile add ipcore_dir/FIFO.xco
+#xfile add ipcore_dir/CounterUp.xco
+xfile add ipcore_dir/internalTriggerGenerator.xco
+
+# Don't regenerate cores for now...
+#cd ipcore_dir
+#catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
+#catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
+#catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+#catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
+#cd ..
+
+puts "Adding TLU Files "
+# Add FMC-MTLU files. First the hand-written VHDL
+xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
+xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
+xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
+xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/TPx3Logic_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
+
+
+# Then add the HDL-Designer generated files..
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+
+
+
+# Add user constraints file
+xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a.ucf
+
+project close
+
+puts "Successfully finished building project file"
diff --git a/firmware/minitlu/hdl/common/DUTInterfaces_rtl.vhd b/firmware/minitlu/hdl/common/DUTInterfaces_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..590c177dc2066d62f79fa9a9e9320b2036b1119a
--- /dev/null
+++ b/firmware/minitlu/hdl/common/DUTInterfaces_rtl.vhd
@@ -0,0 +1,277 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:09:50 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--! Address map:\n
+--! 5-bit decoded
+--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
+--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
+--!
+--
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+
+ENTITY DUTInterfaces IS
+ GENERIC(
+ g_NUM_DUTS : positive := 3;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ clk_4x_logic_i : IN std_logic;
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
+ ipbus_reset_i : IN std_logic;
+ strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
+ --trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
+ clk_to_dut_i : IN std_logic ; -- ! clock to DUT
+ reset_or_clk_to_dut_i : IN std_logic;
+ AIDAhandshake_i : IN std_logic; -- AIDA/EUDET handshake
+ ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
+ clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ veto_o : OUT std_logic -- goes high when one or more DUT are busy
+ );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+ signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
+ signal s_veto : std_logic;
+ signal s_strobe_4x_logic_d1 : std_logic;
+ signal s_clk_to_DUT , s_busy_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut : std_logic_vector(g_NUM_DUTS-1 downto 0);
+ signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
+ signal s_clk_is_input, s_clk_is_input_b : std_logic := '0'; --! Indicates the direction of the clock in the RJ45 DUT
+ signal s_clk_to_tlu : std_logic := '0';
+
+ constant c_N_CTRL : positive := 1;
+ constant c_N_STAT : positive := 1;
+ signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+ signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+BEGIN
+
+
+ -- Dummy code.
+ s_intermediate_busy_or(0) <= '0';
+ --s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
+
+ -----------------------------------------------------------------------------
+ -- IPBus interface
+ -----------------------------------------------------------------------------
+ ipbus_registers: entity work.ipbus_ctrlreg_v
+ generic map(
+ N_CTRL => c_N_CTRL,
+ N_STAT => c_N_STAT
+ )
+ port map(
+ clk => ipbus_clk_i,
+ reset=> '0',--ipbus_reset_i ,
+ ipbus_in=> ipbus_i,
+ ipbus_out=> ipbus_o,
+ d=> s_sync_status_to_ipbus,
+ q=> s_control_from_ipbus,
+ stb=> open
+ );
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_status: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_STAT )
+ port map (
+ clk_input_i => clk_4x_logic_i,
+ data_i => s_status_to_ipbus,
+ data_o => s_sync_status_to_ipbus,
+ clk_output_i => ipbus_clk_i);
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_ctrl: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_4x_logic_i);
+
+ -- Map the control registers
+ s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+
+ -- Map the status registers
+ s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+
+
+ -- These instances need to be out of the loop because the RJ45 permits a bidirectional clock
+ clk_to_DUT_OBUFDS_inst_0 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => clk_to_dut_p_o(0), -- Diff_p output (connect directly to top-level port)
+ OB => clk_to_dut_n_o(0), -- Diff_n output (connect directly to top-level port)
+ I => s_clk_to_dut(0) -- Buffer output
+ );
+ clk_to_DUT_OBUFDS_inst_1 : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => clk_to_dut_p_o(1), -- Diff_p output (connect directly to top-level port)
+ OB => clk_to_dut_n_o(1), -- Diff_n output (connect directly to top-level port)
+ I => s_clk_to_dut(1) -- Buffer output
+ );
+ clk_to_DUT_OBUFDS_inst_2 : IOBUFDS
+ generic map (
+ IOSTANDARD => "BLVDS_25")
+ port map (
+ O => s_clk_to_tlu, -- Buffer output
+ IO => clk_to_dut_p_o(2), -- Diff_p inout (connect directly to top-level port)
+ IOB => clk_to_dut_n_o(2), -- Diff_n inout (connect directly to top-level port)
+ I => s_clk_to_dut(2), -- Buffer input
+ T => s_clk_is_input_b -- 3-state enable input, high=input, low=output
+ );
+ s_clk_is_input <= not AIDAhandshake_i;
+
+
+ --When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
+ --also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
+ --output.
+ ddr_for_clk_to_DUT_tristate : ODDR2
+ generic map(
+ DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
+ INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+ SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+ port map (
+ Q => s_clk_is_input_b, -- 1-bit output data
+ C0 => clk_to_dut_i, -- 1-bit clock input
+ C1 => not clk_to_dut_i, --not s_clk160_internal, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D0 => s_clk_is_input, -- 1-bit data input (associated with C0)
+ D1 => s_clk_is_input, -- 1-bit data input (associated with C1)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ duts: for dut in 1 to g_NUM_DUTS generate
+
+ busy_IBUFDS_inst : IBUFDS
+ generic map (
+ DIFF_TERM => TRUE, -- Differential Termination
+ IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => s_busy_from_dut(dut-1), -- Buffer output
+ I => busy_from_dut_p_i(dut-1), -- Diff_p buffer input (connect directly to top-level port)
+ IB => busy_from_dut_n_i(dut-1) -- Diff_n buffer input (connect directly to top-level port)
+ );
+
+
+ trig_OBUFDS_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => trigger_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
+ OB => trigger_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
+ I => s_trigger_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
+ );
+
+ clk_rst_OBUFDS_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => reset_or_clk_to_dut_p_o(dut-1), -- Diff_p output (connect directly to top-level port)
+ OB => reset_or_clk_to_dut_n_o(dut-1), -- Diff_n output (connect directly to top-level port)
+ I => reset_or_clk_to_dut_i --s_reset_or_clk_to_dut(dut-1) and s_DUT_mask(dut-1) -- Buffer input
+ );
+
+ s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
+ (s_busy_from_dut(dut-1) and
+ s_DUT_mask(dut-1));
+
+
+ ddr_for_clk_output : ODDR2
+ generic map(
+ DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
+ INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+ SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+ port map (
+ Q => s_clk_to_dut(dut-1), -- 1-bit output data
+ C0 => clk_to_dut_i, -- 1-bit clock input
+ C1 => not clk_to_dut_i, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D0 => '1', -- 1-bit data input (associated with C0)
+ D1 => '0', -- 1-bit data input (associated with C1)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ end generate duts;
+
+ s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
+
+ -- purpose: register for internal signals and output signals
+ -- type : combinational
+ -- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
+ -- outputs: veto_o
+ register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
+ begin -- process register_signals
+ if rising_edge(clk_4x_logic_i) then
+ veto_o <= s_veto;
+ s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
+ --s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
+ s_trigger_to_dut <= ( others => trigger_i );
+ --shutter_to_dut <= ( others => shutter_i );
+ end if;
+ end process register_signals;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/GPL_doxygen_header.vhdl b/firmware/minitlu/hdl/common/GPL_doxygen_header.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d1fb4cc77bda49970035bafce322eb023a93c257
--- /dev/null
+++ b/firmware/minitlu/hdl/common/GPL_doxygen_header.vhdl
@@ -0,0 +1,78 @@
+--! @file dtype_fds.vhdl
+--
+-------------------------------------------------------------------------------
+-- --
+-- (c) University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+--
+-- This file is part of IPBus.
+--
+-- IPBus is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- IPBus is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
+--
+-- IPBus is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- IPBus is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with IPBus. If not, see <http://www.gnu.org/licenses/>.
+--
+--
+--! Standard library
+library IEEE;
+
+-- Standard logic defintions.
+use IEEE.STD_LOGIC_1164.all;
+
+--
+-- unit name: dtype_fds
+--
+--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
diff --git a/firmware/minitlu/hdl/common/GPP_rtl.vhd b/firmware/minitlu/hdl/common/GPP_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bc02a5efb0ee30d0bdc486bac320ba25b6c7f611
--- /dev/null
+++ b/firmware/minitlu/hdl/common/GPP_rtl.vhd
@@ -0,0 +1,312 @@
+--=============================================================================
+--! @file GPP_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+--
+--
+--! @brief GPP - General purpose pulser. Generates a sycronous custom pulse \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 15:42:31 01/15/2013
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity GPP is
+ GENERIC(
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT( clk_i : IN std_logic; --! Rising edge active
+ Enable_i : IN std_logic; --
+ Reset_i : IN std_logic; --
+ RstPulsCnt_i : IN std_logic; -- Reset pulse counter
+ Trigger_i : IN std_logic; -- Trigger input signal
+ NMaxPulses_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Max number of pulses
+ SuDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Startup dead time
+ PulsLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse length
+ IpDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Interpulse dead time
+ RearmTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Time before rearm after reach the max number of pulses
+ Force_PullDown_i : IN std_logic; -- Force pull down
+ WU_i : IN std_logic; -- Output trigger signal with update
+ PulseDelay_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse delay
+ event_number_o : OUT std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Event number
+ MaxPulses_o : OUT std_logic; -- Maximun number of pulses reached
+ Pulse_o : OUT std_logic; --! pulse output
+ Pulse_d_o : OUT std_logic --! pulse output delayed
+ );
+end GPP;
+
+architecture rtl of GPP is
+ --! FSM state values
+ type state_values is (st0, st1, st2, st3, st4, st5, st6);
+ signal pres_state, next_state: state_values;
+
+ signal s_PulsCnt_en : std_logic := '0'; --! Pulse counter enable
+ signal s_RstPulsCnt : std_logic := '0'; --! Reset pulse counter
+ signal s_RstPulsCnt_int : std_logic := '0'; --! Reset pulse counter internal signal
+ signal s_PulsLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Pulse Length
+ signal s_PulsCnt : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Pulse counter value
+ signal s_MaxPulses : std_logic := '0'; --! Max number of pulses reached
+ signal s_Pulse : std_logic := '0'; --! Active pulse signal
+ signal s_Pulse_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others=>'0'); --! Active pulse signal delayed
+
+ signal s_load_SuDTime : std_logic := '1'; --! Counter load signal
+ signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
+ signal EOSDT : std_logic := '0'; --! End of startup dead time signal
+
+ signal s_load_PulsLen : std_logic := '1'; --! Counter load
+ signal EOP : std_logic := '0'; --! End of pulse length signal
+
+ signal s_load_IpDTime : std_logic := '1'; --! Counter load signal
+ signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Interpulse dead time counter
+ signal EOIDT : std_logic := '0'; --! End of interpulse dead time signal
+
+ signal s_load_RearmTime : std_logic := '1'; --! Rearm counter load signal
+ signal s_RearmLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
+ signal EOREARM : std_logic := '0'; --! End of startup dead time signal
+
+begin
+ -----------------------------------------------------------------------------
+ -- Counters
+ -----------------------------------------------------------------------------
+ --! Startup dead time counter
+ c_startup_dtime : entity work.CounterDown
+ generic map(
+ MAX_WIDTH => g_IPBUS_WIDTH
+ )
+ port map(
+ Clk => clk_i,
+ Reset => '0',
+ Load => s_load_SuDTime,
+ InitVal => std_logic_vector(unsigned(s_SuDTime)-1),
+ Count => open,
+ Q => EOSDT
+ );
+ s_SuDTime <= x"00000001" when SuDTime_i = x"00000000" -- At least one clock cycle pulse is generated
+ else SuDTime_i;
+
+ --! Pulse time counter
+ c_pulse_time : entity work.CounterDown
+ generic map(
+ MAX_WIDTH => g_IPBUS_WIDTH
+ )
+ port map(
+ Clk => clk_i,
+ Reset => '0',
+ Load => s_load_PulsLen,
+ InitVal => std_logic_vector(unsigned(s_PulsLen)-1),
+ Count => open,
+ Q => EOP
+ );
+ s_PulsLen <= x"00000001" when PulsLen_i = x"00000000" -- At least one clock cycle pulse is generated
+ else PulsLen_i;
+
+ --! Interpulse dead time counter
+ c_interpulse_dtime : entity work.CounterDown
+ generic map(
+ MAX_WIDTH => g_IPBUS_WIDTH
+ )
+ port map(
+ Clk => clk_i,
+ Reset => '0',
+ Load => s_load_IpDTime,
+ InitVal => std_logic_vector(unsigned(s_IpDTime)-1),
+ Count => open,
+ Q => EOIDT
+ );
+ s_IpDTime <= x"00000001" when IpDTime_i = x"00000000" -- At least one clock cycle pulse is generated
+ else IpDTime_i;
+
+ --! Rearm time after the max pulses reached
+ c_rearm_dtime : entity work.CounterDown
+ generic map(
+ MAX_WIDTH => g_IPBUS_WIDTH
+ )
+ port map(
+ Clk => clk_i,
+ Reset => '0',
+ Load => s_load_RearmTime,
+ InitVal => std_logic_vector(unsigned(s_RearmLen)-1),
+ Count => open,
+ Q => EOREARM
+ );
+ s_RearmLen <= x"00000001" when RearmTime_i = x"00000000" -- At least one clock cycle pulse is generated
+ else RearmTime_i;
+
+
+ --! FSM register
+ statereg: process(clk_i, Enable_i, Reset_i)
+ begin
+ if Enable_i = '0' then
+ pres_state <= st0; -- Move to st0 - INITIAL STATE
+
+ elsif Reset_i = '1' then
+ pres_state <= st0; -- Move to st0 - INITIAL STATE
+
+ elsif rising_edge(clk_i) then
+ pres_state <= next_state; -- Move to next state
+
+ end if;
+ end process statereg;
+
+
+ --! FSM combinational block
+ fsm: process(pres_state, Enable_i, Reset_i, Trigger_i, s_MaxPulses, EOP, EOSDT, EOIDT, Force_PullDown_i)
+ begin
+ next_state <= pres_state;
+ -- Default values
+ s_Pulse <= '0';
+ s_load_SuDTime <= '1';
+ s_load_PulsLen <= '1';
+ s_load_IpDTime <= '1';
+ s_load_RearmTime <= '1';
+ s_RstPulsCnt_int <= '0';
+
+ case pres_state is
+
+ -- st0 - INITIAL STATE
+ when st0=>
+ if (Enable_i = '1') and (Reset_i = '0') then
+ next_state <= st1; -- Next state is "st1 - IDLE"
+ end if;
+
+ -- st1 - IDLE STATE
+ when st1=>
+ if s_MaxPulses = '1' then
+ next_state <= st5; -- Next state is "st5 - NMAX PULSES REACHED"
+ else
+ if Trigger_i = '1' and Force_PullDown_i = '0' then
+ if (to_integer(unsigned(SuDTime_i)) = 0) then
+ next_state <= st3; -- Next state is "st3 - PULSE"
+ else
+ next_state <= st2; -- Next state is "st2 - STARTUP DEAD-TIME"
+ end if;
+ end if;
+ end if;
+
+ -- st2 - STARTUP DEAD-TIME
+ when st2=>
+ s_load_SuDTime <= '0';
+ if EOSDT = '1' then
+ next_state <= st3; -- Next state is "st3 - PULSE"
+ end if;
+
+ -- st3 - PULSE
+ when st3=>
+ s_Pulse <= '1';
+ s_load_PulsLen <= '0';
+
+ if (EOP = '1') or (Force_PullDown_i = '1')then
+ if (to_integer(unsigned(IpDTime_i)) = 0) then
+ next_state <= st1; -- Next state is "st1 - IDLE"
+ else
+ next_state <= st4; -- Next state is "st4 - INTERPULSE DEAD-TIME"
+ end if;
+ end if;
+
+ if Trigger_i = '1' then
+ if (WU_i = '1') then
+ next_state <= st6; -- Next state is "st6 - RELOAD PULSE TIMER"
+ end if;
+ end if;
+
+
+ -- st4 - INTERPULSE DEAD-TIME
+ when st4=>
+ s_load_IpDTime <= '0';
+ if EOIDT = '1' then
+ next_state <= st1; -- Next state is "st1 - IDLE"
+ end if;
+
+ -- st5 - NMAX PULSES REACHED
+ when st5=>
+ s_load_RearmTime <= '0';
+ if EOREARM = '1' then
+ next_state <= st1; -- Next state is "st1 - IDLE"
+ s_RstPulsCnt_int <= '1';
+ end if;
+
+ -- st6 - RELOAD PULSE TIMER
+ when st6=>
+ s_Pulse <= '1';
+ next_state <= st3; -- Next state is "st3 - PULSE"
+
+-- when others=>
+-- next_state<=st0; -- Next state is "st0 - INITIAL STATE"
+
+ end case;
+
+ end process fsm;
+
+ -- Pulse reg
+ p_reg_pulse : process ( clk_i , Reset_i )
+ begin
+ if Reset_i = '1' then
+ s_Pulse_d <= (others => '0');
+
+ elsif rising_edge(clk_i) then
+ for i in 0 to g_IPBUS_WIDTH-2 loop
+ s_Pulse_d(i+1) <= s_Pulse_d(i);
+ end loop;
+ s_Pulse_d(0) <= s_Pulse;
+ end if;
+ end process p_reg_pulse;
+
+ event_number_o <= std_logic_vector(s_PulsCnt);
+ MaxPulses_o <= s_MaxPulses;
+ Pulse_o <= s_Pulse;
+ Pulse_d_o <= s_Pulse when PulseDelay_i = x"00000000" else
+ s_Pulse_d(to_integer(unsigned(PulseDelay_i)-1));
+
+
+ -----------------------------------------------------------------------------
+ -- Count runs and synchronization
+ -----------------------------------------------------------------------------
+ p_PulsCounter : process (clk_i )
+ begin -- process p_run_counter
+
+ if rising_edge(clk_i) then
+ if s_RstPulsCnt = '1' then
+ s_PulsCnt <= (others => '0');
+ elsif s_PulsCnt_en = '1' then
+ s_PulsCnt <= s_PulsCnt + 1;
+ end if;
+
+ end if;
+ end process p_PulsCounter;
+
+ s_RstPulsCnt <= Reset_i or RstPulsCnt_i or s_RstPulsCnt_int;
+ s_PulsCnt_en <= '1' when (s_Pulse = '1') and (s_Pulse_d(0) = '0') and (s_MaxPulses = '0')
+ else '0';
+ s_MaxPulses <= '1' when (s_PulsCnt = unsigned(NMaxPulses_i)) and (NMaxPulses_i /= x"00000000")
+ else '0';
+
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/IODELAYCal_FSM_rtl.vhd b/firmware/minitlu/hdl/common/IODELAYCal_FSM_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d69931d3dd04bfae2a5f4876c7984d6ebf0e28f
--- /dev/null
+++ b/firmware/minitlu/hdl/common/IODELAYCal_FSM_rtl.vhd
@@ -0,0 +1,102 @@
+--=============================================================================
+--! @file IODELAYCal_FSM_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- UoB , USC
+-- --
+------------------------------------------------------------------------------- --
+--
+--! @brief Finite-state machine to control calibration and reset signals to
+--! Iserdes, IDelay
+--! based on code by Alvaro Dosil\n
+--
+--! @author Alvaro Dosil
+--
+--! @date 22/Feb/2014
+--
+--! @version v0.1
+--
+--! @details
+--
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--! <another thing to do> \n
+
+ LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity IODELAYCal_FSM is
+ port (
+ clk_i : in std_logic; --! Global clock
+ startcal_i : in std_logic; --! Start calibration
+ busy_i : in std_logic; --! Status of the IDELAY component
+ calibrate_o : out std_logic; --! Calibration signals to IODELAY
+ reset_o : out std_logic --! Reset to IODELAY component
+ );
+end entity IODELAYCal_FSM;
+
+architecture rtl of IODELAYCal_FSM is
+
+ --! Calibration FSM state values
+ type state_values is (st0, st1, st2, st3);
+ signal pres_state, next_state: state_values := st0;
+
+ signal s_cal_FSM : std_logic := '0'; -- IODELAY reset
+ signal s_rst_FSM : std_logic := '0'; -- IODELAY reset
+
+begin -- rtl
+
+ --! Calibration FSM register
+ statereg: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ pres_state <= next_state; -- Move to next state
+
+ end if;
+ end process statereg;
+
+
+ --! Calibration FSM combinational block
+ fsm: process(pres_state, startcal_i, busy_i)
+ begin
+ next_state <= pres_state;
+ -- Default values
+ s_Rst_FSM <= '0';
+ s_cal_FSM <= '0';
+
+ case pres_state is
+
+ -- st0 - IDLE
+ when st0=>
+ if ( startcal_i = '1') then
+ next_state <= st1; -- Next state is "st1 - SEND CALIBRATION SIGNAL"
+ end if;
+
+ -- st1 - SEND CALIBRATION SIGNAL
+ when st1=>
+ s_cal_FSM <= '1';
+ next_state <= st2; -- Next state is "st2 - WAIT BUSY = '0'"
+
+ -- st2 - WAIT BUSY = '0'
+ when st2=>
+ if busy_i = '0' then
+ next_state <= st3; -- Next state is "st3 - RESET STATE"
+ end if;
+
+ -- st3 - RESET STATE
+ when st3=>
+ s_Rst_FSM <= '1';
+ next_state <= st0; -- Next state is "st0 - IDLE"
+
+ end case;
+
+ end process fsm;
+
+ calibrate_o <= s_cal_FSM;
+ reset_o <= s_Rst_FSM;
+
+end rtl;
diff --git a/firmware/minitlu/hdl/common/IPBusInterface_rtl.vhd b/firmware/minitlu/hdl/common/IPBusInterface_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3916f8a9aecbfe433b753e3e47cc82104a8a1386
--- /dev/null
+++ b/firmware/minitlu/hdl/common/IPBusInterface_rtl.vhd
@@ -0,0 +1,202 @@
+--=============================================================================
+--! @file IPBusInterface_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 16:06:57 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.emac_hostbus_decl.all;
+
+ENTITY IPBusInterface IS
+ GENERIC(
+ NUM_EXT_SLAVES : positive := 5
+ );
+ PORT(
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
+ sysclk_n_i : IN std_logic;
+ sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
+ clocks_locked_o : OUT std_logic;
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ ipb_clk_o : OUT std_logic; -- ! IPBus clock to slaves
+ ipb_rst_o : OUT std_logic; -- ! IPBus reset to slaves
+ ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
+ onehz_o : OUT std_logic;
+ phy_rstb_o : OUT std_logic;
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ clk_logic_xtal_o : OUT std_logic
+ );
+
+-- Declarations
+
+END ENTITY IPBusInterface ;
+
+--
+ARCHITECTURE rtl OF IPBusInterface IS
+
+ --! Number of slaves inside the IPBusInterface block.
+ constant c_NUM_INTERNAL_SLAVES : positive := 1;
+
+ signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
+ signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
+ signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
+ signal ipb_master_out : ipb_wbus;
+ signal ipb_master_in : ipb_rbus;
+ signal mac_addr: std_logic_vector(47 downto 0);
+ signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
+ signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
+
+ signal ip_addr: std_logic_vector(31 downto 0);
+ signal s_ipb_clk : std_logic;
+ signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+ signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
+ signal s_sysclk : std_logic;
+ signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
+
+BEGIN
+
+
+-- DCM clock generation for internal bus, ethernet
+ clocks: entity work.clocks_s6_extphy port map(
+ sysclk_p => sysclk_p_i,
+ sysclk_n => sysclk_n_i,
+ clk_logic_xtal_o => clk_logic_xtal_o,
+ clko_125 => clk125,
+ clko_ipb => s_ipb_clk,
+ locked => clocks_locked_o,
+ rsto_125 => rst_125,
+ rsto_ipb => rst_ipb,
+ onehz => onehz_o
+ );
+
+ -- Connect IPBus clock and reset to output ports.
+ ipb_clk_o <= s_ipb_clk;
+ ipb_rst_o <= rst_ipb;
+
+ -- leds <= ('0', '0', locked, onehz);
+
+-- Ethernet MAC core and PHY interface
+-- In this version, consists of hard MAC core and GMII interface to external PHY
+-- Can be replaced by any other MAC / PHY combination
+
+ eth: entity work.eth_s6_gmii port map(
+ clk125 => clk125,
+ rst => rst_125,
+ gmii_gtx_clk => gmii_gtx_clk_o,
+ gmii_tx_en => gmii_tx_en_o,
+ gmii_tx_er => gmii_tx_er_o,
+ gmii_txd => gmii_txd_o,
+ gmii_rx_clk => gmii_rx_clk_i,
+ gmii_rx_dv => gmii_rx_dv_i,
+ gmii_rx_er => gmii_rx_er_i,
+ gmii_rxd => gmii_rxd_i,
+ tx_data => mac_tx_data,
+ tx_valid => mac_tx_valid,
+ tx_last => mac_tx_last,
+ tx_error => mac_tx_error,
+ tx_ready => mac_tx_ready,
+ rx_data => mac_rx_data,
+ rx_valid => mac_rx_valid,
+ rx_last => mac_rx_last,
+ rx_error => mac_rx_error
+ );
+
+ phy_rstb_o <= '1';
+
+-- ipbus control logic
+ ipbus: entity work.ipbus_ctrl
+ generic map (
+ BUFWIDTH => 2)
+ port map(
+ mac_clk => clk125,
+ rst_macclk => rst_125,
+ ipb_clk => s_ipb_clk,
+ rst_ipb => rst_ipb,
+ mac_rx_data => mac_rx_data,
+ mac_rx_valid => mac_rx_valid,
+ mac_rx_last => mac_rx_last,
+ mac_rx_error => mac_rx_error,
+ mac_tx_data => mac_tx_data,
+ mac_tx_valid => mac_tx_valid,
+ mac_tx_last => mac_tx_last,
+ mac_tx_error => mac_tx_error,
+ mac_tx_ready => mac_tx_ready,
+ ipb_out => ipb_master_out,
+ ipb_in => ipb_master_in,
+ mac_addr => mac_addr,
+ ip_addr => ip_addr,
+ pkt_rx => pkt_rx,
+ pkt_tx => pkt_tx,
+ pkt_rx_led => pkt_rx_led,
+ pkt_tx_led => pkt_tx_led
+ );
+
+
+ mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
+ ip_addr <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
+
+ fabric: entity work.ipbus_fabric
+ generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
+ port map(
+ ipb_in => ipb_master_out,
+ ipb_out => ipb_master_in,
+ ipb_to_slaves => s_ipbw_internal,
+ ipb_from_slaves => s_ipbr_internal
+ );
+
+ ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
+
+ s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
+
+ -- Slave: firmware ID
+ firmware_id: entity work.ipbus_ver
+ port map(
+ ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
+ ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
+ );
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/Reg_2clks.vhd b/firmware/minitlu/hdl/common/Reg_2clks.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..df7168fc6283b56b28cef8af2b300d774b576bf7
--- /dev/null
+++ b/firmware/minitlu/hdl/common/Reg_2clks.vhd
@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+--
+-- Create Date: 31/07/2012
+-- Module Name: Reg_2clks - Behavioral
+-- Revision 0.01 - File Created
+-- Additional Comments:
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 1b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity Reg_2clks is
+ port(
+ clk_i : in std_logic; --! Synchronous clock
+ async_i : in std_logic; --! Asynchronous input data
+ sync_o : out std_logic --! Synchronous output data
+ );
+end Reg_2clks;
+
+--! @brief
+--! @details Synchronize 1 bit of data
+
+architecture Behavioral of Reg_2clks is
+signal sreg : std_logic_vector(1 downto 0);
+
+attribute TIG : string;
+attribute IOB : string;
+attribute ASYNC_REG : string;
+attribute SHIFT_EXTRACT : string;
+attribute HBLKNM : string;
+
+attribute TIG of async_i : signal is "TRUE";
+attribute IOB of async_i : signal is "FALSE";
+attribute ASYNC_REG of sreg : signal is "TRUE";
+attribute SHIFT_EXTRACT of sreg : signal is "NO";
+attribute HBLKNM of sreg : signal is "sync_reg";
+
+begin
+
+process (clk_i)
+begin
+ if rising_edge(clk_i) then
+ sync_o <= sreg(1);
+ sreg <= sreg(0) & async_i;
+ end if;
+end process;
+
+end Behavioral;
+
diff --git a/firmware/minitlu/hdl/common/TPx3Logic_rtl.vhd b/firmware/minitlu/hdl/common/TPx3Logic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1e35cfacd18f53ec298aefd1d5f836b05254aa2c
--- /dev/null
+++ b/firmware/minitlu/hdl/common/TPx3Logic_rtl.vhd
@@ -0,0 +1,177 @@
+--=============================================================================
+--! @file TPx3Logic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.TPx3Logic.rtl
+--
+--! @brief Produces shutters \n
+--! IPBus address map:\n
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 16:06:19 11/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY TPx3Logic IS
+ GENERIC(
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ clk_i : IN std_logic; -- ! Rising edge active
+ Start_T0sync_i : IN std_logic;
+ T0syncLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+ logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
+ Busy_i : IN std_logic;
+ Veto_i : IN std_logic;
+ Shutter_o : OUT std_logic;
+ T0sync_o : OUT std_logic
+ );
+
+
+-- Declarations
+
+END ENTITY TPx3Logic ;
+
+--
+ARCHITECTURE rtl OF TPx3Logic IS
+
+ type state_values is (st0, st1);
+ signal pres_state, next_state: state_values;
+
+ signal s_Enable : std_logic := '0';
+ signal s_Shutter, s_Shutter_d1f, s_Shutter_d1, s_T0sync, s_T0sync_d1f : std_logic := '0';
+ signal s_Start_T0sync, s_Start_T0sync_d1, s_Start_T0sync_d2, s_Start_T0sync_d3 : std_logic;
+ signal Rst_T0sync, T0syncT : std_logic; --Load signal and flag for the T0sync
+ signal s_RunNumber : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for runs
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- Counters
+ -----------------------------------------------------------------------------
+ --T0sync counter
+ c_T0sync: entity work.CounterDown
+ generic map(
+ MAX_WIDTH => g_IPBUS_WIDTH
+ )
+ port map(
+ Clk => clk_i,
+ Reset => '0',
+ Load => Rst_T0sync,
+ InitVal => std_logic_vector(unsigned(T0syncLen_i)-1),
+ Count => open,
+ Q => T0syncT
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- FSM register
+ -----------------------------------------------------------------------------
+ statereg: process(clk_i)
+ begin
+ if rising_edge(clk_i) then
+ pres_state <= next_state; --Move to the next state
+ end if;
+ end process statereg;
+
+
+ -----------------------------------------------------------------------------
+ -- FSM combinational block
+ -----------------------------------------------------------------------------
+ fsm: process(pres_state, s_Start_T0sync, T0syncT)
+ begin
+ next_state<=pres_state;
+ s_T0sync <='0';
+ Rst_T0sync <= '1';
+
+ case pres_state is
+ when st0=>
+ if s_Start_T0sync = '1' then
+ next_state <= st1; --Next state is "Whait for end of T0sync signal"
+ end if;
+ when st1 =>
+ Rst_T0sync <='0';
+ s_T0sync <='1';
+ if T0syncT = '1' then
+ next_state<=st0; --Next state is "Whait for end of T0-sync counter"
+ end if;
+ when others=>
+ next_state<=st0; --Next state is "Whait for T0sync start"
+ end case;
+ end process fsm;
+
+
+ -----------------------------------------------------------------------------
+ -- Busy signals
+ -----------------------------------------------------------------------------
+ s_Enable <= not Veto_i;
+ s_Shutter <= not Busy_i and not Veto_i;
+ --Shutter_o <= s_Shutter;
+ --T0sync_o <= s_T0sync;
+
+
+ -----------------------------------------------------------------------------
+ -- Count runs and synchronization
+ -----------------------------------------------------------------------------
+ p_run_counter: process (clk_i )
+ begin -- process p_run_counter
+ if rising_edge(clk_i) then
+ s_Start_T0sync_d1 <= Start_T0sync_i;
+ s_Start_T0sync_d2 <= s_Start_T0sync_d1;
+ s_Start_T0sync_d3 <= s_Start_T0sync_d2;
+ s_Start_T0sync <= s_Start_T0sync_d2 and ( not s_Start_T0sync_d3);
+
+ s_Shutter_d1 <= s_Shutter;
+
+ if logic_reset_i = '1' then
+ s_RunNumber <= (others => '0');
+ elsif s_Shutter='1' and s_Shutter_d1='0' then
+ s_RunNumber <= s_RunNumber + 1;
+ end if;
+ end if;
+ -- Signals synchronous with falling edge clock
+ if falling_edge(clk_i) then
+ s_Shutter_d1f <= s_Shutter;
+ Shutter_o <= s_Shutter_d1f;
+
+ s_T0sync_d1f <= s_T0sync;
+ T0sync_o <= s_T0sync_d1f;
+ end if;
+ end process p_run_counter;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/arrivalTimeLUT_rtl.vhd b/firmware/minitlu/hdl/common/arrivalTimeLUT_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8b5f6882b84f7dc7a55cc8ac0ab85ee7a24201df
--- /dev/null
+++ b/firmware/minitlu/hdl/common/arrivalTimeLUT_rtl.vhd
@@ -0,0 +1,198 @@
+--=============================================================================
+--! @file arrivalTimeLUT_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.ArivalTimeLUT.rtl
+--
+--! @brief Uses a look-up-table to convert the eight bits from the two 1:4 deserializers\n
+--! into a 5-bit time ( 3 bits from the position in 8-bit deserialized data \n
+--! plus two bits from position w.r.t. the strobe_4x_logic_i signal ( one pulse
+--! every 4 cycles of clk_4x_logic_i
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:46:34 11/21/12
+--
+--! @version v0.1
+--
+--! @details
+--! Rising and falling edge times encoded as a LUT. Contents:
+--! MRFrrrfff
+--! M = multiple edges present ( more then one rising or falling edge)
+--! R = at least one rising edge present
+--! F = at least one falling edge present.
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY arrivalTimeLUT IS
+ GENERIC(
+ g_NUM_FINE_BITS : positive := 3;
+ g_NUM_COARSE_BITS : positive := 2
+ );
+ PORT(
+ clk_4x_logic_i : IN std_logic; --! Rising edge active
+ strobe_4x_logic_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
+ deserialized_data_i : IN std_logic_vector (8 DOWNTO 0); -- Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data
+ first_rising_edge_time_o : OUT std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0); -- Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+ last_falling_edge_time_o : OUT std_logic_vector (g_NUM_FINE_BITS+g_NUM_COARSE_BITS-1 DOWNTO 0); -- Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i
+ rising_edge_o : OUT std_logic; -- goes high if there is a rising edge in the data. Clocked by clk_4x_logic_i
+ falling_edge_o : OUT std_logic; -- goes high if there is a falling edge in the data.Clocked by clk_4x_logic_i
+ multiple_edges_o : OUT std_logic -- there is more than one rising or falling edge transition.
+ );
+
+-- Declarations
+
+END ENTITY arrivalTimeLUT ;
+
+--
+ARCHITECTURE rtl OF arrivalTimeLUT IS
+
+ constant c_FALLING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS; --! Bit position of bit set when falling edge detected
+ constant c_RISING_EDGE_BIT : positive := 2*g_NUM_FINE_BITS+1; --! Bit position of bit set when rising edge detected
+ constant c_MULTI_EDGE_BIT : positive := 2*g_NUM_FINE_BITS+2; --! Bit position of bit set when rising edge detected
+
+
+ signal s_coarse_bits : std_logic_vector(g_NUM_COARSE_BITS-1 downto 0) := "00"; --! phase w.r.t. strobe
+
+ signal s_LUT_entry : std_logic_vector(g_NUM_FINE_BITS*2 +3-1 downto 0); -- stores intermediate LUT value.
+
+ type t_LUT is array (natural range <>) of std_logic_vector(g_NUM_FINE_BITS*2 + 3 -1 downto 0);
+ --! Lookup table for arrival time and rising/falling edge detection (3bits
+ --! for position in 8-bit deserialized data plus two bits for rising/falling
+ constant c_LUT : t_LUT(0 to 511) := (
+ "000000000", "001000000", "011000001", "001000001", "011001010", "011001010", "011000010", "001000010",
+ "011010011", "011010011", "111000011", "011010011", "011001011", "011001011", "011000011", "001000011",
+ "011011100", "011011100", "111000100", "011011100", "111001100", "111001100", "111000100", "011011100",
+ "011010100", "011010100", "111000100", "011010100", "011001100", "011001100", "011000100", "001000100",
+ "011100101", "011100101", "111000101", "011100101", "111001101", "111001101", "111000101", "011100101",
+ "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011100101",
+ "011011101", "011011101", "111000101", "011011101", "111001101", "111001101", "111000101", "011011101",
+ "011010101", "011010101", "111000101", "011010101", "011001101", "011001101", "011000101", "001000101",
+ "011101110", "011101110", "111000110", "011101110", "111001110", "111001110", "111000110", "011101110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110",
+ "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011101110",
+ "011100110", "011100110", "111000110", "011100110", "111001110", "111001110", "111000110", "011100110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011100110",
+ "011011110", "011011110", "111000110", "011011110", "111001110", "111001110", "111000110", "011011110",
+ "011010110", "011010110", "111000110", "011010110", "011001110", "011001110", "011000110", "001000110",
+ "011110111", "011110111", "111000111", "011110111", "111001111", "111001111", "111000111", "011110111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
+ "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
+ "111100111", "111100111", "111000111", "111100111", "111001111", "111001111", "111000111", "111100111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "111100111",
+ "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011110111",
+ "011101111", "011101111", "111000111", "011101111", "111001111", "111001111", "111000111", "011101111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111",
+ "111011111", "111011111", "111000111", "111011111", "111001111", "111001111", "111000111", "111011111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011101111",
+ "011100111", "011100111", "111000111", "011100111", "111001111", "111001111", "111000111", "011100111",
+ "111010111", "111010111", "111000111", "111010111", "111001111", "111001111", "111000111", "011100111",
+ "011011111", "011011111", "111000111", "011011111", "111001111", "111001111", "111000111", "011011111",
+ "011010111", "011010111", "111000111", "011010111", "011001111", "011001111", "011000111", "001000111",
+ "010111000", "011111000", "111000001", "011111001", "111001010", "111001010", "111000010", "011111010",
+ "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011111011",
+ "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
+ "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011111100",
+ "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101",
+ "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101",
+ "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101",
+ "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011111101",
+ "111101110", "111101110", "111000110", "111101110", "111001110", "111001110", "111000110", "111101110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110",
+ "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111101110",
+ "111100110", "111100110", "111000110", "111100110", "111001110", "111001110", "111000110", "111100110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "111100110",
+ "111011110", "111011110", "111000110", "111011110", "111001110", "111001110", "111000110", "111011110",
+ "111010110", "111010110", "111000110", "111010110", "111001110", "111001110", "111000110", "011111110",
+ "010110000", "011110000", "111000001", "011110001", "111001010", "111001010", "111000010", "011110010",
+ "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011110011",
+ "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
+ "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011110100",
+ "111100101", "111100101", "111000101", "111100101", "111001101", "111001101", "111000101", "111100101",
+ "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "111100101",
+ "111011101", "111011101", "111000101", "111011101", "111001101", "111001101", "111000101", "111011101",
+ "111010101", "111010101", "111000101", "111010101", "111001101", "111001101", "111000101", "011110101",
+ "010101000", "011101000", "111000001", "011101001", "111001010", "111001010", "111000010", "011101010",
+ "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011101011",
+ "111011100", "111011100", "111000100", "111011100", "111001100", "111001100", "111000100", "111011100",
+ "111010100", "111010100", "111000100", "111010100", "111001100", "111001100", "111000100", "011101100",
+ "010100000", "011100000", "111000001", "011100001", "111001010", "111001010", "111000010", "011100010",
+ "111010011", "111010011", "111000011", "111010011", "111001011", "111001011", "111000011", "011100011",
+ "010011000", "011011000", "111000001", "011011001", "111001010", "111001010", "111000010", "011011010",
+ "010010000", "011010000", "111000001", "011010001", "010001000", "011001000", "010000000", "000000000"
+ );
+
+BEGIN
+
+ -- purpose: uses the deserialized data as a index into
+ -- a lookup table holding the position of the first rising edge (if any)
+ -- and if there is a rising or falling edge
+ -- type : combinational
+ -- inputs : clk_4x_logic_i
+ -- outputs: arrival_time_o , rising_edge_o , falling_edge_o
+ examine_lut: process (clk_4x_logic_i) -- , deserialized_data_i)
+-- variable v_LUT_entry : std_logic_vector(g_NUM_FINE_BITS+2-1 downto 0); --! Entry in LUT pointed to by deserialized data
+ begin -- process examine_lut
+
+-- v_LUT_entry := c_LUT(to_integer(unsigned(deserialized_data_i)));
+
+ if rising_edge(clk_4x_logic_i) then
+ s_LUT_entry <= c_LUT(to_integer(unsigned(deserialized_data_i)));
+ first_rising_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS*2-1 downto g_NUM_FINE_BITS);
+ last_falling_edge_time_o <= s_coarse_bits & s_LUT_ENTRY(g_NUM_FINE_BITS-1 downto 0);
+ rising_edge_o <= s_LUT_ENTRY(c_RISING_EDGE_BIT);
+ falling_edge_o <= s_LUT_ENTRY(c_FALLING_EDGE_BIT);
+ multiple_edges_o <= s_LUT_ENTRY(c_MULTI_EDGE_BIT);
+ end if;
+
+ end process examine_lut;
+
+ --! Coarse time stamp. Phase w.r.t. strobe
+-- c_coarse_ts : entity work.CounterUp
+-- PORT MAP (
+-- clk => clk_4x_logic_i,
+-- ce => '1',
+-- sinit => strobe_4x_logic_i, --'0',
+-- q(31 downto 2) => open,
+-- q(1 downto 0) => s_coarse_bits
+-- );
+--
+ c_coarse_ts : entity work.CounterWithReset
+ GENERIC MAP (
+ g_COUNTER_WIDTH => 2 )
+ PORT MAP (
+ clock_i => clk_4x_logic_i,
+ enable_i => '1',
+ reset_i => strobe_4x_logic_i, -- Synchronous reset, so the counter will present result_o="11" when reset_i='1'
+ result_o => s_coarse_bits
+ );
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/clocks_s6_extphy.vhd b/firmware/minitlu/hdl/common/clocks_s6_extphy.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..c64f1777208442dc76fa5f83e4f62d2b3474d8e2
--- /dev/null
+++ b/firmware/minitlu/hdl/common/clocks_s6_extphy.vhd
@@ -0,0 +1,157 @@
+-- clocks_s6_extphy
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_s6_extphy is port(
+ sysclk_p, sysclk_n: in std_logic;
+ -- dummy_sysclk : in std_logic;
+ clk_logic_xtal_o : out std_logic;
+ clko_125: out std_logic;
+ clko_ipb: out std_logic;
+ locked: out std_logic;
+ rsto_125: out std_logic;
+ rsto_ipb: out std_logic;
+ onehz: out std_logic
+ );
+
+end clocks_s6_extphy;
+
+architecture rtl of clocks_s6_extphy is
+
+ signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
+ -- signal sysclk_in : std_logic;
+ signal d25, d25_d, dcm_locked: std_logic;
+ signal rst: std_logic := '1';
+ signal s_xtal_dcm_locked: std_logic;
+ signal s_clk_logic_xtal : std_logic;
+ -- signal clk_400: std_logic;
+
+-- component clock_divider_s6 port(
+-- clk: in std_logic;
+-- d25: out std_logic;
+-- d28: out std_logic
+-- );
+-- end component;
+
+begin
+
+ ibufgds0: IBUFGDS port map(
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sysclk
+ );
+
+-- -- Add global clock buffer in sysclk path.
+-- bufg_sysclk : BUFG port map (
+-- i => sysclk_in,
+-- o => sysclk);
+
+ bufg_125: BUFG port map(
+ i => clk_125_i,
+ o => clk_125_b
+ );
+
+ clko_125 <= clk_125_b;
+
+ bufg_ipb: BUFG port map(
+ i => clk_ipb_i,
+ o => clk_ipb_b
+ );
+
+ bufg_clk_logic_xtal: BUFG port map(
+ i => s_clk_logic_xtal,
+ o => clk_logic_xtal_o
+ );
+
+ clko_ipb <= clk_ipb_b;
+
+ dcm0: DCM_CLKGEN
+ generic map(
+ CLKIN_PERIOD => 5.0,
+ CLKFX_MULTIPLY => 5,
+ CLKFX_DIVIDE => 8,
+ CLKFXDV_DIVIDE => 4
+ )
+ port map(
+ clkin => sysclk,
+ clkfx => clk_125_i,
+ clkfxdv => clk_ipb_i,
+ locked => dcm_locked,
+ rst => '0'
+ );
+
+ clkdiv: entity work.clock_divider_s6 port map(
+-- clkdiv: entity work.clock_div port map(
+ clk => sysclk,
+-- D17 => open,
+ d25 => d25,
+ d28 => onehz
+ );
+
+ process(sysclk)
+ begin
+ if rising_edge(sysclk) then
+ d25_d <= d25;
+ if d25='1' and d25_d='0' then
+ rst <= not dcm_locked;
+ end if;
+ end if;
+ end process;
+
+ locked <= dcm_locked;
+
+ process(clk_ipb_b)
+ begin
+ if rising_edge(clk_ipb_b) then
+ rsto_ipb <= rst;
+ end if;
+ end process;
+
+ process(clk_125_b)
+ begin
+ if rising_edge(clk_125_b) then
+ rsto_125 <= rst;
+ end if;
+ end process;
+
+ sys40_gen : BUFIO2
+ generic map (
+ DIVIDE => 5, -- DIVCLK divider (1-8)
+ DIVIDE_BYPASS => FALSE) -- Bypass the divider circuitry (TRUE/FALSE)
+ port map (
+ I => SysClk, -- 1-bit input: Clock input (connect to IBUFG)
+ DIVCLK => s_clk_logic_xtal, -- 1-bit output: Divided clock output
+ IOCLK => open, -- 1-bit output: I/O output clock
+ SERDESSTROBE => open); -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+
+
+
+ -- Generate 40MHz clock from 200MHz crystal
+-- dcmXTAL: DCM_CLKGEN
+-- generic map(
+-- CLKIN_PERIOD => 5.0,
+-- CLKFX_MULTIPLY => 2,
+-- CLKFX_DIVIDE => 10,
+-- CLKFXDV_DIVIDE => 2
+-- )
+-- port map(
+-- clkin => sysclk,
+-- clkfx => s_clk_logic_xtal,
+-- clkfxdv => open,
+-- locked => s_xtal_dcm_locked,
+-- rst => '0'
+-- );
+--
+
+end rtl;
diff --git a/firmware/minitlu/hdl/common/counterDown.vhd b/firmware/minitlu/hdl/common/counterDown.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de1509001a37cdc74e132a60d4201581a96d83aa
--- /dev/null
+++ b/firmware/minitlu/hdl/common/counterDown.vhd
@@ -0,0 +1,50 @@
+--Counter down
+--Outputs: Q<='1' while counting
+-- Q<='0' if not counting
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+ENTITY CounterDown IS
+ GENERIC(
+ MAX_WIDTH: positive := 32
+ );
+ PORT(
+ Clk : in std_logic;
+ Reset : in std_logic;
+ Load : in std_logic;
+ InitVal : in std_logic_vector(MAX_WIDTH-1 downto 0);
+ Count : out Std_logic_vector(MAX_WIDTH-1 downto 0);
+ Q : out std_logic
+ );
+END ENTITY CounterDown;
+
+architecture rtl of CounterDown is
+ signal cnt : std_logic_vector(MAX_WIDTH-1 downto 0);
+ signal Qtmp : std_logic;
+
+begin
+ Counter: process (Clk, Reset)
+ begin
+ if (Reset='1') then
+ cnt <= (others =>'0');
+ elsif rising_edge(Clk) then
+ if (Load='1') then
+ cnt <= InitVal;
+ else
+ if Qtmp='0' then
+ cnt <= std_logic_vector(unsigned(cnt) - 1);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ Qtmp <= '1' when cnt=(cnt'range=>'0') else
+ '0';
+
+ Count <= cnt;
+ Q <= Qtmp;
+end rtl;
diff --git a/firmware/minitlu/hdl/common/counterWithReset_rtl.vhd b/firmware/minitlu/hdl/common/counterWithReset_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ebe400300f261f7373ca9da8828b18ef4ed53347
--- /dev/null
+++ b/firmware/minitlu/hdl/common/counterWithReset_rtl.vhd
@@ -0,0 +1,95 @@
+--=============================================================================
+--! @file counterWithReset_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- unit name: counterWithReset (counterWithReset / rtl)
+--
+--! @brief Simple counter with synchronous reset
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date Feb\2012
+--
+--! @version v0.1
+--
+--! @details
+--!
+--! <b>Dependencies:</b>\n
+--! None
+--!
+--! <b>References:</b>\n
+--! referenced by ipBusMarocTriggerGenerator \n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 5/Mar/12 DGC Changed to use numeric_std\n
+--! 26/Feb/14 DGC Added registers to output to aid timing closure.
+--!
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+---------------------------------------------------------------------------------
+
+--============================================================================
+--! Entity declaration for counterWithReset
+--============================================================================
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+ENTITY counterWithReset IS
+ GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
+ g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
+ );
+ PORT
+ (
+ clock_i: IN STD_LOGIC; --! rising edge active clock
+ reset_i: IN STD_LOGIC; --! Active high. syncronous with rising clk
+ enable_i: IN STD_LOGIC; --! counts when enable=1
+ result_o: OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
+
+ );
+END counterWithReset;
+
+ARCHITECTURE rtl OF counterWithReset IS
+ type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
+ signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0')); -- --! Output registers.
+
+BEGIN
+
+ --! Process to count up from zero when enable_i is high.
+ p_counter: PROCESS (clock_i)
+ BEGIN
+ IF rising_edge(clock_i) THEN
+ IF (reset_i = '1') THEN
+ s_output_registers(0) <= (others => '0');
+ ELSIF (enable_i='1') THEN
+ s_output_registers(0) <= s_output_registers(0) + 1;
+ END IF;
+ END IF;
+ END PROCESS p_counter;
+
+ --! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
+ generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
+
+ --! An individual register
+ p_outputRegister: process (clock_i)
+ begin -- process p_outputRegister
+ if rising_edge(clock_i) then
+ s_output_registers( v_register) <=
+ s_output_registers( v_register-1);
+ end if;
+ end process p_outputRegister;
+
+ end generate generate_registers; -- v_register
+
+ --! Copy the (registered) result to the output
+ result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
+
+END rtl;
diff --git a/firmware/minitlu/hdl/common/dualSERDES_1to4_rtl.vhd b/firmware/minitlu/hdl/common/dualSERDES_1to4_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ff11184545eb84821f33ca2145817872ac0a0355
--- /dev/null
+++ b/firmware/minitlu/hdl/common/dualSERDES_1to4_rtl.vhd
@@ -0,0 +1,218 @@
+--=============================================================================
+--! @file dualSERDES_1to4_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.dualSERDES_1to4.rtl
+--
+--! @brief Two 1:4 Deserializers. One has input delayed w.r.t. other\n
+--! based on TDC by Alvaro Dosil\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 12:06:53 11/16/12
+--
+--! @version v0.1
+--
+--! @details
+--! data_o(7) is the most recently arrived data , data_o(0) is the oldest data.
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Separated FSM for calibration control into a separate entity. DGC, 22/Feb/14
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence\n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+library unisim ;
+use unisim.vcomponents.all;
+
+
+ENTITY dualSERDES_1to4 IS
+ PORT(
+ reset_i : IN std_logic; --! Resets IODELAY
+ --calibrate_i : IN std_logic; --! Starts IODELAY calibration.
+ data_i : IN std_logic; --! from input buffer.
+ fastClk_i : IN std_logic; --! 4x fabric clock. e.g. 640MHz
+ fabricClk_i : IN std_logic; --! clock for output to FPGA. e.g. 160MHz
+ strobe_i : IN std_logic; --! Strobes once every 4 cycles of fastClk
+ data_o : OUT std_logic_vector (7 DOWNTO 0); --! Deserialized data. Interleaved between prompt and delayed serdes.
+ --! data_o(0) is the oldest data
+ status_o : OUT std_logic_vector(1 downto 0) --! outputs from IODELAY "busy" 0=prompt,1=delayed
+ );
+
+-- Declarations
+
+END ENTITY dualSERDES_1to4 ;
+
+--
+ARCHITECTURE rtl OF dualSERDES_1to4 IS
+
+ constant c_S : positive := 4; -- ! SERDES division ratio
+
+ signal s_Data_i_d_p : std_logic;
+ signal s_Data_i_d_d : std_logic;
+ signal s_busy_idelay_p : std_logic; -- Busy from iodelay.
+ signal s_busy_idelay_d : std_logic; -- Busy from iodelay.
+ signal s_busy : std_logic; -- Busy from the two iodelays.
+ signal s_data_o : std_logic_vector(7 downto 0); --! Deserialized data
+ signal s_cal : std_logic := '0'; --! Calibration signal
+ signal s_rst_cal : std_logic := '0'; --! reset after calibration process
+
+
+
+
+BEGIN
+
+ -- IODELAYs calibration FSM
+ IODELAYCal: entity work.IODELAYCal_FSM
+ port map (
+ clk_i => fabricClk_i,
+ startcal_i => reset_i,
+ busy_i => s_busy,
+ calibrate_o => s_cal,
+ reset_o => s_rst_cal);
+
+
+ IODELAY2_Prompt : IODELAY2
+ generic map (
+ COUNTER_WRAPAROUND => "STAY_AT_LIMIT" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
+ DATA_RATE => "SDR", -- "SDR" or "DDR"
+ DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
+ SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
+ IDELAY_TYPE => "VARIABLE_FROM_ZERO",
+ IDELAY_VALUE => 0 -- Amount of taps for fixed input delay (0-255)
+ --SIM_TAPDELAY_VALUE=> 10 -- Per tap delay used for simulation in ps
+ )
+ port map (
+ BUSY => s_busy_idelay_p, -- 1-bit output: Busy output after CAL
+ DATAOUT => s_Data_i_d_p, -- 1-bit output: Delayed data output to ISERDES/input register
+ DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
+ DOUT => open, -- 1-bit output: Delayed data output
+ TOUT => open, -- 1-bit output: Delayed 3-state output
+ CAL => s_cal, -- 1-bit input: Initiate calibration input
+ CE => '0', -- 1-bit input: Enable INC input
+ CLK => fabricClk_i, -- 1-bit input: Clock input
+ IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+ INC => '0', -- 1-bit input: Increment / decrement input
+ IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
+ IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
+ ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
+ RST => s_rst_cal, -- 1-bit input: reset_i to 1/2 of total delay period
+ T => '1' -- 1-bit input: 3-state input signal
+ );
+ status_o(1) <= s_busy_idelay_p;
+
+ IODELAY2_Delayed : IODELAY2
+ generic map (
+ COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
+ DATA_RATE => "SDR", -- "SDR" or "DDR"
+ DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
+ SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
+ IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
+ IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
+ IDELAY2_VALUE => 0 -- Delay value when IDELAY_MODE="PCI" (0-255)
+ --SIM_TAPDELAY_VALUE => 10 -- Per tap delay used for simulation in ps
+ )
+ port map (
+ BUSY => s_busy_idelay_d, -- 1-bit output: Busy output after CAL
+ DATAOUT => s_Data_i_d_d, -- 1-bit output: Delayed data output to ISERDES/input register
+ DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
+ DOUT => open, -- 1-bit output: Delayed data output
+ TOUT => open, -- 1-bit output: Delayed 3-state output
+ CAL => s_cal, -- 1-bit input: Initiate calibration input
+ CE => '0', -- 1-bit input: Enable INC input
+ CLK => fabricClk_i, -- 1-bit input: Clock input
+ IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+ INC => '0', -- 1-bit input: Increment / decrement input
+ IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
+ IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
+ ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
+ RST => s_rst_cal, -- 1-bit input: reset_i to zero
+ T => '1' -- 1-bit input: 3-state input signal
+ );
+ status_o(0) <= s_busy_idelay_d;
+
+ s_busy <= s_busy_idelay_p or s_busy_idelay_d;
+
+ ISERDES2_Prompt : ISERDES2
+ generic map (
+ BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
+ DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
+ DATA_WIDTH => 4, -- Parallel data width selection (2-8)
+ INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+ )
+ port map (
+ -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+ Q1 => s_Data_o(1), -- Oldest data
+ Q2 => s_Data_o(3),
+ Q3 => s_Data_o(5),
+ Q4 => s_Data_o(7), -- most recent data
+ --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
+ VALID => open, -- 1-bit output Output status of the phase detector
+ BITSLIP => '0', -- 1-bit input Bitslip enable input
+ CE0 => '1', -- 1-bit input Clock enable input
+ CLK0 => fastClk_i, -- 1-bit input I/O clock network input
+ CLK1 => '0', -- 1-bit input Secondary I/O clock network input
+ CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
+ D => s_Data_i_d_p, -- 1-bit input Input data
+ IOCE => strobe_i, -- 1-bit input Data strobe_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
+ SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
+ );
+
+ ISERDES2_Delayed : ISERDES2
+ generic map (
+ BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
+ DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
+ DATA_WIDTH => 4, -- Parallel data width selection (2-8)
+ INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+ )
+ port map (
+ -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+ Q1 => s_Data_o(0), -- oldest data
+ Q2 => s_Data_o(2),
+ Q3 => s_Data_o(4),
+ Q4 => s_Data_o(6), -- most recent data
+ --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
+ VALID => open, -- 1-bit output Output status of the phase detector
+ BITSLIP => '0', -- 1-bit input Bitslip enable input
+ CE0 => '1', -- 1-bit input Clock enable input
+ CLK0 => fastClk_i, -- 1-bit input I/O clock network input
+ CLK1 => '0', -- 1-bit input Secondary I/O clock network input
+ CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
+ D => s_Data_i_d_d, -- 1-bit input Input data
+ IOCE => strobe_i, -- 1-bit input Data strobe_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
+ SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
+ );
+
+reg_out : process(fabricClk_i)
+begin
+ if rising_edge(fabricClk_i) then
+ Data_o <= s_Data_o;
+ end if;
+end process;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/eventBuffer_rtl.vhd b/firmware/minitlu/hdl/common/eventBuffer_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fbcb40ee51620d092671b7988bbb8d9340d4d1a6
--- /dev/null
+++ b/firmware/minitlu/hdl/common/eventBuffer_rtl.vhd
@@ -0,0 +1,159 @@
+--=============================================================================
+--! @file eventBuffer_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventBuffer.rtl
+--
+--! @brief Stores input words (64bits) for readout over IPBus. \n
+--! Uses a FIFO ( 64bits at input, 32 bits at output )\n
+--! Address map:\n
+--! 0x0000 - FIFO data\n
+--! 0x0001 - FIFO fill level\n
+--! 0x0010 - FIFO status/control:\n
+--! Writing Bit-0 resets pointers.\n
+--! Reading bit-1 returns "prog_full" flag
+--
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:24:50 11/13/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY eventBuffer IS
+ GENERIC(
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_WRITE_COUNTER_WIDTH : positive := 15;
+ g_READ_COUNTER_WIDTH : positive := 16
+ );
+ PORT(
+ clk_4x_logic_i : IN std_logic;
+ data_strobe_i : IN std_logic; -- Indicates data to transfer
+ event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus;
+ ipbus_reset_i : IN std_logic;
+ strobe_4x_logic_i : IN std_logic;
+ --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+ rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
+ buffer_full_o : OUT std_logic; --! Goes high when event buffer almost full
+ ipbus_o : OUT ipb_rbus;
+ logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
+ );
+
+-- Declarations
+
+END ENTITY eventBuffer ;
+
+--
+ARCHITECTURE rtl OF eventBuffer IS
+
+
+ signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
+
+ signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
+
+ signal s_write_strobe : std_logic := '0';
+ signal s_rst_fifo, s_rst_fifo_ipb : std_logic := '0'; -- ! Take high to reset FIFO pointers.
+ signal s_fifo_prog_full : std_logic := '0'; -- ! Controlled by programmable-full flag of FIFO core
+ signal s_fifo_rd_en : std_logic := '0'; -- ! Take high to clock data out of FIFO
+ signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
+ signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
+ signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
+ signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- IPBus IO
+ -----------------------------------------------------------------------------
+
+ --! Generate FIFO read enable
+ s_fifo_rd_en <= '1' when ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '0' and ipbus_i.ipb_addr(1 downto 0) = "00" else '0';
+ s_fifo_valid <= '1';
+
+ --! Generate IPBus ACK
+ ipbus_o.ipb_ack <= (ipbus_i.ipb_strobe and not s_fifo_rd_en) or (s_fifo_valid and s_fifo_rd_en);
+ ipbus_o.ipb_err <= '0';
+
+ --! Multiplex output data.
+ with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
+ s_fifo_dout when "00",
+ s_fifo_fill_level when "01",
+ s_fifo_status_ipb when "10",
+ (others => '1') when others;
+
+ ipbus_write: process (ipbus_clk_i)
+ begin -- process ipbus_write
+ if rising_edge(ipbus_clk_i) then
+ s_rst_fifo_ipb <= '0';
+ if ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_addr(1 downto 0) = "10" and ipbus_i.ipb_write = '1' then
+ s_rst_fifo_ipb <= '1';
+ end if;
+
+ -- Register data onto IPBus clock domain to ease timing closure.
+ s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+ s_fifo_fill_level <= X"0000" & s_rd_data_count;
+ end if;
+ end process ipbus_write;
+
+ rst_fifo_o <= s_rst_fifo_ipb;
+ s_rst_fifo <= s_rst_fifo_ipb or logic_reset_i;
+
+ -----------------------------------------------------------------------------
+ -- FIFO and fill-level calculation
+ -----------------------------------------------------------------------------
+
+ -- Instantiate a buffer to store the data. 64-bit on input, 32-bit on output.
+ event_fifo : entity work.tlu_event_fifo
+ PORT MAP (
+ rst => s_rst_fifo,
+ wr_clk => clk_4x_logic_i,
+ rd_clk => ipbus_clk_i,
+ din => event_data_i,
+ wr_en => data_strobe_i,
+ rd_en => s_fifo_rd_en,
+ dout => s_fifo_dout,
+ full => s_fifo_full,
+ almost_full => s_fifo_almost_full,
+ empty => s_fifo_empty,
+ almost_empty => s_fifo_almost_empty,
+ rd_data_count => s_rd_data_count,
+ prog_full => s_fifo_prog_full
+ );
+
+ buffer_full_o <= s_fifo_prog_full;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/eventFormatter_rtl.vhd b/firmware/minitlu/hdl/common/eventFormatter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d0639e1ecf187c7d6a336be9732c3e6a8833e584
--- /dev/null
+++ b/firmware/minitlu/hdl/common/eventFormatter_rtl.vhd
@@ -0,0 +1,498 @@
+--=============================================================================
+--! @file eventFormatter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.eventFormatter.rtl
+--
+--! @brief Takes the data delivered on each trigger and turns it into a 64-bit
+--! word\n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:10:35 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! 27/Feb/14 DGC Change "If" when setting s_word2 to a case ... generate. Questasim
+--! doesn't like having an if that can take an array out of bounds.
+-------------------------------------------------------------------------------
+--! @todo Add more input data: \n
+--! a) shutter signals. One per DUT. ?? \n
+--! b) input levels ( for recording edge data ). Record rising and falling edges\n
+--! c) veto levels. One per DUT. Record rising and falling edges.\n
+--! \n
+--! Add backpressure output if short FIFOs fill up? But many inputs won't
+--! respond - e.g. scintillator inputs. This data will be lost....
+--! some ports are redundant - e.g. trigger counter, others confusingly
+--! labelled. Sort this out..
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.fmcTLU.all;
+USE work.ipbus.all;
+
+ENTITY eventFormatter IS
+ GENERIC(
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_COUNTER_TRIG_WIDTH : positive := 32;
+ g_COUNTER_WIDTH : positive := 12;
+ g_EVTTYPE_WIDTH : positive := 4; --! Width of the event type word
+ --g_NUM_INPUT_TYPES : positive := 4; --! Number of different input types (trigger, shutter, edge...)
+ g_NUM_EDGE_INPUTS : positive := 4; --! Number of edge inputs
+ g_NUM_TRIG_INPUTS : positive := 5 --! Number of trigger inputs
+ );
+ PORT(
+ clk_4x_logic_i : IN std_logic; --! Rising edge active
+ ipbus_clk_i : IN std_logic;
+ logic_strobe_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
+ logic_reset_i : IN std_logic; --! goes high to reset counters. Synchronous with clk_4x_logic
+ rst_fifo_i : IN std_logic; --! Reset fifos
+ buffer_full_i : in std_logic; --! Buffer full signal from main buffer
+
+ trigger_i : IN std_logic; --! goes high to load trigger data. One cycle of clk_4x_logic
+ trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times ( w.r.t. logic_strobe)
+ trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! high for each input that "fired"
+ trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
+
+ shutter_i : IN std_logic;
+ shutter_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
+
+ spill_i : IN std_logic;
+ spill_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
+
+ edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when rising edge
+ edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when falling edge
+ edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
+ edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
+
+ ipbus_i : IN ipb_wbus;
+ ipbus_o : OUT ipb_rbus;
+ data_strobe_o : OUT std_logic; -- goes high when data ready to load into event buffer
+ event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ event_number_i : in std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
+ );
+
+-- Declarations
+
+END ENTITY eventFormatter ;
+
+--
+ARCHITECTURE rtl OF eventFormatter IS
+
+ -- add to ports
+ -- trigger_i : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
+ -- signal inputs_triggered_i : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
+ -- signal logic_reset_i : std_logic := '0'; -- put into ports...
+
+ constant c_NUM_INPUT_TYPES : positive := 3+g_NUM_EDGE_INPUTS; -- Number of different input types (trigger, shutter, edge(0), edge(1)...)
+
+ type t_fifo_io is array(natural range <>) of std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0);
+ type t_evttype is array(natural range <>) of std_logic_vector(g_EVTTYPE_WIDTH-1 downto 0);
+ type t_var is array(natural range <>) of std_logic_vector(g_COUNTER_WIDTH-1 downto 0);
+ -- Input types:
+ -- 0 - Trigger
+ -- 1 - Shutter
+ -- 2 - Edge signal
+ -- 3 - Spill
+
+ --! delayed strobes
+ signal s_event_strobe , s_event_strobe_d1 ,s_event_strobe_d2 ,s_event_strobe_d3 , s_event_strobe_d3_opt : std_logic := '0';
+ signal shutter_i_d1, shutter_i_d2, edge_i_d1, edge_i_d2, spill_i_d1, spill_i_d2 : std_logic := '0';
+
+ signal s_evttype : t_evttype(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>(others=>'0')); -- Event type
+ -- 0000 trigger internal
+ -- 0001 trigger external
+ -- 0010 shutter falling
+ -- 0011 shutter rising
+ -- 0100 edge falling
+ -- 0101 edge rising
+ -- 0111 spill on
+ -- 0110 spill off
+
+ signal s_var : t_var(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- 12b different in every input
+
+ signal s_FIFO_wr : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO write signal
+ signal s_FIFO_rd : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals
+ signal s_FIFO_rd_d1 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
+ signal s_FIFO_rd_d2 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
+ constant c_FIFO_rd_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (0 =>'1',others=>'0'); --(3+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- FIFO read mask
+ signal s_FIFO_empty : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO empty signals
+ signal s_FIFO_full : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO full signals
+ signal s_FIFO_i : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO input data
+ signal s_FIFO_o : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO output data
+
+
+ signal s_data_o : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0); -- Multiplexed data from FIFOs
+ --signal s_data_o_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (g_NUM_TRIG_INPUTS+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- Output data mask
+
+ --constant c_COARSE_TIMESTAMP_WIDTH : positive := 48; -- ! Number of bits in 40MHz timestamp
+ constant c_COARSE_TIMESTAMP_L_WIDTH : positive := 16; -- ! Number of bits in 40MHz timestamp lower bits
+ constant c_COARSE_TIMESTAMP_H_WIDTH : positive := 32; -- ! Number of bits in 40MHz timestamp higher bits
+ signal s_coarse_timestamp_l, s_coarse_timestamp_l_d1, s_coarse_timestamp_l_d2, s_coarse_timestamp_l_d3 : unsigned(c_COARSE_TIMESTAMP_L_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
+ signal s_coarse_timestamp_h, s_coarse_timestamp_h_d1, s_coarse_timestamp_h_d2, s_coarse_timestamp_h_d3 : unsigned(c_COARSE_TIMESTAMP_H_WIDTH-1 downto 0) := (others => '0'); -- 40MHz timestamp.
+ signal s_timestamp_h_en : std_logic:='0';
+-- signal s_event_number : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- increment after each post-veto trigger.
+
+ signal s_word0 , s_word1, s_word2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+ signal s_word0_d1 , s_word1_d1, s_word2_d1 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+ signal s_word0_d2 , s_word1_d2, s_word2_d2 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+ signal s_word0_d3 , s_word1_d3, s_word2_d3 : std_logic_vector(g_EVENT_DATA_WIDTH-1 downto 0) := (others => '0'); -- clocked to data output on logic_strobe , s_logic_strobe_d1 , etc.
+ signal trigger_inputs_fired_d1 : std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => '0');
+ signal trigger_times_d1 : t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) := (others => (others=>'0'));
+
+ signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
+ signal s_enable_record, s_enable_record_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (2 downto 0 => '1', others=>'0'); -- Enable data record
+ signal s_enable_trigger : std_logic := '1'; -- Enable trigger record
+ signal s_enable_shutter : std_logic := '1'; -- Enable shutter record
+ signal s_enable_spill : std_logic := '1'; -- Enable spill record
+ signal s_enable_edges : std_logic_vector(g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- Enable edges record
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- IPBus write
+ -----------------------------------------------------------------------------
+ ipbus_write: process (ipbus_clk_i)
+ begin -- process ipb_clk_i
+ if rising_edge(ipbus_clk_i) then
+
+ if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+ case ipbus_i.ipb_addr(2 downto 0) is
+ when "000" => s_enable_record_ipb <= ipbus_i.ipb_wdata ; -- Enable data record
+ when others => null;
+ end case;
+
+ end if;
+
+ s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+
+ end if;
+ end process ipbus_write;
+
+ ipbus_o.ipb_ack <= s_ipbus_ack;
+ ipbus_o.ipb_err <= '0';
+
+
+ -----------------------------------------------------------------------------
+ -- IPBUS read
+ -----------------------------------------------------------------------------
+ with ipbus_i.ipb_addr(2 downto 0) select
+ ipbus_o.ipb_rdata <=
+ s_enable_record_ipb when "000",
+ (others => '1') when others;
+
+ -- Change clock domain
+ p_signals_clk_domain: process (clk_4x_logic_i )
+ begin -- process p_internal_triggers
+ if rising_edge(clk_4x_logic_i) then
+ s_enable_record <= s_enable_record_ipb;
+
+ s_enable_trigger <= s_enable_record(0);
+ s_enable_shutter <= s_enable_record(1);
+ s_enable_spill <= s_enable_record(2);
+ s_enable_edges <= s_enable_record(g_NUM_EDGE_INPUTS-1+3 downto 3);
+
+ end if;
+ end process p_signals_clk_domain;
+
+
+ -- purpose: generate delayed strobes and write enable flags to the FIFOs
+ -- type : combinational
+ -- inputs : clk_4x_logic_i , s_FIFO_rd
+ -- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
+ p_ff_rst: process (clk_4x_logic_i)
+ begin -- process p_generate_strobes
+ if rising_edge(clk_4x_logic_i) then
+ if rst_fifo_i = '1' then
+ s_event_strobe_d1 <= '0';
+ s_event_strobe_d2 <= '0';
+ s_event_strobe_d3 <= '0';
+
+ shutter_i_d1 <= '0';
+ shutter_i_d2 <= '0';
+
+ spill_i_d1 <= '0';
+ spill_i_d2 <= '0';
+
+ s_FIFO_rd_d1 <= (others=>'0');
+ s_FIFO_rd_d2 <= (others=>'0');
+
+ else
+ s_event_strobe_d1 <= trigger_i and s_enable_trigger and not s_FIFO_full(0);
+ s_event_strobe_d2 <= s_event_strobe_d1;
+ s_event_strobe_d3 <= s_event_strobe_d2;
+
+ shutter_i_d1 <= shutter_i and s_enable_shutter and not s_FIFO_full(1);
+ shutter_i_d2 <= shutter_i_d1;
+
+ spill_i_d1 <= spill_i and s_enable_spill and not s_FIFO_full(3+g_NUM_EDGE_INPUTS-1);
+ spill_i_d2 <= spill_i_d1;
+
+ s_FIFO_rd_d1 <= s_FIFO_rd;
+ s_FIFO_rd_d2 <= s_FIFO_rd_d1;
+ end if;
+ end if;
+ end process p_ff_rst;
+
+ p_ff: process (clk_4x_logic_i)
+ begin -- process p_generate_strobes
+ if rising_edge(clk_4x_logic_i) then
+ for i in 0 to g_NUM_TRIG_INPUTS-1 loop
+ trigger_inputs_fired_d1(g_NUM_TRIG_INPUTS-1-i) <= trigger_inputs_fired_i(i);
+ end loop;
+ trigger_times_d1 <= trigger_times_i;
+
+ s_word0_d1 <= s_word0;
+ s_word1_d1 <= s_word1;
+ s_word1_d2 <= s_word1_d1;
+ s_word2_d1 <= s_word2;
+ s_word2_d2 <= s_word2_d1;
+ s_word2_d3 <= s_word2_d2;
+
+ s_coarse_timestamp_l_d1 <= s_coarse_timestamp_l;
+ s_coarse_timestamp_l_d2 <= s_coarse_timestamp_l_d1;
+ s_coarse_timestamp_l_d3 <= s_coarse_timestamp_l_d2;
+ s_coarse_timestamp_h_d1 <= s_coarse_timestamp_h;
+ s_coarse_timestamp_h_d2 <= s_coarse_timestamp_h_d1;
+ s_coarse_timestamp_h_d3 <= s_coarse_timestamp_h_d2;
+ end if;
+ end process;
+
+ -- If there are more than 4 trigger inputs we need to fill a second word.
+ -- .. do this by having an optional strobe.
+ -- If 4 or fewer trigger inputs, just leave s_event_strobe_d3_opt at zero..
+ gen_strobe_d3: if (g_NUM_TRIG_INPUTS > 4) generate
+ s_event_strobe_d3_opt <= s_event_strobe_d3;
+ end generate;
+
+-------------------------------------------------------------------------------
+-- Trigger event formater
+-------------------------------------------------------------------------------
+ s_evttype(0) <= "0000" when unsigned(trigger_inputs_fired_d1) = 0 and trigger_i = '1' else
+ "0001";
+ s_var(0) <= trigger_inputs_fired_d1 & std_logic_vector(to_unsigned(0,s_var(0)'length-g_NUM_TRIG_INPUTS));
+
+ --s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_d2);
+ s_word0 <= s_evttype(0) & s_var(0) & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
+
+ s_word1 <= "000" & trigger_times_d1(0) & "000" & trigger_times_d1(1) &
+ "000" & trigger_times_d1(2) & "000" & trigger_times_d1(3) &
+ trigger_cnt_i;
+
+
+ -- Different number of trigger inputs require packing into s_word2 in
+ -- different ways.
+ -- Do this in a generate since g_NUM_TRIG_INPUTS is static and
+ -- Questasim doesn't like refering to indices outside declared range.
+ s_word2 <= (others=>'0'); -- Set all bits to zero
+ -- then override with the following assignments....
+ gen_word2: for v_trigInput in 4 to g_NUM_TRIG_INPUTS-1 generate
+ s_word2( (((11-v_trigInput)*8)+c_NUM_TIME_BITS-1) downto ((11-v_trigInput)*8) ) <= trigger_times_i(v_trigInput);
+ end generate;
+
+
+ --! Could also output data on trigger_i , but let's use the delayed signals. \n
+ --! The counters are one cycle delayed from the signal generation
+ p_fifo_i : process (clk_4x_logic_i)
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ s_FIFO_wr(0) <= s_event_strobe_d1 or s_event_strobe_d2 or s_event_strobe_d3_opt;
+
+ if s_event_strobe_d1 = '1' then
+ s_FIFO_i(0) <= s_word0_d1;
+ elsif s_event_strobe_d2 = '1' then
+ s_FIFO_i(0) <= s_word1_d2;
+ elsif s_event_strobe_d3_opt = '1' then
+ s_FIFO_i(0) <= s_word2_d3;
+ else
+ s_FIFO_i(0) <= (others=>'0');
+ end if;
+ end if;
+ end process;
+
+
+ s_evttype(1) <= "0011" when shutter_i_d1 = '1' and shutter_i_d2 = '0' else
+ "0010" when shutter_i_d1 = '0' and shutter_i_d2 = '1' else
+ (others=>'0');
+ s_var(1) <= shutter_cnt_i;
+
+ edge_formatting : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
+ s_evttype(i+2) <= "0101" when edge_rise_i(i) = '1' else
+ "0100" when edge_fall_i(i) = '1' else
+ (others=>'0');
+ s_var(i+2) <= std_logic_vector(to_unsigned(i,4)) & "000" & edge_rise_time_i(i) when edge_rise_i(i) = '1' else
+ std_logic_vector(to_unsigned(i,4)) & "000" & edge_fall_time_i(i) when edge_fall_i(i) = '1' else
+ (others=>'0');
+ end generate;
+
+
+ s_evttype(3+g_NUM_EDGE_INPUTS-1) <= "0111" when spill_i_d1 = '1' and spill_i_d2 = '0' else
+ "0110" when spill_i_d1 = '0' and spill_i_d2 = '1' else
+ (others=>'0');
+ s_var(3+g_NUM_EDGE_INPUTS-1) <= spill_cnt_i;
+
+
+
+ p_fifo_wr : process (clk_4x_logic_i)
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ s_FIFO_wr(1) <= shutter_i_d1 xor shutter_i_d2;
+ s_FIFO_wr(3+g_NUM_EDGE_INPUTS-1) <= spill_i_d1 xor spill_i_d2;
+ end if;
+ end process;
+
+ gen_fifo_wr_edge : for i in 0 to (g_NUM_EDGE_INPUTS-1) generate
+ p_fifo_wr : process (clk_4x_logic_i)
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ s_FIFO_wr(i+2) <= (edge_rise_i(i) or edge_fall_i(i)) and s_enable_edges(i) and not s_FIFO_full(i+2);
+ end if;
+ end process;
+ end generate;
+
+ gen_FIFO_i : for i in 1 to 3+g_NUM_EDGE_INPUTS-1 generate
+ p_fifo_i_n : process (clk_4x_logic_i)
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ s_FIFO_i(i) <= s_evttype(i) & s_var(i) & std_logic_vector(s_coarse_timestamp_h_d2) & std_logic_vector(s_coarse_timestamp_l_d2);
+ end if;
+ end process;
+ end generate gen_FIFO_i;
+
+
+-------------------------------------------------------------------------------
+-- first level of FIFOs
+-------------------------------------------------------------------------------
+
+ gen_FIFOs : for i in 0 to 3+g_NUM_EDGE_INPUTS-1 generate
+ begin
+
+ FIFO_i : entity work.FIFO
+ PORT MAP (
+ clk => clk_4x_logic_i,
+ rst => rst_fifo_i, --logic_reset_i,
+ din => s_FIFO_i(i),
+ wr_en => s_FIFO_wr(i),
+ rd_en => s_FIFO_rd(i),
+ dout => s_FIFO_o(i),
+ full => open,
+ prog_full => s_FIFO_full(i),
+ empty => s_FIFO_empty(i)
+ );
+
+ end generate gen_FIFOs;
+
+
+
+-------------------------------------------------------------------------------
+-- Reading FIFOs and multiplexing them to the output
+-------------------------------------------------------------------------------
+
+ -- NOTE: Rewrite this
+ -- Mux to send the read signal to only one FIFO. Priority order: trigger, shutter, edge, spill
+ -- every trigger word will be read before jump to other data
+
+ p_FIFO_rd: process (rst_fifo_i, s_FIFO_empty, buffer_full_i)
+ begin -- process p_generate_strobes
+ s_FIFO_rd <= (others=>'0');
+ if buffer_full_i = '0' and rst_fifo_i = '0' then
+ l_FIFO_rd: for i in 0 to 3+g_NUM_EDGE_INPUTS-1 loop
+ if s_FIFO_empty(i) = '0' then
+ s_FIFO_rd <= std_logic_vector(c_FIFO_rd_mask sll i);
+ exit l_FIFO_rd;
+ end if;
+ end loop;
+ end if;
+ end process;
+
+
+ p_data_o : process (clk_4x_logic_i)
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ if s_FIFO_rd_d1 = "0000001" then
+ s_data_o <= s_FIFO_o(0);
+ elsif s_FIFO_rd_d1 = "0000010" then
+ s_data_o <= s_FIFO_o(1);
+ elsif s_FIFO_rd_d1 = "0000100" then
+ s_data_o <= s_FIFO_o(2);
+ elsif s_FIFO_rd_d1 = "0001000" then
+ s_data_o <= s_FIFO_o(3);
+ elsif s_FIFO_rd_d1 = "0010000" then
+ s_data_o <= s_FIFO_o(4);
+ elsif s_FIFO_rd_d1 = "0100000" then
+ s_data_o <= s_FIFO_o(5);
+ elsif s_FIFO_rd_d1 = "1000000" then
+ s_data_o <= s_FIFO_o(6);
+ else
+ s_data_o <= (others=>'0');
+ end if;
+ end if;
+ end process;
+
+
+ -- Send out the data and the strobe signal
+ event_data_o <= s_data_o;
+ data_strobe_o <= '0' when s_FIFO_rd_d2 = std_logic_vector(to_unsigned(0,s_FIFO_rd_d2'length)) else
+ '1';
+
+ -- purpose: Keep track of 40MHz timestamp
+ -- type : sequential
+ -- inputs : clk_4x_logic_i
+ -- outputs:
+ p_timestamp_l: process (clk_4x_logic_i, logic_reset_i)
+ begin -- process p_timestamp
+ if rising_edge(clk_4x_logic_i) then -- rising clock edge
+ if logic_reset_i = '1' then
+ s_coarse_timestamp_l <= ( others => '0');
+ elsif ( logic_strobe_i = '1' ) then
+ s_coarse_timestamp_l <= s_coarse_timestamp_l + 1;
+ end if;
+ end if;
+ end process p_timestamp_l;
+
+ s_timestamp_h_en <= '1' when s_coarse_timestamp_l = x"ffff" else
+ '0';
+
+ p_timestamp_h: process (clk_4x_logic_i, logic_reset_i)
+ begin -- process p_timestamp
+ if rising_edge(clk_4x_logic_i) then -- rising clock edge
+ if logic_reset_i = '1' then
+ s_coarse_timestamp_h <= ( others => '0');
+ elsif ( logic_strobe_i = '1' ) and (s_timestamp_h_en='1') then
+ s_coarse_timestamp_h <= s_coarse_timestamp_h + 1;
+ end if;
+ end if;
+ end process p_timestamp_h;
+
+ -- Generate data in format decided at DESY. Put out two strobes for the
+ -- two 64 bit words.
+ -- get trigger inputs to also generate a global time-stamp ??
+ -- add trigger_inputs_active_i array (to indicate which triggers fired)
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/handshakes_rtl.vhd b/firmware/minitlu/hdl/common/handshakes_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ab893a2a99708784f934579adc8439a2593fe067
--- /dev/null
+++ b/firmware/minitlu/hdl/common/handshakes_rtl.vhd
@@ -0,0 +1,248 @@
+--=============================================================================
+--! @file handshakes_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Santiago de Compostela, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.handshakes.rtl
+--
+--! @brief Handshakes between TLU and DUTs. \n
+--
+--
+--! @author Alvaro Dosil , alvaro.dosil@usc.es
+--
+--! @date 12:08:30 25/06/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+ENTITY handshakes IS
+ GENERIC(
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ clk_i : IN std_logic;
+ Trigger_i : IN std_logic;
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus;
+ ipbus_reset_i : IN std_logic;
+ ipbus_o : OUT ipb_rbus;
+ logic_reset_i : IN std_logic;
+ Busy_i : IN std_logic;
+ AIDAhandshake_o : OUT std_logic; -- running an AIDA handshake or the old EUDET handshake
+ Trigger_o : OUT std_logic;
+ rst_or_clk_o : OUT std_logic -- CONT in schematics
+ );
+
+-- Declarations
+
+END ENTITY handshakes ;
+
+--
+ARCHITECTURE rtl OF handshakes IS
+
+ signal s_handshakeEnabled : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
+ signal s_Shutter, s_T0sync : std_logic;
+ signal s_Trigger, s_TrigAux : std_logic := '0';
+ signal s_Busy, s_Busy_d1, s_Busy_d2, s_Busy_d3 : std_logic;
+
+ signal TPx3_T0syncLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000004"; --! T0-sync length
+ signal TPx3_Start_T0sync : std_logic; --! Flag to start the T0-sync signal
+
+ signal s_Veto : std_logic := '0';
+ signal s_WU : std_logic := '0';
+ signal s_NMaxPulses : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+ signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+ signal s_PulseLen : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+ signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"00000001";
+ signal s_RearmTime : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := x"10000000";
+ signal s_PulseDelay : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0) := (others=>'0');
+ signal s_MaxPulses : std_logic;
+ signal s_pulse : std_logic;
+
+ constant c_N_CTRL : positive := 13;
+ constant c_N_STAT : positive := 13;
+ signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+ signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- IPBus interface
+ -----------------------------------------------------------------------------
+ ipbus_registers: entity work.ipbus_ctrlreg_v
+ generic map(
+ N_CTRL => c_N_CTRL,
+ N_STAT => c_N_STAT
+ )
+ port map(
+ clk => ipbus_clk_i,
+ reset=> '0',--ipbus_reset_i ,
+ ipbus_in=> ipbus_i,
+ ipbus_out=> ipbus_o,
+ d=> s_sync_status_to_ipbus,
+ q=> s_control_from_ipbus,
+ stb=> open
+ );
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_status: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_STAT )
+ port map (
+ clk_input_i => clk_i,
+ data_i => s_status_to_ipbus,
+ data_o => s_sync_status_to_ipbus,
+ clk_output_i => ipbus_clk_i);
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_ctrl: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_i);
+
+ -----------------------------------------------------------------------------
+ -- Logic not ready to use
+ -----------------------------------------------------------------------------
+
+ --Map the control registers
+ s_handshakeEnabled <= s_sync_control_from_ipbus(0);
+
+ s_status_to_ipbus(0) <= s_handshakeEnabled;
+
+
+ -- No handshake registers
+ s_NMaxPulses <= s_sync_control_from_ipbus(5);
+ s_SuDTime <= s_sync_control_from_ipbus(6);
+ s_PulseLen <= s_sync_control_from_ipbus(7);
+ s_IpDTime <= s_sync_control_from_ipbus(8);
+ s_RearmTime <= s_sync_control_from_ipbus(9);
+ s_PulseDelay <= s_sync_control_from_ipbus(10);
+ s_Veto <= s_sync_control_from_ipbus(11)(0);
+ s_WU <= s_sync_control_from_ipbus(11)(1);
+
+ s_status_to_ipbus(5) <= s_NMaxPulses;
+ s_status_to_ipbus(6) <= s_SuDTime;
+ s_status_to_ipbus(7) <= s_PulseLen;
+ s_status_to_ipbus(8) <= s_IpDTime;
+ s_status_to_ipbus(9) <= s_RearmTime;
+ s_status_to_ipbus(10) <= s_PulseDelay;
+ s_status_to_ipbus(11) <= x"0000000"& "00" & s_WU & s_Veto;
+ s_status_to_ipbus(12) <= x"0000000"& "000" & s_MaxPulses;
+
+ -- TPx3 registers
+ TPx3_Start_T0sync <= s_sync_control_from_ipbus(1)(0);
+ TPx3_T0syncLen <= x"00000001" when s_sync_control_from_ipbus(2)<x"000000002" else
+ s_sync_control_from_ipbus(2);
+
+ s_status_to_ipbus(1) <= x"0000000" & "000" & TPx3_Start_T0sync;
+ s_status_to_ipbus(2) <= TPx3_T0syncLen;
+
+
+ -----------------------------------------------------------------------------
+ -- Synchronization - Rewrite!!!
+ -----------------------------------------------------------------------------
+ p_trigger : process(Trigger_i, s_Trigger)
+ begin
+ if Trigger_i = '1' then
+ s_TrigAux <= '1';
+ elsif s_Trigger = '1' then
+ s_TrigAux <= '0';
+ end if;
+ end process p_trigger;
+
+ p_sync: process (clk_i )
+ begin -- process p_run_counter
+ if rising_edge(clk_i) then
+ s_Trigger <= s_TrigAux;
+
+ s_Busy_d1 <= Busy_i;
+ s_Busy_d2 <= s_Busy_d1;
+ s_Busy_d3 <= s_Busy_d2;
+ s_Busy <= s_Busy_d2;
+ end if;
+ end process p_sync;
+
+ -----------------------------------------------------------------------------
+ -- I/O
+ -----------------------------------------------------------------------------
+ Trigger_o <= s_Trigger when s_handshakeEnabled(1 downto 0) = "00" and s_Busy = '0' else
+ s_pulse when s_handshakeEnabled(1 downto 0) = "01" else -- No handshake
+ s_Shutter when s_handshakeEnabled(1 downto 0) = "10" else -- TPx3 handshake
+ '0';
+ rst_or_clk_o <= s_T0sync when s_handshakeEnabled(1 downto 0) = "10" else
+ '0';
+
+ AIDAhandshake_o <= not s_handshakeEnabled(3); -- s_handshakeEnabled = x"00001000" => EUDET handshake.
+ -- All handshakes with s_handshakeEnabled(3)='0' are AIDA handshakes
+
+ -- No Handshake (GPP)
+ No_handshake: entity work.GPP
+ GENERIC MAP(
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH)
+ PORT MAP(
+ clk_i => clk_i,
+ Enable_i => not (s_Busy or s_Veto),
+ Reset_i => logic_reset_i,
+ RstPulsCnt_i => '0',
+ Trigger_i => s_Trigger,
+ NMaxPulses_i => s_NMaxPulses,
+ SuDTime_i => s_SuDTime,
+ PulsLen_i => s_PulseLen,
+ IpDTime_i => s_IpDTime,
+ RearmTime_i => s_RearmTime,
+ Force_PullDown_i => s_Busy or s_Veto,
+ WU_i => s_WU,
+ PulseDelay_i => s_PulseDelay,
+ event_number_o => open,
+ MaxPulses_o => s_MaxPulses,
+ Pulse_o => s_pulse,
+ Pulse_d_o => open);
+
+ -- TPx3 Handshake
+ TPx3_logic: entity work.TPx3Logic
+ PORT MAP(
+ clk_i => clk_i,
+ Start_T0sync_i => TPx3_Start_T0sync,
+ T0syncLen_i => TPx3_T0syncLen,
+ logic_reset_i => logic_reset_i,
+ Busy_i => s_Busy,
+ Veto_i => s_Veto,
+ Shutter_o => s_Shutter,
+ T0sync_o => s_T0sync
+ );
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/i2c_master_rtl.vhd b/firmware/minitlu/hdl/common/i2c_master_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6d0bb973aa56b1e35107d8d22fd37574f7e7eed6
--- /dev/null
+++ b/firmware/minitlu/hdl/common/i2c_master_rtl.vhd
@@ -0,0 +1,97 @@
+--=============================================================================
+--! @file i2c_master_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture work.i2c_master.rtl
+--
+--! @brief Wraps the Wishbone I2C master in a wrapper where the IPBus signals\n
+--! are bundled together in a record\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 17:22:12 11/30/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+ENTITY i2c_master IS
+ PORT(
+ i2c_scl_i : IN std_logic;
+ i2c_sda_i : IN std_logic;
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
+ ipbus_reset_i : IN std_logic;
+ i2c_scl_enb_o : OUT std_logic;
+ i2c_sda_enb_o : OUT std_logic;
+ ipbus_o : OUT ipb_rbus -- signals from slave to IPBus core
+ );
+
+-- Declarations
+
+END ENTITY i2c_master ;
+
+--
+ARCHITECTURE rtl OF i2c_master IS
+
+ --signal s_i2c_scl, s_i2c_scl_o, s_i2c_scl_enb, s_i2c_sda, s_i2c_sda_enb : std_logic ;
+
+BEGIN
+
+ --i2c_scl_b <= s_i2c_scl when (s_i2c_scl_enb = '0') else 'Z';
+ --i2c_sda_b <= s_i2c_sda when (s_i2c_sda_enb = '0') else 'Z';
+
+ i2c_interface: entity work.i2c_master_top port map(
+ wb_clk_i => ipbus_clk_i,
+ wb_rst_i => ipbus_reset_i,
+ arst_i => '1',
+ wb_adr_i => ipbus_i.ipb_addr(2 downto 0),
+ wb_dat_i => ipbus_i.ipb_wdata(7 downto 0),
+ wb_dat_o => ipbus_o.ipb_rdata(7 downto 0),
+ wb_we_i => ipbus_i.ipb_write,
+ wb_stb_i => ipbus_i.ipb_strobe,
+ wb_cyc_i => '1',
+ wb_ack_o => ipbus_o.ipb_ack,
+ wb_inta_o => open,
+ scl_pad_i => i2c_scl_i,
+ scl_pad_o => open,
+ scl_padoen_o => i2c_scl_enb_o,
+ sda_pad_i => i2c_sda_i,
+ sda_pad_o => open,
+ sda_padoen_o => i2c_sda_enb_o
+ );
+
+
+ ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
+ ipbus_o.ipb_err <= '0'; -- never return an error.
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/ipbus_addr_decode.vhd b/firmware/minitlu/hdl/common/ipbus_addr_decode.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..be7540fbe68a03f87d65d8494ef57ec8c7643bee
--- /dev/null
+++ b/firmware/minitlu/hdl/common/ipbus_addr_decode.vhd
@@ -0,0 +1,56 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+ function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+ function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+ variable sel : integer;
+ begin
+ if std_match(addr, "-----------------------0001-----") then
+ sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
+ elsif std_match(addr, "-----------------------0010-----") then
+ sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
+ elsif std_match(addr, "-----------------------0011-----") then
+ sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
+ elsif std_match(addr, "-----------------------0100-----") then
+ sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
+ elsif std_match(addr, "-----------------------0101-----") then
+ sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
+ elsif std_match(addr, "-----------------------0110-----") then
+ sel := 5; -- i2c_master / base 000000c0 / mask 00000007
+ elsif std_match(addr, "-----------------------0111-----") then
+ sel := 6; -- Trigger_Generator / base 000000e0 / mask 0000001f
+ elsif std_match(addr, "-----------------------1000-----") then
+ sel := 7; -- Shutter_Generator / base 00000100 / mask 0000001f
+ elsif std_match(addr, "-----------------------1001-----") then
+ sel := 8; -- Spill_Generator / base 00000120 / mask 0000001f
+ elsif std_match(addr, "-----------------------1010-----") then
+ sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
+ elsif std_match(addr, "-----------------------1011-----") then
+ sel := 10; -- Handshakes / base 00000160 / mask 0000001f
+ elsif std_match(addr, "-----------------------0000-----") then
+ sel := 11; -- version / base 00000000 / mask 00000000
+ else
+ sel := 99;
+ end if;
+ return sel;
+ end ipbus_addr_sel;
+
+end ipbus_addr_decode;
diff --git a/firmware/minitlu/hdl/common/ipbus_ver.vhd b/firmware/minitlu/hdl/common/ipbus_ver.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bf73c67a42703443d1b34d13a0a7017a75854153
--- /dev/null
+++ b/firmware/minitlu/hdl/common/ipbus_ver.vhd
@@ -0,0 +1,41 @@
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+entity ipbus_ver is
+ port(
+ ipbus_in: in ipb_wbus;
+ ipbus_out: out ipb_rbus
+ );
+
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+ ipbus_out.ipb_rdata <= X"a5ed" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+ ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+ ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/firmware/minitlu/hdl/common/logic_clocks_rtl.vhd b/firmware/minitlu/hdl/common/logic_clocks_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ed79c062b34c0953ceab06cccc9d022b48ec3a70
--- /dev/null
+++ b/firmware/minitlu/hdl/common/logic_clocks_rtl.vhd
@@ -0,0 +1,395 @@
+--=============================================================================
+--! @file logic_clocks_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.logic_clocks.rtl
+--
+--! @brief Generates 160MHz , 640MHz clocks from an incoming 40MHz clock. \n
+--! Can switch between clock generated from on-board Xtal ( clk_logic_xtal ) and external clock\n
+--! Can also output clock to external clock pins.
+--!
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 14:20:26 11/14/12
+--
+--! @version v0.1
+--
+--! @details
+--! Address map:
+--! 0x00000000 - control/status register:
+--! bit-0 - PLL locked ( 1 = locked )
+--! bit-1 - buff-PLL locked ( 1 = locked )
+--! bit-2 - use xtal for logic ( 1 = xtal , 0= external)
+--! bit-3 - clock connector is an input ( 1=input , 0 = output)
+--! 0x00000001 - reset logic. Write to bit-zero to send reset.
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+-- Based on output of Xilinx Coregen and Alvro Dosil TLU code.
+------------------------------------------------------------------------------
+-- "Output Output Phase Duty Pk-to-Pk Phase"
+-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1___640.000______0.000______50.0______175.916____213.982
+-- CLK_OUT2___160.000______0.000______50.0______223.480____213.982
+-- CLK_OUT3____40.000______0.000______50.0______306.416____213.982
+--
+------------------------------------------------------------------------------
+-- "Input Clock Freq (MHz) Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary__________40.000____________0.010
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+ENTITY logic_clocks IS
+ PORT(
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus;
+ ipbus_reset_i : IN std_logic;
+ Reset_i : IN std_logic;
+ clk_logic_xtal_i : IN std_logic; -- ! 40MHz clock from onboard xtal
+ clk_16x_logic_o : OUT std_logic; -- 640MHz clock
+ clk_4x_logic_o : OUT std_logic; -- 160MHz clock
+ ipbus_o : OUT ipb_rbus;
+ strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
+ strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
+ extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
+ extclk_n_b : INOUT std_logic;
+ DUT_clk_o : OUT std_logic;
+ logic_clocks_locked_o : OUT std_logic;
+ logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
+ );
+
+-- Declarations
+
+END ENTITY logic_clocks ;
+
+--
+ARCHITECTURE rtl OF logic_clocks IS
+
+ signal s_clk40 , s_clk40_internal : std_logic;
+ signal s_clk160 ,s_clk160_internal : std_logic;
+ signal s_clk640 , s_clk640_internal : std_logic;
+ signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip.
+-- signal s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
+
+ -- Eventually connect up clock control & status lines to IPBus
+ --signal s_extclk_is_input : std_logic := '0';
+-- signal s_extclk_is_input_buf : std_logic := '1';
+ signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
+-- signal s_logic_clk_rst : std_logic := '0';
+ signal s_locked_pll, s_locked_bufpll : std_logic;
+
+ signal s_clk : std_logic;
+ signal s_DUT_Clk, s_DUT_Clk_o, s_DUT_ClkG : std_logic;
+ signal s_extclk, s_extclkG : std_logic;
+ -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
+ signal s_clkfbout_buf , s_clkfbout : std_logic;
+
+ signal s_strobe_generator : std_logic_vector(3 downto 0) := "1000"; -- ! Store state of ring buffer to generate strobe
+ signal s_logic_clk_generator : std_logic_vector(3 downto 0) := "1100"; --! Stores state of 40MHz "clock"
+ signal s_strobe_fb : std_logic := '0';
+
+ signal s_logic_reset_ipb, s_logic_reset_ipb_d1 : std_logic := '0';
+ -- ! Reset signal in IPBus clock domain
+ signal s_logic_reset , s_logic_reset_d1 , s_logic_reset_d2 , s_logic_reset_d3 : std_logic := '0';
+ -- ! reset signal clocked onto logic-clock domain.
+ signal s_ipbus_ack : std_logic := '0';
+
+ signal s_reset_pll : std_logic := '0';
+
+ --signal s_Reset : std_logic := '0';
+ -- ! Global Reset signal
+
+ signal s_extclk_internal : std_logic := '0';
+
+ signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- IPBus write
+ -----------------------------------------------------------------------------
+ ipbus_write: process (ipbus_clk_i)
+ begin -- process ipb_clk_i
+ if rising_edge(ipbus_clk_i) then
+
+ s_logic_reset_ipb <= '0';
+
+ if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
+
+ case ipbus_i.ipb_addr(1 downto 0) is
+ when "00" =>
+ s_clk_is_xtal <= ipbus_i.ipb_wdata(2) ; -- select clock source
+
+ when "01" =>
+ s_logic_reset_ipb <= ipbus_i.ipb_wdata(0) ; -- write to reset
+ when others => null;
+ end case;
+
+ end if;
+
+ -- register reset signal to aid timing.
+ s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
+
+ s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
+
+ -- register the clock status signals onto IPBus domain.
+ --s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+ s_clock_status_ipb <= x"0000000" & '0' & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
+ end if;
+ end process ipbus_write;
+
+ ipbus_o.ipb_ack <= s_ipbus_ack;
+ ipbus_o.ipb_err <= '0';
+
+ -----------------------------------------------------------------------------
+ -- IPBUS read
+ -----------------------------------------------------------------------------
+ with ipbus_i.ipb_addr(1 downto 0) select
+ ipbus_o.ipb_rdata <=
+ s_clock_status_ipb when "00",
+ (others => '1') when others;
+
+
+ -----------------------------------------------------------------------------
+ -- Generate reset signal on logic-clock domain
+ -- This relies on the IPBus clock being much slower than the 4x logic clock.
+ -----------------------------------------------------------------------------
+ p_reset: process (s_clk160_internal)
+ begin -- process p_reset
+ if rising_edge(s_clk160_internal) then
+ s_logic_reset_d1 <= s_logic_reset_ipb_d1;
+ s_logic_reset_d2 <= s_logic_reset_d1;
+ s_logic_reset_d3 <= s_logic_reset_d2;
+ s_logic_reset <= s_logic_reset_d2 and ( not s_logic_reset_d3);
+ end if;
+ end process p_reset;
+
+ logic_reset_o <= s_logic_reset;
+ logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+
+ ext_clk_obuf : IOBUFDS
+ generic map (
+ IOSTANDARD => "BLVDS_25")
+ port map (
+ O => s_extclk, -- Buffer output
+ IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
+ IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
+ I => s_DUT_Clk_o, -- Buffer input
+ T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
+ );
+
+
+ ddr_for_extclk_output : ODDR2
+ generic map(
+ DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
+ INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+ SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+ port map (
+ Q => s_DUT_Clk_o, -- 1-bit output data
+ C0 => clk_logic_xtal_i, -- 1-bit clock input
+ C1 => not clk_logic_xtal_i, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D0 => '1', -- 1-bit data input (associated with C0)
+ D1 => '0', -- 1-bit data input (associated with C1)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ --When an ODDR2 primitive is used in conjunction with a 3-state output, the T control pin must
+ --also use an ODDR2 primitive configured in the same mode as the ODDR2 primitive used for data
+ --output.
+ ddr_for_40MHz_tristate : ODDR2
+ generic map(
+ DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
+ INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+ SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+ port map (
+ Q => s_clk_is_ext_buf, -- 1-bit output data
+ C0 => clk_logic_xtal_i, -- 1-bit clock input
+ C1 => not clk_logic_xtal_i, --not s_clk160_internal, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D0 => not s_clk_is_xtal, -- 1-bit data input (associated with C0)
+ D1 => '0', --not s_clk_is_xtal, -- 1-bit data input (associated with C1)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+
+ --! Clock selection
+ clock_mux : BUFGMUX
+ generic map (
+ CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
+ )
+ port map (
+ O => s_DUT_Clk, -- 1-bit output: Clock buffer output
+ I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
+ I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
+ S => s_clk_is_xtal -- 1-bit input: Clock buffer select
+ );
+
+ extclk_buf : BUFG
+ port map(
+ O => s_extclkG,
+ I => s_extclk);
+
+-- IBUFG_inst : IBUFG
+-- generic map (
+-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
+-- IOSTANDARD => "DEFAULT")
+-- port map (
+-- O => s_Reset, -- Clock buffer output
+-- I => Reset_i -- Clock buffer input (connect directly to top-level port)
+-- );
+
+
+ --! Clocking primitive
+ -------------------------------------
+ --! Instantiation of the PLL primitive
+ pll_base_inst : PLL_BASE
+ generic map
+ (BANDWIDTH => "OPTIMIZED",
+ --CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT",
+ CLK_FEEDBACK => "CLKFBOUT",
+ COMPENSATION => "SYSTEM_SYNCHRONOUS",
+ DIVCLK_DIVIDE => 1,
+ CLKFBOUT_MULT => 16,
+ CLKFBOUT_PHASE => 0.000,
+ CLKOUT0_DIVIDE => 1, -- 1-->2 move from 640 to 320
+ CLKOUT0_PHASE => 0.000,
+ CLKOUT0_DUTY_CYCLE => 0.500,
+ CLKOUT1_DIVIDE => 4, -- 4-->8 move from 160 to 80
+ CLKOUT1_PHASE => 0.000,
+ CLKOUT1_DUTY_CYCLE => 0.500,
+ CLKOUT2_DIVIDE => 16, -- 16--> 32 move from 40 to 20
+ CLKOUT2_PHASE => 0.000,
+ CLKOUT2_DUTY_CYCLE => 0.500,
+ CLKIN_PERIOD => 25.000,
+ REF_JITTER => 0.010)
+ port map(
+ -- Output clocks
+ CLKFBOUT => s_clkfbout,
+ CLKOUT0 => s_clk640,
+ CLKOUT1 => s_clk160,
+ CLKOUT2 => s_clk40,
+ CLKOUT3 => open,
+ CLKOUT4 => open,
+ CLKOUT5 => open,
+ -- Status and control signals
+ LOCKED => s_locked_pll,
+-- RST => s_logic_clk_rst,
+ RST => s_reset_pll,
+ -- Input clock control
+-- CLKFBIN => s_clkfbout_buf,
+ CLKFBIN => s_clkfbout,
+ CLKIN => clk_logic_xtal_i);
+
+ s_reset_pll <= Reset_i or s_logic_reset;
+
+ -- Buffer the 16x clock and generate the ISERDES strobe signal
+ BUFPLL_inst : BUFPLL
+ generic map (
+ DIVIDE => 4)
+ port map (
+ IOCLK => s_clk640_internal, -- 1-bit output: Output I/O clock
+ LOCK => s_locked_bufpll, -- 1-bit output: Synchronized LOCK output
+ SERDESSTROBE => strobe_16x_logic_O, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+ GCLK => s_clk160_internal, -- 1-bit input: BUFG clock input
+ LOCKED => s_locked_pll, -- 1-bit input: LOCKED input from PLL
+ PLLIN => s_clk640 -- 1-bit input: Clock input from PLL
+ );
+
+ clk_16x_logic_o <= s_clk640_internal;
+ DUT_clk_o <= s_DUT_clk;
+
+
+
+ -- Generate a copy of the
+ -- purpose: generates a strobe in time with rising edge of s_clk
+ -- type : combinational
+ -- inputs : s_clk160 , s_clk
+ -- outputs: strobe_4x_logic_o
+ -- Can't use a clock signal as a combinatorial signal. Hence the baroque
+ -- method of generating a strobe. Add a mechanism to restart if the '1' gets
+ -- lost ....
+ generate_4x_strobe: process (s_clk160)-- , s_clk40_out)
+ begin -- process generate_4x_strobe
+ if rising_edge(s_clk160) then
+ if s_logic_reset = '1' then
+ s_strobe_generator <= "1000";
+ s_logic_clk_generator <= "1100";
+ else
+ s_strobe_generator <= s_strobe_generator(2 downto 0) & s_strobe_generator(3);
+ s_logic_clk_generator <= s_logic_clk_generator(2 downto 0) & s_logic_clk_generator(3);
+ end if;
+
+ end if;
+ end process generate_4x_strobe;
+
+ strobe_4x_logic_o <= s_strobe_generator(3);
+ s_clk40_out <= s_logic_clk_generator(3);
+
+ -- Try fbout out again....
+ -- buffer feedback clock
+ -------------------------------------
+ --clkf_buf : BUFG
+ --port map(
+ -- O => s_clkfbout_buf,
+ -- I => s_clkfbout);
+ ---
+
+-- clkf_buf : BUFIO2FB
+-- port map (
+-- O => s_clkfbout_buf, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
+-- I => s_clk640_internal -- 1-bit input: Feedback clock input (connect to input port)
+-- );
+
+ -- buffer 160MHz (4x) clock
+ --------------------------------------
+ clk160_o_buf : BUFG
+ port map(
+ O => s_clk160_internal,
+ I => s_clk160);
+
+ clk_4x_logic_o <= s_clk160_internal;
+
+-- -- buffer 40MHz (1x) clock
+-- --------------------------------------
+-- clk40_o_buf : BUFG
+-- port map(
+-- O => s_clk40_internal,
+-- I => s_clk40);
+
+-- clk_logic_o <= s_clk40_out;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/pulseClockDomainCrossing_rtl.vhd b/firmware/minitlu/hdl/common/pulseClockDomainCrossing_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..663cac3b9e4476ee3146730afc6efc5d79225de3
--- /dev/null
+++ b/firmware/minitlu/hdl/common/pulseClockDomainCrossing_rtl.vhd
@@ -0,0 +1,100 @@
+--=============================================================================
+--! @file pulseClockDomainCrossing_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.pulseClockDomainCrossing.rtl
+--
+--! @brief Takes a pulse synchronized with one clock and produces a
+--! pulse synchronized to another clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date September/2012
+--
+--! @version v0.1
+--
+--! @details A "ring" of D-type flip-flops is used to transfer a strobe
+--! from the input clock domain to the output clock domain and then back again.
+--! The time taken to transit from input to output is approximately
+--! two clock cycles of clock_output_i .
+--! After an additional two cycles of clk_input_i another pulse can be sent
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity pulseClockDomainCrossing is
+ port (
+ clk_input_i : in std_logic; --! clock for input
+ pulse_i : in std_logic; --! input pulse. Active high
+ clk_output_i: in std_logic; --! clock for output
+ pulse_o : out std_logic --! Single cycle pulse synchronized to clock_output_i
+ );
+
+end pulseClockDomainCrossing;
+
+architecture rtl of pulseClockDomainCrossing is
+
+ signal s_pulse_out , s_pulse_out_d1 , s_pulse_out_d2 , s_pulse_out_d3 , s_pulse_out_d4 , s_pulse_back_d1 , s_pulse_back_d2: std_logic := '0';
+
+begin -- rtl
+
+ -- purpose: registers and flip-flop on clk_input_i
+ p_input_clock_logic: process (clk_input_i)
+ begin
+ if rising_edge(clk_input_i) then
+
+ -- Register signals coming from output clock domain back to the
+ -- input clock domain
+ s_pulse_back_d1 <= s_pulse_out_d2;
+ s_pulse_back_d2 <= s_pulse_back_d1;
+
+ -- JK flip-flop
+ if (s_pulse_back_d2 = '1') then
+ s_pulse_out <= '0';
+ elsif (pulse_i = '1') then
+ s_pulse_out <= '1';
+ end if;
+
+ end if;
+ end process p_input_clock_logic;
+
+ -- purpose: registers and flip-flop on clk_output_o
+ p_output_clock_logic: process (clk_output_i)
+ begin
+ if rising_edge(clk_output_i) then
+
+ -- Register signal on input clock domain onto output clock domain
+ s_pulse_out_d1 <= s_pulse_out;
+ s_pulse_out_d2 <= s_pulse_out_d1;
+
+ s_pulse_out_d3 <= s_pulse_out_d2;
+ s_pulse_out_d4 <= s_pulse_out_d3;
+
+ -- Generate single clock-cycle pulse on pulse_o
+ pulse_o <= s_pulse_out_d3 and ( not s_pulse_out_d4 );
+
+ end if;
+ end process p_output_clock_logic;
+
+
+end rtl;
diff --git a/firmware/minitlu/hdl/common/registerCounter_rtl.vhd b/firmware/minitlu/hdl/common/registerCounter_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..de5587cd9ab98905a3da88d0eb2cd5a3c8a279ee
--- /dev/null
+++ b/firmware/minitlu/hdl/common/registerCounter_rtl.vhd
@@ -0,0 +1,113 @@
+--=============================================================================
+--! @file registerCounter_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.registerCounter.rtl
+--
+--! @brief Regularly transfers the input to the output.\n
+--! One clock for input , one clock for output\n
+--! Can't just put entire bus through a couple of register stages,\n
+--! Since this will just swap meta-stability issues for race issues.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 24/Nov/12
+--
+--! @version v0.1
+--
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! We could use gray-scale and put through registers, but this method
+--! should work well enough at the expense of latency.\n
+--! \n
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity registerCounter is
+
+ generic (
+ g_DATA_WIDTH : positive := 15); -- ! Width of counter
+
+ port (
+ clk_input_i : in std_logic; -- ! clock for input
+ data_i : in std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! data to transfer to output
+ data_o : out std_logic_vector(g_DATA_WIDTH-1 downto 0); -- ! Data now in clk_read_i domain
+ clk_output_i : in std_logic); -- ! clock for output
+
+end registerCounter;
+
+architecture rtl of registerCounter is
+ signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
+ signal s_registered_data : std_logic_vector(data_i'range) := ( others => '0'); -- ! Register to store data between clock domains
+
+ signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
+
+begin -- rtl
+
+ -- purpose: part of "ring oscillator" transfering strobe between clock domains
+ -- type : combinational
+ -- inputs : clk_read_i
+ -- outputs:
+ p_gen_capture_strobe: process (clk_input_i)
+ begin -- process p_gen_capture_strobe
+ if rising_edge(clk_input_i) then
+ s_ring_d0 <= not s_ring_d5;
+ s_ring_d1 <= s_ring_d0;
+ s_ring_d2 <= s_ring_d1;
+
+ if s_read_strobe = '1' then
+ s_registered_data <= data_i;
+ end if;
+ end if;
+ end process p_gen_capture_strobe;
+
+ s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
+ --width one clk_read_i
+
+ -- purpose: part of "ring oscillator" transfering strobe between clock domains
+ -- type : combinational
+ -- inputs : clk_output_i
+ -- outputs:
+ p_gen_output_strobe: process (clk_output_i)
+ begin -- process p_gen_output_strobe
+ if rising_edge(clk_output_i) then
+ s_ring_d3 <= s_ring_d2;
+ s_ring_d4 <= s_ring_d3;
+ s_ring_d5 <= s_ring_d4;
+
+ if s_write_strobe = '1' then
+ data_o <= s_registered_data;
+ end if;
+ end if;
+ end process p_gen_output_strobe;
+
+ s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
+ --
+end rtl;
diff --git a/firmware/minitlu/hdl/common/serdes_1_to_n_SDR.vhd b/firmware/minitlu/hdl/common/serdes_1_to_n_SDR.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a0a119e3cb6fd53afcdc50779d0affc9703b57ce
--- /dev/null
+++ b/firmware/minitlu/hdl/common/serdes_1_to_n_SDR.vhd
@@ -0,0 +1,235 @@
+------------------------------------------------------------------------------/
+-- Copyright (c) 2009 Xilinx, Inc.
+-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
+------------------------------------------------------------------------------/
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version: 1.0
+-- \ \ Filename: top_nto1_ddr_diff_rx.vhd
+-- / / Date Last Modified: November 5 2009
+-- /___/ /\ Date Created: June 1 2009
+-- \ \ / \
+-- \___\/\___\
+--
+--Device: Spartan 6
+--Purpose: Example differential input receiver for DDR clock and data using 2 x BUFIO2
+-- Serdes factor and number of data lines are set by constants in the code
+--Reference:
+--
+--Revision History:
+-- Rev 1.0 - First created (nicks)
+--
+------------------------------------------------------------------------------/
+--
+-- Disclaimer:
+--
+-- This disclaimer is not a license and does not grant any rights to the materials
+-- distributed herewith. Except as otherwise provided in a valid license issued to you
+-- by Xilinx, and to the maximum extent permitted by applicable law:
+-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
+-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
+-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
+-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
+-- or tort, including negligence, or under any other theory of liability) for any loss or damage
+-- of any kind or nature related to, arising under or in connection with these materials,
+-- including for any direct, or any indirect, special, incidental, or consequential loss
+-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
+-- as a result of any action brought by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
+--
+-- Critical Applications:
+--
+-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
+-- requiring fail-safe performance, such as life-support or safety devices or systems,
+-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
+-- or any other applications that could lead to death, personal injury, or severe property or
+-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
+-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
+-- to applicable laws and signalulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Serdes 1 to n SDR
+--! @author Alvaro Dosil
+-------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all ;
+
+library unisim ;
+use unisim.vcomponents.all ;
+
+entity serdes_1_to_n_SDR is
+generic ( g_S : integer := 4); --! Parameter to set the serdes factor 1..8
+port( clk_i : in std_logic; --! Fast clock to sample data (640MHz)
+ hclk_i : in std_logic; --! A quarter frequency clock (160MHz)
+ reset_i : in std_logic; --! reset signal
+ Data_i : in std_logic; --! 1-Bit Input data
+ strobe_i : in std_logic; --! Iserdes strobe_i
+ Data_o : out std_logic_vector(2*g_S-1 downto 0) --! data output
+ );
+
+end serdes_1_to_n_SDR;
+
+
+architecture Behavioral of serdes_1_to_n_SDR is
+
+signal s_Data_i_d_m : std_logic; -- Data_i delayed master
+signal s_Data_i_d_2m : std_logic; -- Data_i delayed master second signal
+signal s_Data_i_d_s : std_logic; -- Data_i delayed slave
+signal s_Data_i_d_2s : std_logic; -- Data_i delayed slave second signal
+signal s_Data_o : std_logic_vector(2*g_S-1 downto 0);
+
+--signal s_clk_b : std_logic;
+--signal s_ISERDES_STROBE : std_logic;
+
+begin
+
+---- Generate the ISERDES strobe signal
+--
+-- BUFPLL_inst : BUFPLL
+-- generic map (
+-- DIVIDE => 4)
+-- port map (
+-- IOCLK => s_clk_b, -- 1-bit output: Output I/O clock
+-- LOCK => open, -- 1-bit output: Synchronized LOCK output
+-- SERDESSTROBE => s_ISERDES_STROBE, -- 1-bit output: Output SERDES strobe (connect to ISERDES2/OSERDES2)
+-- GCLK => hclk_i, -- 1-bit input: BUFG clock input
+-- LOCKED => locked_pll_i, -- 1-bit input: LOCKED input from PLL
+-- PLLIN => clk_i -- 1-bit input: Clock input from PLL
+-- );
+
+
+ IODELAY2_M : IODELAY2
+ generic map (
+ COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
+ DATA_RATE => "SDR", -- "SDR" or "DDR"
+ DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
+ IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
+ IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
+ -- or "DIFF_PHASE_DETECTOR"
+ IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
+ IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
+ ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+-- SIM_TAPDELAY_VALUE=> 43 -- Per tap delay used for simulation in ps
+ )
+ port map (
+ BUSY => open, -- 1-bit output: Busy output after CAL
+ DATAOUT => s_Data_i_d_m, -- 1-bit output: Delayed data output to ISERDES/input register
+ DATAOUT2 => s_Data_i_d_2m, -- 1-bit output: Delayed data output to general FPGA fabric
+ DOUT => open, -- 1-bit output: Delayed data output
+ TOUT => open, -- 1-bit output: Delayed 3-state output
+ CAL => '0', -- 1-bit input: Initiate calibration input
+ CE => '0', -- 1-bit input: Enable INC input
+ CLK => '0', -- 1-bit input: Clock input
+ IDATAIN => Data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+ INC => '0', -- 1-bit input: Increment / decrement input
+ IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
+ IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
+ ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
+ RST => reset_i, -- 1-bit input: reset_i to zero or 1/2 of total delay period
+ T => '0' -- 1-bit input: 3-state input signal
+ );
+
+
+ IODELAY2_S : IODELAY2
+ generic map (
+ COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
+ DATA_RATE => "SDR", -- "SDR" or "DDR"
+ DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
+ IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
+ IDELAY_TYPE => "FIXED", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
+ -- or "DIFF_PHASE_DETECTOR"
+ IDELAY_VALUE => 10,--29, -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
+ IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
+ ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+ --SIM_TAPDELAY_VALUE => 43 -- Per tap delay used for simulation in ps
+ )
+ port map (
+ BUSY => open, -- 1-bit output: Busy output after CAL
+ DATAOUT => s_Data_i_d_s, -- 1-bit output: Delayed data output to ISERDES/input register
+ DATAOUT2 => s_Data_i_d_2s, -- 1-bit output: Delayed data output to general FPGA fabric
+ DOUT => open, -- 1-bit output: Delayed data output
+ TOUT => open, -- 1-bit output: Delayed 3-state output
+ CAL => '0', -- 1-bit input: Initiate calibration input
+ CE => '0', -- 1-bit input: Enable INC input
+ CLK => '0', -- 1-bit input: Clock input
+ IDATAIN => Data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
+ INC => '0', -- 1-bit input: Increment / decrement input
+ IOCLK0 => '0', -- 1-bit input: Input from the I/O clock network
+ IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
+ ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
+ RST => reset_i, -- 1-bit input: reset_i to zero or 1/2 of total delay period
+ T => '0' -- 1-bit input: 3-state input signal
+ );
+
+
+ ISERDES2_M : ISERDES2
+ generic map (
+ BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
+ DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
+ DATA_WIDTH => g_S, -- Parallel data width selection (2-8)
+ INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+ )
+ port map (
+ -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+ Q1 => s_Data_o(1),
+ Q2 => s_Data_o(3),
+ Q3 => s_Data_o(5),
+ Q4 => s_Data_o(7),
+ --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
+ VALID => open, -- 1-bit output Output status of the phase detector
+ BITSLIP => '0', -- 1-bit input Bitslip enable input
+ CE0 => '1', -- 1-bit input Clock enable input
+ CLK0 => clk_i, -- 1-bit input I/O clock network input
+ CLK1 => '0', -- 1-bit input Secondary I/O clock network input
+ CLKDIV => hclk_i, -- 1-bit input FPGA logic domain clock input
+ D => s_Data_i_d_m, -- 1-bit input Input data
+ IOCE => strobe_i, -- 1-bit input Data strobe_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
+ SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
+ );
+
+ ISERDES2_S : ISERDES2
+ generic map (
+ BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
+ DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
+ DATA_WIDTH => g_S, -- Parallel data width selection (2-8)
+ INTERFACE_TYPE => "NETWORKING_PIPELINED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
+ SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
+ )
+ port map (
+ -- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
+ Q1 => s_Data_o(0),
+ Q2 => s_Data_o(2),
+ Q3 => s_Data_o(4),
+ Q4 => s_Data_o(6),
+ --SHIFTOUT => SHIFTOUTsig, -- 1-bit output Cascade output signal for master/slave I/O
+ VALID => open, -- 1-bit output Output status of the phase detector
+ BITSLIP => '0', -- 1-bit input Bitslip enable input
+ CE0 => '1', -- 1-bit input Clock enable input
+ CLK0 => clk_i, -- 1-bit input I/O clock network input
+ CLK1 => '0', -- 1-bit input Secondary I/O clock network input
+ CLKDIV => hclk_i, -- 1-bit input FPGA logic domain clock input
+ D => s_Data_i_d_s, -- 1-bit input Input data
+ IOCE => strobe_i, -- 1-bit input Data strobe_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
+ SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
+ );
+
+reg_out : process(hclk_i)
+begin
+ if rising_edge(hclk_i) then
+ Data_o <= s_Data_o;
+ end if;
+end process;
+
+end Behavioral;
diff --git a/firmware/minitlu/hdl/common/sync_reg.vhd b/firmware/minitlu/hdl/common/sync_reg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e88eb54b67be346b7398099036524bcd023f6c9d
--- /dev/null
+++ b/firmware/minitlu/hdl/common/sync_reg.vhd
@@ -0,0 +1,50 @@
+----------------------------------------------------------------------------------
+-- Company: Universidade de Santiago de Compostela
+-- Engineer: Alvaro Dosil
+--
+-- Create Date: 15/08/2012
+-- Module Name: Conf_Regs - Behavioral
+-- Revision 1.00 - File Created
+-- Additional Comments:
+----------------------------------------------------------------------------------
+-------------------------------------------------------
+--! @file
+--! @brief Synchronization module 32b
+--! @author Alvaro Dosil
+-------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity sync_reg is
+ generic(g_Data_width : positive := 32);
+ port(
+ clk_i : in std_logic; --! synchronous clock
+ Async_i : in std_logic_vector(g_Data_width-1 downto 0); --! Asynchronous input data
+ Sync_o : out std_logic_vector(g_Data_width-1 downto 0)); --! Synchronous output data
+
+end sync_reg;
+
+--! @brief
+--! @details Synchronize words (n bits)of data
+
+architecture Behavioral of sync_reg is
+
+signal s_async_i : std_logic_vector(g_Data_width-1 downto 0);
+signal s_sync_o : std_logic_vector(g_Data_width-1 downto 0);
+begin
+
+loop0: for i in 0 to g_Data_width-1 generate
+ begin
+ reg: entity work.Reg_2clks
+ port map(
+ clk_i => clk_i,
+ async_i => s_async_i(i),
+ sync_o => s_sync_o(i));
+ end generate;
+
+s_async_i <= Async_i;
+Sync_o <= s_sync_o;
+
+end Behavioral;
+
diff --git a/firmware/minitlu/hdl/common/synchronizeRegisters_rtl.vhd b/firmware/minitlu/hdl/common/synchronizeRegisters_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..485f7318ec8399d155e01c35707a3ccfed33db4d
--- /dev/null
+++ b/firmware/minitlu/hdl/common/synchronizeRegisters_rtl.vhd
@@ -0,0 +1,114 @@
+--=============================================================================
+--! @file synchronizeRegisters_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture worklib.synchronizeRegisters.rtl
+--
+--! @brief Regularly transfers the input to the output.\n
+--! One clock for input , one clock for output\n
+--! Can't just put entire bus through a couple of register stages,\n
+--! Since this will just swap meta-stability issues for race issues.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 24/Nov/12
+--
+--! @version v0.1
+--
+--! @details A six stage "ring oscillator" is used to generate two strobes.
+--! One reads data into a register. The other registers the data to the output
+--! Three stages are clocked on clk_write_i , three stages are clocked on clk_read_i
+--! The time taken for an edge to travel round the complete loop is
+--! 2 cycles of clk_read_i and 2 cycles of clk_write_i plus two intervals
+--! that depend on the relative phase of clk_read_i and clk_write_i
+--!
+--! Based on registerCounters
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+--! David Cussans, 26/2/14 - Added registers to output to aid timing closure.
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--use work.fmcTLU.all;
+use work.ipbus_reg_types.all;
+
+entity synchronizeRegisters is
+
+ generic (
+ --g_DATA_WIDTH : positive := 15;
+ g_NUM_REGISTERS : positive := 1); -- ! Width of counter
+
+ port (
+ clk_input_i : in std_logic; -- ! clock for input
+ data_i : in ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! array of registers to transfer to output
+ data_o : out ipb_reg_v(g_NUM_REGISTERS-1 downto 0); -- ! Data now in clk_output_i domain
+ clk_output_i : in std_logic); -- ! clock for output
+
+end synchronizeRegisters;
+
+architecture rtl of synchronizeRegisters is
+ signal s_ring_d0 , s_ring_d1 , s_ring_d2 , s_ring_d3 , s_ring_d4, s_ring_d5: std_logic := '0'; -- stages in "ring oscillator" used to generate strobes
+ signal s_registered_data : ipb_reg_v(data_i'range) := ( others => ( others => '0')); -- ! Register to store data between clock domains
+
+ signal s_read_strobe , s_write_strobe : std_logic := '0'; -- ! Strobes high to register data from input and to output
+
+begin -- rtl
+
+ -- purpose: part of "ring oscillator" transfering strobe between clock domains
+ -- type : combinational
+ -- inputs : clk_read_i
+ -- outputs:
+ p_gen_capture_strobe: process (clk_input_i)
+ begin -- process p_gen_capture_strobe
+ if rising_edge(clk_input_i) then
+ s_ring_d0 <= not s_ring_d5;
+ s_ring_d1 <= s_ring_d0;
+ s_ring_d2 <= s_ring_d1;
+
+ if s_read_strobe = '1' then
+ s_registered_data <= data_i;
+ end if;
+ end if;
+ end process p_gen_capture_strobe;
+
+ s_read_strobe <= s_ring_d1 xor s_ring_d2; --! Generate a strobe with
+ --width one clk_read_i
+
+ -- purpose: part of "ring oscillator" transfering strobe between clock domains
+ -- type : combinational
+ -- inputs : clk_output_i
+ -- outputs:
+ p_gen_output_strobe: process (clk_output_i)
+ begin -- process p_gen_output_strobe
+ if rising_edge(clk_output_i) then
+ s_ring_d3 <= s_ring_d2;
+ s_ring_d4 <= s_ring_d3;
+ s_ring_d5 <= s_ring_d4;
+
+ if s_write_strobe = '1' then
+ data_o <= s_registered_data;
+ end if;
+ end if;
+ end process p_gen_output_strobe;
+
+ s_write_strobe <= s_ring_d4 xor s_ring_d5; --! Generate a strobe
+ --
+end rtl;
diff --git a/firmware/minitlu/hdl/common/triggerInputs_rtl.vhd b/firmware/minitlu/hdl/common/triggerInputs_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8a4b0b90f3ca47d46742746721d3874e5f1b30e8
--- /dev/null
+++ b/firmware/minitlu/hdl/common/triggerInputs_rtl.vhd
@@ -0,0 +1,343 @@
+--=============================================================================
+--! @file triggerInputs_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerInputs.rtl
+--
+--! @brief Measures arrival time of trigger pulses using two deserializers
+--! clocked on 14x clock ( 640MHz) \n
+--! Based on TDC code by Alvaro Dosil\n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--
+--! @date 15:43:57 11/08/12
+--
+--! @version v0.1
+--
+--! @details
+--! IPBus address 0 = control and status
+--! bit0 = reset serdes
+--! bit1 = reset counter
+--! bit2 = calibrate IDELAYs
+--! bit3 = not connected
+--!
+--! bit4 = Thresh discr IDelay(0) status prompt
+--! bit5 = Thresh discr IDelay(0) status delayed
+--! bit6 = Thresh discr IDelay(1) status prompt
+--! bit7 = Thresh discr IDelay(1) status delayed
+--! bit8 = Thresh discr IDelay(2) status prompt
+--! bit9 = Thresh discr IDelay(2) status delayed
+--! bit10= Thresh discr IDelay(3) status prompt
+--! bit11= Thresh discr IDelay(3) status delayed
+--!
+--! bit12= CFD discr IDelay(0) status prompt
+--! bit13= CFD discr IDelay(0) status delayed
+--! bit14= CFD discr IDelay(1) status prompt
+--! bit15= CFD discr IDelay(1) status delayed
+--! bit16= CFD discr IDelay(2) status prompt
+--! bit17= CFD discr IDelay(2) status delayed
+--! bit18= CFD discr IDelay(3) status prompt
+--! bit19= CFD discr IDelay(3) status delayed
+--!
+--! bit20= Thresh deserialized data monitor(0)
+--! bit21= Thresh deserialized data monitor(1)
+--! bit22= Thresh deserialized data monitor(2)
+--! bit23= Thresh deserialized data monitor(3)
+--! bit24= CFD deserialized data monitor(0)
+--! bit25= CFD deserialized data monitor(1)
+--! bit26= CFD deserialized data monitor(2)
+--! bit27= CFD deserialized data monitor(3)
+--!
+--! IPBus address 1 = edge rising(0) counter
+--! IPBus address 2 = edge rising(1) counter
+--! IPBus address 3 = edge rising(2) counter
+--! IPBus address 4 = edge rising(3) counter
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+
+library unisim ;
+use unisim.vcomponents.all;
+
+ENTITY triggerInputs IS
+ GENERIC(
+ g_NUM_INPUTS : natural := 1;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Inputs from constant-fraction discriminators
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 downto 0);--! Input from CFD
+ clk_4x_logic : IN std_logic; --! Rising edge active. By default = 4*40MHz = 160MHz
+ strobe_4x_logic_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! inputs from threshold comparators
+ reset_i : IN std_logic;
+ trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
+ trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+ trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); --! Copy of input trigger level. High bits CFD, Low threshold
+ edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
+ edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
+ edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge. Syncronous with clk_4x_logic_i
+ edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when falling edge
+ ipbus_clk_i : IN std_logic;
+ ipbus_reset_i : IN std_logic;
+ ipbus_i : IN ipb_wbus; --! Signals from IPBus core to slave
+ ipbus_o : OUT ipb_rbus; --! signals from slave to IPBus core
+ clk_16x_logic_i : IN std_logic; --! 640MHz clock ( 16x 40MHz )
+ strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
+ );
+
+-- Declarations
+
+END ENTITY triggerInputs ;
+
+--
+ARCHITECTURE rtl OF triggerInputs IS
+
+ signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
+
+ signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); --! inputs from comparator
+
+ type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
+ signal s_deserialized_threshold_data, s_deserialized_threshold_data_d , s_deserialized_cfd_data, s_deserialized_cfd_data_d : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
+
+ type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
+ signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
+
+ signal s_cfd_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
+
+ signal s_CFD_rising_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
+ signal s_CFD_falling_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
+
+ signal s_threshold_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
+ signal s_CFD_previous_late_bit : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0'); -- last bit to arrive from previous 4
+
+ signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
+
+ signal s_edge_rising_times: t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
+ signal s_edge_falling_times: t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! edge arrival time ( w.r.t. logic_strobe)
+ signal s_edge_rising: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge
+ signal s_edge_falling: std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when falling edge
+
+ constant c_N_CTRL : positive := 1;
+ constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
+ signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
+ signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
+-- signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+ signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
+
+BEGIN
+ -----------------------------------------------------------------------------
+ -- IPBus interface
+ -----------------------------------------------------------------------------
+
+ -- Can't get ipbus_syncreg_v to meet timing. So use non-syncronized followed
+ -- by synchronizer.
+ ipbus_registers: entity work.ipbus_ctrlreg_v
+ generic map (
+ N_STAT => c_N_STAT )
+ port map(
+ clk=> ipbus_clk_i,
+ reset => ipbus_reset_i ,
+ ipbus_in => ipbus_i,
+ ipbus_out => ipbus_o,
+ d=> s_sync_status_to_ipbus,
+ q=> s_control_from_ipbus,
+ stb => open
+ );
+
+ -- sync data from I/O logic to IPBus
+ sync_registers: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_STAT )
+ port map (
+ clk_input_i => clk_4x_logic,
+ data_i => s_status_to_ipbus,
+ data_o => s_sync_status_to_ipbus,
+ clk_output_i => ipbus_clk_i);
+
+ -- sync data from I/O logic to IPBus
+ sync_ipbus: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_4x_logic);
+
+ -- Map the control registers...
+ -- Register that controls IODELAY and ISERDES reset is at address 0
+ s_rst_iserdes <= reset_i or s_sync_control_from_ipbus(0)(0);
+ s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+ s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+
+ s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+ s_status_to_ipbus(0)(1) <= s_counter_reset;
+ s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+ -- Connect up unused lines in status regiser to 0.
+ s_status_to_ipbus(0)(3) <= '0';
+ s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
+
+ -----------------------------------------------------------------------------
+ -- Connect up trigger inputs to deserializers and a LUT to determine
+ -- arrival time
+ -----------------------------------------------------------------------------
+
+
+ trigger_input_loop: for triggerInput in 0 to (g_NUM_INPUTS-1) generate
+
+ thresholdInputBuffer: IBUFDS
+ generic map (
+ DIFF_TERM => true,
+ IBUF_LOW_PWR => false,
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => s_threshold_discr_input(triggerInput),
+ I => threshold_discr_p_i(triggerInput),
+ IB => threshold_discr_n_i(triggerInput)
+ );
+
+ thresholdDeserializer: entity work.dualSERDES_1to4
+ port map (
+ reset_i => s_rst_iserdes,
+ --calibrate_i => s_calibrate_idelay,
+ data_i => s_threshold_discr_input(triggerInput),
+ fastClk_i => clk_16x_logic_i,
+ fabricClk_i => clk_4x_logic,
+ strobe_i => strobe_16x_logic_i,
+ data_o => s_deserialized_threshold_data(triggerInput),
+ status_o => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
+ );
+
+ --s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput)(3 downto 0) & s_deserialized_threshold_data_d(triggerInput)(7 downto 3);
+ s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
+ thresholdLUT : entity work.arrivalTimeLUT
+ port map (
+ clk_4x_logic_i => clk_4x_logic,
+ strobe_4x_logic_i => strobe_4x_logic_i,
+ deserialized_data_i => s_deserialized_threshold_data_l(triggerInput),
+ first_rising_edge_time_o => s_edge_rising_times(triggerInput),
+ last_falling_edge_time_o => s_edge_falling_times(triggerInput),
+ rising_edge_o => s_edge_rising(triggerInput),
+ falling_edge_o => s_edge_falling(triggerInput),
+ multiple_edges_o => open
+ );
+
+ -- The leading edge may be a high-->low or a low-->high transition (
+ -- depending on polarity of input signal. ). For now assume that leading
+ -- edge is low-->high and connect trigger times and trigger output accordingly.
+ -- In the future have this selectable.
+ edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+ edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+ edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+ edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+ trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+ trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+
+
+ CFDInputBuffer: IBUFDS
+ generic map (
+ DIFF_TERM => true,
+ IBUF_LOW_PWR => false,
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => s_CFD_discr_input(triggerInput),
+ I => CFD_discr_p_i(triggerInput),
+ IB => CFD_discr_n_i(triggerInput)
+ );
+
+ CFDDeserializer: entity work.dualSERDES_1to4
+ port map (
+ reset_i => s_rst_iserdes,
+ --calibrate_i => s_calibrate_idelay,
+ data_i => s_CFD_discr_input(triggerInput),
+ fastClk_i => clk_16x_logic_i,
+ fabricClk_i => clk_4x_logic,
+ strobe_i => strobe_16x_logic_i,
+ data_o => s_deserialized_CFD_data(triggerInput),
+ status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
+ );
+ --s_deserialized_CFD_data(triggerInput) <= (others=>'0');
+
+ s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
+ CFDLUT : entity work.arrivalTimeLUT
+ port map (
+ clk_4x_logic_i => clk_4x_logic,
+ strobe_4x_logic_i => strobe_4x_logic_i,
+ deserialized_data_i => s_deserialized_CFD_data_l(triggerInput),
+ first_rising_edge_time_o => s_cfd_trigger_times(triggerInput),
+ last_falling_edge_time_o => open,
+ rising_edge_o => s_CFD_rising_edge(triggerInput),
+ falling_edge_o => s_CFD_falling_edge(triggerInput),
+ multiple_edges_o => open
+ );
+
+ p_register_delayed_bits : process ( clk_4x_logic )
+ begin
+ if rising_edge(clk_4x_logic) then
+ s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
+ --s_deserialized_threshold_data_d(triggerInput) <= s_deserialized_threshold_data(triggerInput);
+ s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+
+ -- Monitor output of serdes - just look at one per serdes
+ -- Don't care about latency so put a couple of registers in to aid
+ -- timing closure.
+ s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+ s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+
+ end if ;
+ end process;
+
+ --! Instantiate counter for output triggers.
+ --! Input I is connected to address I+1
+ cmp_inputTriggerCounter : entity work.counterWithReset
+ generic map (
+ g_COUNTER_WIDTH => g_IPBUS_WIDTH)
+ port map (
+ clock_i => clk_4x_logic,
+ reset_i => s_counter_reset,
+ enable_i => s_edge_rising(triggerInput),
+ result_o => s_status_to_ipbus(triggerInput+1));
+
+ end generate trigger_input_loop;
+
+ --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
+ --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+ --! Monitor output of deserializer
+ -- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_status_to_ipbus(0)(23 downto 20);
+ --trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_edge_rising;
+ trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
+ trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/common/triggerLogic_rtl.vhd b/firmware/minitlu/hdl/common/triggerLogic_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e2966bb4acbce570027e18b2a81dfa421835da2
--- /dev/null
+++ b/firmware/minitlu/hdl/common/triggerLogic_rtl.vhd
@@ -0,0 +1,304 @@
+--=============================================================================
+--! @file triggerLogic_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.triggerLogic.rtl
+--
+--! @brief Produces triggers from either trigger inputs or internal generator\n
+--! IPBus address map:\n
+--! 0x00000000 RO - Number of triggers issued since last reset.\n
+--! 0x00000001 RO - Number of possible triggers since last reset (i.e. pre-veto triggers)\n
+--! 0x00000010 RW - Interval between internal triggers in ticks of logic_strobe_i\n
+--! 0x00000011 RW - trigger mask ( 1 bit per input )\n
+--! 0x00000100 RW - bit-0 - internal trigger veto. Set to halt vetos.\n
+--! 0x00000101 RO - state of external veto
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 16:06:19 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: Alvaro Dosil , alvaro.dosil@usc.es </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! Move all IPBus stuff into ipbus_syncreg_v , which also handles clock domain
+--! crossing. 20/Feb/2014 , David Cussans
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+USE work.fmcTLU.all;
+
+ENTITY triggerLogic IS
+ GENERIC(
+ g_NUM_INPUTS : positive := 4;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ clk_4x_logic_i : IN std_logic; -- ! Rising edge active
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
+ ipbus_reset_i : IN std_logic;
+ logic_reset_i : IN std_logic; -- active high. Synchronous with clk_4x_logic
+ logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active
+ trigger_times_i : IN t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+ veto_i : IN std_logic; -- ! Halts triggers when high
+ trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and enabled
+ trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+ event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
+ ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
+ post_veto_trigger_o : OUT std_logic; -- ! goes high when trigger passes
+ pre_veto_trigger_o : OUT std_logic;
+ trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
+ );
+
+-- Declarations
+
+END ENTITY triggerLogic ;
+
+--
+ARCHITECTURE rtl OF triggerLogic IS
+
+ --! vector that stores trigger output for each combination of trigger inputs.
+ signal s_trigger_inputs_enabled , s_trigger_inputs_enabled_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := x"00000001";--(others=>'1');
+ signal s_external_trigger , s_internal_veto , s_internal_veto_ipb : std_logic := '0';
+ signal s_internal_trigger_interval: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- setting s_internal_trigger_interval to zero means no internal triggers
+ signal s_pre_veto_trigger_counter , s_post_veto_trigger_counter : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for triggers before and after veto
+ signal s_pre_veto_trigger_counter_ipb , s_post_veto_trigger_counter_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- ! counters for triggers before and after veto, on ipbus clock domain
+
+ signal s_triggers : std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) := (others=>'0');
+ signal s_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) := (others=>(others=>'0'));
+ signal s_internal_trigger, s_internal_trigger_d : std_logic := '0'; -- ! Strobes high for one clock cycle at intervals of s_internal_trigger_interval cycles
+-- signal s_internal_trigger_timer : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation
+ signal s_internal_trigger_timer , s_internal_trigger_timer_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); -- counter for internal trigger generation and counter delay
+ signal s_internal_trigger_active , s_internal_trigger_active_d, s_internal_trigger_active_ipb : std_logic := '0'; -- ! Goes high when internal trigger is running.
+ signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal
+
+-- signal s_logic_reset , s_logic_reset_ipb : std_logic := '0'; -- ! Take high to reset counters etc.
+ signal s_pre_veto_trigger ,s_post_veto_trigger : std_logic := '0'; -- ! Can't read from an output port so keep internal copy
+
+ signal s_AND_Window : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Time window for the trigger coincidence
+ signal s_AND_Mask, s_AND_Mask_ipb : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Mask to select the trigger inputs in coincidence
+ signal s_OR_Mask : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+ signal s_AND_trigger: std_logic := '0';
+ signal s_OR_trigger: std_logic := '0';
+
+ constant c_N_CTRL : positive := 8;
+ constant c_N_STAT : positive := 8;
+ signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+ signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+ signal s_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+ signal s_external_veto_word : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+
+BEGIN
+ -----------------------------------------------------------------------------
+ -- IPBus interface
+ -----------------------------------------------------------------------------
+ ipbus_registers: entity work.ipbus_ctrlreg_v
+ generic map(
+ N_CTRL => c_N_CTRL,
+ N_STAT => c_N_STAT
+ )
+ port map(
+ clk => ipbus_clk_i,
+ reset=> '0',--ipbus_reset_i ,
+ ipbus_in=> ipbus_i,
+ ipbus_out=> ipbus_o,
+ d=> s_sync_status_to_ipbus,
+ q=> s_control_from_ipbus,
+ stb=> open
+ );
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_status: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_STAT )
+ port map (
+ clk_input_i => clk_4x_logic_i,
+ data_i => s_status_to_ipbus,
+ data_o => s_sync_status_to_ipbus,
+ clk_output_i => ipbus_clk_i);
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_ctrl: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_4x_logic_i);
+
+ -- Map the control registers
+ -- workaround to match the number of clock cycles with the configured interval
+ s_internal_trigger_interval <= x"00000000" when s_sync_control_from_ipbus(2)<x"00000005" else
+ std_logic_vector(unsigned(s_sync_control_from_ipbus(2))-2);
+
+ s_trigger_inputs_enabled <= s_sync_control_from_ipbus(3);
+ s_veto_word <= s_sync_control_from_ipbus(4);
+ s_internal_veto <= s_veto_word(0);
+ s_AND_Mask_ipb <= s_sync_control_from_ipbus(6);
+ s_AND_Window <= s_sync_control_from_ipbus(7);
+
+ -- Map the status registers
+ s_status_to_ipbus(0) <= std_logic_vector(s_post_veto_trigger_counter);
+ s_status_to_ipbus(1) <= std_logic_vector(s_pre_veto_trigger_counter);
+ s_status_to_ipbus(2) <= s_internal_trigger_interval;
+ s_status_to_ipbus(3) <= s_trigger_inputs_enabled;
+ s_status_to_ipbus(4) <= s_veto_word;
+ s_status_to_ipbus(5) <= s_external_veto_word;
+ s_external_veto_word(0) <= veto_i;
+ s_external_veto_word(g_IPBUS_WIDTH-1 downto 1) <= (others=>'0');
+ s_status_to_ipbus(6) <= s_AND_Mask;
+ s_status_to_ipbus(7) <= s_AND_Window;
+
+ -----------------------------------------------------------------------------
+ -- Generate triggers
+ -----------------------------------------------------------------------------
+ s_AND_Mask <= s_AND_Mask_ipb and s_trigger_inputs_enabled;
+ s_OR_Mask <= (not s_AND_Mask) and s_trigger_inputs_enabled; -- Inputs not selected for coincidence will work as OR triggers.
+ --s_OR_trigger <= '0' when (s_OR_Mask(trigger_i'range) and trigger_i) = std_logic_vector(to_unsigned(0,trigger_i'length)) else
+ -- '1';
+
+ -- Trigger Filtering
+ s_external_trigger <= '0' when (s_trigger_inputs_enabled(trigger_i'range) and trigger_i) = std_logic_vector(to_unsigned(0,trigger_i'length)) else
+ '1';
+
+ s_triggers <= trigger_i and s_trigger_inputs_enabled(trigger_i'range);
+
+ trig_masks : process(trigger_times_i, s_trigger_inputs_enabled)
+ begin
+ for i in 0 to g_NUM_INPUTS-1 loop
+ s_trigger_times(i)(4 downto 3) <= trigger_times_i(i)(4 downto 3);
+ if s_trigger_inputs_enabled(i)='1' then
+ s_trigger_times(i)(2 downto 0) <= trigger_times_i(i)(2 downto 0);
+ else
+ s_trigger_times(i)(2 downto 0) <= "000";
+ end if;
+ end loop;
+ end process;
+
+ trigger_o <= s_triggers;
+ trigger_times_o <= s_trigger_times;
+
+
+
+-- --! Trigger coincidence logic
+-- coincicence_logic : entity work.coincidences
+-- generic map(
+-- g_nInputs => g_NUM_INPUTS,
+-- g_IPBUS_WIDTH => g_IPBUS_WIDTH
+-- )
+-- Port map(
+-- trigger_i => trigger_i,
+-- data_i => trigger_times_i,
+-- clk_i => clk_4x_logic_i,
+-- rst_i => logic_reset_i,
+-- Window_i => s_AND_Window,
+-- mask_i => s_AND_Mask,
+-- trigger_o => s_AND_trigger,
+-- data_first_trig_o => open,
+-- data_o => trigger_times_o
+-- );
+
+ --s_external_trigger <= s_OR_trigger; -- or s_AND_trigger;
+
+
+ --! Produce triggers....
+ trigGen : process ( clk_4x_logic_i )
+ begin
+ if rising_edge(clk_4x_logic_i) then
+ s_post_veto_trigger <= (s_external_trigger or s_internal_trigger) and (not ( s_internal_veto or veto_i) );
+ s_pre_veto_trigger <= (s_external_trigger or s_internal_trigger);
+ end if;
+ end process;
+
+
+ pre_veto_trigger_o <= s_pre_veto_trigger ;
+ post_veto_trigger_o <= s_post_veto_trigger;
+ trigger_active_o <= s_post_veto_trigger;
+
+
+ --! Internal trigger generator
+ p_internal_triggers: process (clk_4x_logic_i )
+ begin -- process p_internal_triggers
+ if rising_edge(clk_4x_logic_i) then
+ if (s_internal_trigger_interval = x"00000000") then
+ s_internal_trigger_active <= '0';
+ else
+ s_internal_trigger_active <= '1';
+ end if;
+
+ s_internal_trigger_active_d <= s_internal_trigger_active; -- signal delayed
+ s_internal_trigger_timer_d <= s_internal_trigger_timer; -- Signal delayed
+ end if;
+ end process p_internal_triggers;
+
+ s_internal_trigger <= '1' when (s_internal_trigger_timer = ( x"00000000" )) and (s_internal_trigger_timer_d = ( x"00000001" ))
+ else '0';
+
+
+
+ -- Use a coregen counter to allow timing constraints to be met.
+ c_internal_triggers: entity work.internalTriggerGenerator
+ PORT MAP (
+ clk => clk_4x_logic_i,
+ ce => s_internal_trigger_active,
+ load => s_internal_trigger or (s_internal_trigger_active and not s_internal_trigger_active_d),
+ l => s_internal_trigger_interval,
+ q => s_internal_trigger_timer
+ );
+
+ -----------------------------------------------------------------------------
+ -- Count triggers
+ -----------------------------------------------------------------------------
+ p_trigger_counter: process (clk_4x_logic_i )
+ begin -- process p_trigger_counter
+
+ if rising_edge(clk_4x_logic_i) then
+
+ if logic_reset_i = '1' then
+ s_post_veto_trigger_counter <= ( others => '0');
+ elsif s_post_veto_trigger = '1' then
+ s_post_veto_trigger_counter <= s_post_veto_trigger_counter + 1;
+ end if;
+
+ if logic_reset_i = '1' then
+ s_pre_veto_trigger_counter <= ( others => '0');
+ elsif s_pre_veto_trigger = '1' then
+ s_pre_veto_trigger_counter <= s_pre_veto_trigger_counter + 1;
+ end if;
+
+ end if;
+ end process p_trigger_counter;
+
+ event_number_o <= std_logic_vector(s_post_veto_trigger_counter);
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/test/DUTInterfaces_rtl.vhd b/firmware/minitlu/hdl/test/DUTInterfaces_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..47225c7085cb0ec834cfacb4bac10944f7811f89
--- /dev/null
+++ b/firmware/minitlu/hdl/test/DUTInterfaces_rtl.vhd
@@ -0,0 +1,240 @@
+--=============================================================================
+--! @file DUTInterfaces_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.DUTInterfaces.rtl
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:09:50 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--! Address map:\n
+--! 5-bit decoded
+--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
+--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
+--!
+--
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> Indicate if the DUT works under AIDA/EUDET style\n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+
+ENTITY DUTInterfaces IS
+ GENERIC(
+ g_NUM_DUTS : positive := 3;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ --busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ --busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ clk_4x_logic_i : IN std_logic;
+ clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus; -- Signals from IPBus core to slave
+ ipbus_reset_i : IN std_logic;
+ strobe_4x_logic_i : IN std_logic; -- ! goes high every 4th clock cycle
+ trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_i : IN std_logic; -- goes high when trigger logic issues a trigger
+ --shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
+ ipbus_o : OUT ipb_rbus; -- signals from slave to IPBus core
+ --reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ --reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ --trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ --trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ --shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ --shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ veto_o : OUT std_logic -- goes high when one or more DUT are busy
+ );
+
+-- Declarations
+
+END ENTITY DUTInterfaces ;
+
+--
+ARCHITECTURE rtl OF DUTInterfaces IS
+
+ signal s_intermediate_busy_or : std_logic_vector(g_NUM_DUTS downto 0); -- OR tree
+ signal s_veto : std_logic;
+ signal s_strobe_4x_logic_d1, clk_2x_logic : std_logic;
+ signal s_busy_from_dut , s_clk_from_dut , s_reset_or_clk_to_dut , s_trigger_to_dut , s_shutter_to_dut: std_logic_vector(g_NUM_DUTS-1 downto 0);
+ signal s_DUT_mask : std_logic_vector(g_NUM_DUTS-1 downto 0) := (others => '0'); --! Mask for the DUTs not used
+ signal s_EnableOutput : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+
+ constant c_N_CTRL : positive := 2;
+ constant c_N_STAT : positive := 2;
+ signal s_status_to_ipbus, s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+ signal s_control_from_ipbus,s_sync_control_from_ipbus : ipb_reg_v(c_N_CTRL-1 downto 0);
+BEGIN
+
+
+ -- Dummy code.
+ s_intermediate_busy_or(0) <= '0';
+ --s_busy_from_dut(g_NUM_DUTS-1 downto 0) <= (others=>'0');
+
+ -----------------------------------------------------------------------------
+ -- IPBus interface
+ -----------------------------------------------------------------------------
+ ipbus_registers: entity work.ipbus_ctrlreg_v
+ generic map(
+ N_CTRL => c_N_CTRL,
+ N_STAT => c_N_STAT
+ )
+ port map(
+ clk => ipbus_clk_i,
+ reset=> '0',--ipbus_reset_i ,
+ ipbus_in=> ipbus_i,
+ ipbus_out=> ipbus_o,
+ d=> s_sync_status_to_ipbus,
+ q=> s_control_from_ipbus,
+ stb=> open
+ );
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_status: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_STAT )
+ port map (
+ clk_input_i => clk_4x_logic_i,
+ data_i => s_status_to_ipbus,
+ data_o => s_sync_status_to_ipbus,
+ clk_output_i => ipbus_clk_i);
+
+ -- Synchronize registers from logic clock to ipbus.
+ sync_ctrl: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_4x_logic_i);
+
+ -- Map the control registers
+ s_DUT_mask <= s_sync_control_from_ipbus(0)(g_NUM_DUTS-1 downto 0);
+ s_EnableOutput <= s_sync_control_from_ipbus(1);
+
+ -- Map the status registers
+ s_status_to_ipbus(0) <= std_logic_vector(to_unsigned(0,g_IPBUS_WIDTH-g_NUM_DUTS)) & s_DUT_mask;
+ s_status_to_ipbus(1) <= s_EnableOutput;
+
+
+ -- purpose: Writes in the positive pin of the signals an 80MHz clock and the strobe_4x_logic_i in the negative one.
+ --The output signals (one signal is an lvds pair) can be enabled independently in the s_EnableOutput via IPBus.
+ -- type : combinational
+ -- inputs : clk_2x_logic , strobe_4x_logic_i, s_EnableOutput
+ -- outputs: output_0_p, output_0_n, output_1_p, output_1_n, output_2_p, output_2_n, output_3_p, output_3_n
+ duts: for dut in 1 to g_NUM_DUTS generate
+
+ output_0_p_inst : OBUF
+ port map (
+ O => output_0_p(dut-1),
+ I => s_EnableOutput(0) and clk_2x_logic -- Buffer input
+ );
+ output_0_n_inst : OBUF
+ port map (
+ O => output_0_n(dut-1),
+ I => s_EnableOutput(0) and strobe_4x_logic_i -- Buffer input
+ );
+
+ output_1_p_inst : OBUF
+ port map (
+ O => output_1_p(dut-1),
+ I => s_EnableOutput(1) and clk_2x_logic -- Buffer input
+ );
+ output_1_n_inst : OBUF
+ port map (
+ O => output_1_n(dut-1),
+ I => s_EnableOutput(1) and strobe_4x_logic_i -- Buffer input
+ );
+
+ output_2_p_inst : OBUF
+ port map (
+ O => output_2_p(dut-1),
+ I => s_EnableOutput(2) and clk_2x_logic -- Buffer input
+ );
+ output_2_n_inst : OBUF
+ port map (
+ O => output_2_n(dut-1),
+ I => s_EnableOutput(2) and strobe_4x_logic_i -- Buffer input
+ );
+ output_3_p_inst : OBUF
+ port map (
+ O => output_3_p(dut-1),
+ I => s_EnableOutput(3) and clk_2x_logic -- Buffer input
+ );
+ output_3_n_inst : OBUF
+ port map (
+ O => output_3_n(dut-1),
+ I => s_EnableOutput(3) and strobe_4x_logic_i -- Buffer input
+ );
+
+
+ s_intermediate_busy_or(dut) <= s_intermediate_busy_or(dut-1) or
+ (s_busy_from_dut(dut-1) and
+ s_DUT_mask(dut-1));
+
+ end generate duts;
+
+ s_veto <= s_intermediate_busy_or(g_NUM_DUTS);
+ clk_2x_logic <= s_strobe_4x_logic_d1 or strobe_4x_logic_i; --80 MHz clock
+
+ -- purpose: register for internal signals and output signals
+ -- type : combinational
+ -- inputs : clk_4x_logic_i , strobe_4x_logic_i , s_veto
+ -- outputs: veto_o
+ register_signals: process (clk_4x_logic_i)-- , strobe_4x_logic_i , s_veto)
+ begin -- process register_signals
+ if rising_edge(clk_4x_logic_i) then
+ veto_o <= s_veto;
+ s_strobe_4x_logic_d1 <= strobe_4x_logic_i;
+ s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
+ s_trigger_to_dut <= ( others => trigger_i );
+ --shutter_to_dut <= ( others => shutter_i );
+ end if;
+ end process register_signals;
+
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl/test/clock_divider_s6.v b/firmware/minitlu/hdl/test/clock_divider_s6.v
new file mode 100755
index 0000000000000000000000000000000000000000..3e29a336be8c059d649a8f5d9862f4dcb41c7f01
--- /dev/null
+++ b/firmware/minitlu/hdl/test/clock_divider_s6.v
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+
+module clock_divider_s6(
+ input clk,
+ output d25,
+ output d28
+ );
+
+ wire [6:0] q;
+ reg [5:0] qr = 0;
+ reg [2:0] ctr = 0;
+ //wire unconnected; // horrid hack
+
+ assign q[0] = 1'b1;
+
+ generate
+ genvar i;
+ for(i=1; i<=5; i=i+1) begin: gen_sr
+
+ SRLC32E #(
+ .INIT(32'h80000000)
+ ) sr_0 (
+ .Q(q[i]),
+ .A(5'b11111),
+ .CE(q[i-1] & ~qr[i-1]),
+ .CLK(clk),
+ .D(q[i])
+ );
+
+ always @(posedge clk)
+ begin
+ qr[i] <= q[i];
+ end
+
+ end
+ endgenerate
+
+ assign d25 = q[5];
+
+ always @(posedge clk)
+ begin
+ if(q[5] & ~qr[5]) ctr <= ctr + 1;
+ end
+
+ assign d28 = ctr[2];
+
+endmodule
diff --git a/firmware/minitlu/hdl/test/clocks_s6_extphy.vhd b/firmware/minitlu/hdl/test/clocks_s6_extphy.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..ddca849e191c6a2c380e422d3dc42b46e088e3b8
--- /dev/null
+++ b/firmware/minitlu/hdl/test/clocks_s6_extphy.vhd
@@ -0,0 +1,110 @@
+-- clocks_s6_extphy
+--
+-- Generates a 125MHz ethernet clock and 31MHz ipbus clock from the 200MHz reference
+-- Includes reset logic for ipbus
+--
+-- Dave Newbold, April 2011
+--
+-- $Id$
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.VComponents.all;
+
+entity clocks_s6_extphy is port(
+ sysclk_p, sysclk_n: in std_logic;
+ clko_125: out std_logic;
+ clko_ipb: out std_logic;
+ locked: out std_logic;
+ rsto_125: out std_logic;
+ rsto_ipb: out std_logic;
+ onehz: out std_logic
+ );
+
+end clocks_s6_extphy;
+
+architecture rtl of clocks_s6_extphy is
+
+ signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk: std_logic;
+ signal d25, d25_d, dcm_locked: std_logic;
+ signal rst: std_logic := '1';
+
+ component clock_divider_s6 port(
+ clk: in std_logic;
+ d25: out std_logic;
+ d28: out std_logic
+ );
+ end component;
+
+begin
+
+ ibufgds0: IBUFGDS port map(
+ i => sysclk_p,
+ ib => sysclk_n,
+ o => sysclk
+ );
+
+ bufg_125: BUFG port map(
+ i => clk_125_i,
+ o => clk_125_b
+ );
+
+ clko_125 <= clk_125_b;
+
+ bufg_ipb: BUFG port map(
+ i => clk_ipb_i,
+ o => clk_ipb_b
+ );
+
+ clko_ipb <= clk_ipb_b;
+
+ dcm0: DCM_CLKGEN
+ generic map(
+ CLKIN_PERIOD => 5.0,
+ CLKFX_MULTIPLY => 5,
+ CLKFX_DIVIDE => 8,
+ CLKFXDV_DIVIDE => 4
+ )
+ port map(
+ clkin => sysclk,
+ clkfx => clk_125_i,
+ clkfxdv => clk_ipb_i,
+ locked => dcm_locked,
+ rst => '0'
+ );
+
+ clkdiv: clock_divider_s6 port map(
+ clk => sysclk,
+ d25 => d25,
+ d28 => onehz
+ );
+
+ process(sysclk)
+ begin
+ if rising_edge(sysclk) then
+ d25_d <= d25;
+ if d25='1' and d25_d='0' then
+ rst <= not dcm_locked;
+ end if;
+ end if;
+ end process;
+
+ locked <= dcm_locked;
+
+ process(clk_ipb_b)
+ begin
+ if rising_edge(clk_ipb_b) then
+ rsto_ipb <= rst;
+ end if;
+ end process;
+
+ process(clk_125_b)
+ begin
+ if rising_edge(clk_125_b) then
+ rsto_125 <= rst;
+ end if;
+ end process;
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/comb_generator_rtl.vhd b/firmware/minitlu/hdl/test/comb_generator_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0ad1db2c2724fdf1664fe4ef3cd3fc3d7856ba83
--- /dev/null
+++ b/firmware/minitlu/hdl/test/comb_generator_rtl.vhd
@@ -0,0 +1,90 @@
+--@file
+--
+--@brief Generates a series of "10" bits followed by a run of "0". The number
+-- of "10" is the same as the output bit plus one.
+--
+--@detailed i.e. output(0) has "1000......0010......" etc.
+-- output(1) has "1010.......001010......" etc. and so on.
+--
+-- David Cussans, February 2011
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+
+entity comb_generator is
+
+ generic (
+ g_SEQUENCE_LENGTH : positive := 4; -- --! Length of sequence before repeat = 2^g_SEQUENCE_LENGTH
+ g_N_OUTPUT_BITS : positive := 5); -- --! Number of bits in output. g_N_OUTPUT_BITS<2^g_SEQUENCE_LENGTH
+
+ port (
+ clk_i : in std_logic; -- --! Rising edge active
+ reset_i : in std_logic; -- --! Active high. Synchronous
+ data_o : out std_logic_vector(g_N_OUTPUT_BITS-1 downto 0)); --! Output pattern
+
+ subtype t_COMB_ARRAY is std_logic_vector( 2**g_SEQUENCE_LENGTH -1 downto 0);
+ -- Function to generate a "10101010" pattern.
+ function f_GenerateComb ( v_Length : positive ) return t_COMB_ARRAY is
+ variable v_Comb : t_COMB_ARRAY ;
+ begin
+ for v_bit in v_Comb'range loop
+ if ((v_bit mod 2) = 0) then
+ v_Comb(v_bit) := '0';
+ else
+ v_Comb(v_bit) := '1';
+ end if;
+ end loop;
+ return v_Comb;
+ end f_GenerateComb;
+
+end entity comb_generator;
+
+architecture rtl of comb_generator is
+
+ signal s_counter : unsigned( g_SEQUENCE_LENGTH-1 downto 0) := ( others => '0'); -- --! roll over of the counter sets the sequence length
+ constant c_SEQUENCE_WIDTH : positive := 2**g_SEQUENCE_LENGTH; -- generate a constant to make code easier to read...
+ constant c_ZEROS : std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0) := (others => '0'); --! a vector of zeros to pad out sequence
+ constant c_COMB : std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0) := f_GenerateComb(1); -- --! Pattern of 1 and 0
+ subtype t_sequence is std_logic_vector(c_SEQUENCE_WIDTH-1 downto 0);
+ type t_patternArray is array(g_N_OUTPUT_BITS-1 downto 0) of t_sequence;
+ signal s_pattern : t_patternArray := ( others => ( others => '0')); --! Array of patterns. One for each output bit.
+
+begin -- architecture rtl
+
+ gen_bits: for v_bitNumber in 1 to g_N_OUTPUT_BITS generate
+
+ -- purpose: Generates the comb pattern. Different for each bit
+ -- type : sequential
+ -- inputs : clk_i, reset_i, s_counter
+ -- outputs: data_o(v_bitNumber)
+ p_genPattern: process (clk_i, reset_i) is
+ begin -- process p_genPattern
+ if rising_edge(clk_i) then -- rising clock edge
+ if reset_i = '1' then -- synchronous reset (active high)
+ s_counter <= ( others => '0');
+ else
+
+ s_counter <= s_counter + 1 ;
+ data_o(v_bitNumber-1) <= s_pattern(v_bitNumber-1)(0);
+
+ if ( s_counter = 0 ) then
+ s_pattern(v_bitNumber-1) <= c_COMB( (v_bitNumber*2)-1 downto 0) & c_ZEROS( c_SEQUENCE_WIDTH - (v_bitNumber*2)-1 downto 0);
+ else
+ s_pattern(v_bitNumber-1) <= '0' & s_pattern(v_bitNumber-1)(c_SEQUENCE_WIDTH-1 downto 1);
+ end if;
+ end if;
+ end if;
+ end process p_genPattern;
+
+ end generate gen_bits;
+
+
+
+end architecture rtl;
+
+
+
+
diff --git a/firmware/minitlu/hdl/test/dtype_fd.vhdl b/firmware/minitlu/hdl/test/dtype_fd.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..2ab1f6763c8db5ff55ba4fd49116bbbb499a5d7e
--- /dev/null
+++ b/firmware/minitlu/hdl/test/dtype_fd.vhdl
@@ -0,0 +1,38 @@
+----- CELL dtype_fd -----
+--
+--@file
+--
+--@brief Aims to be the same as the Xilinx "FD" primitive -
+-- D-Type flip-flop
+--
+-- Modified from D-type example in VHDL book.
+-- See Xilinx spartan6_scm.pdf
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity dtype_fd is
+
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ D : in std_logic --! Input
+ );
+
+end dtype_fd;
+
+architecture rtl of dtype_fd is
+begin
+
+ VITALBehavior : process(CLK)
+ begin
+
+ if rising_edge(CLK) then
+ Q <= D ;
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/firmware/minitlu/hdl/test/dtype_fdpe.vhdl b/firmware/minitlu/hdl/test/dtype_fdpe.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..d6c2e8a315345d0cbd35f3787cbaf4cc693ea482
--- /dev/null
+++ b/firmware/minitlu/hdl/test/dtype_fdpe.vhdl
@@ -0,0 +1,43 @@
+----- CELL dtype_fdpe -----
+--
+--@file
+--
+--@brief Aims to be the same as the Xilinx "FDPE" primitive -
+-- D-Type flip-flop with asynchronous set.
+--
+-- Modified from D-type example in VHDL book.
+-- See Xilinx spartan6_scm.pdf
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+-- use IEEE.VITAL_Timing.all;
+
+entity dtype_fdpe is
+
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ D : in std_logic; --! Input
+ CE : in std_logic; --! Clock enable
+ PRE : in std_logic --! Asynchronous preload
+ );
+
+end dtype_fdpe;
+
+architecture dtype_V of dtype_fdpe is
+begin
+
+ VITALBehavior : process(CLK, PRE , CE)
+ begin
+
+ if (PRE = '1') then
+ Q <= '1';
+ elsif ( rising_edge(CLK) and CE = '1' ) then
+ Q <= D ;
+ end if;
+ end process;
+
+end dtype_V;
+
diff --git a/firmware/minitlu/hdl/test/dtype_fdr.vhdl b/firmware/minitlu/hdl/test/dtype_fdr.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..cd388ae802200cfc9e3f50167e8b4e41a3e2befc
--- /dev/null
+++ b/firmware/minitlu/hdl/test/dtype_fdr.vhdl
@@ -0,0 +1,75 @@
+
+--! @file dtype_fdr.vhdl
+--
+
+--
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: dtype_fdr
+--
+--! @brief Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdfOutput goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
+entity dtype_fdr is
+
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ RST : in std_logic; --! Active high, synchronous
+ D : in STD_LOGIC --! Input
+ );
+
+end dtype_fdr;
+
+architecture rtl of dtype_fdr is
+begin
+
+ VITALBehavior : process(CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if (RST = '1') then
+ Q <= '0';
+ else
+ Q <= D ;
+ end if;
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/firmware/minitlu/hdl/test/dtype_fds.vhdl b/firmware/minitlu/hdl/test/dtype_fds.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..22593c5c96bcc0acccfd21615d9025ef7a5c046e
--- /dev/null
+++ b/firmware/minitlu/hdl/test/dtype_fds.vhdl
@@ -0,0 +1,76 @@
+
+--! @file dtype_fds.vhdl
+--
+
+--
+library IEEE;
+
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: dtype_fds
+--
+--! @brief Aims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
+--
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details -- Modified from D-type example in VHDL book.
+--! See Xilinx spartan6_scm.pdf
+--! Output goes high when input goes high ( asyncnronous to system clock).
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+-------------------------------------------------------------------------------
+
+entity dtype_fds is
+
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ SET : in std_logic; --! Active high, synchronous
+ D : in STD_LOGIC --! Input
+ );
+
+end dtype_fds;
+
+architecture rtl of dtype_fds is
+begin
+
+ VITALBehavior : process(CLK)
+ begin
+
+ if rising_edge(CLK) then
+ if (SET = '1') then
+ Q <= '1';
+ else
+ Q <= D ;
+ end if;
+ end if;
+ end process;
+
+end rtl;
+
diff --git a/firmware/minitlu/hdl/test/fmc-tlu_sp601_pulse_shaper.vhdl b/firmware/minitlu/hdl/test/fmc-tlu_sp601_pulse_shaper.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..f9fe826f276fc8ff8d0f059c92994a18236cc240
--- /dev/null
+++ b/firmware/minitlu/hdl/test/fmc-tlu_sp601_pulse_shaper.vhdl
@@ -0,0 +1,65 @@
+--@file
+--
+--@brief Top level for AIDA Mini-TLU in FMC format using IPBUS.
+--
+-- David Cussans, February 2011
+-------------------------------------------------------------------------------
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+--! Use library for instantiating Xilinx primitive components.
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity fmc_tlu_sp601 is
+ port (
+ SYSCLK_N , SYSCLK_P : in std_logic; --! 200MHz crystal clock
+ D : in std_logic; --! pulse input
+ Q : out std_logic; --! pulse_output
+ RST : in std_logic; --! active high. Syncronous
+ pulse_length : in std_logic_vector(3 downto 0) --!
+ --Dummy
+ --to
+ --avoid pruning
+
+ );
+
+end fmc_tlu_sp601;
+
+architecture rtl of fmc_tlu_sp601 is
+
+ -- constant MASK_WIDTH : integer := 16; -- Number of registers in shift-reg
+
+ component pulse_shaper
+ port (
+ D_a_i : in std_logic; --! Input pulse
+ Q_a_o : out std_logic; --! output pulse
+ CLK_i : in std_logic; --! Clock , rising edge active
+ RST_i : in std_logic; --! Active high. Synchronous
+ PULSE_LENGTH_i : in std_logic_vector(3 downto 0)); -- ! Load with desired
+ -- width of pulse.
+ end component;
+
+ signal buffered_clock : std_logic := '0';
+
+begin -- rtl
+
+ -- buf_sysclk : IBUFGDS
+-- port map (
+-- I => sysclk_p,
+-- IB => sysclk_n,
+-- O => buffered_clock);
+
+ -- for simulation bodge up by connecting buffered_clock to sysclk_p
+ buffered_clock <= sysclk_p;
+
+ shaper : pulse_shaper
+ port map (
+ D_a_i => D,
+ Q_a_o => Q,
+ RST_i => RST,
+ CLK_i => buffered_clock,
+ pulse_length_i => pulse_length);
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/fmc_tlu_pin_test.vhd b/firmware/minitlu/hdl/test/fmc_tlu_pin_test.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..3430ed9b7bc6040460d0c3d09fe1ebcf1c977dba
--- /dev/null
+++ b/firmware/minitlu/hdl/test/fmc_tlu_pin_test.vhd
@@ -0,0 +1,216 @@
+--=============================================================================
+--! @file fmcTlu_pinTest_struct.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL -- VHDL Architecture work.fmcTlu_pinTest.struct
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
+--
+--! @date 16:18:26 01/24/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY fmcTlu_pinTest IS
+ GENERIC(
+ g_NUM_DUTS : positive := 3;
+ g_NUM_TRIG_INPUTS : positive := 4;
+ g_NUM_EXT_SLAVES : positive := 11; --! Number of slaves outside IPBus interface
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_NUM_EDGE_INPUTS : positive := 4;
+ g_SPILL_COUNTER_WIDTH : positive := 12
+ );
+ PORT(
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
+ sysclk_p_i : IN std_logic;
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ reset_i : IN std_logic;
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
+ leds_o : OUT std_logic_vector (3 DOWNTO 0);
+ phy_rstb_o : OUT std_logic;
+ i2c_scl_b : INOUT std_logic;
+ i2c_sda_b : INOUT std_logic;
+ -- Signal definitions for TLU in normal use:
+ --busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
+ --dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
+ --extclk_n_b : INOUT std_logic;
+ --extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
+ -- Declare all as outputs for test purposes
+ busy_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ busy_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
+ dut_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ dut_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
+ spare_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
+ spare_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 1);
+ extclk_n_o : OUT std_logic;
+ extclk_p_o : OUT std_logic --! either external clock in, or a clock being driven out
+
+ );
+
+-- Declarations
+
+END ENTITY fmcTlu_pinTest ;
+
+
+
+LIBRARY work;
+--USE work.ipbus.all;
+--USE work.emac_hostbus_decl.all;
+--
+--USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;
+
+
+ARCHITECTURE struct OF fmcTlu_pinTest IS
+
+ -- Architecture declarations
+
+ constant c_NUM_OUTPUTS : positive := 6;
+ signal s_patternData : std_logic_vector( c_NUM_OUTPUTS-1 downto 0);
+ signal s_reset : std_logic := '0';
+ signal ipbus_clk : std_logic := '0';
+
+BEGIN
+
+ cmp_clks: entity work.clocks_s6_extphy
+ port map (
+ sysclk_p => sysclk_p_i,
+ sysclk_n => sysclk_n_i,
+ clk_logic_xtal_o=> OPEN,
+ clko_125 => OPEN,
+ clko_ipb => ipbus_clk,
+ locked => leds_o(2),
+ rsto_125 => OPEN,
+ rsto_ipb => s_reset,
+ onehz => leds_o(3)
+ );
+
+ leds_o(1 downto 0) <= ( others => '0');
+
+ i2c_scl_b <= 'Z';
+ i2c_sda_b <= 'Z';
+
+ cmp_pattern: entity work.comb_generator
+ generic map (
+ g_N_OUTPUT_BITS => c_NUM_OUTPUTS
+ )
+ port map (
+ clk_i => ipbus_clk,
+ reset_i => s_reset,
+ data_o => s_patternData
+ );
+
+ gen_duts: for nDut in 0 to g_NUM_DUTS-1 generate
+
+ OBUFDS_busy_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => busy_p_o(nDut), -- Diff_p output
+ OB => busy_n_o(nDut), -- Diff_n output
+ I => s_patternData(0) -- Buffer input
+ );
+
+ OBUFDS_dut_clk_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => dut_clk_p_o(nDut), -- Diff_p output
+ OB => dut_clk_n_o(nDut), -- Diff_n output
+ I => s_patternData(1) -- Buffer input
+ );
+
+ OBUFDS_reset_or_clk_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => reset_or_clk_p_o(nDut), -- Diff_p output
+ OB => reset_or_clk_n_o(nDut), -- Diff_n output
+ I => s_patternData(2) -- Buffer input
+ );
+
+ OBUFDS_triggers_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => triggers_p_o(nDut), -- Diff_p output
+ OB => triggers_n_o(nDut), -- Diff_n output
+ I => s_patternData(3) -- Buffer input
+ );
+
+ end generate gen_duts;
+
+ gen_duts1: for nDut in 1 to g_NUM_DUTS-1 generate
+ OBUFDS_spare_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => spare_p_o(nDut), -- Diff_p output
+ OB => spare_n_o(nDut), -- Diff_n output
+ I => s_patternData(4) -- Buffer input
+ );
+ end generate gen_duts1;
+
+ OBUFDS_extclk_inst : OBUFDS
+ generic map (
+ IOSTANDARD => "DEFAULT")
+ port map (
+ O => extclk_p_o, -- Diff_p output
+ OB => extclk_n_o, -- Diff_n output
+ I => s_patternData(5) -- Buffer input
+ );
+
+END ARCHITECTURE struct;
diff --git a/firmware/minitlu/hdl/test/fmc_tlu_sp601_tb.vhdl b/firmware/minitlu/hdl/test/fmc_tlu_sp601_tb.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1ac494f5ae50c5209a2f23088642a7d19bf32894
--- /dev/null
+++ b/firmware/minitlu/hdl/test/fmc_tlu_sp601_tb.vhdl
@@ -0,0 +1,160 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 16:24:12 02/25/2011
+-- Design Name:
+-- Module Name: /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/synthesis/ise/mTLU/fmc_tlu_sp601_tb.vhd
+-- Project Name: mTLU
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: fmc_tlu_sp601
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+use IEEE.Math_real.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+ENTITY fmc_tlu_sp601_tb IS
+END fmc_tlu_sp601_tb;
+
+ARCHITECTURE behavior OF fmc_tlu_sp601_tb IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT fmc_tlu_sp601
+ PORT(
+ SYSCLK_N : IN std_logic;
+ SYSCLK_P : IN std_logic;
+ D : IN std_logic;
+ Q : OUT std_logic;
+ RST: in std_logic;
+ pulse_length : IN std_logic_vector(3 downto 0)
+ );
+ END COMPONENT;
+
+ component pulse_shaper_scorer
+ port (
+ clk_i : in std_logic; -- ! system clock
+ pulse_in_a_i : in std_logic; -- ! input ( unstretched) pulse
+ pulse_out_a_i : in std_logic; -- ! stretched pulse (output of pulse_stretcher)
+ pulse_length_i : in std_logic_vector --! Parameter to pulse_strecher
+ );
+ end component;
+
+ --min and max can be swapped quite happily
+ procedure rand_int( variable seed1, seed2 : inout positive;
+ min, max : in integer;
+ result : out integer) is
+ variable rand : real;
+ begin
+ uniform(seed1, seed2, rand);
+ result := integer(real(min) + (rand * (real(max)-real(min)) ) );
+ end procedure;
+
+ --Inputs
+ signal SYSCLK_N : std_logic := '0';
+ signal SYSCLK_P : std_logic := '0';
+ signal SYSCLK : std_logic := '0';
+ signal D : std_logic := '0';
+ signal RST : std_logic := '0';
+ signal pulse_length : std_logic_vector(3 downto 0) := (others => '0');
+
+ --Outputs
+ signal Q : std_logic;
+
+ constant sysclk_period : time := 10.0 ns;
+
+ constant averagePulseWidth : real := 3.0;
+ constant averagePulseLow : real := 500.0;
+
+BEGIN
+
+ --! set pulse length to 7(?) clock cycles + internal
+-- pulse_length <= "0100" ;
+ --! set pulse length to 5 clock cycles + internal
+ pulse_length <= "0001" ;
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: fmc_tlu_sp601 PORT MAP (
+ SYSCLK_N => SYSCLK_N,
+ SYSCLK_P => SYSCLK_P,
+ D => D,
+ Q => Q,
+ RST => RST,
+ pulse_length => pulse_length
+ );
+
+ --! Instantiate "scorer" process
+ --! Examine signals and check for errors
+ scorer: pulse_shaper_scorer
+ port map (
+ clk_i => sysclk ,
+ pulse_in_a_i => D,
+ pulse_out_a_i => Q,
+ pulse_length_i => pulse_length
+ );
+
+ -- Clock process definitions
+ sysclk_process :process
+ begin
+ sysclk <= '0';
+ wait for sysclk_period/2;
+ sysclk <= '1';
+ wait for sysclk_period/2;
+ end process;
+ sysclk_n <= not sysclk;
+ sysclk_p <= sysclk;
+
+
+ -- Stimulus process
+ stim_proc: process
+ variable seed1 , seed2 : POSITIVE;
+ variable PulseWidth , PulseLow : time ;
+ variable Rand : real;
+
+ begin
+ D <= '0';
+ RST <= '1';
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ RST <= '0';
+
+ wait for sysclk_period*10;
+
+ -- insert stimulus here
+ for I in 1 to 50 loop
+ D<= '1';
+ -- wait for random pulse width
+ uniform(seed1, seed2, Rand);
+ PulseWidth := Rand * averagePulseWidth * sysclk_period;
+ wait for PulseWidth;
+ D<= '0';
+ -- wait for random gap between pulses
+ uniform(seed1, seed2, Rand);
+ PulseLow := Rand * averagePulseLow * sysclk_period;
+ wait for PulseLow;
+ end loop;
+ wait;
+ end process;
+
+END;
diff --git a/firmware/minitlu/hdl/test/fmc_tlu_top_sp601.vhd b/firmware/minitlu/hdl/test/fmc_tlu_top_sp601.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..7587013ab73124ab02a16046488495aad0533dca
--- /dev/null
+++ b/firmware/minitlu/hdl/test/fmc_tlu_top_sp601.vhd
@@ -0,0 +1,164 @@
+--=============================================================================
+--! @file fmc_tlu_top_sp601.vhd
+--=============================================================================
+-- @brief Top-level design for ipbus Maroc test . You must edit this file to set the IP and MAC addresses
+--
+--! @details Based on ipbus_demo_sp601 by Dave Newbold, 23/2/11
+--! This version is for xc6slx16 on Xilinx SP601 eval board
+--! Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
+--! You will need a license for the core
+--
+--! @author David Cussans, 31/07/12
+--
+
+-- Top-level design for trigger logic unit with IPBus readout
+--
+-- This version is for xc6slx16 on Xilinx SP601 eval board
+-- Uses the s6 soft TEMAC core with GMII inteface to an external Gb PHY
+-- You will need a license for the core
+--
+-- You must edit this file to set the IP and MAC addresses
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.ALL;
+use work.ipbus_bus_decl.all;
+use work.emac_hostbus_decl.all;
+
+--! Use UNISIM for Xilix primitives
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity fmc_tlu_top is port(
+ sysclk_p, sysclk_n : in STD_LOGIC;
+ leds: out STD_LOGIC_VECTOR(3 downto 0);
+ gmii_gtx_clk, gmii_tx_en, gmii_tx_er : out STD_LOGIC;
+ gmii_txd : out STD_LOGIC_VECTOR(7 downto 0);
+ gmii_rx_clk, gmii_rx_dv, gmii_rx_er: in STD_LOGIC;
+ gmii_rxd : in STD_LOGIC_VECTOR(7 downto 0);
+ phy_rstb : out STD_LOGIC;
+ dip_switch: in std_logic_vector(3 downto 0);
+
+ -- Main I2C signals
+ i2c_sda_io: inout std_logic;
+ i2c_scl_io: inout std_logic;
+
+ );
+end top;
+
+architecture rtl of top is
+
+ --
+ signal clk125, ipb_clk, locked, rst_125, rst_ipb, onehz : STD_LOGIC;
+ signal ipb_clk_n : STD_LOGIC;
+ signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
+ signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
+ signal ipb_master_out : ipb_wbus;
+ signal ipb_master_in : ipb_rbus;
+ signal mac_addr: std_logic_vector(47 downto 0);
+ signal ip_addr: std_logic_vector(31 downto 0);
+ signal hostbus_in: emac_hostbus_in;
+ signal hostbus_out: emac_hostbus_out;
+
+ -- signals for main I2C
+ signal i2c_sda_oen_s: std_logic;
+ signal i2c_scl_oen_s: std_logic;
+
+begin
+
+-- DCM clock generation for internal bus, ethernet
+
+ clocks: entity work.clocks_s6_extphy port map(
+ sysclk_p => sysclk_p,
+ sysclk_n => sysclk_n,
+ clko_125 => clk125,
+ clko_ipb => ipb_clk,
+ locked => locked,
+ rsto_125 => rst_125,
+ rsto_ipb => rst_ipb,
+ onehz => onehz
+ );
+
+ leds <= ('0', '0', locked, onehz);
+
+-- Ethernet MAC core and PHY interface
+-- In this version, consists of hard MAC core and GMII interface to external PHY
+-- Can be replaced by any other MAC / PHY combination
+
+ eth: entity work.eth_s6_gmii port map(
+ clk125 => clk125,
+ rst => rst_125,
+ gmii_gtx_clk => gmii_gtx_clk,
+ gmii_tx_en => gmii_tx_en,
+ gmii_tx_er => gmii_tx_er,
+ gmii_txd => gmii_txd,
+ gmii_rx_clk => gmii_rx_clk,
+ gmii_rx_dv => gmii_rx_dv,
+ gmii_rx_er => gmii_rx_er,
+ gmii_rxd => gmii_rxd,
+ txd => mac_txd,
+ txdvld => mac_txdvld,
+ txack => mac_txack,
+ rxd => mac_rxd,
+ rxclko => mac_rxclko,
+ rxdvld => mac_rxdvld,
+ rxgoodframe => mac_rxgoodframe,
+ rxbadframe => mac_rxbadframe,
+ hostbus_in => hostbus_in,
+ hostbus_out => hostbus_out
+ );
+
+ phy_rstb <= '1';
+
+-- ipbus control logic
+
+ ipbus: entity work.ipbus_ctrl_udponly port map(
+ ipb_clk => ipb_clk,
+ rst_ipb => rst_ipb,
+ rst_macclk => rst_125,
+ mac_txclk => clk125,
+ mac_rxclk => mac_rxclko,
+ mac_rxd => mac_rxd,
+ mac_rxdvld => mac_rxdvld,
+ mac_rxgoodframe => mac_rxgoodframe,
+ mac_rxbadframe => mac_rxbadframe,
+ mac_txd => mac_txd,
+ mac_txdvld => mac_txdvld,
+ mac_txack => mac_txack,
+ ipb_out => ipb_master_out,
+ ipb_in => ipb_master_in,
+ mac_addr => mac_addr,
+ ip_addr => ip_addr
+ );
+
+ mac_addr <= X"020ddba115" & dip_switch & X"0"; -- Careful here, arbitrary addresses do not always work
+ ip_addr <= X"c0a8c8" & dip_switch & X"0"; -- 192.168.200.X
+
+-- ipbus slaves live in the entity below, and can expose top-level ports
+-- The ipbus fabric is instantiated within.
+
+ slaves: entity work.slaves port map(
+ ipb_clk => ipb_clk,
+ rst => rst_ipb,
+ ipb_in => ipb_master_out,
+ ipb_out => ipb_master_in,
+-- Top level ports from here
+ hostbus_out => hostbus_in,
+ hostbus_in => hostbus_out,
+
+ gpio => open,
+ -- Main I2C signals
+ i2c_scl_i => i2c_scl_io ,
+ i2c_scl_oen_o => i2c_scl_oen_s ,
+ i2c_sda_i => i2c_sda_io,
+ i2c_sda_oen_o => i2c_sda_oen_s,
+
+ );
+
+ -- For main I2C bus, need to put in a tri-state....
+ i2c_scl_io <= '0' when (i2c_scl_oen_s = '0') else 'Z';
+ i2c_sda_io <= '0' when (i2c_sda_oen_s = '0') else 'Z';
+
+end rtl;
+
diff --git a/firmware/minitlu/hdl/test/i2c_chipscope_debug.cdc b/firmware/minitlu/hdl/test/i2c_chipscope_debug.cdc
new file mode 100644
index 0000000000000000000000000000000000000000..1ead4c373d277470c4838bfb9317a569447e32d2
--- /dev/null
+++ b/firmware/minitlu/hdl/test/i2c_chipscope_debug.cdc
@@ -0,0 +1,41 @@
+#ChipScope Core Inserter Project File Version 3.0
+#Tue Jul 23 13:58:01 BST 2013
+Project.device.designInputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
+Project.device.designOutputFile=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/top_extphy_cs.ngc
+Project.device.deviceFamily=18
+Project.device.enableRPMs=true
+Project.device.outputDirectory=/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/fmcTLU/fmcTLU_v1/_ngo
+Project.device.useSRL16=true
+Project.filter.dimension=7
+Project.filter<0>=*i2c*
+Project.filter<1>=*sda*
+Project.filter<2>=i2c*
+Project.filter<3>=ipbus_clk*
+Project.filter<4>=*wb_clk*
+Project.filter<5>=wb_clk*
+Project.filter<6>=
+Project.icon.boundaryScanChain=1
+Project.icon.enableExtTriggerIn=false
+Project.icon.enableExtTriggerOut=false
+Project.icon.triggerInPinName=
+Project.icon.triggerOutPinName=
+Project.unit.dimension=1
+Project.unit<0>.clockEdge=Rising
+Project.unit<0>.dataDepth=1024
+Project.unit<0>.dataEqualsTrigger=true
+Project.unit<0>.dataPortWidth=8
+Project.unit<0>.enableGaps=false
+Project.unit<0>.enableStorageQualification=false
+Project.unit<0>.enableTimestamps=false
+Project.unit<0>.timestampDepth=0
+Project.unit<0>.timestampWidth=0
+Project.unit<0>.triggerConditionCountWidth=0
+Project.unit<0>.triggerMatchCount<0>=1
+Project.unit<0>.triggerMatchCountWidth<0><0>=0
+Project.unit<0>.triggerMatchType<0><0>=1
+Project.unit<0>.triggerPortCount=1
+Project.unit<0>.triggerPortIsData<0>=true
+Project.unit<0>.triggerPortWidth<0>=8
+Project.unit<0>.triggerSequencerLevels=16
+Project.unit<0>.triggerSequencerType=0
+Project.unit<0>.type=ilapro
diff --git a/firmware/minitlu/hdl/test/ipbus_addr_decode.vhd b/firmware/minitlu/hdl/test/ipbus_addr_decode.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..6521459dbf6a85b9942d185a27176e84e0ef7937
--- /dev/null
+++ b/firmware/minitlu/hdl/test/ipbus_addr_decode.vhd
@@ -0,0 +1,46 @@
+-- Address decode logic for ipbus fabric
+--
+-- This file has been AUTOGENERATED from the address table - do not hand edit
+--
+-- We assume the synthesis tool is clever enough to recognise exclusive conditions
+-- in the if statement.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+use work.ipbus.all;
+
+package ipbus_addr_decode is
+
+ function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
+
+end ipbus_addr_decode;
+
+package body ipbus_addr_decode is
+
+ function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
+ variable sel : integer;
+ begin
+ if std_match(addr, "--------------------------000-00") then
+ sel := 0; -- statusReg / base 00000000 / mask 00000000
+ elsif std_match(addr, "--------------------------000-01") then
+ sel := 1; -- controlReg / base 00000001 / mask 00000000
+ elsif std_match(addr, "--------------------------000-10") then
+ sel := 2; -- pulser / base 00000002 / mask 00000000
+ elsif std_match(addr, "--------------------------001---") then
+ sel := 3; -- cbcI2C / base 00000008 / mask 00000007
+ elsif std_match(addr, "--------------------------010---") then
+ sel := 4; -- mainI2C / base 00000010 / mask 00000007
+ elsif std_match(addr, "--------------------------011---") then
+ sel := 5; -- captureBuffer / base 00000018 / mask 00000007
+ elsif std_match(addr, "--------------------------100-0-") then
+ sel := 6; -- emac_hostbus / base 00000020 / mask 00000001
+ else
+ sel := 99;
+ end if;
+ return sel;
+ end ipbus_addr_sel;
+
+end ipbus_addr_decode;
diff --git a/firmware/minitlu/hdl/test/ipbus_ver.vhd b/firmware/minitlu/hdl/test/ipbus_ver.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..81529bda8ac545c7dd15926a8d8f332ded42d02a
--- /dev/null
+++ b/firmware/minitlu/hdl/test/ipbus_ver.vhd
@@ -0,0 +1,41 @@
+-- Version register, returns a fixed value
+--
+-- To be replaced by a more coherent versioning mechanism later
+--
+-- Dave Newbold, August 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.ipbus.all;
+
+entity ipbus_ver is
+ port(
+ ipbus_in: in ipb_wbus;
+ ipbus_out: out ipb_rbus
+ );
+
+end ipbus_ver;
+
+architecture rtl of ipbus_ver is
+
+begin
+
+ ipbus_out.ipb_rdata <= X"a5cd" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+ ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
+ ipbus_out.ipb_err <= '0';
+
+end rtl;
+
+-- Build log
+--
+-- build 0x1000 : 22/08/11 : Starting build ID
+-- build 0x1001 : 29/08/11 : Version for SPI testing
+-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
+-- build 0x1003 : buggy
+-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
+-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
+-- build 0x1006 : 26/10/11 : trying with jumbo frames
+-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
+-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
+
+
diff --git a/firmware/minitlu/hdl/test/pulse_shaper.vhdl b/firmware/minitlu/hdl/test/pulse_shaper.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1d363ac8757df26cb7082eff3d098ea79cd24196
--- /dev/null
+++ b/firmware/minitlu/hdl/test/pulse_shaper.vhdl
@@ -0,0 +1,200 @@
+--=============================================================================
+--! @file pulse_shaper.vhdl
+--=============================================================================
+
+--! Standard library
+Library IEEE;
+
+--! Standard logic package
+use IEEE.STD_LOGIC_1164.all;
+
+--! Xilinx library
+Library UNISIM;
+
+--! Xilinx component
+use UNISIM.vcomponents.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: pulse_shaper
+--
+--! @brief Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details Output won't retrigger if input is still high at end of pulse.
+--! Length of pulse (in clock cycles) is pulse_length+4
+--
+--! <b>Dependencies:</b>\n
+--! dtype_fdpe
+--! dtype_fdr
+--! dtype_fds
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+--
+-------------------------------------------------------------------------------
+--! @todo Broaden pulse fed into set/reset flip-flop \n
+--
+-------------------------------------------------------------------------------
+
+entity pulse_shaper is
+ port (
+ D_a_i : in std_logic; --! Input pulse
+ Q_a_o : out std_logic; --! output pulse
+ CLK_i : in std_logic; --! Clock , rising edge active
+ RST_i : in std_logic; --! Hold high for PULSE_LENGTH+4
+ PULSE_LENGTH_i : in std_logic_vector(3 downto 0) --! length of output pulse
+ );
+
+end pulse_shaper;
+
+architecture rtl of pulse_shaper is
+
+ component dtype_fdpe
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ D : in std_logic; --! Input
+ CE : in std_logic; --! Clock enable
+ PRE : in std_logic --! Asynchronous preload
+ );
+ end component;
+
+
+ component dtype_fd
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ D : in std_logic --! Input
+ );
+ end component;
+
+ component dtype_fds
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ SET : in std_logic; --! Active high. Synchronous
+ D : in std_logic --! Input
+ );
+ end component;
+
+ component dtype_fdr
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ RST : in std_logic; --! Active high. Synchronous
+ D : in std_logic --! Input
+ );
+ end component;
+
+ signal s_vetoed_pulse_a : std_logic := '0'; --! input signal after internal veto
+
+ signal s_async_pulse_a : std_logic := '0'; -- ! Output from pre-settable D-type
+
+ signal s_srl_ce , s_srl_d , s_srl_q : std_logic := '0'; -- ! Input, output from shift reg.
+
+ signal s_Q_d1 , s_Q_d2 , s_Q_d3 : std_logic := '0'; --! Output, delayed by one clock. Used to form veto.
+
+ signal s_D_d1 , s_D_d2 : std_logic := '0'; --! Input, delayed by one clock. Used to form veto.
+
+begin -- rtl
+
+ --! Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST
+ s_srl_d <= s_Q_d2 and (not s_Q_d3);
+
+ --! Clock the SRL if the output is high ( or if the output of the SRL is high.... )
+ s_srl_ce <= s_Q_d2 or s_srl_q ;
+
+ SRL16E_inst : SRL16E
+ generic map (
+ INIT => X"0000")
+ port map (
+ Q => S_SRL_Q, -- SRL data output
+ A0 => PULSE_LENGTH_i(0), -- Select[0] input
+ A1 => PULSE_LENGTH_i(1), -- Select[1] input
+ A2 => PULSE_LENGTH_i(2), -- Select[2] input
+ A3 => PULSE_LENGTH_i(3), -- Select[3] input
+ CE => S_SRL_CE, -- Clock enable input
+ CLK => CLK_i, --Clock input
+ D => S_SRL_D -- SRL data input
+ );
+
+ --! In order for a pulse to get to the PREset input, the output must be low
+ --! and the input must be low. Goes low on RST high
+ s_vetoed_pulse_a <= D_a_i and (not s_Q_d2) and (not s_D_d2);
+
+ Q_a_o <= s_async_pulse_a; --! Connect output of FDPE to output.
+
+ --! Async. set, sync clear.
+ async_reg: dtype_fdpe
+ port map (
+ Q => s_async_pulse_a,
+ D => '0', --! Clock in zero when shift reg. spits out a '1'
+ CLK => CLK_i,
+ CE => S_SRL_Q,
+ PRE => s_vetoed_pulse_a ) ;
+
+ q_reg1 : dtype_fdr --! Delay the output signal
+ port map (
+ Q => s_Q_d1,
+ D => s_async_pulse_a,
+ RST => RST_i,
+ CLK => CLK_i
+ ) ;
+
+ --! Delay the output signal
+ q_reg2 : dtype_fds
+ port map (
+ Q => s_Q_d2,
+ D => s_Q_d1,
+ SET => RST_i, --! Take high on reset.
+ CLK => CLK_i
+ ) ;
+
+ --! Delay the output signal
+ q_reg3 : dtype_fdr
+ port map (
+ Q => s_Q_d3,
+ D => s_Q_d2,
+ RST => RST_i, --! Take low on reset
+ CLK => CLK_i
+ ) ;
+
+ d_reg1 : dtype_fd --! Delay the input
+ port map (
+ Q => s_D_d1,
+ D => D_a_i,
+ CLK => CLK_i
+ ) ;
+
+ d_reg2 : dtype_fds --! Delay the input
+ port map (
+ Q => s_D_d2,
+ D => s_D_d1,
+ SET => RST_i,
+ CLK => CLK_i
+ ) ;
+
+
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/pulse_shaper_async_dtypes.vhdl b/firmware/minitlu/hdl/test/pulse_shaper_async_dtypes.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..6ba14ad38c67726b4b0cfeb17e87083ab7600268
--- /dev/null
+++ b/firmware/minitlu/hdl/test/pulse_shaper_async_dtypes.vhdl
@@ -0,0 +1,92 @@
+----- CELL pulse_shaper -----
+--
+--@file
+--
+--@brief Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--! Pile-up will result in timing errors ( veto-cleared sync. with clock )
+--
+--! Output won't retrigger if input is still high at end of pulse.
+--
+--! Fill top bits of PULSE_MASK
+--! For example for a pulse width of 4.X clock cycles load '1111000000000000'
+--
+-- David Cussans, Feb 2011
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity pulse_shaper_async_dtypes is
+ generic (
+ MASK_WIDTH : integer := 16); --! Width of shift register and hence maximum width of pulse
+ port (
+ D : in std_logic; --! Input pulse
+ Q : out std_logic; --! output pulse
+ CLK : in std_logic; --! Clock , rising edge active
+ PULSE_MASK : in std_logic_vector(MASK_WIDTH-1 downto 0)); -- ! preload for shift-register. Fill with number of '1's that the ouput pulse should be
+
+end pulse_shaper_async_dtypes;
+
+architecture rtl of pulse_shaper_async_dtypes is
+
+ component dtype_fdpe
+ port(
+ Q : out std_logic; --! Output
+ CLK : in std_logic; --! Clock - rising edge active
+ D : in std_logic; --! Input
+ CE : in std_logic; --! Clock enable
+ PRE : in std_logic --! Asynchronous preload
+ );
+ end component;
+
+ signal shift_reg : std_logic_vector(MASK_WIDTH downto 0) := ( others => '0' ); --! shift register holding '1's to be shifted out
+
+ signal preload : std_logic_vector(MASK_WIDTH-1 downto 0) := ( others => '0' ); --! Mask register holding '1's to be shifted out
+
+ signal vetoed_pulse : std_logic := '0'; --! input signal after internal veto
+
+ signal Q_R1 , Q_R2 , D_R1 : std_logic := '0'; --! Output, input delayed by one clock. Used
+ --to form veto.
+
+begin -- rtl
+
+ shift_reg(0) <= '0'; --! Shift in zero at start of SReg.
+
+ --! Generate a shift register out of flip-flops.
+ --! Unfortunately SRL16 , SRL32 don't have async. load.
+ SR : for bit in 0 to MASK_WIDTH-1 generate
+ preload(bit) <= (vetoed_pulse and pulse_mask(bit));
+ dtype : dtype_fdpe
+ port map (
+ Q => shift_reg(bit+1),
+ D => shift_reg(bit),
+ CLK => CLK,
+ CE => '1',
+ PRE => preload(bit)) ;
+ end generate SR ;
+
+ Q <= shift_reg(MASK_WIDTH); --! Take output from end of SR.
+
+ q_reg : dtype_fdpe --! Delay the output signal
+ port map (
+ Q => Q_R1,
+ D => shift_reg(MASK_WIDTH),
+ CLK => CLK,
+ CE => '1',
+ PRE => '0') ;
+
+ d_reg : dtype_fdpe --! Delay the input signal
+ port map (
+ Q => D_R1,
+ D => D,
+ CLK => CLK,
+ CE => '1',
+ PRE => '0') ;
+
+ --! Arrgh... problems with glitching if veto immediately.
+ -- put in a transparent latch or something to force some delay???
+ vetoed_pulse <= D and (not shift_reg(MASK_WIDTH) ) and (not Q_R1) and (not D_R1);
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/pulse_shaper_scorer.vhdl b/firmware/minitlu/hdl/test/pulse_shaper_scorer.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..ef7b48acb7403dd2c0955d41ab3315ac1339e0a5
--- /dev/null
+++ b/firmware/minitlu/hdl/test/pulse_shaper_scorer.vhdl
@@ -0,0 +1,67 @@
+--=============================================================================
+--! @file pulse_stretcher_scorer.vhdl
+--=============================================================================
+
+--! Standard library
+Library IEEE;
+
+--! Standard logic package
+use IEEE.STD_LOGIC_1164.all;
+
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group --
+-- --
+-------------------------------------------------------------------------------
+--
+-- unit name: pulse_stretcher_scoer
+--
+--! @brief Checks that pulse_shaper is behaving correctly.
+--! Check for Output goes high when input goes high ( asyncnronous to system clock).
+--! Output goes low again a controllable number of clock cycles later,
+--! synchronous with the rising edge of the clock.
+--! Gap of at least one clock cycle before output goes high again.
+--
+--! @author David.Cussans@bristol.ac.uk
+--
+--! @date 7/May/2011
+--
+--! @version 0.1
+--
+--! @details
+--
+--
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--! <reference one> \n
+--! <reference two>
+--!
+--! <b>Modified by:</b>\n
+--! Author: <name>
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+--! <date> <initials> <log>\n
+--! <extended description>
+--
+-------------------------------------------------------------------------------
+--! @todo \n
+--
+-------------------------------------------------------------------------------
+
+entity pulse_shaper_scorer is
+ port (
+ clk_i : in std_logic; -- ! system clock
+ pulse_in_a_i : in std_logic; -- ! input ( unstretched) pulse
+ pulse_out_a_i : in std_logic -- ! stretched pulse (output of pulse_stretcher)
+ pulse_length_i : in std_logic_vector; --! Parameter to pulse_strecher
+ );
+end pulse_shaper_scorer;
+
+architecture rtl of pulse_shaper_scorer is
+
+
+begin -- rtl
+
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/slaves.vhd b/firmware/minitlu/hdl/test/slaves.vhd
new file mode 100755
index 0000000000000000000000000000000000000000..0bb0f37ce106c6585c361dbd0d426c141469c904
--- /dev/null
+++ b/firmware/minitlu/hdl/test/slaves.vhd
@@ -0,0 +1,199 @@
+-- The ipbus slaves live in this entity - modify according to requirements
+--
+-- Ports can be added to give ipbus slaves access to the chip top level.
+--
+-- Dave Newbold, February 2011
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+use work.ipbus.ALL;
+use work.emac_hostbus_decl.all;
+
+entity slaves is port(
+ ipb_clk, rst : in STD_LOGIC;
+ ipb_in : in ipb_wbus;
+ ipb_out : out ipb_rbus;
+-- Top level ports from here
+ hostbus_out: out emac_hostbus_in;
+ hostbus_in: in emac_hostbus_out;
+
+ -- GPIO
+ gpio : out STD_LOGIC_VECTOR(3 downto 0);
+ -- Main I2C signals
+ i2c_scl_i: in std_logic;
+ i2c_scl_oen_o: out std_logic;
+ i2c_sda_i: in std_logic;
+ i2c_sda_oen_o: out std_logic;
+ -- CBC I2C signals
+ cbc_i2c_sda_enb_o: out std_logic; --! Active low. SDA pulled low when enb is high
+ cbc_i2c_scl_o: out std_logic; --! I2C Clock output.
+ cbc_i2c_sda_i : in std_logic;
+ -- CBC "fast" signals
+ cbc_trg_o, ext_trg_o, cbc_reset_o: out std_logic;
+ cbc_data_i: in std_logic
+
+ );
+
+end slaves;
+
+architecture rtl of slaves is
+
+ constant NSLV: positive := 7;
+ signal ipbw: ipb_wbus_array(NSLV-1 downto 0);
+ signal ipbr, ipbr_d: ipb_rbus_array(NSLV-1 downto 0);
+
+ signal cbc_i2c_scl_o_int: std_logic;
+ signal ctrl_reg: std_logic_vector(31 downto 0);
+ signal s_pulse_reg : std_logic_vector(31 downto 0); -- ! pulsed control signals
+
+ signal s_cbc_reset : std_logic := '0'; -- ! Active high. Driven from cbcstuff
+
+ signal s_cap_trg : std_logic := '0'; -- ! Starts capture of incoming data into capture buffer
+
+begin
+
+ fabric: entity work.ipbus_fabric
+ generic map(NSLV => NSLV)
+ port map(
+ ipb_clk => ipb_clk,
+ rst => rst,
+ ipb_in => ipb_in,
+ ipb_out => ipb_out,
+ ipb_to_slaves => ipbw,
+ ipb_from_slaves => ipbr
+ );
+
+-- Slave 0: version register
+
+ slave0: entity work.ipbus_ver
+ port map(
+ ipbus_in => ipbw(0),
+ ipbus_out => ipbr(0));
+
+ -- Slave 1: 32b register
+ slave1: entity work.ipbus_reg
+ generic map(addr_width => 0)
+ port map(
+ clk => ipb_clk,
+ reset => rst,
+ ipbus_in => ipbw(1),
+ ipbus_out => ipbr(1),
+ q => ctrl_reg
+ );
+
+ s_cbc_reset <= ctrl_reg(16);
+ cbc_reset_o <= s_cbc_reset;
+
+ -- Slave 2: 32b pulser
+ slave2: entity work.ipbus_pulser
+ port map(
+ clk_i => ipb_clk,
+ reset_i => rst,
+ ipbus_i => ipbw(2),
+ ipbus_o => ipbr(2),
+ q_o => s_pulse_reg
+ );
+
+ -- CBC clock and trigger signals. Connected to slave-1 ( 32 bit register )
+ cbcstuff: entity work.cbc_logic
+ port map(
+ clk_i => ipb_clk,
+ cbc_trg_o => cbc_trg_o,
+ ext_trg_o => ext_trg_o,
+ cap_trg_o => s_cap_trg,
+ go_p_i => s_pulse_reg(0),
+ delay_i => unsigned(ctrl_reg(31 downto 24)),
+ trg_patt_i => ctrl_reg(22 downto 20)
+ );
+
+
+ -- Slave 3: I2C core connected to CBC
+
+ slave3: entity work.i2c_master_top
+ generic map (
+ ARST_LVL => 0
+ )
+ port map(
+ wb_clk_i => ipb_clk,
+ wb_rst_i => rst,
+ arst_i => '1', --! Active low reset.
+ wb_adr_i => ipbw(3).ipb_addr(2 downto 0),
+ wb_dat_i => ipbw(3).ipb_wdata(7 downto 0),
+ wb_dat_o => ipbr(3).ipb_rdata(7 downto 0),
+ wb_we_i => ipbw(3).ipb_write,
+ wb_stb_i => ipbw(3).ipb_strobe,
+ wb_cyc_i => '1',
+ wb_ack_o => ipbr(3).ipb_ack,
+ wb_inta_o => open,
+ scl_pad_i => cbc_i2c_scl_o_int,
+ scl_pad_o => open,
+ scl_padoen_o => cbc_i2c_scl_o_int,
+ sda_pad_i => cbc_i2c_sda_i,
+ sda_pad_o => open,
+ sda_padoen_o => cbc_i2c_sda_enb_o
+ );
+
+
+ cbc_i2c_scl_o <= cbc_i2c_scl_o_int;
+
+ ipbr(3).ipb_rdata(31 downto 8) <= (others => '0');
+
+
+ -- Slave 4: I2C core connected to main I2C
+ slave4: entity work.i2c_master_top
+ generic map (
+ ARST_LVL => 0
+ )
+ port map(
+ wb_clk_i => ipb_clk,
+ wb_rst_i => rst,
+ arst_i => '1', --! Active low reset.
+ wb_adr_i => ipbw(4).ipb_addr(2 downto 0),
+ wb_dat_i => ipbw(4).ipb_wdata(7 downto 0),
+ wb_dat_o => ipbr(4).ipb_rdata(7 downto 0),
+ wb_we_i => ipbw(4).ipb_write,
+ wb_stb_i => ipbw(4).ipb_strobe,
+ wb_cyc_i => '1',
+ wb_ack_o => ipbr(4).ipb_ack,
+ wb_inta_o => open,
+ scl_pad_i => i2c_scl_i,
+ scl_pad_o => open,
+ scl_padoen_o => i2c_scl_oen_o,
+ sda_pad_i => i2c_sda_i,
+ sda_pad_o => open,
+ sda_padoen_o => i2c_sda_oen_o
+ );
+ ipbr(4).ipb_rdata(31 downto 8) <= (others => '0');
+
+ -- Slave 5: Capture register.
+ slave5 : entity work.ipbus_capture_buffer
+ generic map (
+ g_DATA_WIDTH => 32, --! Width of WB bus
+ g_RAM_ADDRESS_WIDTH => 3) --! size of RAM = 2^ram_address_width
+ port map (
+ -- Wishbone signals
+ ipbus_clk_i => ipb_clk,
+ ipbus_i => ipbw(5),
+ ipbus_o => ipbr(5),
+ -- Data to capture.
+ reset_i => s_cbc_reset,
+ cap_clk_i => ipb_clk,
+ cap_d_i => cbc_data_i,
+ cap_go_i => s_cap_trg,
+ cap_edge_i => ctrl_reg(8)
+ );
+
+
+-- Slave 6: MAC host interface
+
+ slave6: entity work.ipbus_emac_hostbus
+ port map(
+ clk => ipb_clk,
+ reset => rst,
+ ipbus_in => ipbw(6),
+ ipbus_out => ipbr(6),
+ hostbus_out => hostbus_out,
+ hostbus_in => hostbus_in);
+
+end rtl;
diff --git a/firmware/minitlu/hdl/test/sp601_FMC_mTLU.ucf b/firmware/minitlu/hdl/test/sp601_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..9ae9c0d9395019baee0834ba5947cb0cb19ee4f7
--- /dev/null
+++ b/firmware/minitlu/hdl/test/sp601_FMC_mTLU.ucf
@@ -0,0 +1,176 @@
+NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET I6/s_clk_is_xtal TIG;
+
+NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=D14;
+NET dip_switch_i<1> LOC=E12;
+NET dip_switch_i<2> LOC=F12;
+NET dip_switch_i<3> LOC=V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
+
+# Main I2C bus
+NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
+NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
+
+#
+# I/O to devices under test
+
+
+#NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
+##NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
+##NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
+##NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
+
+# Remove for now.
+#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
+##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
+##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
+##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+#NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
+#NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
+#
+#NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
+#NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+#
+#NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
+#NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
+#
+#NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
+#NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
+
+# Threshold comparator outputs
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
+NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
+
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
+NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
+NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
+NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+
+#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+
+# GPIO pins for debugging.
+#NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
+#NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
+#NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
+#NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
+#NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
+#NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
+#NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
+#NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
+
+NET "output_0_p[0]" LOC = D8;
+NET "output_0_p[1]" LOC = U15;
+NET "output_0_p[2]" LOC = G11;
+NET "output_0_n[0]" LOC = C8;
+NET "output_0_n[1]" LOC = V15;
+NET "output_0_n[2]" LOC = F10;
+NET "output_1_p[0]" LOC = T6;
+NET "output_1_p[1]" LOC = U8;
+NET "output_1_p[2]" LOC = F11;
+NET "output_1_n[0]" LOC = V6;
+NET "output_1_n[1]" LOC = V8;
+NET "output_1_n[2]" LOC = E11;
+NET "output_2_p[0]" LOC = M10;
+NET "output_2_p[1]" LOC = T4;
+NET "output_2_p[2]" LOC = B16;
+NET "output_2_n[0]" LOC = N9;
+NET "output_2_n[1]" LOC = V4;
+NET "output_2_n[2]" LOC = A16;
+NET "output_3_p[0]" LOC = D12;
+NET "output_3_p[1]" LOC = U11;
+NET "output_3_p[2]" LOC = E7;
+NET "output_3_n[0]" LOC = C12;
+NET "output_3_n[1]" LOC = V11;
+NET "output_3_n[2]" LOC = E8;
\ No newline at end of file
diff --git a/firmware/minitlu/hdl/test/sp601_FMC_mTLU_v1a.ucf b/firmware/minitlu/hdl/test/sp601_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..c605cd9d78f22933b891b835b8a4f3abd617dba7
--- /dev/null
+++ b/firmware/minitlu/hdl/test/sp601_FMC_mTLU_v1a.ucf
@@ -0,0 +1,279 @@
+#
+# UCF for version 1a of updated mini-TLU
+#
+
+NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
+NET "sysclk_p_i" LOC = K15;
+NET "sysclk_p_i" IOSTANDARD = LVDS_25;
+NET "sysclk_p_i" DIFF_TERM = "TRUE";
+NET "sysclk_n_i" LOC = K16;
+NET "sysclk_n_i" IOSTANDARD = LVDS_25;
+NET "sysclk_n_i" DIFF_TERM = "TRUE";
+
+TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET "I6/s_clk_is_xtal" TIG;
+
+NET "leds_o[0]" LOC = E13;
+NET "leds_o[0]" IOSTANDARD = LVCMOS25;
+NET "leds_o[1]" LOC = C14;
+NET "leds_o[1]" IOSTANDARD = LVCMOS25;
+NET "leds_o[2]" LOC = C4;
+NET "leds_o[2]" IOSTANDARD = LVCMOS25;
+NET "leds_o[3]" LOC = A4;
+NET "leds_o[3]" IOSTANDARD = LVCMOS25;
+
+NET "dip_switch_i[0]" LOC = D14;
+NET "dip_switch_i[1]" LOC = E12;
+NET "dip_switch_i[2]" LOC = F12;
+NET "dip_switch_i[3]" LOC = V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
+TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET "gmii_gtx_clk_o" LOC = A9;
+NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
+NET "gmii_gtx_clk_o" SLEW = FAST;
+NET "gmii_txd_o[0]" LOC = F8;
+NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[1]" LOC = G8;
+NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[2]" LOC = A6;
+NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[3]" LOC = B6;
+NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[4]" LOC = E6;
+NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[5]" LOC = F7;
+NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[6]" LOC = A5;
+NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[7]" LOC = C5;
+NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_en_o" LOC = B8;
+NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_er_o" LOC = A8;
+NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;
+
+NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
+NET "gmii_rx_clk_i" LOC = L16;
+NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
+TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
+OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
+NET "gmii_rxd_i[0]" LOC = M14;
+NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[1]" LOC = U18;
+NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[2]" LOC = U17;
+NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[3]" LOC = T18;
+NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[4]" LOC = T17;
+NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[5]" LOC = N16;
+NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[6]" LOC = N15;
+NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[7]" LOC = P18;
+NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_dv_i" LOC = N18;
+NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_er_i" LOC = P17;
+NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;
+
+NET "phy_rstb_o" LOC = L13;
+NET "phy_rstb_o" IOSTANDARD = LVCMOS25;
+
+# Main I2C bus
+## C30 on FMC
+NET "i2c_scl_b" LOC = P11;
+## C31 on FMC
+NET "i2c_sda_b" LOC = N10;
+
+#
+# I/O to devices under test
+
+#NET "BUSY_N_I<0>" LOC = "P7"; ## "FMC_LA19_N" , H23 on FMC
+#NET "BUSY_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+#NET "BUSY_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+## "FMC_LA19_P" , H22 on FMC
+#NET "busy_p_i[0]" LOC = N6;
+## "FMC_LA14_P" , C18 on FMC
+#NET "busy_p_i[1]" LOC = B2;
+## "FMC_LA12_P" , G15 on FMC
+#NET "busy_p_i[2]" LOC = D6;
+
+#NET "TRIGGERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+## "FMC_LA20_P" , G21 on FMC
+#NET "triggers_p_o[0]" LOC = N7;
+## "FMC_LA03_P" , G9 on FMC
+#NET "triggers_p_o[1]" LOC = C13;
+## "FMC_LA16_P" , G18 on FMC
+#NET "triggers_p_o[2]" LOC = C7;
+
+# Remove shutters ( also known as SPARE ) for now
+#NET "SPARE_N_O<1>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
+#NET "SPARE_N_O<2>" LOC = "A12"; ## "FMC_LA11_N" , H17 on FMC
+#NET "SPARE_P_O<1>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
+#NET "SPARE_P_O<2>" LOC = "B12"; ## "FMC_LA11_P" , H16 on FMC
+
+# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
+#NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
+#NET "DUT_CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
+#NET "DUT_CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+## "FMC_LA27_P" , C26 on FMC
+## "FMC_LA02_P" , H7 on FMC
+## "FMC_LA21_P" , H25 on FMC
+
+# Labelled CONT on schematic.
+#NET "RESET_OR_CLK_N_O<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
+#NET "RESET_OR_CLK_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "RESET_OR_CLK_N_O<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+## "FMC_LA22_P" , G24 on FMC
+#NET "reset_or_clk_p_o[0]" LOC = R7;
+## "FMC_LA18_CC_P" , C22 on FMC
+#NET "reset_or_clk_p_o[1]" LOC = R10;
+## "FMC_LA07_P" , H13 on FMC
+#NET "reset_or_clk_p_o[2]" LOC = E7;
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+## "FMC_LA32_N" , H38 on FMC
+NET "cfd_discr_n_i[0]" LOC = V15;
+## "FMC_LA30_N" , H35 on FMC
+NET "cfd_discr_n_i[1]" LOC = V12;
+## "FMC_LA28_N" , H32 on FMC
+NET "cfd_discr_n_i[2]" LOC = V11;
+## "FMC_LA24_N" , H29 on FMC
+NET "cfd_discr_n_i[3]" LOC = V8;
+## "FMC_LA32_P" , H37 on FMC
+NET "cfd_discr_p_i[0]" LOC = U15;
+## "FMC_LA30_P" , H34 on FMC
+NET "cfd_discr_p_i[1]" LOC = T12;
+## "FMC_LA28_P" , H31 on FMC
+NET "cfd_discr_p_i[2]" LOC = U11;
+## "FMC_LA24_P" , H28 on FMC
+NET "cfd_discr_p_i[3]" LOC = U8;
+
+# Threshold comparator outputs
+## "FMC_LA33_N" , G37 on FMC
+NET "threshold_discr_n_i[0]" LOC = N9;
+## "FMC_LA31_N" , G34 on FMC
+NET "threshold_discr_n_i[1]" LOC = V6;
+## "FMC_LA29_N" , G31 on FMC
+NET "threshold_discr_n_i[2]" LOC = N8;
+## "FMC_LA25_N" , G28 on FMC
+NET "threshold_discr_n_i[3]" LOC = N11;
+## "FMC_LA33_P" , G36 on FMC
+NET "threshold_discr_p_i[0]" LOC = M10;
+## "FMC_LA31_P" , G33 on FMC
+NET "threshold_discr_p_i[1]" LOC = T6;
+## "FMC_LA29_P" , G30 on FMC
+NET "threshold_discr_p_i[2]" LOC = M8;
+## "FMC_LA25_P" , G27 on FMC
+NET "threshold_discr_p_i[3]" LOC = M11;
+
+############
+# External clock pins
+## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "extclk_p_b" LOC = C10;
+## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+NET "extclk_n_b" LOC = A10;
+
+
+#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
+
+# GPIO pins for debugging.
+## 1 on J13 (thru series R100 200 ohm)
+#NET "gpio_hdr[0]" LOC = N17;
+## 3 on J13 (thru series R102 200 ohm)
+#NET "gpio_hdr[1]" LOC = M18;
+## 5 on J13 (thru series R101 200 ohm)
+#NET "gpio_hdr[2]" LOC = A3;
+## 7 on J13 (thru series R103 200 ohm)
+#NET "gpio_hdr[3]" LOC = L15;
+## 2 on J13 (thru series R99 200 ohm)
+#NET "gpio_hdr[4]" LOC = F15;
+## 4 on J13 (thru series R98 200 ohm)
+#NET "gpio_hdr[5]" LOC = B4;
+## 6 on J13 (thru series R97 200 ohm)
+#NET "gpio_hdr[6]" LOC = F13;
+## 8 on J13 (thru series R96 20
+#NET "gpio_hdr[7]" LOC = P12;
+
+
+#NET "busy_p_i[2]" PULLDOWN;
+#NET "busy_p_i[1]" PULLDOWN;
+#NET "busy_p_i[0]" PULLDOWN;
+
+# PlanAhead Generated miscellaneous constraints
+
+NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rst_ipb_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/we_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rarp_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/enable_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/req_send_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[2]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_write_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/pkt_done_read_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_up_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/busy_down_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/rx_read_buf_buf[0]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[1]" KEEP = "TRUE";
+NET "I4/ipbus/udp_if/clock_crossing_if/tx_write_buf_buf[0]" KEEP = "TRUE";
+
+# PlanAhead Generated physical constraints
+
+NET "output_0_p[0]" LOC = N7;
+NET "output_0_p[1]" LOC = C13;
+NET "output_0_p[2]" LOC = C7;
+NET "output_0_n[0]" LOC = P8;
+NET "output_0_n[1]" LOC = A13;
+NET "output_0_n[2]" LOC = A7;
+NET "output_1_p[0]" LOC = R11;
+NET "output_1_p[1]" LOC = C15;
+NET "output_1_p[2]" LOC = T4;
+NET "output_1_n[0]" LOC = T11;
+NET "output_1_n[1]" LOC = A15;
+NET "output_1_n[2]" LOC = V4;
+NET "output_2_p[0]" LOC = R7;
+NET "output_2_p[1]" LOC = R10;
+NET "output_2_p[2]" LOC = E7;
+NET "output_2_n[0]" LOC = T7;
+NET "output_2_n[1]" LOC = T10;
+NET "output_2_n[2]" LOC = E8;
+NET "output_3_p[0]" LOC = N6;
+NET "output_3_p[1]" LOC = B2;
+NET "output_3_p[2]" LOC = D6;
+NET "output_3_n[0]" LOC = P7;
+NET "output_3_n[1]" LOC = A2;
+NET "output_3_n[2]" LOC = C6;
diff --git a/firmware/minitlu/hdl/test/sp605_FMC_mTLU.ucf b/firmware/minitlu/hdl/test/sp605_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..66bb1db813ae7648f2743e5470e826095cf77eb8
--- /dev/null
+++ b/firmware/minitlu/hdl/test/sp605_FMC_mTLU.ucf
@@ -0,0 +1,164 @@
+NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+#NET Reset_i LOC=F3; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+
+NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=C18;
+NET dip_switch_i<1> LOC=Y6;
+NET dip_switch_i<2> LOC=W6;
+NET dip_switch_i<3> LOC=E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+
+
+# Main I2C bus
+#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
+#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
+NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
+NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
+
+#
+# I/O to devices under test
+
+#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
+
+#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
+#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
+#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger inputs
+# first constant-fraction-discrimiator comparator outputs
+NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
+NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
+NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
+NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
+NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
+NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
+NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
+#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
+#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
+# then threshold comparator outputs
+# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
+#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
+#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
+#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+
+#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
+
+
+NET "output_0_p[0]" LOC = H10;
+NET "output_0_p[1]" LOC = W17;
+NET "output_0_p[2]" LOC = F7;
+NET "output_0_n[0]" LOC = H11;
+NET "output_0_n[1]" LOC = Y18;
+NET "output_0_n[2]" LOC = F8;
+NET "output_1_p[0]" LOC = U16;
+NET "output_1_p[1]" LOC = V11;
+NET "output_1_p[2]" LOC = C19;
+NET "output_1_n[0]" LOC = V15;
+NET "output_1_n[1]" LOC = W11;
+NET "output_1_n[2]" LOC = A19;
+NET "output_2_p[0]" LOC = Y17;
+NET "output_2_p[1]" LOC = AA14;
+NET "output_2_p[2]" LOC = B20;
+NET "output_2_n[0]" LOC = AB17;
+NET "output_2_n[1]" LOC = AB14;
+NET "output_2_n[2]" LOC = A20;
+NET "output_3_p[0]" LOC = D4;
+NET "output_3_p[1]" LOC = AA16;
+NET "output_3_p[2]" LOC = B2;
+NET "output_3_n[0]" LOC = D5;
+NET "output_3_n[1]" LOC = AB16;
+NET "output_3_n[2]" LOC = A2;
\ No newline at end of file
diff --git a/firmware/minitlu/hdl/test/sp605_FMC_mTLU_v1a.ucf b/firmware/minitlu/hdl/test/sp605_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..994eafd1308f29d2872304e56ca066a2c6155b34
--- /dev/null
+++ b/firmware/minitlu/hdl/test/sp605_FMC_mTLU_v1a.ucf
@@ -0,0 +1,164 @@
+NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+#NET Reset_i LOC=F3; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+
+NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=C18;
+NET dip_switch_i<1> LOC=Y6;
+NET dip_switch_i<2> LOC=W6;
+NET dip_switch_i<3> LOC=E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+
+
+# Main I2C bus
+#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
+#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
+NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
+NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
+
+#
+# I/O to devices under test
+
+#NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
+#NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
+#NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
+#NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
+#NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
+#NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
+
+#NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
+#NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
+#NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
+
+#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
+#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
+#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
+
+#NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+#NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+#NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+#NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+#NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+#NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+#NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+##NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+#NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+##NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+#NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+##NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger inputs
+# first constant-fraction-discrimiator comparator outputs
+#NET "CFD_DISCR_P_I<0>" LOC = "W17"; ## "FMC_LA00_CC_P" , G6 on FMC
+#NET "CFD_DISCR_N_I<0>" LOC = "Y18"; ## "FMC_LA00_CC_N" , G7 on FMC
+#NET "CFD_DISCR_P_I<1>" LOC = "Y15"; ## "FMC_LA14_P" , C18 on FMC
+#NET "CFD_DISCR_N_I<1>" LOC = "AB15"; ## "FMC_LA14_N" , C19 on FMC
+#NET "CFD_DISCR_P_I<2>" LOC = "AA16"; ## "FMC_LA12_P" , C22 on FMC
+#NET "CFD_DISCR_N_I<2>" LOC = "AB16"; ## "FMC_LA12_N" , C23 on FMC
+#NET "CFD_DISCR_P_I<3>" LOC = "AA14"; ## "FMC_LA16_P" , C26 on FMC
+#NET "CFD_DISCR_N_I<3>" LOC = "AB14"; ## "FMC_LA16_N" , C27 on FMC
+##NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+##NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+##NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
+##NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
+# then threshold comparator outputs
+# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
+#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
+#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
+#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+
+#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
+
+
+NET "output_0_p[0]" LOC = R9;
+NET "output_0_p[1]" LOC = B18;
+NET "output_0_p[2]" LOC = C5;
+NET "output_0_n[0]" LOC = R8;
+NET "output_0_n[1]" LOC = A18;
+NET "output_0_n[2]" LOC = A5;
+NET "output_1_p[0]" LOC = AA10;
+NET "output_1_p[1]" LOC = G8;
+NET "output_1_p[2]" LOC = V11;
+NET "output_1_n[0]" LOC = AB10;
+NET "output_1_n[1]" LOC = F9;
+NET "output_1_n[2]" LOC = W11;
+NET "output_2_p[0]" LOC = V7;
+NET "output_2_p[1]" LOC = T12;
+NET "output_2_p[2]" LOC = B2;
+NET "output_2_n[0]" LOC = W8;
+NET "output_2_n[1]" LOC = U12;
+NET "output_2_n[2]" LOC = A2;
+NET "output_3_p[0]" LOC = R11;
+NET "output_3_p[1]" LOC = C17;
+NET "output_3_p[2]" LOC = H13;
+NET "output_3_n[0]" LOC = T11;
+NET "output_3_n[1]" LOC = A17;
+NET "output_3_n[2]" LOC = G13;
\ No newline at end of file
diff --git a/firmware/minitlu/hdl/test/top_extphy_struct.vhd b/firmware/minitlu/hdl/test/top_extphy_struct.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4e16507123e0d0f22833ef68c8859fdcc5de7d25
--- /dev/null
+++ b/firmware/minitlu/hdl/test/top_extphy_struct.vhd
@@ -0,0 +1,596 @@
+-- VHDL Entity work.top_extphy.symbol
+--
+-- Created:
+-- by - phdgc.users (fortis.phy.bris.ac.uk)
+-- at - 16:06:33 01/24/14
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY top_extphy IS
+ GENERIC(
+ g_NUM_DUTS : positive := 3;
+ g_NUM_TRIG_INPUTS : positive := 4;
+ g_NUM_EXT_SLAVES : positive := 10; --! Number of slaves outside IPBus interface
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_NUM_EDGE_INPUTS : positive := 4;
+ g_SPILL_COUNTER_WIDTH : positive := 12
+ );
+ PORT(
+ --busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ --busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ dut_clk_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ dut_clk_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
+ sysclk_p_i : IN std_logic;
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
+ leds_o : OUT std_logic_vector (3 DOWNTO 0);
+ phy_rstb_o : OUT std_logic;
+-- reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+-- reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+-- triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+-- triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
+ extclk_n_b : OUT std_logic;
+ extclk_p_b : OUT std_logic; --! either external clock in, or a clock being driven out
+ output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ i2c_scl_b : INOUT std_logic;
+ i2c_sda_b : INOUT std_logic
+ );
+
+-- Declarations
+
+END ENTITY top_extphy ;
+
+--=============================================================================
+--! @file top_extphy_struct.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL -- VHDL Architecture work.top_extphy.struct
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
+--
+--! @date 16:18:26 01/24/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+LIBRARY work;
+USE work.ipbus.all;
+USE work.emac_hostbus_decl.all;
+
+USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;
+
+
+ARCHITECTURE struct OF top_extphy IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
+ SIGNAL clk_16x_logic : std_logic; -- 640MHz clock
+ SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
+ SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
+ SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
+ SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ SIGNAL event_number_o : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
+ SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IPBus read signals
+ SIGNAL ipbus_clk : std_logic;
+ SIGNAL ipbus_reset : std_logic;
+ SIGNAL ipbus_rst : std_logic; -- ! IPBus reset to slaves
+ SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IBus write signals
+ SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
+ SIGNAL logic_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
+ SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
+ SIGNAL overall_veto : std_logic; --! Halts triggers when high
+ SIGNAL s_i2c_scl_enb : std_logic;
+ SIGNAL s_i2c_sda_enb : std_logic;
+ SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+ SIGNAL shutter_i : std_logic;
+ SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+ SIGNAL spill_i : std_logic;
+ SIGNAL strobe_16x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
+ SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
+ SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+ SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+ SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
+ SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
+
+
+ -- Component Declarations
+ COMPONENT DUTInterfaces
+ GENERIC (
+ g_NUM_DUTS : positive := 3;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT (
+ --busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ --busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ clk_4x_logic_i : IN std_logic ;
+ clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
+ trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
+ --shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+-- reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+-- reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+-- trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+-- trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ --shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ --shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ output_0_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_0_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_1_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_2_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_p : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ output_3_n : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ veto_o : OUT std_logic -- goes high when one or more DUT are busy
+ );
+ END COMPONENT DUTInterfaces;
+ COMPONENT IPBusInterface
+ GENERIC (
+ NUM_EXT_SLAVES : positive := 5
+ );
+ PORT (
+ gmii_rx_clk_i : IN std_logic ;
+ gmii_rx_dv_i : IN std_logic ;
+ gmii_rx_er_i : IN std_logic ;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
+ sysclk_n_i : IN std_logic ;
+ sysclk_p_i : IN std_logic ; -- ! 200 MHz xtal clock
+ clocks_locked_o : OUT std_logic ;
+ gmii_gtx_clk_o : OUT std_logic ;
+ gmii_tx_en_o : OUT std_logic ;
+ gmii_tx_er_o : OUT std_logic ;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ ipb_clk_o : OUT std_logic ; -- ! IPBus clock TO slaves
+ ipb_rst_o : OUT std_logic ; -- ! IPBus reset TO slaves
+ ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
+ onehz_o : OUT std_logic ;
+ phy_rstb_o : OUT std_logic ;
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ clk_logic_xtal_o : OUT std_logic
+ );
+ END COMPONENT IPBusInterface;
+ COMPONENT eventBuffer
+ GENERIC (
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_WRITE_COUNTER_WIDTH : positive := 13;
+ g_READ_COUNTER_WIDTH : positive := 14
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ;
+ data_strobe_i : IN std_logic ; -- Indicates data TO transfer
+ event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ;
+ ipbus_reset_i : IN std_logic ;
+ strobe_4x_logic_i : IN std_logic ;
+ trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not yet used.
+ buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full
+ ipbus_o : OUT ipb_rbus ;
+ logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
+ );
+ END COMPONENT eventBuffer;
+ COMPONENT eventFormatter
+ GENERIC (
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_COUNTER_TRIG_WIDTH : positive := 32;
+ g_COUNTER_WIDTH : positive := 12;
+ g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
+ --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+ g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
+ g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
+ ipbus_clk_i : IN std_logic ;
+ logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ logic_reset_i : IN std_logic ; -- goes high TO reset counters. Synchronous with clk_4x_logic
+ trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic
+ trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
+ trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
+ trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
+ shutter_i : IN std_logic ;
+ shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+ spill_i : IN std_logic ;
+ spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+ edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ ipbus_i : IN ipb_wbus ;
+ ipbus_o : OUT ipb_rbus ;
+ data_strobe_o : OUT std_logic ; -- goes high when data ready TO load into event buffer
+ event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ event_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
+ );
+ END COMPONENT eventFormatter;
+ COMPONENT i2c_master
+ PORT (
+ i2c_scl_i : IN std_logic ;
+ i2c_sda_i : IN std_logic ;
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ i2c_scl_enb_o : OUT std_logic ;
+ i2c_sda_enb_o : OUT std_logic ;
+ ipbus_o : OUT ipb_rbus -- signals from slave TO IPBus core
+ );
+ END COMPONENT i2c_master;
+ COMPONENT logic_clocks
+ PORT (
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ;
+ ipbus_reset_i : IN std_logic ;
+ Reset_i : IN std_logic ;
+ clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal
+ clk_16x_logic_o : OUT std_logic ; -- 640MHz clock
+ clk_4x_logic_o : OUT std_logic ; -- 160MHz clock
+ ipbus_o : OUT ipb_rbus ;
+ strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
+ strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
+ extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
+ extclk_n_b : OUT std_logic ;
+ clk_logic_o : OUT std_logic ;
+ logic_clocks_locked_o : OUT std_logic ;
+ logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
+ );
+ END COMPONENT logic_clocks;
+ COMPONENT triggerInputs
+ GENERIC (
+ g_NUM_INPUTS : natural := 1
+ );
+ PORT (
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
+ clk_4x_logic : IN std_logic ; -- ! Rising edge active
+ strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
+ trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
+ trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
+ trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
+ edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
+ edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
+ edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ ipbus_clk_i : IN std_logic ;
+ ipbus_reset_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+ clk_16x_logic_i : IN std_logic ; --! 640MHz clock ( 16x 40MHz )
+ strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
+ );
+ END COMPONENT triggerInputs;
+ COMPONENT triggerLogic
+ GENERIC (
+ g_NUM_INPUTS : positive := 4;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ logic_reset_i : IN std_logic ; -- active high. Synchronous with clk_4x_logic
+ logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input conector active
+ veto_i : IN std_logic ; -- ! Halts triggers when high
+ event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+ post_veto_trigger_o : OUT std_logic ; -- ! goes high when trigger passes
+ pre_veto_trigger_o : OUT std_logic ;
+ trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
+ );
+ END COMPONENT triggerLogic;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+ FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+ FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+ FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+ FOR ALL : i2c_master USE ENTITY work.i2c_master;
+ FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+ FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
+ FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 i2c_tristate
+ -- eb1 1
+ i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+ i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+
+
+
+ -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+ logic_clocks_reset <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I10' of 'gnd'
+ --trigger_cnt_i <= (OTHERS => '0');
+ trigger_cnt_i <= event_number_o;
+
+ -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+ spill_i <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+ spill_cnt_i <= (OTHERS => '0');
+
+ -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+ shutter_i <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+ shutter_cnt_i <= (OTHERS => '0');
+
+ -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+ overall_veto <= buffer_full_o OR veto_o;
+
+ -- Instance port mappings.
+ I0 : DUTInterfaces
+ GENERIC MAP (
+ g_NUM_DUTS => g_NUM_DUTS,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH
+ )
+ PORT MAP (
+ --busy_from_dut_n_i => (others=>'0'), --busy_n_i,
+ --busy_from_dut_p_i => (others=>'0'), --busy_p_i,
+ clk_4x_logic_i => clk_4x_logic,
+ clk_from_dut_n_i => dut_clk_n_i,
+ clk_from_dut_p_i => dut_clk_p_i,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(0),
+ ipbus_reset_i => ipbus_reset,
+ strobe_4x_logic_i => strobe_4x_logic,
+ trigger_counter_i => trigger_count,
+ trigger_i => overall_trigger,
+ ipbus_o => ipbr(0),
+-- reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+-- reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+-- trigger_to_dut_n_o => triggers_n_o,
+-- trigger_to_dut_p_o => triggers_p_o,
+ output_0_p => output_0_p,
+ output_0_n => output_0_n,
+ output_1_p => output_1_p,
+ output_1_n => output_1_n,
+ output_2_p => output_2_p,
+ output_2_n => output_2_n,
+ output_3_p => output_3_p,
+ output_3_n => output_3_n,
+ veto_o => veto_o
+ );
+ I4 : IPBusInterface
+ GENERIC MAP (
+ NUM_EXT_SLAVES => g_NUM_EXT_SLAVES
+ )
+ PORT MAP (
+ gmii_rx_clk_i => gmii_rx_clk_i,
+ gmii_rx_dv_i => gmii_rx_dv_i,
+ gmii_rx_er_i => gmii_rx_er_i,
+ gmii_rxd_i => gmii_rxd_i,
+ ipbr_i => ipbr,
+ sysclk_n_i => sysclk_n_i,
+ sysclk_p_i => sysclk_p_i,
+ clocks_locked_o => leds_o(2),
+ gmii_gtx_clk_o => gmii_gtx_clk_o,
+ gmii_tx_en_o => gmii_tx_en_o,
+ gmii_tx_er_o => gmii_tx_er_o,
+ gmii_txd_o => gmii_txd_o,
+ ipb_clk_o => ipbus_clk,
+ ipb_rst_o => ipbus_rst,
+ ipbw_o => ipbw,
+ onehz_o => leds_o(3),
+ phy_rstb_o => phy_rstb_o,
+ dip_switch_i => dip_switch_i,
+ clk_logic_xtal_o => clk_logic_xtal
+ );
+ I5 : eventBuffer
+ GENERIC MAP (
+ g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH,
+ g_WRITE_COUNTER_WIDTH => 13,
+ g_READ_COUNTER_WIDTH => 14
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ data_strobe_i => data_strobe,
+ event_data_i => event_data,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(3),
+ ipbus_reset_i => ipbus_reset,
+ strobe_4x_logic_i => strobe_4x_logic,
+ trigger_count_i => trigger_count,
+ buffer_full_o => buffer_full_o,
+ ipbus_o => ipbr(3),
+ logic_reset_i => logic_reset
+ );
+ I2 : eventFormatter
+ GENERIC MAP (
+ g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH,
+ g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+ g_COUNTER_WIDTH => 12,
+ g_EVTTYPE_WIDTH => 4, -- Width of the event type word
+ --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+ g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, -- Number of edge inputs
+ g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS -- Number of trigger inputs
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ ipbus_clk_i => ipbus_clk,
+ logic_strobe_i => strobe_4x_logic,
+ logic_reset_i => logic_reset,
+ trigger_i => overall_trigger,
+ trigger_times_i => trigger_times,
+ trigger_inputs_fired_i => triggers,
+ trigger_cnt_i => trigger_cnt_i,
+ shutter_i => shutter_i,
+ shutter_cnt_i => shutter_cnt_i,
+ spill_i => spill_i,
+ spill_cnt_i => spill_cnt_i,
+ edge_rise_i => edge_rise_i,
+ edge_fall_i => edge_fall_i,
+ edge_rise_time_i => edge_rise_time_i,
+ edge_fall_time_i => edge_fall_time_i,
+ ipbus_i => ipbw(9),
+ ipbus_o => ipbr(9),
+ data_strobe_o => data_strobe,
+ event_data_o => event_data,
+ event_number_i => event_number_o,
+ trigger_count_o => trigger_count
+ );
+ I7 : i2c_master
+ PORT MAP (
+ i2c_scl_i => i2c_scl_b,
+ i2c_sda_i => i2c_sda_b,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(5),
+ ipbus_reset_i => ipbus_reset,
+ i2c_scl_enb_o => s_i2c_scl_enb,
+ i2c_sda_enb_o => s_i2c_sda_enb,
+ ipbus_o => ipbr(5)
+ );
+ I6 : logic_clocks
+ PORT MAP (
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(4),
+ ipbus_reset_i => ipbus_reset,
+ Reset_i => logic_clocks_reset,
+ clk_logic_xtal_i => clk_logic_xtal,
+ clk_16x_logic_o => clk_16x_logic,
+ clk_4x_logic_o => clk_4x_logic,
+ ipbus_o => ipbr(4),
+ strobe_16x_logic_o => strobe_16x_logic,
+ strobe_4x_logic_o => strobe_4x_logic,
+ extclk_p_b => extclk_p_b,
+ extclk_n_b => extclk_n_b,
+ clk_logic_o => OPEN,
+ logic_clocks_locked_o => leds_o(1),
+ logic_reset_o => logic_reset
+ );
+ I1 : triggerInputs
+ GENERIC MAP (
+ g_NUM_INPUTS => g_NUM_TRIG_INPUTS
+ )
+ PORT MAP (
+ cfd_discr_p_i => cfd_discr_p_i,
+ cfd_discr_n_i => cfd_discr_n_i,
+ clk_4x_logic => clk_4x_logic,
+ strobe_4x_logic_i => strobe_4x_logic,
+ threshold_discr_p_i => threshold_discr_p_i,
+ threshold_discr_n_i => threshold_discr_n_i,
+ trigger_times_o => trigger_times,
+ trigger_o => triggers,
+ trigger_debug_o => OPEN, --gpio_hdr,
+ edge_rising_times_o => OPEN,
+ edge_falling_times_o => OPEN,
+ edge_rising_o => OPEN,
+ edge_falling_o => OPEN,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_reset_i => ipbus_reset,
+ ipbus_i => ipbw(1),
+ ipbus_o => ipbr(1),
+ clk_16x_logic_i => clk_16x_logic,
+ strobe_16x_logic_i => strobe_16x_logic
+ );
+ I3 : triggerLogic
+ GENERIC MAP (
+ g_NUM_INPUTS => g_NUM_TRIG_INPUTS,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(2),
+ ipbus_reset_i => ipbus_reset,
+ logic_reset_i => logic_reset,
+ logic_strobe_i => strobe_4x_logic,
+ trigger_i => triggers,
+ veto_i => overall_veto,
+ event_number_o => event_number_o,
+ ipbus_o => ipbr(2),
+ post_veto_trigger_o => overall_trigger,
+ pre_veto_trigger_o => OPEN,
+ trigger_active_o => leds_o(0)
+ );
+
+ gpio_hdr(0) <= overall_trigger;
+ --gpio_hdr(1) <= clk_4x_logic;
+
+END ARCHITECTURE struct;
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU.hdp b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU.hdp
new file mode 100644
index 0000000000000000000000000000000000000000..e15dc481e7520ea2ffadb529b620ea575fef462f
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU.hdp
@@ -0,0 +1,40 @@
+[DesignChecker]
+work = $HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck
+[ModelSim]
+work = $HDS_PROJECT_DIR/fmc_mTLU_lib/work
+[QuestaSim]
+simprim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/simprim
+unisim = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/unisim
+xilinxcorelib = /software/CAD/Xilinx/14.3_64b/14.3/ISE_DS/ISE/vhdl/questasim/10.0d/lin64/xilinxcorelib
+[XilinxISE]
+work = $HDS_PROJECT_DIR/fmc_mTLU_lib/ise
+[hdl]
+exemplar = $HDS_HOME/examples/exemplar/hdl
+hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hdl
+renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hdl
+work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hdl
+[hds]
+exemplar = $HDS_HOME/examples/exemplar/hds
+hds_package_library = $HDS_HOME/hdl_libs/hds_package_library/hds
+renoir_package_library = $HDS_HOME/hdl_libs/renoir_package_library/hds
+work = $HDS_PROJECT_DIR/fmc_mTLU_lib/hds
+[hds_settings]
+default_library = work
+design_root = work.top_extphy(struct)top_extphy/struct.bd
+project_description = Firmware for AIDA Mini-TLU in FMC format
+version = 2
+[library_files_inclusion]
+simprim = all
+unisim = all
+work = specify
+xilinxcorelib = all
+[library_type]
+exemplar = regular
+hds_package_library = regular
+renoir_package_library = regular
+simprim = downstream_only
+unisim = downstream_only
+work = regular
+xilinxcorelib = downstream_only
+[shared]
+others = $HDS_TEAM_HOME/shared.hdp
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/DUTInterfaces_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/DUTInterfaces_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..41f02543c4c5f587e6b0cfca48b6785ba1702c42
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/DUTInterfaces_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..8a1c89d1e920d455f6f05c7381345fea4145c063
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/IPBusInterface_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arp.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arp.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..66d130d9f9597317009bc7c03320c624d0e070df
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arp.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/arp.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arrivalTimeLUT_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arrivalTimeLUT_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..d10a01da0d7a8c42d97d05a38e2b955e7d04e78c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/arrivalTimeLUT_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/bus_arb.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/bus_arb.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..2bc82b82f0edb1d84f7e2eb4065511e3cd95739a
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/bus_arb.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/bus_arb.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..4de80e65854d3dfd215bfac8dc4cd42f3949a329
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/dualSERDES_1to4_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/emac_hostbus_decl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/emac_hostbus_decl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..7c72d66db18fd5e5336ea9f9442fae1f033a3004
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/emac_hostbus_decl.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/emac_hostbus_decl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_1000basex.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_1000basex.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..1866fa7e2bbea3af0255701cc09804b3e77061cd
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_1000basex.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_1000basex.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_gmii.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_gmii.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..c4e9337d5fbe6b38c81ae2545990465a7b5094a5
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eth_s6_gmii.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/eth_s6_gmii.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..c24650aeeb3b8670bb9c00d48ab9bc3af1b87568
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventBuffer_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..b81a1a5e72e8df9bb5acc9010d40697304492d26
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/eventFormatter_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6c3004bd72093dbad7697ba77e8d69deeb4af4fe
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
@@ -0,0 +1,27 @@
+--=============================================================================
+--! @file fmcTLU_pkg.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Header fmc_mTLU_lib.fmcTLU
+--
+--! @author phdgc
+--! @date 16:44:31 11/08/12
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+PACKAGE fmcTLU IS
+
+ constant c_NUM_TIME_BITS : natural := 5;
+ constant c_NUM_TRIG_INPUTS : natural := 4;
+ constant c_EVENT_DATA_WIDTH : natural := 32;
+ constant c_DATA_WIDTH : natural := 32;
+
+ --subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
+ --type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
+ type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+ type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
+
+END fmcTLU;
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9437776d393daa1b6e790f3d5470fb09344259bc
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
@@ -0,0 +1,13 @@
+--=============================================================================
+--! @file fmcTLU_pkg_body.vhd
+--=============================================================================
+---
+--! @brief VHDL Package Body fmc_mTLU_lib.fmcTLU
+--
+--! @author phdgc
+--! @date 16:45:08 11/08/12
+--
+-- using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+PACKAGE BODY fmcTLU IS
+END fmcTLU;
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_rxpacketbuffer.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_rxpacketbuffer.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..acd0a003837b272fa78f1400c1af100374a85e8e
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_rxpacketbuffer.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_rxpacketbuffer.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_txpacketbuffer.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_txpacketbuffer.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..6af9187daebc9ba8bcdf262e936c24524607556d
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/gbe_txpacketbuffer.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/gbe_txpacketbuffer.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/i2c_master_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/i2c_master_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..1097e9a58233bd340ab393db8ea3bc9be83b80c8
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/i2c_master_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/icmp.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/icmp.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..117c5cc0a398f715fd1b1c0a3aadbac1384fe79e
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/icmp.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/icmp.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ip_checksum_8bit.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ip_checksum_8bit.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..1e040858eb1dd224784dda7eafc6080949c8523b
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ip_checksum_8bit.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ip_checksum_8bit.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_bus_decl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_bus_decl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..47b239076fb25d1894ea34e2e5fe76ad5cc4bab5
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_bus_decl.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_bus_decl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..0162697c93635fd6b5e074c7db59c13adfb88555
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_decl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_decl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..90d178e6e582e4eb93d43dc7bb1c2661308a3004
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_decl.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl_decl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_udponly.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_udponly.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..6630c192a189c91d27f7d7bd6d1099eb7760ba1b
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_ctrl_udponly.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_ctrl_udponly.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_fabric.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_fabric.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..5a5dfbadb997af4a958bb788da372dfaadad5696
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_fabric.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_fabric.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_package.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_package.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..12d51cef2cb2b95b03913008a2961e0938c50619
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_package.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_package.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_v_defs.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_v_defs.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..313e15b7c21416b8880d7d627b80166907e5a100
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/ipbus_v_defs.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_v_defs.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/logic_clocks_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/logic_clocks_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..731503555632909619b2d1fb7b57b365e8ec1636
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/logic_clocks_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..ba591c1c63bc01416f8f5690e32951a8aa76d8db
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/mac_arbiter.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter_decl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter_decl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..a779a30aabe8865be1905c0c14f81d08abe5623b
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/mac_arbiter_decl.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ethernet/hdl/mac_arbiter_decl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/packet_handler.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/packet_handler.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..4f99b77c80c9997f636ce1876e74d0e89cb869d4
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/packet_handler.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/packet_handler.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetbuffer.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetbuffer.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..6adccd4ab705ef2b1cfca9bae807f8dfee30ffcf
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetbuffer.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetbuffer.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetreq.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetreq.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..8ca55eb0f1d76c9c318fbd0ecc5daab9ff7f9b03
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetreq.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetreq.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetresp.v.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetresp.v.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..42dbcaa26fdbdbb3e1cfb937035826047d7021e4
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/sub_packetresp.v.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/sub_packetresp.v
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..24805110070a64bee4f90b99a84399adc1a818c2
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd
@@ -0,0 +1,80 @@
+--=============================================================================
+--! @file top_extphy_rtl.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL Architecture fmc_mTLU_lib.top_extphy.rtl
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--
+--! @date 15:11:55 11/09/12
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY top_extphy IS
+ GENERIC(
+ NUM_DUTS : positive := 3;
+ NUM_TRIG_INPUTS : positive := 4
+ );
+ PORT(
+ busy_i : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
+ cfd_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
+ dut_clk : IN std_logic_vector (NUM_DUTS-1 DOWNTO 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ sysclk_n_i : IN std_logic;
+ sysclk_p_i : IN std_logic; -- ! 200 MHz xtal clock
+ threshold_discr_i : IN std_logic_vector (NUM_TRIG_INPUTS-1 DOWNTO 0);
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ i2c_scl_o : OUT std_logic;
+ leds_o : OUT std_logic_vector (3 DOWNTO 0);
+ phy_rstb_o : OUT std_logic;
+ reset_or_clk_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
+ triggers_o : OUT std_logic_vector (NUM_DUTS-1 DOWNTO 0);
+ i2c_sda_d : INOUT std_logic
+ );
+
+-- Declarations
+
+END ENTITY top_extphy ;
+
+--
+ARCHITECTURE rtl OF top_extphy IS
+BEGIN
+END ARCHITECTURE rtl;
+
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a9386458f7c57de30c092a6780877ad190bacdbe
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
@@ -0,0 +1,631 @@
+-- VHDL Entity work.top_extphy.symbol
+--
+-- Created:
+-- by - phdgc.users (fortis.phy.bris.ac.uk)
+-- at - 16:06:33 01/24/14
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY top_extphy IS
+ GENERIC(
+ g_NUM_DUTS : positive := 3;
+ g_NUM_TRIG_INPUTS : positive := 4;
+ g_NUM_EXT_SLAVES : positive := 11; --! Number of slaves outside IPBus interface
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_NUM_EDGE_INPUTS : positive := 4;
+ g_SPILL_COUNTER_WIDTH : positive := 12
+ );
+ PORT(
+ busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Busy lines from DUTs ( active high )
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ sysclk_n_i : IN std_logic; --! 200 MHz xtal clock
+ sysclk_p_i : IN std_logic;
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ reset_i : IN std_logic;
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ gpio_hdr : OUT std_logic_vector (7 DOWNTO 0);
+ leds_o : OUT std_logic_vector (3 DOWNTO 0);
+ phy_rstb_o : OUT std_logic;
+ dut_clk_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ dut_clk_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
+ triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
+ extclk_n_b : INOUT std_logic;
+ extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
+ i2c_scl_b : INOUT std_logic;
+ i2c_sda_b : INOUT std_logic
+ );
+
+-- Declarations
+
+END ENTITY top_extphy ;
+
+--=============================================================================
+--! @file top_extphy_struct.vhd
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+-- VHDL -- VHDL Architecture work.top_extphy.struct
+--
+--! @brief \n
+--! \n
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk ( phdgc.users (fortis.phy.bris.ac.uk))
+--
+--! @date 16:18:26 01/24/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by:</b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo <next thing to do> \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+--
+--
+-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+LIBRARY work;
+USE work.ipbus.all;
+USE work.emac_hostbus_decl.all;
+
+USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;
+
+
+ARCHITECTURE struct OF top_extphy IS
+
+ -- Architecture declarations
+
+ -- Internal signal declarations
+ SIGNAL buffer_full_o : std_logic; --! Goes high when event buffer almost full
+ SIGNAL clk_16x_logic : std_logic; -- 640MHz clock
+ SIGNAL clk_4x_logic : std_logic; --! normally 160MHz
+ SIGNAL clk_logic_xtal : std_logic; -- ! 40MHz clock from onboard xtal
+ SIGNAL s_DUT_clk : std_logic; -- ! Clock to DUT
+ SIGNAL data_strobe : std_logic; -- goes high when data ready to load into event buffer
+ SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ SIGNAL event_number_o : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
+ SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IPBus read signals
+ SIGNAL ipbus_clk : std_logic;
+ SIGNAL ipbus_reset : std_logic;
+ SIGNAL ipbus_rst : std_logic; -- ! IPBus reset to slaves
+ SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0); --! IBus write signals
+ SIGNAL logic_clocks_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
+ SIGNAL logic_reset : std_logic; -- Goes high to reset counters etc. Sync with clk_4x_logic
+ SIGNAL overall_trigger : std_logic; --! goes high to load trigger data
+ SIGNAL overall_veto : std_logic; --! Halts triggers when high
+ SIGNAL postVeto_trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
+ SIGNAL s_rst_buffer : std_logic;
+ SIGNAL s_AIDAhandshake : std_logic;
+ SIGNAL s_i2c_scl_enb : std_logic;
+ SIGNAL s_i2c_sda_enb : std_logic;
+ SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+ SIGNAL shutter_i : std_logic;
+ SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0);
+ SIGNAL spill_i : std_logic;
+ SIGNAL strobe_16x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
+ SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
+ SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+ SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
+ SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
+ SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ SIGNAL postVeto_triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
+ SIGNAL s_Trig_TO_DUT : std_logic;
+ SIGNAL s_rst_or_clk_to_dut: std_logic;
+
+ -- Component Declarations
+ COMPONENT DUTInterfaces
+ GENERIC (
+ g_NUM_DUTS : positive := 3;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT (
+ busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- BUSY input from DUTs
+ clk_4x_logic_i : IN std_logic ;
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
+ --trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
+ clk_to_dut_i : IN std_logic ; -- ! clock to DUT
+ reset_or_clk_to_dut_i : IN std_logic ; -- ! Either reset line or trigger
+ AIDAhandshake_i : IN std_logic ; -- AIDA/EUDET
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+ clk_to_dut_n_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ clk_to_dut_p_o : INOUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- clocks trigger data when in EUDET mode
+ reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Either reset line or trigger
+ trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Trigger output
+ veto_o : OUT std_logic -- goes high when one or more DUT are busy
+ );
+ END COMPONENT DUTInterfaces;
+ COMPONENT IPBusInterface
+ GENERIC (
+ NUM_EXT_SLAVES : positive := 5
+ );
+ PORT (
+ gmii_rx_clk_i : IN std_logic ;
+ gmii_rx_dv_i : IN std_logic ;
+ gmii_rx_er_i : IN std_logic ;
+ gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
+ ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IPBus read signals
+ sysclk_n_i : IN std_logic ;
+ sysclk_p_i : IN std_logic ; -- ! 200 MHz xtal clock
+ clocks_locked_o : OUT std_logic ;
+ gmii_gtx_clk_o : OUT std_logic ;
+ gmii_tx_en_o : OUT std_logic ;
+ gmii_tx_er_o : OUT std_logic ;
+ gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
+ ipb_clk_o : OUT std_logic ; -- ! IPBus clock TO slaves
+ ipb_rst_o : OUT std_logic ; -- ! IPBus reset TO slaves
+ ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); -- ! IBus write signals
+ onehz_o : OUT std_logic ;
+ phy_rstb_o : OUT std_logic ;
+ dip_switch_i : IN std_logic_vector (3 DOWNTO 0);
+ clk_logic_xtal_o : OUT std_logic
+ );
+ END COMPONENT IPBusInterface;
+ COMPONENT eventBuffer
+ GENERIC (
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_WRITE_COUNTER_WIDTH : positive := 15;
+ g_READ_COUNTER_WIDTH : positive := 16
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ;
+ data_strobe_i : IN std_logic ; -- Indicates data TO transfer
+ event_data_i : IN std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ;
+ ipbus_reset_i : IN std_logic ;
+ strobe_4x_logic_i : IN std_logic ;
+ --trigger_count_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); --! Not used yet.
+ rst_fifo_o : OUT std_logic; --! rst signal to first level fifos
+ buffer_full_o : OUT std_logic ; --! Goes high when event buffer almost full
+ ipbus_o : OUT ipb_rbus ;
+ logic_reset_i : IN std_logic -- reset buffers when high. Synch withclk_4x_logic
+ );
+ END COMPONENT eventBuffer;
+ COMPONENT eventFormatter
+ GENERIC (
+ g_EVENT_DATA_WIDTH : positive := 64;
+ g_IPBUS_WIDTH : positive := 32;
+ g_COUNTER_TRIG_WIDTH : positive := 32;
+ g_COUNTER_WIDTH : positive := 12;
+ g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
+ --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+ g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
+ g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
+ ipbus_clk_i : IN std_logic ;
+ logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ logic_reset_i : IN std_logic ; -- goes high TO reset counters. Synchronous with clk_4x_logic
+ rst_fifo_i : IN std_logic; --! Reset fifos
+ buffer_full_i : IN std_logic; -- Buffer full signal from main buffer
+ trigger_i : IN std_logic ; --! goes high TO load trigger data. One cycle of clk_4x_logic
+ trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
+ trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
+ trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
+ shutter_i : IN std_logic ;
+ shutter_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+ spill_i : IN std_logic ;
+ spill_cnt_i : IN std_logic_vector (g_COUNTER_WIDTH-1 DOWNTO 0);
+ edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
+ ipbus_i : IN ipb_wbus ;
+ ipbus_o : OUT ipb_rbus ;
+ data_strobe_o : OUT std_logic ; -- goes high when data ready TO load into event buffer
+ event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0);
+ event_number_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0);
+ trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
+ );
+ END COMPONENT eventFormatter;
+ COMPONENT i2c_master
+ PORT (
+ i2c_scl_i : IN std_logic ;
+ i2c_sda_i : IN std_logic ;
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ i2c_scl_enb_o : OUT std_logic ;
+ i2c_sda_enb_o : OUT std_logic ;
+ ipbus_o : OUT ipb_rbus -- signals from slave TO IPBus core
+ );
+ END COMPONENT i2c_master;
+ COMPONENT logic_clocks
+ PORT (
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ;
+ ipbus_reset_i : IN std_logic ;
+ Reset_i : IN std_logic ;
+ clk_logic_xtal_i : IN std_logic ; -- ! 40MHz clock from onboard xtal
+ clk_16x_logic_o : OUT std_logic ; -- 640MHz clock
+ clk_4x_logic_o : OUT std_logic ; -- 160MHz clock
+ ipbus_o : OUT ipb_rbus ;
+ strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
+ strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
+ extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
+ extclk_n_b : INOUT std_logic ;
+ DUT_clk_o : OUT std_logic ;
+ logic_clocks_locked_o : OUT std_logic ;
+ logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
+ );
+ END COMPONENT logic_clocks;
+ COMPONENT triggerInputs
+ GENERIC (
+ g_NUM_INPUTS : natural := 1
+ );
+ PORT (
+ cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
+ cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
+ clk_4x_logic : IN std_logic ; -- ! Rising edge active
+ strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
+ threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! inputs from threshold comparators
+ reset_i : IN std_logic;
+ trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
+ trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger active
+ trigger_debug_o : OUT std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0); -- ! Copy of input trigger level. High bits CFD, Low threshold
+ edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
+ edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); -- ! edge arrival time ( w.r.t. logic_strobe)
+ edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when rising edge
+ edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when falling edge
+ ipbus_clk_i : IN std_logic ;
+ ipbus_reset_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+ clk_16x_logic_i : IN std_logic ; --! 640MHz clock ( 16x 40MHz )
+ strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
+ );
+ END COMPONENT triggerInputs;
+ COMPONENT triggerLogic
+ GENERIC (
+ g_NUM_INPUTS : positive := 4;
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT (
+ clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
+ ipbus_clk_i : IN std_logic ;
+ ipbus_i : IN ipb_wbus ; -- Signals from IPBus core TO slave
+ ipbus_reset_i : IN std_logic ;
+ logic_reset_i : IN std_logic ; -- active high. Synchronous with clk_4x_logic
+ logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+ trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active
+ trigger_times_i : IN t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+ veto_i : IN std_logic ; -- ! Halts triggers when high
+ trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); -- ! High when trigger from input connector active and input enabled
+ trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0); --! trigger arrival time
+ event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0); -- starts at one. Increments for each post_veto_trigger
+ ipbus_o : OUT ipb_rbus ; -- signals from slave TO IPBus core
+ post_veto_trigger_o : OUT std_logic ; -- ! goes high when trigger passes
+ pre_veto_trigger_o : OUT std_logic ;
+ trigger_active_o : OUT std_logic --! Goes high when triggers are active ( ie. not veoted)
+ );
+ END COMPONENT triggerLogic;
+ COMPONENT handshakes
+ GENERIC(
+ g_IPBUS_WIDTH : positive := 32
+ );
+ PORT(
+ clk_i : IN std_logic;
+ Trigger_i : IN std_logic;
+ ipbus_clk_i : IN std_logic;
+ ipbus_i : IN ipb_wbus;
+ ipbus_reset_i : IN std_logic;
+ ipbus_o : OUT ipb_rbus;
+ logic_reset_i : IN std_logic; -- reset buffers when high. Synch withclk_4x_logic
+ Busy_i : IN std_logic;
+ AIDAhandshake_o : OUT std_logic; -- running an AIDA handshake or the old EUDET handshake
+ Trigger_o : OUT std_logic;
+ rst_or_clk_o : OUT std_logic
+ );
+ END COMPONENT handshakes;
+
+ -- Optional embedded configurations
+ -- pragma synthesis_off
+ FOR ALL : DUTInterfaces USE ENTITY work.DUTInterfaces;
+ FOR ALL : IPBusInterface USE ENTITY work.IPBusInterface;
+ FOR ALL : eventBuffer USE ENTITY work.eventBuffer;
+ FOR ALL : eventFormatter USE ENTITY work.eventFormatter;
+ FOR ALL : i2c_master USE ENTITY work.i2c_master;
+ FOR ALL : logic_clocks USE ENTITY work.logic_clocks;
+ FOR ALL : triggerInputs USE ENTITY work.triggerInputs;
+ FOR ALL : triggerLogic USE ENTITY work.triggerLogic;
+ FOR ALL : handshakes USE ENTITY work.handshakes;
+ -- pragma synthesis_on
+
+
+BEGIN
+ -- Architecture concurrent statements
+ -- HDL Embedded Text Block 1 i2c_tristate
+ -- eb1 1
+ i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+ i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+
+
+
+ -- ModuleWare code(v1.12) for instance 'I9' of 'gnd'
+ logic_clocks_reset <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I10' of 'gnd'
+ --trigger_cnt_i <= (OTHERS => '0');
+ trigger_cnt_i <= event_number_o;
+
+ -- ModuleWare code(v1.12) for instance 'I11' of 'gnd'
+ spill_i <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I12' of 'gnd'
+ spill_cnt_i <= (OTHERS => '0');
+
+ -- ModuleWare code(v1.12) for instance 'I13' of 'gnd'
+ shutter_i <= '0';
+
+ -- ModuleWare code(v1.12) for instance 'I14' of 'gnd'
+ shutter_cnt_i <= (OTHERS => '0');
+
+ -- ModuleWare code(v1.12) for instance 'I8' of 'sor'
+ overall_veto <= buffer_full_o; -- OR veto_o;
+
+ -- Instance port mappings.
+ I0 : DUTInterfaces
+ GENERIC MAP (
+ g_NUM_DUTS => g_NUM_DUTS,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH
+ )
+ PORT MAP (
+ busy_from_dut_n_i => busy_n_i,
+ busy_from_dut_p_i => busy_p_i,
+ clk_4x_logic_i => clk_4x_logic,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(0),
+ ipbus_reset_i => ipbus_reset,
+ strobe_4x_logic_i => strobe_4x_logic,
+ --trigger_counter_i => trigger_count,
+ clk_to_dut_i => s_DUT_clk,
+ trigger_i => s_Trig_TO_DUT, --overall_trigger,
+ reset_or_clk_to_dut_i => s_rst_or_clk_to_dut,
+ AIDAhandshake_i => s_AIDAhandshake, -- RJ45 DUT clock as output/input (1/0)
+ ipbus_o => ipbr(0),
+ clk_to_dut_n_o => dut_clk_n_o,
+ clk_to_dut_p_o => dut_clk_p_o,
+ reset_or_clk_to_dut_n_o => reset_or_clk_n_o,
+ reset_or_clk_to_dut_p_o => reset_or_clk_p_o,
+ trigger_to_dut_n_o => triggers_n_o,
+ trigger_to_dut_p_o => triggers_p_o,
+ veto_o => veto_o
+ );
+ I4 : IPBusInterface
+ GENERIC MAP (
+ NUM_EXT_SLAVES => g_NUM_EXT_SLAVES
+ )
+ PORT MAP (
+ gmii_rx_clk_i => gmii_rx_clk_i,
+ gmii_rx_dv_i => gmii_rx_dv_i,
+ gmii_rx_er_i => gmii_rx_er_i,
+ gmii_rxd_i => gmii_rxd_i,
+ ipbr_i => ipbr,
+ sysclk_n_i => sysclk_n_i,
+ sysclk_p_i => sysclk_p_i,
+ clocks_locked_o => leds_o(2),
+ gmii_gtx_clk_o => gmii_gtx_clk_o,
+ gmii_tx_en_o => gmii_tx_en_o,
+ gmii_tx_er_o => gmii_tx_er_o,
+ gmii_txd_o => gmii_txd_o,
+ ipb_clk_o => ipbus_clk,
+ ipb_rst_o => ipbus_rst,
+ ipbw_o => ipbw,
+ onehz_o => leds_o(3),
+ phy_rstb_o => phy_rstb_o,
+ dip_switch_i => dip_switch_i,
+ clk_logic_xtal_o => clk_logic_xtal
+ );
+ I5 : eventBuffer
+ GENERIC MAP (
+ g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH,
+ g_WRITE_COUNTER_WIDTH => 15,
+ g_READ_COUNTER_WIDTH => 16
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ data_strobe_i => data_strobe,
+ event_data_i => event_data,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(3),
+ ipbus_reset_i => ipbus_reset,
+ strobe_4x_logic_i => strobe_4x_logic,
+ --trigger_count_i => trigger_count,
+ rst_fifo_o => s_rst_buffer,
+ buffer_full_o => buffer_full_o,
+ ipbus_o => ipbr(3),
+ logic_reset_i => logic_reset or reset_i
+ );
+ I2 : eventFormatter
+ GENERIC MAP (
+ g_EVENT_DATA_WIDTH => g_EVENT_DATA_WIDTH,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH,
+ g_COUNTER_TRIG_WIDTH => g_IPBUS_WIDTH,
+ g_COUNTER_WIDTH => 12,
+ g_EVTTYPE_WIDTH => 4, -- Width of the event type word
+ --g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+ g_NUM_EDGE_INPUTS => g_NUM_EDGE_INPUTS, -- Number of edge inputs
+ g_NUM_TRIG_INPUTS => g_NUM_TRIG_INPUTS -- Number of trigger inputs
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ ipbus_clk_i => ipbus_clk,
+ logic_strobe_i => strobe_4x_logic,
+ logic_reset_i => logic_reset or reset_i,
+ rst_fifo_i => s_rst_buffer,
+ buffer_full_i => buffer_full_o,
+ trigger_i => overall_trigger,
+ trigger_times_i => postVeto_trigger_times,
+ trigger_inputs_fired_i => postVeto_triggers,
+ -- trigger_cnt_i => trigger_cnt_i,
+ trigger_cnt_i => event_number_o,
+ shutter_i => shutter_i,
+ shutter_cnt_i => shutter_cnt_i,
+ spill_i => spill_i,
+ spill_cnt_i => spill_cnt_i,
+ edge_rise_i => edge_rise_i,
+ edge_fall_i => edge_fall_i,
+ edge_rise_time_i => edge_rise_time_i,
+ edge_fall_time_i => edge_fall_time_i,
+ ipbus_i => ipbw(9),
+ ipbus_o => ipbr(9),
+ data_strobe_o => data_strobe,
+ event_data_o => event_data,
+ event_number_i => event_number_o,
+ trigger_count_o => trigger_count
+ );
+ I7 : i2c_master
+ PORT MAP (
+ i2c_scl_i => i2c_scl_b,
+ i2c_sda_i => i2c_sda_b,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(5),
+ ipbus_reset_i => ipbus_reset,
+ i2c_scl_enb_o => s_i2c_scl_enb,
+ i2c_sda_enb_o => s_i2c_sda_enb,
+ ipbus_o => ipbr(5)
+ );
+ I6 : logic_clocks
+ PORT MAP (
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(4),
+ ipbus_reset_i => ipbus_reset,
+ Reset_i => logic_clocks_reset,
+ clk_logic_xtal_i => clk_logic_xtal,
+ clk_16x_logic_o => clk_16x_logic,
+ clk_4x_logic_o => clk_4x_logic,
+ ipbus_o => ipbr(4),
+ strobe_16x_logic_o => strobe_16x_logic,
+ strobe_4x_logic_o => strobe_4x_logic,
+ extclk_p_b => extclk_p_b,
+ extclk_n_b => extclk_n_b,
+ DUT_clk_o => s_DUT_clk,
+ logic_clocks_locked_o => leds_o(1),
+ logic_reset_o => logic_reset
+ );
+ I1 : triggerInputs
+ GENERIC MAP (
+ g_NUM_INPUTS => g_NUM_TRIG_INPUTS
+ )
+ PORT MAP (
+ cfd_discr_p_i => cfd_discr_p_i,
+ cfd_discr_n_i => cfd_discr_n_i,
+ clk_4x_logic => clk_4x_logic,
+ strobe_4x_logic_i => strobe_4x_logic,
+ threshold_discr_p_i => threshold_discr_p_i,
+ threshold_discr_n_i => threshold_discr_n_i,
+ reset_i => reset_i,
+ trigger_times_o => trigger_times,
+ trigger_o => triggers,
+ trigger_debug_o => gpio_hdr,
+ edge_rising_times_o => OPEN,
+ edge_falling_times_o => OPEN,
+ edge_rising_o => OPEN,
+ edge_falling_o => OPEN,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_reset_i => ipbus_reset,
+ ipbus_i => ipbw(1),
+ ipbus_o => ipbr(1),
+ clk_16x_logic_i => clk_16x_logic,
+ strobe_16x_logic_i => strobe_16x_logic
+ );
+ I3 : triggerLogic
+ GENERIC MAP (
+ g_NUM_INPUTS => g_NUM_TRIG_INPUTS,
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH
+ )
+ PORT MAP (
+ clk_4x_logic_i => clk_4x_logic,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(2),
+ ipbus_reset_i => ipbus_reset,
+ logic_reset_i => logic_reset or reset_i,
+ logic_strobe_i => strobe_4x_logic,
+ trigger_i => triggers,
+ trigger_times_i => trigger_times,
+ veto_i => overall_veto,
+ trigger_o => postVeto_triggers,
+ trigger_times_o => postVeto_trigger_times,
+ event_number_o => event_number_o,
+ ipbus_o => ipbr(2),
+ post_veto_trigger_o => overall_trigger,
+ pre_veto_trigger_o => OPEN,
+ trigger_active_o => leds_o(0)
+ );
+
+ I8 : handshakes
+ GENERIC MAP(
+ g_IPBUS_WIDTH => g_IPBUS_WIDTH
+ )
+ PORT MAP(
+ clk_i => s_DUT_clk,
+ Trigger_i => overall_trigger,
+ ipbus_clk_i => ipbus_clk,
+ ipbus_i => ipbw(10),
+ ipbus_reset_i => ipbus_reset,
+ ipbus_o => ipbr(10),
+ logic_reset_i => logic_reset or reset_i,
+ Busy_i => veto_o,
+ AIDAhandshake_o => s_AIDAhandshake,
+ Trigger_o => s_Trig_TO_DUT,
+ rst_or_clk_o => s_rst_or_clk_to_dut
+ );
+
+END ARCHITECTURE struct;
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..3375b6f5fe3906289dd4bfbff13ed1568fcb5204
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_rx.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_rx.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..9498aac6b4bcb0f35ade66a8afb0f2278c5c812f
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_rx.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_rx.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_sm.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_sm.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..8f6ea4a53383a1d4a51138428dc210bfa9a41f6e
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_sm.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_sm.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_tx.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_tx.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..12abb3d08cf45d4ff3e9ef968642d0d785535ea6
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/transactor_tx.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/transactor_tx.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerInputs_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerInputs_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..812a550051dc10f5117f6365d85d2cb5bcb670e0
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerInputs_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerLogic_rtl.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerLogic_rtl.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..8dc8e409d78a9e621153c2fdd01c6ba57d1a8796
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/triggerLogic_rtl.vhd.rlnk
@@ -0,0 +1 @@
+/tmp/fmc_tlu/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/udp_shim.vhd.rlnk b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/udp_shim.vhd.rlnk
new file mode 100644
index 0000000000000000000000000000000000000000..627bc5a7ca510ae5e2f3b32cae103cc834db4d82
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/udp_shim.vhd.rlnk
@@ -0,0 +1 @@
+/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/udp_shim.vhd
\ No newline at end of file
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
new file mode 100644
index 0000000000000000000000000000000000000000..9c5eefa82c953d1fb38ffe321451c08affd17721
Binary files /dev/null and b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat differ
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.xrf/top_extphy_struct.xrf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.xrf/top_extphy_struct.xrf
new file mode 100644
index 0000000000000000000000000000000000000000..ba081b227448f1807410ebc0b7d90ff2f4293b81
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.xrf/top_extphy_struct.xrf
@@ -0,0 +1,1100 @@
+DESIGN top_extphy
+VIEW symbol.sb
+NO_GRAPHIC 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 50,0 8 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 13,0 13 1
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1783,0 23 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 206,0 24 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1282,0 25 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1277,0 26 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1812,0 27 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1798,0 28 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 216,0 29 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 171,0 30 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 176,0 31 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 181,0 32 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 186,0 33 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 339,0 34 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 146,0 35 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1287,0 36 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1272,0 37 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 156,0 38 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 161,0 39 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 166,0 40 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 196,0 41 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1991,0 42 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 151,0 43 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 191,0 44 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1788,0 45 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 211,0 46 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1793,0 47 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 201,0 48 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 950,0 49 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 945,0 50 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1842,0 51 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1805,0 52 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1,0 55 0
+DESIGN top_extphy
+VIEW symbol.sb
+GRAPHIC 1,0 56 0
+DESIGN top_extphy
+VIEW struct.bd
+NO_GRAPHIC 59
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 345,0 99 0
+DESIGN top_extphy
+VIEW struct.bd
+NO_GRAPHIC 110
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 0,0 112 2
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4988,0 117 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4693,0 118 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1205,0 119 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4667,0 120 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 2360,0 121 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10562,0 122 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10570,0 123 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10578,0 124 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10586,0 125 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 3567,0 126 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 9139,0 127 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1668,0 128 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1429,0 129 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10532,0 130 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1431,0 131 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 7099,0 132 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1588,0 133 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 11202,0 134 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 9381,0 135 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1808,0 136 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 1810,0 137 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10096,0 138 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10122,0 139 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10594,0 140 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10602,0 141 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10610,0 142 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10618,0 143 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4695,0 144 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4691,0 145 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 10626,0 146 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 2273,0 147 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 3331,0 148 0
+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 2117,0 149 0
+DESIGN top_extphy
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+DESIGN top_extphy
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+DESIGN top_extphy
+VIEW struct.bd
+NO_GRAPHIC 152
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+DESIGN @d@u@t@interfaces
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+GRAPHIC 6898,0 154 0
+DESIGN @d@u@t@interfaces
+VIEW symbol.sb
+GRAPHIC 14,0 155 1
+DESIGN @d@u@t@interfaces
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+DESIGN @d@u@t@interfaces
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+DESIGN @d@u@t@interfaces
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+DESIGN @d@u@t@interfaces
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+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 4555,0 182 0
+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN @i@p@bus@interface
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+DESIGN top_extphy
+VIEW struct.bd
+GRAPHIC 9363,0 208 0
+DESIGN event@buffer
+VIEW symbol.sb
+GRAPHIC 14,0 209 1
+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN event@buffer
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+DESIGN top_extphy
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN event@formatter
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+DESIGN top_extphy
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+DESIGN i2c_master
+VIEW rtl
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+DESIGN i2c_master
+VIEW rtl
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+DESIGN i2c_master
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+DESIGN i2c_master
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+DESIGN i2c_master
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+DESIGN i2c_master
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+DESIGN i2c_master
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+DESIGN top_extphy
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+DESIGN logic_clocks
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
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+DESIGN logic_clocks
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
+VIEW rtl
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+DESIGN logic_clocks
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+DESIGN logic_clocks
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+DESIGN top_extphy
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+DESIGN trigger@inputs
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+NO_GRAPHIC 568
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..46d5435e1f73442a3186138828f2b47d657a9544
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd
@@ -0,0 +1,3337 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "DUTInterfaces_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352817281"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/DUTInterfaces"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "DUTInterfaces"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "DUTInterfaces"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/DUTInterfaces/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:30"
+)
+(vvPair
+variable "unit"
+value "DUTInterfaces"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+optionalChildren [
+*1 (PortIoIn
+uid 9,0
+shape (CompositeShape
+uid 10,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11,0
+sl 0
+ro 270
+xt "-4000,6625,-2500,7375"
+)
+(Line
+uid 12,0
+sl 0
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+xt "-2500,7000,-2000,7000"
+pts [
+"-2500,7000"
+"-2000,7000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 13,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 14,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-13000,6500,-5000,7400"
+st "busy_from_dut_i"
+ju 2
+blo "-5000,7200"
+tm "WireNameMgr"
+)
+)
+)
+*2 (Net
+uid 15,0
+decl (Decl
+n "busy_from_dut_i"
+t "std_logic_vector"
+b "(NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 1
+suid 1,0
+)
+declText (MLText
+uid 16,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,14175,63000,15075"
+st "busy_from_dut_i : std_logic_vector(NUM_DUTS-1 downto 0) -- BUSY input from DUTs
+"
+)
+)
+*3 (PortIoIn
+uid 23,0
+shape (CompositeShape
+uid 24,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
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+)
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+pts [
+"-2500,6000"
+"-2000,6000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 27,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 28,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-12500,5500,-5000,6400"
+st "clk_4x_logic_i"
+ju 2
+blo "-5000,6200"
+tm "WireNameMgr"
+)
+)
+)
+*4 (Net
+uid 29,0
+lang 11
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+o 2
+suid 2,0
+)
+declText (MLText
+uid 30,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,15075,37000,15975"
+st "clk_4x_logic_i : std_logic
+"
+)
+)
+*5 (PortIoIn
+uid 37,0
+shape (CompositeShape
+uid 38,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 39,0
+sl 0
+ro 270
+xt "-4000,4625,-2500,5375"
+)
+(Line
+uid 40,0
+sl 0
+ro 270
+xt "-2500,5000,-2000,5000"
+pts [
+"-2500,5000"
+"-2000,5000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 41,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 42,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-12500,4500,-5000,5400"
+st "clk_from_dut_i"
+ju 2
+blo "-5000,5200"
+tm "WireNameMgr"
+)
+)
+)
+*6 (Net
+uid 43,0
+decl (Decl
+n "clk_from_dut_i"
+t "std_logic_vector"
+b "(NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 3
+suid 3,0
+)
+declText (MLText
+uid 44,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,15975,72000,16875"
+st "clk_from_dut_i : std_logic_vector(NUM_DUTS-1 downto 0) -- clocks trigger data when in EUDET mode
+"
+)
+)
+*7 (PortIoIn
+uid 51,0
+shape (CompositeShape
+uid 52,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 53,0
+sl 0
+ro 270
+xt "-4000,3625,-2500,4375"
+)
+(Line
+uid 54,0
+sl 0
+ro 270
+xt "-2500,4000,-2000,4000"
+pts [
+"-2500,4000"
+"-2000,4000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 55,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 56,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-11000,3500,-5000,4400"
+st "ipbus_clk_i"
+ju 2
+blo "-5000,4200"
+tm "WireNameMgr"
+)
+)
+)
+*8 (Net
+uid 57,0
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 4
+suid 4,0
+)
+declText (MLText
+uid 58,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,16875,37000,17775"
+st "ipbus_clk_i : std_logic
+"
+)
+)
+*9 (PortIoIn
+uid 65,0
+shape (CompositeShape
+uid 66,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 67,0
+sl 0
+ro 270
+xt "-4000,2625,-2500,3375"
+)
+(Line
+uid 68,0
+sl 0
+ro 270
+xt "-2500,3000,-2000,3000"
+pts [
+"-2500,3000"
+"-2000,3000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 69,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 70,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-8500,2500,-5000,3400"
+st "ipbus_i"
+ju 2
+blo "-5000,3200"
+tm "WireNameMgr"
+)
+)
+)
+*10 (Net
+uid 71,0
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 5
+suid 5,0
+)
+declText (MLText
+uid 72,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,17775,54500,18675"
+st "ipbus_i : ipb_wbus -- Signals from IPBus core to slave
+"
+)
+)
+*11 (PortIoIn
+uid 79,0
+shape (CompositeShape
+uid 80,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 81,0
+sl 0
+ro 270
+xt "-4000,1625,-2500,2375"
+)
+(Line
+uid 82,0
+sl 0
+ro 270
+xt "-2500,2000,-2000,2000"
+pts [
+"-2500,2000"
+"-2000,2000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 83,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 84,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-12000,1500,-5000,2400"
+st "ipbus_reset_i"
+ju 2
+blo "-5000,2200"
+tm "WireNameMgr"
+)
+)
+)
+*12 (Net
+uid 85,0
+lang 11
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 6
+suid 6,0
+)
+declText (MLText
+uid 86,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,18675,37000,19575"
+st "ipbus_reset_i : std_logic
+"
+)
+)
+*13 (PortIoIn
+uid 93,0
+shape (CompositeShape
+uid 94,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 95,0
+sl 0
+ro 270
+xt "-4000,625,-2500,1375"
+)
+(Line
+uid 96,0
+sl 0
+ro 270
+xt "-2500,1000,-2000,1000"
+pts [
+"-2500,1000"
+"-2000,1000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 97,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 98,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-12500,500,-5000,1400"
+st "logic_strobe_i"
+ju 2
+blo "-5000,1200"
+tm "WireNameMgr"
+)
+)
+)
+*14 (Net
+uid 99,0
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! goes high every 4th clock cycle"
+o 7
+suid 7,0
+)
+declText (MLText
+uid 100,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,19575,55500,20475"
+st "logic_strobe_i : std_logic -- ! goes high every 4th clock cycle
+"
+)
+)
+*15 (PortIoIn
+uid 107,0
+shape (CompositeShape
+uid 108,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 109,0
+sl 0
+ro 270
+xt "-4000,-375,-2500,375"
+)
+(Line
+uid 110,0
+sl 0
+ro 270
+xt "-2500,0,-2000,0"
+pts [
+"-2500,0"
+"-2000,0"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 111,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 112,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-14000,-500,-5000,400"
+st "trigger_counter_i"
+ju 2
+blo "-5000,200"
+tm "WireNameMgr"
+)
+)
+)
+*16 (Net
+uid 113,0
+decl (Decl
+n "trigger_counter_i"
+t "std_logic_vector"
+b "(IPBUS_WIDTH-1 DOWNTO 0)"
+o 8
+suid 8,0
+)
+declText (MLText
+uid 114,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,20475,52500,21375"
+st "trigger_counter_i : std_logic_vector(IPBUS_WIDTH-1 downto 0)
+"
+)
+)
+*17 (PortIoIn
+uid 121,0
+shape (CompositeShape
+uid 122,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 123,0
+sl 0
+ro 270
+xt "-4000,-1375,-2500,-625"
+)
+(Line
+uid 124,0
+sl 0
+ro 270
+xt "-2500,-1000,-2000,-1000"
+pts [
+"-2500,-1000"
+"-2000,-1000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 125,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 126,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-9500,-1500,-5000,-600"
+st "trigger_i"
+ju 2
+blo "-5000,-800"
+tm "WireNameMgr"
+)
+)
+)
+*18 (Net
+uid 127,0
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "goes high when trigger logic issues a trigger"
+o 9
+suid 9,0
+)
+declText (MLText
+uid 128,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,21375,61500,22275"
+st "trigger_i : std_logic -- goes high when trigger logic issues a trigger
+"
+)
+)
+*19 (PortIoOut
+uid 135,0
+shape (CompositeShape
+uid 136,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 137,0
+sl 0
+ro 270
+xt "500,3625,2000,4375"
+)
+(Line
+uid 138,0
+sl 0
+ro 270
+xt "0,4000,500,4000"
+pts [
+"0,4000"
+"500,4000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 139,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 140,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,3500,6500,4400"
+st "ipbus_o"
+blo "3000,4200"
+tm "WireNameMgr"
+)
+)
+)
+*20 (Net
+uid 141,0
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 10
+suid 10,0
+)
+declText (MLText
+uid 142,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,22275,54500,23175"
+st "ipbus_o : ipb_rbus -- signals from slave to IPBus core
+"
+)
+)
+*21 (PortIoOut
+uid 149,0
+shape (CompositeShape
+uid 150,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 151,0
+sl 0
+ro 270
+xt "500,2625,2000,3375"
+)
+(Line
+uid 152,0
+sl 0
+ro 270
+xt "0,3000,500,3000"
+pts [
+"0,3000"
+"500,3000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 153,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 154,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,2500,14000,3400"
+st "reset_or_clk_to_dut_o"
+blo "3000,3200"
+tm "WireNameMgr"
+)
+)
+)
+*22 (Net
+uid 155,0
+decl (Decl
+n "reset_or_clk_to_dut_o"
+t "std_logic_vector"
+b "(NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 11
+suid 11,0
+)
+declText (MLText
+uid 156,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,23175,68000,24075"
+st "reset_or_clk_to_dut_o : std_logic_vector(NUM_DUTS-1 downto 0) -- ! Either reset line or trigger
+"
+)
+)
+*23 (PortIoOut
+uid 163,0
+shape (CompositeShape
+uid 164,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 165,0
+sl 0
+ro 270
+xt "500,1625,2000,2375"
+)
+(Line
+uid 166,0
+sl 0
+ro 270
+xt "0,2000,500,2000"
+pts [
+"0,2000"
+"500,2000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 167,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 168,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,1500,11500,2400"
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+name "NUM_DUTS"
+type "positive"
+value "3"
+)
+uid 223,0
+)
+*139 (LogGeneric
+generic (GiElement
+name "IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+uid 225,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
+optionalChildren [
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+font "courier,10,0"
+)
+cellVa (MVa
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+fontColor "0,0,0"
+font "courier,10,0"
+)
+groupVa (MVa
+cellColor "39936,56832,65280"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *141 (MRCItem
+litem &126
+pos 3
+dimension 20
+)
+optionalChildren [
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+pos 5
+dimension 50
+)
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+pos 6
+dimension 80
+)
+]
+)
+fixedCol 3
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+name "Ports"
+vaOverrides [
+]
+)
+]
+)
+type 1
+)
+)
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..fd97c4987d7c242b62bd03d12812da647c40dfd6
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb
@@ -0,0 +1,2488 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+(DmPackageRef
+library "unisim"
+unitName "VComponents"
+)
+]
+libraryRefs [
+"ieee"
+"unisim"
+]
+)
+version "25.1"
+appVersion "2012.1 (Build 6)"
+model (Symbol
+commonDM (CommonDM
+ldm (LogicalDM
+ordering 1
+suid 19,0
+usingSuid 1
+emptyRow *1 (LEmptyRow
+)
+uid 144,0
+optionalChildren [
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+)
+*3 (TitleRowHdr
+)
+*4 (FilterRowHdr
+)
+*5 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*6 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*7 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*8 (NameColHdr
+tm "NameColHdrMgr"
+)
+*9 (ModeColHdr
+tm "ModeColHdrMgr"
+)
+*10 (TypeColHdr
+tm "TypeColHdrMgr"
+)
+*11 (BoundsColHdr
+tm "BoundsColHdrMgr"
+)
+*12 (InitColHdr
+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
+*14 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "-- ! Trigger output"
+posAdd 0
+o 16
+suid 1,0
+)
+)
+uid 51,0
+)
+*15 (LogPort
+port (LogicalPort
+decl (Decl
+n "busy_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 2
+suid 2,0
+)
+)
+uid 53,0
+)
+*16 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 14
+suid 3,0
+)
+)
+uid 55,0
+)
+*17 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "clk_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 5
+suid 4,0
+)
+)
+uid 57,0
+)
+*18 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "-- goes high when trigger logic issues a trigger"
+posAdd 0
+o 11
+suid 5,0
+)
+)
+uid 59,0
+)
+*19 (LogPort
+port (LogicalPort
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+o 3
+suid 6,0
+)
+)
+uid 61,0
+)
+*20 (LogPort
+port (LogicalPort
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! goes high every 4th clock cycle"
+o 9
+suid 7,0
+)
+)
+uid 63,0
+)
+*21 (LogPort
+port (LogicalPort
+decl (Decl
+n "trigger_counter_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 10
+suid 8,0
+)
+)
+uid 65,0
+)
+*22 (LogPort
+port (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 6
+suid 9,0
+)
+)
+uid 107,0
+)
+*23 (LogPort
+port (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 8
+suid 10,0
+)
+)
+uid 109,0
+)
+*24 (LogPort
+port (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 7
+suid 11,0
+)
+)
+uid 111,0
+)
+*25 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+prec "--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter"
+eolc "signals from slave to IPBus core"
+preAdd 0
+o 12
+suid 12,0
+)
+)
+uid 113,0
+)
+*26 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "veto_o"
+t "std_logic"
+prec "--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ --shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output"
+eolc "goes high when one or more DUT are busy"
+preAdd 0
+o 17
+suid 13,0
+)
+)
+uid 115,0
+)
+*27 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 15
+suid 14,0
+)
+)
+uid 341,0
+)
+*28 (LogPort
+port (LogicalPort
+decl (Decl
+n "busy_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 1
+suid 15,0
+)
+)
+uid 343,0
+)
+*29 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 13
+suid 16,0
+)
+)
+uid 345,0
+)
+*30 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "clk_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 4
+suid 17,0
+)
+)
+uid 347,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
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+)
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+)
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+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *32 (MRCItem
+litem &1
+pos 17
+dimension 20
+)
+uid 159,0
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+litem &2
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+name "Ports"
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+]
+)
+]
+)
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+)
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+ldm (LogicalDM
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+)
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+)
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+)
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+)
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+tm "RowExpandColHdrMgr"
+)
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+tm "GroupColHdrMgr"
+)
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+tm "GenericNameColHdrMgr"
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+tm "GenericEolColHdrMgr"
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+name "g_NUM_DUTS"
+type "positive"
+value "3"
+)
+uid 433,0
+)
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+generic (GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+uid 435,0
+)
+]
+)
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+)
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+)
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+dimension 20
+)
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+)
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+)
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+)
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+)
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+)
+fixedCol 3
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+vaOverrides [
+]
+)
+]
+)
+uid 172,0
+type 1
+)
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/DUTInterfaces"
+)
+(vvPair
+variable "date"
+value "07/23/13"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "23"
+)
+(vvPair
+variable "entity_name"
+value "DUTInterfaces"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
+(vvPair
+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
+)
+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "07"
+)
+(vvPair
+variable "module_name"
+value "DUTInterfaces"
+)
+(vvPair
+variable "month"
+value "Jul"
+)
+(vvPair
+variable "month_long"
+value "July"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@d@u@t@interfaces/symbol.sb"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/DUTInterfaces/symbol.sb"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
+variable "this_file"
+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "16:34:25"
+)
+(vvPair
+variable "unit"
+value "DUTInterfaces"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2012.1 (Build 6)"
+)
+(vvPair
+variable "view"
+value "symbol"
+)
+(vvPair
+variable "year"
+value "2013"
+)
+(vvPair
+variable "yy"
+value "13"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 142,0
+optionalChildren [
+*89 (SymbolBody
+uid 8,0
+optionalChildren [
+*90 (CptPort
+uid 67,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 68,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,18625,59750,19375"
+)
+tg (CPTG
+uid 69,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 70,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39000,18550,58000,19450"
+st "trigger_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "58000,19250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 71,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,16200,92000,17100"
+st "trigger_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- ! Trigger output
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "-- ! Trigger output"
+posAdd 0
+o 16
+suid 1,0
+)
+)
+)
+*91 (CptPort
+uid 72,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 73,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,17625,14000,18375"
+)
+tg (CPTG
+uid 74,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 75,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,17550,33500,18450"
+st "busy_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "15000,18250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 76,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,2700,94000,3600"
+st "busy_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- BUSY input from DUTs
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "busy_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 2
+suid 2,0
+)
+)
+)
+*92 (CptPort
+uid 77,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 78,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,25625,59750,26375"
+)
+tg (CPTG
+uid 79,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 80,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,25550,58000,26450"
+st "reset_or_clk_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "58000,26250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 81,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,14400,99000,15300"
+st "reset_or_clk_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- ! Either reset line or trigger
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 14
+suid 3,0
+)
+)
+)
+*93 (CptPort
+uid 82,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 83,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,21625,14000,22375"
+)
+tg (CPTG
+uid 84,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 85,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,21550,33000,22450"
+st "clk_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "15000,22250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 86,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,5400,103000,6300"
+st "clk_from_dut_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- clocks trigger data when in EUDET mode
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 5
+suid 4,0
+)
+)
+)
+*94 (CptPort
+uid 87,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 88,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,25625,14000,26375"
+)
+tg (CPTG
+uid 89,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 90,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,25550,19500,26450"
+st "trigger_i"
+blo "15000,26250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 91,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,10800,91500,11700"
+st "trigger_i : IN std_logic ; -- goes high when trigger logic issues a trigger
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "-- goes high when trigger logic issues a trigger"
+posAdd 0
+o 11
+suid 5,0
+)
+)
+)
+*95 (CptPort
+uid 92,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 93,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,27625,14000,28375"
+)
+tg (CPTG
+uid 94,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 95,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,27550,22500,28450"
+st "clk_4x_logic_i"
+blo "15000,28250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 96,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,3600,67000,4500"
+st "clk_4x_logic_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+o 3
+suid 6,0
+)
+)
+)
+*96 (CptPort
+uid 97,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 98,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,29625,14000,30375"
+)
+tg (CPTG
+uid 99,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 100,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,29550,24000,30450"
+st "strobe_4x_logic_i"
+blo "15000,30250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 101,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9000,85500,9900"
+st "strobe_4x_logic_i : IN std_logic ; -- ! goes high every 4th clock cycle
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! goes high every 4th clock cycle"
+o 9
+suid 7,0
+)
+)
+)
+*97 (CptPort
+uid 102,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 103,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,31625,14000,32375"
+)
+tg (CPTG
+uid 104,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 105,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,31550,35000,32450"
+st "trigger_counter_i : (g_IPBUS_WIDTH-1:0)"
+blo "15000,32250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 106,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9900,83500,10800"
+st "trigger_counter_i : IN std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_counter_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 10
+suid 8,0
+)
+)
+)
+*98 (CptPort
+uid 117,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 118,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,33625,14000,34375"
+)
+tg (CPTG
+uid 119,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 120,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,33550,21000,34450"
+st "ipbus_clk_i"
+blo "15000,34250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 121,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,6300,67000,7200"
+st "ipbus_clk_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 6
+suid 9,0
+)
+)
+)
+*99 (CptPort
+uid 122,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 123,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,35625,14000,36375"
+)
+tg (CPTG
+uid 124,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 125,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,35550,22000,36450"
+st "ipbus_reset_i"
+blo "15000,36250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 126,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,8100,67000,9000"
+st "ipbus_reset_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 8
+suid 10,0
+)
+)
+)
+*100 (CptPort
+uid 127,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 128,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,37625,14000,38375"
+)
+tg (CPTG
+uid 129,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 130,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,37550,18500,38450"
+st "ipbus_i"
+blo "15000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 131,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,7200,84500,8100"
+st "ipbus_i : IN ipb_wbus ; -- Signals from IPBus core to slave
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 7
+suid 11,0
+)
+)
+)
+*101 (CptPort
+uid 132,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 133,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,32625,59750,33375"
+)
+tg (CPTG
+uid 134,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 135,0
+va (VaSet
+font "courier,8,0"
+)
+xt "54500,32550,58000,33450"
+st "ipbus_o"
+ju 2
+blo "58000,33250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 136,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,11700,109000,13500"
+st "--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter
+ipbus_o : OUT ipb_rbus ; -- signals from slave to IPBus core
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+prec "--shutter_i : IN std_logic; -- goes high when trigger logic issues a shutter"
+eolc "signals from slave to IPBus core"
+preAdd 0
+o 12
+suid 12,0
+)
+)
+)
+*102 (CptPort
+uid 137,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 138,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,36625,59750,37375"
+)
+tg (CPTG
+uid 139,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 140,0
+va (VaSet
+font "courier,8,0"
+)
+xt "55000,36550,58000,37450"
+st "veto_o"
+ju 2
+blo "58000,37250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 141,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,17100,95500,19800"
+st "--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ --shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+veto_o : OUT std_logic -- goes high when one or more DUT are busy
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "veto_o"
+t "std_logic"
+prec "--shutter_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output
+ --shutter_to_dut_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); -- ! Shutter output"
+eolc "goes high when one or more DUT are busy"
+preAdd 0
+o 17
+suid 13,0
+)
+)
+)
+*103 (CptPort
+uid 349,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 350,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,20625,59750,21375"
+)
+tg (CPTG
+uid 351,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 352,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39000,20550,58000,21450"
+st "trigger_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "58000,21250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 353,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,15300,92000,16200"
+st "trigger_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- ! Trigger output
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 15
+suid 14,0
+)
+)
+)
+*104 (CptPort
+uid 354,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 355,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,19625,14000,20375"
+)
+tg (CPTG
+uid 356,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 357,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,19550,33500,20450"
+st "busy_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "15000,20250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 358,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,1800,94000,2700"
+st "busy_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- BUSY input from DUTs
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "busy_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 1
+suid 15,0
+)
+)
+)
+*105 (CptPort
+uid 359,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 360,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "59000,27625,59750,28375"
+)
+tg (CPTG
+uid 361,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 362,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,27550,58000,28450"
+st "reset_or_clk_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "58000,28250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 363,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,13500,99000,14400"
+st "reset_or_clk_to_dut_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- ! Either reset line or trigger
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 13
+suid 16,0
+)
+)
+)
+*106 (CptPort
+uid 364,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 365,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "13250,23625,14000,24375"
+)
+tg (CPTG
+uid 366,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 367,0
+va (VaSet
+font "courier,8,0"
+)
+xt "15000,23550,33000,24450"
+st "clk_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "15000,24250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 368,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,4500,103000,5400"
+st "clk_from_dut_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; -- clocks trigger data when in EUDET mode
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 4
+suid 17,0
+)
+)
+)
+]
+shape (Rectangle
+uid 9,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "14000,17000,59000,40000"
+)
+oxt "14000,17000,57000,37000"
+biTextGroup (BiTextGroup
+uid 10,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (Text
+uid 11,0
+va (VaSet
+font "courier,8,1"
+)
+xt "23750,26100,25750,27000"
+st "work"
+blo "23750,26800"
+)
+second (Text
+uid 12,0
+va (VaSet
+font "courier,8,1"
+)
+xt "23750,27000,30750,27900"
+st "DUTInterfaces"
+blo "23750,27700"
+)
+)
+gi *107 (GenericInterface
+uid 13,0
+ps "CenterOffsetStrategy"
+matrix (Matrix
+uid 14,0
+text (MLText
+uid 15,0
+va (VaSet
+font "courier,8,0"
+)
+xt "22000,13400,36000,17000"
+st "Generic Declarations
+
+g_NUM_DUTS positive 3
+g_IPBUS_WIDTH positive 32
+"
+)
+header "Generic Declarations"
+showHdrWhenContentsEmpty 1
+)
+elements [
+(GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "3"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+]
+)
+portInstanceVisAsIs 1
+portInstanceVis (PortSigDisplay
+sIVOD 1
+)
+portVis (PortSigDisplay
+sIVOD 1
+)
+)
+*108 (Grouping
+uid 16,0
+optionalChildren [
+*109 (CommentText
+uid 18,0
+shape (Rectangle
+uid 19,0
+sl 0
+va (VaSet
+vasetType 1
+fg "65280,65280,46080"
+)
+xt "32000,50000,49000,51000"
+)
+oxt "18000,70000,35000,71000"
+text (MLText
+uid 20,0
+va (VaSet
+fg "0,0,32768"
+bg "0,0,32768"
+font "courier,8,0"
+)
+xt "32200,50050,44200,50950"
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..dd3880ce4353cd51da9f46ba35cd83bb4a987eff
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd
@@ -0,0 +1,10323 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+instances [
+(Instance
+name "clocks"
+duLibraryName "fmc_mTLU_lib"
+duName "clocks_s6_extphy"
+elements [
+]
+mwi 0
+uid 371,0
+)
+(Instance
+name "eth"
+duLibraryName "fmc_mTLU_lib"
+duName "eth_s6_gmii"
+elements [
+(GiElement
+name "IODEL"
+type "integer"
+value "10"
+)
+]
+mwi 0
+uid 554,0
+)
+(Instance
+name "ipbus"
+duLibraryName "fmc_mTLU_lib"
+duName "ipbus_ctrl_udponly"
+elements [
+]
+mwi 0
+uid 831,0
+)
+(Instance
+name "fabric"
+duLibraryName "fmc_mTLU_lib"
+duName "ipbus_fabric"
+elements [
+(GiElement
+name "NSLV"
+type "positive"
+value "NUM_SLAVES"
+)
+(GiElement
+name "STROBE_GAP"
+type "boolean"
+value "false"
+)
+]
+mwi 0
+uid 1028,0
+)
+(Instance
+name "hostbus_interface"
+duLibraryName "fmc_mTLU_lib"
+duName "ipbus_emac_hostbus"
+elements [
+]
+mwi 0
+uid 1122,0
+)
+]
+embeddedInstances [
+(EmbeddedInstance
+name "eb1"
+number "1"
+)
+(EmbeddedInstance
+name "eb2"
+number "2"
+)
+(EmbeddedInstance
+name "eb3"
+number "3"
+)
+(EmbeddedInstance
+name "eb4"
+number "4"
+)
+(EmbeddedInstance
+name "eb5"
+number "5"
+)
+(EmbeddedInstance
+name "eb6"
+number "6"
+)
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "IPBusInterface_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352817615"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
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+)
+(vvPair
+variable "appl"
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+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/IPBusInterface"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "IPBusInterface"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "IPBusInterface"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/IPBusInterface/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:33"
+)
+(vvPair
+variable "unit"
+value "IPBusInterface"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+optionalChildren [
+*1 (Net
+uid 9,0
+lang 11
+decl (Decl
+n "clk125"
+t "STD_LOGIC"
+o 21
+suid 1,0
+)
+declText (MLText
+uid 10,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,83200,37500,84100"
+st "SIGNAL clk125 : STD_LOGIC
+"
+)
+)
+*2 (Net
+uid 11,0
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+)
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+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*77 (SaComponent
+uid 554,0
+optionalChildren [
+*78 (CptPort
+uid 564,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 565,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,21625,33000,22375"
+)
+tg (CPTG
+uid 566,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 567,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,21550,37000,22450"
+st "clk125"
+blo "34000,22250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk125"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*79 (CptPort
+uid 568,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 569,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,22625,33000,23375"
+)
+tg (CPTG
+uid 570,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 571,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,22550,35500,23450"
+st "rst"
+blo "34000,23250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rst"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*80 (CptPort
+uid 572,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 573,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,16625,48750,17375"
+)
+tg (CPTG
+uid 574,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 575,0
+va (VaSet
+font "courier,8,0"
+)
+xt "40500,16550,47000,17450"
+st "gmii_gtx_clk"
+ju 2
+blo "47000,17250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*81 (CptPort
+uid 576,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 577,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,19625,48750,20375"
+)
+tg (CPTG
+uid 578,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 579,0
+va (VaSet
+font "courier,8,0"
+)
+xt "43000,19550,47000,20450"
+st "gmii_txd"
+ju 2
+blo "47000,20250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*82 (CptPort
+uid 580,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 581,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,17625,48750,18375"
+)
+tg (CPTG
+uid 582,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 583,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41500,17550,47000,18450"
+st "gmii_tx_en"
+ju 2
+blo "47000,18250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*83 (CptPort
+uid 584,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 585,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,18625,48750,19375"
+)
+tg (CPTG
+uid 586,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 587,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41500,18550,47000,19450"
+st "gmii_tx_er"
+ju 2
+blo "47000,19250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*84 (CptPort
+uid 588,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 589,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,16625,33000,17375"
+)
+tg (CPTG
+uid 590,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 591,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,16550,40000,17450"
+st "gmii_rx_clk"
+blo "34000,17250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*85 (CptPort
+uid 592,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 593,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,19625,33000,20375"
+)
+tg (CPTG
+uid 594,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 595,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,19550,38000,20450"
+st "gmii_rxd"
+blo "34000,20250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*86 (CptPort
+uid 596,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 597,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,17625,33000,18375"
+)
+tg (CPTG
+uid 598,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 599,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,17550,39500,18450"
+st "gmii_rx_dv"
+blo "34000,18250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_dv"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*87 (CptPort
+uid 600,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 601,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,18625,33000,19375"
+)
+tg (CPTG
+uid 602,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 603,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,18550,39500,19450"
+st "gmii_rx_er"
+blo "34000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_er"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
+*88 (CptPort
+uid 604,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 605,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,23625,33000,24375"
+)
+tg (CPTG
+uid 606,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 607,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,23550,35500,24450"
+st "txd"
+blo "34000,24250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "txd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*89 (CptPort
+uid 608,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 609,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,24625,33000,25375"
+)
+tg (CPTG
+uid 610,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 611,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,24550,37000,25450"
+st "txdvld"
+blo "34000,25250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "txdvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*90 (CptPort
+uid 612,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 613,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,21625,48750,22375"
+)
+tg (CPTG
+uid 614,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 615,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44500,21550,47000,22450"
+st "txack"
+ju 2
+blo "47000,22250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "txack"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 13
+)
+)
+)
+*91 (CptPort
+uid 616,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 617,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,22625,48750,23375"
+)
+tg (CPTG
+uid 618,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 619,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,22550,47000,23450"
+st "rxclko"
+ju 2
+blo "47000,23250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rxclko"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 14
+)
+)
+)
+*92 (CptPort
+uid 620,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 621,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,23625,48750,24375"
+)
+tg (CPTG
+uid 622,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 623,0
+va (VaSet
+font "courier,8,0"
+)
+xt "45500,23550,47000,24450"
+st "rxd"
+ju 2
+blo "47000,24250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rxd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 15
+)
+)
+)
+*93 (CptPort
+uid 624,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 625,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,24625,48750,25375"
+)
+tg (CPTG
+uid 626,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 627,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,24550,47000,25450"
+st "rxdvld"
+ju 2
+blo "47000,25250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rxdvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 16
+)
+)
+)
+*94 (CptPort
+uid 628,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 629,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,25625,48750,26375"
+)
+tg (CPTG
+uid 630,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 631,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41000,25550,47000,26450"
+st "rxgoodframe"
+ju 2
+blo "47000,26250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rxgoodframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 17
+)
+)
+)
+*95 (CptPort
+uid 632,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 633,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,26625,48750,27375"
+)
+tg (CPTG
+uid 634,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 635,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41500,26550,47000,27450"
+st "rxbadframe"
+ju 2
+blo "47000,27250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rxbadframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 18
+)
+)
+)
+*96 (CptPort
+uid 636,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 637,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "32250,25625,33000,26375"
+)
+tg (CPTG
+uid 638,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 639,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34000,25550,39500,26450"
+st "hostbus_in"
+blo "34000,26250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostbus_in"
+t "emac_hostbus_in"
+preAdd 0
+posAdd 0
+o 19
+)
+)
+)
+*97 (CptPort
+uid 640,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 641,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "48000,26625,48750,27375"
+)
+tg (CPTG
+uid 642,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 643,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41000,26550,47000,27450"
+st "hostbus_out"
+ju 2
+blo "47000,27250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "hostbus_out"
+t "emac_hostbus_out"
+preAdd 0
+posAdd 0
+o 20
+)
+)
+)
+*98 (CommentText
+uid 764,0
+ps "EdgeToEdgeStrategy"
+shape (Rectangle
+uid 765,0
+layer 0
+va (VaSet
+vasetType 1
+fg "65280,65280,46080"
+lineColor "0,0,32768"
+)
+xt "33000,16000,48000,20000"
+)
+text (MLText
+uid 766,0
+va (VaSet
+fg "0,0,32768"
+font "courier,8,0"
+)
+xt "33200,16200,48200,19800"
+st "
+ leds <= ('0', '0', locked, onehz);
+
+ Ethernet MAC core and PHY interface
+ In this version, consists of hard MAC core and GMII interface to external PHY
+ Can be replaced by any other MAC / PHY combination
+
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 4000
+visibleWidth 15000
+)
+included 1
+)
+*99 (PortMapFrame
+uid 1373,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 1374,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "31000,14000,50000,30000"
+)
+portMapText (BiTextGroup
+uid 1375,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 1376,0
+va (VaSet
+font "courier,8,0"
+)
+xt "50000,30000,66000,39000"
+st "gmii_rx_clk => gmii_rx_clk_i,
+gmii_rx_dv => gmii_rx_dv_i,
+gmii_rx_er => gmii_rx_er_i,
+gmii_rxd => gmii_rxd_i,
+hostbus_in => hostbus_in,
+gmii_gtx_clk => gmii_gtx_clk_o,
+gmii_tx_en => gmii_tx_en_o,
+gmii_tx_er => gmii_tx_er_o,
+gmii_txd => gmii_txd_o,
+hostbus_out => hostbus_out,"
+)
+second (MLText
+uid 1377,0
+va (VaSet
+font "courier,8,0"
+)
+xt "50000,39000,66000,48000"
+st "clk125 => clk125,
+rst => rst_125,
+rxclko => mac_rxclko,
+rxbadframe => mac_rxbadframe,
+txack => mac_txack,
+rxgoodframe => mac_rxgoodframe,
+rxd => mac_rxd,
+rxdvld => mac_rxdvld,
+txdvld => mac_txdvld,
+txd => mac_txd"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 555,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "33000,16000,48000,28000"
+)
+ttg (MlTextGroup
+uid 556,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*100 (Text
+uid 557,0
+va (VaSet
+font "courier,8,1"
+)
+xt "37250,28000,43750,28900"
+st "fmc_mTLU_lib"
+blo "37250,28700"
+tm "BdLibraryNameMgr"
+)
+*101 (Text
+uid 558,0
+va (VaSet
+font "courier,8,1"
+)
+xt "37250,28900,43250,29800"
+st "eth_s6_gmii"
+blo "37250,29600"
+tm "CptNameMgr"
+)
+*102 (Text
+uid 559,0
+va (VaSet
+font "courier,8,1"
+)
+xt "37250,29800,38750,30700"
+st "eth"
+blo "37250,30500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 560,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 561,0
+text (MLText
+uid 562,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32750,15100,46750,16000"
+st "IODEL = 10 ( integer )
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "IODEL"
+type "integer"
+value "10"
+)
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 563,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "33250,26250,34750,27750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*103 (SaComponent
+uid 831,0
+optionalChildren [
+*104 (CptPort
+uid 841,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 842,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,18625,65000,19375"
+)
+tg (CPTG
+uid 843,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 844,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,18550,69500,19450"
+st "ipb_clk"
+blo "66000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipb_clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*105 (CptPort
+uid 845,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 846,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,19625,65000,20375"
+)
+tg (CPTG
+uid 847,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 848,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,19550,69500,20450"
+st "rst_ipb"
+blo "66000,20250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rst_ipb"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*106 (CptPort
+uid 849,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 850,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,20625,65000,21375"
+)
+tg (CPTG
+uid 851,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 852,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,20550,71500,21450"
+st "rst_macclk"
+blo "66000,21250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rst_macclk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*107 (CptPort
+uid 853,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 854,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,21625,65000,22375"
+)
+tg (CPTG
+uid 855,0
+ps "CptPortTextPlaceStrategy"
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+)
+xt "66000,21550,70500,22450"
+st "mac_txclk"
+blo "66000,22250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_txclk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*108 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "64250,22625,65000,23375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "66000,22550,70500,23450"
+st "mac_rxclk"
+blo "66000,23250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_rxclk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*109 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
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+)
+tg (CPTG
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+f (Text
+uid 864,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,23550,69500,24450"
+st "mac_rxd"
+blo "66000,24250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_rxd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*110 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "64250,24625,65000,25375"
+)
+tg (CPTG
+uid 867,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 868,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,24550,71500,25450"
+st "mac_rxdvld"
+blo "66000,25250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_rxdvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*111 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+fg "0,65535,0"
+)
+xt "64250,25625,65000,26375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 872,0
+va (VaSet
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+)
+xt "66000,25550,74000,26450"
+st "mac_rxgoodframe"
+blo "66000,26250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_rxgoodframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*112 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 874,0
+ro 90
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+)
+xt "64250,26625,65000,27375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "66000,26550,73500,27450"
+st "mac_rxbadframe"
+blo "66000,27250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_rxbadframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*113 (CptPort
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+)
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+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
+f (Text
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+va (VaSet
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+)
+xt "76500,14550,80000,15450"
+st "mac_txd"
+ju 2
+blo "80000,15250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "mac_txd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
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+)
+xt "81000,15625,81750,16375"
+)
+tg (CPTG
+uid 883,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 884,0
+va (VaSet
+font "courier,8,0"
+)
+xt "74500,15550,80000,16450"
+st "mac_txdvld"
+ju 2
+blo "80000,16250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "mac_txdvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*115 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,23625,65000,24375"
+)
+tg (CPTG
+uid 887,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 888,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,23550,70500,24450"
+st "mac_txack"
+blo "66000,24250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_txack"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*116 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 890,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "81000,26625,81750,27375"
+)
+tg (CPTG
+uid 891,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 892,0
+va (VaSet
+font "courier,8,0"
+)
+xt "76500,26550,80000,27450"
+st "ipb_out"
+ju 2
+blo "80000,27250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipb_out"
+t "ipb_wbus"
+preAdd 0
+posAdd 0
+o 13
+)
+)
+)
+*117 (CptPort
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+ps "OnEdgeStrategy"
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+uid 894,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,26625,65000,27375"
+)
+tg (CPTG
+uid 895,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 896,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,26550,69000,27450"
+st "ipb_in"
+blo "66000,27250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipb_in"
+t "ipb_rbus"
+preAdd 0
+posAdd 0
+o 14
+)
+)
+)
+*118 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
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+fg "0,65535,0"
+)
+xt "64250,15625,65000,16375"
+)
+tg (CPTG
+uid 899,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 900,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,15550,70000,16450"
+st "mac_addr"
+blo "66000,16250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "mac_addr"
+t "std_logic_vector"
+b "(47 downto 0)"
+preAdd 0
+posAdd 0
+o 15
+)
+)
+)
+*119 (CptPort
+uid 901,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 902,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "64250,17625,65000,18375"
+)
+tg (CPTG
+uid 903,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 904,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,17550,69500,18450"
+st "ip_addr"
+blo "66000,18250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ip_addr"
+t "std_logic_vector"
+b "(31 downto 0)"
+preAdd 0
+posAdd 0
+o 16
+)
+)
+)
+*120 (CommentText
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+ps "EdgeToEdgeStrategy"
+shape (Rectangle
+uid 1002,0
+layer 0
+va (VaSet
+vasetType 1
+fg "65280,65280,46080"
+lineColor "0,0,32768"
+)
+xt "65000,14000,80000,18000"
+)
+text (MLText
+uid 1003,0
+va (VaSet
+fg "0,0,32768"
+font "courier,8,0"
+)
+xt "65200,14200,75700,15100"
+st "
+ ipbus control logic
+
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 4000
+visibleWidth 15000
+)
+included 1
+)
+*121 (PortMapFrame
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+shape (RectFrame
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+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "63000,12000,83000,30000"
+)
+portMapText (BiTextGroup
+uid 1441,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 1442,0
+va (VaSet
+font "courier,8,0"
+)
+xt "83000,30000,96500,33600"
+st "ip_addr => ip_addr,
+ipb_in => ipb_master_in,
+mac_addr => mac_addr,
+ipb_out => ipb_master_out,"
+)
+second (MLText
+uid 1443,0
+va (VaSet
+font "courier,8,0"
+)
+xt "83000,33600,101000,44400"
+st "rst_macclk => rst_125,
+rst_ipb => rst_ipb,
+mac_txclk => clk125,
+ipb_clk => ipb_clk,
+mac_rxgoodframe => mac_rxgoodframe,
+mac_rxbadframe => mac_rxbadframe,
+mac_rxdvld => mac_rxdvld,
+mac_txack => mac_txack,
+mac_rxd => mac_rxd,
+mac_rxclk => mac_rxclko,
+mac_txd => mac_txd,
+mac_txdvld => mac_txdvld"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
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+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "65000,14000,81000,28000"
+)
+ttg (MlTextGroup
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+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*122 (Text
+uid 834,0
+va (VaSet
+font "courier,8,1"
+)
+xt "68250,28000,74750,28900"
+st "fmc_mTLU_lib"
+blo "68250,28700"
+tm "BdLibraryNameMgr"
+)
+*123 (Text
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+va (VaSet
+font "courier,8,1"
+)
+xt "68250,28900,77750,29800"
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+blo "68250,29600"
+tm "CptNameMgr"
+)
+*124 (Text
+uid 836,0
+va (VaSet
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+)
+xt "68250,29800,70750,30700"
+st "ipbus"
+blo "68250,30500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 837,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 838,0
+text (MLText
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+va (VaSet
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+)
+xt "63250,14000,63250,14000"
+)
+header ""
+)
+elements [
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
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+sl 0
+va (VaSet
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+)
+xt "65250,26250,66750,27750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*125 (SaComponent
+uid 1028,0
+optionalChildren [
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+uid 1038,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+va (VaSet
+vasetType 1
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+)
+xt "64250,6625,65000,7375"
+)
+tg (CPTG
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+f (Text
+uid 1041,0
+va (VaSet
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+)
+xt "66000,6550,69500,7450"
+st "ipb_clk"
+blo "66000,7250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipb_clk"
+t "STD_LOGIC"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*127 (CptPort
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+)
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+)
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+va (VaSet
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+)
+xt "66000,7550,67500,8450"
+st "rst"
+blo "66000,8250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rst"
+t "STD_LOGIC"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*128 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "64250,8625,65000,9375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "66000,8550,69000,9450"
+st "ipb_in"
+blo "66000,9250"
+)
+)
+thePort (LogicalPort
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+n "ipb_in"
+t "ipb_wbus"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*129 (CptPort
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+ps "OnEdgeStrategy"
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+)
+xt "82000,8625,82750,9375"
+)
+tg (CPTG
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+f (Text
+uid 1053,0
+va (VaSet
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+)
+xt "77500,8550,81000,9450"
+st "ipb_out"
+ju 2
+blo "81000,9250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipb_out"
+t "ipb_rbus"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*130 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "82000,7625,82750,8375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "74000,7550,81000,8450"
+st "ipb_to_slaves"
+ju 2
+blo "81000,8250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipb_to_slaves"
+t "ipb_wbus_array"
+b "(NSLV-1 downto 0)"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*131 (CptPort
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+)
+xt "64250,7625,65000,8375"
+)
+tg (CPTG
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+f (Text
+uid 1061,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66000,7550,74000,8450"
+st "ipb_from_slaves"
+blo "66000,8250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipb_from_slaves"
+t "ipb_rbus_array"
+b "(NSLV-1 downto 0)"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*132 (PortMapFrame
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+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 1467,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
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+lineWidth 2
+)
+xt "63000,3000,84000,12000"
+)
+portMapText (BiTextGroup
+uid 1468,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 1469,0
+va (VaSet
+font "courier,8,0"
+)
+xt "84000,12000,102000,15600"
+st "ipb_from_slaves => s_ipbr_internal,
+ipb_in => ipb_master_out,
+ipb_out => ipb_master_in,
+ipb_to_slaves => s_ipbw_internal,"
+)
+second (MLText
+uid 1470,0
+va (VaSet
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+)
+xt "84000,15600,94000,17400"
+st "ipb_clk => ipb_clk,
+rst => rst_ipb"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 1029,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "65000,5000,82000,10000"
+)
+ttg (MlTextGroup
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+ps "CenterOffsetStrategy"
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+va (VaSet
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+)
+xt "70250,10000,76750,10900"
+st "fmc_mTLU_lib"
+blo "70250,10700"
+tm "BdLibraryNameMgr"
+)
+*134 (Text
+uid 1032,0
+va (VaSet
+font "courier,8,1"
+)
+xt "70250,10900,76750,11800"
+st "ipbus_fabric"
+blo "70250,11600"
+tm "CptNameMgr"
+)
+*135 (Text
+uid 1033,0
+va (VaSet
+font "courier,8,1"
+)
+xt "70250,11800,73250,12700"
+st "fabric"
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+)
+]
+)
+ga (GenericAssociation
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+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 1035,0
+text (MLText
+uid 1036,0
+va (VaSet
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+)
+xt "64750,3200,85750,5000"
+st "NSLV = NUM_SLAVES ( positive )
+STROBE_GAP = false ( boolean )
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "NSLV"
+type "positive"
+value "NUM_SLAVES"
+)
+(GiElement
+name "STROBE_GAP"
+type "boolean"
+value "false"
+)
+]
+)
+viewicon (ZoomableIcon
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+sl 0
+va (VaSet
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+)
+xt "65250,8250,66750,9750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*136 (SaComponent
+uid 1122,0
+optionalChildren [
+*137 (CptPort
+uid 1132,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
+vasetType 1
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+)
+xt "98250,38625,99000,39375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
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+)
+xt "100000,38550,101500,39450"
+st "clk"
+blo "100000,39250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*138 (CptPort
+uid 1136,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1137,0
+ro 90
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+)
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+)
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+"
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+)
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+)
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+)
+]
+)
+)
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+)
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+)
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+)
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+)
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+)
+*390 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*391 (NameColHdr
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+)
+*392 (TypeColHdr
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..0c60ef7a4985a338cbe60253dae23defa1a571c6
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb
@@ -0,0 +1,2531 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+(DmPackageRef
+library "work"
+unitName "emac_hostbus_decl"
+)
+]
+libraryRefs [
+"ieee"
+]
+)
+version "25.1"
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+usingSuid 1
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+)
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+)
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+)
+*6 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*7 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*8 (NameColHdr
+tm "NameColHdrMgr"
+)
+*9 (ModeColHdr
+tm "ModeColHdrMgr"
+)
+*10 (TypeColHdr
+tm "TypeColHdrMgr"
+)
+*11 (BoundsColHdr
+tm "BoundsColHdrMgr"
+)
+*12 (InitColHdr
+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
+*14 (LogPort
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+n "gmii_rx_clk_i"
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+o 1
+suid 2,0
+)
+)
+uid 50,0
+)
+*15 (LogPort
+port (LogicalPort
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+o 2
+suid 3,0
+)
+)
+uid 52,0
+)
+*16 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 3
+suid 4,0
+)
+)
+uid 54,0
+)
+*17 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 4
+suid 5,0
+)
+)
+uid 56,0
+)
+*18 (LogPort
+port (LogicalPort
+m 1
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+t "std_logic"
+o 10
+suid 6,0
+)
+)
+uid 58,0
+)
+*19 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
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+o 11
+suid 7,0
+)
+)
+uid 60,0
+)
+*20 (LogPort
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+m 1
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+o 12
+suid 8,0
+)
+)
+uid 62,0
+)
+*21 (LogPort
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+o 17
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+)
+)
+uid 66,0
+)
+*22 (LogPort
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+m 1
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+n "gmii_gtx_clk_o"
+t "std_logic"
+o 9
+suid 1,0
+)
+)
+uid 48,0
+)
+*23 (LogPort
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+o 6
+suid 12,0
+)
+)
+uid 70,0
+)
+*24 (LogPort
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+lang 11
+decl (Decl
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+t "std_logic"
+eolc "! 200 MHz xtal clock"
+o 7
+suid 13,0
+)
+)
+uid 72,0
+)
+*25 (LogPort
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+m 1
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+t "std_logic"
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+o 13
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+)
+)
+uid 190,0
+)
+*26 (LogPort
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+lang 11
+m 1
+decl (Decl
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+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 14
+suid 15,0
+)
+)
+uid 192,0
+)
+*27 (LogPort
+port (LogicalPort
+lang 11
+m 1
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+n "ipbw_o"
+t "ipb_wbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IBus write signals"
+o 15
+suid 16,0
+)
+)
+uid 194,0
+)
+*28 (LogPort
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+lang 11
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+t "ipb_rbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IPBus read signals"
+o 5
+suid 19,0
+)
+)
+uid 200,0
+)
+*29 (LogPort
+port (LogicalPort
+m 1
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+o 16
+suid 22,0
+)
+)
+uid 283,0
+)
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+m 1
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+o 8
+suid 23,0
+)
+)
+uid 285,0
+)
+*31 (LogPort
+port (LogicalPort
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 18
+suid 25,0
+)
+)
+uid 306,0
+)
+*32 (LogPort
+port (LogicalPort
+m 1
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+o 19
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+)
+)
+uid 384,0
+)
+]
+)
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+emptyRow *65 (LEmptyRow
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+optionalChildren [
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+)
+*72 (NameColHdr
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+)
+*74 (InitColHdr
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+*77 (LogGeneric
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+)
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+)
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+vaOverrides [
+]
+)
+]
+)
+uid 161,0
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+)
+VExpander (VariableExpander
+vvMap [
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+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
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+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
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+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/IPBusInterface"
+)
+(vvPair
+variable "date"
+value "11/15/12"
+)
+(vvPair
+variable "day"
+value "Thu"
+)
+(vvPair
+variable "day_long"
+value "Thursday"
+)
+(vvPair
+variable "dd"
+value "15"
+)
+(vvPair
+variable "entity_name"
+value "IPBusInterface"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
+(vvPair
+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "calgary.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "IPBusInterface"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/@i@p@bus@interface/symbol.sb"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/IPBusInterface/symbol.sb"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
+variable "this_file"
+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "18:00:57"
+)
+(vvPair
+variable "unit"
+value "IPBusInterface"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "symbol"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 222,0
+optionalChildren [
+*91 (SymbolBody
+uid 8,0
+optionalChildren [
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+uid 74,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+fg "0,65535,0"
+)
+xt "4250,22625,5000,23375"
+)
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+)
+xt "6000,22550,13000,23450"
+st "gmii_rx_clk_i"
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+tm "CptPortNameMgr"
+)
+)
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+)
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+)
+thePort (LogicalPort
+decl (Decl
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+o 1
+suid 2,0
+)
+)
+)
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+)
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+)
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+)
+xt "6000,25550,12500,26450"
+st "gmii_rx_dv_i"
+blo "6000,26250"
+tm "CptPortNameMgr"
+)
+)
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+font "courier,8,0"
+)
+xt "32000,3500,51500,4400"
+st "gmii_rx_dv_i : IN std_logic ;"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 2
+suid 3,0
+)
+)
+)
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+uid 85,0
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+)
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+)
+tg (CPTG
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+)
+xt "6000,28550,12500,29450"
+st "gmii_rx_er_i"
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+tm "CptPortNameMgr"
+)
+)
+dt (MLText
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+)
+xt "32000,4400,51500,5300"
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+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 3
+suid 4,0
+)
+)
+)
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 90,0
+ro 90
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+fg "0,65535,0"
+)
+xt "4250,31625,5000,32375"
+)
+tg (CPTG
+uid 91,0
+ps "CptPortTextPlaceStrategy"
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+)
+xt "6000,31550,15500,32450"
+st "gmii_rxd_i : (7:0)"
+blo "6000,32250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 93,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,5300,61000,6200"
+st "gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0) ;"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 4
+suid 5,0
+)
+)
+)
+*96 (CptPort
+uid 94,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 95,0
+ro 90
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+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,21625,38750,22375"
+)
+tg (CPTG
+uid 96,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 97,0
+va (VaSet
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+)
+xt "30500,21550,37000,22450"
+st "gmii_tx_en_o"
+ju 2
+blo "37000,22250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 98,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,10700,51500,11600"
+st "gmii_tx_en_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 10
+suid 6,0
+)
+)
+)
+*97 (CptPort
+uid 99,0
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+uid 100,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,23625,38750,24375"
+)
+tg (CPTG
+uid 101,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
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+va (VaSet
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+)
+xt "30500,23550,37000,24450"
+st "gmii_tx_er_o"
+ju 2
+blo "37000,24250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 103,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,11600,51500,12500"
+st "gmii_tx_er_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 11
+suid 7,0
+)
+)
+)
+*98 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 105,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,26625,38750,27375"
+)
+tg (CPTG
+uid 106,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 107,0
+va (VaSet
+font "courier,8,0"
+)
+xt "27500,26550,37000,27450"
+st "gmii_txd_o : (7:0)"
+ju 2
+blo "37000,27250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 108,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,12500,61000,13400"
+st "gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0) ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 12
+suid 8,0
+)
+)
+)
+*99 (CptPort
+uid 109,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
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+fg "0,65535,0"
+)
+xt "38000,28625,38750,29375"
+)
+tg (CPTG
+uid 111,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 112,0
+va (VaSet
+font "courier,8,0"
+)
+xt "31500,28550,37000,29450"
+st "phy_rstb_o"
+ju 2
+blo "37000,29250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 113,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,17000,51500,17900"
+st "phy_rstb_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 17
+suid 10,0
+)
+)
+)
+*100 (CptPort
+uid 114,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,30625,38750,31375"
+)
+tg (CPTG
+uid 116,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 117,0
+va (VaSet
+font "courier,8,0"
+)
+xt "29500,30550,37000,31450"
+st "gmii_gtx_clk_o"
+ju 2
+blo "37000,31250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 118,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,9800,51500,10700"
+st "gmii_gtx_clk_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 9
+suid 1,0
+)
+)
+)
+*101 (CptPort
+uid 119,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 120,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "4250,34625,5000,35375"
+)
+tg (CPTG
+uid 121,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 122,0
+va (VaSet
+font "courier,8,0"
+)
+xt "6000,34550,11500,35450"
+st "sysclk_n_i"
+blo "6000,35250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 123,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,7100,51500,8000"
+st "sysclk_n_i : IN std_logic ;"
+)
+thePort (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+o 6
+suid 12,0
+)
+)
+)
+*102 (CptPort
+uid 124,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 125,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "4250,37625,5000,38375"
+)
+tg (CPTG
+uid 126,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 127,0
+va (VaSet
+font "courier,8,0"
+)
+xt "6000,37550,11500,38450"
+st "sysclk_p_i"
+blo "6000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 128,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,8000,63500,8900"
+st "sysclk_p_i : IN std_logic ; -- ! 200 MHz xtal clock"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+eolc "! 200 MHz xtal clock"
+o 7
+suid 13,0
+)
+)
+)
+*103 (CptPort
+uid 202,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 203,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,32625,38750,33375"
+)
+tg (CPTG
+uid 204,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 205,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,32550,37000,33450"
+st "ipb_clk_o"
+ju 2
+blo "37000,33250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 206,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,13400,65000,14300"
+st "ipb_clk_o : OUT std_logic ; -- ! IPBus clock to slaves"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_clk_o"
+t "std_logic"
+eolc "! IPBus clock to slaves"
+o 13
+suid 14,0
+)
+)
+)
+*104 (CptPort
+uid 207,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 208,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,35625,38750,36375"
+)
+tg (CPTG
+uid 209,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 210,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,35550,37000,36450"
+st "ipb_rst_o"
+ju 2
+blo "37000,36250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 211,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,14300,65000,15200"
+st "ipb_rst_o : OUT std_logic ; -- ! IPBus reset to slaves"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_rst_o"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 14
+suid 15,0
+)
+)
+)
+*105 (CptPort
+uid 212,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 213,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,37625,38750,38375"
+)
+tg (CPTG
+uid 214,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 215,0
+va (VaSet
+font "courier,8,0"
+)
+xt "22000,37550,37000,38450"
+st "ipbw_o : (NUM_EXT_SLAVES-1:0)"
+ju 2
+blo "37000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 216,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,15200,79500,16100"
+st "ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0) ; -- ! IBus write signals"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbw_o"
+t "ipb_wbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IBus write signals"
+o 15
+suid 16,0
+)
+)
+)
+*106 (CptPort
+uid 217,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 218,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "4250,40625,5000,41375"
+)
+tg (CPTG
+uid 219,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 220,0
+va (VaSet
+font "courier,8,0"
+)
+xt "6000,40550,21000,41450"
+st "ipbr_i : (NUM_EXT_SLAVES-1:0)"
+blo "6000,41250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 221,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,6200,79500,7100"
+st "ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0) ; -- ! IPBus read signals"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbr_i"
+t "ipb_rbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IPBus read signals"
+o 5
+suid 19,0
+)
+)
+)
+*107 (CptPort
+uid 287,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 288,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,39625,38750,40375"
+)
+tg (CPTG
+uid 289,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 290,0
+va (VaSet
+font "courier,8,0"
+)
+xt "33500,39550,37000,40450"
+st "onehz_o"
+ju 2
+blo "37000,40250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 291,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,16100,51500,17000"
+st "onehz_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "onehz_o"
+t "std_logic"
+o 16
+suid 22,0
+)
+)
+)
+*108 (CptPort
+uid 292,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 293,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,42625,38750,43375"
+)
+tg (CPTG
+uid 294,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 295,0
+va (VaSet
+font "courier,8,0"
+)
+xt "29000,42550,37000,43450"
+st "clocks_locked_o"
+ju 2
+blo "37000,43250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 296,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,8900,51500,9800"
+st "clocks_locked_o : OUT std_logic ;"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "clocks_locked_o"
+t "std_logic"
+o 8
+suid 23,0
+)
+)
+)
+*109 (CptPort
+uid 308,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 309,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "4250,43625,5000,44375"
+)
+tg (CPTG
+uid 310,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 311,0
+va (VaSet
+font "courier,8,0"
+)
+xt "6000,43550,16500,44450"
+st "dip_switch_i : (3:0)"
+blo "6000,44250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 312,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,17900,61000,18800"
+st "dip_switch_i : IN std_logic_vector (3 DOWNTO 0) ;"
+)
+thePort (LogicalPort
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 18
+suid 25,0
+)
+)
+)
+*110 (CptPort
+uid 386,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 387,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "38000,44625,38750,45375"
+)
+tg (CPTG
+uid 388,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 389,0
+va (VaSet
+font "courier,8,0"
+)
+xt "28500,44550,37000,45450"
+st "clk_logic_xtal_o"
+ju 2
+blo "37000,45250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 390,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32000,18800,50500,19700"
+st "clk_logic_xtal_o : OUT std_logic "
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "clk_logic_xtal_o"
+t "std_logic"
+o 19
+suid 26,0
+)
+)
+)
+]
+shape (Rectangle
+uid 9,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "5000,21000,38000,46000"
+)
+oxt "20000,19000,49000,39000"
+biTextGroup (BiTextGroup
+uid 10,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (Text
+uid 11,0
+va (VaSet
+font "courier,8,1"
+)
+xt "14750,32100,16750,33000"
+st "work"
+blo "14750,32800"
+)
+second (Text
+uid 12,0
+va (VaSet
+font "courier,8,1"
+)
+xt "14750,33000,22250,33900"
+st "IPBusInterface"
+blo "14750,33700"
+)
+)
+gi *111 (GenericInterface
+uid 13,0
+ps "CenterOffsetStrategy"
+matrix (Matrix
+uid 14,0
+text (MLText
+uid 15,0
+va (VaSet
+font "courier,8,0"
+)
+xt "13000,19300,27000,22000"
+st "Generic Declarations
+
+NUM_EXT_SLAVES positive 5 "
+)
+header "Generic Declarations"
+showHdrWhenContentsEmpty 1
+)
+elements [
+(GiElement
+name "NUM_EXT_SLAVES"
+type "positive"
+value "5"
+)
+]
+)
+portInstanceVisAsIs 1
+portInstanceVis (PortSigDisplay
+sIVOD 1
+)
+portVis (PortSigDisplay
+sIVOD 1
+)
+)
+*112 (Grouping
+uid 16,0
+optionalChildren [
+*113 (CommentText
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+shape (Rectangle
+uid 19,0
+sl 0
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+vasetType 1
+fg "65280,65280,46080"
+)
+xt "32000,50000,49000,51000"
+)
+oxt "18000,70000,35000,71000"
+text (MLText
+uid 20,0
+va (VaSet
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+bg "0,0,32768"
+font "courier,8,0"
+)
+xt "32200,50050,44200,50950"
+st "
+by %user on %dd %month %year
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 1000
+visibleWidth 17000
+)
+position 1
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_arrivaltimelut._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_arrivaltimelut._epf
new file mode 100755
index 0000000000000000000000000000000000000000..a299428c671141716c31e1d143ea9437baf203b9
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_arrivaltimelut._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom arrivalTimeLUT_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_clocks_s6_extphy._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_clocks_s6_extphy._epf
new file mode 100755
index 0000000000000000000000000000000000000000..dfa7ad18628c37f01c01d4a4d835a0b2e810c75d
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_clocks_s6_extphy._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom clocks_s6_extphy.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dualserdes_1to4._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dualserdes_1to4._epf
new file mode 100755
index 0000000000000000000000000000000000000000..6cf3d0b013748d9a575990efee1aad59076eec18
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dualserdes_1to4._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom dualSERDES_1to4_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dutinterfaces._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dutinterfaces._epf
new file mode 100755
index 0000000000000000000000000000000000000000..9539d765d3509a80c2a5c2e88543638c8b560f6a
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_dutinterfaces._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom DUTInterfaces_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventbuffer._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventbuffer._epf
new file mode 100755
index 0000000000000000000000000000000000000000..c3baf18f6cca5669f7456bd63fce9ba36410912c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventbuffer._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom eventBuffer_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventformatter._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventformatter._epf
new file mode 100755
index 0000000000000000000000000000000000000000..02462c3fc409b2d68444ece150b2c5b0d66c327d
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_eventformatter._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom eventFormatter_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_ipbusinterface._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_ipbusinterface._epf
new file mode 100755
index 0000000000000000000000000000000000000000..d9e2bc05d790acf0d8e74656b71fb6b192d4864f
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_ipbusinterface._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom IPBusInterface_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_logic_clocks._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_logic_clocks._epf
new file mode 100755
index 0000000000000000000000000000000000000000..54f29c789a1b3f9ff00459cc3cc1f2f1188238ae
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_logic_clocks._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom logic_clocks_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_top_extphy._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_top_extphy._epf
new file mode 100755
index 0000000000000000000000000000000000000000..b60e62e0af4636c81039b3cb238758b3d273a71f
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_top_extphy._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom struct
+DEFAULT_FILE atom top_extphy/struct.bd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerinputs._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerinputs._epf
new file mode 100755
index 0000000000000000000000000000000000000000..419d0f1be69c7c3c2ea083920b2f3d68ccd7b0a2
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerinputs._epf
@@ -0,0 +1,2 @@
+DEFAULT_ARCHITECTURE atom rtl
+DEFAULT_FILE atom triggerInputs_rtl.vhd
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerlogic._epf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerlogic._epf
new file mode 100755
index 0000000000000000000000000000000000000000..41217221c73acd615365663a6ff1b69be0f9eff9
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/_triggerlogic._epf
@@ -0,0 +1,2 @@
+DEFAULT_FILE atom triggerLogic_rtl.vhd
+DEFAULT_ARCHITECTURE atom rtl
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/fsm.sm b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/fsm.sm
new file mode 100644
index 0000000000000000000000000000000000000000..7002c46296826af9ec3c3ee3ffcdfdc976757440
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/fsm.sm
@@ -0,0 +1,6443 @@
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+)
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+(vvPair
+variable "SideDataUserDir"
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+(vvPair
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+(vvPair
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..9d62c765f81e00775b7e306262dec96ffb875afb
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arp/struct.bd
@@ -0,0 +1,10879 @@
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+)
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
+actions (TextAssociate
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+)
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
+)
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+)
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+)
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+)
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+)
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+va (VaSet
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+font "courier,8,0"
+)
+xt "35200,6200,51900,10700"
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+ (packet_read_addr==6'd16)?(8'h8):
+ (packet_read_addr==6'd18)?(8'h6):
+ (packet_read_addr==6'd19)?(8'h4):
+ (packet_read_addr==6'd21)?(8'h1):
+ 8'h0;
+
+"
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+xt "15200,19200,32800,23700"
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+ (packet_read_addr==6'd39)?(myIP[23:16]):
+ (packet_read_addr==6'd40)?(myIP[15:8]):
+ myIP[7:0];
+
+"
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+xt "35200,-800,51900,3700"
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+assign resp_read_addr = (packet_out_addr==6'd00)?(6'd06):
+ (packet_out_addr==6'd01)?(6'd07):
+ (packet_out_addr==6'd02)?(6'd08):
+ (packet_out_addr==6'd03)?(6'd09):
+ (packet_out_addr==6'd04)?(6'd10):
+ (packet_out_addr==6'd05)?(6'd11):
+ (packet_out_addr==6'd32)?(6'd22):
+ (packet_out_addr==6'd33)?(6'd23):
+ (packet_out_addr==6'd34)?(6'd24):
+ (packet_out_addr==6'd35)?(6'd25):
+ (packet_out_addr==6'd36)?(6'd26):
+ (packet_out_addr==6'd37)?(6'd27):
+ (packet_out_addr==6'd38)?(6'd28):
+ (packet_out_addr==6'd39)?(6'd29):
+ (packet_out_addr==6'd40)?(6'd30):
+ (packet_out_addr==6'd41)?(6'd31):
+ packet_out_addr;
+
+"
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+assign resp_data= (packet_out_addr>=6'd00 && packet_out_addr<=6'd05)?packet_data:
+ (packet_out_addr==6'd06)?myMAC[47:40]:
+ (packet_out_addr==6'd07)?myMAC[39:32]:
+ (packet_out_addr==6'd08)?myMAC[31:24]:
+ (packet_out_addr==6'd09)?myMAC[23:16]:
+ (packet_out_addr==6'd10)?myMAC[15:8]:
+ (packet_out_addr==6'd11)?myMAC[7:0]:
+ (packet_out_addr==6'd12)?8'h08:
+ (packet_out_addr==6'd13)?8'h06:
+ (packet_out_addr==6'd14)?8'h00:
+ (packet_out_addr==6'd15)?8'h01:
+ (packet_out_addr==6'd16)?8'h08:
+ (packet_out_addr==6'd17)?8'h00:
+ (packet_out_addr==6'd18)?8'h06:
+ (packet_out_addr==6'd19)?8'h04:
+ (packet_out_addr==6'd20)?8'h00:
+ (packet_out_addr==6'd21)?8'h02:
+ (packet_out_addr==6'd22)?myMAC[47:40]:
+ (packet_out_addr==6'd23)?myMAC[39:32]:
+ (packet_out_addr==6'd24)?myMAC[31:24]:
+ (packet_out_addr==6'd25)?myMAC[23:16]:
+ (packet_out_addr==6'd26)?myMAC[15:8]:
+ (packet_out_addr==6'd27)?myMAC[7:0]:
+ (packet_out_addr==6'd28)?myIP[31:24]:
+ (packet_out_addr==6'd29)?myIP[23:16]:
+ (packet_out_addr==6'd30)?myIP[15:8]:
+ (packet_out_addr==6'd31)?myIP[7:0]:
+ packet_data;
+
+"
+tm "HdlTextMgr"
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+viewiconposition 0
+)
+*212 (Property
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+ptn "String"
+)
+*213 (Property
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+ptn "String"
+)
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+)
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+"26000,14000"
+"27000,14000"
+]
+)
+start &5
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+)
+xt "25000,13100,28500,14000"
+st "mac_clk"
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+)
+)
+on &6
+)
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+)
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+"27000,15000"
+]
+)
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+)
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+)
+)
+on &8
+)
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+va (VaSet
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+)
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+"26000,16000"
+"27000,16000"
+]
+)
+start &9
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+tg (WTG
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+stg "STSignalDisplayStrategy"
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+uid 60,0
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+)
+xt "23000,15100,29500,16000"
+st "packet_ready"
+blo "23000,15800"
+tm "WireNameMgr"
+)
+)
+on &10
+)
+*217 (Wire
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+ps "OnConnectorStrategy"
+shape (Circle
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+)
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+)
+)
+]
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+)
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+"19000,19000"
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+)
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+f (Text
+uid 88,0
+va (VaSet
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+)
+xt "16000,18100,22000,19000"
+st "packet_data"
+blo "16000,18800"
+tm "WireNameMgr"
+)
+)
+on &14
+)
+*219 (Wire
+uid 111,0
+shape (OrthoPolyLine
+uid 112,0
+va (VaSet
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+)
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+"7000,0"
+]
+)
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+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "3000,-900,5500,0"
+st "myMAC"
+blo "3000,-200"
+tm "WireNameMgr"
+)
+)
+on &18
+)
+*220 (Wire
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+optionalChildren [
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+ps "OnConnectorStrategy"
+shape (Circle
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+)
+xt "600,20600,1400,21400"
+radius 400
+)
+)
+]
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "-2000,3000,7000,31000"
+pts [
+"-2000,31000"
+"1000,31000"
+"1000,3000"
+"7000,3000"
+]
+)
+start &19
+end &208
+ss 0
+sat 32
+eat 1
+sty 1
+stc 0
+st 0
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 130,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "-1000,2100,1000,3000"
+st "myIP"
+blo "-1000,2800"
+tm "WireNameMgr"
+)
+)
+on &20
+)
+*222 (Wire
+uid 859,0
+shape (OrthoPolyLine
+uid 860,0
+va (VaSet
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+lineWidth 2
+)
+xt "25000,8000,39000,26000"
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..22b8eaad5ae95daead7c300a3dc981837a2eebc8
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t/symbol.sb
@@ -0,0 +1,1871 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+]
+libraryRefs [
+"ieee"
+]
+)
+version "25.1"
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+usingSuid 1
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+*10 (TypeColHdr
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+*11 (BoundsColHdr
+tm "BoundsColHdrMgr"
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+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
+*14 (LogPort
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+decl (Decl
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+o 1
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+)
+uid 82,0
+)
+*15 (LogPort
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+decl (Decl
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+eolc "--! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
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+o 2
+suid 2,0
+)
+)
+uid 84,0
+)
+*16 (LogPort
+port (LogicalPort
+decl (Decl
+n "deserialized_data_i"
+t "std_logic_vector"
+b "(8 DOWNTO 0)"
+eolc "-- Output from the two 4-bit deserializers, concatenated with most recent bit of previous clock cycle. Clocked by clk_4x_logic_i . bit-8 is the most recent data"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+)
+uid 86,0
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+*17 (LogPort
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+eolc "-- Position of rising edge w.r.t. 40MHz strobe. Clocked by clk_4x_logic_i"
+preAdd 0
+posAdd 0
+o 4
+suid 4,0
+)
+)
+uid 88,0
+)
+*18 (LogPort
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+posAdd 0
+o 6
+suid 5,0
+)
+)
+uid 90,0
+)
+*19 (LogPort
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+preAdd 0
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+o 7
+suid 6,0
+)
+)
+uid 92,0
+)
+*20 (LogPort
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+)
+)
+uid 177,0
+)
+*21 (LogPort
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+type 1
+)
+VExpander (VariableExpander
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+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
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+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrival@time@l@u@t"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/arrivalTimeLUT"
+)
+(vvPair
+variable "date"
+value "12/11/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "11"
+)
+(vvPair
+variable "entity_name"
+value "arrivalTimeLUT"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
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+variable "f_logical"
+value "symbol.sb"
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+variable "f_noext"
+value "symbol"
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+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
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+variable "library"
+value "work"
+)
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+variable "library_downstream_ISEPARInvoke"
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+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
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+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
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+(vvPair
+variable "mm"
+value "12"
+)
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+variable "module_name"
+value "arrivalTimeLUT"
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+(vvPair
+variable "month"
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+variable "package_name"
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+)
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+variable "project_name"
+value "fmc_mTLU"
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+variable "series"
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+variable "task_ADMS"
+value "<TBD>"
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+value "<TBD>"
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+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
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+variable "task_ModelSimPath"
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+variable "task_NC-SimPath"
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+)
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+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
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+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
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+variable "this_file"
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+variable "this_file_logical"
+value "symbol"
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+variable "time"
+value "10:37:01"
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+variable "unit"
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+)
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+variable "user"
+value "phdgc"
+)
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+variable "version"
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+)
+(vvPair
+variable "view"
+value "symbol"
+)
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+eolc "--! Rising edge active"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/clocks_s6_extphy/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/clocks_s6_extphy/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..9104dd3002d74480aaa8d0430bee1b6118978621
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/clocks_s6_extphy/rtl.bd
@@ -0,0 +1,5669 @@
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..a51a6a2a8f395327461b062287fd24ae8df98113
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4/symbol.sb
@@ -0,0 +1,1734 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
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+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "unisim"
+unitName "vcomponents"
+)
+]
+libraryRefs [
+"ieee"
+"unisim"
+]
+)
+version "25.1"
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+)
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+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
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+)
+*14 (LogPort
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+o 1
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+)
+)
+uid 108,0
+)
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+)
+)
+uid 110,0
+)
+*16 (LogPort
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+decl (Decl
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+t "std_logic"
+eolc "--! 4x fabric clock. e.g. 640MHz"
+o 3
+suid 3,0
+)
+)
+uid 112,0
+)
+*17 (LogPort
+port (LogicalPort
+decl (Decl
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+)
+)
+uid 114,0
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+)
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+)
+)
+uid 118,0
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+*20 (LogPort
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+VExpander (VariableExpander
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+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
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+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4/symbol.sb.info"
+)
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+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/dual@s@e@r@d@e@s_1to4"
+)
+(vvPair
+variable "d_logical"
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+)
+(vvPair
+variable "date"
+value "12/04/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "04"
+)
+(vvPair
+variable "entity_name"
+value "dualSERDES_1to4"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
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+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
+)
+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
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+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
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+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
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+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
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+variable "mm"
+value "12"
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+(vvPair
+variable "module_name"
+value "dualSERDES_1to4"
+)
+(vvPair
+variable "month"
+value "Dec"
+)
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+variable "month_long"
+value "December"
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+variable "p"
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+value "<Undefined Variable>"
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+variable "project_name"
+value "fmc_mTLU"
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+variable "series"
+value "HDL Designer Series"
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+variable "task_ADMS"
+value "<TBD>"
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+variable "task_DesignCompilerPath"
+value "<TBD>"
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+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
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+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
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+variable "task_NC-SimPath"
+value "<TBD>"
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+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
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+variable "task_QuestaSimPath"
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+variable "task_VCSPath"
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+variable "this_file_logical"
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+variable "time"
+value "12:08:24"
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+variable "unit"
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+variable "user"
+value "phdgc"
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+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "symbol"
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+variable "year"
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+variable "yy"
+value "12"
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eth_s6_gmii/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eth_s6_gmii/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..94c277ae4a21e45cf1beae01a220dac3b8afe716
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eth_s6_gmii/rtl.bd
@@ -0,0 +1,9881 @@
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+stg "VerticalLayoutStrategy"
+f (Text
+uid 902,0
+va (VaSet
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+)
+xt "51000,26550,60500,27450"
+st "clientemacpauseval"
+blo "51000,27250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clientemacpauseval"
+t "std_logic_vector"
+b "(15 downto 0)"
+preAdd 0
+posAdd 0
+o 18
+)
+)
+)
+*131 (CptPort
+uid 903,0
+ps "OnEdgeStrategy"
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+ro 90
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+vasetType 1
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+)
+xt "74000,15625,74750,16375"
+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 906,0
+va (VaSet
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+)
+xt "66000,15550,73000,16450"
+st "emacclientrxd"
+ju 2
+blo "73000,16250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxd"
+t "std_logic_vector"
+b "(7 downto 0)"
+preAdd 0
+posAdd 0
+o 19
+)
+)
+)
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+)
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+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 910,0
+va (VaSet
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+)
+xt "64500,16550,73000,17450"
+st "emacclientrxdvld"
+ju 2
+blo "73000,17250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxdvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 20
+)
+)
+)
+*133 (CptPort
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+uid 912,0
+ro 90
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+)
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+)
+tg (CPTG
+uid 913,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 914,0
+va (VaSet
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+)
+xt "62000,17550,73000,18450"
+st "emacclientrxgoodframe"
+ju 2
+blo "73000,18250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxgoodframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 21
+)
+)
+)
+*134 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 916,0
+ro 90
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+)
+xt "74000,18625,74750,19375"
+)
+tg (CPTG
+uid 917,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 918,0
+va (VaSet
+font "courier,8,0"
+)
+xt "62500,18550,73000,19450"
+st "emacclientrxbadframe"
+ju 2
+blo "73000,19250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxbadframe"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 22
+)
+)
+)
+*135 (CptPort
+uid 919,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 920,0
+ro 90
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+vasetType 1
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+)
+xt "74000,26625,74750,27375"
+)
+tg (CPTG
+uid 921,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 922,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64000,26550,73000,27450"
+st "emacclienttxstats"
+ju 2
+blo "73000,27250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclienttxstats"
+t "std_logic_vector"
+b "(31 downto 0)"
+preAdd 0
+posAdd 0
+o 23
+)
+)
+)
+*136 (CptPort
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+ps "OnEdgeStrategy"
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+vasetType 1
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+)
+xt "74000,27625,74750,28375"
+)
+tg (CPTG
+uid 925,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 926,0
+va (VaSet
+font "courier,8,0"
+)
+xt "62500,27550,73000,28450"
+st "emacclienttxstatsvld"
+ju 2
+blo "73000,28250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclienttxstatsvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 24
+)
+)
+)
+*137 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 928,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,28625,74750,29375"
+)
+tg (CPTG
+uid 929,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 930,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64000,28550,73000,29450"
+st "emacclientrxstats"
+ju 2
+blo "73000,29250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxstats"
+t "std_logic_vector"
+b "(27 downto 0)"
+preAdd 0
+posAdd 0
+o 25
+)
+)
+)
+*138 (CptPort
+uid 931,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 932,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,29625,74750,30375"
+)
+tg (CPTG
+uid 933,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 934,0
+va (VaSet
+font "courier,8,0"
+)
+xt "62500,29550,73000,30450"
+st "emacclientrxstatsvld"
+ju 2
+blo "73000,30250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "emacclientrxstatsvld"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 26
+)
+)
+)
+*139 (CptPort
+uid 935,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 936,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,33625,50000,34375"
+)
+tg (CPTG
+uid 937,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 938,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,33550,57500,34450"
+st "txgmiimiiclk"
+blo "51000,34250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "txgmiimiiclk"
+t "std_logic"
+prec "-- tieemacconfigvec: in std_logic_vector(67 downto 0);"
+preAdd 0
+posAdd 0
+o 27
+)
+)
+)
+*140 (CptPort
+uid 939,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 940,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,18625,50000,19375"
+)
+tg (CPTG
+uid 941,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 942,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,18550,57500,19450"
+st "rxgmiimiiclk"
+blo "51000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rxgmiimiiclk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 28
+)
+)
+)
+*141 (CptPort
+uid 943,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 944,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,30625,74750,31375"
+)
+tg (CPTG
+uid 945,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 946,0
+va (VaSet
+font "courier,8,0"
+)
+xt "67500,30550,73000,31450"
+st "speedis100"
+ju 2
+blo "73000,31250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "speedis100"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 29
+)
+)
+)
+*142 (CptPort
+uid 947,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 948,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,31625,74750,32375"
+)
+tg (CPTG
+uid 949,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 950,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66500,31550,73000,32450"
+st "speedis10100"
+ju 2
+blo "73000,32250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "speedis10100"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 30
+)
+)
+)
+*143 (CptPort
+uid 951,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 952,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,27625,50000,28375"
+)
+tg (CPTG
+uid 953,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 954,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,27550,54500,28450"
+st "hostclk"
+blo "51000,28250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostclk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 31
+)
+)
+)
+*144 (CptPort
+uid 955,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 956,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,28625,50000,29375"
+)
+tg (CPTG
+uid 957,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 958,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,28550,56500,29450"
+st "hostopcode"
+blo "51000,29250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostopcode"
+t "std_logic_vector"
+b "(1 downto 0)"
+preAdd 0
+posAdd 0
+o 32
+)
+)
+)
+*145 (CptPort
+uid 959,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 960,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,29625,50000,30375"
+)
+tg (CPTG
+uid 961,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 962,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,29550,54500,30450"
+st "hostreq"
+blo "51000,30250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostreq"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 33
+)
+)
+)
+*146 (CptPort
+uid 963,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 964,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,30625,50000,31375"
+)
+tg (CPTG
+uid 965,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 966,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,30550,57000,31450"
+st "hostmiimsel"
+blo "51000,31250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostmiimsel"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 34
+)
+)
+)
+*147 (CptPort
+uid 967,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 968,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,31625,50000,32375"
+)
+tg (CPTG
+uid 969,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 970,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,31550,55000,32450"
+st "hostaddr"
+blo "51000,32250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostaddr"
+t "std_logic_vector"
+b "(9 downto 0)"
+preAdd 0
+posAdd 0
+o 35
+)
+)
+)
+*148 (CptPort
+uid 971,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 972,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,32625,50000,33375"
+)
+tg (CPTG
+uid 973,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 974,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,32550,56500,33450"
+st "hostwrdata"
+blo "51000,33250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "hostwrdata"
+t "std_logic_vector"
+b "(31 downto 0)"
+preAdd 0
+posAdd 0
+o 36
+)
+)
+)
+*149 (CptPort
+uid 975,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 976,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,32625,74750,33375"
+)
+tg (CPTG
+uid 977,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 978,0
+va (VaSet
+font "courier,8,0"
+)
+xt "67000,32550,73000,33450"
+st "hostmiimrdy"
+ju 2
+blo "73000,33250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "hostmiimrdy"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 37
+)
+)
+)
+*150 (CptPort
+uid 979,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 980,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "74000,33625,74750,34375"
+)
+tg (CPTG
+uid 981,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 982,0
+va (VaSet
+font "courier,8,0"
+)
+xt "67500,33550,73000,34450"
+st "hostrddata"
+ju 2
+blo "73000,34250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "hostrddata"
+t "std_logic_vector"
+b "(31 downto 0)"
+preAdd 0
+posAdd 0
+o 38
+)
+)
+)
+*151 (CptPort
+uid 983,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 984,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "49250,33625,50000,34375"
+)
+tg (CPTG
+uid 985,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 986,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,33550,57500,34450"
+st "corehassgmii"
+blo "51000,34250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "corehassgmii"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 39
+)
+)
+)
+*152 (PortMapFrame
+uid 987,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 988,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "48000,12000,76000,37000"
+)
+portMapText (BiTextGroup
+uid 989,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 990,0
+va (VaSet
+font "courier,8,0"
+)
+xt "76000,37000,95000,46000"
+st "clientemactxd => txd,
+clientemactxdvld => txdvld,
+reset => rst,
+rxgmiimiiclk => rx_clk,
+txgmiimiiclk => clk125,
+emacclientrxbadframe => rxbadframe,
+emacclientrxd => rxd,
+emacclientrxdvld => rxdvld,
+emacclientrxgoodframe => rxgoodframe,
+emacclienttxack => txack,"
+)
+second (MLText
+uid 991,0
+va (VaSet
+font "courier,8,0"
+)
+xt "76000,46000,96700,64000"
+st "phyemacmdin => '0',
+clientemactxunderrun => '0',
+clientemactxifgdelay => (others => '0'),
+clientemacpausereq => '0',
+clientemacpauseval => (others => '0'),
+hostclk => hostbus_in.hostclk,
+hostopcode => hostbus_in.hostopcode,
+hostreq => hostbus_in.hostreq,
+hostmiimsel => hostbus_in.hostmiimsel,
+hostaddr => hostbus_in.hostaddr,
+hostwrdata => hostbus_in.hostwrdata,
+hostmiimrdy => hostbus_out.hostmiimrdy,
+hostrddata => hostbus_out.hostrddata,
+corehassgmii => '0',
+emacphytxen => tx_en_e,
+emacphytxer => tx_er_e,
+emacphytxd => txd_e,
+phyemacrxd => rxd_r,
+phyemacrxdv => rx_dv_r,
+phyemacrxer => rx_er_r"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 822,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "50000,14000,74000,35000"
+)
+ttg (MlTextGroup
+uid 823,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*153 (Text
+uid 824,0
+va (VaSet
+font "courier,8,1"
+)
+xt "57250,35000,63750,35900"
+st "fmc_mTLU_lib"
+blo "57250,35700"
+tm "BdLibraryNameMgr"
+)
+*154 (Text
+uid 825,0
+va (VaSet
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+)
+xt "57250,35900,66750,36800"
+st "soft_emac_gmii_4_5"
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+tm "CptNameMgr"
+)
+*155 (Text
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+va (VaSet
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+)
+xt "57250,36800,58750,37700"
+st "mac"
+blo "57250,37500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
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+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 828,0
+text (MLText
+uid 829,0
+va (VaSet
+font "courier,8,0"
+)
+xt "48250,14000,48250,14000"
+)
+header ""
+)
+elements [
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 830,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "50250,33250,51750,34750"
+iconName "UnknownFile.png"
+iconMaskName "UnknownFile.msk"
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*156 (SaComponent
+uid 1088,0
+optionalChildren [
+*157 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "114000,4625,114750,5375"
+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
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+va (VaSet
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+)
+xt "111500,4550,113000,5450"
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+ju 2
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+)
+)
+thePort (LogicalPort
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+decl (Decl
+n "cal"
+t "bit"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*158 (CptPort
+uid 1102,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1103,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,4625,106000,5375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1105,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,4550,108000,5450"
+st "ce"
+blo "107000,5250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ce"
+t "bit"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*159 (CptPort
+uid 1106,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1107,0
+ro 90
+va (VaSet
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+)
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+)
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+)
+]
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..b23df7f92bd11445fec50484c32fd7cad852ce30
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd
@@ -0,0 +1,2842 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "eventBuffer_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352824745"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventBuffer"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "eventBuffer"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "eventBuffer"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventBuffer/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:30"
+)
+(vvPair
+variable "unit"
+value "eventBuffer"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..11ef674d04c1416351c4bd4df87491fa32e50b87
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@buffer/symbol.sb
@@ -0,0 +1,2085 @@
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..4085d65e0c769f256b536e806ed061d010b2bd5b
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd
@@ -0,0 +1,2644 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "eventFormatter_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352820697"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventFormatter"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "eventFormatter"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "eventFormatter"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventFormatter/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:30"
+)
+(vvPair
+variable "unit"
+value "eventFormatter"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+optionalChildren [
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+uid 9,0
+shape (CompositeShape
+uid 10,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
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+uid 11,0
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+"-2000,1000"
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+stc 0
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+)
+xt "-12500,500,-5000,1400"
+st "clk_4x_logic_i"
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+blo "-5000,1200"
+tm "WireNameMgr"
+)
+)
+)
+*2 (Net
+uid 15,0
+lang 2
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
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+)
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+)
+uid 127,0
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+name "IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+uid 129,0
+)
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+name "NUM_TRIG_INPUTS"
+type "positive"
+value "4"
+)
+uid 131,0
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..15fa593834fd0097664a520a908cacd945049e3e
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb
@@ -0,0 +1,2935 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "fmcTLU"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+]
+libraryRefs [
+"ieee"
+]
+)
+version "25.1"
+appVersion "2012.1 (Build 6)"
+model (Symbol
+commonDM (CommonDM
+ldm (LogicalDM
+ordering 1
+suid 23,0
+usingSuid 1
+emptyRow *1 (LEmptyRow
+)
+uid 53,0
+optionalChildren [
+*2 (RefLabelRowHdr
+)
+*3 (TitleRowHdr
+)
+*4 (FilterRowHdr
+)
+*5 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*6 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*7 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*8 (NameColHdr
+tm "NameColHdrMgr"
+)
+*9 (ModeColHdr
+tm "ModeColHdrMgr"
+)
+*10 (TypeColHdr
+tm "TypeColHdrMgr"
+)
+*11 (BoundsColHdr
+tm "BoundsColHdrMgr"
+)
+*12 (InitColHdr
+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
+*14 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "--! goes high to load trigger data. One cycle of clk_4x_logic"
+posAdd 0
+o 5
+suid 1,0
+)
+)
+uid 108,0
+)
+*15 (LogPort
+port (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 2,0
+)
+)
+uid 110,0
+)
+*16 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+)
+uid 112,0
+)
+*17 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "data_strobe_o"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 19
+suid 4,0
+)
+)
+uid 114,0
+)
+*18 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_count_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 22
+suid 5,0
+)
+)
+uid 116,0
+)
+*19 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "trigger_times_i"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "Array of trigger times ( w.r.t. logic_strobe)"
+preAdd 0
+o 6
+suid 6,0
+)
+)
+uid 118,0
+)
+*20 (LogPort
+port (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "event_data_o"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 20
+suid 7,0
+)
+)
+uid 120,0
+)
+*21 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "goes high to reset counters. Synchronous with clk_4x_logic"
+o 4
+suid 9,0
+)
+)
+uid 263,0
+)
+*22 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "trigger_inputs_fired_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "high for each input that \"fired\""
+o 7
+suid 10,0
+)
+)
+uid 275,0
+)
+*23 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 14
+suid 11,0
+)
+)
+uid 366,0
+)
+*24 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 16
+suid 12,0
+)
+)
+uid 368,0
+)
+*25 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 13
+suid 13,0
+)
+)
+uid 370,0
+)
+*26 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 15
+suid 14,0
+)
+)
+uid 372,0
+)
+*27 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 15,0
+)
+)
+uid 374,0
+)
+*28 (LogPort
+port (LogicalPort
+lang 11
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+n "ipbus_i"
+t "ipb_wbus"
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+)
+)
+uid 376,0
+)
+*29 (LogPort
+port (LogicalPort
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+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
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+)
+)
+uid 378,0
+)
+*30 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 10
+suid 18,0
+)
+)
+uid 380,0
+)
+*31 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 9
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+)
+)
+uid 382,0
+)
+*32 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "spill_cnt_i"
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+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 12
+suid 20,0
+)
+)
+uid 384,0
+)
+*33 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 11
+suid 21,0
+)
+)
+uid 386,0
+)
+*34 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_TRIG_WIDTH-1 DOWNTO 0)"
+o 8
+suid 22,0
+)
+)
+uid 388,0
+)
+*35 (LogPort
+port (LogicalPort
+lang 11
+decl (Decl
+n "event_number_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 21
+suid 23,0
+)
+)
+uid 432,0
+)
+]
+)
+pdm (PhysicalDM
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+)
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+)
+genericsCommonDM (CommonDM
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+)
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+)
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+)
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+)
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+tm "GenericTypeColHdrMgr"
+)
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+)
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+tm "GenericPragmaColHdrMgr"
+)
+*82 (EolColHdr
+tm "GenericEolColHdrMgr"
+)
+*83 (LogGeneric
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+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "64"
+)
+uid 471,0
+)
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+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+uid 473,0
+)
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+name "g_COUNTER_TRIG_WIDTH"
+type "positive"
+value "32"
+)
+uid 475,0
+)
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+name "g_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+uid 477,0
+)
+*87 (LogGeneric
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+name "g_EVTTYPE_WIDTH"
+type "positive"
+value "4"
+e "-- Width of the event type word"
+)
+uid 479,0
+)
+*88 (LogGeneric
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+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "4"
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+apr 0
+e "-- Number of edge inputs"
+)
+uid 481,0
+)
+*89 (LogGeneric
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+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "5"
+e "-- Number of trigger inputs"
+)
+uid 483,0
+)
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+)
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+)
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+)
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+)
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+)
+]
+)
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+)
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventFormatter"
+)
+(vvPair
+variable "date"
+value "07/23/13"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "23"
+)
+(vvPair
+variable "entity_name"
+value "eventFormatter"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
+(vvPair
+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
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+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "07"
+)
+(vvPair
+variable "module_name"
+value "eventFormatter"
+)
+(vvPair
+variable "month"
+value "Jul"
+)
+(vvPair
+variable "month_long"
+value "July"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/event@formatter/symbol.sb"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/eventFormatter/symbol.sb"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
+variable "this_file"
+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "17:09:18"
+)
+(vvPair
+variable "unit"
+value "eventFormatter"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2012.1 (Build 6)"
+)
+(vvPair
+variable "view"
+value "symbol"
+)
+(vvPair
+variable "year"
+value "2013"
+)
+(vvPair
+variable "yy"
+value "13"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 51,0
+optionalChildren [
+*109 (SymbolBody
+uid 8,0
+optionalChildren [
+*110 (CptPort
+uid 122,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 123,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,19625,16000,20375"
+)
+tg (CPTG
+uid 124,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 125,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,19550,21500,20450"
+st "trigger_i"
+blo "17000,20250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 126,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,5600,55500,6500"
+st "trigger_i : IN std_logic ; --! goes high to load trigger data. One cycle of clk_4x_logic
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "--! goes high to load trigger data. One cycle of clk_4x_logic"
+posAdd 0
+o 5
+suid 1,0
+)
+)
+)
+*111 (CptPort
+uid 127,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 128,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,22625,16000,23375"
+)
+tg (CPTG
+uid 129,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 130,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,22550,24500,23450"
+st "clk_4x_logic_i"
+blo "17000,23250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 131,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,2000,36500,2900"
+st "clk_4x_logic_i : IN std_logic ; -- ! Rising edge active
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 2,0
+)
+)
+)
+*112 (CptPort
+uid 132,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 133,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,25625,16000,26375"
+)
+tg (CPTG
+uid 134,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 135,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,25550,24500,26450"
+st "logic_strobe_i"
+blo "17000,26250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 136,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,3800,51000,4700"
+st "logic_strobe_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+)
+)
+*113 (CptPort
+uid 137,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 138,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "68000,21625,68750,22375"
+)
+tg (CPTG
+uid 139,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 140,0
+va (VaSet
+font "courier,8,0"
+)
+xt "60000,21550,67000,22450"
+st "data_strobe_o"
+ju 2
+blo "67000,22250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 141,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,18200,52000,19100"
+st "data_strobe_o : OUT std_logic ; -- goes high when data ready to load into event buffer
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "data_strobe_o"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 19
+suid 4,0
+)
+)
+)
+*114 (CptPort
+uid 142,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 143,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "68000,28625,68750,29375"
+)
+tg (CPTG
+uid 144,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 145,0
+va (VaSet
+font "courier,8,0"
+)
+xt "48000,28550,67000,29450"
+st "trigger_count_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "67000,29250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 146,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,20900,40000,21800"
+st "trigger_count_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 DOWNTO 0)
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_count_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 22
+suid 5,0
+)
+)
+)
+*115 (CptPort
+uid 147,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 148,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,28625,16000,29375"
+)
+tg (CPTG
+uid 149,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 150,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,28550,38000,29450"
+st "trigger_times_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "17000,29250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 151,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,6500,68500,7400"
+st "trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ; -- Array of trigger times ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_times_i"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "Array of trigger times ( w.r.t. logic_strobe)"
+preAdd 0
+o 6
+suid 6,0
+)
+)
+)
+*116 (CptPort
+uid 152,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 153,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "68000,36625,68750,37375"
+)
+tg (CPTG
+uid 154,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 155,0
+va (VaSet
+font "courier,8,0"
+)
+xt "47000,36550,67000,37450"
+st "event_data_o : (g_EVENT_DATA_WIDTH-1:0)"
+ju 2
+blo "67000,37250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 156,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,19100,43500,20000"
+st "event_data_o : OUT std_logic_vector (g_EVENT_DATA_WIDTH-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "event_data_o"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 20
+suid 7,0
+)
+)
+)
+*117 (CptPort
+uid 270,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 271,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,32625,16000,33375"
+)
+tg (CPTG
+uid 272,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 273,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,32550,24000,33450"
+st "logic_reset_i"
+blo "17000,33250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 274,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,4700,55500,5600"
+st "logic_reset_i : IN std_logic ; -- goes high to reset counters. Synchronous with clk_4x_logic
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "goes high to reset counters. Synchronous with clk_4x_logic"
+o 4
+suid 9,0
+)
+)
+)
+*118 (CptPort
+uid 277,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 278,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,38625,16000,39375"
+)
+tg (CPTG
+uid 279,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 280,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,38550,41500,39450"
+st "trigger_inputs_fired_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "17000,39250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 281,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,7400,61000,8300"
+st "trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ; -- high for each input that \"fired\"
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_inputs_fired_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "high for each input that \"fired\""
+o 7
+suid 10,0
+)
+)
+)
+*119 (CptPort
+uid 306,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 307,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,39625,16000,40375"
+)
+tg (CPTG
+uid 308,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 309,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,39550,36000,40450"
+st "edge_fall_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "17000,40250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 310,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,13700,57000,14600"
+st "edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0) ; -- ! High when falling edge
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 14
+suid 11,0
+)
+)
+)
+*120 (CptPort
+uid 311,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 312,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,40625,16000,41375"
+)
+tg (CPTG
+uid 313,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 314,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,40550,38500,41450"
+st "edge_fall_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "17000,41250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 315,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,15500,67000,16400"
+st "edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0) ; -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 16
+suid 12,0
+)
+)
+)
+*121 (CptPort
+uid 316,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 317,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,41625,16000,42375"
+)
+tg (CPTG
+uid 318,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 319,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,41550,36000,42450"
+st "edge_rise_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "17000,42250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 320,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,12800,56500,13700"
+st "edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0) ; -- ! High when rising edge
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 13
+suid 13,0
+)
+)
+)
+*122 (CptPort
+uid 321,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 322,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,42625,16000,43375"
+)
+tg (CPTG
+uid 323,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 324,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,42550,38500,43450"
+st "edge_rise_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "17000,43250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 325,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,14600,67000,15500"
+st "edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0) ; -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 15
+suid 14,0
+)
+)
+)
+*123 (CptPort
+uid 326,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 327,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,43625,16000,44375"
+)
+tg (CPTG
+uid 328,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 329,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,43550,23000,44450"
+st "ipbus_clk_i"
+blo "17000,44250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 330,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,2900,24500,3800"
+st "ipbus_clk_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 15,0
+)
+)
+)
+*124 (CptPort
+uid 331,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 332,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,44625,16000,45375"
+)
+tg (CPTG
+uid 333,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 334,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,44550,20500,45450"
+st "ipbus_i"
+blo "17000,45250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 335,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,16400,24000,17300"
+st "ipbus_i : IN ipb_wbus ;
+"
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+preAdd 0
+o 17
+suid 16,0
+)
+)
+)
+*125 (CptPort
+uid 336,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 337,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "68000,37625,68750,38375"
+)
+tg (CPTG
+uid 338,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 339,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,37550,67000,38450"
+st "ipbus_o"
+ju 2
+blo "67000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 340,0
+va (VaSet
+font "courier,8,0"
+)
+xt "2000,17300,24000,18200"
+st "ipbus_o : OUT ipb_rbus ;
+"
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+o 18
+suid 17,0
+)
+)
+)
+*126 (CptPort
+uid 341,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 342,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "15250,45625,16000,46375"
+)
+tg (CPTG
+uid 343,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 344,0
+va (VaSet
+font "courier,8,0"
+)
+xt "17000,45550,36000,46450"
+st "shutter_cnt_i : (g_COUNTER_WIDTH-1:0)"
+blo "17000,46250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 345,0
+va (VaSet
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_rxpacketbuffer/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_rxpacketbuffer/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..10c3d437409611bbaf9390a485ebae9e184d8244
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_rxpacketbuffer/struct.bd
@@ -0,0 +1,6388 @@
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+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+"45500,13000"
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+)
+)
+)
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+)
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+)
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+"-2000,34000"
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+)
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+stg "STSignalDisplayStrategy"
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+)
+)
+)
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+)
+)
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+)
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+)
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+)
+)
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+posAdd 0
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+ro 90
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+st "clkb"
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+)
+)
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+posAdd 0
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+)
+)
+)
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+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
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+)
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+)
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+)
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+"
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+)
+)
+)
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+)
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+always @(posedge mac_clk) was_packetok<=mac_rxpacketok;
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+"
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_txpacketbuffer/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_txpacketbuffer/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..15cf1476a69539219c15cebe398abb2366422454
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/gbe_txpacketbuffer/struct.bd
@@ -0,0 +1,9718 @@
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+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "gbe_txpacketbuffer"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
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+variable "mm"
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+)
+(vvPair
+variable "module_name"
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+)
+(vvPair
+variable "month"
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+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
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+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
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+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
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+)
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+value "<TBD>"
+)
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+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
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+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
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+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "16:59:32"
+)
+(vvPair
+variable "unit"
+value "gbe_txpacketbuffer"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
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+// Company:
+// Engineer:
+//
+// Create Date: 08:57:35 01/07/2010
+// Design Name:
+// Module Name: gbe_packetbuffer
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
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+// Revision:
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+)
+)
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+)
+)
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+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
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+)
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+)
+)
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+)
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+)
+)
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+)
+)
+uid 600,0
+)
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+)
+)
+uid 602,0
+)
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+o 22
+suid 24,0
+)
+)
+uid 604,0
+)
+*349 (LeafLogPort
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+decl (Decl
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+suid 25,0
+)
+)
+uid 606,0
+)
+*350 (LeafLogPort
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+)
+)
+uid 608,0
+)
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+suid 27,0
+)
+)
+uid 610,0
+)
+]
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..dfa328189abe9bf0af913f53d5f97f96515f2c45
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd
@@ -0,0 +1,5417 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+language 1
+dialect 5
+dmPackageRefs [
+]
+instances [
+(Instance
+name "csum_icmp"
+duLibraryName "fmc_mTLU_lib"
+duName "ip_checksum_8bit"
+elements [
+]
+mwi 0
+uid 219,0
+)
+]
+embeddedInstances [
+(EmbeddedInstance
+name "eb1"
+number "1"
+)
+(EmbeddedInstance
+name "eb2"
+number "2"
+)
+(EmbeddedInstance
+name "eb3"
+number "3"
+)
+(EmbeddedInstance
+name "eb4"
+number "4"
+)
+(EmbeddedInstance
+name "eb5"
+number "5"
+)
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/icmp.v"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352727141"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "icmp"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "icmp"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/icmp/struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "16:59:31"
+)
+(vvPair
+variable "unit"
+value "icmp"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "Verilog2001LangMgr"
+optionalChildren [
+*1 (Net
+uid 11,0
+lang 5
+decl (Decl
+n "resp_read_addr"
+t "reg"
+b "[9:0]"
+prec "// to be worth responding to, HARDWARE = 0x0 0x1, PROTOCOL = 0x8 0x0,
+// HLEN = 0x6, PLEN=0x4, OPERATION = 0x0 0x1
+// TARGET IA = my IP
+
+ // wire [9:0] resp_read_addr;
+ // wire [7:0] resp_data;"
+preAdd 0
+o 1
+suid 2,0
+)
+declText (MLText
+uid 12,0
+va (VaSet
+font "courier,8,0"
+)
+xt "46000,57400,82000,63700"
+st "// to be worth responding to, HARDWARE = 0x0 0x1, PROTOCOL = 0x8 0x0,
+// HLEN = 0x6, PLEN=0x4, OPERATION = 0x0 0x1
+// TARGET IA = my IP
+
+ // wire [9:0] resp_read_addr;
+ // wire [7:0] resp_data;
+reg [9:0] resp_read_addr;
+"
+)
+)
+*2 (Net
+uid 13,0
+lang 5
+decl (Decl
+n "resp_data"
+t "reg"
+b "[7:0]"
+o 2
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+st ".clk(mac_clk),
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+.checksum(icmp_checksum),"
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+iconMaskName "VerilogFileViewIcon.msk"
+ftype 11
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+viewiconposition 0
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+assign in_icmp_addresses=(packet_out_addr>=10'd34);
+
+"
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+visibleWidth 17600
+)
+)
+)
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+//always @(posedge mac_clk)
+ assign icmp_csum_cond=(state==STATE_RESP_NEXT && in_icmp_addresses);
+
+"
+tm "HdlTextMgr"
+wrapOption 3
+visibleHeight 4600
+visibleWidth 17600
+)
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+)
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+always @(posedge mac_clk)
+ if (reset) begin
+ state<=STATE_IDLE;
+ checksum_toggle<=0;
+ packet_out_we<=0;
+ packet_xmit<=0;
+ done_with_packet<=0;
+ ICMP_type<=0;
+ reset_reg_out<=0;
+ reset_reg_int<=0;
+ end else case (state)
+
+ STATE_IDLE: if (packet_ready) begin
+ packet_read_addr<=10'd34; // check the type - 14(ethernet header length) + 20(IPv4 header assumed length)
+ packet_out_addr<=0;
+ checksum_toggle<=0;
+ packet_out_we<=0;
+ packet_xmit<=0;
+ packet_out_len<=10'h3ff;
+ done_with_packet<=0;
+ reset_reg_out<=0;
+ reset_reg_int<=0;
+ state<=STATE_CHECK0WAIT;
+ end
+
+ STATE_CHECK0WAIT :
+ state<=STATE_CHECK0; // one wait state
+
+ STATE_CHECK0 : begin
+ ICMP_type<=packet_data;
+ if (packet_data == 8'd08) begin // only handle ping!
+ state<=STATE_RESP_READSET;
+ end else if (packet_data == 8'd42) begin // and the \"unused\" #42!
+ state<=STATE_RESP_READSET;
+ end else state<=STATE_DONEFAIL;
+ end
+
+ STATE_RESP_READSET : begin // handle ping and the \"unused\" #42!
+ checksum_toggle<=0;
+ packet_read_addr<=resp_read_addr;
+ state<=STATE_RESP_READWAIT;
+ end
+
+ STATE_RESP_READWAIT : begin
+ state<=STATE_RESP_READWAIT2;
+ end
+
+ STATE_RESP_READWAIT2 : begin
+ state<=STATE_RESP_WE;
+ end
+
+ STATE_RESP_WE : begin
+ packet_out<=resp_data;
+ packet_out_we<=1;
+ if (packet_out_addr==10'd16) packet_out_len[9:8]<=packet_data[1:0];
+ else if (packet_out_addr==10'd17) packet_out_len[7:0]<=packet_data;
+ else if (packet_out_addr==10'd18) packet_out_len<=packet_out_len+14; // for the ethernet header
+
+ state<=STATE_RESP_NEXT;
+
+ if ( ICMP_type==8'd42 ) begin
+ if (packet_out_addr==10'd18)
+ if (packet_out_len!=10'd32)
+ state<=STATE_DONEFAIL;
+ else if (packet_out_addr==10'd42) reset_reg_int[31:24]<=packet_data;
+ else if (packet_out_addr==10'd43) reset_reg_int[23:16]<=packet_data;
+ else if (packet_out_addr==10'd44) reset_reg_int[15:8]<=packet_data;
+ else if (packet_out_addr==10'd45) reset_reg_int[7:0]<=packet_data;
+ end
+ end
+
+ STATE_RESP_NEXT : begin
+ packet_out_we<=0;
+ checksum_toggle<=1;
+ if (packet_out_addr>10'd18 && packet_out_addr==packet_out_len )
+ state<=STATE_ADDCHECKSUM0;
+ else begin
+ if (packet_out_addr==10'd35) packet_out_addr <= 10'd38;
+ else packet_out_addr<=packet_out_addr+1;
+ state<=STATE_RESP_READSET;
+ end
+ end
+
+ STATE_ADDCHECKSUM0 : begin
+ packet_out_addr<=10'd36;
+ packet_out<=icmp_checksum[15:8];
+ checksum_toggle<=0;
+ packet_out_we<=1;
+ state<=STATE_ADDCHECKSUM1;
+ end
+
+ STATE_ADDCHECKSUM1 : begin
+ packet_out_addr<=10'd37;
+ packet_out<=icmp_checksum[7:0];
+ packet_out_we<=1;
+ state<=STATE_ADDCHECKSUMDONE;
+ end
+
+ STATE_ADDCHECKSUMDONE : begin
+ packet_out_we<=0;
+ state<=STATE_DONEOK;
+ end
+
+ STATE_DONEFAIL : begin
+ done_with_packet<=1;
+ if (done_with_packet==0) state<=STATE_DONEFAIL;
+ else state<=STATE_PREIDLE;
+ end
+
+ STATE_DONEOK : begin
+ reset_reg_out<=reset_reg_int;
+ done_with_packet<=1;
+ packet_xmit<=1;
+ if (done_with_packet==0) state<=STATE_DONEOK;
+ else state<=STATE_PREIDLE;
+ end
+
+ STATE_PREIDLE : begin
+ done_with_packet<=0;
+ packet_xmit<=0;
+ if (done_with_packet==1) state<=STATE_PREIDLE;
+ else state<=STATE_IDLE;
+ end
+
+ endcase
+
+"
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+visibleHeight 4600
+visibleWidth 17600
+)
+)
+)
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+// this section sets the address of the input pointer, according to the address of the output pointer, in order to fill the ETHERNET and IPv4 headers
+// it does this by simply swapping the transmit/receive MAC addresses, copies the rest of the header and swaps the transmit/receive IP addresses
+// assign resp_read_addr = (packet_out_addr==10'd00)?(10'd06):// packet out 0 (MAC destination 0) <- packet in 6 (MAC source 0)
+ // (packet_out_addr==10'd01)?(10'd07):// packet out 1 (MAC destination 1) <- packet in 7 (MAC source 1)
+ // (packet_out_addr==10'd02)?(10'd08):// packet out 2 (MAC destination 2) <- packet in 8 (MAC source 2)
+ // (packet_out_addr==10'd03)?(10'd09):// packet out 3 (MAC destination 3) <- packet in 9 (MAC source 3)
+ // (packet_out_addr==10'd04)?(10'd10):// packet out 4 (MAC destination 4) <- packet in 10 (MAC source 4)
+ // (packet_out_addr==10'd05)?(10'd11):// packet out 5 (MAC destination 5) <- packet in 11 (MAC source 5)
+ // (packet_out_addr==10'd06)?(10'd00):// packet out 6 (MAC source 0) <- packet in 0 (MAC destination 0)
+ // (packet_out_addr==10'd07)?(10'd01):// packet out 7 (MAC source 1) <- packet in 1 (MAC destination 1)
+ // (packet_out_addr==10'd08)?(10'd02):// packet out 8 (MAC source 2) <- packet in 2 (MAC destination 2)
+ // (packet_out_addr==10'd09)?(10'd03):// packet out 9 (MAC source 3) <- packet in 3 (MAC destination 3)
+ // (packet_out_addr==10'd10)?(10'd04):// packet out 10 (MAC source 4) <- packet in 4 (MAC destination 4)
+ // (packet_out_addr==10'd11)?(10'd05):// packet out 11 (MAC source 5) <- packet in 5 (MAC destination 5)
+ // // .
+ // // . 12 through 25 are \"default\" making packet out 12 <- packet in 12
+ // // .
+ // // . these are:
+ // // . 12,13 = length
+ // // . 14 = IP version + header length
+ // // . 15 = IP type of service
+ // // . 16,17 = IP total length in bytes
+ // // . 18,19 = identification
+ // // . 20,21 = flags + fragment offset
+ // // . 22 = time to live
+ // // . 23 = protocol
+ // // . 24,25 = header checksum
+ // // .
+ // // . 12 through 25 are \"default\" making packet out 25 <- packet in 25
+ // // .
+ // (packet_out_addr==10'd26)?(10'd30):// packet out 26 (IPv4 destination 0) <- packet in 30 (IPv4 source 0)
+ // (packet_out_addr==10'd27)?(10'd31):// packet out 27 (IPv4 destination 1) <- packet in 31 (IPv4 source 1)
+ // (packet_out_addr==10'd28)?(10'd32):// packet out 28 (IPv4 destination 2) <- packet in 32 (IPv4 source 2)
+ // (packet_out_addr==10'd29)?(10'd33):// packet out 29 (IPv4 destination 3) <- packet in 33 (IPv4 source 3)
+ // (packet_out_addr==10'd30)?(10'd26):// packet out 30 (IPv4 source 0) <- packet in 26 (IPv4 destination 0)
+ // (packet_out_addr==10'd31)?(10'd27):// packet out 31 (IPv4 source 1) <- packet in 27 (IPv4 destination 1)
+ // (packet_out_addr==10'd32)?(10'd28):// packet out 32 (IPv4 source 2) <- packet in 28 (IPv4 destination 2)
+ // (packet_out_addr==10'd33)?(10'd29):// packet out 33 (IPv4 source 3) <- packet in 29 (IPv4 destination 3)
+ // (packet_out_addr); // for 34 and 35, this is irrelevant since the value is fixed, rather than using the location pointed to by the read pointer
+
+
+
+// this section sets the address of the input pointer, according to the address of the output pointer, in order to fill the ETHERNET and IPv4 headers
+// it does this by simply swapping the transmit/receive MAC addresses, copies the rest of the header and swaps the transmit/receive IP addresses
+always @ (packet_out_addr)
+ case (packet_out_addr)
+ 10'd00 :
+ // packet out 0 (MAC destination 0) <- packet in 6 (MAC source 0)
+ resp_read_addr = 10'd06;
+ 10'd01 :
+ // packet out 1 (MAC destination 1) <- packet in 7 (MAC source 1)
+ resp_read_addr = 10'd07;
+ 10'd02 :
+ // packet out 2 (MAC destination 2) <- packet in 8 (MAC source 2)
+ resp_read_addr = 10'd08;
+ 10'd03 :
+ // packet out 3 (MAC destination 3) <- packet in 9 (MAC source 3)
+ resp_read_addr = 10'd09;
+ 10'd04 :
+ // packet out 4 (MAC destination 4) <- packet in 10 (MAC source 4)
+ resp_read_addr = 10'd10;
+ 10'd05 :
+ // packet out 5 (MAC destination 5) <- packet in 11 (MAC source 5)
+ resp_read_addr = 10'd11;
+ 10'd06 :
+ // packet out 6 (MAC source 0) <- packet in 0 (MAC destination 0)
+ resp_read_addr = 10'd00;
+ 10'd07 :
+ // packet out 7 (MAC source 1) <- packet in 1 (MAC destination 1)
+ resp_read_addr = 10'd01;
+ 10'd08 :
+ // packet out 8 (MAC source 2) <- packet in 2 (MAC destination 2)
+ resp_read_addr = 10'd02;
+ 10'd09 :
+ // packet out 9 (MAC source 3) <- packet in 3 (MAC destination 3)
+ resp_read_addr = 10'd03;
+ 10'd10 :
+ // packet out 10 (MAC source 4) <- packet in 4 (MAC destination 4)
+ resp_read_addr = 10'd04;
+ 10'd11 :
+ // packet out 11 (MAC source 5) <- packet in 5 (MAC destination 5)
+ resp_read_addr = 10'd05;
+ // .
+ // . 12 through 25 are \"default\" making packet out 12 <- packet in 12
+ // .
+ // . these are:
+ // . 12,13 = length
+ // . 14 = IP version + header length
+ // . 15 = IP type of service
+ // . 16,17 = IP total length in bytes
+ // . 18,19 = identification
+ // . 20,21 = flags + fragment offset
+ // . 22 = time to live
+ // . 23 = protocol
+ // . 24,25 = header checksum
+ // .
+ // . 12 through 25 are \"default\" making packet out 25 <- packet in 25
+ // .
+ 10'd26 :
+ // packet out 26 (IPv4 destination 0) <- packet in 30 (IPv4 source 0)
+ resp_read_addr = 10'd30;
+ 10'd27 :
+ // packet out 27 (IPv4 destination 1) <- packet in 31 (IPv4 source 1)
+ resp_read_addr = 10'd31;
+ 10'd28 :
+ // packet out 28 (IPv4 destination 2) <- packet in 32 (IPv4 source 2)
+ resp_read_addr = 10'd32;
+ 10'd29 :
+ // packet out 29 (IPv4 destination 3) <- packet in 33 (IPv4 source 3)
+ resp_read_addr = 10'd33;
+ 10'd30 :
+ // packet out 30 (IPv4 source 0) <- packet in 26 (IPv4 destination 0)
+ resp_read_addr = 10'd26;
+ 10'd31 :
+ // packet out 31 (IPv4 source 1) <- packet in 27 (IPv4 destination 1)
+ resp_read_addr = 10'd27;
+ 10'd32 :
+ // packet out 32 (IPv4 source 2) <- packet in 28 (IPv4 destination 2)
+ resp_read_addr = 10'd28;
+ 10'd33 :
+ // packet out 33 (IPv4 source 3) <- packet in 29 (IPv4 destination 3)
+ resp_read_addr = 10'd29;
+ default :
+ // for 34 and 35, this is irrelevant since the value is fixed, rather than using the location pointed to by the read pointer
+ resp_read_addr = packet_out_addr;
+ endcase
+
+"
+tm "HdlTextMgr"
+wrapOption 3
+visibleHeight 4600
+visibleWidth 17600
+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+// // this section sets the data to be written to the location indicaterd by the output pointer
+// // if it is in the ICMP packet, it sets the type/code to 0 (ping reply)
+// // else, set the output value to the value of the location pointed to by the input pointer
+// assign resp_data = (packet_out_addr==10'd34)?(8'h0):// packet out 34 (ICMP type) <- 0 (ping reply)
+ // (packet_out_addr==10'd35)?(8'h0):// packet out 35 (ICMP code) <- 0 (ping reply)
+ // (packet_out_addr==10'd36)?(8'h0):// packet out 36 (checksum 0) <- 0
+ // (packet_out_addr==10'd37)?(8'h0):// packet out 37 (checksum 1) <- 0
+ // packet_data;
+
+
+
+
+// this section sets the data to be written to the location indicaterd by the output pointer
+// if it is in the ICMP packet, it sets the type/code to 0 (ping reply)
+// else, set the output value to the value of the location pointed to by the input pointer
+always @ (packet_out_addr , packet_data)
+ case (packet_out_addr)
+ 10'd34 :
+ // packet out 34 (ICMP type) <- 0 (ping reply)
+ resp_data = 8'h0;
+ 10'd35 :
+ // packet out 35 (ICMP code) <- 0 (ping reply)
+ resp_data = 8'h0;
+ 10'd36 :
+ // packet out 36 (checksum 0) <- 0
+ resp_data = 8'h0;
+ 10'd37 :
+ // packet out 37 (checksum 1) <- 0
+ resp_data = 8'h0;
+ default :
+ resp_data = packet_data;
+ endcase
+
+"
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+wrapOption 3
+visibleHeight 4600
+visibleWidth 17600
+)
+)
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_ctrl_udponly/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_ctrl_udponly/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..d9b72378644a2b08783917db172cfaa8dd8ef083
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_ctrl_udponly/rtl.bd
@@ -0,0 +1,15291 @@
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+duLibraryName "fmc_mTLU_lib"
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+name "ST_COPYHEADER"
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+name "trans"
+duLibraryName "fmc_mTLU_lib"
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+name "DocView"
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+(vvPair
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+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
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+(vvPair
+variable "d"
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+(vvPair
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+(vvPair
+variable "date"
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+)
+(vvPair
+variable "day"
+value "Tue"
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+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "ipbus_ctrl_udponly"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
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+(vvPair
+variable "group"
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+(vvPair
+variable "host"
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+(vvPair
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+variable "library"
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+(vvPair
+variable "library_downstream_HdsLintPlugin"
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+(vvPair
+variable "library_downstream_ModelSimCompiler"
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+(vvPair
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+)
+(vvPair
+variable "module_name"
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+(vvPair
+variable "month"
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+(vvPair
+variable "month_long"
+value "November"
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+variable "p"
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+)
+(vvPair
+variable "p_logical"
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+(vvPair
+variable "package_name"
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+)
+(vvPair
+variable "project_name"
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+variable "series"
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+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
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+(vvPair
+variable "task_LeonardoPath"
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+(vvPair
+variable "task_ModelSimPath"
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+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
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+variable "task_PrecisionRTLPath"
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+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:32"
+)
+(vvPair
+variable "unit"
+value "ipbus_ctrl_udponly"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
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+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
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+)
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+st "mac_addr"
+ju 2
+blo "106000,13200"
+tm "WireNameMgr"
+)
+)
+)
+*77 (Net
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+decl (Decl
+n "mac_addr"
+t "std_logic_vector"
+b "(47 downto 0)"
+o 62
+suid 62,0
+)
+declText (MLText
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+va (VaSet
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+)
+xt "20000,81400,44500,82300"
+st "mac_addr : std_logic_vector(47 downto 0)
+"
+)
+)
+*78 (PortIoIn
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+shape (CompositeShape
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+)
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+(Pentagon
+uid 315,0
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+ro 270
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+)
+(Line
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+ro 270
+xt "-2500,37000,-2000,37000"
+pts [
+"-2500,37000"
+"-2000,37000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
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+f (Text
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+va (VaSet
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+)
+xt "-8500,36500,-5000,37400"
+st "ip_addr"
+ju 2
+blo "-5000,37200"
+tm "WireNameMgr"
+)
+)
+)
+*79 (Net
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+decl (Decl
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+t "std_logic_vector"
+b "(31 downto 0)"
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+suid 63,0
+)
+declText (MLText
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+va (VaSet
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+)
+xt "20000,82300,44500,83200"
+st "ip_addr : std_logic_vector(31 downto 0)
+"
+)
+)
+*80 (SaComponent
+uid 367,0
+optionalChildren [
+*81 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
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+fg "0,65535,0"
+)
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+)
+tg (CPTG
+uid 379,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
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+)
+xt "114000,29550,117500,30450"
+st "mac_clk"
+blo "114000,30250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
+n "mac_clk"
+t "wire"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*82 (CptPort
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+)
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+)
+tg (CPTG
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+f (Text
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+)
+xt "120500,23550,124000,24450"
+st "mac_txd"
+ju 2
+blo "124000,24250"
+)
+)
+thePort (LogicalPort
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+m 1
+decl (Decl
+n "mac_txd"
+t "reg"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
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+)
+xt "125000,24625,125750,25375"
+)
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+f (Text
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+va (VaSet
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+)
+xt "120000,24550,124000,25450"
+st "mac_txdv"
+ju 2
+blo "124000,25250"
+)
+)
+thePort (LogicalPort
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+m 1
+decl (Decl
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+t "reg"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
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+shape (Triangle
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+)
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+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "114000,23550,118500,24450"
+st "mac_txack"
+blo "114000,24250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+t "wire"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*85 (CptPort
+uid 393,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
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+vasetType 1
+fg "0,65535,0"
+)
+xt "112250,24625,113000,25375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
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+)
+xt "114000,24550,119500,25450"
+st "packet_txd"
+blo "114000,25250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
+n "packet_txd"
+t "wire"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
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+ps "OnEdgeStrategy"
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+)
+xt "112250,25625,113000,26375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "114000,25550,120000,26450"
+st "packet_addr"
+blo "114000,26250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
+n "packet_addr"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*87 (CptPort
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+shape (Triangle
+uid 402,0
+ro 90
+va (VaSet
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+)
+xt "112250,26625,113000,27375"
+)
+tg (CPTG
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+f (Text
+uid 404,0
+va (VaSet
+font "courier,8,0"
+)
+xt "114000,26550,119500,27450"
+st "packet_len"
+blo "114000,27250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_len"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*88 (CptPort
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+shape (Triangle
+uid 406,0
+ro 90
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+)
+xt "112250,27625,113000,28375"
+)
+tg (CPTG
+uid 407,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
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+va (VaSet
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+)
+xt "114000,27550,118500,28450"
+st "packet_we"
+blo "114000,28250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_we"
+t "wire"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*89 (CptPort
+uid 409,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 410,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "112250,28625,113000,29375"
+)
+tg (CPTG
+uid 411,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 412,0
+va (VaSet
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+)
+xt "114000,28550,120000,29450"
+st "packet_done"
+blo "114000,29250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_done"
+t "wire"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*90 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 414,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "112250,28625,113000,29375"
+)
+tg (CPTG
+uid 415,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 416,0
+va (VaSet
+font "courier,8,0"
+)
+xt "114000,28550,116500,29450"
+st "reset"
+blo "114000,29250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+t "wire"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
+*91 (PortMapFrame
+uid 2408,0
+ps "PortMapFrameStrategy"
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+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "111000,21000,127000,34000"
+)
+portMapText (BiTextGroup
+uid 2410,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 2411,0
+va (VaSet
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+)
+xt "127000,34000,139000,38500"
+st "mac_clk => mac_txclk,
+mac_txack => mac_txack,
+reset => rst_macclk,
+mac_txd => mac_txd,
+mac_txdv => mac_txdvld,"
+)
+second (MLText
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+va (VaSet
+font "courier,8,0"
+)
+xt "127000,38500,141500,43000"
+st "packet_txd => packet_txd,
+packet_addr => packet_txa,
+packet_len => packet_txlen,
+packet_we => packet_txwe,
+packet_done => packet_txdone"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 368,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "113000,23000,125000,32000"
+)
+ttg (MlTextGroup
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+stg "VerticalLayoutStrategy"
+textVec [
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+va (VaSet
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+)
+xt "114250,32000,120750,32900"
+st "fmc_mTLU_lib"
+blo "114250,32700"
+tm "BdLibraryNameMgr"
+)
+*93 (Text
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+va (VaSet
+font "courier,8,1"
+)
+xt "114250,32900,123750,33800"
+st "gbe_txpacketbuffer"
+blo "114250,33600"
+tm "CptNameMgr"
+)
+*94 (Text
+uid 372,0
+va (VaSet
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+)
+xt "114250,33800,116750,34700"
+st "txbuf"
+blo "114250,34500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
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+ps "EdgeToEdgeStrategy"
+matrix (Matrix
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+text (MLText
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+)
+xt "111250,19400,122350,23000"
+st "ST_IDLE = 2'h0
+ST_FIRSTBYTE = 2'h1
+ST_WAITSTART = 2'h2
+ST_BYTES = 2'h3
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "ST_IDLE"
+value "2'h0"
+)
+(GiElement
+name "ST_FIRSTBYTE"
+value "2'h1"
+)
+(GiElement
+name "ST_WAITSTART"
+value "2'h2"
+)
+(GiElement
+name "ST_BYTES"
+value "2'h3"
+)
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 376,0
+sl 0
+va (VaSet
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+fg "49152,49152,49152"
+)
+xt "113250,30250,114750,31750"
+iconName "VerilogFileViewIcon.png"
+iconMaskName "VerilogFileViewIcon.msk"
+ftype 11
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+sF 0
+)
+archFileType "UNKNOWN"
+)
+*95 (SaComponent
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+)
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+)
+tg (CPTG
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+)
+xt "35000,46550,38500,47450"
+st "mac_rxd"
+blo "35000,47250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+b "[7:0]"
+preAdd 0
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+o 1
+)
+)
+)
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+)
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+)
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+f (Text
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+va (VaSet
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+)
+xt "35000,47550,39000,48450"
+st "mac_rxdv"
+blo "35000,48250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
+n "mac_rxdv"
+t "wire"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
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+ps "OnEdgeStrategy"
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+)
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+)
+tg (CPTG
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+f (Text
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+)
+xt "35000,51550,37500,52450"
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+blo "35000,52250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+posAdd 0
+o 3
+)
+)
+)
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+)
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+)
+tg (CPTG
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+)
+xt "35000,48550,42500,49450"
+st "mac_rxpacketok"
+blo "35000,49250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "mac_rxpacketok"
+t "wire"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*100 (CptPort
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+)
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+)
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+)
+xt "35000,49550,43000,50450"
+st "mac_rxpacketbad"
+blo "35000,50250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+o 5
+)
+)
+)
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+)
+xt "33250,45625,34000,46375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
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+f (Text
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+va (VaSet
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+)
+xt "35000,45550,38500,46450"
+st "mac_clk"
+blo "35000,46250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "mac_clk"
+t "wire"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*102 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+vasetType 1
+fg "0,65535,0"
+)
+xt "33250,52625,34000,53375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 562,0
+va (VaSet
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+)
+xt "35000,52550,36500,53450"
+st "clk"
+blo "35000,53250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "clk"
+t "wire"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*103 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 564,0
+ro 90
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+)
+xt "52000,47625,52750,48375"
+)
+tg (CPTG
+uid 565,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 566,0
+va (VaSet
+font "courier,8,0"
+)
+xt "45500,47550,51000,48450"
+st "packet_rxd"
+ju 2
+blo "51000,48250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_rxd"
+t "wire"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*104 (CptPort
+uid 567,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 568,0
+ro 90
+va (VaSet
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+)
+xt "33250,50625,34000,51375"
+)
+tg (CPTG
+uid 569,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 570,0
+va (VaSet
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+)
+xt "35000,50550,40500,51450"
+st "packet_rxa"
+blo "35000,51250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_rxa"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*105 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+fg "0,65535,0"
+)
+xt "52000,48625,52750,49375"
+)
+tg (CPTG
+uid 573,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 574,0
+va (VaSet
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+)
+xt "45500,48550,51000,49450"
+st "packet_len"
+ju 2
+blo "51000,49250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_len"
+t "reg"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
+*106 (CptPort
+uid 575,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 576,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,49625,52750,50375"
+)
+tg (CPTG
+uid 577,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 578,0
+va (VaSet
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+)
+xt "43500,49550,51000,50450"
+st "packet_rxready"
+ju 2
+blo "51000,50250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_rxready"
+t "reg"
+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*107 (CptPort
+uid 579,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
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+fg "0,65535,0"
+)
+xt "33250,51625,34000,52375"
+)
+tg (CPTG
+uid 581,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 582,0
+va (VaSet
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+)
+xt "35000,51550,42000,52450"
+st "packet_rxdone"
+blo "35000,52250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_rxdone"
+t "wire"
+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*108 (PortMapFrame
+uid 2363,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 2364,0
+va (VaSet
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+)
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+)
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+)
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+mac_clk => mac_rxclk,
+mac_rxd => mac_rxd,
+mac_rxdv => mac_rxdvld,
+mac_rxpacketbad => mac_rxbadframe,
+mac_rxpacketok => mac_rxgoodframe,
+reset => rst_macclk,"
+)
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+)
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+packet_rxd => packet_rxd,
+packet_rxready => packet_rxready,
+packet_len => packet_rxl"
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+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+]
+)
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+)
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+)
+header ""
+)
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+]
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+)
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+)
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+iconMaskName "VerilogFileViewIcon.msk"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 20
+)
+)
+)
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+)
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+)
+tg (CPTG
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 23
+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 24
+)
+)
+)
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+ps "OnEdgeStrategy"
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+)
+xt "144250,18625,145000,19375"
+)
+tg (CPTG
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+)
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+)
+)
+thePort (LogicalPort
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+posAdd 0
+o 25
+)
+)
+)
+*138 (CptPort
+uid 921,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 922,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,19625,145000,20375"
+)
+tg (CPTG
+uid 923,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 924,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,19550,150500,20450"
+st "icmp_xmit"
+blo "146000,20250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "icmp_xmit"
+t "wire"
+preAdd 0
+posAdd 0
+o 26
+)
+)
+)
+*139 (CptPort
+uid 925,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 926,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,20625,145000,21375"
+)
+tg (CPTG
+uid 927,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 928,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,20550,150500,21450"
+st "icmp_done"
+blo "146000,21250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "icmp_done"
+t "wire"
+preAdd 0
+posAdd 0
+o 27
+)
+)
+)
+*140 (CptPort
+uid 929,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 930,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "160000,28625,160750,29375"
+)
+tg (CPTG
+uid 931,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 932,0
+va (VaSet
+font "courier,8,0"
+)
+xt "153500,28550,159000,29450"
+st "icmp_ready"
+ju 2
+blo "159000,29250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "icmp_ready"
+t "reg"
+preAdd 0
+posAdd 0
+o 28
+)
+)
+)
+*141 (CptPort
+uid 933,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 934,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,21625,145000,22375"
+)
+tg (CPTG
+uid 935,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 936,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,21550,149500,22450"
+st "udp_rxa"
+blo "146000,22250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_rxa"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 29
+)
+)
+)
+*142 (CptPort
+uid 937,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 938,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,22625,145000,23375"
+)
+tg (CPTG
+uid 939,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 940,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,22550,149500,23450"
+st "udp_txa"
+blo "146000,23250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_txa"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 30
+)
+)
+)
+*143 (CptPort
+uid 941,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 942,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,23625,145000,24375"
+)
+tg (CPTG
+uid 943,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 944,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,23550,149500,24450"
+st "udp_len"
+blo "146000,24250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_len"
+t "wire"
+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 31
+)
+)
+)
+*144 (CptPort
+uid 945,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 946,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,24625,145000,25375"
+)
+tg (CPTG
+uid 947,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 948,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,24550,149500,25450"
+st "udp_txd"
+blo "146000,25250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_txd"
+t "wire"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 32
+)
+)
+)
+*145 (CptPort
+uid 949,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 950,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,25625,145000,26375"
+)
+tg (CPTG
+uid 951,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 952,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,25550,149000,26450"
+st "udp_we"
+blo "146000,26250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_we"
+t "wire"
+preAdd 0
+posAdd 0
+o 33
+)
+)
+)
+*146 (CptPort
+uid 953,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 954,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,26625,145000,27375"
+)
+tg (CPTG
+uid 955,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 956,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,26550,150000,27450"
+st "udp_xmit"
+blo "146000,27250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_xmit"
+t "wire"
+preAdd 0
+posAdd 0
+o 34
+)
+)
+)
+*147 (CptPort
+uid 957,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 958,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,27625,145000,28375"
+)
+tg (CPTG
+uid 959,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 960,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,27550,150000,28450"
+st "udp_done"
+blo "146000,28250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_done"
+t "wire"
+preAdd 0
+posAdd 0
+o 35
+)
+)
+)
+*148 (CptPort
+uid 961,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 962,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,28625,145000,29375"
+)
+tg (CPTG
+uid 963,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 964,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,28550,152500,29450"
+st "udp_xmit_req"
+blo "146000,29250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_xmit_req"
+t "wire"
+preAdd 0
+posAdd 0
+o 36
+)
+)
+)
+*149 (CptPort
+uid 965,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 966,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "144250,29625,145000,30375"
+)
+tg (CPTG
+uid 967,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 968,0
+va (VaSet
+font "courier,8,0"
+)
+xt "146000,29550,150500,30450"
+st "udp_space"
+blo "146000,30250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "udp_space"
+t "wire"
+preAdd 0
+posAdd 0
+o 37
+)
+)
+)
+*150 (CptPort
+uid 969,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 970,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "160000,10625,160750,11375"
+)
+tg (CPTG
+uid 971,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 972,0
+va (VaSet
+font "courier,8,0"
+)
+xt "154500,10550,159000,11450"
+st "udp_ready"
+ju 2
+blo "159000,11250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "udp_ready"
+t "reg"
+preAdd 0
+posAdd 0
+o 38
+)
+)
+)
+*151 (CptPort
+uid 973,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 974,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "160000,11625,160750,12375"
+)
+tg (CPTG
+uid 975,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 976,0
+va (VaSet
+font "courier,8,0"
+)
+xt "153000,11550,159000,12450"
+st "udp_xmit_ok"
+ju 2
+blo "159000,12250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "udp_xmit_ok"
+t "reg"
+preAdd 0
+posAdd 0
+o 39
+)
+)
+)
+*152 (PortMapFrame
+uid 977,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 978,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "143000,1000,162000,34000"
+)
+portMapText (BiTextGroup
+uid 979,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 980,0
+va (VaSet
+font "courier,8,0"
+)
+xt "162000,34000,175000,38500"
+st "clk => mac_txclk,
+ip => ip_addr,
+reset => rst_macclk,
+arp_ready => arp_ready,
+icmp_ready => icmp_ready,"
+)
+second (MLText
+uid 981,0
+va (VaSet
+font "courier,8,0"
+)
+xt "162000,38500,177000,69100"
+st "arp_len => \"101010\",
+icmp_txd => icmp_txd,
+icmp_done => icmp_done,
+icmp_rxa => icmp_rxa,
+icmp_txa => icmp_txa,
+icmp_len => icmp_len,
+icmp_we => icmp_we,
+icmp_xmit => icmp_xmit,
+arp_rxa => arp_rxa,
+arp_txa => arp_txa,
+arp_xmit => arp_xmit,
+arp_done => arp_done,
+arp_txd => arp_txd,
+arp_we => arp_we,
+udp_ready => udp_ready,
+udp_xmit_ok => udp_xmit_ok,
+rxa => packet_rxa,
+rx_done => packet_rxdone,
+txd => packet_txd,
+tx_len => packet_txlen,
+txa => packet_txa,
+tx_we => packet_txwe,
+tx_done => packet_txdone,
+udp_space => udp_space,
+udp_xmit_req => udp_xmit_req,
+udp_rxa => udp_rxa,
+udp_xmit => udp_xmit,
+udp_done => udp_done,
+udp_txa => udp_txa,
+udp_len => udp_len,
+udp_txd => udp_txd,
+udp_we => udp_we,
+rxd => packet_rxd,
+rx_ready => packet_rxready"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 812,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "145000,3000,160000,32000"
+)
+ttg (MlTextGroup
+uid 813,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*153 (Text
+uid 814,0
+va (VaSet
+font "courier,8,1"
+)
+xt "148750,32000,155250,32900"
+st "fmc_mTLU_lib"
+blo "148750,32700"
+tm "BdLibraryNameMgr"
+)
+*154 (Text
+uid 815,0
+va (VaSet
+font "courier,8,1"
+)
+xt "148750,32900,156250,33800"
+st "packet_handler"
+blo "148750,33600"
+tm "CptNameMgr"
+)
+*155 (Text
+uid 816,0
+va (VaSet
+font "courier,8,1"
+)
+xt "148750,33800,152250,34700"
+st "handler"
+blo "148750,34500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 817,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 818,0
+text (MLText
+uid 819,0
+va (VaSet
+font "courier,8,0"
+)
+xt "144250,-16800,173850,3000"
+st "SRC_SELF = 2'h0
+SRC_ARP = 2'h1
+SRC_ICMP = 2'h2
+SRC_UDP = 2'h3
+ST_IDLE = 5'h00
+ST_WAITETH0 = 5'h01
+ST_ETH0 = 5'h02
+ST_ETH1 = 5'h03
+ST_ARP = 5'h04
+ST_IP0 = 5'h05
+ST_IP1 = 5'h06
+ST_IP2 = 5'h07
+ST_IP3 = 5'h08
+ST_IP = 5'h09
+ST_ICMP = 5'h0a
+ST_UDP = 5'h0b
+ST_UDP0 = 5'h0c
+ST_UDP1 = 5'h0d
+ST_PREDONE = 5'h1d
+ST_DONE = 5'h1e
+ST_UDP_XMIT = 5'h1f
+UDP_PORT_CTL = 16'hc351 --// Original JM definition d791;
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "SRC_SELF"
+value "2'h0"
+)
+(GiElement
+name "SRC_ARP"
+value "2'h1"
+)
+(GiElement
+name "SRC_ICMP"
+value "2'h2"
+)
+(GiElement
+name "SRC_UDP"
+value "2'h3"
+)
+(GiElement
+name "ST_IDLE"
+value "5'h00"
+)
+(GiElement
+name "ST_WAITETH0"
+value "5'h01"
+)
+(GiElement
+name "ST_ETH0"
+value "5'h02"
+)
+(GiElement
+name "ST_ETH1"
+value "5'h03"
+)
+(GiElement
+name "ST_ARP"
+value "5'h04"
+)
+(GiElement
+name "ST_IP0"
+value "5'h05"
+)
+(GiElement
+name "ST_IP1"
+value "5'h06"
+)
+(GiElement
+name "ST_IP2"
+value "5'h07"
+)
+(GiElement
+name "ST_IP3"
+value "5'h08"
+)
+(GiElement
+name "ST_IP"
+value "5'h09"
+)
+(GiElement
+name "ST_ICMP"
+value "5'h0a"
+)
+(GiElement
+name "ST_UDP"
+value "5'h0b"
+)
+(GiElement
+name "ST_UDP0"
+value "5'h0c"
+)
+(GiElement
+name "ST_UDP1"
+value "5'h0d"
+)
+(GiElement
+name "ST_PREDONE"
+value "5'h1d"
+)
+(GiElement
+name "ST_DONE"
+value "5'h1e"
+)
+(GiElement
+name "ST_UDP_XMIT"
+value "5'h1f"
+)
+(GiElement
+name "UDP_PORT_CTL"
+value "16'hc351"
+e "// Original JM definition d791;"
+)
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 820,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "145250,30250,146750,31750"
+iconName "VerilogFileViewIcon.png"
+iconMaskName "VerilogFileViewIcon.msk"
+ftype 11
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+sF 0
+)
+archFileType "UNKNOWN"
+)
+*156 (SaComponent
+uid 1258,0
+optionalChildren [
+*157 (CptPort
+uid 1268,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1269,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,16625,111000,17375"
+)
+tg (CPTG
+uid 1270,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1271,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,16550,115500,17450"
+st "mac_clk"
+blo "112000,17250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "mac_clk"
+t "wire"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*158 (CptPort
+uid 1272,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1273,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,15625,111000,16375"
+)
+tg (CPTG
+uid 1274,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1275,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,15550,114500,16450"
+st "reset"
+blo "112000,16250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "reset"
+t "wire"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*159 (CptPort
+uid 1276,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1277,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,17625,111000,18375"
+)
+tg (CPTG
+uid 1278,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1279,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,17550,118500,18450"
+st "packet_ready"
+blo "112000,18250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_ready"
+t "wire"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*160 (CptPort
+uid 1280,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1281,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,12625,128750,13375"
+)
+tg (CPTG
+uid 1282,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1283,0
+va (VaSet
+font "courier,8,0"
+)
+xt "118500,12550,127000,13450"
+st "done_with_packet"
+ju 2
+blo "127000,13250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "done_with_packet"
+t "reg"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*161 (CptPort
+uid 1284,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1285,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,13625,111000,14375"
+)
+tg (CPTG
+uid 1286,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1287,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,13550,118000,14450"
+st "packet_data"
+blo "112000,14250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_data"
+t "wire"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*162 (CptPort
+uid 1288,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1289,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,13625,128750,14375"
+)
+tg (CPTG
+uid 1290,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1291,0
+va (VaSet
+font "courier,8,0"
+)
+xt "118500,13550,127000,14450"
+st "packet_read_addr"
+ju 2
+blo "127000,14250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_read_addr"
+t "reg"
+b "[5:0]"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*163 (CptPort
+uid 1292,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1293,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,12625,111000,13375"
+)
+tg (CPTG
+uid 1294,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1295,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,12550,114500,13450"
+st "myMAC"
+blo "112000,13250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "myMAC"
+t "wire"
+b "[47:0]"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*164 (CptPort
+uid 1296,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1297,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "110250,14625,111000,15375"
+)
+tg (CPTG
+uid 1298,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1299,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,14550,114000,15450"
+st "myIP"
+blo "112000,15250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "myIP"
+t "wire"
+b "[31:0]"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*165 (CptPort
+uid 1300,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1301,0
+ro 90
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+vasetType 1
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+)
+xt "128000,14625,128750,15375"
+)
+tg (CPTG
+uid 1302,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1303,0
+va (VaSet
+font "courier,8,0"
+)
+xt "121500,14550,127000,15450"
+st "packet_out"
+ju 2
+blo "127000,15250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out"
+t "reg"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*166 (CptPort
+uid 1304,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+)
+xt "128000,15625,128750,16375"
+)
+tg (CPTG
+uid 1306,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1307,0
+va (VaSet
+font "courier,8,0"
+)
+xt "119000,15550,127000,16450"
+st "packet_out_addr"
+ju 2
+blo "127000,16250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out_addr"
+t "reg"
+b "[5:0]"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
+*167 (CptPort
+uid 1308,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1309,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,16625,128750,17375"
+)
+tg (CPTG
+uid 1310,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1311,0
+va (VaSet
+font "courier,8,0"
+)
+xt "120000,16550,127000,17450"
+st "packet_out_we"
+ju 2
+blo "127000,17250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out_we"
+t "reg"
+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*168 (CptPort
+uid 1312,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1313,0
+ro 90
+va (VaSet
+vasetType 1
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+)
+xt "128000,17625,128750,18375"
+)
+tg (CPTG
+uid 1314,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1315,0
+va (VaSet
+font "courier,8,0"
+)
+xt "121000,17550,127000,18450"
+st "packet_xmit"
+ju 2
+blo "127000,18250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_xmit"
+t "reg"
+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*169 (PortMapFrame
+uid 2309,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 2310,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "109000,10000,130000,21000"
+)
+portMapText (BiTextGroup
+uid 2311,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 2312,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,21000,143500,26400"
+st "mac_clk => mac_txclk,
+myIP => ip_addr,
+myMAC => mac_addr,
+packet_data => packet_rxd,
+packet_ready => arp_ready,
+reset => rst_macclk,"
+)
+second (MLText
+uid 2313,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,26400,145000,31800"
+st "done_with_packet => arp_done,
+packet_out => arp_txd,
+packet_out_addr => arp_txa,
+packet_out_we => arp_we,
+packet_read_addr => arp_rxa,
+packet_xmit => arp_xmit"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 1259,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "111000,12000,128000,19000"
+)
+ttg (MlTextGroup
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+uid 1261,0
+va (VaSet
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+)
+xt "116250,19000,122750,19900"
+st "fmc_mTLU_lib"
+blo "116250,19700"
+tm "BdLibraryNameMgr"
+)
+*171 (Text
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+va (VaSet
+font "courier,8,1"
+)
+xt "116250,19900,117750,20800"
+st "arp"
+blo "116250,20600"
+tm "CptNameMgr"
+)
+*172 (Text
+uid 1263,0
+va (VaSet
+font "courier,8,1"
+)
+xt "116250,20800,120750,21700"
+st "arp_block"
+blo "116250,21500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 1264,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 1265,0
+text (MLText
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+va (VaSet
+font "courier,8,0"
+)
+xt "110750,300,124350,12000"
+st "ST_IDLE = 4'h0
+ST_CHECKCONSTWAIT = 4'h1
+ST_CHECKCONST = 4'h2
+ST_CHECKIP_WAIT = 4'h3
+ST_CHECKIP = 4'h4
+ST_RESP_READSET = 4'h5
+ST_RESP_READWAIT = 4'h6
+ST_RESP_WE = 4'h7
+ST_RESP_NEXT = 4'h8
+ST_RESP_READWAIT2 = 4'h9
+ST_PREIDLE = 4'hd
+ST_DONEOK = 4'he
+ST_DONEFAIL = 4'hf
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "ST_IDLE"
+value "4'h0"
+)
+(GiElement
+name "ST_CHECKCONSTWAIT"
+value "4'h1"
+)
+(GiElement
+name "ST_CHECKCONST"
+value "4'h2"
+)
+(GiElement
+name "ST_CHECKIP_WAIT"
+value "4'h3"
+)
+(GiElement
+name "ST_CHECKIP"
+value "4'h4"
+)
+(GiElement
+name "ST_RESP_READSET"
+value "4'h5"
+)
+(GiElement
+name "ST_RESP_READWAIT"
+value "4'h6"
+)
+(GiElement
+name "ST_RESP_WE"
+value "4'h7"
+)
+(GiElement
+name "ST_RESP_NEXT"
+value "4'h8"
+)
+(GiElement
+name "ST_RESP_READWAIT2"
+value "4'h9"
+)
+(GiElement
+name "ST_PREIDLE"
+value "4'hd"
+)
+(GiElement
+name "ST_DONEOK"
+value "4'he"
+)
+(GiElement
+name "ST_DONEFAIL"
+value "4'hf"
+)
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
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+sl 0
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+vasetType 1
+fg "49152,49152,49152"
+)
+xt "111250,17250,112750,18750"
+iconName "VerilogFileViewIcon.png"
+iconMaskName "VerilogFileViewIcon.msk"
+ftype 11
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+sF 0
+)
+archFileType "UNKNOWN"
+)
+*173 (SaComponent
+uid 1436,0
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+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
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+)
+xt "110250,5625,111000,6375"
+)
+tg (CPTG
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+f (Text
+uid 1449,0
+va (VaSet
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+)
+xt "112000,5550,115500,6450"
+st "mac_clk"
+blo "112000,6250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "mac_clk"
+t "wire"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*175 (CptPort
+uid 1450,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1451,0
+ro 90
+va (VaSet
+vasetType 1
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+)
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+)
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+ps "CptPortTextPlaceStrategy"
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+f (Text
+uid 1453,0
+va (VaSet
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+)
+xt "112000,4550,114500,5450"
+st "reset"
+blo "112000,5250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "reset"
+t "wire"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*176 (CptPort
+uid 1454,0
+ps "OnEdgeStrategy"
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+ro 90
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+)
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+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1457,0
+va (VaSet
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+)
+xt "112000,6550,118500,7450"
+st "packet_ready"
+blo "112000,7250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_ready"
+t "wire"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*177 (CptPort
+uid 1458,0
+ps "OnEdgeStrategy"
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+)
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+)
+tg (CPTG
+uid 1460,0
+ps "CptPortTextPlaceStrategy"
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+f (Text
+uid 1461,0
+va (VaSet
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+)
+xt "118500,-450,127000,450"
+st "done_with_packet"
+ju 2
+blo "127000,250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "done_with_packet"
+t "reg"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*178 (CptPort
+uid 1462,0
+ps "OnEdgeStrategy"
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+uid 1463,0
+ro 90
+va (VaSet
+vasetType 1
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+)
+xt "110250,-375,111000,375"
+)
+tg (CPTG
+uid 1464,0
+ps "CptPortTextPlaceStrategy"
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+f (Text
+uid 1465,0
+va (VaSet
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+)
+xt "112000,-450,118000,450"
+st "packet_data"
+blo "112000,250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "packet_data"
+t "wire"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*179 (CptPort
+uid 1466,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
+vasetType 1
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+)
+xt "128000,625,128750,1375"
+)
+tg (CPTG
+uid 1468,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1469,0
+va (VaSet
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+)
+xt "118500,550,127000,1450"
+st "packet_read_addr"
+ju 2
+blo "127000,1250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_read_addr"
+t "reg"
+b "[9:0]"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*180 (CptPort
+uid 1470,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1471,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,1625,128750,2375"
+)
+tg (CPTG
+uid 1472,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1473,0
+va (VaSet
+font "courier,8,0"
+)
+xt "121500,1550,127000,2450"
+st "packet_out"
+ju 2
+blo "127000,2250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out"
+t "reg"
+b "[7:0]"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*181 (CptPort
+uid 1474,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1475,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,2625,128750,3375"
+)
+tg (CPTG
+uid 1476,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1477,0
+va (VaSet
+font "courier,8,0"
+)
+xt "119500,2550,127000,3450"
+st "packet_out_len"
+ju 2
+blo "127000,3250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out_len"
+t "reg"
+b "[9:0]"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*182 (CptPort
+uid 1478,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1479,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,3625,128750,4375"
+)
+tg (CPTG
+uid 1480,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1481,0
+va (VaSet
+font "courier,8,0"
+)
+xt "119000,3550,127000,4450"
+st "packet_out_addr"
+ju 2
+blo "127000,4250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out_addr"
+t "reg"
+b "[9:0]"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*183 (CptPort
+uid 1482,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1483,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,4625,128750,5375"
+)
+tg (CPTG
+uid 1484,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1485,0
+va (VaSet
+font "courier,8,0"
+)
+xt "120000,4550,127000,5450"
+st "packet_out_we"
+ju 2
+blo "127000,5250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_out_we"
+t "reg"
+preAdd 0
+posAdd 0
+o 10
+)
+)
+)
+*184 (CptPort
+uid 1486,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1487,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,5625,128750,6375"
+)
+tg (CPTG
+uid 1488,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1489,0
+va (VaSet
+font "courier,8,0"
+)
+xt "121000,5550,127000,6450"
+st "packet_xmit"
+ju 2
+blo "127000,6250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "packet_xmit"
+t "reg"
+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*185 (CptPort
+uid 1490,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1491,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,6625,128750,7375"
+)
+tg (CPTG
+uid 1492,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1493,0
+va (VaSet
+font "courier,8,0"
+)
+xt "120000,6550,127000,7450"
+st "reset_reg_out"
+ju 2
+blo "127000,7250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "reset_reg_out"
+t "reg"
+b "[31:0]"
+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*186 (PortMapFrame
+uid 2258,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 2259,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "109000,-3000,130000,10000"
+)
+portMapText (BiTextGroup
+uid 2260,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 2261,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,10000,144000,13600"
+st "mac_clk => mac_txclk,
+packet_data => packet_rxd,
+packet_ready => icmp_ready,
+reset => rst_macclk,"
+)
+second (MLText
+uid 2262,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,13600,145500,19900"
+st "packet_out_len => icmp_len,
+packet_read_addr => icmp_rxa,
+done_with_packet => icmp_done,
+packet_out => icmp_txd,
+packet_out_addr => icmp_txa,
+packet_out_we => icmp_we,
+packet_xmit => icmp_xmit"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 1437,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "111000,-1000,128000,8000"
+)
+ttg (MlTextGroup
+uid 1438,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*187 (Text
+uid 1439,0
+va (VaSet
+font "courier,8,1"
+)
+xt "116250,8000,122750,8900"
+st "fmc_mTLU_lib"
+blo "116250,8700"
+tm "BdLibraryNameMgr"
+)
+*188 (Text
+uid 1440,0
+va (VaSet
+font "courier,8,1"
+)
+xt "116250,8900,118250,9800"
+st "icmp"
+blo "116250,9600"
+tm "CptNameMgr"
+)
+*189 (Text
+uid 1441,0
+va (VaSet
+font "courier,8,1"
+)
+xt "116250,9800,121750,10700"
+st "icmp_block"
+blo "116250,10500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 1442,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 1443,0
+text (MLText
+uid 1444,0
+va (VaSet
+font "courier,8,0"
+)
+xt "110750,-13600,126350,-1000"
+st "STATE_IDLE = 4'h0
+STATE_CHECK0WAIT = 4'h1
+STATE_CHECK0 = 4'h2
+STATE_RESP_READSET = 4'h3
+STATE_RESP_READWAIT = 4'h4
+STATE_RESP_READWAIT2 = 4'h5
+STATE_RESP_WE = 4'h6
+STATE_RESP_NEXT = 4'h7
+STATE_ADDCHECKSUM0 = 4'h8
+STATE_ADDCHECKSUM1 = 4'h9
+STATE_ADDCHECKSUMDONE = 4'ha
+STATE_PREIDLE = 4'hd
+STATE_DONEOK = 4'he
+STATE_DONEFAIL = 4'hf
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "STATE_IDLE"
+value "4'h0"
+)
+(GiElement
+name "STATE_CHECK0WAIT"
+value "4'h1"
+)
+(GiElement
+name "STATE_CHECK0"
+value "4'h2"
+)
+(GiElement
+name "STATE_RESP_READSET"
+value "4'h3"
+)
+(GiElement
+name "STATE_RESP_READWAIT"
+value "4'h4"
+)
+(GiElement
+name "STATE_RESP_READWAIT2"
+value "4'h5"
+)
+(GiElement
+name "STATE_RESP_WE"
+value "4'h6"
+)
+(GiElement
+name "STATE_RESP_NEXT"
+value "4'h7"
+)
+(GiElement
+name "STATE_ADDCHECKSUM0"
+value "4'h8"
+)
+(GiElement
+name "STATE_ADDCHECKSUM1"
+value "4'h9"
+)
+(GiElement
+name "STATE_ADDCHECKSUMDONE"
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+)
+(GiElement
+name "STATE_PREIDLE"
+value "4'hd"
+)
+(GiElement
+name "STATE_DONEOK"
+value "4'he"
+)
+(GiElement
+name "STATE_DONEFAIL"
+value "4'hf"
+)
+]
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+)
+viewicon (ZoomableIcon
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+)
+xt "111250,6250,112750,7750"
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+iconMaskName "VerilogFileViewIcon.msk"
+ftype 11
+)
+viewiconposition 0
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+ju 2
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+)
+)
+thePort (LogicalPort
+lang 5
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+decl (Decl
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+preAdd 0
+posAdd 0
+o 11
+)
+)
+)
+*202 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+vasetType 1
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+)
+xt "89000,51625,89750,52375"
+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "85000,51550,88000,52450"
+st "tx_req"
+ju 2
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+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
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+preAdd 0
+posAdd 0
+o 12
+)
+)
+)
+*203 (CptPort
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+)
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+)
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+f (Text
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+va (VaSet
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+)
+xt "84500,52550,88000,53450"
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+)
+)
+thePort (LogicalPort
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+m 1
+decl (Decl
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+preAdd 0
+posAdd 0
+o 13
+)
+)
+)
+*204 (CptPort
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+)
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+)
+tg (CPTG
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+f (Text
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+va (VaSet
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+)
+xt "71000,50550,73500,51450"
+st "tx_ok"
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+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+t "wire"
+preAdd 0
+posAdd 0
+o 14
+)
+)
+)
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+)
+xt "89000,53625,89750,54375"
+)
+tg (CPTG
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+va (VaSet
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+)
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+ju 2
+blo "88000,54250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
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+b "[`pbuf_awidth - 1:0]"
+preAdd 0
+posAdd 0
+o 15
+)
+)
+)
+*206 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
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+)
+xt "89000,54625,89750,55375"
+)
+tg (CPTG
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+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1733,0
+va (VaSet
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+)
+xt "80500,54550,88000,55450"
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+ju 2
+blo "88000,55250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
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+t "wire"
+preAdd 0
+posAdd 0
+o 16
+)
+)
+)
+*207 (CptPort
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+)
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+)
+tg (CPTG
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+va (VaSet
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+)
+xt "71000,51550,75000,52450"
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+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+b "[`pbuf_awidth - 3:0]"
+preAdd 0
+posAdd 0
+o 17
+)
+)
+)
+*208 (CptPort
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+)
+xt "89000,55625,89750,56375"
+)
+tg (CPTG
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+va (VaSet
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+)
+xt "84000,55550,88000,56450"
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+ju 2
+blo "88000,56250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
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+t "wire"
+b "[31:0]"
+preAdd 0
+posAdd 0
+o 18
+)
+)
+)
+*209 (CptPort
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+)
+xt "89000,56625,89750,57375"
+)
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+f (Text
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+va (VaSet
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+)
+xt "84500,56550,88000,57450"
+st "req_len"
+ju 2
+blo "88000,57250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
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+t "wire"
+b "[`pbuf_awidth - 3:0]"
+preAdd 0
+posAdd 0
+o 19
+)
+)
+)
+*210 (CptPort
+uid 1746,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1747,0
+ro 90
+va (VaSet
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+)
+xt "69250,52625,70000,53375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1749,0
+va (VaSet
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+)
+xt "71000,52550,75500,53450"
+st "resp_addr"
+blo "71000,53250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "resp_addr"
+t "wire"
+b "[`pbuf_awidth - 3:0]"
+preAdd 0
+posAdd 0
+o 20
+)
+)
+)
+*211 (CptPort
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+ps "OnEdgeStrategy"
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+)
+xt "69250,53625,70000,54375"
+)
+tg (CPTG
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+f (Text
+uid 1753,0
+va (VaSet
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+)
+xt "71000,53550,75500,54450"
+st "resp_data"
+blo "71000,54250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+t "wire"
+b "[31:0]"
+preAdd 0
+posAdd 0
+o 21
+)
+)
+)
+*212 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "69250,54625,70000,55375"
+)
+tg (CPTG
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+f (Text
+uid 1757,0
+va (VaSet
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+)
+xt "71000,54550,75000,55450"
+st "resp_len"
+blo "71000,55250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
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+t "wire"
+b "[`pbuf_awidth - 3:0]"
+preAdd 0
+posAdd 0
+o 22
+)
+)
+)
+*213 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+)
+xt "69250,55625,70000,56375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
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+f (Text
+uid 1761,0
+va (VaSet
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+)
+xt "71000,55550,74500,56450"
+st "resp_we"
+blo "71000,56250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "resp_we"
+t "wire"
+preAdd 0
+posAdd 0
+o 23
+)
+)
+)
+*214 (CptPort
+uid 1762,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "89000,57625,89750,58375"
+)
+tg (CPTG
+uid 1764,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1765,0
+va (VaSet
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+)
+xt "83500,57550,88000,58450"
+st "req_avail"
+ju 2
+blo "88000,58250"
+)
+)
+thePort (LogicalPort
+lang 5
+m 1
+decl (Decl
+n "req_avail"
+t "reg"
+preAdd 0
+posAdd 0
+o 24
+)
+)
+)
+*215 (CptPort
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+ps "OnEdgeStrategy"
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+ro 90
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+fg "0,65535,0"
+)
+xt "69250,56625,70000,57375"
+)
+tg (CPTG
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+f (Text
+uid 1769,0
+va (VaSet
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+)
+xt "71000,56550,75500,57450"
+st "resp_done"
+blo "71000,57250"
+)
+)
+thePort (LogicalPort
+lang 5
+decl (Decl
+n "resp_done"
+t "wire"
+preAdd 0
+posAdd 0
+o 25
+)
+)
+)
+*216 (PortMapFrame
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+ps "PortMapFrameStrategy"
+shape (RectFrame
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+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "68000,43000,91000,61000"
+)
+portMapText (BiTextGroup
+uid 2338,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 2339,0
+va (VaSet
+font "courier,8,0"
+)
+xt "91000,61000,102000,63700"
+st "ipb_clk => ipb_clk,
+mac_clk => mac_txclk,
+reset => rst_macclk,"
+)
+second (MLText
+uid 2340,0
+va (VaSet
+font "courier,8,0"
+)
+xt "91000,63700,107000,83500"
+st "incoming_ready => udp_ready,
+tx_ok => udp_xmit_ok,
+done_with_incoming => udp_done,
+incoming_space => udp_space,
+rxa => udp_rxa,
+txa => udp_txa,
+txd => udp_txd,
+tx_we => udp_we,
+txl => udp_len,
+tx_send => udp_xmit,
+tx_req => udp_xmit_req,
+req_len => packet_req_len,
+req_avail => req_avail,
+req_data => packet_req_data,
+rxd => packet_rxd,
+rxl => packet_rxl,
+resp_addr => packet_resp_addr,
+resp_data => packet_resp_data,
+resp_len => packet_resp_len,
+resp_we => resp_we,
+resp_done => resp_done,
+req_addr => packet_req_addr"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 1661,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+"
+)
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+)
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+)
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+)
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+name "ST_COPYHEADER2"
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+)
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+)
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+name "ST_DONE"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..ffa9ff2097818298982ae3a2b2e60a944d7ef94c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.bd
@@ -0,0 +1,5793 @@
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+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "ipbus_emac_hostbus"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:32"
+)
+(vvPair
+variable "unit"
+value "ipbus_emac_hostbus"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
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+)
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+)
+)
+)
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+)
+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
+)
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+ else X\"0000\" & \"000\" & emac1sel & mdiocyc & '0' & addr;
+
+"
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+)
+)
+)
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+)
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+"
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+)
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+)
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+st "
+process(clk)
+ begin
+ if rising_edge(clk) then
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+ emac1sel <= ipbus_in.ipb_wdata(12);
+ mdiocyc <= ipbus_in.ipb_wdata(11);
+ addr <= ipbus_in.ipb_wdata(9 downto 0);
+ end if;
+ dcyc_d <= dcyc;
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+"
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.fc b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.fc
new file mode 100644
index 0000000000000000000000000000000000000000..69340622067f8595461a81ff8c5a4208b0a6636a
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_emac_hostbus/rtl.fc
@@ -0,0 +1,2161 @@
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..111cc1b4880dd1c0736f8a47588a765cc5ebd521
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.bd
@@ -0,0 +1,4275 @@
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.fc b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.fc
new file mode 100644
index 0000000000000000000000000000000000000000..96ba989fa7638875d4649bfc1143d14e58154d92
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.fc
@@ -0,0 +1,1742 @@
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+name "process0"
+children [
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+)
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+name "DocView"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/ipbus_fabric.vhd"
+)
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+class "HDS"
+name "DocViewState"
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+)
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+)
+version "19.1"
+appVersion "2010.3 (Build 21)"
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+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric/rtl.fc.info"
+)
+(vvPair
+variable "SideDataUserDir"
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+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/ipbus_fabric"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
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+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
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+value "rtl.fc"
+)
+(vvPair
+variable "f_logical"
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+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
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+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
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+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "ipbus_fabric"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
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+)
+(vvPair
+variable "p_logical"
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+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "fc"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:31"
+)
+(vvPair
+variable "unit"
+value "ipbus_fabric"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
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+)
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+signal sel: integer;
+type mux_rdata_t is array(NSLV downto 0) of std_logic_vector(31 downto 0);
+signal mux_rdata: mux_rdata_t;
+signal ored_ack, ored_err: std_logic_vector(NSLV downto 0);
+signal qstrobe: std_logic;
+"
+tm "FcArchDeclTextMgr"
+)
+associable 1
+)
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+ored_err(NSLV) <= '0';
+
+qstrobe <= ipb_in.ipb_strobe when STROBE_GAP = false else
+ipb_in.ipb_strobe and not (ored_ack(0) or ored_err(0));
+busgen: for i in NSLV-1 downto 0 generate
+signal qual_rdata: std_logic_vector(31 downto 0);
+begin
+ipb_to_slaves(i).ipb_addr <= ipb_in.ipb_addr;
+ipb_to_slaves(i).ipb_wdata <= ipb_in.ipb_wdata;
+ipb_to_slaves(i).ipb_strobe <= qstrobe when sel=i else '0';
+ipb_to_slaves(i).ipb_write <= ipb_in.ipb_write;
+qual_rdata <= ipb_from_slaves(i).ipb_rdata when sel=i else (others => '0');
+mux_rdata(i) <= qual_rdata or mux_rdata(i+1);
+ored_ack(i) <= ored_ack(i+1) or ipb_from_slaves(i).ipb_ack;
+ored_err(i) <= ored_err(i+1) or ipb_from_slaves(i).ipb_err;
+end generate;
+ipb_out.ipb_rdata <= mux_rdata(0);
+ipb_out.ipb_ack <= ored_ack(0);
+ipb_out.ipb_err <= ored_err(0);
+
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/logic_clocks/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/logic_clocks/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..560ca4ebc81b66efd185e0afb3ba78f8b3744a5b
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/logic_clocks/symbol.sb
@@ -0,0 +1,2299 @@
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/fsm.sm b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/fsm.sm
new file mode 100644
index 0000000000000000000000000000000000000000..a1ac8615c7777588130c6d40e50fa4f4fcdc4c13
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/fsm.sm
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..42e1d269fbc657790099ccfc688dd4a9ec3ca6af
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/packet_handler/struct.bd
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+"
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+"
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+"
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/sub_packetbuffer/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/sub_packetbuffer/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..f8a9fa037a9eca76801c76223b0ce92c068ae58c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/sub_packetbuffer/struct.bd
@@ -0,0 +1,13912 @@
+DocumentHdrVersion "1.1"
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+language 1
+dialect 5
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+name "inbuf"
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+duName "sub_packetreq"
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+name "ST_IDLE"
+value "2'h0"
+)
+(GiElement
+name "ST_COPY"
+value "2'h1"
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+name "ST_DONE"
+value "2'h2"
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+uid 441,0
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+name "outbuf"
+duLibraryName "fmc_mTLU_lib"
+duName "sub_packetresp"
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+name "ST_IDLE"
+value "4'h0"
+)
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+name "ST_PREPCOPY"
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+name "ST_COPYWAIT"
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
+]
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+)
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+)
+ttg (MlTextGroup
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+)
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+)
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+)
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+)
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+)
+xt "12000,29800,14500,30700"
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+)
+]
+)
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+)
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+ST_COPY = 2'h1
+ST_DONE = 2'h2
+"
+)
+header ""
+)
+elements [
+(GiElement
+name "ST_IDLE"
+value "2'h0"
+)
+(GiElement
+name "ST_COPY"
+value "2'h1"
+)
+(GiElement
+name "ST_DONE"
+value "2'h2"
+)
+]
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+)
+viewicon (ZoomableIcon
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+)
+xt "7250,26250,8750,27750"
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+)
+viewiconposition 0
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+)
+archFileType "UNKNOWN"
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+o 10
+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 11
+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 12
+)
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+o 13
+)
+)
+)
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+)
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+)
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+)
+xt "110000,3550,114000,4450"
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+)
+)
+thePort (LogicalPort
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+posAdd 0
+o 14
+)
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_struct.bd._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_struct.bd._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_struct.bd._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
new file mode 100644
index 0000000000000000000000000000000000000000..382dde123fa24aed73d8c7bef07cb26e95ea75ea
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
@@ -0,0 +1,17784 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+(DmPackageRef
+library "work"
+unitName "emac_hostbus_decl"
+)
+(DmPackageRef
+library "work"
+unitName "fmcTLU"
+)
+(DmPackageRef
+library "unisim"
+unitName "vcomponents"
+)
+]
+instances [
+(Instance
+name "I4"
+duLibraryName "work"
+duName "IPBusInterface"
+elements [
+(GiElement
+name "NUM_EXT_SLAVES"
+type "positive"
+value "g_NUM_EXT_SLAVES"
+)
+]
+mwi 0
+uid 4555,0
+)
+(Instance
+name "I8"
+duLibraryName "moduleware"
+duName "sor"
+elements [
+]
+mwi 1
+uid 4949,0
+)
+(Instance
+name "I0"
+duLibraryName "work"
+duName "DUTInterfaces"
+elements [
+(GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "g_NUM_DUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+mwi 0
+uid 6898,0
+)
+(Instance
+name "I3"
+duLibraryName "work"
+duName "triggerLogic"
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+mwi 0
+uid 9123,0
+)
+(Instance
+name "I5"
+duLibraryName "work"
+duName "eventBuffer"
+elements [
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_WRITE_COUNTER_WIDTH"
+type "positive"
+value "13"
+)
+(GiElement
+name "g_READ_COUNTER_WIDTH"
+type "positive"
+value "14"
+)
+]
+mwi 0
+uid 9363,0
+)
+(Instance
+name "I7"
+duLibraryName "work"
+duName "i2c_master"
+elements [
+]
+mwi 0
+uid 10058,0
+)
+(Instance
+name "I2"
+duLibraryName "work"
+duName "eventFormatter"
+elements [
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_TRIG_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+(GiElement
+name "g_EVTTYPE_WIDTH"
+type "positive"
+value "4"
+e "-- Width of the event type word"
+)
+(GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "g_NUM_EDGE_INPUTS"
+pr "--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)"
+apr 0
+e "-- Number of edge inputs"
+)
+(GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+e "-- Number of trigger inputs"
+)
+]
+mwi 0
+uid 10522,0
+)
+(Instance
+name "I6"
+duLibraryName "work"
+duName "logic_clocks"
+elements [
+]
+mwi 0
+uid 11070,0
+)
+(Instance
+name "I9"
+duLibraryName "moduleware"
+duName "gnd"
+elements [
+]
+mwi 1
+uid 11097,0
+)
+(Instance
+name "I10"
+duLibraryName "moduleware"
+duName "gnd"
+elements [
+]
+mwi 1
+uid 11116,0
+)
+(Instance
+name "I11"
+duLibraryName "moduleware"
+duName "gnd"
+elements [
+]
+mwi 1
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+)
+(Instance
+name "I12"
+duLibraryName "moduleware"
+duName "gnd"
+elements [
+]
+mwi 1
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+)
+(Instance
+name "I13"
+duLibraryName "moduleware"
+duName "gnd"
+elements [
+]
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+)
+(Instance
+name "I14"
+duLibraryName "moduleware"
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+]
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+)
+(Instance
+name "I1"
+duLibraryName "work"
+duName "triggerInputs"
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "natural"
+value "g_NUM_TRIG_INPUTS"
+)
+]
+mwi 0
+uid 11619,0
+)
+]
+embeddedInstances [
+(EmbeddedInstance
+name "i2c_tristate"
+number "1"
+)
+]
+libraryRefs [
+"ieee"
+"work"
+"unisim"
+]
+)
+version "30.1"
+appVersion "2012.2b (Build 5)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy"
+)
+(vvPair
+variable "date"
+value "01/24/14"
+)
+(vvPair
+variable "day"
+value "Fri"
+)
+(vvPair
+variable "day_long"
+value "Friday"
+)
+(vvPair
+variable "dd"
+value "24"
+)
+(vvPair
+variable "entity_name"
+value "top_extphy"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "graphical_source_author"
+value "phdgc"
+)
+(vvPair
+variable "graphical_source_date"
+value "01/24/14"
+)
+(vvPair
+variable "graphical_source_group"
+value "users"
+)
+(vvPair
+variable "graphical_source_time"
+value "16:06:33"
+)
+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "01"
+)
+(vvPair
+variable "module_name"
+value "top_extphy"
+)
+(vvPair
+variable "month"
+value "Jan"
+)
+(vvPair
+variable "month_long"
+value "January"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
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+)
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+)
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+)
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+)
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+)
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+bg "0,0,32768"
+font "courier,8,0"
+)
+xt "183200,160050,194700,160950"
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+%library/%unit/%view
+"
+tm "CommentText"
+wrapOption 3
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+visibleWidth 17000
+)
+position 1
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+)
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+)
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+)
+oxt "14000,66000,55000,71000"
+)
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+shape (CompositeShape
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+)
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+"79500,22000"
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+)
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+)
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+)
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+ju 2
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+tm "WireNameMgr"
+)
+)
+)
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+"79500,25000"
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+)
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+)
+)
+)
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+)
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+)
+xt "-10000,45700,19500,46600"
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+"
+)
+)
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+decl (Decl
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+)
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+)
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+)
+)
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+)
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+)
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+"
+)
+)
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+decl (Decl
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+suid 41,0
+)
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+)
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+"
+)
+)
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+decl (Decl
+n "ipbr"
+t "ipb_rbus_array"
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+o 42
+suid 42,0
+)
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+)
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+st "SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --! IPBus read signals
+"
+)
+)
+*44 (Net
+uid 1808,0
+decl (Decl
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+t "std_logic"
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+suid 61,0
+)
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+)
+xt "-10000,61000,27000,61900"
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+"
+)
+)
+*45 (Net
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+)
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+)
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+"
+)
+)
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+)
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+"
+)
+)
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+)
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+"
+)
+)
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+)
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+"
+)
+)
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+"208000,4000"
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+)
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+)
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+)
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+blo "211000,4200"
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+)
+)
+)
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+)
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+)
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+"
+)
+)
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+lang 2
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+preAdd 0
+posAdd 0
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+)
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+)
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+"
+)
+)
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+)
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+)
+xt "-10000,52000,28500,52900"
+st "SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0)
+"
+)
+)
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+)
+xt "96000,9550,103000,10450"
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+)
+)
+thePort (LogicalPort
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+t "std_logic"
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+)
+)
+)
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+)
+xt "96000,12550,102500,13450"
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+blo "96000,13250"
+)
+)
+thePort (LogicalPort
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+o 2
+suid 3,0
+)
+)
+)
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+)
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+st "gmii_rx_er_i"
+blo "96000,16250"
+)
+)
+thePort (LogicalPort
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+)
+)
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+)
+xt "94250,18625,95000,19375"
+)
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+va (VaSet
+font "courier,8,0"
+)
+xt "96000,18550,105500,19450"
+st "gmii_rxd_i : (7:0)"
+blo "96000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 4
+suid 5,0
+)
+)
+)
+*58 (CptPort
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4496,0
+ro 90
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+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,8625,128750,9375"
+)
+tg (CPTG
+uid 4497,0
+ps "CptPortTextPlaceStrategy"
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+va (VaSet
+font "courier,8,0"
+)
+xt "120500,8550,127000,9450"
+st "gmii_tx_en_o"
+ju 2
+blo "127000,9250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 10
+suid 6,0
+)
+)
+)
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+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4500,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,10625,128750,11375"
+)
+tg (CPTG
+uid 4501,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4502,0
+va (VaSet
+font "courier,8,0"
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+xt "120500,10550,127000,11450"
+st "gmii_tx_er_o"
+ju 2
+blo "127000,11250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 11
+suid 7,0
+)
+)
+)
+*60 (CptPort
+uid 4503,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4504,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,13625,128750,14375"
+)
+tg (CPTG
+uid 4505,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4506,0
+va (VaSet
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+)
+xt "117500,13550,127000,14450"
+st "gmii_txd_o : (7:0)"
+ju 2
+blo "127000,14250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 12
+suid 8,0
+)
+)
+)
+*61 (CptPort
+uid 4507,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4508,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,15625,128750,16375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
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+f (Text
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+va (VaSet
+font "courier,8,0"
+)
+xt "121500,15550,127000,16450"
+st "phy_rstb_o"
+ju 2
+blo "127000,16250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 17
+suid 10,0
+)
+)
+)
+*62 (CptPort
+uid 4511,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4512,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,17625,128750,18375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4514,0
+va (VaSet
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+)
+xt "119500,17550,127000,18450"
+st "gmii_gtx_clk_o"
+ju 2
+blo "127000,18250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 9
+suid 1,0
+)
+)
+)
+*63 (CptPort
+uid 4515,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4516,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,21625,95000,22375"
+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4518,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,21550,101500,22450"
+st "sysclk_n_i"
+blo "96000,22250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+o 6
+suid 12,0
+)
+)
+)
+*64 (CptPort
+uid 4519,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4520,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,24625,95000,25375"
+)
+tg (CPTG
+uid 4521,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4522,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,24550,101500,25450"
+st "sysclk_p_i"
+blo "96000,25250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+eolc "! 200 MHz xtal clock"
+o 7
+suid 13,0
+)
+)
+)
+*65 (CptPort
+uid 4523,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4524,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,19625,128750,20375"
+)
+tg (CPTG
+uid 4525,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4526,0
+va (VaSet
+font "courier,8,0"
+)
+xt "122500,19550,127000,20450"
+st "ipb_clk_o"
+ju 2
+blo "127000,20250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_clk_o"
+t "std_logic"
+eolc "! IPBus clock to slaves"
+o 13
+suid 14,0
+)
+)
+)
+*66 (CptPort
+uid 4527,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4528,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,22625,128750,23375"
+)
+tg (CPTG
+uid 4529,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4530,0
+va (VaSet
+font "courier,8,0"
+)
+xt "122500,22550,127000,23450"
+st "ipb_rst_o"
+ju 2
+blo "127000,23250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_rst_o"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 14
+suid 15,0
+)
+)
+)
+*67 (CptPort
+uid 4531,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4532,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,24625,128750,25375"
+)
+tg (CPTG
+uid 4533,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4534,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,24550,127000,25450"
+st "ipbw_o : (NUM_EXT_SLAVES-1:0)"
+ju 2
+blo "127000,25250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbw_o"
+t "ipb_wbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IBus write signals"
+o 15
+suid 16,0
+)
+)
+)
+*68 (CptPort
+uid 4535,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4536,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
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+)
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+)
+header ""
+)
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+value "g_NUM_EXT_SLAVES"
+)
+]
+)
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+)
+ordering 1
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+)
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+)
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+)
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+)
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+st "extclk_n_b"
+ju 2
+blo "154000,40250"
+tm "WireNameMgr"
+)
+)
+)
+*78 (Net
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+decl (Decl
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+)
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+"
+)
+)
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+)
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+)
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+)
+)
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+)
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+"
+)
+)
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+decl (Decl
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+t "std_logic"
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+suid 109,0
+)
+declText (MLText
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+"
+)
+)
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+"
+)
+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
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+)
+)
+)
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+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6032,0
+sl 0
+ro 270
+xt "3000,136625,4500,137375"
+)
+(Line
+uid 6033,0
+sl 0
+ro 270
+xt "4500,137000,5000,137000"
+pts [
+"4500,137000"
+"5000,137000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6034,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6035,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-8000,136550,2000,137450"
+st "threshold_discr_n_i"
+ju 2
+blo "2000,137250"
+tm "WireNameMgr"
+)
+)
+)
+*112 (Net
+uid 6042,0
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 121,0
+)
+declText (MLText
+uid 6043,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,27700,24500,28600"
+st "threshold_discr_n_i : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0)
+"
+)
+)
+*113 (Net
+uid 6676,0
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+o 13
+suid 129,0
+)
+declText (MLText
+uid 6677,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,26800,6000,27700"
+st "sysclk_p_i : std_logic
+"
+)
+)
+*114 (Net
+uid 6678,0
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 130,0
+)
+declText (MLText
+uid 6679,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,25900,17500,26800"
+st "sysclk_n_i : std_logic --! 200 MHz xtal clock
+"
+)
+)
+*115 (PortIoOut
+uid 6702,0
+shape (CompositeShape
+uid 6703,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6704,0
+sl 0
+ro 270
+xt "64500,89625,66000,90375"
+)
+(Line
+uid 6705,0
+sl 0
+ro 270
+xt "64000,90000,64500,90000"
+pts [
+"64000,90000"
+"64500,90000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6706,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6707,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,88550,63500,89450"
+st "triggers_p_o"
+blo "57000,89250"
+tm "WireNameMgr"
+)
+)
+)
+*116 (Net
+uid 6714,0
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 131,0
+)
+declText (MLText
+uid 6715,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,38500,33500,39400"
+st "triggers_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0) --! Trigger lines to DUT
+"
+)
+)
+*117 (PortIoIn
+uid 6716,0
+shape (CompositeShape
+uid 6717,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6718,0
+sl 0
+ro 270
+xt "-2000,88625,-500,89375"
+)
+(Line
+uid 6719,0
+sl 0
+ro 270
+xt "-500,89000,0,89000"
+pts [
+"-500,89000"
+"0,89000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6720,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6721,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-7000,88500,-3000,89400"
+st "busy_p_i"
+ju 2
+blo "-3000,89200"
+tm "WireNameMgr"
+)
+)
+)
+*118 (Net
+uid 6728,0
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 132,0
+)
+declText (MLText
+uid 6729,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,16900,41500,17800"
+st "busy_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0) --! Busy lines from DUTs ( active high )
+"
+)
+)
+*119 (PortIoOut
+uid 6730,0
+shape (CompositeShape
+uid 6731,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6732,0
+sl 0
+ro 270
+xt "64500,96625,66000,97375"
+)
+(Line
+uid 6733,0
+sl 0
+ro 270
+xt "64000,97000,64500,97000"
+pts [
+"64000,97000"
+"64500,97000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6734,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6735,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,95550,65500,96450"
+st "reset_or_clk_p_o"
+blo "57000,96250"
+tm "WireNameMgr"
+)
+)
+)
+*120 (Net
+uid 6742,0
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 133,0
+)
+declText (MLText
+uid 6743,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,36700,21000,37600"
+st "reset_or_clk_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*121 (PortIoIn
+uid 6744,0
+shape (CompositeShape
+uid 6745,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6746,0
+sl 0
+ro 270
+xt "-2000,92625,-500,93375"
+)
+(Line
+uid 6747,0
+sl 0
+ro 270
+xt "-500,93000,0,93000"
+pts [
+"-500,93000"
+"0,93000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6748,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6749,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-9000,92500,-3000,93400"
+st "dut_clk_p_i"
+ju 2
+blo "-3000,93200"
+tm "WireNameMgr"
+)
+)
+)
+*122 (Net
+uid 6756,0
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 134,0
+)
+declText (MLText
+uid 6757,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,21400,21000,22300"
+st "dut_clk_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*123 (Net
+uid 6770,0
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 135,0
+)
+declText (MLText
+uid 6771,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,19600,15500,20500"
+st "dip_switch_i : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*124 (PortIoIn
+uid 6772,0
+shape (CompositeShape
+uid 6773,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6774,0
+sl 0
+ro 270
+xt "-2000,90625,-500,91375"
+)
+(Line
+uid 6775,0
+sl 0
+ro 270
+xt "-500,91000,0,91000"
+pts [
+"-500,91000"
+"0,91000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6776,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6777,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-7000,90500,-3000,91400"
+st "busy_n_i"
+ju 2
+blo "-3000,91200"
+tm "WireNameMgr"
+)
+)
+)
+*125 (Net
+uid 6784,0
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 136,0
+)
+declText (MLText
+uid 6785,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,16000,21000,16900"
+st "busy_n_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*126 (PortIoOut
+uid 6786,0
+shape (CompositeShape
+uid 6787,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6788,0
+sl 0
+ro 270
+xt "64500,98625,66000,99375"
+)
+(Line
+uid 6789,0
+sl 0
+ro 270
+xt "64000,99000,64500,99000"
+pts [
+"64000,99000"
+"64500,99000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6790,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6791,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,97550,65500,98450"
+st "reset_or_clk_n_o"
+blo "57000,98250"
+tm "WireNameMgr"
+)
+)
+)
+*127 (Net
+uid 6798,0
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 137,0
+)
+declText (MLText
+uid 6799,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,35800,21000,36700"
+st "reset_or_clk_n_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*128 (PortIoOut
+uid 6800,0
+shape (CompositeShape
+uid 6801,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6802,0
+sl 0
+ro 270
+xt "64500,91625,66000,92375"
+)
+(Line
+uid 6803,0
+sl 0
+ro 270
+xt "64000,92000,64500,92000"
+pts [
+"64000,92000"
+"64500,92000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6804,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6805,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,90550,63500,91450"
+st "triggers_n_o"
+blo "57000,91250"
+tm "WireNameMgr"
+)
+)
+)
+*129 (Net
+uid 6812,0
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 138,0
+)
+declText (MLText
+uid 6813,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,37600,21000,38500"
+st "triggers_n_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*130 (PortIoIn
+uid 6814,0
+shape (CompositeShape
+uid 6815,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6816,0
+sl 0
+ro 270
+xt "-2000,94625,-500,95375"
+)
+(Line
+uid 6817,0
+sl 0
+ro 270
+xt "-500,95000,0,95000"
+pts [
+"-500,95000"
+"0,95000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6818,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6819,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-9000,94500,-3000,95400"
+st "dut_clk_n_i"
+ju 2
+blo "-3000,95200"
+tm "WireNameMgr"
+)
+)
+)
+*131 (Net
+uid 6826,0
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 139,0
+)
+declText (MLText
+uid 6827,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,20500,21000,21400"
+st "dut_clk_n_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*132 (SaComponent
+uid 6898,0
+optionalChildren [
+*133 (CptPort
+uid 6830,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6831,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,89625,55750,90375"
+)
+tg (CPTG
+uid 6832,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6833,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,89550,54000,90450"
+st "trigger_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,90250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 16
+suid 1,0
+)
+)
+)
+*134 (CptPort
+uid 6834,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6835,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,88625,10000,89375"
+)
+tg (CPTG
+uid 6836,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6837,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,88550,29500,89450"
+st "busy_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "11000,89250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 2
+suid 2,0
+)
+)
+)
+*135 (CptPort
+uid 6838,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6839,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,96625,55750,97375"
+)
+tg (CPTG
+uid 6840,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6841,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,96550,54000,97450"
+st "reset_or_clk_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,97250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 14
+suid 3,0
+)
+)
+)
+*136 (CptPort
+uid 6842,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6843,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,92625,10000,93375"
+)
+tg (CPTG
+uid 6844,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6845,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,92550,29000,93450"
+st "clk_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "11000,93250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 4
+suid 4,0
+)
+)
+)
+*137 (CptPort
+uid 6846,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6847,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,96625,10000,97375"
+)
+tg (CPTG
+uid 6848,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6849,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,96550,15500,97450"
+st "trigger_i"
+blo "11000,97250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "goes high when trigger logic issues a trigger"
+o 11
+suid 5,0
+)
+)
+)
+*138 (CptPort
+uid 6850,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6851,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,98625,10000,99375"
+)
+tg (CPTG
+uid 6852,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6853,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,98550,18500,99450"
+st "clk_4x_logic_i"
+blo "11000,99250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+o 3
+suid 6,0
+)
+)
+)
+*139 (CptPort
+uid 6854,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6855,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,100625,10000,101375"
+)
+tg (CPTG
+uid 6856,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6857,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,100550,20000,101450"
+st "strobe_4x_logic_i"
+blo "11000,101250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! goes high every 4th clock cycle"
+o 9
+suid 7,0
+)
+)
+)
+*140 (CptPort
+uid 6858,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6859,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,102625,10000,103375"
+)
+tg (CPTG
+uid 6860,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6861,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,102550,31000,103450"
+st "trigger_counter_i : (g_IPBUS_WIDTH-1:0)"
+blo "11000,103250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_counter_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 10
+suid 8,0
+)
+)
+)
+*141 (CptPort
+uid 6862,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6863,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,104625,10000,105375"
+)
+tg (CPTG
+uid 6864,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6865,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,104550,17000,105450"
+st "ipbus_clk_i"
+blo "11000,105250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 6
+suid 9,0
+)
+)
+)
+*142 (CptPort
+uid 6866,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6867,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,106625,10000,107375"
+)
+tg (CPTG
+uid 6868,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6869,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,106550,18000,107450"
+st "ipbus_reset_i"
+blo "11000,107250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 8
+suid 10,0
+)
+)
+)
+*143 (CptPort
+uid 6870,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6871,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,108625,10000,109375"
+)
+tg (CPTG
+uid 6872,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6873,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,108550,14500,109450"
+st "ipbus_i"
+blo "11000,109250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 7
+suid 11,0
+)
+)
+)
+*144 (CptPort
+uid 6874,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6875,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,103625,55750,104375"
+)
+tg (CPTG
+uid 6876,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6877,0
+va (VaSet
+font "courier,8,0"
+)
+xt "50500,103550,54000,104450"
+st "ipbus_o"
+ju 2
+blo "54000,104250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 12
+suid 12,0
+)
+)
+)
+*145 (CptPort
+uid 6878,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6879,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,107625,55750,108375"
+)
+tg (CPTG
+uid 6880,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6881,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,107550,54000,108450"
+st "veto_o"
+ju 2
+blo "54000,108250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "veto_o"
+t "std_logic"
+eolc "goes high when one or more DUT are busy"
+o 17
+suid 13,0
+)
+)
+)
+*146 (CptPort
+uid 6882,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6883,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,91625,55750,92375"
+)
+tg (CPTG
+uid 6884,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6885,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,91550,54000,92450"
+st "trigger_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,92250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 15
+suid 14,0
+)
+)
+)
+*147 (CptPort
+uid 6886,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6887,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,90625,10000,91375"
+)
+tg (CPTG
+uid 6888,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6889,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,90550,29500,91450"
+st "busy_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "11000,91250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 1
+suid 15,0
+)
+)
+)
+*148 (CptPort
+uid 6890,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6891,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,98625,55750,99375"
+)
+tg (CPTG
+uid 6892,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6893,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,98550,54000,99450"
+st "reset_or_clk_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,99250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 13
+suid 16,0
+)
+)
+)
+*149 (CptPort
+uid 6894,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6895,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,94625,10000,95375"
+)
+tg (CPTG
+uid 6896,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6897,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,94550,29000,95450"
+st "clk_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "11000,95250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 5
+suid 17,0
+)
+)
+)
+]
+shape (Rectangle
+uid 6899,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "10000,88000,55000,110000"
+)
+oxt "14000,17000,59000,39000"
+ttg (MlTextGroup
+uid 6900,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*150 (Text
+uid 6901,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,97100,21750,98000"
+st "work"
+blo "19750,97800"
+tm "BdLibraryNameMgr"
+)
+*151 (Text
+uid 6902,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,98000,26750,98900"
+st "DUTInterfaces"
+blo "19750,98700"
+tm "CptNameMgr"
+)
+*152 (Text
+uid 6903,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,98900,20750,99800"
+st "I0"
+blo "19750,99600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 6904,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 6905,0
+text (MLText
+uid 6906,0
+va (VaSet
+font "courier,8,0"
+)
+xt "18000,86200,42000,88000"
+st "g_NUM_DUTS = g_NUM_DUTS ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "g_NUM_DUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 6907,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "10250,108250,11750,109750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*153 (PortIoIn
+uid 6908,0
+shape (CompositeShape
+uid 6909,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6910,0
+sl 0
+ro 270
+xt "78000,30625,79500,31375"
+)
+(Line
+uid 6911,0
+sl 0
+ro 270
+xt "79500,31000,80000,31000"
+pts [
+"79500,31000"
+"80000,31000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6912,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6913,0
+va (VaSet
+font "courier,8,0"
+)
+xt "70500,30500,77000,31400"
+st "dip_switch_i"
+ju 2
+blo "77000,31200"
+tm "WireNameMgr"
+)
+)
+)
+*154 (Net
+uid 7099,0
+decl (Decl
+n "ipbus_rst"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 46
+suid 140,0
+)
+declText (MLText
+uid 7100,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,57400,23000,58300"
+st "SIGNAL ipbus_rst : std_logic -- ! IPBus reset to slaves
+"
+)
+)
+*155 (PortIoInOut
+uid 7881,0
+shape (CompositeShape
+uid 7882,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Hexagon
+uid 7883,0
+sl 0
+xt "217500,14625,219000,15375"
+)
+(Line
+uid 7884,0
+sl 0
+xt "217000,15000,217500,15000"
+pts [
+"217000,15000"
+"217500,15000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 7885,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 7886,0
+va (VaSet
+font "courier,8,0"
+)
+xt "220000,14550,224500,15450"
+st "i2c_scl_b"
+blo "220000,15250"
+tm "WireNameMgr"
+)
+)
+)
+*156 (SaComponent
+uid 9123,0
+optionalChildren [
+*157 (CptPort
+uid 9071,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9072,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,131625,106000,132375"
+)
+tg (CPTG
+uid 9073,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9074,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,131550,114500,132450"
+st "clk_4x_logic_i"
+blo "107000,132250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 1,0
+)
+)
+)
+*158 (CptPort
+uid 9075,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9076,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,134625,106000,135375"
+)
+tg (CPTG
+uid 9077,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9078,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,134550,114500,135450"
+st "logic_strobe_i"
+blo "107000,135250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 5
+suid 2,0
+)
+)
+)
+*159 (CptPort
+uid 9079,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9080,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,142625,106000,143375"
+)
+tg (CPTG
+uid 9081,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9082,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,142550,113000,143450"
+st "ipbus_clk_i"
+blo "107000,143250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 3,0
+)
+)
+)
+*160 (CptPort
+uid 9083,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9084,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,144625,106000,145375"
+)
+tg (CPTG
+uid 9085,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9086,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,144550,110500,145450"
+st "ipbus_i"
+blo "107000,145250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 3
+suid 4,0
+)
+)
+)
+*161 (CptPort
+uid 9087,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9088,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,149625,143750,150375"
+)
+tg (CPTG
+uid 9089,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9090,0
+va (VaSet
+font "courier,8,0"
+)
+xt "138500,149550,142000,150450"
+st "ipbus_o"
+ju 2
+blo "142000,150250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 6
+suid 5,0
+)
+)
+)
+*162 (CptPort
+uid 9091,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9092,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,147625,106000,148375"
+)
+tg (CPTG
+uid 9093,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9094,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,147550,114000,148450"
+st "ipbus_reset_i"
+blo "107000,148250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 4
+suid 6,0
+)
+)
+)
+*163 (CptPort
+uid 9095,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9096,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,137625,106000,138375"
+)
+tg (CPTG
+uid 9097,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9098,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,137550,122500,138450"
+st "trigger_i : (g_NUM_INPUTS-1:0)"
+blo "107000,138250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "trigger_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger from input conector active"
+o 7
+suid 7,0
+)
+)
+)
+*164 (CptPort
+uid 9099,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9100,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,139625,106000,140375"
+)
+tg (CPTG
+uid 9101,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9102,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,139550,110000,140450"
+st "veto_i"
+blo "107000,140250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "veto_i"
+t "std_logic"
+eolc "! Halts triggers when high"
+o 8
+suid 8,0
+)
+)
+)
+*165 (CptPort
+uid 9103,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9104,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,136625,143750,137375"
+)
+tg (CPTG
+uid 9105,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9106,0
+va (VaSet
+font "courier,8,0"
+)
+xt "132000,136550,142000,137450"
+st "post_veto_trigger_o"
+ju 2
+blo "142000,137250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "post_veto_trigger_o"
+t "std_logic"
+eolc "! goes high when trigger passes"
+o 9
+suid 9,0
+)
+)
+)
+*166 (CptPort
+uid 9107,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9108,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,141625,143750,142375"
+)
+tg (CPTG
+uid 9109,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9110,0
+va (VaSet
+font "courier,8,0"
+)
+xt "133500,141550,142000,142450"
+st "trigger_active_o"
+ju 2
+blo "142000,142250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_active_o"
+t "std_logic"
+eolc "--! Goes high when triggers are active ( ie. not veoted)"
+o 10
+suid 10,0
+)
+)
+)
+*167 (CptPort
+uid 9111,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9112,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,132625,143750,133375"
+)
+tg (CPTG
+uid 9113,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9114,0
+va (VaSet
+font "courier,8,0"
+)
+xt "132500,132550,142000,133450"
+st "pre_veto_trigger_o"
+ju 2
+blo "142000,133250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pre_veto_trigger_o"
+t "std_logic"
+o 11
+suid 11,0
+)
+)
+)
+*168 (CptPort
+uid 9115,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9116,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,145625,143750,146375"
+)
+tg (CPTG
+uid 9117,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9118,0
+va (VaSet
+font "courier,8,0"
+)
+xt "123500,145550,142000,146450"
+st "event_number_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "142000,146250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "event_number_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 12
+suid 12,0
+)
+)
+)
+*169 (CptPort
+uid 9119,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9120,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,150625,106000,151375"
+)
+tg (CPTG
+uid 9121,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9122,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,150550,114000,151450"
+st "logic_reset_i"
+blo "107000,151250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "active high. Synchronous with clk_4x_logic"
+o 13
+suid 13,0
+)
+)
+)
+]
+shape (Rectangle
+uid 9124,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "106000,131000,143000,152000"
+)
+oxt "8000,17000,45000,38000"
+ttg (MlTextGroup
+uid 9125,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*170 (Text
+uid 9126,0
+va (VaSet
+font "courier,8,1"
+)
+xt "115750,140100,117750,141000"
+st "work"
+blo "115750,140800"
+tm "BdLibraryNameMgr"
+)
+*171 (Text
+uid 9127,0
+va (VaSet
+font "courier,8,1"
+)
+xt "115750,141000,122250,141900"
+st "triggerLogic"
+blo "115750,141700"
+tm "CptNameMgr"
+)
+*172 (Text
+uid 9128,0
+va (VaSet
+font "courier,8,1"
+)
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+)
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+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
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+)
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+)
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+)
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+)
+archFileType "UNKNOWN"
+)
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+)
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+)
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+"
+)
+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+st "g_EVENT_DATA_WIDTH = g_EVENT_DATA_WIDTH ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive )
+g_WRITE_COUNTER_WIDTH = 13 ( positive )
+g_READ_COUNTER_WIDTH = 14 ( positive ) "
+)
+header ""
+)
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+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
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+)
+(GiElement
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+)
+(GiElement
+name "g_READ_COUNTER_WIDTH"
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+)
+]
+)
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+)
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+)
+ordering 1
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+)
+archFileType "UNKNOWN"
+)
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+)
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+)
+xt "-10000,60100,39000,61000"
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+"
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
+xt "190500,20550,195000,21450"
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+font "courier,8,0"
+)
+xt "208200,21200,224100,27500"
+st "
+-- eb1 1
+i2c_scl_b <= '0' when (s_i2c_scl_enb = '0') else 'Z';
+i2c_sda_b <= '0' when (s_i2c_sda_enb = '0') else 'Z';
+
+
+"
+tm "HdlTextMgr"
+wrapOption 3
+visibleHeight 7000
+visibleWidth 18000
+)
+)
+)
+]
+shape (Rectangle
+uid 10079,0
+va (VaSet
+vasetType 1
+fg "65535,65535,37120"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "208000,19000,226000,28000"
+)
+oxt "0,0,8000,10000"
+ttg (MlTextGroup
+uid 10080,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*204 (Text
+uid 10081,0
+va (VaSet
+font "courier,8,1"
+)
+xt "208250,19100,214750,20000"
+st "i2c_tristate"
+blo "208250,19800"
+tm "HdlTextNameMgr"
+)
+*205 (Text
+uid 10082,0
+va (VaSet
+font "courier,8,1"
+)
+xt "208250,20000,208750,20900"
+st "1"
+blo "208250,20700"
+tm "HdlTextNumberMgr"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 10083,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "208250,26250,209750,27750"
+iconName "TextFile.png"
+iconMaskName "TextFile.msk"
+ftype 21
+)
+viewiconposition 0
+)
+*206 (Net
+uid 10096,0
+decl (Decl
+n "s_i2c_scl_enb"
+t "std_logic"
+o 52
+suid 153,0
+)
+declText (MLText
+uid 10097,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,62800,9500,63700"
+st "SIGNAL s_i2c_scl_enb : std_logic
+"
+)
+)
+*207 (Net
+uid 10122,0
+decl (Decl
+n "s_i2c_sda_enb"
+t "std_logic"
+o 53
+suid 157,0
+)
+declText (MLText
+uid 10123,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,63700,9500,64600"
+st "SIGNAL s_i2c_sda_enb : std_logic
+"
+)
+)
+*208 (SaComponent
+uid 10522,0
+optionalChildren [
+*209 (CptPort
+uid 10434,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10435,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,66625,98000,67375"
+)
+tg (CPTG
+uid 10436,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10437,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,66550,103500,67450"
+st "trigger_i"
+blo "99000,67250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "--! goes high to load trigger data. One cycle of clk_4x_logic"
+posAdd 0
+o 5
+suid 1,0
+)
+)
+)
+*210 (CptPort
+uid 10438,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10439,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,69625,98000,70375"
+)
+tg (CPTG
+uid 10440,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10441,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,69550,106500,70450"
+st "clk_4x_logic_i"
+blo "99000,70250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 2,0
+)
+)
+)
+*211 (CptPort
+uid 10442,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10443,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,72625,98000,73375"
+)
+tg (CPTG
+uid 10444,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10445,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,72550,106500,73450"
+st "logic_strobe_i"
+blo "99000,73250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+)
+)
+*212 (CptPort
+uid 10446,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10447,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,68625,150750,69375"
+)
+tg (CPTG
+uid 10448,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10449,0
+va (VaSet
+font "courier,8,0"
+)
+xt "142000,68550,149000,69450"
+st "data_strobe_o"
+ju 2
+blo "149000,69250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "data_strobe_o"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 19
+suid 4,0
+)
+)
+)
+*213 (CptPort
+uid 10450,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10451,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,75625,150750,76375"
+)
+tg (CPTG
+uid 10452,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10453,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,75550,149000,76450"
+st "trigger_count_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "149000,76250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_count_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 22
+suid 5,0
+)
+)
+)
+*214 (CptPort
+uid 10454,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10455,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,75625,98000,76375"
+)
+tg (CPTG
+uid 10456,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10457,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,75550,120000,76450"
+st "trigger_times_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "99000,76250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_times_i"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "Array of trigger times ( w.r.t. logic_strobe)"
+preAdd 0
+o 6
+suid 6,0
+)
+)
+)
+*215 (CptPort
+uid 10458,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10459,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,83625,150750,84375"
+)
+tg (CPTG
+uid 10460,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10461,0
+va (VaSet
+font "courier,8,0"
+)
+xt "129000,83550,149000,84450"
+st "event_data_o : (g_EVENT_DATA_WIDTH-1:0)"
+ju 2
+blo "149000,84250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "event_data_o"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 20
+suid 7,0
+)
+)
+)
+*216 (CptPort
+uid 10462,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10463,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,79625,98000,80375"
+)
+tg (CPTG
+uid 10464,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10465,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,79550,106000,80450"
+st "logic_reset_i"
+blo "99000,80250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "goes high to reset counters. Synchronous with clk_4x_logic"
+o 4
+suid 9,0
+)
+)
+)
+*217 (CptPort
+uid 10466,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10467,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,85625,98000,86375"
+)
+tg (CPTG
+uid 10468,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10469,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,85550,123500,86450"
+st "trigger_inputs_fired_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "99000,86250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_inputs_fired_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "high for each input that \"fired\""
+o 7
+suid 10,0
+)
+)
+)
+*218 (CptPort
+uid 10470,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10471,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,86625,98000,87375"
+)
+tg (CPTG
+uid 10472,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10473,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,86550,118000,87450"
+st "edge_fall_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,87250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 14
+suid 11,0
+)
+)
+)
+*219 (CptPort
+uid 10474,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10475,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,87625,98000,88375"
+)
+tg (CPTG
+uid 10476,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10477,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,87550,120500,88450"
+st "edge_fall_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,88250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 16
+suid 12,0
+)
+)
+)
+*220 (CptPort
+uid 10478,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10479,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,88625,98000,89375"
+)
+tg (CPTG
+uid 10480,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10481,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,88550,118000,89450"
+st "edge_rise_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,89250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 13
+suid 13,0
+)
+)
+)
+*221 (CptPort
+uid 10482,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10483,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,89625,98000,90375"
+)
+tg (CPTG
+uid 10484,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10485,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,89550,120500,90450"
+st "edge_rise_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,90250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 15
+suid 14,0
+)
+)
+)
+*222 (CptPort
+uid 10486,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10487,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,81625,98000,82375"
+)
+tg (CPTG
+uid 10488,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10489,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,81550,105000,82450"
+st "ipbus_clk_i"
+blo "99000,82250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 15,0
+)
+)
+)
+*223 (CptPort
+uid 10490,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10491,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,82625,98000,83375"
+)
+tg (CPTG
+uid 10492,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10493,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,82550,102500,83450"
+st "ipbus_i"
+blo "99000,83250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+preAdd 0
+o 17
+suid 16,0
+)
+)
+)
+*224 (CptPort
+uid 10494,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10495,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,95625,150750,96375"
+)
+tg (CPTG
+uid 10496,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10497,0
+va (VaSet
+font "courier,8,0"
+)
+xt "145500,95550,149000,96450"
+st "ipbus_o"
+ju 2
+blo "149000,96250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+o 18
+suid 17,0
+)
+)
+)
+*225 (CptPort
+uid 10498,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10499,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,92625,98000,93375"
+)
+tg (CPTG
+uid 10500,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10501,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,92550,118000,93450"
+st "shutter_cnt_i : (g_COUNTER_WIDTH-1:0)"
+blo "99000,93250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 10
+suid 18,0
+)
+)
+)
+*226 (CptPort
+uid 10502,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10503,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,95625,98000,96375"
+)
+tg (CPTG
+uid 10504,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10505,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,95550,103500,96450"
+st "shutter_i"
+blo "99000,96250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 9
+suid 19,0
+)
+)
+)
+*227 (CptPort
+uid 10506,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10507,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,98625,98000,99375"
+)
+tg (CPTG
+uid 10508,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10509,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,98550,117000,99450"
+st "spill_cnt_i : (g_COUNTER_WIDTH-1:0)"
+blo "99000,99250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 12
+suid 20,0
+)
+)
+)
+*228 (CptPort
+uid 10510,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10511,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,101625,98000,102375"
+)
+tg (CPTG
+uid 10512,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10513,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,101550,102500,102450"
+st "spill_i"
+blo "99000,102250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 11
+suid 21,0
+)
+)
+)
+*229 (CptPort
+uid 10514,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10515,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,104625,98000,105375"
+)
+tg (CPTG
+uid 10516,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10517,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,104550,120500,105450"
+st "trigger_cnt_i : (g_COUNTER_TRIG_WIDTH-1:0)"
+blo "99000,105250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_TRIG_WIDTH-1 DOWNTO 0)"
+o 8
+suid 22,0
+)
+)
+)
+*230 (CptPort
+uid 10518,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10519,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,91625,150750,92375"
+)
+tg (CPTG
+uid 10520,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10521,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130500,91550,149000,92450"
+st "event_number_i : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "149000,92250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "event_number_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 21
+suid 23,0
+)
+)
+)
+]
+shape (Rectangle
+uid 10523,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "98000,65000,150000,108000"
+)
+oxt "16000,18000,68000,51000"
+ttg (MlTextGroup
+uid 10524,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*231 (Text
+uid 10525,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,70100,108750,71000"
+st "work"
+blo "106750,70800"
+tm "BdLibraryNameMgr"
+)
+*232 (Text
+uid 10526,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,71000,114250,71900"
+st "eventFormatter"
+blo "106750,71700"
+tm "CptNameMgr"
+)
+*233 (Text
+uid 10527,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,71900,107750,72800"
+st "I2"
+blo "106750,72600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 10528,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 10529,0
+text (MLText
+uid 10530,0
+va (VaSet
+font "courier,8,0"
+)
+xt "98000,56800,157000,64000"
+st "g_EVENT_DATA_WIDTH = g_EVENT_DATA_WIDTH ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive )
+g_COUNTER_TRIG_WIDTH = g_IPBUS_WIDTH ( positive )
+g_COUNTER_WIDTH = 12 ( positive )
+g_EVTTYPE_WIDTH = 4 ( positive ) -- Width of the event type word
+--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+g_NUM_EDGE_INPUTS = g_NUM_EDGE_INPUTS ( positive ) -- Number of edge inputs
+g_NUM_TRIG_INPUTS = g_NUM_TRIG_INPUTS ( positive ) -- Number of trigger inputs "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_TRIG_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+(GiElement
+name "g_EVTTYPE_WIDTH"
+type "positive"
+value "4"
+e "-- Width of the event type word"
+)
+(GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "g_NUM_EDGE_INPUTS"
+pr "--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)"
+apr 0
+e "-- Number of edge inputs"
+)
+(GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+e "-- Number of trigger inputs"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 10531,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "98250,106250,99750,107750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*234 (Net
+uid 10532,0
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 44
+suid 158,0
+)
+declText (MLText
+uid 10533,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,55600,9500,56500"
+st "SIGNAL ipbus_clk_i : std_logic
+"
+)
+)
+*235 (Net
+uid 10562,0
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 36
+suid 161,0
+)
+declText (MLText
+uid 10563,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,48400,42000,49300"
+st "SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- ! High when falling edge
+"
+)
+)
+*236 (Net
+uid 10570,0
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 37
+suid 162,0
+)
+declText (MLText
+uid 10571,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,49300,52000,50200"
+st "SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+)
+*237 (Net
+uid 10578,0
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 38
+suid 163,0
+)
+declText (MLText
+uid 10579,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,50200,41500,51100"
+st "SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- ! High when rising edge
+"
+)
+)
+*238 (Net
+uid 10586,0
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 39
+suid 164,0
+)
+declText (MLText
+uid 10587,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,51100,52000,52000"
+st "SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+)
+*239 (Net
+uid 10594,0
+lang 11
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 54
+suid 165,0
+)
+declText (MLText
+uid 10595,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,64600,30000,65500"
+st "SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*240 (Net
+uid 10602,0
+lang 11
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 55
+suid 166,0
+)
+declText (MLText
+uid 10603,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,65500,9500,66400"
+st "SIGNAL shutter_i : std_logic
+"
+)
+)
+*241 (Net
+uid 10610,0
+lang 11
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 56
+suid 167,0
+)
+declText (MLText
+uid 10611,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,66400,30000,67300"
+st "SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*242 (Net
+uid 10618,0
+lang 11
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 57
+suid 168,0
+)
+declText (MLText
+uid 10619,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,67300,9500,68200"
+st "SIGNAL spill_i : std_logic
+"
+)
+)
+*243 (Net
+uid 10626,0
+lang 11
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 60
+suid 169,0
+)
+declText (MLText
+uid 10627,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,70000,26000,70900"
+st "SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*244 (SaComponent
+uid 11070,0
+optionalChildren [
+*245 (CptPort
+uid 11010,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11011,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,43625,165000,44375"
+)
+tg (CPTG
+uid 11012,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11013,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,43550,174500,44450"
+st "clk_logic_xtal_i"
+blo "166000,44250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_logic_xtal_i"
+t "std_logic"
+eolc "! 40MHz clock from onboard xtal"
+o 5
+suid 1,0
+)
+)
+)
+*246 (CptPort
+uid 11014,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 11015,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,36625,165000,37375"
+)
+tg (CPTG
+uid 11016,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11017,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,36550,171500,37450"
+st "extclk_p_b"
+blo "166000,37250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "either external clock in, or a clock being driven out"
+preAdd 0
+o 11
+suid 2,0
+)
+)
+)
+*247 (CptPort
+uid 11018,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11019,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,35625,196750,36375"
+)
+tg (CPTG
+uid 11020,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11021,0
+va (VaSet
+font "courier,8,0"
+)
+xt "187500,35550,195000,36450"
+st "clk_4x_logic_o"
+ju 2
+blo "195000,36250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_4x_logic_o"
+t "std_logic"
+eolc "160MHz clock"
+preAdd 0
+o 7
+suid 3,0
+)
+)
+)
+*248 (CptPort
+uid 11022,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11023,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,38625,196750,39375"
+)
+tg (CPTG
+uid 11024,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11025,0
+va (VaSet
+font "courier,8,0"
+)
+xt "186000,38550,195000,39450"
+st "strobe_4x_logic_o"
+ju 2
+blo "195000,39250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "strobe_4x_logic_o"
+t "std_logic"
+eolc "-- one pulse every 4 cycles of clk_4x"
+preAdd 0
+posAdd 0
+o 10
+suid 4,0
+)
+)
+)
+*249 (CptPort
+uid 11026,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11027,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,41625,196750,42375"
+)
+tg (CPTG
+uid 11028,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11029,0
+va (VaSet
+font "courier,8,0"
+)
+xt "187000,41550,195000,42450"
+st "clk_16x_logic_o"
+ju 2
+blo "195000,42250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_16x_logic_o"
+t "std_logic"
+eolc "-- 640MHz clock"
+posAdd 0
+o 6
+suid 5,0
+)
+)
+)
+*250 (CptPort
+uid 11030,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11031,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,43625,196750,44375"
+)
+tg (CPTG
+uid 11032,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11033,0
+va (VaSet
+font "courier,8,0"
+)
+xt "185500,43550,195000,44450"
+st "strobe_16x_logic_o"
+ju 2
+blo "195000,44250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "strobe_16x_logic_o"
+t "std_logic"
+eolc "-- strobes once every 4 cycles of clk_16x"
+posAdd 0
+o 9
+suid 6,0
+)
+)
+)
+*251 (CptPort
+uid 11034,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11035,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,46625,165000,47375"
+)
+tg (CPTG
+uid 11036,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11037,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,46550,172000,47450"
+st "ipbus_clk_i"
+blo "166000,47250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 1
+suid 7,0
+)
+)
+)
+*252 (CptPort
+uid 11038,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11039,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,50625,165000,51375"
+)
+tg (CPTG
+uid 11040,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11041,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,50550,169500,51450"
+st "ipbus_i"
+blo "166000,51250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+o 2
+suid 8,0
+)
+)
+)
+*253 (CptPort
+uid 11042,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11043,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,46625,196750,47375"
+)
+tg (CPTG
+uid 11044,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11045,0
+va (VaSet
+font "courier,8,0"
+)
+xt "191500,46550,195000,47450"
+st "ipbus_o"
+ju 2
+blo "195000,47250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+o 8
+suid 9,0
+)
+)
+)
+*254 (CptPort
+uid 11046,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11047,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,53625,165000,54375"
+)
+tg (CPTG
+uid 11048,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11049,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,53550,173000,54450"
+st "ipbus_reset_i"
+blo "166000,54250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 3
+suid 10,0
+)
+)
+)
+*255 (CptPort
+uid 11050,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 11051,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,39625,165000,40375"
+)
+tg (CPTG
+uid 11052,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11053,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,39550,171500,40450"
+st "extclk_n_b"
+blo "166000,40250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 12
+suid 11,0
+)
+)
+)
+*256 (CptPort
+uid 11054,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11055,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,48625,196750,49375"
+)
+tg (CPTG
+uid 11056,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11057,0
+va (VaSet
+font "courier,8,0"
+)
+xt "189000,48550,195000,49450"
+st "clk_logic_o"
+ju 2
+blo "195000,49250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_logic_o"
+t "std_logic"
+o 13
+suid 13,0
+)
+)
+)
+*257 (CptPort
+uid 11058,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11059,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,51625,196750,52375"
+)
+tg (CPTG
+uid 11060,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11061,0
+va (VaSet
+font "courier,8,0"
+)
+xt "184000,51550,195000,52450"
+st "logic_clocks_locked_o"
+ju 2
+blo "195000,52250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "logic_clocks_locked_o"
+t "std_logic"
+o 14
+suid 14,0
+)
+)
+)
+*258 (CptPort
+uid 11062,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11063,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,54625,196750,55375"
+)
+tg (CPTG
+uid 11064,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11065,0
+va (VaSet
+font "courier,8,0"
+)
+xt "188000,54550,195000,55450"
+st "logic_reset_o"
+ju 2
+blo "195000,55250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "logic_reset_o"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 15
+suid 15,0
+)
+)
+)
+*259 (CptPort
+uid 11066,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11067,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,54625,165000,55375"
+)
+tg (CPTG
+uid 11068,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11069,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,54550,169500,55450"
+st "Reset_i"
+blo "166000,55250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "Reset_i"
+t "std_logic"
+o 4
+suid 16,0
+)
+)
+)
+]
+shape (Rectangle
+uid 11071,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "165000,35000,196000,60000"
+)
+oxt "11000,20000,42000,41000"
+ttg (MlTextGroup
+uid 11072,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*260 (Text
+uid 11073,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,37100,178750,38000"
+st "work"
+blo "176750,37800"
+tm "BdLibraryNameMgr"
+)
+*261 (Text
+uid 11074,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,38000,183250,38900"
+st "logic_clocks"
+blo "176750,38700"
+tm "CptNameMgr"
+)
+*262 (Text
+uid 11075,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,38900,177750,39800"
+st "I6"
+blo "176750,39600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 11076,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 11077,0
+text (MLText
+uid 11078,0
+va (VaSet
+font "courier,8,0"
+)
+xt "175000,34000,175000,34000"
+)
+header ""
+)
+elements [
+]
+)
+viewicon (ZoomableIcon
+uid 11079,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "165250,58250,166750,59750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*263 (MWC
+uid 11097,0
+optionalChildren [
+*264 (CptPort
+uid 11088,0
+optionalChildren [
+*265 (Line
+uid 11092,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+)
+xt "154000,55000,155000,55000"
+pts [
+"154000,55000"
+"155000,55000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11089,0
+ro 270
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "153250,54625,154000,55375"
+)
+tg (CPTG
+uid 11090,0
+ps "CptPortTextPlaceStrategy"
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+xt "88450,92795,93950,93695"
+st "moduleware"
+blo "88450,93495"
+)
+*309 (Text
+uid 11196,0
+va (VaSet
+font "courier,8,0"
+)
+xt "88450,93695,89950,94595"
+st "gnd"
+blo "88450,94395"
+)
+*310 (Text
+uid 11197,0
+va (VaSet
+font "courier,8,0"
+)
+xt "88450,94595,89950,95495"
+st "I14"
+blo "88450,95295"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 11198,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 11199,0
+text (MLText
+uid 11200,0
+va (VaSet
+font "courier,8,0"
+)
+xt "81000,72300,81000,72300"
+)
+header ""
+)
+elements [
+]
+)
+sed 1
+awe 1
+portVis (PortSigDisplay
+disp 1
+sN 0
+sTC 0
+selT 0
+)
+prms (Property
+pclass "params"
+pname "params"
+ptn "String"
+)
+visOptions (mwParamsVisibilityOptions
+)
+)
+*311 (Net
+uid 11202,0
+decl (Decl
+n "logic_clocks_reset"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 48
+suid 171,0
+)
+declText (MLText
+uid 11203,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,59200,39000,60100"
+st "SIGNAL logic_clocks_reset : std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
+"
+)
+)
+*312 (PortIoOut
+uid 11458,0
+shape (CompositeShape
+uid 11459,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11460,0
+sl 0
+ro 270
+xt "73500,151625,75000,152375"
+)
+(Line
+uid 11461,0
+sl 0
+ro 270
+xt "73000,152000,73500,152000"
+pts [
+"73000,152000"
+"73500,152000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11462,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11463,0
+va (VaSet
+font "courier,8,0"
+)
+xt "76000,151550,80000,152450"
+st "gpio_hdr"
+blo "76000,152250"
+tm "WireNameMgr"
+)
+)
+)
+*313 (Net
+uid 11470,0
+lang 2
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 20
+suid 172,0
+)
+declText (MLText
+uid 11471,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,33100,15500,34000"
+st "gpio_hdr : std_logic_vector(7 DOWNTO 0)
+"
+)
+)
+*314 (SaComponent
+uid 11619,0
+optionalChildren [
+*315 (CptPort
+uid 11542,0
+optionalChildren [
+*316 (FFT
+pts [
+"13750,127000"
+"13000,127375"
+"13000,126625"
+]
+uid 11546,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "13000,126625,13750,127375"
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11543,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,126625,13000,127375"
+)
+tg (CPTG
+uid 11544,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11545,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,126550,20500,127450"
+st "clk_4x_logic"
+blo "14000,127250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 3
+suid 1,0
+)
+)
+)
+*317 (CptPort
+uid 11547,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11548,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,128625,13000,129375"
+)
+tg (CPTG
+uid 11549,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11550,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,128550,23000,129450"
+st "strobe_4x_logic_i"
+blo "14000,129250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 4
+suid 2,0
+)
+)
+)
+*318 (CptPort
+uid 11551,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11552,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,135625,13000,136375"
+)
+tg (CPTG
+uid 11553,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11554,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,135550,34500,136450"
+st "threshold_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "14000,136250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 5
+suid 3,0
+)
+)
+)
+*319 (CptPort
+uid 11555,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11556,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,139625,13000,140375"
+)
+tg (CPTG
+uid 11557,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11558,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,139550,31500,140450"
+st "cfd_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "14000,140250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 1
+suid 4,0
+)
+)
+)
+*320 (CptPort
+uid 11559,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11560,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,129625,58750,130375"
+)
+tg (CPTG
+uid 11561,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11562,0
+va (VaSet
+font "courier,8,0"
+)
+xt "38500,129550,57000,130450"
+st "trigger_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,130250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 7
+suid 5,0
+)
+)
+)
+*321 (CptPort
+uid 11563,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11564,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,137625,58750,138375"
+)
+tg (CPTG
+uid 11565,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11566,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41500,137550,57000,138450"
+st "trigger_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,138250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger active"
+o 8
+suid 7,0
+)
+)
+)
+*322 (CptPort
+uid 11567,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11568,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,144625,13000,145375"
+)
+tg (CPTG
+uid 11569,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11570,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,144550,20000,145450"
+st "ipbus_clk_i"
+blo "14000,145250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+preAdd 0
+o 14
+suid 8,0
+)
+)
+)
+*323 (CptPort
+uid 11571,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11572,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,147625,13000,148375"
+)
+tg (CPTG
+uid 11573,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11574,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,147550,17500,148450"
+st "ipbus_i"
+blo "14000,148250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 16
+suid 9,0
+)
+)
+)
+*324 (CptPort
+uid 11575,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11576,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,146625,58750,147375"
+)
+tg (CPTG
+uid 11577,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11578,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53500,146550,57000,147450"
+st "ipbus_o"
+ju 2
+blo "57000,147250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 17
+suid 10,0
+)
+)
+)
+*325 (CptPort
+uid 11579,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11580,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,149625,13000,150375"
+)
+tg (CPTG
+uid 11581,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11582,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,149550,21000,150450"
+st "ipbus_reset_i"
+blo "14000,150250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 15
+suid 11,0
+)
+)
+)
+*326 (CptPort
+uid 11583,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11584,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,131625,13000,132375"
+)
+tg (CPTG
+uid 11585,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11586,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,131550,22000,132450"
+st "clk_16x_logic_i"
+blo "14000,132250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_16x_logic_i"
+t "std_logic"
+eolc "--! 640MHz clock ( 16x 40MHz )"
+o 18
+suid 13,0
+)
+)
+)
+*327 (CptPort
+uid 11587,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11588,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,133625,13000,134375"
+)
+tg (CPTG
+uid 11589,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11590,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,133550,23500,134450"
+st "strobe_16x_logic_i"
+blo "14000,134250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_16x_logic_i"
+t "std_logic"
+eolc "--! Pulses one cycle every 4 of 16x clock."
+o 19
+suid 14,0
+)
+)
+)
+*328 (CptPort
+uid 11591,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11592,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,140625,13000,141375"
+)
+tg (CPTG
+uid 11593,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11594,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,140550,31500,141450"
+st "cfd_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "14000,141250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 2
+suid 15,0
+)
+)
+)
+*329 (CptPort
+uid 11595,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11596,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,136625,13000,137375"
+)
+tg (CPTG
+uid 11597,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11598,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,136550,34500,137450"
+st "threshold_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "14000,137250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 6
+suid 16,0
+)
+)
+)
+*330 (CptPort
+uid 11599,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11600,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,147625,58750,148375"
+)
+tg (CPTG
+uid 11601,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11602,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39000,147550,57000,148450"
+st "edge_falling_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,148250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 13
+suid 17,0
+)
+)
+)
+*331 (CptPort
+uid 11603,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11604,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,148625,58750,149375"
+)
+tg (CPTG
+uid 11605,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11606,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36000,148550,57000,149450"
+st "edge_falling_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,149250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 11
+suid 18,0
+)
+)
+)
+*332 (CptPort
+uid 11607,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11608,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,149625,58750,150375"
+)
+tg (CPTG
+uid 11609,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11610,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39500,149550,57000,150450"
+st "edge_rising_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,150250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+preAdd 0
+posAdd 0
+o 12
+suid 19,0
+)
+)
+)
+*333 (CptPort
+uid 11611,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11612,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,150625,58750,151375"
+)
+tg (CPTG
+uid 11613,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11614,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,150550,57000,151450"
+st "edge_rising_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,151250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 10
+suid 20,0
+)
+)
+)
+*334 (CptPort
+uid 11615,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11616,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,151625,58750,152375"
+)
+tg (CPTG
+uid 11617,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11618,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35500,151550,57000,152450"
+st "trigger_debug_o : (((2*g_NUM_INPUTS)-1):0)"
+ju 2
+blo "57000,152250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_debug_o"
+t "std_logic_vector"
+b "( ((2*g_NUM_INPUTS)-1) DOWNTO 0)"
+eolc "-- ! Copy of input trigger level. High bits CFD, Low threshold"
+posAdd 0
+o 9
+suid 21,0
+)
+)
+)
+]
+shape (Rectangle
+uid 11620,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "13000,126000,58000,153000"
+)
+oxt "7000,16000,52000,43000"
+ttg (MlTextGroup
+uid 11621,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*335 (Text
+uid 11622,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,141100,31750,142000"
+st "work"
+blo "29750,141800"
+tm "BdLibraryNameMgr"
+)
+*336 (Text
+uid 11623,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,142000,36750,142900"
+st "triggerInputs"
+blo "29750,142700"
+tm "CptNameMgr"
+)
+*337 (Text
+uid 11624,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,142900,30750,143800"
+st "I1"
+blo "29750,143600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 11625,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 11626,0
+text (MLText
+uid 11627,0
+va (VaSet
+font "courier,8,0"
+)
+xt "26000,124100,51000,125000"
+st "g_NUM_INPUTS = g_NUM_TRIG_INPUTS ( natural ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "natural"
+value "g_NUM_TRIG_INPUTS"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 11628,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "13250,151250,14750,152750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
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+)
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+)
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+)
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+"5000,140000"
+"12250,140000"
+]
+)
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+)
+xt "7000,139100,14000,140000"
+st "cfd_discr_p_i"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"135000,18000"
+"128750,18000"
+]
+)
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+eat 32
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+)
+xt "134000,17100,141500,18000"
+st "gmii_gtx_clk_o"
+blo "134000,17800"
+tm "WireNameMgr"
+)
+)
+on &4
+)
+*340 (Wire
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+)
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+pts [
+"80000,10000"
+"94250,10000"
+]
+)
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+sf 1
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+)
+xt "82000,9100,89000,10000"
+st "gmii_rx_clk_i"
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+tm "WireNameMgr"
+)
+)
+on &6
+)
+*341 (Wire
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+va (VaSet
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+)
+xt "80000,13000,94250,13000"
+pts [
+"80000,13000"
+"94250,13000"
+]
+)
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+sat 32
+eat 32
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+)
+xt "82000,12100,88500,13000"
+st "gmii_rx_dv_i"
+blo "82000,12800"
+tm "WireNameMgr"
+)
+)
+on &8
+)
+*342 (Wire
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+)
+xt "80000,16000,94250,16000"
+pts [
+"80000,16000"
+"94250,16000"
+]
+)
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+end &56
+sat 32
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+st 0
+sf 1
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+font "courier,8,0"
+)
+xt "82000,15100,88500,16000"
+st "gmii_rx_er_i"
+blo "82000,15800"
+tm "WireNameMgr"
+)
+)
+on &10
+)
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+)
+xt "80000,19000,94250,19000"
+pts [
+"80000,19000"
+"94250,19000"
+]
+)
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+sat 32
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+font "courier,8,0"
+)
+xt "82000,18100,87500,19000"
+st "gmii_rxd_i"
+blo "82000,18800"
+tm "WireNameMgr"
+)
+)
+on &12
+)
+*344 (Wire
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+va (VaSet
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+)
+xt "128750,9000,135000,9000"
+pts [
+"135000,9000"
+"128750,9000"
+]
+)
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+eat 32
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+stg "STSignalDisplayStrategy"
+f (Text
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+)
+xt "134000,8100,140500,9000"
+st "gmii_tx_en_o"
+blo "134000,8800"
+tm "WireNameMgr"
+)
+)
+on &14
+)
+*345 (Wire
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+va (VaSet
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+)
+xt "128750,11000,135000,11000"
+pts [
+"135000,11000"
+"128750,11000"
+]
+)
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+eat 32
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+stg "STSignalDisplayStrategy"
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+)
+xt "134000,10100,140500,11000"
+st "gmii_tx_er_o"
+blo "134000,10800"
+tm "WireNameMgr"
+)
+)
+on &16
+)
+*346 (Wire
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+)
+xt "128750,14000,135000,14000"
+pts [
+"135000,14000"
+"128750,14000"
+]
+)
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+stg "STSignalDisplayStrategy"
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+font "courier,8,0"
+)
+xt "134000,13100,139500,14000"
+st "gmii_txd_o"
+blo "134000,13800"
+tm "WireNameMgr"
+)
+)
+on &18
+)
+*347 (Wire
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+)
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+pts [
+"217000,15000"
+"211750,15000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
+f (Text
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+)
+xt "216000,14100,220500,15000"
+st "i2c_scl_b"
+blo "216000,14800"
+tm "WireNameMgr"
+)
+)
+on &19
+)
+*348 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "211750,13000,217000,13000"
+pts [
+"217000,13000"
+"211750,13000"
+]
+)
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+st 0
+sf 1
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+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "219000,12100,223500,13000"
+st "i2c_sda_b"
+blo "219000,12800"
+tm "WireNameMgr"
+)
+)
+on &21
+)
+*349 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "128750,16000,135000,16000"
+pts [
+"135000,16000"
+"128750,16000"
+]
+)
+start &22
+end &61
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
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+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,15100,139500,16000"
+st "phy_rstb_o"
+blo "134000,15800"
+tm "WireNameMgr"
+)
+)
+on &23
+)
+*350 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "5000,136000,12250,136000"
+pts [
+"5000,136000"
+"12250,136000"
+]
+)
+start &24
+end &318
+sat 32
+eat 32
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+sf 1
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+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 258,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "7000,135100,17000,136000"
+st "threshold_discr_p_i"
+blo "7000,135800"
+tm "WireNameMgr"
+)
+)
+on &25
+)
+*351 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "80000,22000,94250,22000"
+pts [
+"80000,22000"
+"94250,22000"
+]
+)
+start &37
+end &63
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
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+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,21100,87500,22000"
+st "sysclk_n_i"
+blo "82000,21800"
+tm "WireNameMgr"
+)
+)
+on &114
+)
+*352 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "80000,25000,94250,25000"
+pts [
+"80000,25000"
+"94250,25000"
+]
+)
+start &38
+end &64
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 770,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,24100,87500,25000"
+st "sysclk_p_i"
+blo "82000,24800"
+tm "WireNameMgr"
+)
+)
+on &113
+)
+*353 (Wire
+uid 1215,0
+shape (OrthoPolyLine
+uid 1216,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,101000,9250,101000"
+pts [
+"9250,101000"
+"-4000,101000"
+]
+)
+start &139
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1219,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1220,0
+va (VaSet
+font "courier,8,0"
+)
+xt "250,100100,8250,101000"
+st "strobe_4x_logic"
+blo "250,100800"
+tm "WireNameMgr"
+)
+)
+on &81
+)
+*354 (Wire
+uid 1304,0
+shape (OrthoPolyLine
+uid 1305,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,99000,9250,99000"
+pts [
+"-4000,99000"
+"9250,99000"
+]
+)
+end &138
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1308,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1309,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,98100,4500,99000"
+st "clk_4x_logic"
+blo "-2000,98800"
+tm "WireNameMgr"
+)
+)
+on &39
+)
+*355 (Wire
+uid 1359,0
+shape (OrthoPolyLine
+uid 1360,0
+va (VaSet
+vasetType 3
+)
+xt "128750,20000,136000,20000"
+pts [
+"128750,20000"
+"136000,20000"
+]
+)
+start &65
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1364,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130750,19100,135250,20000"
+st "ipbus_clk"
+blo "130750,19800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*356 (Wire
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+shape (OrthoPolyLine
+uid 1368,0
+va (VaSet
+vasetType 3
+)
+xt "128750,23000,136000,23000"
+pts [
+"128750,23000"
+"136000,23000"
+]
+)
+start &66
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1371,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1372,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130750,22100,135250,23000"
+st "ipbus_rst"
+blo "130750,22800"
+tm "WireNameMgr"
+)
+)
+on &154
+)
+*357 (Wire
+uid 1383,0
+shape (OrthoPolyLine
+uid 1384,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "128750,25000,136000,25000"
+pts [
+"128750,25000"
+"136000,25000"
+]
+)
+start &67
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+tg (WTG
+uid 1387,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1388,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,24100,145000,25000"
+st "ipbw : (g_NUM_EXT_SLAVES-1:0)"
+blo "130000,24800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*358 (Wire
+uid 1391,0
+shape (OrthoPolyLine
+uid 1392,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "79000,28000,94250,28000"
+pts [
+"94250,28000"
+"79000,28000"
+]
+)
+start &68
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1396,0
+va (VaSet
+font "courier,8,0"
+)
+xt "80000,27100,95000,28000"
+st "ipbr : (g_NUM_EXT_SLAVES-1:0)"
+blo "80000,27800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
+*359 (Wire
+uid 1415,0
+shape (OrthoPolyLine
+uid 1416,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,105000,9250,105000"
+pts [
+"9250,105000"
+"-4000,105000"
+]
+)
+start &141
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1419,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1420,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,104100,2500,105000"
+st "ipbus_clk"
+blo "-2000,104800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*360 (Wire
+uid 1423,0
+shape (OrthoPolyLine
+uid 1424,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,107000,9250,107000"
+pts [
+"9250,107000"
+"-4000,107000"
+]
+)
+start &142
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1427,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1428,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,106100,4000,107000"
+st "ipbus_reset"
+blo "-2000,106800"
+tm "WireNameMgr"
+)
+)
+on &41
+)
+*361 (Wire
+uid 1672,0
+shape (OrthoPolyLine
+uid 1673,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-4000,109000,9250,109000"
+pts [
+"-4000,109000"
+"9250,109000"
+]
+)
+end &143
+sat 16
+eat 32
+sty 1
+sl "(0)"
+st 0
+sf 1
+tg (WTG
+uid 1676,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1677,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,108100,14500,109000"
+st "ipbw(0) : (g_NUM_EXT_SLAVES-1:0)"
+blo "-2000,108800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*362 (Wire
+uid 1680,0
+shape (OrthoPolyLine
+uid 1681,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55750,104000,65000,104000"
+pts [
+"55750,104000"
+"65000,104000"
+]
+)
+start &144
+sat 32
+eat 16
+sty 1
+sl "(0)"
+st 0
+sf 1
+tg (WTG
+uid 1684,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1685,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,103100,74500,104000"
+st "ipbr(0) : (g_NUM_EXT_SLAVES-1:0)"
+blo "58000,103800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
+*363 (Wire
+uid 1698,0
+shape (OrthoPolyLine
+uid 1699,0
+va (VaSet
+vasetType 3
+)
+xt "2000,127000,12250,127000"
+pts [
+"2000,127000"
+"12250,127000"
+]
+)
+end &315
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1702,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1703,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,126100,10500,127000"
+st "clk_4x_logic"
+blo "4000,126800"
+tm "WireNameMgr"
+)
+)
+on &39
+)
+*364 (Wire
+uid 1706,0
+shape (OrthoPolyLine
+uid 1707,0
+va (VaSet
+vasetType 3
+)
+xt "2000,129000,12250,129000"
+pts [
+"2000,129000"
+"12250,129000"
+]
+)
+end &317
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1710,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1711,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,128100,12000,129000"
+st "strobe_4x_logic"
+blo "4000,128800"
+tm "WireNameMgr"
+)
+)
+on &81
+)
+*365 (Wire
+uid 1714,0
+shape (OrthoPolyLine
+uid 1715,0
+va (VaSet
+vasetType 3
+)
+xt "2000,145000,12250,145000"
+pts [
+"2000,145000"
+"12250,145000"
+]
+)
+end &322
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1718,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1719,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,144100,7500,145000"
+st "ipbus_clk"
+blo "3000,144800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*366 (Wire
+uid 1722,0
+shape (OrthoPolyLine
+uid 1723,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "2000,148000,12250,148000"
+pts [
+"2000,148000"
+"12250,148000"
+]
+)
+end &323
+sat 16
+eat 32
+sty 1
+sl "(1)"
+st 0
+sf 1
+tg (WTG
+uid 1726,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1727,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,147100,20500,148000"
+st "ipbw(1) : (g_NUM_EXT_SLAVES-1:0)"
+blo "4000,147800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*367 (Wire
+uid 1730,0
+shape (OrthoPolyLine
+uid 1731,0
+va (VaSet
+vasetType 3
+)
+xt "2000,150000,12250,150000"
+pts [
+"2000,150000"
+"12250,150000"
+]
+)
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+sf 1
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+)
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+st "ipbus_reset"
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+)
+)
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+)
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+)
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+pts [
+"143750,150000"
+"160000,150000"
+]
+)
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+)
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+st "ipbr(2) : (g_NUM_EXT_SLAVES-1:0)"
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+)
+)
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+)
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+)
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+pts [
+"105250,132000"
+"98000,132000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"105250,135000"
+"98000,135000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"105250,140000"
+"87000,140000"
+"87000,122000"
+"84000,122000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"105250,143000"
+"98000,143000"
+]
+)
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+)
+xt "98250,142100,102750,143000"
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+)
+)
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+)
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+)
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+pts [
+"105250,145000"
+"98000,145000"
+]
+)
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+)
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+st "ipbw(2) : (g_NUM_EXT_SLAVES-1:0)"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"105250,148000"
+"98000,148000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"9250,97000"
+"-4000,97000"
+]
+)
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
+xt "71600,137600,72400,138400"
+radius 400
+)
+)
+]
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+)
+xt "58750,138000,105250,138000"
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+"58750,138000"
+"105250,138000"
+]
+)
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"58750,147000"
+"74000,147000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"9250,103000"
+"-4000,103000"
+]
+)
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"97250,67000"
+"85000,67000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,70000"
+"85000,70000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"97250,73000"
+"86000,73000"
+]
+)
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+)
+xt "87000,72100,95000,73000"
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+tm "WireNameMgr"
+)
+)
+on &81
+)
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+)
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+"150750,69000"
+"158000,69000"
+"165250,69000"
+]
+)
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+)
+xt "158750,67100,164750,68000"
+st "data_strobe"
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+tm "WireNameMgr"
+)
+)
+on &48
+)
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+)
+xt "198000,4000,208000,4000"
+pts [
+"198000,4000"
+"208000,4000"
+]
+)
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+sf 1
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+)
+xt "200000,3100,207500,4000"
+st "leds_o : (3:0)"
+blo "200000,3800"
+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"58750,130000"
+"69000,130000"
+"69000,76000"
+"97250,76000"
+]
+)
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+)
+xt "71000,75100,91000,76000"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"150750,84000"
+"155000,84000"
+"155000,77000"
+"165250,77000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"150750,76000"
+"151000,76000"
+"151000,74000"
+"165250,74000"
+]
+)
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+)
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+st "trigger_count"
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+tm "WireNameMgr"
+)
+)
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+)
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+va (VaSet
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+)
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+pts [
+"165250,72000"
+"155000,72000"
+]
+)
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+sf 1
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"165250,79000"
+"157000,79000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
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+)
+xt "159000,78100,163500,79000"
+st "ipbus_clk"
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+tm "WireNameMgr"
+)
+)
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+)
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+va (VaSet
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+)
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+pts [
+"165250,84000"
+"157000,84000"
+]
+)
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+sf 1
+tg (WTG
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+stg "STSignalDisplayStrategy"
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+)
+xt "159000,83100,165000,84000"
+st "ipbus_reset"
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+tm "WireNameMgr"
+)
+)
+on &41
+)
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "157000,81000,165250,81000"
+pts [
+"165250,81000"
+"157000,81000"
+]
+)
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+sat 32
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+sl "(3)"
+st 0
+sf 1
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
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+va (VaSet
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+)
+xt "159000,80100,175500,81000"
+st "ipbw(3) : (g_NUM_EXT_SLAVES-1:0)"
+blo "159000,80800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
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+)
+xt "209750,74000,219000,74000"
+pts [
+"209750,74000"
+"219000,74000"
+]
+)
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+sf 1
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+)
+xt "211000,73100,227500,74000"
+st "ipbr(3) : (g_NUM_EXT_SLAVES-1:0)"
+blo "211000,73800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "196750,36000,219000,36000"
+pts [
+"196750,36000"
+"219000,36000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
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+va (VaSet
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+)
+xt "198750,35100,205250,36000"
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+blo "198750,35800"
+tm "WireNameMgr"
+)
+)
+on &39
+)
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "196750,39000,219000,39000"
+pts [
+"196750,39000"
+"219000,39000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
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+va (VaSet
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+)
+xt "198750,38100,206750,39000"
+st "strobe_4x_logic"
+blo "198750,38800"
+tm "WireNameMgr"
+)
+)
+on &81
+)
+*395 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "196750,42000,219000,42000"
+pts [
+"196750,42000"
+"219000,42000"
+]
+)
+start &249
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+eat 16
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+sf 1
+tg (WTG
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+)
+xt "198750,41100,205750,42000"
+st "clk_16x_logic"
+blo "198750,41800"
+tm "WireNameMgr"
+)
+)
+on &82
+)
+*396 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+)
+xt "196750,44000,219000,44000"
+pts [
+"196750,44000"
+"219000,44000"
+]
+)
+start &250
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+eat 16
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+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+)
+xt "198750,43100,207250,44000"
+st "strobe_16x_logic"
+blo "198750,43800"
+tm "WireNameMgr"
+)
+)
+on &83
+)
+*397 (Wire
+uid 4599,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "196750,47000,219000,47000"
+pts [
+"196750,47000"
+"219000,47000"
+]
+)
+start &253
+sat 32
+eat 16
+sty 1
+sl "(4)"
+st 0
+sf 1
+tg (WTG
+uid 4603,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 4604,0
+va (VaSet
+font "courier,8,0"
+)
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+)
+)
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+)
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+)
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+pts [
+"164250,54000"
+"155000,54000"
+]
+)
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+sf 1
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+)
+xt "156250,53100,162250,54000"
+st "ipbus_reset"
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+tm "WireNameMgr"
+)
+)
+on &41
+)
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+)
+xt "155000,51000,164250,51000"
+pts [
+"164250,51000"
+"155000,51000"
+]
+)
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+)
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+st "ipbw(4) : (g_NUM_EXT_SLAVES-1:0)"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"164250,47000"
+"155000,47000"
+]
+)
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+sf 1
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+)
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+)
+)
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+)
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+)
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+pts [
+"164250,44000"
+"155000,44000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"157000,37000"
+"164250,37000"
+]
+)
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+)
+xt "159000,36100,164500,37000"
+st "extclk_p_b"
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+)
+)
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+)
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+)
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+pts [
+"157000,40000"
+"164250,40000"
+]
+)
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+end &255
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+)
+xt "159000,39100,164500,40000"
+st "extclk_n_b"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"128750,32000"
+"136000,32000"
+]
+)
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+)
+xt "130750,31100,138250,32000"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"165250,86000"
+"157000,86000"
+]
+)
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+)
+xt "155250,85100,163250,86000"
+st "strobe_4x_logic"
+blo "155250,85800"
+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"55750,108000"
+"74000,108000"
+"74000,123000"
+"78000,123000"
+]
+)
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+sf 1
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+)
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+st "veto_o"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"209750,85000"
+"211000,85000"
+"211000,117000"
+"77000,117000"
+"77000,121000"
+"78000,121000"
+]
+)
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+end &88
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+st 0
+sf 1
+tg (WTG
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"12250,132000"
+"2000,132000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
+f (Text
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+)
+xt "3250,131100,10250,132000"
+st "clk_16x_logic"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"12250,134000"
+"2000,134000"
+]
+)
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+stg "STSignalDisplayStrategy"
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+)
+xt "1250,133100,9750,134000"
+st "strobe_16x_logic"
+blo "1250,133800"
+tm "WireNameMgr"
+)
+)
+on &83
+)
+*410 (Wire
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+)
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+pts [
+"5000,141000"
+"12250,141000"
+]
+)
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+sat 32
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+)
+xt "6000,140100,13000,141000"
+st "cfd_discr_n_i"
+blo "6000,140800"
+tm "WireNameMgr"
+)
+)
+on &110
+)
+*411 (Wire
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+)
+xt "5000,137000,12250,137000"
+pts [
+"5000,137000"
+"12250,137000"
+]
+)
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+sat 32
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+)
+xt "3000,136100,13000,137000"
+st "threshold_discr_n_i"
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+tm "WireNameMgr"
+)
+)
+on &112
+)
+*412 (Wire
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+)
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+pts [
+"128750,30000"
+"136000,30000"
+]
+)
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+)
+xt "130750,29100,139750,30000"
+st "leds_o(2) : (3:0)"
+blo "130750,29800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
+*413 (Wire
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+)
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+pts [
+"128750,27000"
+"136000,27000"
+]
+)
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+sat 32
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+f (Text
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+)
+xt "130750,26100,139750,27000"
+st "leds_o(3) : (3:0)"
+blo "130750,26800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
+*414 (Wire
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+lineWidth 2
+)
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+pts [
+"196750,52000"
+"219000,52000"
+]
+)
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+)
+xt "198750,51100,207750,52000"
+st "leds_o(1) : (3:0)"
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+tm "WireNameMgr"
+)
+)
+on &50
+)
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+)
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+pts [
+"143750,142000"
+"160000,142000"
+]
+)
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+)
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+st "leds_o(0) : (3:0)"
+blo "145750,141800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
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+)
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+pts [
+"55750,90000"
+"64000,90000"
+]
+)
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+)
+xt "56000,89100,72000,90000"
+st "triggers_p_o : (g_NUM_DUTS-1:0)"
+blo "56000,89800"
+tm "WireNameMgr"
+)
+)
+on &116
+)
+*417 (Wire
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+)
+xt "0,89000,9250,89000"
+pts [
+"0,89000"
+"9250,89000"
+]
+)
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+)
+xt "1000,88100,15000,89000"
+st "busy_p_i : (g_NUM_DUTS-1:0)"
+blo "1000,88800"
+tm "WireNameMgr"
+)
+)
+on &118
+)
+*418 (Wire
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+)
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+pts [
+"55750,97000"
+"64000,97000"
+]
+)
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+sf 1
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,96100,74000,97000"
+st "reset_or_clk_p_o : (g_NUM_DUTS-1:0)"
+blo "56000,96800"
+tm "WireNameMgr"
+)
+)
+on &120
+)
+*419 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "0,93000,9250,93000"
+pts [
+"0,93000"
+"9250,93000"
+]
+)
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+end &136
+sat 32
+eat 32
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+st 0
+sf 1
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+f (Text
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+va (VaSet
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+)
+xt "1000,92100,16500,93000"
+st "dut_clk_p_i : (g_NUM_DUTS-1:0)"
+blo "1000,92800"
+tm "WireNameMgr"
+)
+)
+on &122
+)
+*420 (Wire
+uid 6778,0
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "0,91000,9250,91000"
+pts [
+"0,91000"
+"9250,91000"
+]
+)
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+end &147
+sat 32
+eat 32
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+sf 1
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+stg "STSignalDisplayStrategy"
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+va (VaSet
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+)
+xt "1000,90100,15000,91000"
+st "busy_n_i : (g_NUM_DUTS-1:0)"
+blo "1000,90800"
+tm "WireNameMgr"
+)
+)
+on &125
+)
+*421 (Wire
+uid 6792,0
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "55750,99000,64000,99000"
+pts [
+"55750,99000"
+"64000,99000"
+]
+)
+start &148
+end &126
+ss 0
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+eat 32
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+sf 1
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+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,98100,74000,99000"
+st "reset_or_clk_n_o : (g_NUM_DUTS-1:0)"
+blo "56000,98800"
+tm "WireNameMgr"
+)
+)
+on &127
+)
+*422 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "55750,92000,64000,92000"
+pts [
+"55750,92000"
+"64000,92000"
+]
+)
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+end &128
+sat 32
+eat 32
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+st 0
+sf 1
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,91100,72000,92000"
+st "triggers_n_o : (g_NUM_DUTS-1:0)"
+blo "56000,91800"
+tm "WireNameMgr"
+)
+)
+on &129
+)
+*423 (Wire
+uid 6820,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "0,95000,9250,95000"
+pts [
+"0,95000"
+"9250,95000"
+]
+)
+start &130
+end &149
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "1000,94100,16500,95000"
+st "dut_clk_n_i : (g_NUM_DUTS-1:0)"
+blo "1000,94800"
+tm "WireNameMgr"
+)
+)
+on &131
+)
+*424 (Wire
+uid 6914,0
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "80000,31000,94250,31000"
+pts [
+"80000,31000"
+"94250,31000"
+]
+)
+start &153
+end &71
+es 0
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+eat 32
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+sf 1
+si 0
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+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "86000,30100,96500,31000"
+st "dip_switch_i : (3:0)"
+blo "86000,30800"
+tm "WireNameMgr"
+)
+)
+on &123
+)
+*425 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "160000,10000,171250,10000"
+pts [
+"171250,10000"
+"160000,10000"
+]
+)
+start &191
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8091,0
+va (VaSet
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+)
+xt "164250,9100,168750,10000"
+st "ipbus_clk"
+blo "164250,9800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*426 (Wire
+uid 8094,0
+shape (OrthoPolyLine
+uid 8095,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "160000,17000,171250,17000"
+pts [
+"160000,17000"
+"171250,17000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"160000,24000"
+"171250,24000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"205000,10000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"143750,137000"
+"160000,137000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"72000,138000"
+"72000,86000"
+"97250,86000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"143750,146000"
+"165000,146000"
+"165000,92000"
+"150750,92000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,55000"
+"219000,55000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"165250,89000"
+"157000,89000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,80000"
+"85000,80000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"98000,151000"
+]
+)
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+)
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+)
+)
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+)
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+"196750,19000"
+"206000,19000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,21000"
+"206000,21000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"206000,23000"
+]
+)
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+)
+)
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+)
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+)
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+"196750,25000"
+"206000,25000"
+]
+)
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+)
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+)
+)
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+)
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+"85000,82000"
+]
+)
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+)
+)
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+)
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+)
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+"97250,83000"
+"85000,83000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"150750,96000"
+"163000,96000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,87000"
+"91000,87000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,88000"
+"91000,88000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,89000"
+"91000,89000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,90000"
+"91000,90000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"97250,93000"
+"89000,93000"
+]
+)
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+)
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+st "shutter_cnt_i : (g_SPILL_COUNTER_WIDTH-1:0)"
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+)
+)
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+)
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+)
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+"97250,96000"
+"89000,96000"
+]
+)
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+)
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+)
+)
+on &240
+)
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+)
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+"97250,99000"
+"89000,99000"
+]
+)
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+)
+xt "76000,98100,97000,99000"
+st "spill_cnt_i : (g_SPILL_COUNTER_WIDTH-1:0)"
+blo "76000,98800"
+tm "WireNameMgr"
+)
+)
+on &241
+)
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+va (VaSet
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+)
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+pts [
+"97250,102000"
+"89000,102000"
+]
+)
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+end &280
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+)
+xt "90250,101100,93750,102000"
+st "spill_i"
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+tm "WireNameMgr"
+)
+)
+on &242
+)
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+)
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+"97250,105000"
+"89000,105000"
+]
+)
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+)
+xt "72250,104100,90250,105000"
+st "trigger_cnt_i : (g_IPBUS_WIDTH-1:0)"
+blo "72250,104800"
+tm "WireNameMgr"
+)
+)
+on &243
+)
+*452 (Wire
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+va (VaSet
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+)
+xt "154000,55000,164250,55000"
+pts [
+"154000,55000"
+"164250,55000"
+]
+)
+start &264
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+)
+xt "147000,57100,156500,58000"
+st "logic_clocks_reset"
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+tm "WireNameMgr"
+)
+)
+on &311
+)
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+)
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+"58750,152000"
+"73000,152000"
+]
+)
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+)
+xt "60750,151100,69250,152000"
+st "gpio_hdr : (7:0)"
+blo "60750,151800"
+tm "WireNameMgr"
+)
+)
+on &313
+)
+]
+bg "65535,65535,65535"
+grid (Grid
+origin "0,0"
+isVisible 1
+isActive 1
+xSpacing 1000
+xySpacing 1000
+xShown 1
+yShown 1
+color "26368,26368,26368"
+)
+packageList *454 (PackageList
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+)
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+)
+*456 (MLText
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+va (VaSet
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+)
+xt "-13000,900,3000,10800"
+st "LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+LIBRARY work;
+USE work.ipbus.all;
+USE work.emac_hostbus_decl.all;
+
+USE work.fmcTLU.all;
+LIBRARY unisim;
+USE unisim.vcomponents.all;"
+tm "PackageList"
+)
+]
+)
+compDirBlock (MlTextGroup
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+stg "VerticalLayoutStrategy"
+textVec [
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+)
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+blo "20000,700"
+)
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+)
+xt "20000,900,31500,1800"
+st "Pre-module directives:"
+blo "20000,1600"
+)
+*459 (MLText
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+preUserLabel (Text
+uid 4,0
+va (VaSet
+isHidden 1
+font "courier,8,1"
+)
+xt "-12000,14200,-7500,15100"
+st "Pre User:"
+blo "-12000,14900"
+)
+preUserText (MLText
+uid 5,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "-12000,14200,-12000,14200"
+tm "BdDeclarativeTextMgr"
+)
+diagSignalLabel (Text
+uid 6,0
+va (VaSet
+font "courier,8,1"
+)
+xt "-12000,43000,-3500,43900"
+st "Diagram Signals:"
+blo "-12000,43700"
+)
+postUserLabel (Text
+uid 7,0
+va (VaSet
+font "courier,8,1"
+)
+xt "-12000,74500,-6500,75400"
+st "Post User:"
+blo "-12000,75200"
+)
+postUserText (MLText
+uid 8,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,61000,-10000,61900"
+tm "BdDeclarativeTextMgr"
+)
+)
+commonDM (CommonDM
+ldm (LogicalDM
+suid 173,0
+usingSuid 1
+emptyRow *485 (LEmptyRow
+)
+uid 358,0
+optionalChildren [
+*486 (RefLabelRowHdr
+)
+*487 (TitleRowHdr
+)
+*488 (FilterRowHdr
+)
+*489 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*490 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*491 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*492 (NameColHdr
+tm "BlockDiagramNameColHdrMgr"
+)
+*493 (ModeColHdr
+tm "BlockDiagramModeColHdrMgr"
+)
+*494 (TypeColHdr
+tm "BlockDiagramTypeColHdrMgr"
+)
+*495 (BoundsColHdr
+tm "BlockDiagramBoundsColHdrMgr"
+)
+*496 (InitColHdr
+tm "BlockDiagramInitColHdrMgr"
+)
+*497 (EolColHdr
+tm "BlockDiagramEolColHdrMgr"
+)
+*498 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 16
+suid 4,0
+)
+)
+uid 279,0
+)
+*499 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 17
+suid 9,0
+)
+)
+uid 281,0
+)
+*500 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 18
+suid 10,0
+)
+)
+uid 283,0
+)
+*501 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_clk_i"
+t "std_logic"
+o 8
+suid 5,0
+)
+)
+uid 285,0
+)
+*502 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 9
+suid 6,0
+)
+)
+uid 287,0
+)
+*503 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 10
+suid 7,0
+)
+)
+uid 289,0
+)
+*504 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 11
+suid 8,0
+)
+)
+uid 291,0
+)
+*505 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 22
+suid 15,0
+)
+)
+uid 293,0
+)
+*506 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 19
+suid 11,0
+)
+)
+uid 295,0
+)
+*507 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 15
+suid 18,0
+)
+)
+uid 305,0
+)
+*508 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 4
+suid 2,0
+)
+)
+uid 307,0
+)
+*509 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_scl_b"
+t "std_logic"
+o 29
+suid 12,0
+)
+)
+uid 309,0
+)
+*510 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_sda_b"
+t "std_logic"
+o 30
+suid 13,0
+)
+)
+uid 311,0
+)
+*511 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "--! normally 160MHz"
+o 33
+suid 26,0
+)
+)
+uid 1223,0
+)
+*512 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_clk"
+t "std_logic"
+o 43
+suid 39,0
+)
+)
+uid 2119,0
+)
+*513 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_reset"
+t "std_logic"
+o 45
+suid 40,0
+)
+)
+uid 2121,0
+)
+*514 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbw"
+t "ipb_wbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IBus write signals"
+o 47
+suid 41,0
+)
+)
+uid 2123,0
+)
+*515 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbr"
+t "ipb_rbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IPBus read signals"
+o 42
+suid 42,0
+)
+)
+uid 2125,0
+)
+*516 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "overall_trigger"
+t "std_logic"
+eolc "--! goes high to load trigger data"
+o 50
+suid 61,0
+)
+)
+uid 2131,0
+)
+*517 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "overall_veto"
+t "std_logic"
+eolc "--! Halts triggers when high"
+o 51
+suid 62,0
+)
+)
+uid 2133,0
+)
+*518 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "triggers"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 63
+suid 68,0
+)
+)
+uid 2137,0
+)
+*519 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "trigger_count"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 61
+suid 77,0
+)
+)
+uid 2287,0
+)
+*520 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "data_strobe"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 35
+suid 82,0
+)
+)
+uid 2362,0
+)
+*521 (LeafLogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "leds_o"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 21
+suid 83,0
+)
+)
+uid 2814,0
+scheme 0
+)
+*522 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "trigger_times"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 62
+suid 86,0
+)
+)
+uid 3333,0
+)
+*523 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "event_data"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 40
+suid 93,0
+)
+)
+uid 3653,0
+)
+*524 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "--! either external clock in, or a clock being driven out"
+o 28
+suid 105,0
+)
+)
+uid 4683,0
+)
+*525 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 27
+suid 106,0
+)
+)
+uid 4685,0
+)
+*526 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "clk_logic_xtal"
+t "std_logic"
+eolc "! 40MHz clock from onboard xtal"
+o 34
+suid 107,0
+)
+)
+uid 4687,0
+)
+*527 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "strobe_4x_logic"
+t "std_logic"
+eolc "one pulse every 4 cycles of clk_4x"
+o 59
+suid 109,0
+)
+)
+uid 4705,0
+)
+*528 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "clk_16x_logic"
+t "std_logic"
+eolc "640MHz clock"
+o 32
+suid 110,0
+)
+)
+uid 4707,0
+)
+*529 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "strobe_16x_logic"
+t "std_logic"
+eolc "--! Pulses one cycle every 4 of 16x clock."
+o 58
+suid 111,0
+)
+)
+uid 4709,0
+)
+*530 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "veto_o"
+t "std_logic"
+eolc "--! goes high when one or more DUT are busy"
+o 64
+suid 116,0
+)
+)
+uid 4994,0
+)
+*531 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "buffer_full_o"
+t "std_logic"
+eolc "--! Goes high when event buffer almost full"
+o 31
+suid 117,0
+)
+)
+uid 4996,0
+)
+*532 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 3
+suid 120,0
+)
+)
+uid 6012,0
+)
+*533 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 121,0
+)
+)
+uid 6014,0
+)
+*534 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+o 13
+suid 129,0
+)
+)
+uid 6680,0
+)
+*535 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 130,0
+)
+)
+uid 6682,0
+)
+*536 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 131,0
+)
+)
+uid 6685,0
+)
+*537 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 132,0
+)
+)
+uid 6687,0
+)
+*538 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 133,0
+)
+)
+uid 6689,0
+)
+*539 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 134,0
+)
+)
+uid 6691,0
+)
+*540 (LeafLogPort
+port (LogicalPort
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 135,0
+)
+)
+uid 6693,0
+)
+*541 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 136,0
+)
+)
+uid 6695,0
+)
+*542 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 137,0
+)
+)
+uid 6697,0
+)
+*543 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 138,0
+)
+)
+uid 6699,0
+)
+*544 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 139,0
+)
+)
+uid 6701,0
+)
+*545 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_rst"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 46
+suid 140,0
+)
+)
+uid 7101,0
+)
+*546 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "event_number_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 41
+suid 146,0
+)
+)
+uid 9407,0
+)
+*547 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "logic_reset"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 49
+suid 148,0
+)
+)
+uid 9409,0
+)
+*548 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_i2c_scl_enb"
+t "std_logic"
+o 52
+suid 153,0
+)
+)
+uid 10124,0
+)
+*549 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_i2c_sda_enb"
+t "std_logic"
+o 53
+suid 157,0
+)
+)
+uid 10126,0
+)
+*550 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 44
+suid 158,0
+)
+)
+uid 10540,0
+)
+*551 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 36
+suid 161,0
+)
+)
+uid 10634,0
+)
+*552 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 37
+suid 162,0
+)
+)
+uid 10636,0
+)
+*553 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 38
+suid 163,0
+)
+)
+uid 10638,0
+)
+*554 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 39
+suid 164,0
+)
+)
+uid 10640,0
+)
+*555 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 54
+suid 165,0
+)
+)
+uid 10642,0
+)
+*556 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 55
+suid 166,0
+)
+)
+uid 10644,0
+)
+*557 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 56
+suid 167,0
+)
+)
+uid 10646,0
+)
+*558 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 57
+suid 168,0
+)
+)
+uid 10648,0
+)
+*559 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 60
+suid 169,0
+)
+)
+uid 10650,0
+)
+*560 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "logic_clocks_reset"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 48
+suid 171,0
+)
+)
+uid 11204,0
+)
+*561 (LeafLogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 20
+suid 172,0
+)
+)
+uid 11457,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
+uid 371,0
+optionalChildren [
+*562 (Sheet
+sheetRow (SheetRow
+headerVa (MVa
+cellColor "49152,49152,49152"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+cellVa (MVa
+cellColor "65535,65535,65535"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+groupVa (MVa
+cellColor "39936,56832,65280"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *563 (MRCItem
+litem &485
+pos 64
+dimension 20
+)
+uid 373,0
+optionalChildren [
+*564 (MRCItem
+litem &486
+pos 0
+dimension 20
+uid 374,0
+)
+*565 (MRCItem
+litem &487
+pos 1
+dimension 23
+uid 375,0
+)
+*566 (MRCItem
+litem &488
+pos 2
+hidden 1
+dimension 20
+uid 376,0
+)
+*567 (MRCItem
+litem &498
+pos 0
+dimension 20
+uid 280,0
+)
+*568 (MRCItem
+litem &499
+pos 1
+dimension 20
+uid 282,0
+)
+*569 (MRCItem
+litem &500
+pos 2
+dimension 20
+uid 284,0
+)
+*570 (MRCItem
+litem &501
+pos 3
+dimension 20
+uid 286,0
+)
+*571 (MRCItem
+litem &502
+pos 4
+dimension 20
+uid 288,0
+)
+*572 (MRCItem
+litem &503
+pos 5
+dimension 20
+uid 290,0
+)
+*573 (MRCItem
+litem &504
+pos 6
+dimension 20
+uid 292,0
+)
+*574 (MRCItem
+litem &505
+pos 7
+dimension 20
+uid 294,0
+)
+*575 (MRCItem
+litem &506
+pos 8
+dimension 20
+uid 296,0
+)
+*576 (MRCItem
+litem &507
+pos 17
+dimension 20
+uid 306,0
+)
+*577 (MRCItem
+litem &508
+pos 19
+dimension 20
+uid 308,0
+)
+*578 (MRCItem
+litem &509
+pos 21
+dimension 20
+uid 310,0
+)
+*579 (MRCItem
+litem &510
+pos 22
+dimension 20
+uid 312,0
+)
+*580 (MRCItem
+litem &511
+pos 30
+dimension 20
+uid 1224,0
+)
+*581 (MRCItem
+litem &512
+pos 31
+dimension 20
+uid 2120,0
+)
+*582 (MRCItem
+litem &513
+pos 32
+dimension 20
+uid 2122,0
+)
+*583 (MRCItem
+litem &514
+pos 33
+dimension 20
+uid 2124,0
+)
+*584 (MRCItem
+litem &515
+pos 34
+dimension 20
+uid 2126,0
+)
+*585 (MRCItem
+litem &516
+pos 35
+dimension 20
+uid 2132,0
+)
+*586 (MRCItem
+litem &517
+pos 36
+dimension 20
+uid 2134,0
+)
+*587 (MRCItem
+litem &518
+pos 37
+dimension 20
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+fixedCol 4
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+)
+]
+)
+uid 357,0
+)
+genericsCommonDM (CommonDM
+ldm (LogicalDM
+emptyRow *639 (LEmptyRow
+)
+uid 387,0
+optionalChildren [
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+)
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+)
+*642 (FilterRowHdr
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+)
+*644 (RowExpandColHdr
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+tm "GroupColHdrMgr"
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+*650 (EolColHdr
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
new file mode 100644
index 0000000000000000000000000000000000000000..e175e0e4cd442208c11eb346d75965762e5b13ef
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
@@ -0,0 +1,17784 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+(DmPackageRef
+library "work"
+unitName "emac_hostbus_decl"
+)
+(DmPackageRef
+library "work"
+unitName "fmcTLU"
+)
+(DmPackageRef
+library "unisim"
+unitName "vcomponents"
+)
+]
+instances [
+(Instance
+name "I4"
+duLibraryName "work"
+duName "IPBusInterface"
+elements [
+(GiElement
+name "NUM_EXT_SLAVES"
+type "positive"
+value "g_NUM_EXT_SLAVES"
+)
+]
+mwi 0
+uid 4555,0
+)
+(Instance
+name "I8"
+duLibraryName "moduleware"
+duName "sor"
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+]
+mwi 1
+uid 4949,0
+)
+(Instance
+name "I0"
+duLibraryName "work"
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+elements [
+(GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "g_NUM_DUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+mwi 0
+uid 6898,0
+)
+(Instance
+name "I3"
+duLibraryName "work"
+duName "triggerLogic"
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+mwi 0
+uid 9123,0
+)
+(Instance
+name "I5"
+duLibraryName "work"
+duName "eventBuffer"
+elements [
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+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_WRITE_COUNTER_WIDTH"
+type "positive"
+value "13"
+)
+(GiElement
+name "g_READ_COUNTER_WIDTH"
+type "positive"
+value "14"
+)
+]
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+name "I7"
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+)
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+name "I2"
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+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_TRIG_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+(GiElement
+name "g_EVTTYPE_WIDTH"
+type "positive"
+value "4"
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+)
+(GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "g_NUM_EDGE_INPUTS"
+pr "--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)"
+apr 0
+e "-- Number of edge inputs"
+)
+(GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+e "-- Number of trigger inputs"
+)
+]
+mwi 0
+uid 10522,0
+)
+(Instance
+name "I6"
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+name "g_NUM_INPUTS"
+type "natural"
+value "g_NUM_TRIG_INPUTS"
+)
+]
+mwi 0
+uid 11619,0
+)
+]
+embeddedInstances [
+(EmbeddedInstance
+name "i2c_tristate"
+number "1"
+)
+]
+libraryRefs [
+"ieee"
+"work"
+"unisim"
+]
+)
+version "30.1"
+appVersion "2012.2b (Build 5)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "struct"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy"
+)
+(vvPair
+variable "date"
+value "01/24/14"
+)
+(vvPair
+variable "day"
+value "Fri"
+)
+(vvPair
+variable "day_long"
+value "Friday"
+)
+(vvPair
+variable "dd"
+value "24"
+)
+(vvPair
+variable "entity_name"
+value "top_extphy"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "struct.bd"
+)
+(vvPair
+variable "f_logical"
+value "struct.bd"
+)
+(vvPair
+variable "f_noext"
+value "struct"
+)
+(vvPair
+variable "graphical_source_author"
+value "phdgc"
+)
+(vvPair
+variable "graphical_source_date"
+value "07/24/13"
+)
+(vvPair
+variable "graphical_source_group"
+value "users"
+)
+(vvPair
+variable "graphical_source_time"
+value "18:45:06"
+)
+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "fortis.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "01"
+)
+(vvPair
+variable "module_name"
+value "top_extphy"
+)
+(vvPair
+variable "month"
+value "Jan"
+)
+(vvPair
+variable "month_long"
+value "January"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "struct"
+)
+(vvPair
+variable "this_file_logical"
+value "struct"
+)
+(vvPair
+variable "time"
+value "16:06:32"
+)
+(vvPair
+variable "unit"
+value "top_extphy"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2012.2b (Build 5)"
+)
+(vvPair
+variable "view"
+value "struct"
+)
+(vvPair
+variable "year"
+value "2014"
+)
+(vvPair
+variable "yy"
+value "14"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 356,0
+optionalChildren [
+*1 (PortIoIn
+uid 23,0
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+xt "183000,160000,200000,161000"
+)
+oxt "18000,69000,35000,70000"
+text (MLText
+uid 344,0
+va (VaSet
+fg "0,0,32768"
+bg "0,0,32768"
+font "courier,8,0"
+)
+xt "183200,160050,194700,160950"
+st "
+%library/%unit/%view
+"
+tm "CommentText"
+wrapOption 3
+visibleHeight 1000
+visibleWidth 17000
+)
+position 1
+ignorePrefs 1
+titleBlock 1
+)
+]
+shape (GroupingShape
+uid 314,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineStyle 2
+lineWidth 2
+)
+xt "179000,157000,220000,162000"
+)
+oxt "14000,66000,55000,71000"
+)
+*37 (PortIoIn
+uid 745,0
+shape (CompositeShape
+uid 746,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 747,0
+sl 0
+ro 270
+xt "78000,21625,79500,22375"
+)
+(Line
+uid 748,0
+sl 0
+ro 270
+xt "79500,22000,80000,22000"
+pts [
+"79500,22000"
+"80000,22000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 749,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 750,0
+va (VaSet
+font "courier,8,0"
+)
+xt "71500,21550,77000,22450"
+st "sysclk_n_i"
+ju 2
+blo "77000,22250"
+tm "WireNameMgr"
+)
+)
+)
+*38 (PortIoIn
+uid 759,0
+shape (CompositeShape
+uid 760,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 761,0
+sl 0
+ro 270
+xt "78000,24625,79500,25375"
+)
+(Line
+uid 762,0
+sl 0
+ro 270
+xt "79500,25000,80000,25000"
+pts [
+"79500,25000"
+"80000,25000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 763,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 764,0
+va (VaSet
+font "courier,8,0"
+)
+xt "71500,24550,77000,25450"
+st "sysclk_p_i"
+ju 2
+blo "77000,25250"
+tm "WireNameMgr"
+)
+)
+)
+*39 (Net
+uid 1205,0
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "--! normally 160MHz"
+o 33
+suid 26,0
+)
+declText (MLText
+uid 1206,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,45700,19500,46600"
+st "SIGNAL clk_4x_logic : std_logic --! normally 160MHz
+"
+)
+)
+*40 (Net
+uid 1429,0
+decl (Decl
+n "ipbus_clk"
+t "std_logic"
+o 43
+suid 39,0
+)
+declText (MLText
+uid 1430,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,54700,9500,55600"
+st "SIGNAL ipbus_clk : std_logic
+"
+)
+)
+*41 (Net
+uid 1431,0
+decl (Decl
+n "ipbus_reset"
+t "std_logic"
+o 45
+suid 40,0
+)
+declText (MLText
+uid 1432,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,56500,9500,57400"
+st "SIGNAL ipbus_reset : std_logic
+"
+)
+)
+*42 (Net
+uid 1588,0
+decl (Decl
+n "ipbw"
+t "ipb_wbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IBus write signals"
+o 47
+suid 41,0
+)
+declText (MLText
+uid 1589,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,58300,38000,59200"
+st "SIGNAL ipbw : ipb_wbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --! IBus write signals
+"
+)
+)
+*43 (Net
+uid 1668,0
+decl (Decl
+n "ipbr"
+t "ipb_rbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IPBus read signals"
+o 42
+suid 42,0
+)
+declText (MLText
+uid 1669,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,53800,38000,54700"
+st "SIGNAL ipbr : ipb_rbus_array(g_NUM_EXT_SLAVES-1 DOWNTO 0) --! IPBus read signals
+"
+)
+)
+*44 (Net
+uid 1808,0
+decl (Decl
+n "overall_trigger"
+t "std_logic"
+eolc "--! goes high to load trigger data"
+o 50
+suid 61,0
+)
+declText (MLText
+uid 1809,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,61000,27000,61900"
+st "SIGNAL overall_trigger : std_logic --! goes high to load trigger data
+"
+)
+)
+*45 (Net
+uid 1810,0
+decl (Decl
+n "overall_veto"
+t "std_logic"
+eolc "--! Halts triggers when high"
+o 51
+suid 62,0
+)
+declText (MLText
+uid 1811,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,61900,24000,62800"
+st "SIGNAL overall_veto : std_logic --! Halts triggers when high
+"
+)
+)
+*46 (Net
+uid 2117,0
+decl (Decl
+n "triggers"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 63
+suid 68,0
+)
+declText (MLText
+uid 2118,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,72700,28000,73600"
+st "SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0)
+"
+)
+)
+*47 (Net
+uid 2273,0
+lang 2
+decl (Decl
+n "trigger_count"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 61
+suid 77,0
+)
+declText (MLText
+uid 2274,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,70900,26000,71800"
+st "SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*48 (Net
+uid 2360,0
+lang 2
+decl (Decl
+n "data_strobe"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 35
+suid 82,0
+)
+declText (MLText
+uid 2361,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,47500,37000,48400"
+st "SIGNAL data_strobe : std_logic -- goes high when data ready to load into event buffer
+"
+)
+)
+*49 (PortIoOut
+uid 2818,0
+shape (CompositeShape
+uid 2819,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 2820,0
+sl 0
+ro 270
+xt "208500,3625,210000,4375"
+)
+(Line
+uid 2821,0
+sl 0
+ro 270
+xt "208000,4000,208500,4000"
+pts [
+"208000,4000"
+"208500,4000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 2822,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 2823,0
+va (VaSet
+font "courier,8,0"
+)
+xt "211000,3500,214000,4400"
+st "leds_o"
+blo "211000,4200"
+tm "WireNameMgr"
+)
+)
+)
+*50 (Net
+uid 2830,0
+lang 2
+decl (Decl
+n "leds_o"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 21
+suid 83,0
+)
+declText (MLText
+uid 2831,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,34000,15500,34900"
+st "leds_o : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*51 (Net
+uid 3331,0
+lang 2
+decl (Decl
+n "trigger_times"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 62
+suid 86,0
+)
+declText (MLText
+uid 3332,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,71800,53500,72700"
+st "SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0) -- ! trigger arrival time ( w.r.t. logic_strobe)
+"
+)
+)
+*52 (Net
+uid 3567,0
+lang 2
+decl (Decl
+n "event_data"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 40
+suid 93,0
+)
+declText (MLText
+uid 3568,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,52000,28500,52900"
+st "SIGNAL event_data : std_logic_vector(g_EVENT_DATA_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*53 (SaComponent
+uid 4555,0
+optionalChildren [
+*54 (CptPort
+uid 4479,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4480,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,9625,95000,10375"
+)
+tg (CPTG
+uid 4481,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4482,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,9550,103000,10450"
+st "gmii_rx_clk_i"
+blo "96000,10250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_clk_i"
+t "std_logic"
+o 1
+suid 2,0
+)
+)
+)
+*55 (CptPort
+uid 4483,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4484,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,12625,95000,13375"
+)
+tg (CPTG
+uid 4485,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4486,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,12550,102500,13450"
+st "gmii_rx_dv_i"
+blo "96000,13250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 2
+suid 3,0
+)
+)
+)
+*56 (CptPort
+uid 4487,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4488,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,15625,95000,16375"
+)
+tg (CPTG
+uid 4489,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4490,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,15550,102500,16450"
+st "gmii_rx_er_i"
+blo "96000,16250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 3
+suid 4,0
+)
+)
+)
+*57 (CptPort
+uid 4491,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4492,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,18625,95000,19375"
+)
+tg (CPTG
+uid 4493,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4494,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,18550,105500,19450"
+st "gmii_rxd_i : (7:0)"
+blo "96000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 4
+suid 5,0
+)
+)
+)
+*58 (CptPort
+uid 4495,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4496,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,8625,128750,9375"
+)
+tg (CPTG
+uid 4497,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4498,0
+va (VaSet
+font "courier,8,0"
+)
+xt "120500,8550,127000,9450"
+st "gmii_tx_en_o"
+ju 2
+blo "127000,9250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 10
+suid 6,0
+)
+)
+)
+*59 (CptPort
+uid 4499,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4500,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,10625,128750,11375"
+)
+tg (CPTG
+uid 4501,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4502,0
+va (VaSet
+font "courier,8,0"
+)
+xt "120500,10550,127000,11450"
+st "gmii_tx_er_o"
+ju 2
+blo "127000,11250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 11
+suid 7,0
+)
+)
+)
+*60 (CptPort
+uid 4503,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4504,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,13625,128750,14375"
+)
+tg (CPTG
+uid 4505,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4506,0
+va (VaSet
+font "courier,8,0"
+)
+xt "117500,13550,127000,14450"
+st "gmii_txd_o : (7:0)"
+ju 2
+blo "127000,14250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 12
+suid 8,0
+)
+)
+)
+*61 (CptPort
+uid 4507,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4508,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,15625,128750,16375"
+)
+tg (CPTG
+uid 4509,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4510,0
+va (VaSet
+font "courier,8,0"
+)
+xt "121500,15550,127000,16450"
+st "phy_rstb_o"
+ju 2
+blo "127000,16250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 17
+suid 10,0
+)
+)
+)
+*62 (CptPort
+uid 4511,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4512,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,17625,128750,18375"
+)
+tg (CPTG
+uid 4513,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4514,0
+va (VaSet
+font "courier,8,0"
+)
+xt "119500,17550,127000,18450"
+st "gmii_gtx_clk_o"
+ju 2
+blo "127000,18250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 9
+suid 1,0
+)
+)
+)
+*63 (CptPort
+uid 4515,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4516,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,21625,95000,22375"
+)
+tg (CPTG
+uid 4517,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4518,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,21550,101500,22450"
+st "sysclk_n_i"
+blo "96000,22250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+o 6
+suid 12,0
+)
+)
+)
+*64 (CptPort
+uid 4519,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4520,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,24625,95000,25375"
+)
+tg (CPTG
+uid 4521,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4522,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,24550,101500,25450"
+st "sysclk_p_i"
+blo "96000,25250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+eolc "! 200 MHz xtal clock"
+o 7
+suid 13,0
+)
+)
+)
+*65 (CptPort
+uid 4523,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4524,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,19625,128750,20375"
+)
+tg (CPTG
+uid 4525,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4526,0
+va (VaSet
+font "courier,8,0"
+)
+xt "122500,19550,127000,20450"
+st "ipb_clk_o"
+ju 2
+blo "127000,20250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_clk_o"
+t "std_logic"
+eolc "! IPBus clock to slaves"
+o 13
+suid 14,0
+)
+)
+)
+*66 (CptPort
+uid 4527,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4528,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,22625,128750,23375"
+)
+tg (CPTG
+uid 4529,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4530,0
+va (VaSet
+font "courier,8,0"
+)
+xt "122500,22550,127000,23450"
+st "ipb_rst_o"
+ju 2
+blo "127000,23250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipb_rst_o"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 14
+suid 15,0
+)
+)
+)
+*67 (CptPort
+uid 4531,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4532,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,24625,128750,25375"
+)
+tg (CPTG
+uid 4533,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4534,0
+va (VaSet
+font "courier,8,0"
+)
+xt "112000,24550,127000,25450"
+st "ipbw_o : (NUM_EXT_SLAVES-1:0)"
+ju 2
+blo "127000,25250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbw_o"
+t "ipb_wbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IBus write signals"
+o 15
+suid 16,0
+)
+)
+)
+*68 (CptPort
+uid 4535,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4536,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "94250,27625,95000,28375"
+)
+tg (CPTG
+uid 4537,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 4538,0
+va (VaSet
+font "courier,8,0"
+)
+xt "96000,27550,111000,28450"
+st "ipbr_i : (NUM_EXT_SLAVES-1:0)"
+blo "96000,28250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbr_i"
+t "ipb_rbus_array"
+b "(NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "! IPBus read signals"
+o 5
+suid 19,0
+)
+)
+)
+*69 (CptPort
+uid 4539,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 4540,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "128000,26625,128750,27375"
+)
+tg (CPTG
+uid 4541,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 4542,0
+va (VaSet
+font "courier,8,0"
+)
+xt "123500,26550,127000,27450"
+st "onehz_o"
+ju 2
+blo "127000,27250"
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
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+)
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+type "positive"
+value "g_NUM_EXT_SLAVES"
+)
+]
+)
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+)
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+)
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+)
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+)
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+)
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+)
+)
+)
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+)
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+"
+)
+)
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+)
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+)
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+)
+)
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+)
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+)
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+"
+)
+)
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+t "std_logic"
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+suid 109,0
+)
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+"
+)
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+"
+)
+)
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+)
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+)
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+)
+)
+)
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+)
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+)
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+)
+)
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+)
+*113 (Net
+uid 6676,0
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+o 13
+suid 129,0
+)
+declText (MLText
+uid 6677,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,26800,6000,27700"
+st "sysclk_p_i : std_logic
+"
+)
+)
+*114 (Net
+uid 6678,0
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 130,0
+)
+declText (MLText
+uid 6679,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,25900,17500,26800"
+st "sysclk_n_i : std_logic --! 200 MHz xtal clock
+"
+)
+)
+*115 (PortIoOut
+uid 6702,0
+shape (CompositeShape
+uid 6703,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6704,0
+sl 0
+ro 270
+xt "64500,89625,66000,90375"
+)
+(Line
+uid 6705,0
+sl 0
+ro 270
+xt "64000,90000,64500,90000"
+pts [
+"64000,90000"
+"64500,90000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6706,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6707,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,88550,63500,89450"
+st "triggers_p_o"
+blo "57000,89250"
+tm "WireNameMgr"
+)
+)
+)
+*116 (Net
+uid 6714,0
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 131,0
+)
+declText (MLText
+uid 6715,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,38500,33500,39400"
+st "triggers_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0) --! Trigger lines to DUT
+"
+)
+)
+*117 (PortIoIn
+uid 6716,0
+shape (CompositeShape
+uid 6717,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6718,0
+sl 0
+ro 270
+xt "-2000,88625,-500,89375"
+)
+(Line
+uid 6719,0
+sl 0
+ro 270
+xt "-500,89000,0,89000"
+pts [
+"-500,89000"
+"0,89000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6720,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6721,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-7000,88500,-3000,89400"
+st "busy_p_i"
+ju 2
+blo "-3000,89200"
+tm "WireNameMgr"
+)
+)
+)
+*118 (Net
+uid 6728,0
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 132,0
+)
+declText (MLText
+uid 6729,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,16900,41500,17800"
+st "busy_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0) --! Busy lines from DUTs ( active high )
+"
+)
+)
+*119 (PortIoOut
+uid 6730,0
+shape (CompositeShape
+uid 6731,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6732,0
+sl 0
+ro 270
+xt "64500,96625,66000,97375"
+)
+(Line
+uid 6733,0
+sl 0
+ro 270
+xt "64000,97000,64500,97000"
+pts [
+"64000,97000"
+"64500,97000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6734,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6735,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,95550,65500,96450"
+st "reset_or_clk_p_o"
+blo "57000,96250"
+tm "WireNameMgr"
+)
+)
+)
+*120 (Net
+uid 6742,0
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 133,0
+)
+declText (MLText
+uid 6743,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,36700,21000,37600"
+st "reset_or_clk_p_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*121 (PortIoIn
+uid 6744,0
+shape (CompositeShape
+uid 6745,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6746,0
+sl 0
+ro 270
+xt "-2000,92625,-500,93375"
+)
+(Line
+uid 6747,0
+sl 0
+ro 270
+xt "-500,93000,0,93000"
+pts [
+"-500,93000"
+"0,93000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6748,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6749,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-9000,92500,-3000,93400"
+st "dut_clk_p_i"
+ju 2
+blo "-3000,93200"
+tm "WireNameMgr"
+)
+)
+)
+*122 (Net
+uid 6756,0
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 134,0
+)
+declText (MLText
+uid 6757,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,21400,21000,22300"
+st "dut_clk_p_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*123 (Net
+uid 6770,0
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 135,0
+)
+declText (MLText
+uid 6771,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,19600,15500,20500"
+st "dip_switch_i : std_logic_vector(3 DOWNTO 0)
+"
+)
+)
+*124 (PortIoIn
+uid 6772,0
+shape (CompositeShape
+uid 6773,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6774,0
+sl 0
+ro 270
+xt "-2000,90625,-500,91375"
+)
+(Line
+uid 6775,0
+sl 0
+ro 270
+xt "-500,91000,0,91000"
+pts [
+"-500,91000"
+"0,91000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6776,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6777,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-7000,90500,-3000,91400"
+st "busy_n_i"
+ju 2
+blo "-3000,91200"
+tm "WireNameMgr"
+)
+)
+)
+*125 (Net
+uid 6784,0
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 136,0
+)
+declText (MLText
+uid 6785,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,16000,21000,16900"
+st "busy_n_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*126 (PortIoOut
+uid 6786,0
+shape (CompositeShape
+uid 6787,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6788,0
+sl 0
+ro 270
+xt "64500,98625,66000,99375"
+)
+(Line
+uid 6789,0
+sl 0
+ro 270
+xt "64000,99000,64500,99000"
+pts [
+"64000,99000"
+"64500,99000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6790,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6791,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,97550,65500,98450"
+st "reset_or_clk_n_o"
+blo "57000,98250"
+tm "WireNameMgr"
+)
+)
+)
+*127 (Net
+uid 6798,0
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 137,0
+)
+declText (MLText
+uid 6799,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,35800,21000,36700"
+st "reset_or_clk_n_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*128 (PortIoOut
+uid 6800,0
+shape (CompositeShape
+uid 6801,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6802,0
+sl 0
+ro 270
+xt "64500,91625,66000,92375"
+)
+(Line
+uid 6803,0
+sl 0
+ro 270
+xt "64000,92000,64500,92000"
+pts [
+"64000,92000"
+"64500,92000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6804,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6805,0
+va (VaSet
+font "courier,8,0"
+)
+xt "57000,90550,63500,91450"
+st "triggers_n_o"
+blo "57000,91250"
+tm "WireNameMgr"
+)
+)
+)
+*129 (Net
+uid 6812,0
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 138,0
+)
+declText (MLText
+uid 6813,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,37600,21000,38500"
+st "triggers_n_o : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*130 (PortIoIn
+uid 6814,0
+shape (CompositeShape
+uid 6815,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6816,0
+sl 0
+ro 270
+xt "-2000,94625,-500,95375"
+)
+(Line
+uid 6817,0
+sl 0
+ro 270
+xt "-500,95000,0,95000"
+pts [
+"-500,95000"
+"0,95000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6818,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6819,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-9000,94500,-3000,95400"
+st "dut_clk_n_i"
+ju 2
+blo "-3000,95200"
+tm "WireNameMgr"
+)
+)
+)
+*131 (Net
+uid 6826,0
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 139,0
+)
+declText (MLText
+uid 6827,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,20500,21000,21400"
+st "dut_clk_n_i : std_logic_vector(g_NUM_DUTS-1 DOWNTO 0)
+"
+)
+)
+*132 (SaComponent
+uid 6898,0
+optionalChildren [
+*133 (CptPort
+uid 6830,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6831,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,89625,55750,90375"
+)
+tg (CPTG
+uid 6832,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6833,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,89550,54000,90450"
+st "trigger_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,90250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 16
+suid 1,0
+)
+)
+)
+*134 (CptPort
+uid 6834,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6835,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,88625,10000,89375"
+)
+tg (CPTG
+uid 6836,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6837,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,88550,29500,89450"
+st "busy_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "11000,89250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 2
+suid 2,0
+)
+)
+)
+*135 (CptPort
+uid 6838,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6839,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,96625,55750,97375"
+)
+tg (CPTG
+uid 6840,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6841,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,96550,54000,97450"
+st "reset_or_clk_to_dut_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,97250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 14
+suid 3,0
+)
+)
+)
+*136 (CptPort
+uid 6842,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6843,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,92625,10000,93375"
+)
+tg (CPTG
+uid 6844,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6845,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,92550,29000,93450"
+st "clk_from_dut_p_i : (g_NUM_DUTS-1:0)"
+blo "11000,93250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_from_dut_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 4
+suid 4,0
+)
+)
+)
+*137 (CptPort
+uid 6846,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6847,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,96625,10000,97375"
+)
+tg (CPTG
+uid 6848,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6849,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,96550,15500,97450"
+st "trigger_i"
+blo "11000,97250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "goes high when trigger logic issues a trigger"
+o 11
+suid 5,0
+)
+)
+)
+*138 (CptPort
+uid 6850,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6851,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,98625,10000,99375"
+)
+tg (CPTG
+uid 6852,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6853,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,98550,18500,99450"
+st "clk_4x_logic_i"
+blo "11000,99250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+o 3
+suid 6,0
+)
+)
+)
+*139 (CptPort
+uid 6854,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6855,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,100625,10000,101375"
+)
+tg (CPTG
+uid 6856,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6857,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,100550,20000,101450"
+st "strobe_4x_logic_i"
+blo "11000,101250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! goes high every 4th clock cycle"
+o 9
+suid 7,0
+)
+)
+)
+*140 (CptPort
+uid 6858,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6859,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,102625,10000,103375"
+)
+tg (CPTG
+uid 6860,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6861,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,102550,31000,103450"
+st "trigger_counter_i : (g_IPBUS_WIDTH-1:0)"
+blo "11000,103250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "trigger_counter_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 10
+suid 8,0
+)
+)
+)
+*141 (CptPort
+uid 6862,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6863,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,104625,10000,105375"
+)
+tg (CPTG
+uid 6864,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6865,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,104550,17000,105450"
+st "ipbus_clk_i"
+blo "11000,105250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 6
+suid 9,0
+)
+)
+)
+*142 (CptPort
+uid 6866,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6867,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,106625,10000,107375"
+)
+tg (CPTG
+uid 6868,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6869,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,106550,18000,107450"
+st "ipbus_reset_i"
+blo "11000,107250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 8
+suid 10,0
+)
+)
+)
+*143 (CptPort
+uid 6870,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6871,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,108625,10000,109375"
+)
+tg (CPTG
+uid 6872,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6873,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,108550,14500,109450"
+st "ipbus_i"
+blo "11000,109250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 7
+suid 11,0
+)
+)
+)
+*144 (CptPort
+uid 6874,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6875,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,103625,55750,104375"
+)
+tg (CPTG
+uid 6876,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6877,0
+va (VaSet
+font "courier,8,0"
+)
+xt "50500,103550,54000,104450"
+st "ipbus_o"
+ju 2
+blo "54000,104250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 12
+suid 12,0
+)
+)
+)
+*145 (CptPort
+uid 6878,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6879,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,107625,55750,108375"
+)
+tg (CPTG
+uid 6880,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6881,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,107550,54000,108450"
+st "veto_o"
+ju 2
+blo "54000,108250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "veto_o"
+t "std_logic"
+eolc "goes high when one or more DUT are busy"
+o 17
+suid 13,0
+)
+)
+)
+*146 (CptPort
+uid 6882,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6883,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,91625,55750,92375"
+)
+tg (CPTG
+uid 6884,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6885,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,91550,54000,92450"
+st "trigger_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,92250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Trigger output"
+o 15
+suid 14,0
+)
+)
+)
+*147 (CptPort
+uid 6886,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6887,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,90625,10000,91375"
+)
+tg (CPTG
+uid 6888,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6889,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,90550,29500,91450"
+st "busy_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "11000,91250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "BUSY input from DUTs"
+o 1
+suid 15,0
+)
+)
+)
+*148 (CptPort
+uid 6890,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6891,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "55000,98625,55750,99375"
+)
+tg (CPTG
+uid 6892,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 6893,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,98550,54000,99450"
+st "reset_or_clk_to_dut_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "54000,99250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_to_dut_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "! Either reset line or trigger"
+o 13
+suid 16,0
+)
+)
+)
+*149 (CptPort
+uid 6894,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 6895,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "9250,94625,10000,95375"
+)
+tg (CPTG
+uid 6896,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 6897,0
+va (VaSet
+font "courier,8,0"
+)
+xt "11000,94550,29000,95450"
+st "clk_from_dut_n_i : (g_NUM_DUTS-1:0)"
+blo "11000,95250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk_from_dut_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "clocks trigger data when in EUDET mode"
+o 5
+suid 17,0
+)
+)
+)
+]
+shape (Rectangle
+uid 6899,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "10000,88000,55000,110000"
+)
+oxt "14000,17000,59000,39000"
+ttg (MlTextGroup
+uid 6900,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*150 (Text
+uid 6901,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,97100,21750,98000"
+st "work"
+blo "19750,97800"
+tm "BdLibraryNameMgr"
+)
+*151 (Text
+uid 6902,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,98000,26750,98900"
+st "DUTInterfaces"
+blo "19750,98700"
+tm "CptNameMgr"
+)
+*152 (Text
+uid 6903,0
+va (VaSet
+font "courier,8,1"
+)
+xt "19750,98900,20750,99800"
+st "I0"
+blo "19750,99600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 6904,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 6905,0
+text (MLText
+uid 6906,0
+va (VaSet
+font "courier,8,0"
+)
+xt "18000,86200,42000,88000"
+st "g_NUM_DUTS = g_NUM_DUTS ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "g_NUM_DUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 6907,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "10250,108250,11750,109750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*153 (PortIoIn
+uid 6908,0
+shape (CompositeShape
+uid 6909,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 6910,0
+sl 0
+ro 270
+xt "78000,30625,79500,31375"
+)
+(Line
+uid 6911,0
+sl 0
+ro 270
+xt "79500,31000,80000,31000"
+pts [
+"79500,31000"
+"80000,31000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 6912,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6913,0
+va (VaSet
+font "courier,8,0"
+)
+xt "70500,30500,77000,31400"
+st "dip_switch_i"
+ju 2
+blo "77000,31200"
+tm "WireNameMgr"
+)
+)
+)
+*154 (Net
+uid 7099,0
+decl (Decl
+n "ipbus_rst"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 46
+suid 140,0
+)
+declText (MLText
+uid 7100,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,57400,23000,58300"
+st "SIGNAL ipbus_rst : std_logic -- ! IPBus reset to slaves
+"
+)
+)
+*155 (PortIoInOut
+uid 7881,0
+shape (CompositeShape
+uid 7882,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Hexagon
+uid 7883,0
+sl 0
+xt "217500,14625,219000,15375"
+)
+(Line
+uid 7884,0
+sl 0
+xt "217000,15000,217500,15000"
+pts [
+"217000,15000"
+"217500,15000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 7885,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 7886,0
+va (VaSet
+font "courier,8,0"
+)
+xt "220000,14550,224500,15450"
+st "i2c_scl_b"
+blo "220000,15250"
+tm "WireNameMgr"
+)
+)
+)
+*156 (SaComponent
+uid 9123,0
+optionalChildren [
+*157 (CptPort
+uid 9071,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9072,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,131625,106000,132375"
+)
+tg (CPTG
+uid 9073,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9074,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,131550,114500,132450"
+st "clk_4x_logic_i"
+blo "107000,132250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 1,0
+)
+)
+)
+*158 (CptPort
+uid 9075,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9076,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,134625,106000,135375"
+)
+tg (CPTG
+uid 9077,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9078,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,134550,114500,135450"
+st "logic_strobe_i"
+blo "107000,135250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 5
+suid 2,0
+)
+)
+)
+*159 (CptPort
+uid 9079,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9080,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,142625,106000,143375"
+)
+tg (CPTG
+uid 9081,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9082,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,142550,113000,143450"
+st "ipbus_clk_i"
+blo "107000,143250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 3,0
+)
+)
+)
+*160 (CptPort
+uid 9083,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9084,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,144625,106000,145375"
+)
+tg (CPTG
+uid 9085,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9086,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,144550,110500,145450"
+st "ipbus_i"
+blo "107000,145250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 3
+suid 4,0
+)
+)
+)
+*161 (CptPort
+uid 9087,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9088,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,149625,143750,150375"
+)
+tg (CPTG
+uid 9089,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9090,0
+va (VaSet
+font "courier,8,0"
+)
+xt "138500,149550,142000,150450"
+st "ipbus_o"
+ju 2
+blo "142000,150250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 6
+suid 5,0
+)
+)
+)
+*162 (CptPort
+uid 9091,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9092,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,147625,106000,148375"
+)
+tg (CPTG
+uid 9093,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9094,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,147550,114000,148450"
+st "ipbus_reset_i"
+blo "107000,148250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 4
+suid 6,0
+)
+)
+)
+*163 (CptPort
+uid 9095,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9096,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,137625,106000,138375"
+)
+tg (CPTG
+uid 9097,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9098,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,137550,122500,138450"
+st "trigger_i : (g_NUM_INPUTS-1:0)"
+blo "107000,138250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "trigger_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger from input conector active"
+o 7
+suid 7,0
+)
+)
+)
+*164 (CptPort
+uid 9099,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9100,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,139625,106000,140375"
+)
+tg (CPTG
+uid 9101,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9102,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,139550,110000,140450"
+st "veto_i"
+blo "107000,140250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "veto_i"
+t "std_logic"
+eolc "! Halts triggers when high"
+o 8
+suid 8,0
+)
+)
+)
+*165 (CptPort
+uid 9103,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9104,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,136625,143750,137375"
+)
+tg (CPTG
+uid 9105,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9106,0
+va (VaSet
+font "courier,8,0"
+)
+xt "132000,136550,142000,137450"
+st "post_veto_trigger_o"
+ju 2
+blo "142000,137250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "post_veto_trigger_o"
+t "std_logic"
+eolc "! goes high when trigger passes"
+o 9
+suid 9,0
+)
+)
+)
+*166 (CptPort
+uid 9107,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9108,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,141625,143750,142375"
+)
+tg (CPTG
+uid 9109,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9110,0
+va (VaSet
+font "courier,8,0"
+)
+xt "133500,141550,142000,142450"
+st "trigger_active_o"
+ju 2
+blo "142000,142250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "trigger_active_o"
+t "std_logic"
+eolc "--! Goes high when triggers are active ( ie. not veoted)"
+o 10
+suid 10,0
+)
+)
+)
+*167 (CptPort
+uid 9111,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9112,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,132625,143750,133375"
+)
+tg (CPTG
+uid 9113,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9114,0
+va (VaSet
+font "courier,8,0"
+)
+xt "132500,132550,142000,133450"
+st "pre_veto_trigger_o"
+ju 2
+blo "142000,133250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pre_veto_trigger_o"
+t "std_logic"
+o 11
+suid 11,0
+)
+)
+)
+*168 (CptPort
+uid 9115,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9116,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "143000,145625,143750,146375"
+)
+tg (CPTG
+uid 9117,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 9118,0
+va (VaSet
+font "courier,8,0"
+)
+xt "123500,145550,142000,146450"
+st "event_number_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "142000,146250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "event_number_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 12
+suid 12,0
+)
+)
+)
+*169 (CptPort
+uid 9119,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 9120,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "105250,150625,106000,151375"
+)
+tg (CPTG
+uid 9121,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 9122,0
+va (VaSet
+font "courier,8,0"
+)
+xt "107000,150550,114000,151450"
+st "logic_reset_i"
+blo "107000,151250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "active high. Synchronous with clk_4x_logic"
+o 13
+suid 13,0
+)
+)
+)
+]
+shape (Rectangle
+uid 9124,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "106000,131000,143000,152000"
+)
+oxt "8000,17000,45000,38000"
+ttg (MlTextGroup
+uid 9125,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*170 (Text
+uid 9126,0
+va (VaSet
+font "courier,8,1"
+)
+xt "115750,140100,117750,141000"
+st "work"
+blo "115750,140800"
+tm "BdLibraryNameMgr"
+)
+*171 (Text
+uid 9127,0
+va (VaSet
+font "courier,8,1"
+)
+xt "115750,141000,122250,141900"
+st "triggerLogic"
+blo "115750,141700"
+tm "CptNameMgr"
+)
+*172 (Text
+uid 9128,0
+va (VaSet
+font "courier,8,1"
+)
+xt "115750,141900,116750,142800"
+st "I3"
+blo "115750,142600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 9129,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 9130,0
+text (MLText
+uid 9131,0
+va (VaSet
+font "courier,8,0"
+)
+xt "116000,129200,142000,131000"
+st "g_NUM_INPUTS = g_NUM_TRIG_INPUTS ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 9132,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "106250,150250,107750,151750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*173 (Net
+uid 9139,0
+decl (Decl
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+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 41
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+)
+declText (MLText
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+va (VaSet
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+)
+xt "-10000,52900,54000,53800"
+st "SIGNAL event_number_o : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) -- starts at one. Increments for each post_veto_trigger
+"
+)
+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+m 1
+decl (Decl
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+t "ipb_rbus"
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+)
+)
+)
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+)
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+)
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+)
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+blo "167000,77250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 3
+suid 7,0
+)
+)
+)
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+)
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+)
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+)
+xt "167000,73550,186000,74450"
+st "trigger_count_i : (g_IPBUS_WIDTH-1:0)"
+blo "167000,74250"
+)
+)
+thePort (LogicalPort
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+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 8
+suid 8,0
+)
+)
+)
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+)
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+)
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+va (VaSet
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+)
+xt "167000,68550,174000,69450"
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+blo "167000,69250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic"
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+suid 9,0
+)
+)
+)
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+)
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+)
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+)
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+st "buffer_full_o"
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+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic"
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+o 9
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+)
+)
+)
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+)
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+)
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+)
+xt "167000,88550,174000,89450"
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+blo "167000,89250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic"
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+o 11
+suid 11,0
+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
+]
+)
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+)
+xt "173000,63400,203500,67000"
+st "g_EVENT_DATA_WIDTH = g_EVENT_DATA_WIDTH ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive )
+g_WRITE_COUNTER_WIDTH = 13 ( positive )
+g_READ_COUNTER_WIDTH = 14 ( positive ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_WRITE_COUNTER_WIDTH"
+type "positive"
+value "13"
+)
+(GiElement
+name "g_READ_COUNTER_WIDTH"
+type "positive"
+value "14"
+)
+]
+)
+viewicon (ZoomableIcon
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+sl 0
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+)
+xt "166250,88250,167750,89750"
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+ftype 10
+)
+ordering 1
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+portVis (PortSigDisplay
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+)
+archFileType "UNKNOWN"
+)
+*189 (Net
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+t "std_logic"
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+o 49
+suid 148,0
+)
+declText (MLText
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+va (VaSet
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+)
+xt "-10000,60100,39000,61000"
+st "SIGNAL logic_reset : std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
+"
+)
+)
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+)
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+)
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+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
+)
+)
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+)
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+)
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+ju 2
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+)
+)
+thePort (LogicalPort
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+)
+)
+)
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+)
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+xt "188000,24550,195000,25450"
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+blo "195000,25250"
+)
+)
+thePort (LogicalPort
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+decl (Decl
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+t "std_logic"
+o 7
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+)
+)
+)
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+)
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+uid 10057,0
+va (VaSet
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+)
+xt "190500,20550,195000,21450"
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+ju 2
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+)
+)
+thePort (LogicalPort
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+n "i2c_scl_i"
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+o 8
+suid 8,0
+)
+)
+)
+]
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+
+
+"
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+)
+)
+)
+]
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+blo "208250,20700"
+tm "HdlTextNumberMgr"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 10083,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "208250,26250,209750,27750"
+iconName "TextFile.png"
+iconMaskName "TextFile.msk"
+ftype 21
+)
+viewiconposition 0
+)
+*206 (Net
+uid 10096,0
+decl (Decl
+n "s_i2c_scl_enb"
+t "std_logic"
+o 52
+suid 153,0
+)
+declText (MLText
+uid 10097,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,62800,9500,63700"
+st "SIGNAL s_i2c_scl_enb : std_logic
+"
+)
+)
+*207 (Net
+uid 10122,0
+decl (Decl
+n "s_i2c_sda_enb"
+t "std_logic"
+o 53
+suid 157,0
+)
+declText (MLText
+uid 10123,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,63700,9500,64600"
+st "SIGNAL s_i2c_sda_enb : std_logic
+"
+)
+)
+*208 (SaComponent
+uid 10522,0
+optionalChildren [
+*209 (CptPort
+uid 10434,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10435,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,66625,98000,67375"
+)
+tg (CPTG
+uid 10436,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10437,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,66550,103500,67450"
+st "trigger_i"
+blo "99000,67250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_i"
+t "std_logic"
+eolc "--! goes high to load trigger data. One cycle of clk_4x_logic"
+posAdd 0
+o 5
+suid 1,0
+)
+)
+)
+*210 (CptPort
+uid 10438,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10439,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,69625,98000,70375"
+)
+tg (CPTG
+uid 10440,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10441,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,69550,106500,70450"
+st "clk_4x_logic_i"
+blo "99000,70250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_4x_logic_i"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 1
+suid 2,0
+)
+)
+)
+*211 (CptPort
+uid 10442,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10443,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,72625,98000,73375"
+)
+tg (CPTG
+uid 10444,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10445,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,72550,106500,73450"
+st "logic_strobe_i"
+blo "99000,73250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+)
+)
+*212 (CptPort
+uid 10446,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10447,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,68625,150750,69375"
+)
+tg (CPTG
+uid 10448,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10449,0
+va (VaSet
+font "courier,8,0"
+)
+xt "142000,68550,149000,69450"
+st "data_strobe_o"
+ju 2
+blo "149000,69250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "data_strobe_o"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 19
+suid 4,0
+)
+)
+)
+*213 (CptPort
+uid 10450,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10451,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,75625,150750,76375"
+)
+tg (CPTG
+uid 10452,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10453,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,75550,149000,76450"
+st "trigger_count_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "149000,76250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "trigger_count_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 22
+suid 5,0
+)
+)
+)
+*214 (CptPort
+uid 10454,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10455,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,75625,98000,76375"
+)
+tg (CPTG
+uid 10456,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10457,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,75550,120000,76450"
+st "trigger_times_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "99000,76250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_times_i"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "Array of trigger times ( w.r.t. logic_strobe)"
+preAdd 0
+o 6
+suid 6,0
+)
+)
+)
+*215 (CptPort
+uid 10458,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10459,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,83625,150750,84375"
+)
+tg (CPTG
+uid 10460,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10461,0
+va (VaSet
+font "courier,8,0"
+)
+xt "129000,83550,149000,84450"
+st "event_data_o : (g_EVENT_DATA_WIDTH-1:0)"
+ju 2
+blo "149000,84250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "event_data_o"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 20
+suid 7,0
+)
+)
+)
+*216 (CptPort
+uid 10462,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10463,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,79625,98000,80375"
+)
+tg (CPTG
+uid 10464,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10465,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,79550,106000,80450"
+st "logic_reset_i"
+blo "99000,80250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "goes high to reset counters. Synchronous with clk_4x_logic"
+o 4
+suid 9,0
+)
+)
+)
+*217 (CptPort
+uid 10466,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10467,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,85625,98000,86375"
+)
+tg (CPTG
+uid 10468,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10469,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,85550,123500,86450"
+st "trigger_inputs_fired_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "99000,86250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_inputs_fired_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "high for each input that \"fired\""
+o 7
+suid 10,0
+)
+)
+)
+*218 (CptPort
+uid 10470,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10471,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,86625,98000,87375"
+)
+tg (CPTG
+uid 10472,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10473,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,86550,118000,87450"
+st "edge_fall_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,87250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 14
+suid 11,0
+)
+)
+)
+*219 (CptPort
+uid 10474,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10475,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,87625,98000,88375"
+)
+tg (CPTG
+uid 10476,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10477,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,87550,120500,88450"
+st "edge_fall_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,88250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 16
+suid 12,0
+)
+)
+)
+*220 (CptPort
+uid 10478,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10479,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,88625,98000,89375"
+)
+tg (CPTG
+uid 10480,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10481,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,88550,118000,89450"
+st "edge_rise_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,89250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 13
+suid 13,0
+)
+)
+)
+*221 (CptPort
+uid 10482,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10483,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,89625,98000,90375"
+)
+tg (CPTG
+uid 10484,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10485,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,89550,120500,90450"
+st "edge_rise_time_i : (g_NUM_EDGE_INPUTS-1:0)"
+blo "99000,90250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 15
+suid 14,0
+)
+)
+)
+*222 (CptPort
+uid 10486,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10487,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,81625,98000,82375"
+)
+tg (CPTG
+uid 10488,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10489,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,81550,105000,82450"
+st "ipbus_clk_i"
+blo "99000,82250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 2
+suid 15,0
+)
+)
+)
+*223 (CptPort
+uid 10490,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10491,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,82625,98000,83375"
+)
+tg (CPTG
+uid 10492,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10493,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,82550,102500,83450"
+st "ipbus_i"
+blo "99000,83250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+preAdd 0
+o 17
+suid 16,0
+)
+)
+)
+*224 (CptPort
+uid 10494,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10495,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,95625,150750,96375"
+)
+tg (CPTG
+uid 10496,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10497,0
+va (VaSet
+font "courier,8,0"
+)
+xt "145500,95550,149000,96450"
+st "ipbus_o"
+ju 2
+blo "149000,96250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+o 18
+suid 17,0
+)
+)
+)
+*225 (CptPort
+uid 10498,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10499,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,92625,98000,93375"
+)
+tg (CPTG
+uid 10500,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10501,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,92550,118000,93450"
+st "shutter_cnt_i : (g_COUNTER_WIDTH-1:0)"
+blo "99000,93250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 10
+suid 18,0
+)
+)
+)
+*226 (CptPort
+uid 10502,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10503,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,95625,98000,96375"
+)
+tg (CPTG
+uid 10504,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10505,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,95550,103500,96450"
+st "shutter_i"
+blo "99000,96250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 9
+suid 19,0
+)
+)
+)
+*227 (CptPort
+uid 10506,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10507,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,98625,98000,99375"
+)
+tg (CPTG
+uid 10508,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10509,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,98550,117000,99450"
+st "spill_cnt_i : (g_COUNTER_WIDTH-1:0)"
+blo "99000,99250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_WIDTH-1 DOWNTO 0)"
+o 12
+suid 20,0
+)
+)
+)
+*228 (CptPort
+uid 10510,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10511,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,101625,98000,102375"
+)
+tg (CPTG
+uid 10512,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10513,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,101550,102500,102450"
+st "spill_i"
+blo "99000,102250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 11
+suid 21,0
+)
+)
+)
+*229 (CptPort
+uid 10514,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10515,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "97250,104625,98000,105375"
+)
+tg (CPTG
+uid 10516,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 10517,0
+va (VaSet
+font "courier,8,0"
+)
+xt "99000,104550,120500,105450"
+st "trigger_cnt_i : (g_COUNTER_TRIG_WIDTH-1:0)"
+blo "99000,105250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_COUNTER_TRIG_WIDTH-1 DOWNTO 0)"
+o 8
+suid 22,0
+)
+)
+)
+*230 (CptPort
+uid 10518,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 10519,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "150000,91625,150750,92375"
+)
+tg (CPTG
+uid 10520,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 10521,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130500,91550,149000,92450"
+st "event_number_i : (g_IPBUS_WIDTH-1:0)"
+ju 2
+blo "149000,92250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "event_number_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 21
+suid 23,0
+)
+)
+)
+]
+shape (Rectangle
+uid 10523,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "98000,65000,150000,108000"
+)
+oxt "16000,18000,68000,51000"
+ttg (MlTextGroup
+uid 10524,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*231 (Text
+uid 10525,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,70100,108750,71000"
+st "work"
+blo "106750,70800"
+tm "BdLibraryNameMgr"
+)
+*232 (Text
+uid 10526,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,71000,114250,71900"
+st "eventFormatter"
+blo "106750,71700"
+tm "CptNameMgr"
+)
+*233 (Text
+uid 10527,0
+va (VaSet
+font "courier,8,1"
+)
+xt "106750,71900,107750,72800"
+st "I2"
+blo "106750,72600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 10528,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 10529,0
+text (MLText
+uid 10530,0
+va (VaSet
+font "courier,8,0"
+)
+xt "98000,56800,157000,64000"
+st "g_EVENT_DATA_WIDTH = g_EVENT_DATA_WIDTH ( positive )
+g_IPBUS_WIDTH = g_IPBUS_WIDTH ( positive )
+g_COUNTER_TRIG_WIDTH = g_IPBUS_WIDTH ( positive )
+g_COUNTER_WIDTH = 12 ( positive )
+g_EVTTYPE_WIDTH = 4 ( positive ) -- Width of the event type word
+--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
+g_NUM_EDGE_INPUTS = g_NUM_EDGE_INPUTS ( positive ) -- Number of edge inputs
+g_NUM_TRIG_INPUTS = g_NUM_TRIG_INPUTS ( positive ) -- Number of trigger inputs "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "g_EVENT_DATA_WIDTH"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_TRIG_WIDTH"
+type "positive"
+value "g_IPBUS_WIDTH"
+)
+(GiElement
+name "g_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+(GiElement
+name "g_EVTTYPE_WIDTH"
+type "positive"
+value "4"
+e "-- Width of the event type word"
+)
+(GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "g_NUM_EDGE_INPUTS"
+pr "--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)"
+apr 0
+e "-- Number of edge inputs"
+)
+(GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "g_NUM_TRIG_INPUTS"
+e "-- Number of trigger inputs"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 10531,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "98250,106250,99750,107750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*234 (Net
+uid 10532,0
+lang 11
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 44
+suid 158,0
+)
+declText (MLText
+uid 10533,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,55600,9500,56500"
+st "SIGNAL ipbus_clk_i : std_logic
+"
+)
+)
+*235 (Net
+uid 10562,0
+lang 11
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 36
+suid 161,0
+)
+declText (MLText
+uid 10563,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,48400,42000,49300"
+st "SIGNAL edge_fall_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- ! High when falling edge
+"
+)
+)
+*236 (Net
+uid 10570,0
+lang 11
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 37
+suid 162,0
+)
+declText (MLText
+uid 10571,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,49300,52000,50200"
+st "SIGNAL edge_fall_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+)
+*237 (Net
+uid 10578,0
+lang 11
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 38
+suid 163,0
+)
+declText (MLText
+uid 10579,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,50200,41500,51100"
+st "SIGNAL edge_rise_i : std_logic_vector(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- ! High when rising edge
+"
+)
+)
+*238 (Net
+uid 10586,0
+lang 11
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 39
+suid 164,0
+)
+declText (MLText
+uid 10587,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,51100,52000,52000"
+st "SIGNAL edge_rise_time_i : t_triggerTimeArray(g_NUM_EDGE_INPUTS-1 DOWNTO 0) -- Array of edge times ( w.r.t. logic_strobe)
+"
+)
+)
+*239 (Net
+uid 10594,0
+lang 11
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 54
+suid 165,0
+)
+declText (MLText
+uid 10595,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,64600,30000,65500"
+st "SIGNAL shutter_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*240 (Net
+uid 10602,0
+lang 11
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 55
+suid 166,0
+)
+declText (MLText
+uid 10603,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,65500,9500,66400"
+st "SIGNAL shutter_i : std_logic
+"
+)
+)
+*241 (Net
+uid 10610,0
+lang 11
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 56
+suid 167,0
+)
+declText (MLText
+uid 10611,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,66400,30000,67300"
+st "SIGNAL spill_cnt_i : std_logic_vector(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*242 (Net
+uid 10618,0
+lang 11
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 57
+suid 168,0
+)
+declText (MLText
+uid 10619,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,67300,9500,68200"
+st "SIGNAL spill_i : std_logic
+"
+)
+)
+*243 (Net
+uid 10626,0
+lang 11
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 60
+suid 169,0
+)
+declText (MLText
+uid 10627,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,70000,26000,70900"
+st "SIGNAL trigger_cnt_i : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0)
+"
+)
+)
+*244 (SaComponent
+uid 11070,0
+optionalChildren [
+*245 (CptPort
+uid 11010,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11011,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,43625,165000,44375"
+)
+tg (CPTG
+uid 11012,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11013,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,43550,174500,44450"
+st "clk_logic_xtal_i"
+blo "166000,44250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "clk_logic_xtal_i"
+t "std_logic"
+eolc "! 40MHz clock from onboard xtal"
+o 5
+suid 1,0
+)
+)
+)
+*246 (CptPort
+uid 11014,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 11015,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,36625,165000,37375"
+)
+tg (CPTG
+uid 11016,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11017,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,36550,171500,37450"
+st "extclk_p_b"
+blo "166000,37250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "either external clock in, or a clock being driven out"
+preAdd 0
+o 11
+suid 2,0
+)
+)
+)
+*247 (CptPort
+uid 11018,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11019,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,35625,196750,36375"
+)
+tg (CPTG
+uid 11020,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11021,0
+va (VaSet
+font "courier,8,0"
+)
+xt "187500,35550,195000,36450"
+st "clk_4x_logic_o"
+ju 2
+blo "195000,36250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_4x_logic_o"
+t "std_logic"
+eolc "160MHz clock"
+preAdd 0
+o 7
+suid 3,0
+)
+)
+)
+*248 (CptPort
+uid 11022,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11023,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,38625,196750,39375"
+)
+tg (CPTG
+uid 11024,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11025,0
+va (VaSet
+font "courier,8,0"
+)
+xt "186000,38550,195000,39450"
+st "strobe_4x_logic_o"
+ju 2
+blo "195000,39250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "strobe_4x_logic_o"
+t "std_logic"
+eolc "-- one pulse every 4 cycles of clk_4x"
+preAdd 0
+posAdd 0
+o 10
+suid 4,0
+)
+)
+)
+*249 (CptPort
+uid 11026,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11027,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,41625,196750,42375"
+)
+tg (CPTG
+uid 11028,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11029,0
+va (VaSet
+font "courier,8,0"
+)
+xt "187000,41550,195000,42450"
+st "clk_16x_logic_o"
+ju 2
+blo "195000,42250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_16x_logic_o"
+t "std_logic"
+eolc "-- 640MHz clock"
+posAdd 0
+o 6
+suid 5,0
+)
+)
+)
+*250 (CptPort
+uid 11030,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11031,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,43625,196750,44375"
+)
+tg (CPTG
+uid 11032,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11033,0
+va (VaSet
+font "courier,8,0"
+)
+xt "185500,43550,195000,44450"
+st "strobe_16x_logic_o"
+ju 2
+blo "195000,44250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "strobe_16x_logic_o"
+t "std_logic"
+eolc "-- strobes once every 4 cycles of clk_16x"
+posAdd 0
+o 9
+suid 6,0
+)
+)
+)
+*251 (CptPort
+uid 11034,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11035,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,46625,165000,47375"
+)
+tg (CPTG
+uid 11036,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11037,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,46550,172000,47450"
+st "ipbus_clk_i"
+blo "166000,47250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 1
+suid 7,0
+)
+)
+)
+*252 (CptPort
+uid 11038,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11039,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,50625,165000,51375"
+)
+tg (CPTG
+uid 11040,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11041,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,50550,169500,51450"
+st "ipbus_i"
+blo "166000,51250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+o 2
+suid 8,0
+)
+)
+)
+*253 (CptPort
+uid 11042,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11043,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,46625,196750,47375"
+)
+tg (CPTG
+uid 11044,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11045,0
+va (VaSet
+font "courier,8,0"
+)
+xt "191500,46550,195000,47450"
+st "ipbus_o"
+ju 2
+blo "195000,47250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+o 8
+suid 9,0
+)
+)
+)
+*254 (CptPort
+uid 11046,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11047,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,53625,165000,54375"
+)
+tg (CPTG
+uid 11048,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11049,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,53550,173000,54450"
+st "ipbus_reset_i"
+blo "166000,54250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 3
+suid 10,0
+)
+)
+)
+*255 (CptPort
+uid 11050,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 11051,0
+ro 270
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,39625,165000,40375"
+)
+tg (CPTG
+uid 11052,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11053,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,39550,171500,40450"
+st "extclk_n_b"
+blo "166000,40250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 12
+suid 11,0
+)
+)
+)
+*256 (CptPort
+uid 11054,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11055,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,48625,196750,49375"
+)
+tg (CPTG
+uid 11056,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11057,0
+va (VaSet
+font "courier,8,0"
+)
+xt "189000,48550,195000,49450"
+st "clk_logic_o"
+ju 2
+blo "195000,49250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "clk_logic_o"
+t "std_logic"
+o 13
+suid 13,0
+)
+)
+)
+*257 (CptPort
+uid 11058,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11059,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,51625,196750,52375"
+)
+tg (CPTG
+uid 11060,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11061,0
+va (VaSet
+font "courier,8,0"
+)
+xt "184000,51550,195000,52450"
+st "logic_clocks_locked_o"
+ju 2
+blo "195000,52250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "logic_clocks_locked_o"
+t "std_logic"
+o 14
+suid 14,0
+)
+)
+)
+*258 (CptPort
+uid 11062,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11063,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "196000,54625,196750,55375"
+)
+tg (CPTG
+uid 11064,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11065,0
+va (VaSet
+font "courier,8,0"
+)
+xt "188000,54550,195000,55450"
+st "logic_reset_o"
+ju 2
+blo "195000,55250"
+)
+)
+thePort (LogicalPort
+lang 11
+m 1
+decl (Decl
+n "logic_reset_o"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 15
+suid 15,0
+)
+)
+)
+*259 (CptPort
+uid 11066,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11067,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "164250,54625,165000,55375"
+)
+tg (CPTG
+uid 11068,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11069,0
+va (VaSet
+font "courier,8,0"
+)
+xt "166000,54550,169500,55450"
+st "Reset_i"
+blo "166000,55250"
+)
+)
+thePort (LogicalPort
+lang 11
+decl (Decl
+n "Reset_i"
+t "std_logic"
+o 4
+suid 16,0
+)
+)
+)
+]
+shape (Rectangle
+uid 11071,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "165000,35000,196000,60000"
+)
+oxt "11000,20000,42000,41000"
+ttg (MlTextGroup
+uid 11072,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*260 (Text
+uid 11073,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,37100,178750,38000"
+st "work"
+blo "176750,37800"
+tm "BdLibraryNameMgr"
+)
+*261 (Text
+uid 11074,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,38000,183250,38900"
+st "logic_clocks"
+blo "176750,38700"
+tm "CptNameMgr"
+)
+*262 (Text
+uid 11075,0
+va (VaSet
+font "courier,8,1"
+)
+xt "176750,38900,177750,39800"
+st "I6"
+blo "176750,39600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 11076,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 11077,0
+text (MLText
+uid 11078,0
+va (VaSet
+font "courier,8,0"
+)
+xt "175000,34000,175000,34000"
+)
+header ""
+)
+elements [
+]
+)
+viewicon (ZoomableIcon
+uid 11079,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "165250,58250,166750,59750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*263 (MWC
+uid 11097,0
+optionalChildren [
+*264 (CptPort
+uid 11088,0
+optionalChildren [
+*265 (Line
+uid 11092,0
+layer 5
+sl 0
+va (VaSet
+vasetType 3
+)
+xt "154000,55000,155000,55000"
+pts [
+"154000,55000"
+"155000,55000"
+]
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11089,0
+ro 270
+va (VaSet
+vasetType 1
+isHidden 1
+fg "0,65535,65535"
+)
+xt "153250,54625,154000,55375"
+)
+tg (CPTG
+uid 11090,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11091,0
+sl 0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "358964,483595,360964,484495"
+st "dout"
+blo "358964,484295"
+)
+s (Text
+uid 11106,0
+sl 0
+va (VaSet
+font "courier,8,0"
+)
+xt "358964,484495,358964,484495"
+blo "358964,484495"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "dout"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 48
+suid 1,0
+)
+)
+)
+*266 (CommentGraphic
+uid 11093,0
+shape (PolyLine2D
+pts [
+"155000,55000"
+"155000,56000"
+]
+uid 11094,0
+layer 0
+sl 0
+va (VaSet
+vasetType 1
+transparent 1
+fg "49152,49152,49152"
+)
+xt "155000,55000,155000,56000"
+)
+oxt "7000,7000,7000,8000"
+)
+*267 (CommentGraphic
+uid 11095,0
+shape (CustomPolygon
+pts [
+"154000,56000"
+"156000,56000"
+"155000,57000"
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+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 48
+suid 171,0
+)
+declText (MLText
+uid 11203,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,59200,39000,60100"
+st "SIGNAL logic_clocks_reset : std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
+"
+)
+)
+*312 (PortIoOut
+uid 11458,0
+shape (CompositeShape
+uid 11459,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11460,0
+sl 0
+ro 270
+xt "73500,151625,75000,152375"
+)
+(Line
+uid 11461,0
+sl 0
+ro 270
+xt "73000,152000,73500,152000"
+pts [
+"73000,152000"
+"73500,152000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 11462,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 11463,0
+va (VaSet
+font "courier,8,0"
+)
+xt "76000,151550,80000,152450"
+st "gpio_hdr"
+blo "76000,152250"
+tm "WireNameMgr"
+)
+)
+)
+*313 (Net
+uid 11470,0
+lang 2
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 20
+suid 172,0
+)
+declText (MLText
+uid 11471,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-10000,33100,15500,34000"
+st "gpio_hdr : std_logic_vector(7 DOWNTO 0)
+"
+)
+)
+*314 (SaComponent
+uid 11619,0
+optionalChildren [
+*315 (CptPort
+uid 11542,0
+optionalChildren [
+*316 (FFT
+pts [
+"13750,127000"
+"13000,127375"
+"13000,126625"
+]
+uid 11546,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "13000,126625,13750,127375"
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11543,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,126625,13000,127375"
+)
+tg (CPTG
+uid 11544,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11545,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,126550,20500,127450"
+st "clk_4x_logic"
+blo "14000,127250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 3
+suid 1,0
+)
+)
+)
+*317 (CptPort
+uid 11547,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11548,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,128625,13000,129375"
+)
+tg (CPTG
+uid 11549,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11550,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,128550,23000,129450"
+st "strobe_4x_logic_i"
+blo "14000,129250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 4
+suid 2,0
+)
+)
+)
+*318 (CptPort
+uid 11551,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11552,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,135625,13000,136375"
+)
+tg (CPTG
+uid 11553,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11554,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,135550,34500,136450"
+st "threshold_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "14000,136250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 5
+suid 3,0
+)
+)
+)
+*319 (CptPort
+uid 11555,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11556,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,139625,13000,140375"
+)
+tg (CPTG
+uid 11557,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11558,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,139550,31500,140450"
+st "cfd_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "14000,140250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 1
+suid 4,0
+)
+)
+)
+*320 (CptPort
+uid 11559,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11560,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,129625,58750,130375"
+)
+tg (CPTG
+uid 11561,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11562,0
+va (VaSet
+font "courier,8,0"
+)
+xt "38500,129550,57000,130450"
+st "trigger_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,130250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 7
+suid 5,0
+)
+)
+)
+*321 (CptPort
+uid 11563,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11564,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,137625,58750,138375"
+)
+tg (CPTG
+uid 11565,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11566,0
+va (VaSet
+font "courier,8,0"
+)
+xt "41500,137550,57000,138450"
+st "trigger_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,138250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger active"
+o 8
+suid 7,0
+)
+)
+)
+*322 (CptPort
+uid 11567,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11568,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,144625,13000,145375"
+)
+tg (CPTG
+uid 11569,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11570,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,144550,20000,145450"
+st "ipbus_clk_i"
+blo "14000,145250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+preAdd 0
+o 14
+suid 8,0
+)
+)
+)
+*323 (CptPort
+uid 11571,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11572,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,147625,13000,148375"
+)
+tg (CPTG
+uid 11573,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11574,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,147550,17500,148450"
+st "ipbus_i"
+blo "14000,148250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 16
+suid 9,0
+)
+)
+)
+*324 (CptPort
+uid 11575,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11576,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,146625,58750,147375"
+)
+tg (CPTG
+uid 11577,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11578,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53500,146550,57000,147450"
+st "ipbus_o"
+ju 2
+blo "57000,147250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 17
+suid 10,0
+)
+)
+)
+*325 (CptPort
+uid 11579,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11580,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,149625,13000,150375"
+)
+tg (CPTG
+uid 11581,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11582,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,149550,21000,150450"
+st "ipbus_reset_i"
+blo "14000,150250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 15
+suid 11,0
+)
+)
+)
+*326 (CptPort
+uid 11583,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11584,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,131625,13000,132375"
+)
+tg (CPTG
+uid 11585,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11586,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,131550,22000,132450"
+st "clk_16x_logic_i"
+blo "14000,132250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_16x_logic_i"
+t "std_logic"
+eolc "--! 640MHz clock ( 16x 40MHz )"
+o 18
+suid 13,0
+)
+)
+)
+*327 (CptPort
+uid 11587,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11588,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,133625,13000,134375"
+)
+tg (CPTG
+uid 11589,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11590,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,133550,23500,134450"
+st "strobe_16x_logic_i"
+blo "14000,134250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_16x_logic_i"
+t "std_logic"
+eolc "--! Pulses one cycle every 4 of 16x clock."
+o 19
+suid 14,0
+)
+)
+)
+*328 (CptPort
+uid 11591,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11592,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,140625,13000,141375"
+)
+tg (CPTG
+uid 11593,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11594,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,140550,31500,141450"
+st "cfd_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "14000,141250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 2
+suid 15,0
+)
+)
+)
+*329 (CptPort
+uid 11595,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11596,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,136625,13000,137375"
+)
+tg (CPTG
+uid 11597,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 11598,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,136550,34500,137450"
+st "threshold_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "14000,137250"
+)
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 6
+suid 16,0
+)
+)
+)
+*330 (CptPort
+uid 11599,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11600,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,147625,58750,148375"
+)
+tg (CPTG
+uid 11601,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11602,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39000,147550,57000,148450"
+st "edge_falling_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,148250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 13
+suid 17,0
+)
+)
+)
+*331 (CptPort
+uid 11603,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11604,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,148625,58750,149375"
+)
+tg (CPTG
+uid 11605,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11606,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36000,148550,57000,149450"
+st "edge_falling_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,149250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 11
+suid 18,0
+)
+)
+)
+*332 (CptPort
+uid 11607,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11608,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,149625,58750,150375"
+)
+tg (CPTG
+uid 11609,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11610,0
+va (VaSet
+font "courier,8,0"
+)
+xt "39500,149550,57000,150450"
+st "edge_rising_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,150250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+preAdd 0
+posAdd 0
+o 12
+suid 19,0
+)
+)
+)
+*333 (CptPort
+uid 11611,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11612,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,150625,58750,151375"
+)
+tg (CPTG
+uid 11613,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11614,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,150550,57000,151450"
+st "edge_rising_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "57000,151250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 10
+suid 20,0
+)
+)
+)
+*334 (CptPort
+uid 11615,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 11616,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "58000,151625,58750,152375"
+)
+tg (CPTG
+uid 11617,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 11618,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35500,151550,57000,152450"
+st "trigger_debug_o : (((2*g_NUM_INPUTS)-1):0)"
+ju 2
+blo "57000,152250"
+)
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_debug_o"
+t "std_logic_vector"
+b "( ((2*g_NUM_INPUTS)-1) DOWNTO 0)"
+eolc "-- ! Copy of input trigger level. High bits CFD, Low threshold"
+posAdd 0
+o 9
+suid 21,0
+)
+)
+)
+]
+shape (Rectangle
+uid 11620,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "13000,126000,58000,153000"
+)
+oxt "7000,16000,52000,43000"
+ttg (MlTextGroup
+uid 11621,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*335 (Text
+uid 11622,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,141100,31750,142000"
+st "work"
+blo "29750,141800"
+tm "BdLibraryNameMgr"
+)
+*336 (Text
+uid 11623,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,142000,36750,142900"
+st "triggerInputs"
+blo "29750,142700"
+tm "CptNameMgr"
+)
+*337 (Text
+uid 11624,0
+va (VaSet
+font "courier,8,1"
+)
+xt "29750,142900,30750,143800"
+st "I1"
+blo "29750,143600"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 11625,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 11626,0
+text (MLText
+uid 11627,0
+va (VaSet
+font "courier,8,0"
+)
+xt "26000,124100,51000,125000"
+st "g_NUM_INPUTS = g_NUM_TRIG_INPUTS ( natural ) "
+)
+header ""
+)
+elements [
+(GiElement
+name "g_NUM_INPUTS"
+type "natural"
+value "g_NUM_TRIG_INPUTS"
+)
+]
+)
+viewicon (ZoomableIcon
+uid 11628,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "13250,151250,14750,152750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+ordering 1
+viewiconposition 0
+portVis (PortSigDisplay
+sIVOD 1
+)
+archFileType "UNKNOWN"
+)
+*338 (Wire
+uid 29,0
+shape (OrthoPolyLine
+uid 30,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "5000,140000,12250,140000"
+pts [
+"5000,140000"
+"12250,140000"
+]
+)
+start &1
+end &319
+sat 32
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 33,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 34,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "7000,139100,14000,140000"
+st "cfd_discr_p_i"
+blo "7000,139800"
+tm "WireNameMgr"
+)
+)
+on &2
+)
+*339 (Wire
+uid 57,0
+shape (OrthoPolyLine
+uid 58,0
+va (VaSet
+vasetType 3
+)
+xt "128750,18000,135000,18000"
+pts [
+"135000,18000"
+"128750,18000"
+]
+)
+start &3
+end &62
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 62,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,17100,141500,18000"
+st "gmii_gtx_clk_o"
+blo "134000,17800"
+tm "WireNameMgr"
+)
+)
+on &4
+)
+*340 (Wire
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+shape (OrthoPolyLine
+uid 72,0
+va (VaSet
+vasetType 3
+)
+xt "80000,10000,94250,10000"
+pts [
+"80000,10000"
+"94250,10000"
+]
+)
+start &5
+end &54
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 76,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,9100,89000,10000"
+st "gmii_rx_clk_i"
+blo "82000,9800"
+tm "WireNameMgr"
+)
+)
+on &6
+)
+*341 (Wire
+uid 85,0
+shape (OrthoPolyLine
+uid 86,0
+va (VaSet
+vasetType 3
+)
+xt "80000,13000,94250,13000"
+pts [
+"80000,13000"
+"94250,13000"
+]
+)
+start &7
+end &55
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 90,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,12100,88500,13000"
+st "gmii_rx_dv_i"
+blo "82000,12800"
+tm "WireNameMgr"
+)
+)
+on &8
+)
+*342 (Wire
+uid 99,0
+shape (OrthoPolyLine
+uid 100,0
+va (VaSet
+vasetType 3
+)
+xt "80000,16000,94250,16000"
+pts [
+"80000,16000"
+"94250,16000"
+]
+)
+start &9
+end &56
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 104,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,15100,88500,16000"
+st "gmii_rx_er_i"
+blo "82000,15800"
+tm "WireNameMgr"
+)
+)
+on &10
+)
+*343 (Wire
+uid 113,0
+shape (OrthoPolyLine
+uid 114,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "80000,19000,94250,19000"
+pts [
+"80000,19000"
+"94250,19000"
+]
+)
+start &11
+end &57
+sat 32
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 118,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "82000,18100,87500,19000"
+st "gmii_rxd_i"
+blo "82000,18800"
+tm "WireNameMgr"
+)
+)
+on &12
+)
+*344 (Wire
+uid 127,0
+shape (OrthoPolyLine
+uid 128,0
+va (VaSet
+vasetType 3
+)
+xt "128750,9000,135000,9000"
+pts [
+"135000,9000"
+"128750,9000"
+]
+)
+start &13
+end &58
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,8100,140500,9000"
+st "gmii_tx_en_o"
+blo "134000,8800"
+tm "WireNameMgr"
+)
+)
+on &14
+)
+*345 (Wire
+uid 141,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "128750,11000,135000,11000"
+pts [
+"135000,11000"
+"128750,11000"
+]
+)
+start &15
+end &59
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 146,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,10100,140500,11000"
+st "gmii_tx_er_o"
+blo "134000,10800"
+tm "WireNameMgr"
+)
+)
+on &16
+)
+*346 (Wire
+uid 155,0
+shape (OrthoPolyLine
+uid 156,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "128750,14000,135000,14000"
+pts [
+"135000,14000"
+"128750,14000"
+]
+)
+start &17
+end &60
+sat 32
+eat 32
+sty 1
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+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 160,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,13100,139500,14000"
+st "gmii_txd_o"
+blo "134000,13800"
+tm "WireNameMgr"
+)
+)
+on &18
+)
+*347 (Wire
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+shape (OrthoPolyLine
+uid 170,0
+va (VaSet
+vasetType 3
+)
+xt "211750,15000,217000,15000"
+pts [
+"217000,15000"
+"211750,15000"
+]
+)
+start &155
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 174,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "216000,14100,220500,15000"
+st "i2c_scl_b"
+blo "216000,14800"
+tm "WireNameMgr"
+)
+)
+on &19
+)
+*348 (Wire
+uid 183,0
+shape (OrthoPolyLine
+uid 184,0
+va (VaSet
+vasetType 3
+)
+xt "211750,13000,217000,13000"
+pts [
+"217000,13000"
+"211750,13000"
+]
+)
+start &20
+sat 32
+eat 16
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 188,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "219000,12100,223500,13000"
+st "i2c_sda_b"
+blo "219000,12800"
+tm "WireNameMgr"
+)
+)
+on &21
+)
+*349 (Wire
+uid 211,0
+shape (OrthoPolyLine
+uid 212,0
+va (VaSet
+vasetType 3
+)
+xt "128750,16000,135000,16000"
+pts [
+"135000,16000"
+"128750,16000"
+]
+)
+start &22
+end &61
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 216,0
+va (VaSet
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+font "courier,8,0"
+)
+xt "134000,15100,139500,16000"
+st "phy_rstb_o"
+blo "134000,15800"
+tm "WireNameMgr"
+)
+)
+on &23
+)
+*350 (Wire
+uid 253,0
+shape (OrthoPolyLine
+uid 254,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "5000,136000,12250,136000"
+pts [
+"5000,136000"
+"12250,136000"
+]
+)
+start &24
+end &318
+sat 32
+eat 32
+sty 1
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 257,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 258,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "7000,135100,17000,136000"
+st "threshold_discr_p_i"
+blo "7000,135800"
+tm "WireNameMgr"
+)
+)
+on &25
+)
+*351 (Wire
+uid 751,0
+shape (OrthoPolyLine
+uid 752,0
+va (VaSet
+vasetType 3
+)
+xt "80000,22000,94250,22000"
+pts [
+"80000,22000"
+"94250,22000"
+]
+)
+start &37
+end &63
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 755,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 756,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "82000,21100,87500,22000"
+st "sysclk_n_i"
+blo "82000,21800"
+tm "WireNameMgr"
+)
+)
+on &114
+)
+*352 (Wire
+uid 765,0
+shape (OrthoPolyLine
+uid 766,0
+va (VaSet
+vasetType 3
+)
+xt "80000,25000,94250,25000"
+pts [
+"80000,25000"
+"94250,25000"
+]
+)
+start &38
+end &64
+sat 32
+eat 32
+stc 0
+st 0
+sf 1
+si 0
+tg (WTG
+uid 769,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 770,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "82000,24100,87500,25000"
+st "sysclk_p_i"
+blo "82000,24800"
+tm "WireNameMgr"
+)
+)
+on &113
+)
+*353 (Wire
+uid 1215,0
+shape (OrthoPolyLine
+uid 1216,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,101000,9250,101000"
+pts [
+"9250,101000"
+"-4000,101000"
+]
+)
+start &139
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1219,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1220,0
+va (VaSet
+font "courier,8,0"
+)
+xt "250,100100,8250,101000"
+st "strobe_4x_logic"
+blo "250,100800"
+tm "WireNameMgr"
+)
+)
+on &81
+)
+*354 (Wire
+uid 1304,0
+shape (OrthoPolyLine
+uid 1305,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,99000,9250,99000"
+pts [
+"-4000,99000"
+"9250,99000"
+]
+)
+end &138
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1308,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1309,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,98100,4500,99000"
+st "clk_4x_logic"
+blo "-2000,98800"
+tm "WireNameMgr"
+)
+)
+on &39
+)
+*355 (Wire
+uid 1359,0
+shape (OrthoPolyLine
+uid 1360,0
+va (VaSet
+vasetType 3
+)
+xt "128750,20000,136000,20000"
+pts [
+"128750,20000"
+"136000,20000"
+]
+)
+start &65
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1363,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1364,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130750,19100,135250,20000"
+st "ipbus_clk"
+blo "130750,19800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*356 (Wire
+uid 1367,0
+shape (OrthoPolyLine
+uid 1368,0
+va (VaSet
+vasetType 3
+)
+xt "128750,23000,136000,23000"
+pts [
+"128750,23000"
+"136000,23000"
+]
+)
+start &66
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1371,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1372,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130750,22100,135250,23000"
+st "ipbus_rst"
+blo "130750,22800"
+tm "WireNameMgr"
+)
+)
+on &154
+)
+*357 (Wire
+uid 1383,0
+shape (OrthoPolyLine
+uid 1384,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "128750,25000,136000,25000"
+pts [
+"128750,25000"
+"136000,25000"
+]
+)
+start &67
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+tg (WTG
+uid 1387,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1388,0
+va (VaSet
+font "courier,8,0"
+)
+xt "130000,24100,145000,25000"
+st "ipbw : (g_NUM_EXT_SLAVES-1:0)"
+blo "130000,24800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*358 (Wire
+uid 1391,0
+shape (OrthoPolyLine
+uid 1392,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "79000,28000,94250,28000"
+pts [
+"94250,28000"
+"79000,28000"
+]
+)
+start &68
+sat 32
+eat 16
+sty 1
+st 0
+sf 1
+tg (WTG
+uid 1395,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1396,0
+va (VaSet
+font "courier,8,0"
+)
+xt "80000,27100,95000,28000"
+st "ipbr : (g_NUM_EXT_SLAVES-1:0)"
+blo "80000,27800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
+*359 (Wire
+uid 1415,0
+shape (OrthoPolyLine
+uid 1416,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,105000,9250,105000"
+pts [
+"9250,105000"
+"-4000,105000"
+]
+)
+start &141
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1419,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1420,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,104100,2500,105000"
+st "ipbus_clk"
+blo "-2000,104800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*360 (Wire
+uid 1423,0
+shape (OrthoPolyLine
+uid 1424,0
+va (VaSet
+vasetType 3
+)
+xt "-4000,107000,9250,107000"
+pts [
+"9250,107000"
+"-4000,107000"
+]
+)
+start &142
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
+uid 1427,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1428,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,106100,4000,107000"
+st "ipbus_reset"
+blo "-2000,106800"
+tm "WireNameMgr"
+)
+)
+on &41
+)
+*361 (Wire
+uid 1672,0
+shape (OrthoPolyLine
+uid 1673,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "-4000,109000,9250,109000"
+pts [
+"-4000,109000"
+"9250,109000"
+]
+)
+end &143
+sat 16
+eat 32
+sty 1
+sl "(0)"
+st 0
+sf 1
+tg (WTG
+uid 1676,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1677,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-2000,108100,14500,109000"
+st "ipbw(0) : (g_NUM_EXT_SLAVES-1:0)"
+blo "-2000,108800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*362 (Wire
+uid 1680,0
+shape (OrthoPolyLine
+uid 1681,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55750,104000,65000,104000"
+pts [
+"55750,104000"
+"65000,104000"
+]
+)
+start &144
+sat 32
+eat 16
+sty 1
+sl "(0)"
+st 0
+sf 1
+tg (WTG
+uid 1684,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1685,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,103100,74500,104000"
+st "ipbr(0) : (g_NUM_EXT_SLAVES-1:0)"
+blo "58000,103800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
+*363 (Wire
+uid 1698,0
+shape (OrthoPolyLine
+uid 1699,0
+va (VaSet
+vasetType 3
+)
+xt "2000,127000,12250,127000"
+pts [
+"2000,127000"
+"12250,127000"
+]
+)
+end &315
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1702,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1703,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,126100,10500,127000"
+st "clk_4x_logic"
+blo "4000,126800"
+tm "WireNameMgr"
+)
+)
+on &39
+)
+*364 (Wire
+uid 1706,0
+shape (OrthoPolyLine
+uid 1707,0
+va (VaSet
+vasetType 3
+)
+xt "2000,129000,12250,129000"
+pts [
+"2000,129000"
+"12250,129000"
+]
+)
+end &317
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1710,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1711,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,128100,12000,129000"
+st "strobe_4x_logic"
+blo "4000,128800"
+tm "WireNameMgr"
+)
+)
+on &81
+)
+*365 (Wire
+uid 1714,0
+shape (OrthoPolyLine
+uid 1715,0
+va (VaSet
+vasetType 3
+)
+xt "2000,145000,12250,145000"
+pts [
+"2000,145000"
+"12250,145000"
+]
+)
+end &322
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1718,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1719,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,144100,7500,145000"
+st "ipbus_clk"
+blo "3000,144800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*366 (Wire
+uid 1722,0
+shape (OrthoPolyLine
+uid 1723,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "2000,148000,12250,148000"
+pts [
+"2000,148000"
+"12250,148000"
+]
+)
+end &323
+sat 16
+eat 32
+sty 1
+sl "(1)"
+st 0
+sf 1
+tg (WTG
+uid 1726,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1727,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,147100,20500,148000"
+st "ipbw(1) : (g_NUM_EXT_SLAVES-1:0)"
+blo "4000,147800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*367 (Wire
+uid 1730,0
+shape (OrthoPolyLine
+uid 1731,0
+va (VaSet
+vasetType 3
+)
+xt "2000,150000,12250,150000"
+pts [
+"2000,150000"
+"12250,150000"
+]
+)
+end &325
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
+uid 1734,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1735,0
+va (VaSet
+font "courier,8,0"
+)
+xt "4000,149100,10000,150000"
+st "ipbus_reset"
+blo "4000,149800"
+tm "WireNameMgr"
+)
+)
+on &41
+)
+*368 (Wire
+uid 1746,0
+shape (OrthoPolyLine
+uid 1747,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "143750,150000,160000,150000"
+pts [
+"143750,150000"
+"160000,150000"
+]
+)
+start &161
+sat 32
+eat 16
+sty 1
+sl "(2)"
+st 0
+sf 1
+tg (WTG
+uid 1750,0
+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 1751,0
+va (VaSet
+font "courier,8,0"
+)
+xt "150750,149100,167250,150000"
+st "ipbr(2) : (g_NUM_EXT_SLAVES-1:0)"
+blo "150750,149800"
+tm "WireNameMgr"
+)
+)
+on &43
+)
+*369 (Wire
+uid 1754,0
+shape (OrthoPolyLine
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+]
+)
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+"98000,135000"
+]
+)
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+)
+)
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+)
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+"87000,140000"
+"87000,122000"
+"84000,122000"
+]
+)
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+"98000,143000"
+]
+)
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+)
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+)
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+"98000,145000"
+]
+)
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+)
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+)
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+"98000,148000"
+]
+)
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+)
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+]
+)
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+)
+)
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+)
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+)
+)
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+)
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+)
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+)
+)
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+)
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+]
+)
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+)
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+)
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+)
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+"85000,70000"
+]
+)
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+)
+)
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+)
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+"86000,73000"
+]
+)
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+)
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+)
+)
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+"158000,69000"
+"165250,69000"
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+)
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+)
+)
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+)
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+"198000,4000"
+"208000,4000"
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+)
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+)
+)
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+)
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+"58750,130000"
+"69000,130000"
+"69000,76000"
+"97250,76000"
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+)
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+)
+)
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+)
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+)
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+"150750,84000"
+"155000,84000"
+"155000,77000"
+"165250,77000"
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+)
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+)
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+)
+)
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+)
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+"165250,74000"
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+)
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+)
+)
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+)
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+)
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+"155000,72000"
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+)
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+)
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+)
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+"165250,79000"
+"157000,79000"
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+)
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+)
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+)
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+"165250,84000"
+"157000,84000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"165250,81000"
+"157000,81000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"209750,74000"
+"219000,74000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,36000"
+"219000,36000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,39000"
+"219000,39000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,42000"
+"219000,42000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,44000"
+"219000,44000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"196750,47000"
+"219000,47000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+"164250,54000"
+"155000,54000"
+]
+)
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"164250,51000"
+"155000,51000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"164250,47000"
+"155000,47000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"164250,44000"
+"155000,44000"
+]
+)
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+)
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+)
+)
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+)
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+)
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+pts [
+"157000,37000"
+"164250,37000"
+]
+)
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+)
+xt "159000,36100,164500,37000"
+st "extclk_p_b"
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+)
+)
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+)
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+)
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+pts [
+"157000,40000"
+"164250,40000"
+]
+)
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+end &255
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+)
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+st "extclk_n_b"
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+)
+)
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+)
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+)
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+pts [
+"128750,32000"
+"136000,32000"
+]
+)
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+)
+xt "130750,31100,138250,32000"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"165250,86000"
+"157000,86000"
+]
+)
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+)
+xt "155250,85100,163250,86000"
+st "strobe_4x_logic"
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+)
+)
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+)
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+)
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+pts [
+"55750,108000"
+"74000,108000"
+"74000,123000"
+"78000,123000"
+]
+)
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+)
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+st "veto_o"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+"209750,85000"
+"211000,85000"
+"211000,117000"
+"77000,117000"
+"77000,121000"
+"78000,121000"
+]
+)
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+end &88
+sat 32
+eat 32
+st 0
+sf 1
+tg (WTG
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+)
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"12250,132000"
+"2000,132000"
+]
+)
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+sf 1
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+stg "STSignalDisplayStrategy"
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+)
+xt "3250,131100,10250,132000"
+st "clk_16x_logic"
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+tm "WireNameMgr"
+)
+)
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+)
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+)
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+pts [
+"12250,134000"
+"2000,134000"
+]
+)
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+)
+xt "1250,133100,9750,134000"
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+tm "WireNameMgr"
+)
+)
+on &83
+)
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+)
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+pts [
+"5000,141000"
+"12250,141000"
+]
+)
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+end &328
+sat 32
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+)
+xt "6000,140100,13000,141000"
+st "cfd_discr_n_i"
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+tm "WireNameMgr"
+)
+)
+on &110
+)
+*411 (Wire
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+)
+xt "5000,137000,12250,137000"
+pts [
+"5000,137000"
+"12250,137000"
+]
+)
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+)
+xt "3000,136100,13000,137000"
+st "threshold_discr_n_i"
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+tm "WireNameMgr"
+)
+)
+on &112
+)
+*412 (Wire
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+)
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+pts [
+"128750,30000"
+"136000,30000"
+]
+)
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+)
+xt "130750,29100,139750,30000"
+st "leds_o(2) : (3:0)"
+blo "130750,29800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
+*413 (Wire
+uid 6540,0
+shape (OrthoPolyLine
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+)
+xt "128750,27000,136000,27000"
+pts [
+"128750,27000"
+"136000,27000"
+]
+)
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+sat 32
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+stg "STSignalDisplayStrategy"
+f (Text
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+)
+xt "130750,26100,139750,27000"
+st "leds_o(3) : (3:0)"
+blo "130750,26800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
+*414 (Wire
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+lineWidth 2
+)
+xt "196750,52000,219000,52000"
+pts [
+"196750,52000"
+"219000,52000"
+]
+)
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+f (Text
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+)
+xt "198750,51100,207750,52000"
+st "leds_o(1) : (3:0)"
+blo "198750,51800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
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+)
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+pts [
+"143750,142000"
+"160000,142000"
+]
+)
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+)
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+st "leds_o(0) : (3:0)"
+blo "145750,141800"
+tm "WireNameMgr"
+)
+)
+on &50
+)
+*416 (Wire
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+shape (OrthoPolyLine
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+lineWidth 2
+)
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+pts [
+"55750,90000"
+"64000,90000"
+]
+)
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+)
+xt "56000,89100,72000,90000"
+st "triggers_p_o : (g_NUM_DUTS-1:0)"
+blo "56000,89800"
+tm "WireNameMgr"
+)
+)
+on &116
+)
+*417 (Wire
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+)
+xt "0,89000,9250,89000"
+pts [
+"0,89000"
+"9250,89000"
+]
+)
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+end &134
+es 0
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+sf 1
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+f (Text
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+va (VaSet
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+)
+xt "1000,88100,15000,89000"
+st "busy_p_i : (g_NUM_DUTS-1:0)"
+blo "1000,88800"
+tm "WireNameMgr"
+)
+)
+on &118
+)
+*418 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "55750,97000,64000,97000"
+pts [
+"55750,97000"
+"64000,97000"
+]
+)
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+sf 1
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+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,96100,74000,97000"
+st "reset_or_clk_p_o : (g_NUM_DUTS-1:0)"
+blo "56000,96800"
+tm "WireNameMgr"
+)
+)
+on &120
+)
+*419 (Wire
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+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "0,93000,9250,93000"
+pts [
+"0,93000"
+"9250,93000"
+]
+)
+start &121
+end &136
+sat 32
+eat 32
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+sf 1
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+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "1000,92100,16500,93000"
+st "dut_clk_p_i : (g_NUM_DUTS-1:0)"
+blo "1000,92800"
+tm "WireNameMgr"
+)
+)
+on &122
+)
+*420 (Wire
+uid 6778,0
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "0,91000,9250,91000"
+pts [
+"0,91000"
+"9250,91000"
+]
+)
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+end &147
+sat 32
+eat 32
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+st 0
+sf 1
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+stg "STSignalDisplayStrategy"
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+va (VaSet
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+font "courier,8,0"
+)
+xt "1000,90100,15000,91000"
+st "busy_n_i : (g_NUM_DUTS-1:0)"
+blo "1000,90800"
+tm "WireNameMgr"
+)
+)
+on &125
+)
+*421 (Wire
+uid 6792,0
+shape (OrthoPolyLine
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+va (VaSet
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+lineWidth 2
+)
+xt "55750,99000,64000,99000"
+pts [
+"55750,99000"
+"64000,99000"
+]
+)
+start &148
+end &126
+ss 0
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+eat 32
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+sf 1
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+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,98100,74000,99000"
+st "reset_or_clk_n_o : (g_NUM_DUTS-1:0)"
+blo "56000,98800"
+tm "WireNameMgr"
+)
+)
+on &127
+)
+*422 (Wire
+uid 6806,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "55750,92000,64000,92000"
+pts [
+"55750,92000"
+"64000,92000"
+]
+)
+start &146
+end &128
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+font "courier,8,0"
+)
+xt "56000,91100,72000,92000"
+st "triggers_n_o : (g_NUM_DUTS-1:0)"
+blo "56000,91800"
+tm "WireNameMgr"
+)
+)
+on &129
+)
+*423 (Wire
+uid 6820,0
+shape (OrthoPolyLine
+uid 6821,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "0,95000,9250,95000"
+pts [
+"0,95000"
+"9250,95000"
+]
+)
+start &130
+end &149
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6825,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "1000,94100,16500,95000"
+st "dut_clk_n_i : (g_NUM_DUTS-1:0)"
+blo "1000,94800"
+tm "WireNameMgr"
+)
+)
+on &131
+)
+*424 (Wire
+uid 6914,0
+shape (OrthoPolyLine
+uid 6915,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "80000,31000,94250,31000"
+pts [
+"80000,31000"
+"94250,31000"
+]
+)
+start &153
+end &71
+es 0
+sat 32
+eat 32
+sty 1
+st 0
+sf 1
+si 0
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 6919,0
+va (VaSet
+isHidden 1
+font "courier,8,0"
+)
+xt "86000,30100,96500,31000"
+st "dip_switch_i : (3:0)"
+blo "86000,30800"
+tm "WireNameMgr"
+)
+)
+on &123
+)
+*425 (Wire
+uid 8086,0
+shape (OrthoPolyLine
+uid 8087,0
+va (VaSet
+vasetType 3
+)
+xt "160000,10000,171250,10000"
+pts [
+"171250,10000"
+"160000,10000"
+]
+)
+start &191
+sat 32
+eat 16
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8091,0
+va (VaSet
+font "courier,8,0"
+)
+xt "164250,9100,168750,10000"
+st "ipbus_clk"
+blo "164250,9800"
+tm "WireNameMgr"
+)
+)
+on &40
+)
+*426 (Wire
+uid 8094,0
+shape (OrthoPolyLine
+uid 8095,0
+va (VaSet
+vasetType 3
+lineWidth 2
+)
+xt "160000,17000,171250,17000"
+pts [
+"160000,17000"
+"171250,17000"
+]
+)
+end &192
+sat 16
+eat 32
+sty 1
+sl "(5)"
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 8099,0
+va (VaSet
+font "courier,8,0"
+)
+xt "162000,16100,178500,17000"
+st "ipbw(5) : (g_NUM_EXT_SLAVES-1:0)"
+blo "162000,16800"
+tm "WireNameMgr"
+)
+)
+on &42
+)
+*427 (Wire
+uid 8102,0
+shape (OrthoPolyLine
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+va (VaSet
+vasetType 3
+)
+xt "160000,24000,171250,24000"
+pts [
+"160000,24000"
+"171250,24000"
+]
+)
+end &194
+sat 16
+eat 32
+st 0
+sf 1
+tg (WTG
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+ps "ConnStartEndStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
+font "courier,8,0"
+)
+xt "162000,23100,168000,24000"
+st "ipbus_reset"
+blo "162000,23800"
+tm "WireNameMgr"
+)
+)
+on &41
+)
+*428 (Wire
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+)
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+)
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+*486 (RefLabelRowHdr
+)
+*487 (TitleRowHdr
+)
+*488 (FilterRowHdr
+)
+*489 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*490 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*491 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*492 (NameColHdr
+tm "BlockDiagramNameColHdrMgr"
+)
+*493 (ModeColHdr
+tm "BlockDiagramModeColHdrMgr"
+)
+*494 (TypeColHdr
+tm "BlockDiagramTypeColHdrMgr"
+)
+*495 (BoundsColHdr
+tm "BlockDiagramBoundsColHdrMgr"
+)
+*496 (InitColHdr
+tm "BlockDiagramInitColHdrMgr"
+)
+*497 (EolColHdr
+tm "BlockDiagramEolColHdrMgr"
+)
+*498 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 16
+suid 4,0
+)
+)
+uid 279,0
+)
+*499 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 17
+suid 9,0
+)
+)
+uid 281,0
+)
+*500 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 18
+suid 10,0
+)
+)
+uid 283,0
+)
+*501 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_clk_i"
+t "std_logic"
+o 8
+suid 5,0
+)
+)
+uid 285,0
+)
+*502 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 9
+suid 6,0
+)
+)
+uid 287,0
+)
+*503 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 10
+suid 7,0
+)
+)
+uid 289,0
+)
+*504 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 11
+suid 8,0
+)
+)
+uid 291,0
+)
+*505 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 22
+suid 15,0
+)
+)
+uid 293,0
+)
+*506 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 19
+suid 11,0
+)
+)
+uid 295,0
+)
+*507 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 15
+suid 18,0
+)
+)
+uid 305,0
+)
+*508 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 4
+suid 2,0
+)
+)
+uid 307,0
+)
+*509 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_scl_b"
+t "std_logic"
+o 29
+suid 12,0
+)
+)
+uid 309,0
+)
+*510 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_sda_b"
+t "std_logic"
+o 30
+suid 13,0
+)
+)
+uid 311,0
+)
+*511 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "--! normally 160MHz"
+o 33
+suid 26,0
+)
+)
+uid 1223,0
+)
+*512 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_clk"
+t "std_logic"
+o 43
+suid 39,0
+)
+)
+uid 2119,0
+)
+*513 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_reset"
+t "std_logic"
+o 45
+suid 40,0
+)
+)
+uid 2121,0
+)
+*514 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbw"
+t "ipb_wbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IBus write signals"
+o 47
+suid 41,0
+)
+)
+uid 2123,0
+)
+*515 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbr"
+t "ipb_rbus_array"
+b "(g_NUM_EXT_SLAVES-1 DOWNTO 0)"
+eolc "--! IPBus read signals"
+o 42
+suid 42,0
+)
+)
+uid 2125,0
+)
+*516 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "overall_trigger"
+t "std_logic"
+eolc "--! goes high to load trigger data"
+o 50
+suid 61,0
+)
+)
+uid 2131,0
+)
+*517 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "overall_veto"
+t "std_logic"
+eolc "--! Halts triggers when high"
+o 51
+suid 62,0
+)
+)
+uid 2133,0
+)
+*518 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "triggers"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 63
+suid 68,0
+)
+)
+uid 2137,0
+)
+*519 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "trigger_count"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 61
+suid 77,0
+)
+)
+uid 2287,0
+)
+*520 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "data_strobe"
+t "std_logic"
+eolc "goes high when data ready to load into event buffer"
+o 35
+suid 82,0
+)
+)
+uid 2362,0
+)
+*521 (LeafLogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "leds_o"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 21
+suid 83,0
+)
+)
+uid 2814,0
+scheme 0
+)
+*522 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "trigger_times"
+t "t_triggerTimeArray"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 62
+suid 86,0
+)
+)
+uid 3333,0
+)
+*523 (LeafLogPort
+port (LogicalPort
+lang 2
+m 4
+decl (Decl
+n "event_data"
+t "std_logic_vector"
+b "(g_EVENT_DATA_WIDTH-1 DOWNTO 0)"
+o 40
+suid 93,0
+)
+)
+uid 3653,0
+)
+*524 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "--! either external clock in, or a clock being driven out"
+o 28
+suid 105,0
+)
+)
+uid 4683,0
+)
+*525 (LeafLogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 27
+suid 106,0
+)
+)
+uid 4685,0
+)
+*526 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "clk_logic_xtal"
+t "std_logic"
+eolc "! 40MHz clock from onboard xtal"
+o 34
+suid 107,0
+)
+)
+uid 4687,0
+)
+*527 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "strobe_4x_logic"
+t "std_logic"
+eolc "one pulse every 4 cycles of clk_4x"
+o 59
+suid 109,0
+)
+)
+uid 4705,0
+)
+*528 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "clk_16x_logic"
+t "std_logic"
+eolc "640MHz clock"
+o 32
+suid 110,0
+)
+)
+uid 4707,0
+)
+*529 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "strobe_16x_logic"
+t "std_logic"
+eolc "--! Pulses one cycle every 4 of 16x clock."
+o 58
+suid 111,0
+)
+)
+uid 4709,0
+)
+*530 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "veto_o"
+t "std_logic"
+eolc "goes high when one or more DUT are busy"
+o 64
+suid 116,0
+)
+)
+uid 4994,0
+)
+*531 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "buffer_full_o"
+t "std_logic"
+eolc "--! Goes high when event buffer almost full"
+o 31
+suid 117,0
+)
+)
+uid 4996,0
+)
+*532 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 3
+suid 120,0
+)
+)
+uid 6012,0
+)
+*533 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 121,0
+)
+)
+uid 6014,0
+)
+*534 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+o 13
+suid 129,0
+)
+)
+uid 6680,0
+)
+*535 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 130,0
+)
+)
+uid 6682,0
+)
+*536 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 131,0
+)
+)
+uid 6685,0
+)
+*537 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 132,0
+)
+)
+uid 6687,0
+)
+*538 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 133,0
+)
+)
+uid 6689,0
+)
+*539 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 134,0
+)
+)
+uid 6691,0
+)
+*540 (LeafLogPort
+port (LogicalPort
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 135,0
+)
+)
+uid 6693,0
+)
+*541 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 136,0
+)
+)
+uid 6695,0
+)
+*542 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 137,0
+)
+)
+uid 6697,0
+)
+*543 (LeafLogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 138,0
+)
+)
+uid 6699,0
+)
+*544 (LeafLogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 139,0
+)
+)
+uid 6701,0
+)
+*545 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "ipbus_rst"
+t "std_logic"
+eolc "! IPBus reset to slaves"
+o 46
+suid 140,0
+)
+)
+uid 7101,0
+)
+*546 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "event_number_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 41
+suid 146,0
+)
+)
+uid 9407,0
+)
+*547 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "logic_reset"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 49
+suid 148,0
+)
+)
+uid 9409,0
+)
+*548 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_i2c_scl_enb"
+t "std_logic"
+o 52
+suid 153,0
+)
+)
+uid 10124,0
+)
+*549 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "s_i2c_sda_enb"
+t "std_logic"
+o 53
+suid 157,0
+)
+)
+uid 10126,0
+)
+*550 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+o 44
+suid 158,0
+)
+)
+uid 10540,0
+)
+*551 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_fall_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 36
+suid 161,0
+)
+)
+uid 10634,0
+)
+*552 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_fall_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 37
+suid 162,0
+)
+)
+uid 10636,0
+)
+*553 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_rise_i"
+t "std_logic_vector"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+posAdd 0
+o 38
+suid 163,0
+)
+)
+uid 10638,0
+)
+*554 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "edge_rise_time_i"
+t "t_triggerTimeArray"
+b "(g_NUM_EDGE_INPUTS-1 DOWNTO 0)"
+eolc "-- Array of edge times ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 39
+suid 164,0
+)
+)
+uid 10640,0
+)
+*555 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "shutter_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 54
+suid 165,0
+)
+)
+uid 10642,0
+)
+*556 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "shutter_i"
+t "std_logic"
+o 55
+suid 166,0
+)
+)
+uid 10644,0
+)
+*557 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "spill_cnt_i"
+t "std_logic_vector"
+b "(g_SPILL_COUNTER_WIDTH-1 DOWNTO 0)"
+o 56
+suid 167,0
+)
+)
+uid 10646,0
+)
+*558 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "spill_i"
+t "std_logic"
+o 57
+suid 168,0
+)
+)
+uid 10648,0
+)
+*559 (LeafLogPort
+port (LogicalPort
+lang 11
+m 4
+decl (Decl
+n "trigger_cnt_i"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 DOWNTO 0)"
+o 60
+suid 169,0
+)
+)
+uid 10650,0
+)
+*560 (LeafLogPort
+port (LogicalPort
+m 4
+decl (Decl
+n "logic_clocks_reset"
+t "std_logic"
+eolc "Goes high to reset counters etc. Sync with clk_4x_logic"
+o 48
+suid 171,0
+)
+)
+uid 11204,0
+)
+*561 (LeafLogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 20
+suid 172,0
+)
+)
+uid 11457,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
+uid 371,0
+optionalChildren [
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+sheetRow (SheetRow
+headerVa (MVa
+cellColor "49152,49152,49152"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+cellVa (MVa
+cellColor "65535,65535,65535"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+groupVa (MVa
+cellColor "39936,56832,65280"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *563 (MRCItem
+litem &485
+pos 64
+dimension 20
+)
+uid 373,0
+optionalChildren [
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+litem &486
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+)
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+litem &487
+pos 1
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+uid 375,0
+)
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+litem &488
+pos 2
+hidden 1
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+)
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+litem &498
+pos 0
+dimension 20
+uid 280,0
+)
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+litem &499
+pos 1
+dimension 20
+uid 282,0
+)
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+litem &500
+pos 2
+dimension 20
+uid 284,0
+)
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+litem &501
+pos 3
+dimension 20
+uid 286,0
+)
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+litem &502
+pos 4
+dimension 20
+uid 288,0
+)
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+litem &503
+pos 5
+dimension 20
+uid 290,0
+)
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+litem &504
+pos 6
+dimension 20
+uid 292,0
+)
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+litem &505
+pos 7
+dimension 20
+uid 294,0
+)
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+litem &506
+pos 8
+dimension 20
+uid 296,0
+)
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+litem &507
+pos 17
+dimension 20
+uid 306,0
+)
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+litem &508
+pos 19
+dimension 20
+uid 308,0
+)
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+litem &509
+pos 21
+dimension 20
+uid 310,0
+)
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+litem &510
+pos 22
+dimension 20
+uid 312,0
+)
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+litem &511
+pos 30
+dimension 20
+uid 1224,0
+)
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+litem &512
+pos 31
+dimension 20
+uid 2120,0
+)
+*582 (MRCItem
+litem &513
+pos 32
+dimension 20
+uid 2122,0
+)
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+litem &514
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+dimension 20
+uid 2124,0
+)
+*584 (MRCItem
+litem &515
+pos 34
+dimension 20
+uid 2126,0
+)
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+litem &516
+pos 35
+dimension 20
+uid 2132,0
+)
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+litem &517
+pos 36
+dimension 20
+uid 2134,0
+)
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+litem &518
+pos 37
+dimension 20
+uid 2138,0
+)
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+litem &519
+pos 38
+dimension 20
+uid 2288,0
+)
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+litem &520
+pos 39
+dimension 20
+uid 2363,0
+)
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+litem &521
+pos 23
+dimension 20
+uid 2815,0
+)
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+litem &522
+pos 40
+dimension 20
+uid 3334,0
+)
+*592 (MRCItem
+litem &523
+pos 41
+dimension 20
+uid 3654,0
+)
+*593 (MRCItem
+litem &524
+pos 24
+dimension 20
+uid 4684,0
+)
+*594 (MRCItem
+litem &525
+pos 25
+dimension 20
+uid 4686,0
+)
+*595 (MRCItem
+litem &526
+pos 42
+dimension 20
+uid 4688,0
+)
+*596 (MRCItem
+litem &527
+pos 43
+dimension 20
+uid 4706,0
+)
+*597 (MRCItem
+litem &528
+pos 44
+dimension 20
+uid 4708,0
+)
+*598 (MRCItem
+litem &529
+pos 45
+dimension 20
+uid 4710,0
+)
+*599 (MRCItem
+litem &530
+pos 46
+dimension 20
+uid 4995,0
+)
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+)
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+dimension 20
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+)
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+dimension 20
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+)
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+dimension 20
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+)
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+)
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+)
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+)
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+)
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+dimension 20
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+)
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+dimension 20
+uid 6692,0
+)
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+pos 12
+dimension 20
+uid 6694,0
+)
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+pos 14
+dimension 20
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+)
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+)
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+pos 16
+dimension 20
+uid 6700,0
+)
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+pos 48
+dimension 20
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+)
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+dimension 20
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+)
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+dimension 20
+uid 9410,0
+)
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+dimension 20
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+)
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+litem &549
+pos 52
+dimension 20
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+)
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+litem &550
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+dimension 20
+uid 10541,0
+)
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+litem &551
+pos 54
+dimension 20
+uid 10635,0
+)
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+)
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+)
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+)
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+dimension 20
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+)
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+)
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+dimension 20
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+)
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+dimension 20
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+)
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+dimension 20
+uid 10651,0
+)
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+litem &560
+pos 63
+dimension 20
+uid 11205,0
+)
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+litem &561
+pos 29
+dimension 20
+uid 11456,0
+)
+]
+)
+sheetCol (SheetCol
+propVa (MVa
+cellColor "0,49152,49152"
+fontColor "0,0,0"
+font "courier,10,0"
+textAngle 90
+)
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+*631 (MRCItem
+litem &489
+pos 0
+dimension 20
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+)
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+)
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+)
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+)
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+)
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+litem &497
+pos 7
+dimension 711
+uid 385,0
+)
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+)
+fixedCol 4
+fixedRow 2
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+]
+)
+]
+)
+uid 357,0
+)
+genericsCommonDM (CommonDM
+ldm (LogicalDM
+emptyRow *639 (LEmptyRow
+)
+uid 387,0
+optionalChildren [
+*640 (RefLabelRowHdr
+)
+*641 (TitleRowHdr
+)
+*642 (FilterRowHdr
+)
+*643 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*644 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*645 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*646 (NameColHdr
+tm "GenericNameColHdrMgr"
+)
+*647 (TypeColHdr
+tm "GenericTypeColHdrMgr"
+)
+*648 (InitColHdr
+tm "GenericValueColHdrMgr"
+)
+*649 (PragmaColHdr
+tm "GenericPragmaColHdrMgr"
+)
+*650 (EolColHdr
+tm "GenericEolColHdrMgr"
+)
+*651 (LogGeneric
+generic (GiElement
+name "g_NUM_DUTS"
+type "positive"
+value "3"
+)
+uid 738,0
+)
+*652 (LogGeneric
+generic (GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "4"
+)
+uid 740,0
+)
+*653 (LogGeneric
+generic (GiElement
+name "g_NUM_EXT_SLAVES"
+type "positive"
+value "10"
+e "! Number of slaves outside IPBus interface"
+)
+uid 2456,0
+)
+*654 (LogGeneric
+generic (GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "64"
+)
+uid 2458,0
+)
+*655 (LogGeneric
+generic (GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+uid 2460,0
+)
+*656 (LogGeneric
+generic (GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "4"
+)
+uid 10652,0
+)
+*657 (LogGeneric
+generic (GiElement
+name "g_SPILL_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+uid 10832,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
+uid 399,0
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+sheetRow (SheetRow
+headerVa (MVa
+cellColor "49152,49152,49152"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+cellVa (MVa
+cellColor "65535,65535,65535"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+groupVa (MVa
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+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *659 (MRCItem
+litem &639
+pos 7
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+)
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+)
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+)
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+hidden 1
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+dimension 20
+uid 10831,0
+)
+]
+)
+sheetCol (SheetCol
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+font "courier,10,0"
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+)
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+)
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+)
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+pos 2
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+)
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+pos 3
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+)
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+litem &648
+pos 4
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+)
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+litem &649
+pos 5
+dimension 50
+uid 411,0
+)
+*676 (MRCItem
+litem &650
+pos 6
+dimension 602
+uid 412,0
+)
+]
+)
+fixedCol 3
+fixedRow 2
+name "Ports"
+uid 400,0
+vaOverrides [
+]
+)
+]
+)
+uid 386,0
+type 1
+)
+activeModelName "BlockDiag:CDM"
+)
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.ctr b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.ctr
new file mode 100644
index 0000000000000000000000000000000000000000..76b1ead4d9fffc3f438bfb9fd0b2bc1746f9bb41
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.ctr
@@ -0,0 +1,5 @@
+# set_vendor xilinx
+# set_family spartan6
+# set_device 6slx16
+# set_package csg324
+# set_speed -3
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.sdc b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..76b1ead4d9fffc3f438bfb9fd0b2bc1746f9bb41
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.info/Synthesis/Constraints/top_extphy.sdc
@@ -0,0 +1,5 @@
+# set_vendor xilinx
+# set_family spartan6
+# set_device 6slx16
+# set_package csg324
+# set_speed -3
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..93dda4d240ce49348082b1e7d7b693df4b036d9c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
@@ -0,0 +1,3403 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+]
+libraryRefs [
+"ieee"
+]
+)
+version "25.1"
+appVersion "2012.2b (Build 5)"
+model (Symbol
+commonDM (CommonDM
+ldm (LogicalDM
+suid 36,0
+usingSuid 1
+emptyRow *1 (LEmptyRow
+)
+uid 53,0
+optionalChildren [
+*2 (RefLabelRowHdr
+)
+*3 (TitleRowHdr
+)
+*4 (FilterRowHdr
+)
+*5 (RefLabelColHdr
+tm "RefLabelColHdrMgr"
+)
+*6 (RowExpandColHdr
+tm "RowExpandColHdrMgr"
+)
+*7 (GroupColHdr
+tm "GroupColHdrMgr"
+)
+*8 (NameColHdr
+tm "NameColHdrMgr"
+)
+*9 (ModeColHdr
+tm "ModeColHdrMgr"
+)
+*10 (TypeColHdr
+tm "TypeColHdrMgr"
+)
+*11 (BoundsColHdr
+tm "BoundsColHdrMgr"
+)
+*12 (InitColHdr
+tm "InitColHdrMgr"
+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
+*14 (LogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_p_i"
+t "std_logic"
+o 13
+suid 1,0
+)
+)
+uid 109,0
+)
+*15 (LogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "leds_o"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 21
+suid 2,0
+)
+)
+uid 111,0
+)
+*16 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 16
+suid 3,0
+)
+)
+uid 113,0
+)
+*17 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 17
+suid 4,0
+)
+)
+uid 115,0
+)
+*18 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 18
+suid 5,0
+)
+)
+uid 117,0
+)
+*19 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_clk_i"
+t "std_logic"
+o 8
+suid 6,0
+)
+)
+uid 119,0
+)
+*20 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 9
+suid 7,0
+)
+)
+uid 121,0
+)
+*21 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 10
+suid 8,0
+)
+)
+uid 123,0
+)
+*22 (LogPort
+port (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 11
+suid 9,0
+)
+)
+uid 125,0
+)
+*23 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 22
+suid 10,0
+)
+)
+uid 127,0
+)
+*24 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 19
+suid 11,0
+)
+)
+uid 129,0
+)
+*25 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 12,0
+)
+)
+uid 131,0
+)
+*26 (LogPort
+port (LogicalPort
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 13,0
+)
+)
+uid 133,0
+)
+*27 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 14,0
+)
+)
+uid 135,0
+)
+*28 (LogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 15,0
+)
+)
+uid 137,0
+)
+*29 (LogPort
+port (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 20,0
+)
+)
+uid 337,0
+)
+*30 (LogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "--! either external clock in, or a clock being driven out"
+o 28
+suid 23,0
+)
+)
+uid 942,0
+)
+*31 (LogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 27
+suid 24,0
+)
+)
+uid 944,0
+)
+*32 (LogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 15
+suid 25,0
+)
+)
+uid 1265,0
+)
+*33 (LogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 4
+suid 26,0
+)
+)
+uid 1267,0
+)
+*34 (LogPort
+port (LogicalPort
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 3
+suid 27,0
+)
+)
+uid 1269,0
+)
+*35 (LogPort
+port (LogicalPort
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 28,0
+)
+)
+uid 1271,0
+)
+*36 (LogPort
+port (LogicalPort
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 29,0
+)
+)
+uid 1775,0
+)
+*37 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 30,0
+)
+)
+uid 1777,0
+)
+*38 (LogPort
+port (LogicalPort
+m 1
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 31,0
+)
+)
+uid 1779,0
+)
+*39 (LogPort
+port (LogicalPort
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 32,0
+)
+)
+uid 1781,0
+)
+*40 (LogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_sda_b"
+t "std_logic"
+o 30
+suid 33,0
+)
+)
+uid 1804,0
+)
+*41 (LogPort
+port (LogicalPort
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 34,0
+)
+)
+uid 1811,0
+)
+*42 (LogPort
+port (LogicalPort
+m 2
+decl (Decl
+n "i2c_scl_b"
+t "std_logic"
+o 29
+suid 35,0
+)
+)
+uid 1841,0
+)
+*43 (LogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 20
+suid 36,0
+)
+)
+uid 1989,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
+editShortBounds 1
+uid 66,0
+optionalChildren [
+*44 (Sheet
+sheetRow (SheetRow
+headerVa (MVa
+cellColor "49152,49152,49152"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+cellVa (MVa
+cellColor "65535,65535,65535"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+groupVa (MVa
+cellColor "39936,56832,65280"
+fontColor "0,0,0"
+font "courier,10,0"
+)
+emptyMRCItem *45 (MRCItem
+litem &1
+pos 30
+dimension 20
+)
+uid 68,0
+optionalChildren [
+*46 (MRCItem
+litem &2
+pos 0
+dimension 20
+uid 69,0
+)
+*47 (MRCItem
+litem &3
+pos 1
+dimension 23
+uid 70,0
+)
+*48 (MRCItem
+litem &4
+pos 2
+hidden 1
+dimension 20
+uid 71,0
+)
+*49 (MRCItem
+litem &14
+pos 26
+dimension 20
+uid 108,0
+)
+*50 (MRCItem
+litem &15
+pos 23
+dimension 20
+uid 110,0
+)
+*51 (MRCItem
+litem &16
+pos 0
+dimension 20
+uid 112,0
+)
+*52 (MRCItem
+litem &17
+pos 1
+dimension 20
+uid 114,0
+)
+*53 (MRCItem
+litem &18
+pos 2
+dimension 20
+uid 116,0
+)
+*54 (MRCItem
+litem &19
+pos 3
+dimension 20
+uid 118,0
+)
+*55 (MRCItem
+litem &20
+pos 4
+dimension 20
+uid 120,0
+)
+*56 (MRCItem
+litem &21
+pos 5
+dimension 20
+uid 122,0
+)
+*57 (MRCItem
+litem &22
+pos 6
+dimension 20
+uid 124,0
+)
+*58 (MRCItem
+litem &23
+pos 7
+dimension 20
+uid 126,0
+)
+*59 (MRCItem
+litem &24
+pos 8
+dimension 20
+uid 128,0
+)
+*60 (MRCItem
+litem &25
+pos 9
+dimension 20
+uid 130,0
+)
+*61 (MRCItem
+litem &26
+pos 11
+dimension 20
+uid 132,0
+)
+*62 (MRCItem
+litem &27
+pos 13
+dimension 20
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+)
+)
+dt (MLText
+uid 190,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,10800,74500,11700"
+st "gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 11
+suid 9,0
+)
+)
+)
+*135 (CptPort
+uid 191,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 192,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,46625,70750,47375"
+)
+tg (CPTG
+uid 193,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 194,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,46550,69000,47450"
+st "phy_rstb_o"
+ju 2
+blo "69000,47250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 195,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,20700,65000,21600"
+st "phy_rstb_o : OUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 22
+suid 10,0
+)
+)
+)
+*136 (CptPort
+uid 196,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 197,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,48625,70750,49375"
+)
+tg (CPTG
+uid 198,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 199,0
+va (VaSet
+font "courier,8,0"
+)
+xt "59500,48550,69000,49450"
+st "gmii_txd_o : (7:0)"
+ju 2
+blo "69000,49250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 200,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,18000,74500,18900"
+st "gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 19
+suid 11,0
+)
+)
+)
+*137 (CptPort
+uid 201,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 202,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,50625,70750,51375"
+)
+tg (CPTG
+uid 203,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 204,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53000,50550,69000,51450"
+st "triggers_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,51250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 205,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,24300,92500,25200"
+st "triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! Trigger lines to DUT
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Trigger lines to DUT"
+o 26
+suid 12,0
+)
+)
+)
+*138 (CptPort
+uid 206,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 207,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,46625,13000,47375"
+)
+tg (CPTG
+uid 208,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 209,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,46550,28000,47450"
+st "busy_p_i : (g_NUM_DUTS-1:0)"
+blo "14000,47250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 210,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,2700,100500,3600"
+st "busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ; --! Busy lines from DUTs ( active high )
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+eolc "--! Busy lines from DUTs ( active high )"
+o 2
+suid 13,0
+)
+)
+)
+*139 (CptPort
+uid 211,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 212,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,53625,70750,54375"
+)
+tg (CPTG
+uid 213,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 214,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,53550,69000,54450"
+st "reset_or_clk_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,54250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 215,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,22500,80000,23400"
+st "reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 14,0
+)
+)
+)
+*140 (CptPort
+uid 216,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 217,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,48625,13000,49375"
+)
+tg (CPTG
+uid 218,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 219,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,48550,29500,49450"
+st "dut_clk_p_i : (g_NUM_DUTS-1:0)"
+blo "14000,49250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 220,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,7200,80000,8100"
+st "dut_clk_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 15,0
+)
+)
+)
+*141 (CptPort
+uid 339,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 340,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,53625,13000,54375"
+)
+tg (CPTG
+uid 341,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 342,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,53550,19500,54450"
+st "sysclk_n_i"
+blo "14000,54250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 343,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,11700,76500,12600"
+st "sysclk_n_i : IN std_logic ; --! 200 MHz xtal clock
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "--! 200 MHz xtal clock"
+o 12
+suid 20,0
+)
+)
+)
+*142 (CptPort
+uid 945,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 946,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,61625,70750,62375"
+)
+tg (CPTG
+uid 947,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 948,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,61550,69000,62450"
+st "extclk_p_b"
+ju 2
+blo "69000,62250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 949,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,26100,94000,27000"
+st "extclk_p_b : INOUT std_logic ; --! either external clock in, or a clock being driven out
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "--! either external clock in, or a clock being driven out"
+o 28
+suid 23,0
+)
+)
+)
+*143 (CptPort
+uid 950,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 951,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,63625,70750,64375"
+)
+tg (CPTG
+uid 952,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 953,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,63550,69000,64450"
+st "extclk_n_b"
+ju 2
+blo "69000,64250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 954,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,25200,65000,26100"
+st "extclk_n_b : INOUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 27
+suid 24,0
+)
+)
+)
+*144 (CptPort
+uid 1272,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1273,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,57625,13000,58375"
+)
+tg (CPTG
+uid 1274,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1275,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,57550,37000,58450"
+st "threshold_discr_p_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,58250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1276,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,14400,83500,15300"
+st "threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 15
+suid 25,0
+)
+)
+)
+*145 (CptPort
+uid 1277,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1278,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,59625,13000,60375"
+)
+tg (CPTG
+uid 1279,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1280,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,59550,34000,60450"
+st "cfd_discr_p_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,60250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1281,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,4500,83500,5400"
+st "cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 4
+suid 26,0
+)
+)
+)
+*146 (CptPort
+uid 1282,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1283,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,61625,13000,62375"
+)
+tg (CPTG
+uid 1284,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1285,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,61550,34000,62450"
+st "cfd_discr_n_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,62250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1286,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,3600,83500,4500"
+st "cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 3
+suid 27,0
+)
+)
+)
+*147 (CptPort
+uid 1287,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1288,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,63625,13000,64375"
+)
+tg (CPTG
+uid 1289,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1290,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,63550,37000,64450"
+st "threshold_discr_n_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,64250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1291,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,13500,83500,14400"
+st "threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 28,0
+)
+)
+)
+*148 (CptPort
+uid 1783,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1784,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,64625,13000,65375"
+)
+tg (CPTG
+uid 1785,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1786,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,64550,28000,65450"
+st "busy_n_i : (g_NUM_DUTS-1:0)"
+blo "14000,65250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1787,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,1800,80000,2700"
+st "busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 29,0
+)
+)
+)
+*149 (CptPort
+uid 1788,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1789,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,64625,70750,65375"
+)
+tg (CPTG
+uid 1790,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1791,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,64550,69000,65450"
+st "reset_or_clk_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,65250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1792,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,21600,80000,22500"
+st "reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 30,0
+)
+)
+)
+*150 (CptPort
+uid 1793,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1794,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,65625,70750,66375"
+)
+tg (CPTG
+uid 1795,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1796,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53000,65550,69000,66450"
+st "triggers_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,66250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1797,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,23400,80000,24300"
+st "triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 31,0
+)
+)
+)
+*151 (CptPort
+uid 1798,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1799,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,65625,13000,66375"
+)
+tg (CPTG
+uid 1800,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1801,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,65550,29500,66450"
+st "dut_clk_n_i : (g_NUM_DUTS-1:0)"
+blo "14000,66250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1802,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,6300,80000,7200"
+st "dut_clk_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 32,0
+)
+)
+)
+*152 (CptPort
+uid 1805,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 1806,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,66625,70750,67375"
+)
+tg (CPTG
+uid 1807,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1808,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64500,66550,69000,67450"
+st "i2c_sda_b"
+ju 2
+blo "69000,67250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1809,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,27900,64000,28800"
+st "i2c_sda_b : INOUT std_logic
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "i2c_sda_b"
+t "std_logic"
+o 30
+suid 33,0
+)
+)
+)
+*153 (CptPort
+uid 1812,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1813,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,66625,13000,67375"
+)
+tg (CPTG
+uid 1814,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1815,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,66550,24500,67450"
+st "dip_switch_i : (3:0)"
+blo "14000,67250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1816,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,5400,74500,6300"
+st "dip_switch_i : IN std_logic_vector (3 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 34,0
+)
+)
+)
+*154 (CptPort
+uid 1842,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 1843,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,67625,70750,68375"
+)
+tg (CPTG
+uid 1844,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1845,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64500,67550,69000,68450"
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb.bak b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb.bak
new file mode 100644
index 0000000000000000000000000000000000000000..9ddd3a6735c183a8021a1b9d0aeae3a77fc2a323
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb.bak
@@ -0,0 +1,3383 @@
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+)
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+)
+xt "44000,19800,74500,20700"
+st "leds_o : OUT std_logic_vector (3 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "leds_o"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 20
+suid 2,0
+)
+)
+)
+*128 (CptPort
+uid 156,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 157,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,40625,70750,41375"
+)
+tg (CPTG
+uid 158,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 159,0
+va (VaSet
+font "courier,8,0"
+)
+xt "61500,40550,69000,41450"
+st "gmii_gtx_clk_o"
+ju 2
+blo "69000,41250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 160,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,15300,65000,16200"
+st "gmii_gtx_clk_o : OUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_gtx_clk_o"
+t "std_logic"
+o 16
+suid 3,0
+)
+)
+)
+*129 (CptPort
+uid 161,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 162,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,42625,70750,43375"
+)
+tg (CPTG
+uid 163,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 164,0
+va (VaSet
+font "courier,8,0"
+)
+xt "62500,42550,69000,43450"
+st "gmii_tx_en_o"
+ju 2
+blo "69000,43250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 165,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,16200,65000,17100"
+st "gmii_tx_en_o : OUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_en_o"
+t "std_logic"
+o 17
+suid 4,0
+)
+)
+)
+*130 (CptPort
+uid 166,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 167,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,44625,70750,45375"
+)
+tg (CPTG
+uid 168,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 169,0
+va (VaSet
+font "courier,8,0"
+)
+xt "62500,44550,69000,45450"
+st "gmii_tx_er_o"
+ju 2
+blo "69000,45250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 170,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,17100,65000,18000"
+st "gmii_tx_er_o : OUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_tx_er_o"
+t "std_logic"
+o 18
+suid 5,0
+)
+)
+)
+*131 (CptPort
+uid 171,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 172,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,38625,13000,39375"
+)
+tg (CPTG
+uid 173,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 174,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,38550,21000,39450"
+st "gmii_rx_clk_i"
+blo "14000,39250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 175,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,8100,65000,9000"
+st "gmii_rx_clk_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_clk_i"
+t "std_logic"
+o 8
+suid 6,0
+)
+)
+)
+*132 (CptPort
+uid 176,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 177,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,40625,13000,41375"
+)
+tg (CPTG
+uid 178,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 179,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,40550,20500,41450"
+st "gmii_rx_dv_i"
+blo "14000,41250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 180,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9000,65000,9900"
+st "gmii_rx_dv_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_dv_i"
+t "std_logic"
+o 9
+suid 7,0
+)
+)
+)
+*133 (CptPort
+uid 181,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 182,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,42625,13000,43375"
+)
+tg (CPTG
+uid 183,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 184,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,42550,20500,43450"
+st "gmii_rx_er_i"
+blo "14000,43250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 185,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9900,65000,10800"
+st "gmii_rx_er_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rx_er_i"
+t "std_logic"
+o 10
+suid 8,0
+)
+)
+)
+*134 (CptPort
+uid 186,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 187,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,44625,13000,45375"
+)
+tg (CPTG
+uid 188,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 189,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,44550,23500,45450"
+st "gmii_rxd_i : (7:0)"
+blo "14000,45250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 190,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,10800,74500,11700"
+st "gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "gmii_rxd_i"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 11
+suid 9,0
+)
+)
+)
+*135 (CptPort
+uid 191,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 192,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,46625,70750,47375"
+)
+tg (CPTG
+uid 193,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 194,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,46550,69000,47450"
+st "phy_rstb_o"
+ju 2
+blo "69000,47250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 195,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,20700,65000,21600"
+st "phy_rstb_o : OUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "phy_rstb_o"
+t "std_logic"
+o 21
+suid 10,0
+)
+)
+)
+*136 (CptPort
+uid 196,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 197,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,48625,70750,49375"
+)
+tg (CPTG
+uid 198,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 199,0
+va (VaSet
+font "courier,8,0"
+)
+xt "59500,48550,69000,49450"
+st "gmii_txd_o : (7:0)"
+ju 2
+blo "69000,49250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 200,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,18000,74500,18900"
+st "gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "gmii_txd_o"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 19
+suid 11,0
+)
+)
+)
+*137 (CptPort
+uid 201,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 202,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,50625,70750,51375"
+)
+tg (CPTG
+uid 203,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 204,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53000,50550,69000,51450"
+st "triggers_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,51250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 205,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,24300,80000,25200"
+st "triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "triggers_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 25
+suid 12,0
+)
+)
+)
+*138 (CptPort
+uid 206,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 207,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,46625,13000,47375"
+)
+tg (CPTG
+uid 208,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 209,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,46550,28000,47450"
+st "busy_p_i : (g_NUM_DUTS-1:0)"
+blo "14000,47250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 210,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,2700,80000,3600"
+st "busy_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 2
+suid 13,0
+)
+)
+)
+*139 (CptPort
+uid 211,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 212,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,53625,70750,54375"
+)
+tg (CPTG
+uid 213,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 214,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,53550,69000,54450"
+st "reset_or_clk_p_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,54250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 215,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,22500,80000,23400"
+st "reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_p_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 23
+suid 14,0
+)
+)
+)
+*140 (CptPort
+uid 216,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 217,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,48625,13000,49375"
+)
+tg (CPTG
+uid 218,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 219,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,48550,29500,49450"
+st "dut_clk_p_i : (g_NUM_DUTS-1:0)"
+blo "14000,49250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 220,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,7200,80000,8100"
+st "dut_clk_p_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "dut_clk_p_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 7
+suid 15,0
+)
+)
+)
+*141 (CptPort
+uid 339,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 340,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,53625,13000,54375"
+)
+tg (CPTG
+uid 341,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 342,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,53550,19500,54450"
+st "sysclk_n_i"
+blo "14000,54250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 343,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,11700,77000,12600"
+st "sysclk_n_i : IN std_logic ; -- ! 200 MHz xtal clock
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "sysclk_n_i"
+t "std_logic"
+eolc "! 200 MHz xtal clock"
+o 12
+suid 20,0
+)
+)
+)
+*142 (CptPort
+uid 945,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 946,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,61625,70750,62375"
+)
+tg (CPTG
+uid 947,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 948,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,61550,69000,62450"
+st "extclk_p_b"
+ju 2
+blo "69000,62250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 949,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,26100,93500,27000"
+st "extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "extclk_p_b"
+t "std_logic"
+eolc "either external clock in, or a clock being driven out"
+o 27
+suid 23,0
+)
+)
+)
+*143 (CptPort
+uid 950,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 951,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,63625,70750,64375"
+)
+tg (CPTG
+uid 952,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 953,0
+va (VaSet
+font "courier,8,0"
+)
+xt "63500,63550,69000,64450"
+st "extclk_n_b"
+ju 2
+blo "69000,64250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 954,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,25200,65000,26100"
+st "extclk_n_b : INOUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "extclk_n_b"
+t "std_logic"
+o 26
+suid 24,0
+)
+)
+)
+*144 (CptPort
+uid 1272,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1273,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,57625,13000,58375"
+)
+tg (CPTG
+uid 1274,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1275,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,57550,37000,58450"
+st "threshold_discr_p_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,58250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1276,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,14400,83500,15300"
+st "threshold_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 15
+suid 25,0
+)
+)
+)
+*145 (CptPort
+uid 1277,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1278,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,59625,13000,60375"
+)
+tg (CPTG
+uid 1279,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1280,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,59550,34000,60450"
+st "cfd_discr_p_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,60250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1281,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,4500,83500,5400"
+st "cfd_discr_p_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 4
+suid 26,0
+)
+)
+)
+*146 (CptPort
+uid 1282,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1283,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,61625,13000,62375"
+)
+tg (CPTG
+uid 1284,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1285,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,61550,34000,62450"
+st "cfd_discr_n_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,62250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1286,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,3600,83500,4500"
+st "cfd_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 3
+suid 27,0
+)
+)
+)
+*147 (CptPort
+uid 1287,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1288,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,63625,13000,64375"
+)
+tg (CPTG
+uid 1289,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1290,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,63550,37000,64450"
+st "threshold_discr_n_i : (g_NUM_TRIG_INPUTS-1:0)"
+blo "14000,64250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1291,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,13500,83500,14400"
+st "threshold_discr_n_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_TRIG_INPUTS-1 DOWNTO 0)"
+o 14
+suid 28,0
+)
+)
+)
+*148 (CptPort
+uid 1783,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1784,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,64625,13000,65375"
+)
+tg (CPTG
+uid 1785,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1786,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,64550,28000,65450"
+st "busy_n_i : (g_NUM_DUTS-1:0)"
+blo "14000,65250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1787,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,1800,80000,2700"
+st "busy_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "busy_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 1
+suid 29,0
+)
+)
+)
+*149 (CptPort
+uid 1788,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1789,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,64625,70750,65375"
+)
+tg (CPTG
+uid 1790,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1791,0
+va (VaSet
+font "courier,8,0"
+)
+xt "51000,64550,69000,65450"
+st "reset_or_clk_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,65250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1792,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,21600,80000,22500"
+st "reset_or_clk_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "reset_or_clk_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 22
+suid 30,0
+)
+)
+)
+*150 (CptPort
+uid 1793,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1794,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,65625,70750,66375"
+)
+tg (CPTG
+uid 1795,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1796,0
+va (VaSet
+font "courier,8,0"
+)
+xt "53000,65550,69000,66450"
+st "triggers_n_o : (g_NUM_DUTS-1:0)"
+ju 2
+blo "69000,66250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1797,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,23400,80000,24300"
+st "triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "triggers_n_o"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 24
+suid 31,0
+)
+)
+)
+*151 (CptPort
+uid 1798,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1799,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,65625,13000,66375"
+)
+tg (CPTG
+uid 1800,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1801,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,65550,29500,66450"
+st "dut_clk_n_i : (g_NUM_DUTS-1:0)"
+blo "14000,66250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1802,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,6300,80000,7200"
+st "dut_clk_n_i : IN std_logic_vector (g_NUM_DUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "dut_clk_n_i"
+t "std_logic_vector"
+b "(g_NUM_DUTS-1 DOWNTO 0)"
+o 6
+suid 32,0
+)
+)
+)
+*152 (CptPort
+uid 1805,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 1806,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,66625,70750,67375"
+)
+tg (CPTG
+uid 1807,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1808,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64500,66550,69000,67450"
+st "i2c_sda_b"
+ju 2
+blo "69000,67250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1809,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,27900,64000,28800"
+st "i2c_sda_b : INOUT std_logic
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "i2c_sda_b"
+t "std_logic"
+o 29
+suid 33,0
+)
+)
+)
+*153 (CptPort
+uid 1812,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1813,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "12250,66625,13000,67375"
+)
+tg (CPTG
+uid 1814,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 1815,0
+va (VaSet
+font "courier,8,0"
+)
+xt "14000,66550,24500,67450"
+st "dip_switch_i : (3:0)"
+blo "14000,67250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1816,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,5400,74500,6300"
+st "dip_switch_i : IN std_logic_vector (3 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "dip_switch_i"
+t "std_logic_vector"
+b "(3 DOWNTO 0)"
+o 5
+suid 34,0
+)
+)
+)
+*154 (CptPort
+uid 1842,0
+ps "OnEdgeStrategy"
+shape (Diamond
+uid 1843,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,67625,70750,68375"
+)
+tg (CPTG
+uid 1844,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1845,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64500,67550,69000,68450"
+st "i2c_scl_b"
+ju 2
+blo "69000,68250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 1846,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,27000,65000,27900"
+st "i2c_scl_b : INOUT std_logic ;
+"
+)
+thePort (LogicalPort
+m 2
+decl (Decl
+n "i2c_scl_b"
+t "std_logic"
+o 28
+suid 35,0
+)
+)
+)
+*155 (CptPort
+uid 1991,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 1992,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,68625,70750,69375"
+)
+tg (CPTG
+uid 1993,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 1994,0
+va (VaSet
+font "courier,8,0"
+)
+xt "60500,68550,69000,69450"
+st "gpio_hdr : (7:0)"
+ju 2
+blo "69000,69250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
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+va (VaSet
+font "courier,8,0"
+)
+xt "44000,18900,74500,19800"
+st "gpio_hdr : OUT std_logic_vector (7 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "gpio_hdr"
+t "std_logic_vector"
+b "(7 DOWNTO 0)"
+o 30
+suid 36,0
+)
+)
+)
+]
+shape (Rectangle
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+va (VaSet
+vasetType 1
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+lineWidth 2
+)
+xt "13000,38000,70000,70000"
+)
+oxt "15000,6000,39000,26000"
+biTextGroup (BiTextGroup
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+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (Text
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+)
+xt "32750,44100,34750,45000"
+st "work"
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+)
+second (Text
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+va (VaSet
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+)
+xt "32750,45000,38250,45900"
+st "top_extphy"
+blo "32750,45700"
+)
+)
+gi *156 (GenericInterface
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+ps "CenterOffsetStrategy"
+matrix (Matrix
+uid 14,0
+text (MLText
+uid 15,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,31700,60000,39800"
+st "Generic Declarations
+
+g_NUM_DUTS positive 3
+g_NUM_TRIG_INPUTS positive 4
+g_NUM_EXT_SLAVES positive 10 --! Number of slaves outside IPBus interface
+g_EVENT_DATA_WIDTH positive 64
+g_IPBUS_WIDTH positive 32
+g_NUM_EDGE_INPUTS positive 4
+g_SPILL_COUNTER_WIDTH positive 12 "
+)
+header "Generic Declarations"
+showHdrWhenContentsEmpty 1
+)
+elements [
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+name "g_NUM_DUTS"
+type "positive"
+value "3"
+)
+(GiElement
+name "g_NUM_TRIG_INPUTS"
+type "positive"
+value "4"
+)
+(GiElement
+name "g_NUM_EXT_SLAVES"
+type "positive"
+value "10"
+e "! Number of slaves outside IPBus interface"
+)
+(GiElement
+name "g_EVENT_DATA_WIDTH"
+type "positive"
+value "64"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+(GiElement
+name "g_NUM_EDGE_INPUTS"
+type "positive"
+value "4"
+)
+(GiElement
+name "g_SPILL_COUNTER_WIDTH"
+type "positive"
+value "12"
+)
+]
+)
+portInstanceVisAsIs 1
+portInstanceVis (PortSigDisplay
+sIVOD 1
+)
+portVis (PortSigDisplay
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+)
+)
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+)
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+"
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+)
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+"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+"
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+)
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+)
+]
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+)
+xt "68000,69000,109000,74000"
+)
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+)
+]
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+)
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+)
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+)
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+)
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+)
+]
+)
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+]
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+)
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+)
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+)
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+)
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+"
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+)
+)
+defaultRequirementText (RequirementText
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+)
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+)
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+)
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+"
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+)
+)
+defaultPanel (Panel
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+)
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+)
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+)
+)
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/transactor/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/transactor/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..7e740022db1be42e3b9f3ce65d7580847aaa7654
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/transactor/rtl.bd
@@ -0,0 +1,5654 @@
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+xt "58000,14550,60500,15450"
+st "reset"
+blo "58000,15250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "reset"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*26 (CptPort
+uid 167,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 168,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "56250,15625,57000,16375"
+)
+tg (CPTG
+uid 169,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 170,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,15550,62500,16450"
+st "pkt_ready"
+blo "58000,16250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "pkt_ready"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*27 (CptPort
+uid 171,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 172,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "56250,16625,57000,17375"
+)
+tg (CPTG
+uid 173,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 174,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,16550,64500,17450"
+st "pkt_addr_rst"
+blo "58000,17250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "pkt_addr_rst"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*28 (CptPort
+uid 175,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 176,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,13625,70750,14375"
+)
+tg (CPTG
+uid 177,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 178,0
+va (VaSet
+font "courier,8,0"
+)
+xt "64500,13550,69000,14450"
+st "pkt_raddr"
+ju 2
+blo "69000,14250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pkt_raddr"
+t "rbuf_a"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*29 (CptPort
+uid 179,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 180,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "56250,17625,57000,18375"
+)
+tg (CPTG
+uid 181,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 182,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,17550,62500,18450"
+st "pkt_rdata"
+blo "58000,18250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "pkt_rdata"
+t "std_logic_vector"
+b "(31 downto 0)"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*30 (CptPort
+uid 183,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 184,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,17625,70750,18375"
+)
+tg (CPTG
+uid 185,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 186,0
+va (VaSet
+font "courier,8,0"
+)
+xt "65000,17550,69000,18450"
+st "rx_ready"
+ju 2
+blo "69000,18250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rx_ready"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*31 (CptPort
+uid 187,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 188,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "56250,18625,57000,19375"
+)
+tg (CPTG
+uid 189,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 190,0
+va (VaSet
+font "courier,8,0"
+)
+xt "58000,18550,61500,19450"
+st "rx_next"
+blo "58000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rx_next"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*32 (CptPort
+uid 191,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 192,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "70000,18625,70750,19375"
+)
+tg (CPTG
+uid 193,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 194,0
+va (VaSet
+font "courier,8,0"
+)
+xt "66500,18550,69000,19450"
+st "start"
+ju 2
+blo "69000,19250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "start"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+*33 (PortMapFrame
+uid 195,0
+ps "PortMapFrameStrategy"
+shape (RectFrame
+uid 196,0
+va (VaSet
+vasetType 1
+fg "65535,65535,65535"
+lineColor "0,0,32768"
+lineWidth 2
+)
+xt "55000,11000,72000,22000"
+)
+portMapText (BiTextGroup
+uid 197,0
+ps "BottomRightOffsetStrategy"
+stg "VerticalLayoutStrategy"
+first (MLText
+uid 198,0
+va (VaSet
+font "courier,8,0"
+)
+xt "72000,22000,83000,26500"
+st "clk => clk,
+reset => reset,
+rx_next => rx_next,
+rx_ready => rx_ready,
+start => start,"
+)
+second (MLText
+uid 199,0
+va (VaSet
+font "courier,8,0"
+)
+xt "72000,26500,87500,30100"
+st "pkt_ready => moti.ready,
+pkt_addr_rst => moti.addr_rst,
+pkt_raddr => tomi.raddr,
+pkt_rdata => moti.rdata"
+tm "PortMapTextMgr"
+)
+)
+)
+]
+shape (Rectangle
+uid 150,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "57000,13000,70000,20000"
+)
+ttg (MlTextGroup
+uid 151,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*34 (Text
+uid 152,0
+va (VaSet
+font "courier,8,1"
+)
+xt "60000,20000,66500,20900"
+st "fmc_mTLU_lib"
+blo "60000,20700"
+tm "BdLibraryNameMgr"
+)
+*35 (Text
+uid 153,0
+va (VaSet
+font "courier,8,1"
+)
+xt "60000,20900,67000,21800"
+st "transactor_rx"
+blo "60000,21600"
+tm "CptNameMgr"
+)
+*36 (Text
+uid 154,0
+va (VaSet
+font "courier,8,1"
+)
+xt "60000,21800,61000,22700"
+st "rx"
+blo "60000,22500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 155,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 156,0
+text (MLText
+uid 157,0
+va (VaSet
+font "courier,8,0"
+)
+xt "56500,13000,56500,13000"
+)
+header ""
+)
+elements [
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 158,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "57250,18250,58750,19750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*37 (SaComponent
+uid 266,0
+optionalChildren [
+*38 (CptPort
+uid 276,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 277,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "28250,1625,29000,2375"
+)
+tg (CPTG
+uid 278,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 279,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,1550,31500,2450"
+st "clk"
+blo "30000,2250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*39 (CptPort
+uid 280,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 281,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "28250,625,29000,1375"
+)
+tg (CPTG
+uid 282,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 283,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,550,32500,1450"
+st "reset"
+blo "30000,1250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "reset"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*40 (CptPort
+uid 284,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 285,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "28250,-375,29000,375"
+)
+tg (CPTG
+uid 286,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 287,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,-450,33500,450"
+st "rx_data"
+blo "30000,250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rx_data"
+t "std_logic_vector"
+b "(31 downto 0)"
+eolc "-- input packet data"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*41 (CptPort
+uid 288,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 289,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "28250,3625,29000,4375"
+)
+tg (CPTG
+uid 290,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 291,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,3550,34000,4450"
+st "rx_ready"
+blo "30000,4250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "rx_ready"
+t "std_logic"
+eolc "-- asserted when valid input packet data is available"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*42 (CptPort
+uid 292,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 293,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "41000,625,41750,1375"
+)
+tg (CPTG
+uid 294,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 295,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,550,40000,1450"
+st "rx_next"
+ju 2
+blo "40000,1250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "rx_next"
+t "std_logic"
+eolc "-- new input packet data on next cycle when this is asserted"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*43 (CptPort
+uid 296,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 297,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "41000,3625,41750,4375"
+)
+tg (CPTG
+uid 298,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 299,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,3550,40000,4450"
+st "tx_func"
+ju 2
+blo "40000,4250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "tx_func"
+t "std_logic_vector"
+b "(3 downto 0)"
+eolc "-- encodes required transmit function (see transactor_tx)"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*44 (CptPort
+uid 300,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 301,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "41000,2625,41750,3375"
+)
+tg (CPTG
+uid 302,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 303,0
+va (VaSet
+font "courier,8,0"
+)
+xt "34500,2550,40000,3450"
+st "byte_order"
+ju 2
+blo "40000,3250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "byte_order"
+t "std_logic"
+eolc "-- controls byte ordering of input and output packet data"
+preAdd 0
+posAdd 0
+o 7
+)
+)
+)
+*45 (CptPort
+uid 304,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 305,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "41000,1625,41750,2375"
+)
+tg (CPTG
+uid 306,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 307,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36500,1550,40000,2450"
+st "ipb_out"
+ju 2
+blo "40000,2250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "ipb_out"
+t "ipb_wbus"
+preAdd 0
+posAdd 0
+o 8
+)
+)
+)
+*46 (CptPort
+uid 308,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 309,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "28250,2625,29000,3375"
+)
+tg (CPTG
+uid 310,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 311,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,2550,33000,3450"
+st "ipb_in"
+blo "30000,3250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "ipb_in"
+t "ipb_rbus"
+preAdd 0
+posAdd 0
+o 9
+)
+)
+)
+]
+shape (Rectangle
+uid 267,0
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "29000,-1000,41000,5000"
+)
+ttg (MlTextGroup
+uid 268,0
+ps "CenterOffsetStrategy"
+stg "VerticalLayoutStrategy"
+textVec [
+*47 (Text
+uid 269,0
+va (VaSet
+font "courier,8,1"
+)
+xt "31500,5000,38000,5900"
+st "fmc_mTLU_lib"
+blo "31500,5700"
+tm "BdLibraryNameMgr"
+)
+*48 (Text
+uid 270,0
+va (VaSet
+font "courier,8,1"
+)
+xt "31500,5900,38500,6800"
+st "transactor_sm"
+blo "31500,6600"
+tm "CptNameMgr"
+)
+*49 (Text
+uid 271,0
+va (VaSet
+font "courier,8,1"
+)
+xt "31500,6800,32500,7700"
+st "sm"
+blo "31500,7500"
+tm "InstanceNameMgr"
+)
+]
+)
+ga (GenericAssociation
+uid 272,0
+ps "EdgeToEdgeStrategy"
+matrix (Matrix
+uid 273,0
+text (MLText
+uid 274,0
+va (VaSet
+font "courier,8,0"
+)
+xt "28500,-1000,28500,-1000"
+)
+header ""
+)
+elements [
+]
+includeGenericsInHDL 0
+)
+viewicon (ZoomableIcon
+uid 275,0
+sl 0
+va (VaSet
+vasetType 1
+fg "49152,49152,49152"
+)
+xt "29250,3250,30750,4750"
+iconName "VhdlFileViewIcon.png"
+iconMaskName "VhdlFileViewIcon.msk"
+ftype 10
+)
+viewiconposition 0
+portVis (PortSigDisplay
+sTC 0
+)
+archFileType "UNKNOWN"
+)
+*50 (SaComponent
+uid 406,0
+optionalChildren [
+*51 (CptPort
+uid 416,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 417,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "29250,14625,30000,15375"
+)
+tg (CPTG
+uid 418,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 419,0
+va (VaSet
+font "courier,8,0"
+)
+xt "31000,14550,32500,15450"
+st "clk"
+blo "31000,15250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "clk"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 1
+)
+)
+)
+*52 (CptPort
+uid 420,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 421,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "29250,15625,30000,16375"
+)
+tg (CPTG
+uid 422,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 423,0
+va (VaSet
+font "courier,8,0"
+)
+xt "31000,15550,33500,16450"
+st "reset"
+blo "31000,16250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "reset"
+t "std_logic"
+preAdd 0
+posAdd 0
+o 2
+)
+)
+)
+*53 (CptPort
+uid 424,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 425,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,15625,40750,16375"
+)
+tg (CPTG
+uid 426,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 427,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,15550,39000,16450"
+st "pkt_addr"
+ju 2
+blo "39000,16250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pkt_addr"
+t "wbuf_a"
+eolc "-- output packet data pointer"
+preAdd 0
+posAdd 0
+o 3
+)
+)
+)
+*54 (CptPort
+uid 428,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 429,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,16625,40750,17375"
+)
+tg (CPTG
+uid 430,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 431,0
+va (VaSet
+font "courier,8,0"
+)
+xt "36000,16550,39000,17450"
+st "pkt_we"
+ju 2
+blo "39000,17250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pkt_we"
+t "std_logic"
+eolc "-- output packet data write enable"
+preAdd 0
+posAdd 0
+o 4
+)
+)
+)
+*55 (CptPort
+uid 432,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 433,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,14625,40750,15375"
+)
+tg (CPTG
+uid 434,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 435,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35000,14550,39000,15450"
+st "pkt_done"
+ju 2
+blo "39000,15250"
+)
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "pkt_done"
+t "std_logic"
+eolc "-- asserted after last output packet word has been written"
+preAdd 0
+posAdd 0
+o 5
+)
+)
+)
+*56 (CptPort
+uid 436,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 437,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "29250,18625,30000,19375"
+)
+tg (CPTG
+uid 438,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 439,0
+va (VaSet
+font "courier,8,0"
+)
+xt "31000,18550,34500,19450"
+st "tx_func"
+blo "31000,19250"
+)
+)
+thePort (LogicalPort
+decl (Decl
+n "tx_func"
+t "std_logic_vector"
+b "(3 downto 0)"
+eolc "-- tx function required"
+preAdd 0
+posAdd 0
+o 6
+)
+)
+)
+*57 (CptPort
+uid 440,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 441,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "40000,13625,40750,14375"
+)
+tg (CPTG
+uid 442,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 443,0
+va (VaSet
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+)
+)
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+)
+*180 (LeafLogPort
+port (LogicalPort
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+)
+pdm (PhysicalDM
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+font "courier,10,0"
+)
+groupVa (MVa
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..70640fa6f2c3cc51b89385b9152d8719ab267fdb
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd
@@ -0,0 +1,2993 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "triggerInputs_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352816382"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerInputs"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "triggerInputs"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "triggerInputs"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerInputs/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:33"
+)
+(vvPair
+variable "unit"
+value "triggerInputs"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "rtl"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+optionalChildren [
+*1 (PortIoIn
+uid 9,0
+shape (CompositeShape
+uid 10,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 11,0
+sl 0
+ro 270
+xt "-4000,4625,-2500,5375"
+)
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+pts [
+"-2500,5000"
+"-2000,5000"
+]
+)
+]
+)
+stc 0
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+tg (WTG
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+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
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+va (VaSet
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+)
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+)
+)
+)
+*2 (Net
+uid 15,0
+lang 2
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+posAdd 0
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+suid 1,0
+)
+declText (MLText
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+va (VaSet
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+)
+xt "20000,12175,50000,13075"
+st "cfd_discr_i : std_logic_vector(NUM_INPUTS-1 downto 0)
+"
+)
+)
+*3 (PortIoIn
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+shape (CompositeShape
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+optionalChildren [
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+f (Text
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+va (VaSet
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+)
+xt "-11500,3500,-5000,4400"
+st "clk_4x_logic"
+ju 2
+blo "-5000,4200"
+tm "WireNameMgr"
+)
+)
+)
+*4 (Net
+uid 29,0
+lang 2
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 2
+suid 2,0
+)
+declText (MLText
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+va (VaSet
+font "courier,8,0"
+)
+xt "20000,13075,47000,13975"
+st "clk_4x_logic : std_logic -- ! Rising edge active
+"
+)
+)
+*5 (PortIoIn
+uid 37,0
+shape (CompositeShape
+uid 38,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 39,0
+sl 0
+ro 270
+xt "-4000,2625,-2500,3375"
+)
+(Line
+uid 40,0
+sl 0
+ro 270
+xt "-2500,3000,-2000,3000"
+pts [
+"-2500,3000"
+"-2000,3000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
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+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 42,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-12500,2500,-5000,3400"
+st "logic_strobe_i"
+ju 2
+blo "-5000,3200"
+tm "WireNameMgr"
+)
+)
+)
+*6 (Net
+uid 43,0
+lang 2
+decl (Decl
+n "logic_strobe_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 3
+suid 3,0
+)
+declText (MLText
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+va (VaSet
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+st "logic_strobe_i : std_logic -- ! Pulses high once every 4 cycles of clk_4x_logic
+"
+)
+)
+*7 (PortIoIn
+uid 51,0
+shape (CompositeShape
+uid 52,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 53,0
+sl 0
+ro 270
+xt "-4000,1625,-2500,2375"
+)
+(Line
+uid 54,0
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+xt "-2500,2000,-2000,2000"
+pts [
+"-2500,2000"
+"-2000,2000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 55,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 56,0
+va (VaSet
+font "courier,8,0"
+)
+xt "-14000,1500,-5000,2400"
+st "threshold_discr_i"
+ju 2
+blo "-5000,2200"
+tm "WireNameMgr"
+)
+)
+)
+*8 (Net
+uid 57,0
+lang 2
+decl (Decl
+n "threshold_discr_i"
+t "std_logic_vector"
+b "(NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 4
+suid 4,0
+)
+declText (MLText
+uid 58,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,14875,69500,15775"
+st "threshold_discr_i : std_logic_vector(NUM_INPUTS-1 downto 0) -- ! inputs from threshold comparators
+"
+)
+)
+*9 (PortIoOut
+uid 65,0
+shape (CompositeShape
+uid 66,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 67,0
+sl 0
+ro 270
+xt "500,2625,2000,3375"
+)
+(Line
+uid 68,0
+sl 0
+ro 270
+xt "0,3000,500,3000"
+pts [
+"0,3000"
+"500,3000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 69,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 70,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,2500,11000,3400"
+st "trigger_times_o"
+blo "3000,3200"
+tm "WireNameMgr"
+)
+)
+)
+*10 (Net
+uid 71,0
+lang 2
+decl (Decl
+n "trigger_times_o"
+t "t_triggerTimeArray"
+b "(NUM_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 5
+suid 5,0
+)
+declText (MLText
+uid 72,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,15775,75500,16675"
+st "trigger_times_o : t_triggerTimeArray(NUM_INPUTS-1 downto 0) -- ! trigger arrival time ( w.r.t. logic_strobe)
+"
+)
+)
+*11 (PortIoOut
+uid 79,0
+shape (CompositeShape
+uid 80,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
+(Pentagon
+uid 81,0
+sl 0
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+xt "500,1625,2000,2375"
+)
+(Line
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+pts [
+"0,2000"
+"500,2000"
+]
+)
+]
+)
+stc 0
+sf 1
+tg (WTG
+uid 83,0
+ps "PortIoTextPlaceStrategy"
+stg "STSignalDisplayStrategy"
+f (Text
+uid 84,0
+va (VaSet
+font "courier,8,0"
+)
+xt "3000,1500,7500,2400"
+st "trigger_o"
+blo "3000,2200"
+tm "WireNameMgr"
+)
+)
+)
+*12 (Net
+uid 85,0
+lang 2
+decl (Decl
+n "trigger_o"
+t "std_logic_vector"
+b "(NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger active"
+o 6
+suid 6,0
+)
+declText (MLText
+uid 86,0
+va (VaSet
+font "courier,8,0"
+)
+xt "20000,16675,65000,17575"
+st "trigger_o : std_logic_vector(NUM_INPUTS-1 downto 0) -- ! High when trigger active
+"
+)
+)
+*13 (PortIoIn
+uid 93,0
+shape (CompositeShape
+uid 94,0
+va (VaSet
+vasetType 1
+fg "0,0,32768"
+)
+optionalChildren [
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+sl 0
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+xt "-4000,625,-2500,1375"
+)
+(Line
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..b8466a6be85fc076c43ef8ba84b2205de4e7f478
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb
@@ -0,0 +1,2674 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+(DmPackageRef
+library "work"
+unitName "fmcTLU"
+)
+(DmPackageRef
+library "unisim"
+unitName "vcomponents"
+)
+]
+libraryRefs [
+"ieee"
+"unisim"
+]
+)
+version "25.1"
+appVersion "2012.1 (Build 6)"
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+usingSuid 1
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+)
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+)
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+tm "NameColHdrMgr"
+)
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+tm "ModeColHdrMgr"
+)
+*10 (TypeColHdr
+tm "TypeColHdrMgr"
+)
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+tm "BoundsColHdrMgr"
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+)
+*13 (EolColHdr
+tm "EolColHdrMgr"
+)
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+o 3
+suid 1,0
+)
+)
+uid 108,0
+)
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+lang 2
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+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 4
+suid 2,0
+)
+)
+uid 110,0
+)
+*16 (LogPort
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+lang 2
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+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 5
+suid 3,0
+)
+)
+uid 112,0
+)
+*17 (LogPort
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+o 1
+suid 4,0
+)
+)
+uid 114,0
+)
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+lang 2
+m 1
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+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 7
+suid 5,0
+)
+)
+uid 143,0
+)
+*19 (LogPort
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+lang 2
+m 1
+decl (Decl
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+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger active"
+o 8
+suid 7,0
+)
+)
+uid 182,0
+)
+*20 (LogPort
+port (LogicalPort
+lang 2
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+preAdd 0
+o 14
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+)
+)
+uid 189,0
+)
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+o 16
+suid 9,0
+)
+)
+uid 191,0
+)
+*22 (LogPort
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+)
+)
+uid 193,0
+)
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+)
+)
+uid 195,0
+)
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+o 18
+suid 13,0
+)
+)
+uid 316,0
+)
+*25 (LogPort
+port (LogicalPort
+lang 2
+decl (Decl
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+o 19
+suid 14,0
+)
+)
+uid 318,0
+)
+*26 (LogPort
+port (LogicalPort
+lang 2
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+)
+)
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+)
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+preAdd 0
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+)
+)
+uid 332,0
+)
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+preAdd 0
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+)
+)
+uid 433,0
+)
+*29 (LogPort
+port (LogicalPort
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+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
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+o 11
+suid 18,0
+)
+)
+uid 435,0
+)
+*30 (LogPort
+port (LogicalPort
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+n "edge_rising_o"
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+preAdd 0
+posAdd 0
+o 12
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+)
+)
+uid 437,0
+)
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+lang 2
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+preAdd 0
+posAdd 0
+o 10
+suid 20,0
+)
+)
+uid 439,0
+)
+*32 (LogPort
+port (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_debug_o"
+t "std_logic_vector"
+b "( ((2*g_NUM_INPUTS)-1) DOWNTO 0)"
+eolc "-- ! Copy of input trigger level. High bits CFD, Low threshold"
+posAdd 0
+o 9
+suid 21,0
+)
+)
+uid 471,0
+)
+]
+)
+pdm (PhysicalDM
+displayShortBounds 1
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+)
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+)
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+]
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+uid 52,0
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+ldm (LogicalDM
+emptyRow *65 (LEmptyRow
+)
+uid 82,0
+optionalChildren [
+*66 (RefLabelRowHdr
+)
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+)
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+tm "RowExpandColHdrMgr"
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+tm "GroupColHdrMgr"
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+vaOverrides [
+]
+)
+]
+)
+uid 81,0
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+)
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerInputs"
+)
+(vvPair
+variable "date"
+value "07/24/13"
+)
+(vvPair
+variable "day"
+value "Wed"
+)
+(vvPair
+variable "day_long"
+value "Wednesday"
+)
+(vvPair
+variable "dd"
+value "24"
+)
+(vvPair
+variable "entity_name"
+value "triggerInputs"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
+(vvPair
+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
+)
+(vvPair
+variable "group"
+value "users"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "07"
+)
+(vvPair
+variable "module_name"
+value "triggerInputs"
+)
+(vvPair
+variable "month"
+value "Jul"
+)
+(vvPair
+variable "month_long"
+value "July"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@inputs/symbol.sb"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerInputs/symbol.sb"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
+variable "this_file"
+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "18:43:19"
+)
+(vvPair
+variable "unit"
+value "triggerInputs"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2012.1 (Build 6)"
+)
+(vvPair
+variable "view"
+value "symbol"
+)
+(vvPair
+variable "year"
+value "2013"
+)
+(vvPair
+variable "yy"
+value "13"
+)
+]
+)
+LanguageMgr "VhdlLangMgr"
+uid 48,0
+optionalChildren [
+*91 (SymbolBody
+uid 8,0
+optionalChildren [
+*92 (CptPort
+uid 116,0
+optionalChildren [
+*93 (FFT
+pts [
+"7750,17000"
+"7000,17375"
+"7000,16625"
+]
+uid 138,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+lineColor "0,32896,0"
+lineWidth 2
+)
+xt "7000,16625,7750,17375"
+)
+]
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 117,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,16625,7000,17375"
+)
+tg (CPTG
+uid 118,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 119,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,16550,14500,17450"
+st "clk_4x_logic"
+blo "8000,17250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 120,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,3600,77500,4500"
+st "clk_4x_logic : IN std_logic ; -- ! Rising edge active
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_4x_logic"
+t "std_logic"
+eolc "! Rising edge active"
+preAdd 0
+posAdd 0
+o 3
+suid 1,0
+)
+)
+)
+*94 (CptPort
+uid 121,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 122,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,18625,7000,19375"
+)
+tg (CPTG
+uid 123,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 124,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,18550,17000,19450"
+st "strobe_4x_logic_i"
+blo "8000,19250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 125,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,4500,92000,5400"
+st "strobe_4x_logic_i : IN std_logic ; -- ! Pulses high once every 4 cycles of clk_4x_logic
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_4x_logic_i"
+t "std_logic"
+eolc "! Pulses high once every 4 cycles of clk_4x_logic"
+preAdd 0
+posAdd 0
+o 4
+suid 2,0
+)
+)
+)
+*95 (CptPort
+uid 126,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 127,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,25625,7000,26375"
+)
+tg (CPTG
+uid 128,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 129,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,25550,28500,26450"
+st "threshold_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "8000,26250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 130,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,5400,101000,6300"
+st "threshold_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! inputs from threshold comparators
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 5
+suid 3,0
+)
+)
+)
+*96 (CptPort
+uid 131,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 132,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,29625,7000,30375"
+)
+tg (CPTG
+uid 133,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 134,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,29550,25500,30450"
+st "cfd_discr_p_i : (g_NUM_INPUTS-1:0)"
+blo "8000,30250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 135,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,1800,81500,2700"
+st "cfd_discr_p_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_p_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 1
+suid 4,0
+)
+)
+)
+*97 (CptPort
+uid 145,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 146,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,19625,52750,20375"
+)
+tg (CPTG
+uid 147,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 148,0
+va (VaSet
+font "courier,8,0"
+)
+xt "32500,19550,51000,20450"
+st "trigger_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,20250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 149,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,7200,107000,8100"
+st "trigger_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! trigger arrival time ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! trigger arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 7
+suid 5,0
+)
+)
+)
+*98 (CptPort
+uid 184,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 185,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,27625,52750,28375"
+)
+tg (CPTG
+uid 186,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 187,0
+va (VaSet
+font "courier,8,0"
+)
+xt "35500,27550,51000,28450"
+st "trigger_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,28250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 188,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,8100,96500,9000"
+st "trigger_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! High when trigger active
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "trigger_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! High when trigger active"
+o 8
+suid 7,0
+)
+)
+)
+*99 (CptPort
+uid 199,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 200,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,34625,7000,35375"
+)
+tg (CPTG
+uid 201,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 202,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,34550,14000,35450"
+st "ipbus_clk_i"
+blo "8000,35250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 203,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,13500,65500,14400"
+st "ipbus_clk_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_clk_i"
+t "std_logic"
+preAdd 0
+o 14
+suid 8,0
+)
+)
+)
+*100 (CptPort
+uid 204,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 205,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,37625,7000,38375"
+)
+tg (CPTG
+uid 206,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 207,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,37550,11500,38450"
+st "ipbus_i"
+blo "8000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 208,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,15300,83000,16200"
+st "ipbus_i : IN ipb_wbus ; -- Signals from IPBus core to slave
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_i"
+t "ipb_wbus"
+eolc "Signals from IPBus core to slave"
+o 16
+suid 9,0
+)
+)
+)
+*101 (CptPort
+uid 209,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 210,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,36625,52750,37375"
+)
+tg (CPTG
+uid 211,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 212,0
+va (VaSet
+font "courier,8,0"
+)
+xt "47500,36550,51000,37450"
+st "ipbus_o"
+ju 2
+blo "51000,37250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 213,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,16200,83000,17100"
+st "ipbus_o : OUT ipb_rbus ; -- signals from slave to IPBus core
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "ipbus_o"
+t "ipb_rbus"
+eolc "signals from slave to IPBus core"
+o 17
+suid 10,0
+)
+)
+)
+*102 (CptPort
+uid 214,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 215,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,39625,7000,40375"
+)
+tg (CPTG
+uid 216,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 217,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,39550,15000,40450"
+st "ipbus_reset_i"
+blo "8000,40250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 218,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,14400,65500,15300"
+st "ipbus_reset_i : IN std_logic ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "ipbus_reset_i"
+t "std_logic"
+o 15
+suid 11,0
+)
+)
+)
+*103 (CptPort
+uid 320,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 321,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,21625,7000,22375"
+)
+tg (CPTG
+uid 322,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 323,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,21550,16000,22450"
+st "clk_16x_logic_i"
+blo "8000,22250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 324,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,17100,81000,18000"
+st "clk_16x_logic_i : IN std_logic ; --! 640MHz clock ( 16x 40MHz )
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "clk_16x_logic_i"
+t "std_logic"
+eolc "--! 640MHz clock ( 16x 40MHz )"
+o 18
+suid 13,0
+)
+)
+)
+*104 (CptPort
+uid 325,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 326,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,23625,7000,24375"
+)
+tg (CPTG
+uid 327,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 328,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,23550,17500,24450"
+st "strobe_16x_logic_i"
+blo "8000,24250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 329,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,18000,86000,18900"
+st "strobe_16x_logic_i : IN std_logic --! Pulses one cycle every 4 of 16x clock.
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "strobe_16x_logic_i"
+t "std_logic"
+eolc "--! Pulses one cycle every 4 of 16x clock."
+o 19
+suid 14,0
+)
+)
+)
+*105 (CptPort
+uid 334,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 335,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,30625,7000,31375"
+)
+tg (CPTG
+uid 336,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 337,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,30550,25500,31450"
+st "cfd_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "8000,31250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 338,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,2700,81500,3600"
+st "cfd_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ;
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "cfd_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+posAdd 0
+o 2
+suid 15,0
+)
+)
+)
+*106 (CptPort
+uid 339,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 340,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "6250,26625,7000,27375"
+)
+tg (CPTG
+uid 341,0
+ps "CptPortTextPlaceStrategy"
+stg "VerticalLayoutStrategy"
+f (Text
+uid 342,0
+va (VaSet
+font "courier,8,0"
+)
+xt "8000,26550,28500,27450"
+st "threshold_discr_n_i : (g_NUM_INPUTS-1:0)"
+blo "8000,27250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 343,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,6300,101000,7200"
+st "threshold_discr_n_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! inputs from threshold comparators
+"
+)
+thePort (LogicalPort
+lang 2
+decl (Decl
+n "threshold_discr_n_i"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "! inputs from threshold comparators"
+preAdd 0
+posAdd 0
+o 6
+suid 16,0
+)
+)
+)
+*107 (CptPort
+uid 413,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 414,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,37625,52750,38375"
+)
+tg (CPTG
+uid 415,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 416,0
+va (VaSet
+font "courier,8,0"
+)
+xt "33000,37550,51000,38450"
+st "edge_falling_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,38250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 417,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,12600,95500,13500"
+st "edge_falling_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! High when falling edge
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when falling edge"
+preAdd 0
+posAdd 0
+o 13
+suid 17,0
+)
+)
+)
+*108 (CptPort
+uid 418,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 419,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,38625,52750,39375"
+)
+tg (CPTG
+uid 420,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 421,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30000,38550,51000,39450"
+st "edge_falling_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,39250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 422,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,10800,105500,11700"
+st "edge_falling_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! edge arrival time ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_falling_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 11
+suid 18,0
+)
+)
+)
+*109 (CptPort
+uid 423,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 424,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,39625,52750,40375"
+)
+tg (CPTG
+uid 425,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 426,0
+va (VaSet
+font "courier,8,0"
+)
+xt "33500,39550,51000,40450"
+st "edge_rising_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,40250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 427,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,11700,95000,12600"
+st "edge_rising_o : OUT std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! High when rising edge
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_o"
+t "std_logic_vector"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! High when rising edge"
+preAdd 0
+posAdd 0
+o 12
+suid 19,0
+)
+)
+)
+*110 (CptPort
+uid 428,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 429,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,40625,52750,41375"
+)
+tg (CPTG
+uid 430,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 431,0
+va (VaSet
+font "courier,8,0"
+)
+xt "30500,40550,51000,41450"
+st "edge_rising_times_o : (g_NUM_INPUTS-1:0)"
+ju 2
+blo "51000,41250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 432,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9900,105500,10800"
+st "edge_rising_times_o : OUT t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! edge arrival time ( w.r.t. logic_strobe)
+"
+)
+thePort (LogicalPort
+lang 2
+m 1
+decl (Decl
+n "edge_rising_times_o"
+t "t_triggerTimeArray"
+b "(g_NUM_INPUTS-1 DOWNTO 0)"
+eolc "-- ! edge arrival time ( w.r.t. logic_strobe)"
+preAdd 0
+posAdd 0
+o 10
+suid 20,0
+)
+)
+)
+*111 (CptPort
+uid 466,0
+ps "OnEdgeStrategy"
+shape (Triangle
+uid 467,0
+ro 90
+va (VaSet
+vasetType 1
+fg "0,65535,0"
+)
+xt "52000,41625,52750,42375"
+)
+tg (CPTG
+uid 468,0
+ps "CptPortTextPlaceStrategy"
+stg "RightVerticalLayoutStrategy"
+f (Text
+uid 469,0
+va (VaSet
+font "courier,8,0"
+)
+xt "29500,41550,51000,42450"
+st "trigger_debug_o : (((2*g_NUM_INPUTS)-1):0)"
+ju 2
+blo "51000,42250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 470,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,9000,116500,9900"
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+USE ieee.numeric_std.all;
+
+USE work.ipbus.all;
+USE work.fmcTLU.all;
+
+library unisim ;
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/_symbol.sb._fpf b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/_symbol.sb._fpf
new file mode 100755
index 0000000000000000000000000000000000000000..e0bac7fb116ed6613da756e3b4dfbc6595c8a738
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/_symbol.sb._fpf
@@ -0,0 +1,3 @@
+INCLUDE list {
+ DEFAULT atom 1
+}
diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..56adff436fd39ce58a3abdc42dd732f429c88cfb
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd
@@ -0,0 +1,2846 @@
+DocumentHdrVersion "1.1"
+Header (DocumentHdr
+version 2
+dmPackageRefs [
+]
+properties [
+(HdrProperty
+class "HDS"
+name "DocView"
+value "triggerLogic_rtl.vhd"
+)
+(HdrProperty
+class "HDS"
+name "DocViewState"
+value "1352816260"
+)
+]
+)
+version "30.1"
+appVersion "2010.3 (Build 21)"
+noEmbeddedEditors 1
+model (BlockDiag
+VExpander (VariableExpander
+vvMap [
+(vvPair
+variable "HDLDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerLogic"
+)
+(vvPair
+variable "date"
+value "11/13/12"
+)
+(vvPair
+variable "day"
+value "Tue"
+)
+(vvPair
+variable "day_long"
+value "Tuesday"
+)
+(vvPair
+variable "dd"
+value "13"
+)
+(vvPair
+variable "entity_name"
+value "triggerLogic"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "rtl.bd"
+)
+(vvPair
+variable "f_logical"
+value "rtl.bd"
+)
+(vvPair
+variable "f_noext"
+value "rtl"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "fmc_mTLU_lib"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "mm"
+value "11"
+)
+(vvPair
+variable "module_name"
+value "triggerLogic"
+)
+(vvPair
+variable "month"
+value "Nov"
+)
+(vvPair
+variable "month_long"
+value "November"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/rtl.bd"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerLogic/rtl.bd"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "bd"
+)
+(vvPair
+variable "this_file"
+value "rtl"
+)
+(vvPair
+variable "this_file_logical"
+value "rtl"
+)
+(vvPair
+variable "time"
+value "16:59:33"
+)
+(vvPair
+variable "unit"
+value "triggerLogic"
+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb
new file mode 100644
index 0000000000000000000000000000000000000000..6f8d1d299d5c0941ef727c68f75dd8fc5ddb0d9e
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb
@@ -0,0 +1,2169 @@
+DocumentHdrVersion "1.1"
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+(DmPackageRef
+library "ieee"
+unitName "std_logic_1164"
+)
+(DmPackageRef
+library "ieee"
+unitName "numeric_std"
+)
+(DmPackageRef
+library "work"
+unitName "ipbus"
+)
+]
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+"ieee"
+]
+)
+version "25.1"
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+value "work"
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+(vvPair
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+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
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+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
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+(vvPair
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+(vvPair
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+(vvPair
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+(vvPair
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+(vvPair
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+(vvPair
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+(vvPair
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+value "HDL Designer Series"
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+(vvPair
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+value "<TBD>"
+)
+(vvPair
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+value "<TBD>"
+)
+(vvPair
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+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
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+(vvPair
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+value "<TBD>"
+)
+(vvPair
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+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
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+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
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+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "11:16:47"
+)
+(vvPair
+variable "unit"
+value "triggerLogic"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
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+)
+(vvPair
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+(vvPair
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb.bak b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb.bak
new file mode 100644
index 0000000000000000000000000000000000000000..e93a40a73cec03bdb0fffac23613a15fc6c403c6
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb.bak
@@ -0,0 +1,2182 @@
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+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl"
+)
+(vvPair
+variable "HDSDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "SideDataDesignDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb.info"
+)
+(vvPair
+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb.user"
+)
+(vvPair
+variable "SourceDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds"
+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "symbol"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic"
+)
+(vvPair
+variable "d_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerLogic"
+)
+(vvPair
+variable "date"
+value "12/10/12"
+)
+(vvPair
+variable "day"
+value "Mon"
+)
+(vvPair
+variable "day_long"
+value "Monday"
+)
+(vvPair
+variable "dd"
+value "10"
+)
+(vvPair
+variable "entity_name"
+value "triggerLogic"
+)
+(vvPair
+variable "ext"
+value "<TBD>"
+)
+(vvPair
+variable "f"
+value "symbol.sb"
+)
+(vvPair
+variable "f_logical"
+value "symbol.sb"
+)
+(vvPair
+variable "f_noext"
+value "symbol"
+)
+(vvPair
+variable "group"
+value "HEP_Instrumentation"
+)
+(vvPair
+variable "host"
+value "kipper.phy.bris.ac.uk"
+)
+(vvPair
+variable "language"
+value "VHDL"
+)
+(vvPair
+variable "library"
+value "work"
+)
+(vvPair
+variable "library_downstream_HdsLintPlugin"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/designcheck"
+)
+(vvPair
+variable "library_downstream_ISEPARInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ImpactInvoke"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "library_downstream_ModelSimCompiler"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/work"
+)
+(vvPair
+variable "library_downstream_XSTDataPrep"
+value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
+)
+(vvPair
+variable "mm"
+value "12"
+)
+(vvPair
+variable "module_name"
+value "triggerLogic"
+)
+(vvPair
+variable "month"
+value "Dec"
+)
+(vvPair
+variable "month_long"
+value "December"
+)
+(vvPair
+variable "p"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/trigger@logic/symbol.sb"
+)
+(vvPair
+variable "p_logical"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/triggerLogic/symbol.sb"
+)
+(vvPair
+variable "package_name"
+value "<Undefined Variable>"
+)
+(vvPair
+variable "project_name"
+value "fmc_mTLU"
+)
+(vvPair
+variable "series"
+value "HDL Designer Series"
+)
+(vvPair
+variable "task_ADMS"
+value "<TBD>"
+)
+(vvPair
+variable "task_DesignCompilerPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_LeonardoPath"
+value "/opt/CAD/Mentor/LeonardoSpectrum_2008a/bin"
+)
+(vvPair
+variable "task_ModelSimPath"
+value "/opt/CAD/Mentor/Modelsim/6.4a/modeltech/bin"
+)
+(vvPair
+variable "task_NC-SimPath"
+value "<TBD>"
+)
+(vvPair
+variable "task_PrecisionRTLPath"
+value "/opt/CAD/Mentor/Precis_Synth_2009a_update2/Mgc_home/bin"
+)
+(vvPair
+variable "task_QuestaSimPath"
+value "/opt/CAD/Mentor/HDS2008.1b/questasim/bin"
+)
+(vvPair
+variable "task_VCSPath"
+value "<TBD>"
+)
+(vvPair
+variable "this_ext"
+value "sb"
+)
+(vvPair
+variable "this_file"
+value "symbol"
+)
+(vvPair
+variable "this_file_logical"
+value "symbol"
+)
+(vvPair
+variable "time"
+value "10:56:05"
+)
+(vvPair
+variable "unit"
+value "triggerLogic"
+)
+(vvPair
+variable "user"
+value "phdgc"
+)
+(vvPair
+variable "version"
+value "2010.3 (Build 21)"
+)
+(vvPair
+variable "view"
+value "symbol"
+)
+(vvPair
+variable "year"
+value "2012"
+)
+(vvPair
+variable "yy"
+value "12"
+)
+]
+)
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+)
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+)
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+"
+)
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+)
+)
+)
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+"
+)
+thePort (LogicalPort
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+)
+)
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+)
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+"
+)
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+)
+)
+)
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+)
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+)
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+"
+)
+thePort (LogicalPort
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+suid 4,0
+)
+)
+)
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+)
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+)
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+)
+)
+dt (MLText
+uid 91,0
+va (VaSet
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+)
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+st "ipbus_o : OUT ipb_rbus ; -- signals from slave to IPBus core
+"
+)
+thePort (LogicalPort
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+decl (Decl
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+suid 5,0
+)
+)
+)
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+)
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+)
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+)
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+)
+)
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+)
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+"
+)
+thePort (LogicalPort
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+o 4
+suid 6,0
+)
+)
+)
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+ps "OnEdgeStrategy"
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+)
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+)
+tg (CPTG
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+)
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+)
+)
+dt (MLText
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+va (VaSet
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+)
+xt "44000,7200,106000,8100"
+st "trigger_i : IN std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0) ; -- ! High when trigger from input conector active
+"
+)
+thePort (LogicalPort
+lang 2
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+o 7
+suid 7,0
+)
+)
+)
+*89 (CptPort
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+ps "OnEdgeStrategy"
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+)
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+)
+tg (CPTG
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+uid 105,0
+va (VaSet
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+)
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+st "veto_i"
+blo "9000,22250"
+tm "CptPortNameMgr"
+)
+)
+dt (MLText
+uid 106,0
+va (VaSet
+font "courier,8,0"
+)
+xt "44000,8100,80000,9000"
+st "veto_i : IN std_logic ; -- ! Halts triggers when high
+"
+)
+thePort (LogicalPort
+decl (Decl
+n "veto_i"
+t "std_logic"
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+suid 8,0
+)
+)
+)
+*90 (CptPort
+uid 109,0
+ps "OnEdgeStrategy"
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+)
+xt "45000,16625,45750,17375"
+)
+tg (CPTG
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+f (Text
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+)
+xt "34000,16550,44000,17450"
+st "post_veto_trigger_o"
+ju 2
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+tm "CptPortNameMgr"
+)
+)
+dt (MLText
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+va (VaSet
+font "courier,8,0"
+)
+xt "44000,10800,82500,11700"
+st "post_veto_trigger_o : OUT std_logic ; -- ! goes high when trigger passes
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
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+t "std_logic"
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+suid 9,0
+)
+)
+)
+*91 (CptPort
+uid 244,0
+ps "OnEdgeStrategy"
+shape (Triangle
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+ro 90
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+)
+xt "45000,27625,45750,28375"
+)
+tg (CPTG
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+va (VaSet
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+)
+xt "35500,27550,44000,28450"
+st "trigger_active_o"
+ju 2
+blo "44000,28250"
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+)
+)
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+)
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+"
+)
+thePort (LogicalPort
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+o 10
+suid 10,0
+)
+)
+)
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+)
+xt "45000,28625,45750,29375"
+)
+tg (CPTG
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+va (VaSet
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+)
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+st "pre_veto_trigger_o"
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+)
+)
+dt (MLText
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+)
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+"
+)
+thePort (LogicalPort
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+decl (Decl
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+o 11
+suid 11,0
+)
+)
+)
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+)
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+)
+tg (CPTG
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+ps "CptPortTextPlaceStrategy"
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+va (VaSet
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+)
+xt "25500,29550,44000,30450"
+st "event_number_o : (g_IPBUS_WIDTH-1:0)"
+ju 2
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+tm "CptPortNameMgr"
+)
+)
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+)
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+st "event_number_o : OUT std_logic_vector (g_IPBUS_WIDTH-1 downto 0) ; -- starts at one. Increments for each post_veto_trigger
+"
+)
+thePort (LogicalPort
+m 1
+decl (Decl
+n "event_number_o"
+t "std_logic_vector"
+b "(g_IPBUS_WIDTH-1 downto 0)"
+eolc "starts at one. Increments for each post_veto_trigger"
+o 12
+suid 12,0
+)
+)
+)
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+ps "OnEdgeStrategy"
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+uid 360,0
+ro 90
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+)
+xt "7250,31625,8000,32375"
+)
+tg (CPTG
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+)
+xt "9000,31550,16000,32450"
+st "logic_reset_i"
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+)
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+"
+)
+thePort (LogicalPort
+decl (Decl
+n "logic_reset_i"
+t "std_logic"
+eolc "active high. Synchronous with clk_4x_logic"
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+suid 13,0
+)
+)
+)
+]
+shape (Rectangle
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+fg "0,65535,0"
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+)
+xt "8000,12000,45000,33000"
+)
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+)
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+)
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+)
+xt "17750,22000,24250,22900"
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+)
+)
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+ps "CenterOffsetStrategy"
+matrix (Matrix
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+)
+xt "18000,9300,32000,12900"
+st "Generic Declarations
+
+g_NUM_INPUTS positive 4
+g_IPBUS_WIDTH positive 32 "
+)
+header "Generic Declarations"
+showHdrWhenContentsEmpty 1
+)
+elements [
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+name "g_NUM_INPUTS"
+type "positive"
+value "4"
+)
+(GiElement
+name "g_IPBUS_WIDTH"
+type "positive"
+value "32"
+)
+]
+)
+portInstanceVisAsIs 1
+portInstanceVis (PortSigDisplay
+sIVOD 1
+)
+portVis (PortSigDisplay
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+)
+)
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+)
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+"
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+)
+position 1
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.bd b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.bd
new file mode 100644
index 0000000000000000000000000000000000000000..85991d0d1a936368c6e138fe4a35801814077fdd
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.bd
@@ -0,0 +1,5258 @@
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+)
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+
+"
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+)
+)
+)
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+st "
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+
+"
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+)
+)
+)
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+)
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+)
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+
+"
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+)
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+)
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+ begin
+ if rising_edge(clk) then
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+ new_d <= new_packet;
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+"
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+"
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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+)
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diff --git a/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.fc b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.fc
new file mode 100644
index 0000000000000000000000000000000000000000..5cebdbba064b1bdfba0cfd57eee80675bf6ab33c
--- /dev/null
+++ b/firmware/minitlu/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.fc
@@ -0,0 +1,2155 @@
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+class "HDS"
+name "DocView"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/workspace/IPbusFirmware/firmware/ipbus/hdl/udp_shim.vhd"
+)
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+class "HDS"
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+)
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+)
+version "19.1"
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+)
+(vvPair
+variable "HDSDir"
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+)
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+variable "SideDataDesignDir"
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+)
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+variable "SideDataUserDir"
+value "/projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/udp_shim/rtl.fc.user"
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+)
+(vvPair
+variable "appl"
+value "HDL Designer"
+)
+(vvPair
+variable "arch_name"
+value "rtl"
+)
+(vvPair
+variable "config"
+value "%(unit)_config"
+)
+(vvPair
+variable "d"
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+variable "date"
+value "11/13/12"
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+variable "day"
+value "Tue"
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+value "Tuesday"
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+value "13"
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+(vvPair
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+value "16:59:31"
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+variable "user"
+value "phdgc"
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+variable "version"
+value "2010.3 (Build 21)"
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+variable "view"
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+)
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diff --git a/firmware/minitlu/ise/ipcore_dir/CounterDown.xco b/firmware/minitlu/ise/ipcore_dir/CounterDown.xco
new file mode 100644
index 0000000000000000000000000000000000000000..6268e1d052e05d3516949548d30dc4a8f60bda44
--- /dev/null
+++ b/firmware/minitlu/ise/ipcore_dir/CounterDown.xco
@@ -0,0 +1,70 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.4
+# Date: Tue Feb 12 16:06:07 2013
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_counter_binary:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx16
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Binary_Counter xilinx.com:ip:c_counter_binary:11.0
+# END Select
+# BEGIN Parameters
+CSET ainit_value=FFFFFFFF
+CSET ce=false
+CSET component_name=CounterDown
+CSET count_mode=DOWN
+CSET fb_latency=0
+CSET fb_latency_configuration=Manual
+CSET final_count_value=1
+CSET implementation=Fabric
+CSET increment_value=1
+CSET latency=1
+CSET latency_configuration=Manual
+CSET load=true
+CSET load_sense=Active_High
+CSET output_width=32
+CSET restrict_count=false
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_threshold_output=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET threshold_value=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-12T06:28:35Z
+# END Extra information
+GENERATE
+# CRC: 137adc28
diff --git a/firmware/minitlu/ise/ipcore_dir/CounterUp.xco b/firmware/minitlu/ise/ipcore_dir/CounterUp.xco
new file mode 100644
index 0000000000000000000000000000000000000000..9939b99ba85c2dda9b79d664287879e59e91dea3
--- /dev/null
+++ b/firmware/minitlu/ise/ipcore_dir/CounterUp.xco
@@ -0,0 +1,70 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.4
+# Date: Tue Feb 12 15:51:34 2013
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_counter_binary:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx16
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Binary_Counter xilinx.com:ip:c_counter_binary:11.0
+# END Select
+# BEGIN Parameters
+CSET ainit_value=0
+CSET ce=true
+CSET component_name=CounterUp
+CSET count_mode=UP
+CSET fb_latency=0
+CSET fb_latency_configuration=Manual
+CSET final_count_value=1
+CSET implementation=Fabric
+CSET increment_value=1
+CSET latency=1
+CSET latency_configuration=Manual
+CSET load=false
+CSET load_sense=Active_High
+CSET output_width=32
+CSET restrict_count=false
+CSET sclr=false
+CSET sinit=true
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_threshold_output=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET threshold_value=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-12T06:28:35Z
+# END Extra information
+GENERATE
+# CRC: ba6b256c
diff --git a/firmware/minitlu/ise/ipcore_dir/FIFO.xco b/firmware/minitlu/ise/ipcore_dir/FIFO.xco
new file mode 100644
index 0000000000000000000000000000000000000000..0aa0f3f136f85455e0bba3dc6ee33371a615801b
--- /dev/null
+++ b/firmware/minitlu/ise/ipcore_dir/FIFO.xco
@@ -0,0 +1,219 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Fri Aug 29 16:37:03 2014
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:fifo_generator:8.4
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=FIFO
+CSET data_count=false
+CSET data_count_width=4
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=3
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_handshake_flag_options_axis=false
+CSET enable_handshake_flag_options_rach=false
+CSET enable_handshake_flag_options_rdch=false
+CSET enable_handshake_flag_options_wach=false
+CSET enable_handshake_flag_options_wdch=false
+CSET enable_handshake_flag_options_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Common_Clock_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=13
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=12
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=64
+CSET input_depth=16
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=64
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=Empty
+CSET programmable_empty_type_rach=Empty
+CSET programmable_empty_type_rdch=Empty
+CSET programmable_empty_type_wach=Empty
+CSET programmable_empty_type_wdch=Empty
+CSET programmable_empty_type_wrch=Empty
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET programmable_full_type_axis=Full
+CSET programmable_full_type_rach=Full
+CSET programmable_full_type_rdch=Full
+CSET programmable_full_type_wach=Full
+CSET programmable_full_type_wdch=Full
+CSET programmable_full_type_wrch=Full
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=4
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=false
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=4
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-22T06:08:52Z
+# END Extra information
+GENERATE
+# CRC: e0f1f870
diff --git a/firmware/minitlu/ise/ipcore_dir/internalTriggerGenerator.xco b/firmware/minitlu/ise/ipcore_dir/internalTriggerGenerator.xco
new file mode 100644
index 0000000000000000000000000000000000000000..6ad498bf47267a63d15e5afcbeee2d4180eb1715
--- /dev/null
+++ b/firmware/minitlu/ise/ipcore_dir/internalTriggerGenerator.xco
@@ -0,0 +1,70 @@
+##############################################################
+#
+# Xilinx Core Generator version 13.4
+# Date: Mon Dec 10 16:39:06 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:c_counter_binary:11.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx16
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = csg324
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Binary_Counter xilinx.com:ip:c_counter_binary:11.0
+# END Select
+# BEGIN Parameters
+CSET ainit_value=0
+CSET ce=true
+CSET component_name=internalTriggerGenerator
+CSET count_mode=DOWN
+CSET fb_latency=0
+CSET fb_latency_configuration=Automatic
+CSET final_count_value=1
+CSET implementation=DSP48
+CSET increment_value=1
+CSET latency=2
+CSET latency_configuration=Automatic
+CSET load=true
+CSET load_sense=Active_High
+CSET output_width=32
+CSET restrict_count=false
+CSET sclr=false
+CSET sinit=false
+CSET sinit_value=0
+CSET sset=false
+CSET sync_ce_priority=Sync_Overrides_CE
+CSET sync_threshold_output=false
+CSET syncctrlpriority=Reset_Overrides_Set
+CSET threshold_value=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-12T06:28:35Z
+# END Extra information
+GENERATE
+# CRC: 8097337d
diff --git a/firmware/minitlu/ise/ipcore_dir/tlu_event_fifo.xco b/firmware/minitlu/ise/ipcore_dir/tlu_event_fifo.xco
new file mode 100644
index 0000000000000000000000000000000000000000..44329af14dc7282c7b25e9ea2b214806d0d10dab
--- /dev/null
+++ b/firmware/minitlu/ise/ipcore_dir/tlu_event_fifo.xco
@@ -0,0 +1,219 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Thu Aug 28 15:34:30 2014
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:fifo_generator:8.4
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx45t
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fgg484
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.4
+# END Select
+# BEGIN Parameters
+CSET add_ngc_constraint_axi=false
+CSET almost_empty_flag=true
+CSET almost_full_flag=true
+CSET aruser_width=1
+CSET awuser_width=1
+CSET axi_address_width=32
+CSET axi_data_width=64
+CSET axi_type=AXI4_Stream
+CSET axis_type=FIFO
+CSET buser_width=1
+CSET clock_enable_type=Slave_Interface_Clock_Enable
+CSET clock_type_axi=Common_Clock
+CSET component_name=tlu_event_fifo
+CSET data_count=false
+CSET data_count_width=14
+CSET disable_timing_violations=false
+CSET disable_timing_violations_axi=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_assert_value_axis=1022
+CSET empty_threshold_assert_value_rach=1022
+CSET empty_threshold_assert_value_rdch=1022
+CSET empty_threshold_assert_value_wach=1022
+CSET empty_threshold_assert_value_wdch=1022
+CSET empty_threshold_assert_value_wrch=1022
+CSET empty_threshold_negate_value=5
+CSET enable_aruser=false
+CSET enable_awuser=false
+CSET enable_buser=false
+CSET enable_common_overflow=false
+CSET enable_common_underflow=false
+CSET enable_data_counts_axis=false
+CSET enable_data_counts_rach=false
+CSET enable_data_counts_rdch=false
+CSET enable_data_counts_wach=false
+CSET enable_data_counts_wdch=false
+CSET enable_data_counts_wrch=false
+CSET enable_ecc=false
+CSET enable_ecc_axis=false
+CSET enable_ecc_rach=false
+CSET enable_ecc_rdch=false
+CSET enable_ecc_wach=false
+CSET enable_ecc_wdch=false
+CSET enable_ecc_wrch=false
+CSET enable_handshake_flag_options_axis=false
+CSET enable_handshake_flag_options_rach=false
+CSET enable_handshake_flag_options_rdch=false
+CSET enable_handshake_flag_options_wach=false
+CSET enable_handshake_flag_options_wdch=false
+CSET enable_handshake_flag_options_wrch=false
+CSET enable_read_channel=false
+CSET enable_read_pointer_increment_by2=false
+CSET enable_reset_synchronization=true
+CSET enable_ruser=false
+CSET enable_tdata=false
+CSET enable_tdest=false
+CSET enable_tid=false
+CSET enable_tkeep=false
+CSET enable_tlast=false
+CSET enable_tready=true
+CSET enable_tstrobe=false
+CSET enable_tuser=false
+CSET enable_write_channel=false
+CSET enable_wuser=false
+CSET fifo_application_type_axis=Data_FIFO
+CSET fifo_application_type_rach=Data_FIFO
+CSET fifo_application_type_rdch=Data_FIFO
+CSET fifo_application_type_wach=Data_FIFO
+CSET fifo_application_type_wdch=Data_FIFO
+CSET fifo_application_type_wrch=Data_FIFO
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET fifo_implementation_axis=Common_Clock_Block_RAM
+CSET fifo_implementation_rach=Common_Clock_Block_RAM
+CSET fifo_implementation_rdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wach=Common_Clock_Block_RAM
+CSET fifo_implementation_wdch=Common_Clock_Block_RAM
+CSET fifo_implementation_wrch=Common_Clock_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=16000
+CSET full_threshold_assert_value_axis=1023
+CSET full_threshold_assert_value_rach=1023
+CSET full_threshold_assert_value_rdch=1023
+CSET full_threshold_assert_value_wach=1023
+CSET full_threshold_assert_value_wdch=1023
+CSET full_threshold_assert_value_wrch=1023
+CSET full_threshold_negate_value=15999
+CSET id_width=4
+CSET inject_dbit_error=false
+CSET inject_dbit_error_axis=false
+CSET inject_dbit_error_rach=false
+CSET inject_dbit_error_rdch=false
+CSET inject_dbit_error_wach=false
+CSET inject_dbit_error_wdch=false
+CSET inject_dbit_error_wrch=false
+CSET inject_sbit_error=false
+CSET inject_sbit_error_axis=false
+CSET inject_sbit_error_rach=false
+CSET inject_sbit_error_rdch=false
+CSET inject_sbit_error_wach=false
+CSET inject_sbit_error_wdch=false
+CSET inject_sbit_error_wrch=false
+CSET input_data_width=64
+CSET input_depth=16384
+CSET input_depth_axis=1024
+CSET input_depth_rach=16
+CSET input_depth_rdch=1024
+CSET input_depth_wach=16
+CSET input_depth_wdch=1024
+CSET input_depth_wrch=16
+CSET interface_type=Native
+CSET output_data_width=32
+CSET output_depth=32768
+CSET overflow_flag=false
+CSET overflow_flag_axi=false
+CSET overflow_sense=Active_High
+CSET overflow_sense_axi=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_empty_type_axis=Empty
+CSET programmable_empty_type_rach=Empty
+CSET programmable_empty_type_rdch=Empty
+CSET programmable_empty_type_wach=Empty
+CSET programmable_empty_type_wdch=Empty
+CSET programmable_empty_type_wrch=Empty
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET programmable_full_type_axis=Full
+CSET programmable_full_type_rach=Full
+CSET programmable_full_type_rdch=Full
+CSET programmable_full_type_wach=Full
+CSET programmable_full_type_wdch=Full
+CSET programmable_full_type_wrch=Full
+CSET rach_type=FIFO
+CSET rdch_type=FIFO
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=16
+CSET register_slice_mode_axis=Fully_Registered
+CSET register_slice_mode_rach=Fully_Registered
+CSET register_slice_mode_rdch=Fully_Registered
+CSET register_slice_mode_wach=Fully_Registered
+CSET register_slice_mode_wdch=Fully_Registered
+CSET register_slice_mode_wrch=Fully_Registered
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET ruser_width=1
+CSET synchronization_stages=2
+CSET synchronization_stages_axi=2
+CSET tdata_width=64
+CSET tdest_width=4
+CSET tid_width=8
+CSET tkeep_width=4
+CSET tstrb_width=4
+CSET tuser_width=4
+CSET underflow_flag=false
+CSET underflow_flag_axi=false
+CSET underflow_sense=Active_High
+CSET underflow_sense_axi=Active_High
+CSET use_clock_enable=false
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET wach_type=FIFO
+CSET wdch_type=FIFO
+CSET wrch_type=FIFO
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=15
+CSET wuser_width=1
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2011-10-22T06:08:52Z
+# END Extra information
+GENERATE
+# CRC: 9008abaa
diff --git a/firmware/minitlu/scripts/FmcTluI2c.py b/firmware/minitlu/scripts/FmcTluI2c.py
new file mode 100644
index 0000000000000000000000000000000000000000..64f7ff5b53dbda2ec5a0fb4c471dc4d9cc643e8c
--- /dev/null
+++ b/firmware/minitlu/scripts/FmcTluI2c.py
@@ -0,0 +1,136 @@
+import time
+from PyChipsUser import *
+from I2cBusProperties import *
+from RawI2cAccess import *
+
+
+class FmcTluI2c:
+
+
+ ############################
+ ### configure i2c connection
+ ############################
+ def __init__(self,board):
+ self.board = board
+ i2cClockPrescale = 0x30
+ self.i2cBusProps = I2cBusProperties(self.board, i2cClockPrescale)
+ return
+
+
+ ##########################
+ ### scan all i2c addresses
+ ##########################
+ def i2c_scan(self):
+ list=[]
+ for islave in range(128):
+ i2cscan = RawI2cAccess(self.i2cBusProps, islave)
+ try:
+ i2cscan.write([0x00])
+ device="slave address "+hex(islave)+" "
+ if islave==0x1f:
+ device+="(DAC)"
+ elif islave==0x50:
+ device+="(serial number PROM)"
+ elif islave>=0x54 and islave<=0x57:
+ device+="(sp601 onboard EEPROM)"
+ else:
+ device+="(???)"
+ pass
+ list.append(device)
+ pass
+ except:
+ pass
+ pass
+ return list
+
+
+ ###################
+ ### write to EEPROM
+ ###################
+ def eeprom_write(self,address,value):
+ if address<0 or address>127:
+ print "eeprom_write ERROR: address",address,"not in range 0-127"
+ return
+ if value<0 or value>255:
+ print "eeprom_write ERROR: value",value,"not in range 0-255"
+ return
+ i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
+ prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+ prom.write([address,value])
+ time.sleep(0.01) # write cycle time is 5ms. let's wait 10 to make sure.
+ return
+
+
+ ####################
+ ### read from EEPROM
+ ####################
+ def eeprom_read(self,address):
+ if address<0 or address>255:
+ print "eeprom_write ERROR: address",address,"not in range 0-127"
+ return
+ i2cSlaveAddr = 0x50 # seven bit address, binary 1010000
+ prom = RawI2cAccess(self.i2cBusProps, i2cSlaveAddr)
+ prom.write([address])
+ return prom.read(1)[0]
+
+
+ ######################
+ ### read serial number
+ ######################
+ def get_serial_number(self):
+ result=""
+ for iaddr in [0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff]:
+ result+="%02x "%(self.eeprom_read(iaddr))
+ pass
+ return result
+
+
+ #################
+ ### set DAC value
+ #################
+ def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
+ if channel<0 or channel>7:
+ print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
+ return -1
+ if value<0 or value>0xFFFF:
+ print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
+ return -1
+ # AD5665R chip with A0,A1 tied to ground
+ #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
+ print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
+ dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
+ # if we want to enable internal voltage reference:
+ if vrefOn:
+ # enter vref-on mode:
+ print "Turning internal reference ON"
+ dac.write([0x38,0x00,0x01])
+ else:
+ print "Turning internal reference OFF"
+ dac.write([0x38,0x00,0x00])
+ # now set the actual value
+ sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
+ print sequence
+ dac.write(sequence)
+
+
+
+ ##################################################
+ ### convert required threshold voltage to DAC code
+ ##################################################
+ def convert_voltage_to_dac(self,desiredVoltage, Vref=1.300):
+ Vdaq = ( desiredVoltage + Vref ) / 2
+ dacCode = 0xFFFF * Vdaq / Vref
+ return int(dacCode)
+
+
+ ##################################################
+ ### calculate the DAC code required and set DAC
+ ##################################################
+ def set_threshold_voltage(self, channel , voltage ):
+ dacCode = self.convert_voltage_to_dac(voltage)
+ print " requested voltage, calculated DAC code = " , voltage , dacCode
+ self.set_dac(channel , dacCode)
+
+
+
+
diff --git a/firmware/minitlu/scripts/I2cBusProperties.py b/firmware/minitlu/scripts/I2cBusProperties.py
new file mode 100644
index 0000000000000000000000000000000000000000..7b3fbfe651d18ca6abe65606be0bd28aa6b8c9ef
--- /dev/null
+++ b/firmware/minitlu/scripts/I2cBusProperties.py
@@ -0,0 +1,122 @@
+##########################################################
+# I2cBusProperties - simple encapsulation of all items
+# required to control an I2C bus.
+#
+# Carl Jeske, July 2010
+# Refactored by Robert Frazier, May 2011
+##########################################################
+
+
+class I2cBusProperties(object):
+ """Encapsulates details of an I2C bus master in the form of a host device, a clock prescale value, and seven I2C master registers
+
+ Provide the ChipsBus instance to the device hosting your I2C core, a 16-bit clock prescaling
+ value for the Serial Clock Line (see I2C core docs for details), and the names of the seven
+ registers that define/control the bus (assuming these names are not the defaults specified
+ in the constructor below). The seven registers consist of the two clock pre-scaling
+ registers (PRElo, PREhi), and five bus master registers (CONTROL, TRANSMIT, RECEIVE,
+ COMMAND and STATUS).
+
+ Usage: You'll need to create an instance of this class to give to a concrete I2C bus instance, such
+ as OpenCoresI2cBus. This I2cBusProperties class is simply a container to hold the properties
+ that define the bus; a class such as OpenCoresI2cBus will make use of these properties.
+
+ Access the items stored by this class via these (deliberately compact) variable names:
+
+ chipsBus -- the ChipsBus device hosting the I2C core
+ preHiVal -- the top byte of the clock prescale value
+ preLoVal -- the bottom byte of the clock prescale value
+ preHiReg -- the register the top byte of the clk prescale value (preHiVal) gets written to
+ preLoReg -- the register the bottom byte of the clk prescale value (preLoVal) gets written to
+ ctrlReg -- the I2C Control register
+ txReg -- the I2C Transmit register
+ rxReg -- the I2C Receive register
+ cmdReg -- the I2C Command register
+ statusReg -- the I2C Status register
+
+
+ Compatibility Notes: The seven register names are the registers typically required to operate an
+ OpenCores or similar I2C Master (Lattice Semiconductor's I2C bus master works
+ the same way as the OpenCores one). This software is not compatible with your
+ I2C bus master if it doesn't use this register interface.
+ """
+
+ def __init__(self,
+ chipsBusDevice,
+ clkPrescaleU16,
+ clkPrescaleLoByteReg = "i2c_pre_lo",
+ clkPrescaleHiByteReg = "i2c_pre_hi",
+ controlReg = "i2c_ctrl",
+ transmitReg = "i2c_tx",
+ receiveReg = "i2c_rx",
+ commandReg = "i2c_cmd",
+ statusReg = "i2c_status"):
+
+ """Provide a host ChipsBus device that is controlling the I2C bus, and the names of five I2C control registers.
+
+ chipsBusDevice: Provide a ChipsBus instance to the device where the I2C bus is being
+ controlled. The address table for this device must contain the five registers
+ that control the bus, as declared next...
+
+ clkPrescaleU16: A 16-bit value used to prescale the Serial Clock Line based on the host
+ master-clock. This value gets split into two 8-bit values and ultimately will
+ get written to the two I2C clock-prescale registers as declared below. See
+ the OpenCores or Lattice Semiconductor I2C documentation for more details.
+
+ clkPrescaleLoByteReg: The register where the lower byte of the clock prescale value is set. The default
+ name for this register is "i2c_pre_lo".
+
+ clkPrescaleHiByteReg: The register where the higher byte of the clock prescale value is set. The default
+ name for this register is "i2c_pre_hi"
+
+ controlReg: The CONTROL register, used for enabling/disabling the I2C core, etc. This register is
+ usually read and write accessible. The default name for this register is "i2c_ctrl".
+
+ transmitReg: The TRANSMIT register, used for holding the data to be transmitted via I2C, etc. This
+ typically shares the same address as the RECEIVE register, but has write-only access. The default
+ name for this register is "i2c_tx".
+
+ receiveReg: The RECEIVE register - allows access to the byte received over the I2C bus. This
+ typically shares the same address as the TRANSMIT register, but has read-only access. The
+ default name for this register is "i2c_rx".
+
+ commandReg: The COMMAND register - stores the command for the next I2C operation. This typically
+ shares the same address as the STATUS register, but has write-only access. The default name for
+ this register is "i2c_cmd".
+
+ statusReg: The STATUS register - allows monitoring of the I2C operations. This typically shares
+ the same address as the COMMAND register, but has read-only access. The default name for this
+ register is "i2c_status".
+ """
+
+ object.__init__(self)
+ self.chipsBus = chipsBusDevice
+ self.preHiVal = ((clkPrescaleU16 & 0xff00) >> 8)
+ self.preLoVal = (clkPrescaleU16 & 0xff)
+
+ # Check to see all the registers are in the address table
+ registers = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, receiveReg, commandReg, statusReg]
+ for reg in registers:
+ if not self.chipsBus.addrTable.checkItem(reg):
+ raise ChipsException("I2cBusProperties error: register '" + reg + "' is not present in the address table of the device hosting the I2C bus master!")
+
+ # Check that the registers we'll need to write to are indeed writable
+ writableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, transmitReg, commandReg]
+ for wReg in writableRegisters:
+ if not self.chipsBus.addrTable.getItem(wReg).getWriteFlag():
+ raise ChipsException("I2cBusProperties error: register '" + wReg + "' does not have the necessary write permission!")
+
+ # Check that the registers we'll need to read from are indeed readable
+ readableRegisters = [clkPrescaleLoByteReg, clkPrescaleHiByteReg, controlReg, receiveReg, statusReg]
+ for rReg in readableRegisters:
+ if not self.chipsBus.addrTable.getItem(rReg).getReadFlag():
+ raise ChipsException("I2cBusProperties error: register '" + rReg + "' does not have the necessary read permission!")
+
+ # Store the various register name strings
+ self.preHiReg = clkPrescaleHiByteReg
+ self.preLoReg = clkPrescaleLoByteReg
+ self.ctrlReg = controlReg
+ self.txReg = transmitReg
+ self.rxReg = receiveReg
+ self.cmdReg = commandReg
+ self.statusReg = statusReg
diff --git a/firmware/minitlu/scripts/RawI2cAccess.py b/firmware/minitlu/scripts/RawI2cAccess.py
new file mode 100644
index 0000000000000000000000000000000000000000..7e3252bb4e9793aa1d297b61034bba2e4742fe2a
--- /dev/null
+++ b/firmware/minitlu/scripts/RawI2cAccess.py
@@ -0,0 +1,260 @@
+# Created on Sep 10, 2012
+# @author: Kristian Harder, based on code by Carl Jeske
+
+from I2cBusProperties import I2cBusProperties
+from ChipsBus import ChipsBus
+from ChipsLog import chipsLog
+from ChipsException import ChipsException
+
+
+class RawI2cAccess:
+
+ def __init__(self, i2cBusProps, slaveAddr):
+
+ # For performing read/writes over an OpenCores-compatible I2C bus master
+ #
+ # An instance of this class is required to communicate with each
+ # I2C slave on the I2C bus.
+ #
+ # i2cBusProps: an instance of the class I2cBusProperties that contains
+ # the relevant ChipsBus host and the I2C bus-master registers (if
+ # they differ from the defaults specified by the I2cBusProperties
+ # class).
+ #
+ #slaveAddr: The address of the I2C slave you wish to communicate with.
+ #
+
+ self._i2cProps = i2cBusProps # The I2C Bus Properties
+ self._slaveAddr = 0x7f & slaveAddr # 7-bit slave address
+
+
+ def resetI2cBus(self):
+
+ # Resets the I2C bus
+ #
+ # This function does the following:
+ # 1) Disables the I2C core
+ # 2) Sets the clock prescale registers
+ # 3) Enables the I2C core
+ # 4) Sets all writable bus-master registers to default values
+
+ try:
+ self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x00)
+ self._chipsBus().queueWrite(self._i2cProps.preHiReg,
+ self._i2cProps.preHiVal)
+ self._chipsBus().queueWrite(self._i2cProps.preLoReg,
+ self._i2cProps.preLoVal)
+ self._chipsBus().queueWrite(self._i2cProps.ctrlReg, 0x80)
+ self._chipsBus().queueWrite(self._i2cProps.txReg, 0x00)
+ self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x00)
+ self._chipsBus().queueRun()
+ except ChipsException, err:
+ raise ChipsException("I2C reset error:\n\t" + str(err))
+
+
+ def read(self, numBytes):
+
+ # Performs an I2C read. Returns the 8-bit read result(s).
+ #
+ # numBytes: number of bytes expected as response
+ #
+
+ try:
+ result = self._privateRead(numBytes)
+ except ChipsException, err:
+ raise ChipsException("I2C read error:\n\t" + str(err))
+ return result
+
+
+ def write(self, listDataU8):
+
+ # Performs an 8-bit I2C write.
+ #
+ # listDataU8: The 8-bit data values to be written.
+ #
+
+ try:
+ self._privateWrite(listDataU8)
+ except ChipsException, err:
+ raise ChipsException("I2C write error:\n\t" + str(err))
+ return
+
+
+ def _chipsBus(self):
+
+ # Returns the instance of the ChipsBus device that's hosting
+ # the I2C bus master
+
+ return self._i2cProps.chipsBus
+
+
+ def _privateRead(self, numBytes):
+
+ # I2C read implementation.
+ #
+ # Fast I2C read implementation,
+ # i.e. done with the fewest packets possible.
+
+
+ # transmit reg definitions
+ # bits 7-1: 7-bit slave address during address transfer
+ # or first 7 bits of byte during data transfer
+ # bit 0: RW flag during address transfer or LSB during data transfer.
+ # '1' = reading from slave
+ # '0' = writing to slave
+
+ # command reg definitions
+ # bit 7: Generate start condition
+ # bit 6: Generate stop condition
+ # bit 5: Read from slave
+ # bit 4: Write to slave
+ # bit 3: 0 when acknowledgement is received
+ # bit 2:1: Reserved
+ # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
+
+ # Reset bus before beginning
+ self.resetI2cBus()
+
+ # Set slave address in bits 7:1, and set bit 0 to zero
+ # (i.e. we're writing an address to the bus)
+ self._chipsBus().queueWrite(self._i2cProps.txReg,
+ (self._slaveAddr << 1) | 0x01)
+ # Set start and write bit in command reg
+ self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+ # Run the queue
+ self._chipsBus().queueRun()
+ # Wait for transaction to finish.
+ self._i2cWaitUntilFinished()
+
+ result=[]
+ for ibyte in range(numBytes):
+ if ibyte==numBytes-1:
+ stop_bit=0x40
+ ack_bit=0x08
+ else:
+ stop_bit=0
+ ack_bit=0
+ pass
+ # Set read bit, acknowledge and stop bit in command reg
+ self._chipsBus().write(self._i2cProps.cmdReg, 0x20+ack_bit+stop_bit)
+ # Wait for transaction to finish.
+ # Don't expect an ACK, do expect bus free at finish.
+ if stop_bit:
+ self._i2cWaitUntilFinished(requireAcknowledgement = False,
+ requireBusIdleAtEnd = True)
+ else:
+ self._i2cWaitUntilFinished(requireAcknowledgement = False,
+ requireBusIdleAtEnd = False)
+ pass
+ result.append(self._chipsBus().read(self._i2cProps.rxReg))
+
+ return result
+
+
+ def _privateWrite(self, listDataU8):
+
+ # I2C write implementation.
+ #
+ # Fast I2C write implementation,
+ # i.e. done with the fewest packets possible.
+
+ # transmit reg definitions
+ # bits 7-1: 7-bit slave address during address transfer
+ # or first 7 bits of byte during data transfer
+ # bit 0: RW flag during address transfer or LSB during data transfer.
+ # '1' = reading from slave
+ # '0' = writing to slave
+
+ # command reg definitions
+ # bit 7: Generate start condition
+ # bit 6: Generate stop condition
+ # bit 5: Read from slave
+ # bit 4: Write to slave
+ # bit 3: 0 when acknowledgement is received
+ # bit 2:1: Reserved
+ # bit 0: Interrupt acknowledge. When set, clears a pending interrupt
+ # Reset bus before beginning
+ self.resetI2cBus()
+
+ # Set slave address in bits 7:1, and set bit 0 to zero (i.e. "write mode")
+ self._chipsBus().queueWrite(self._i2cProps.txReg,
+ (self._slaveAddr << 1) & 0xfe)
+ # Set start and write bit in command reg
+ self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x90)
+ # Run the queue
+ self._chipsBus().queueRun()
+ # Wait for transaction to finish.
+ self._i2cWaitUntilFinished()
+
+ for ibyte in range(len(listDataU8)):
+ dataU8 = listDataU8[ibyte]
+ if ibyte==len(listDataU8)-1:
+ stop_bit=0x40
+ else:
+ stop_bit=0x00
+ pass
+ # Set data to be written in transmit reg
+ self._chipsBus().queueWrite(self._i2cProps.txReg, (dataU8 & 0xff))
+ # Set write and stop bit in command reg
+ self._chipsBus().queueWrite(self._i2cProps.cmdReg, 0x10+stop_bit)
+ # Run the queue
+ self._chipsBus().queueRun()
+ # Wait for transaction to finish.
+ # Do expect an ACK and do expect bus to be free at finish
+ if stop_bit:
+ self._i2cWaitUntilFinished(requireAcknowledgement = True,
+ requireBusIdleAtEnd = True)
+ else:
+ self._i2cWaitUntilFinished(requireAcknowledgement = True,
+ requireBusIdleAtEnd = False)
+ pass
+ pass
+
+ return
+
+
+ def _i2cWaitUntilFinished(self, requireAcknowledgement = True,
+ requireBusIdleAtEnd = False):
+
+ # Ensures the current bus transaction has finished successfully
+ # before allowing further I2C bus transactions
+
+ # This method monitors the status register
+ # and will not allow execution to continue until the
+ # I2C bus has completed properly. It will throw an exception
+ # if it picks up bus problems or a bus timeout occurs.
+
+ maxRetry = 20
+ attempt = 1
+ while attempt <= maxRetry:
+
+ # Get the status
+ i2c_status = self._chipsBus().read(self._i2cProps.statusReg)
+
+ receivedAcknowledge = not bool(i2c_status & 0x80)
+ busy = bool(i2c_status & 0x40)
+ arbitrationLost = bool(i2c_status & 0x20)
+ transferInProgress = bool(i2c_status & 0x02)
+ interruptFlag = bool(i2c_status & 0x01)
+
+ if arbitrationLost: # This is an instant error at any time
+ raise ChipsException("I2C error: Arbitration lost!")
+
+ if not transferInProgress:
+ break # The transfer looks to have completed successfully, pending further checks
+
+ attempt += 1
+
+ # At this point, we've either had too many retries, or the
+ # Transfer in Progress (TIP) bit went low. If the TIP bit
+ # did go low, then we do a couple of other checks to see if
+ # the bus operated as expected:
+
+ if attempt > maxRetry:
+ raise ChipsException("I2C error: Transaction timeout - the 'Transfer in Progress' bit remained high for too long!")
+
+ if requireAcknowledgement and not receivedAcknowledge:
+ raise ChipsException("I2C error: No acknowledge received!")
+
+ if requireBusIdleAtEnd and busy:
+ raise ChipsException("I2C error: Transfer finished but bus still busy!")
diff --git a/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt b/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9df10ffaa8475dd49f9641cfc7dc229b5d109c11
--- /dev/null
+++ b/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt
@@ -0,0 +1,88 @@
+*RegName RegAddr RegMask R W
+*-------------------------------------------------------------
+FirmwareId 0x00000000 0xffffffff 1 0
+* DUT interfaces base = 0x020
+DUTMaskW 0x00000020 0xffffffff 0 1
+DUTMaskR 0x00000021 0xffffffff 1 0
+*
+* trigger inputs = 0x040
+SerdesRstW 0x00000040 0xffffffff 0 1
+SerdesRstR 0x00000048 0xffffffff 1 0
+ThrCount0R 0x00000049 0xffffffff 1 0
+ThrCount1R 0x0000004a 0xffffffff 1 0
+ThrCount2R 0x0000004b 0xffffffff 1 0
+ThrCount3R 0x0000004c 0xffffffff 1 0
+*
+* trigger logic = 0x060 **Note the different read and write directions
+InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
+TriggerMaskW 0x00000063 0xffffffff 1 1
+TriggerVetoW 0x00000064 0xffffffff 1 1
+ResetCountersW 0x00000066 0xffffffff 0 1
+PostVetoTriggersR 0x00000068 0xffffffff 1 0
+PreVetoTriggersR 0x00000069 0xffffffff 1 0
+InternalTriggerIntervalR 0x0000006a 0xffffffff 1 1
+TriggerMaskR 0x0000006b 0xffffffff 1 1
+TriggerVetoR 0x0000006c 0xffffffff 1 1
+ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
+*
+* event buffer = 0x080
+EventFifoData 0x00000080 0xffffffff 1 0
+EventFifoFillLevel 0x00000081 0xffffffff 1 0
+EventFifoCSR 0x00000082 0xffffffff 1 1
+EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
+*
+* logic clocks = 0x0A0
+LogicClocksCSR 0x000000A0 0xffffffff 1 1
+LogicRst 0x000000A1 0xffffffff 0 1
+*
+* I2C = 0x0C0
+i2c_pre_lo 0x000000C0 0x000000ff 1 1
+i2c_pre_hi 0x000000C1 0x000000ff 1 1
+i2c_ctrl 0x000000C2 0x000000ff 1 1
+i2c_tx 0x000000C3 0x000000ff 0 1
+i2c_rx 0x000000C3 0x000000ff 1 0
+i2c_cmd 0x000000C4 0x000000ff 0 1
+i2c_status 0x000000C4 0x000000ff 1 0
+*
+* trigger generator = 0x0E0
+TriggerLength 0x000000E0 0xffffffff 1 1
+TrigStartupDeadTime 0x000000E1 0xffffffff 1 1
+TrigInterpulseDeadTime 0x000000E2 0xffffffff 1 1
+TriggerDelay 0x000000E3 0xffffffff 1 1
+NMaxTriggers 0x000000E4 0xffffffff 1 1
+TrigEvtNumber 0x000000E5 0xffffffff 1 0
+RstTriggerCounter 0x000000E6 0xffffffff 1 1
+TrigRearmDeadTime 0x000000E7 0xffffffff 1 1
+*
+* shutter generator = 0x100
+ShutterLength 0x00000100 0xffffffff 1 1
+ShutStartupDeadTime 0x00000101 0xffffffff 1 1
+ShutInterpulseDeadTime 0x00000102 0xffffffff 1 1
+ShutterDelay 0x00000103 0xffffffff 1 1
+NMaxShutters 0x00000104 0xffffffff 1 1
+ShutEvtNumber 0x00000105 0xffffffff 1 0
+RstShutterCounter 0x00000106 0xffffffff 1 1
+ShutRearmDeadTime 0x00000107 0xffffffff 1 1
+*
+* spill generator = 0x120
+SpillLength 0x00000120 0xffffffff 1 1
+SpillStartupDeadTime 0x00000121 0xffffffff 1 1
+SpillInterpulseDeadTime 0x00000122 0xffffffff 1 1
+SpillDelay 0x00000123 0xffffffff 1 1
+NMaxSpills 0x00000124 0xffffffff 1 1
+SpillEvtNumber 0x00000125 0xffffffff 1 0
+RstSpillCounter 0x00000126 0xffffffff 1 1
+SpillRearmDeadTime 0x00000127 0xffffffff 1 1
+*
+* Event formatter = 0x140
+Enable_Record_Data 0x00000140 0xffffffff 1 1
+*
+* Handshakes = 0x160
+HandshakeTypeW 0x00000160 0xffffffff 0 1
+HandshakeConfW 0x00000161 0xffffffff 0 1
+TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
+HandshakeTypeR 0x00000168 0xffffffff 1 0
+HandshakeConfR 0x00000169 0xffffffff 1 0
+TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
+TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
+
diff --git a/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt~ b/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt~
new file mode 100644
index 0000000000000000000000000000000000000000..45d646d195d977c53fb30726ce3b530894a1aaf6
--- /dev/null
+++ b/firmware/minitlu/scripts/aida_mini_tlu_addr_map.txt~
@@ -0,0 +1,87 @@
+*RegName RegAddr RegMask R W
+*-------------------------------------------------------------
+FirmwareId 0x00000000 0xffffffff 1 0
+* DUT interfaces base = 0x020
+DUTMaskW 0x00000020 0xffffffff 0 1
+DUTMaskR 0x00000020 0xffffffff 1 0
+*
+* trigger inputs = 0x040
+SerdesRst 0x00000040 0xffffffff 1 1
+ThrCount0 0x00000041 0xffffffff 1 0
+ThrCount1 0x00000042 0xffffffff 1 0
+ThrCount2 0x00000043 0xffffffff 1 0
+ThrCount3 0x00000044 0xffffffff 1 0
+*
+* trigger logic = 0x060 **Note the different read and write directions
+InternalTriggerIntervalW 0x00000062 0xffffffff 1 1
+TriggerMaskW 0x00000063 0xffffffff 1 1
+TriggerVetoW 0x00000064 0xffffffff 1 1
+ResetCountersW 0x00000066 0xffffffff 0 1
+PostVetoTriggersR 0x00000068 0xffffffff 1 0
+PreVetoTriggersR 0x00000069 0xffffffff 1 0
+InternalTriggerIntervalR 0x0000006a 0xffffffff 1 1
+TriggerMaskR 0x0000006b 0xffffffff 1 1
+TriggerVetoR 0x0000006c 0xffffffff 1 1
+ExternalTriggerVetoR 0x0000006d 0xffffffff 1 0
+*
+* event buffer = 0x080
+EventFifoData 0x00000080 0xffffffff 1 0
+EventFifoFillLevel 0x00000081 0xffffffff 1 0
+EventFifoCSR 0x00000082 0xffffffff 1 1
+EventFifoFillLevelFlags 0x00000082 0xffffffff 1 0
+*
+* logic clocks = 0x0A0
+LogicClocksCSR 0x000000A0 0xffffffff 1 1
+LogicRst 0x000000A1 0xffffffff 0 1
+*
+* I2C = 0x0C0
+i2c_pre_lo 0x000000C0 0x000000ff 1 1
+i2c_pre_hi 0x000000C1 0x000000ff 1 1
+i2c_ctrl 0x000000C2 0x000000ff 1 1
+i2c_tx 0x000000C3 0x000000ff 0 1
+i2c_rx 0x000000C3 0x000000ff 1 0
+i2c_cmd 0x000000C4 0x000000ff 0 1
+i2c_status 0x000000C4 0x000000ff 1 0
+*
+* trigger generator = 0x0E0
+TriggerLength 0x000000E0 0xffffffff 1 1
+TrigStartupDeadTime 0x000000E1 0xffffffff 1 1
+TrigInterpulseDeadTime 0x000000E2 0xffffffff 1 1
+TriggerDelay 0x000000E3 0xffffffff 1 1
+NMaxTriggers 0x000000E4 0xffffffff 1 1
+TrigEvtNumber 0x000000E5 0xffffffff 1 0
+RstTriggerCounter 0x000000E6 0xffffffff 1 1
+TrigRearmDeadTime 0x000000E7 0xffffffff 1 1
+*
+* shutter generator = 0x100
+ShutterLength 0x00000100 0xffffffff 1 1
+ShutStartupDeadTime 0x00000101 0xffffffff 1 1
+ShutInterpulseDeadTime 0x00000102 0xffffffff 1 1
+ShutterDelay 0x00000103 0xffffffff 1 1
+NMaxShutters 0x00000104 0xffffffff 1 1
+ShutEvtNumber 0x00000105 0xffffffff 1 0
+RstShutterCounter 0x00000106 0xffffffff 1 1
+ShutRearmDeadTime 0x00000107 0xffffffff 1 1
+*
+* spill generator = 0x120
+SpillLength 0x00000120 0xffffffff 1 1
+SpillStartupDeadTime 0x00000121 0xffffffff 1 1
+SpillInterpulseDeadTime 0x00000122 0xffffffff 1 1
+SpillDelay 0x00000123 0xffffffff 1 1
+NMaxSpills 0x00000124 0xffffffff 1 1
+SpillEvtNumber 0x00000125 0xffffffff 1 0
+RstSpillCounter 0x00000126 0xffffffff 1 1
+SpillRearmDeadTime 0x00000127 0xffffffff 1 1
+*
+* Event formatter = 0x140
+Enable_Record_Data 0x00000140 0xffffffff 1 1
+*
+* Handshakes = 0x160
+HandshakeTypeW 0x00000160 0xffffffff 0 1
+HandshakeConfW 0x00000161 0xffffffff 0 1
+TPx3_T0SyncLenW 0x00000162 0xffffffff 0 1
+HandshakeTypeR 0x00000168 0xffffffff 1 0
+HandshakeConfR 0x00000169 0xffffffff 1 0
+TPx3_T0SyncLenR 0x0000016a 0xffffffff 1 0
+TPx3_ShDTimeLenR 0x0000016b 0xffffffff 1 0
+
diff --git a/firmware/minitlu/scripts/build_bitstream.sh b/firmware/minitlu/scripts/build_bitstream.sh
new file mode 100644
index 0000000000000000000000000000000000000000..a06a8f0b8e1f32072c8e3831c74a41ae66cd4e00
--- /dev/null
+++ b/firmware/minitlu/scripts/build_bitstream.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+#
+# Script to build firmware for FMC-based AIDA mini-TLU
+#
+# This script builds the bitstream using ISE and the ISE project generated
+# by setup_workspace.sh
+#
+# cd to the working directory and execute this script....
+#
+# David Cussans, December 2013
+#
+
+export BOARD_TYPE=sp605
+export ISE_VER=ise14
+
+export FW_WORKSPACE=`pwd`
+echo "Workspace directory = " ${FW_WORKSPACE}/workspace
+TLUDir=`pwd`/fmc-mtlu
+echo "Directory with TLU source files = ${TLUDir}"
+
+pushd $FW_WORKSPACE/workspace
+
+xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/build_bitstream.tcl
+
+echo "Bitstream built in ${FW_WORKSPACE}/workspace"
+
+popd
diff --git a/firmware/minitlu/scripts/fmc_tlu_addr_table b/firmware/minitlu/scripts/fmc_tlu_addr_table
new file mode 100644
index 0000000000000000000000000000000000000000..eb8db2e39c3d01c82fd20cbe1fde45ac7fa3fc0c
--- /dev/null
+++ b/firmware/minitlu/scripts/fmc_tlu_addr_table
@@ -0,0 +1,15 @@
+# Example addr_table file to show the format
+#
+# num name base addr_width
+0 DUTInterfaces 0x020 5
+1 triggerInputs 0x040 5
+2 triggerLogic 0x060 5
+3 eventBuffer 0x080 5
+4 logic_clocks 0x0A0 5
+5 i2c_master 0x0C0 3
+6 Trigger_Generator 0x0E0 5
+7 Shutter_Generator 0x100 5
+8 Spill_Generator 0x120 5
+9 Event_Formatter 0x140 5
+10 Handshakes 0x160 5
+11 version 0x000 0
diff --git a/firmware/minitlu/scripts/generate_arrivaltime_lut.py b/firmware/minitlu/scripts/generate_arrivaltime_lut.py
new file mode 100644
index 0000000000000000000000000000000000000000..21127cb123ca0892d916f27cbfb6809931ea3ffe
--- /dev/null
+++ b/firmware/minitlu/scripts/generate_arrivaltime_lut.py
@@ -0,0 +1,109 @@
+
+# Look for rising and falling edges in 8-bit vector.
+# Print out in form suitable for initializing VHDL array...
+
+# from bitstring import BitArray
+
+
+firstRisingEdge = []
+lastFallingEdge = []
+multipleEdgesPresent = []
+risingEdgePresent = []
+fallingEdgePresent = []
+
+for value in range(0,512):
+ print hex(value)
+
+ # Initialize array and get zero'th element
+ bitSetArray = []
+ bitSet = ( 1 & value)
+ bitSetArray.append(bitSet)
+
+ risingEdges = []
+ fallingEdges = []
+
+ for bit in range (1,9):
+ bitSet = (( 1 << bit ) & value) >> bit
+ # print bitSet
+ bitSetArray.append(bitSet)
+ if (bitSetArray[bit-1] ==0) and (bitSetArray[bit] == 1):
+ print "Rising edge found"
+ risingEdges.append(bit)
+ if (bitSetArray[bit-1] ==1) and (bitSetArray[bit] == 0):
+ print "Falling edge found"
+ fallingEdges.append(bit)
+
+ if len(risingEdges) != 0:
+ firstRisingEdge.append(risingEdges[0] - 1)
+ risingEdgePresent.append(1)
+ else:
+ firstRisingEdge.append(0)
+ risingEdgePresent.append(0)
+
+ if len(fallingEdges) != 0:
+ lastFallingEdge.append(fallingEdges[len(fallingEdges)-1] -1 )
+ fallingEdgePresent.append(1)
+ else:
+ lastFallingEdge.append(0)
+ fallingEdgePresent.append(0)
+
+ if (len(risingEdges) >1 ) or (len(risingEdges) >1 ):
+ multipleEdgesPresent.append(1)
+ else:
+ multipleEdgesPresent.append(0)
+
+
+ print bitSetArray , risingEdges , fallingEdges
+
+print firstRisingEdge
+print risingEdgePresent
+
+print
+
+print lastFallingEdge
+print fallingEdgePresent
+
+print
+
+print multipleEdgesPresent
+
+# Rising and falling edge times encoded as a LUT. Contents:
+# MRFrrrfff
+# M = multiple edges present ( more then one rising or falling edge)
+# R = at least one rising edge present
+# F = at least one falling edge present.
+
+for value in range(0,512):
+
+ if not (value % 8):
+ # print newline every eight values.
+ print
+
+ word = lastFallingEdge[value] + (firstRisingEdge[value]<<3) + (fallingEdgePresent[value]<<6) + (risingEdgePresent[value]<<7) + (multipleEdgesPresent[value]<<8)
+
+# print "last falling edge" , hex(lastFallingEdge[value])
+# print "first rising edge" , hex(firstRisingEdge[value])
+# print "multi edges?" , multipleEdgesPresent[value]
+
+ bitString = ""
+
+ for bit in range (0,9):
+ bitSet = (( 1 << bit ) & word) >> bit
+ if bitSet:
+ bitString = "1" + bitString
+ else:
+ bitString = "0" + bitString
+
+# print hex(value)
+# print hex(word)
+ print ("\"" + bitString + "\","),
+
+
+# print
+
+
+# valBits = BitArray(int = value, length = 8)
+# print BitArray
+
+# Find the first rising edge in time and the last falling edge...
+
diff --git a/firmware/minitlu/scripts/make_fmc-mtlu_pintest_ise.tcl b/firmware/minitlu/scripts/make_fmc-mtlu_pintest_ise.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3252e4d0c49490175dbc05721b3d8c325b13488d
--- /dev/null
+++ b/firmware/minitlu/scripts/make_fmc-mtlu_pintest_ise.tcl
@@ -0,0 +1,540 @@
+#
+# Builds a Xilinx ISE project for AIDA FMC miniTLU pin-test firmware
+#
+# Needs to have code checked out into current working directory as fmc-mtlu/firmware
+# Should just be able to work in the "workspace" directory generated by setup_project process...
+#
+# David Cussans, Bristol, Oct 2014
+#
+# Project automation script for fmc-mtlu
+#
+# Created for ISE version 14.7
+#
+# This file contains several Tcl procedures (procs) that you can use to automate
+# your project by running from xtclsh or the Project Navigator Tcl console.
+# If you load this file (using the Tcl command: source fmc-mtlu.tcl), then you can
+# run any of the procs included here.
+#
+# This script is generated assuming your project has HDL sources.
+# Several of the defined procs won't apply to an EDIF or NGC based project.
+# If that is the case, simply remove them from this script.
+#
+# You may also edit any of these procs to customize them. See comments in each
+# proc for more instructions.
+#
+# This file contains the following procedures:
+#
+# Top Level procs (meant to be called directly by the user):
+# run_process: you can use this top-level procedure to run any processes
+# that you choose to by adding and removing comments, or by
+# adding new entries.
+# rebuild_project: you can alternatively use this top-level procedure
+# to recreate your entire project, and the run selected processes.
+#
+# Lower Level (helper) procs (called under in various cases by the top level procs):
+# show_help: print some basic information describing how this script works
+# add_source_files: adds the listed source files to your project.
+# set_project_props: sets the project properties that were in effect when this
+# script was generated.
+# create_libraries: creates and adds file to VHDL libraries that were defined when
+# this script was generated.
+# set_process_props: set the process properties as they were set for your project
+# when this script was generated.
+#
+
+set myProject "fmc-mtlu"
+set myScript "./fmc-mtlu.tcl"
+
+#
+# Main (top-level) routines
+#
+# run_process
+# This procedure is used to run processes on an existing project. You may comment or
+# uncomment lines to control which processes are run. This routine is set up to run
+# the Implement Design and Generate Programming File processes by default. This proc
+# also sets process properties as specified in the "set_process_props" proc. Only
+# those properties which have values different from their current settings in the project
+# file will be modified in the project.
+#
+proc run_process {} {
+
+ global myScript
+ global myProject
+
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: running ($myProject)...\n"
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ set_process_props
+ #
+ # Remove the comment characters (#'s) to enable the following commands
+ # process run "Synthesize"
+ # process run "Translate"
+ # process run "Map"
+ # process run "Place & Route"
+ #
+ set task "Implement Design"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ set task "Generate Programming File"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ puts "Run completed (successfully)."
+ project close
+
+}
+
+#
+# rebuild_project
+#
+# This procedure renames the project file (if it exists) and recreates the project.
+# It then sets project properties and adds project sources as specified by the
+# set_project_props and add_source_files support procs. It recreates VHDL Libraries
+# as they existed at the time this script was generated.
+#
+# It then calls run_process to set process properties and run selected processes.
+#
+proc rebuild_project {} {
+
+ global myScript
+ global myProject
+
+ project close
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: Rebuilding ($myProject)...\n"
+
+ set proj_exts [ list ise xise gise ]
+ foreach ext $proj_exts {
+ set proj_name "${myProject}.$ext"
+ if { [ file exists $proj_name ] } {
+ file delete $proj_name
+ }
+ }
+
+ project new $myProject
+ set_project_props
+ add_source_files
+ create_libraries
+ puts "$myScript: project rebuild completed."
+
+ run_process
+
+}
+
+#
+# Support Routines
+#
+
+#
+proc run_task { task } {
+
+ # helper proc for run_process
+
+ puts "Running '$task'"
+ set result [ process run "$task" ]
+ #
+ # check process status (and result)
+ set status [ process get $task status ]
+ if { ( ( $status != "up_to_date" ) && \
+ ( $status != "warnings" ) ) || \
+ ! $result } {
+ return false
+ }
+ return true
+}
+
+#
+# show_help: print information to help users understand the options available when
+# running this script.
+#
+proc show_help {} {
+
+ global myScript
+
+ puts ""
+ puts "usage: xtclsh $myScript <options>"
+ puts " or you can run xtclsh and then enter 'source $myScript'."
+ puts ""
+ puts "options:"
+ puts " run_process - set properties and run processes."
+ puts " rebuild_project - rebuild the project from scratch and run processes."
+ puts " set_project_props - set project properties (device, speed, etc.)"
+ puts " add_source_files - add source files"
+ puts " create_libraries - create vhdl libraries"
+ puts " set_process_props - set process property values"
+ puts " show_help - print this message"
+ puts ""
+}
+
+proc open_project {} {
+
+ global myScript
+ global myProject
+
+ if { ! [ file exists ${myProject}.xise ] } {
+ ## project file isn't there, rebuild it.
+ puts "Project $myProject not found. Use project_rebuild to recreate it."
+ return false
+ }
+
+ project open $myProject
+
+ return true
+
+}
+#
+# set_project_props
+#
+# This procedure sets the project properties as they were set in the project
+# at the time this script was generated.
+#
+proc set_project_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Setting project properties..."
+
+ project set family "Spartan6"
+ project set device "xc6slx45t"
+ project set package "fgg484"
+ project set speed "-3"
+ project set top_level_module_type "HDL"
+ project set synthesis_tool "XST (VHDL/Verilog)"
+ project set simulator "ISim (VHDL/Verilog)"
+ project set "Preferred Language" "Verilog"
+ project set "Enable Message Filtering" "false"
+
+}
+
+
+#
+# add_source_files
+#
+# This procedure add the source files that were known to the project at the
+# time this script was generated.
+#
+proc add_source_files {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Adding sources to project..."
+
+ xfile add "fmc-mtlu/firmware/hdl/test/comb_generator_rtl.vhd"
+ xfile add "fmc-mtlu/firmware/hdl/test/fmc_tlu_pin_test.vhd"
+ xfile add "fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a_pintest.ucf"
+ xfile add "fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd"
+ xfile add "fmc-mtlu/firmware/hdl/test/clock_divider_s6.v"
+
+ # Set the Top Module as well...
+ project set top "struct" "fmcTlu_pinTest"
+
+ puts "$myScript: project sources reloaded."
+
+} ; # end add_source_files
+
+#
+# create_libraries
+#
+# This procedure defines VHDL libraries and associates files with those libraries.
+# It is expected to be used when recreating the project. Any libraries defined
+# when this script was generated are recreated by this procedure.
+#
+proc create_libraries {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Creating libraries..."
+
+
+ # must close the project or library definitions aren't saved.
+ project save
+
+} ; # end create_libraries
+
+#
+# set_process_props
+#
+# This procedure sets properties as requested during script generation (either
+# all of the properties, or only those modified from their defaults).
+#
+proc set_process_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: setting process properties..."
+
+ project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
+ project set "Global Optimization" "Off" -process "Map"
+ project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
+ project set "Place And Route Mode" "Route Only" -process "Place & Route"
+ project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
+ project set "Filter Files From Compile Order" "true"
+ project set "Last Applied Goal" "Balanced"
+ project set "Last Applied Strategy" "Xilinx Default (unlocked)"
+ project set "Last Unlock Status" "false"
+ project set "Manual Compile Order" "false"
+ project set "Placer Effort Level" "High" -process "Map"
+ project set "Extra Cost Tables" "0" -process "Map"
+ project set "LUT Combining" "Off" -process "Map"
+ project set "Combinatorial Logic Optimization" "false" -process "Map"
+ project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
+ project set "Power Reduction" "Off" -process "Map"
+ project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
+ project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
+ project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
+ project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
+ project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
+ project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
+ project set "Property Specification in Project File" "Store all values"
+ project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
+ project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
+ project set "Case Implementation Style" "None" -process "Synthesize - XST"
+ project set "RAM Extraction" "true" -process "Synthesize - XST"
+ project set "ROM Extraction" "true" -process "Synthesize - XST"
+ project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
+ project set "Optimization Goal" "Speed" -process "Synthesize - XST"
+ project set "Optimization Effort" "Normal" -process "Synthesize - XST"
+ project set "Resource Sharing" "true" -process "Synthesize - XST"
+ project set "Shift Register Extraction" "true" -process "Synthesize - XST"
+ project set "User Browsed Strategy Files" ""
+ project set "VHDL Source Analysis Standard" "VHDL-93"
+ project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
+ project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
+ project set "Input TCL Command Script" "" -process "Generate Text Power Report"
+ project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
+ project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ project set "Load Simulation File" "Default" -process "Generate Text Power Report"
+ project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
+ project set "Load Setting File" "" -process "Generate Text Power Report"
+ project set "Setting Output File" "" -process "Generate Text Power Report"
+ project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
+ project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
+ project set "Essential Bits" "false" -process "Generate Programming File"
+ project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
+ project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
+ project set "Show All Models" "false" -process "Generate IBIS Model"
+ project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
+ project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
+ project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
+ project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
+ project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
+ project set "Ignore User Timing Constraints" "false" -process "Map"
+ project set "Register Ordering" "4" -process "Map"
+ project set "Use RLOC Constraints" "Yes" -process "Map"
+ project set "Other Map Command Line Options" "" -process "Map"
+ project set "Use LOC Constraints" "true" -process "Translate"
+ project set "Other Ngdbuild Command Line Options" "" -process "Translate"
+ project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
+ project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
+ project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
+ project set "Ignore User Timing Constraints" "false" -process "Place & Route"
+ project set "Other Place & Route Command Line Options" "" -process "Place & Route"
+ project set "Use DSP Block" "Auto" -process "Synthesize - XST"
+ project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
+ project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
+ project set "Enable External Master Clock" "false" -process "Generate Programming File"
+ project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
+ project set "Create Bit File" "true" -process "Generate Programming File"
+ project set "Enable BitStream Compression" "false" -process "Generate Programming File"
+ project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
+ project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
+ project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
+ project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
+ project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
+ project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
+ project set "Configuration Rate" "2" -process "Generate Programming File"
+ project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
+ project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
+ project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
+ project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
+ project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
+ project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
+ project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File"
+ project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
+ project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
+ project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
+ project set "Drive Done Pin High" "false" -process "Generate Programming File"
+ project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
+ project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
+ project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
+ project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
+ project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
+ project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
+ project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
+ project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
+ project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
+ project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
+ project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
+ project set "Maximum Compression" "false" -process "Map"
+ project set "Generate Detailed MAP Report" "false" -process "Map"
+ project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
+ project set "Perform Timing-Driven Packing and Placement" "false"
+ project set "Trim Unconnected Signals" "true" -process "Map"
+ project set "Create I/O Pads from Ports" "false" -process "Translate"
+ project set "Macro Search Path" "" -process "Translate"
+ project set "Netlist Translation Type" "Timestamp" -process "Translate"
+ project set "User Rules File for Netlister Launcher" "" -process "Translate"
+ project set "Allow Unexpanded Blocks" "false" -process "Translate"
+ project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
+ project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
+ project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
+ project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
+ project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
+ project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
+ project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
+ project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
+ project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
+ project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
+ project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
+ project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
+ project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
+ project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
+ project set "Add I/O Buffers" "true" -process "Synthesize - XST"
+ project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
+ project set "Keep Hierarchy" "No" -process "Synthesize - XST"
+ project set "Max Fanout" "100000" -process "Synthesize - XST"
+ project set "Register Balancing" "No" -process "Synthesize - XST"
+ project set "Register Duplication" "true" -process "Synthesize - XST"
+ project set "Library for Verilog Sources" "" -process "Synthesize - XST"
+ project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
+ project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
+ project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
+ project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
+ project set "Bus Delimiter" "<>" -process "Synthesize - XST"
+ project set "Case" "Maintain" -process "Synthesize - XST"
+ project set "Cores Search Directories" "" -process "Synthesize - XST"
+ project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
+ project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
+ project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
+ project set "FSM Style" "LUT" -process "Synthesize - XST"
+ project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
+ project set "Generics, Parameters" "" -process "Synthesize - XST"
+ project set "Hierarchy Separator" "/" -process "Synthesize - XST"
+ project set "HDL INI File" "" -process "Synthesize - XST"
+ project set "LUT Combining" "Auto" -process "Synthesize - XST"
+ project set "Library Search Order" "" -process "Synthesize - XST"
+ project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
+ project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
+ project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
+ project set "Power Reduction" "false" -process "Synthesize - XST"
+ project set "Read Cores" "true" -process "Synthesize - XST"
+ project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
+ project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
+ project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
+ project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
+ project set "Verilog Include Directories" "" -process "Synthesize - XST"
+ project set "Verilog Macros" "" -process "Synthesize - XST"
+ project set "Work Directory" "/users/phdgc/IPBus_stuff/fmc_tlu_alvaro_test_oct14/aida_minitlu_pinoutTest/workspace/xst" -process "Synthesize - XST"
+ project set "Write Timing Constraints" "false" -process "Synthesize - XST"
+ project set "Other XST Command Line Options" "" -process "Synthesize - XST"
+ project set "Timing Mode" "Performance Evaluation" -process "Map"
+ project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
+ project set "Generate Clock Region Report" "false" -process "Place & Route"
+ project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
+ project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
+ project set "Power Reduction" "false" -process "Place & Route"
+ project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
+ project set "Auto Implementation Compile Order" "true"
+ project set "Equivalent Register Removal" "true" -process "Map"
+ project set "Placer Extra Effort" "None" -process "Map"
+ project set "Power Activity File" "" -process "Map"
+ project set "Register Duplication" "Off" -process "Map"
+ project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
+ project set "Synthesis Constraints File" "" -process "Synthesize - XST"
+ project set "RAM Style" "Auto" -process "Synthesize - XST"
+ project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
+ project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
+ project set "Output File Name" "fmcTlu_pinTest" -process "Generate IBIS Model"
+ project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
+ project set "Create Binary Configuration File" "false" -process "Generate Programming File"
+ project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
+ project set "Create Logic Allocation File" "false" -process "Generate Programming File"
+ project set "Create Mask File" "false" -process "Generate Programming File"
+ project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
+ project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
+ project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File"
+ project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
+ project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
+ project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
+ project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
+ project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
+ project set "Enable Multi-Threading" "2" -process "Map"
+ project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
+ project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
+ project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
+ project set "ROM Style" "Auto" -process "Synthesize - XST"
+ project set "Safe Implementation" "No" -process "Synthesize - XST"
+ project set "Power Activity File" "" -process "Place & Route"
+ project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
+ project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
+ project set "Encrypt Bitstream" "false" -process "Generate Programming File"
+ project set "Enable Multi-Threading" "2" -process "Place & Route"
+ project set "AES Initial Vector" "" -process "Generate Programming File"
+ project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
+ project set "AES Key (Hex String)" "" -process "Generate Programming File"
+ project set "Input Encryption Key File" "" -process "Generate Programming File"
+ project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
+ project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
+ project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
+
+ puts "$myScript: project property values set."
+
+} ; # end set_process_props
+
+proc main {} {
+
+ if { [llength $::argv] == 0 } {
+ show_help
+ return true
+ }
+
+ foreach option $::argv {
+ switch $option {
+ "show_help" { show_help }
+ "run_process" { run_process }
+ "rebuild_project" { rebuild_project }
+ "set_project_props" { set_project_props }
+ "add_source_files" { add_source_files }
+ "create_libraries" { create_libraries }
+ "set_process_props" { set_process_props }
+ default { puts "unrecognized option: $option"; show_help }
+ }
+ }
+}
+
+if { $tcl_interactive } {
+ show_help
+} else {
+ if {[catch {main} result]} {
+ puts "$myScript failed: $result."
+ }
+}
+
diff --git a/firmware/minitlu/scripts/setup_workspace.sh b/firmware/minitlu/scripts/setup_workspace.sh
new file mode 100644
index 0000000000000000000000000000000000000000..01a6aa4cd91286d938944cdb0778a5cafa16f44b
--- /dev/null
+++ b/firmware/minitlu/scripts/setup_workspace.sh
@@ -0,0 +1,100 @@
+#!/bin/sh
+#
+# Script to build firmware for FMC-based AIDA mini-TLU
+#
+# This script creates an ISE project.
+#
+# Create a working directory and execute this script....
+#
+# Once project has been created either open in ISE or
+# execute the build_bitstream.sh script.
+#
+# David Cussans, December 2013
+#
+
+export FW_WORKSPACE=`pwd`
+echo "Current directory = " $FW_WORKSPACE
+export BOARD_TYPE=sp605
+export ISE_VER=ise14
+export VERSION=trunk
+
+echo "Setting up AIDA mini-TLU code version $VERSION"
+
+# Check out FMC-MTLU code
+TLUDir=`pwd`/fmc-mtlu
+if [ ! -d "$TLUDir" ]; then
+ echo "Checking out AIDA mini-TLU code"
+ mkdir fmc-mtlu
+ pushd fmc-mtlu
+ svn co http://svn.ohwr.org/fmc-mtlu/${VERSION}/firmware
+ popd
+ echo "Checked out FMC-MTLU code"
+fi
+
+# Check out IPBus code
+IPBusDir=`pwd`/IPBus2
+if [ ! -d "$IPBusDir" ]; then
+ mkdir $IPBusDir
+ pushd $IPBusDir
+ svn co http://svn.cern.ch/guest/cactus/tags/ipbus_fw/ipbus_2_0_v1/firmware
+ echo "Checked out IPBus2 code"
+ popd
+fi
+
+# Check out directory for external cores ( e.g. I2C)
+if [ ! -d "external" ]; then
+ echo "Checking out I2C code"
+ svn co http://cactus.hepforge.org/svn/tags/firmware_pre_131_RAL/firmware/external
+fi
+
+# Create a directory contain the build products.
+WorkDir=workspace
+if [ ! -d "$WorkDir" ]; then
+ mkdir workspace
+ mkdir workspace/ipcore_dir
+ echo "Made workspace"
+fi
+
+export REPOS_BUILD_DIR=`pwd`/workspace
+
+pushd workspace
+
+# Create soft links to ipbus, fmc-mtlu code , i2c code
+if [ ! -e "ipbus" ]; then
+ ln -s $IPBusDir ipbus
+fi
+
+if [ ! -e "fmc-mtlu" ]; then
+ ln -s ../fmc-mtlu .
+fi
+
+if [ ! -e "external" ]; then
+ ln -s ../external .
+fi
+
+
+if [ ! -e "file_list" ]; then
+ ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
+fi
+
+if [ ! -e "ipbus" ]; then
+ ln -s ../$IPBusDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
+fi
+
+
+pushd ipcore_dir
+if [ ! -e "coregen.cgp" ]; then
+ ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/coregen.cgp .
+fi
+popd
+
+#export REPOS_FW_DIR=$IPBusDir
+export REPOS_FW_DIR=ipbus
+
+echo "IPBus directory = " $IPBusDir
+echo "FMC-MTLU directry = " $TLUDir
+
+xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/setup_project.tcl
+
+echo "Finished setting up ISE project."
+echo "Open in $ISE_VER and build bit-stream ,or execute build_bitstream.sh"
diff --git a/firmware/minitlu/scripts/test_aida_tlu.py b/firmware/minitlu/scripts/test_aida_tlu.py
new file mode 100644
index 0000000000000000000000000000000000000000..9a4314895915d05dd3c2beaf79a596752a2dcb2a
--- /dev/null
+++ b/firmware/minitlu/scripts/test_aida_tlu.py
@@ -0,0 +1,242 @@
+#
+# Script to exercise AIDA mini-TLU
+#
+# David Cussans, December 2012
+#
+# Modified by Alvaro Dosil, January 2013
+
+from PyChipsUser import *
+from FmcTluI2c import *
+from ROOT import *
+
+import sys
+import time
+
+
+def mean(TS):
+ val=0
+ for i in range(1,len(TS)):
+ val+=TS[i]-TS[i-1]
+ return val/(len(TS)-1)
+
+
+
+bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+# Assume DIP-switch controlled address. Switches at 1
+board = ChipsBusUdp(bAddrTab,"192.168.200.16",50001)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+firmwareID=board.read("FirmwareId")
+firmwareID=board.read("FirmwareId")
+
+print "Firmware = " , hex(firmwareID)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+resetSerdes = 1
+
+# set DACs to -200mV
+print "Setting all threshold DAC to -200mV "
+boardi2c.set_threshold_voltage(7, 1.0)
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+ print "Resetting clocks"
+ board.write("LogicRst", 1 )
+
+ clockStatus = board.read("LogicClocksCSR")
+ print "Clock status after reset = " , hex(clockStatus)
+
+inputStatus = board.read("SerdesRstR")
+print "Input status = " , hex(inputStatus)
+
+if resetSerdes:
+ board.write("SerdesRstW", 0x00000003 )
+ inputStatus = board.read("SerdesRstR")
+ print "Input status during reset = " , hex(inputStatus)
+
+ board.write("SerdesRstW", 0x00000000 )
+ inputStatus = board.read("SerdesRstR")
+ print "Input status after reset = " , hex(inputStatus)
+
+ board.write("SerdesRstW", 0x00000004 )
+ inputStatus = board.read("SerdesRstR")
+ print "Input status during calibration = " , hex(inputStatus)
+
+ board.write("SerdesRstW", 0x00000000 )
+ inputStatus = board.read("SerdesRstR")
+ print "Input status after calibration = " , hex(inputStatus)
+
+# Look at status of input IODELAYs
+numLoops = 5
+
+for iLoop in range(0,numLoops):
+
+ inputStatus = board.read("SerdesRstR")
+ print "Input status = " , hex(inputStatus)
+
+ count0 = board.read("ThrCount0R")
+ print " Count 0 = " , count0
+
+ count1 = board.read("ThrCount1R")
+ print " Count 1 = " , count1
+
+ count2 = board.read("ThrCount2R")
+ print " Count 2 = " , count2
+
+ count3 = board.read("ThrCount3R")
+ print " Count 3 = " , count3
+
+ time.sleep(1.0)
+
+board.write("InternalTriggerIntervalW",0)
+
+print "Enabling DUT 1"
+board.write("DUTMaskW",0)
+board.write("TriggerMaskW",0x0)
+board.write("TriggerVetoW",0)
+print "Trigger inputs enabled: ", board.read("TriggerMaskR")
+
+print "Reseting FIFO"
+board.write("EventFifoCSR",0x2)
+
+print "Enabling to record data"
+board.write("Enable_Record_Data",1)
+
+print "Enabling handshake: No-handshake"
+board.write("HandshakeTypeW",1)
+
+TriggerInterval = 160
+board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
+
+#sys.exit(0)
+
+f=open("data/data.dat",'w')
+
+n=600000 #number of measurements
+data={"EvtType":[],"InputTrig":[],"CoarseTS":[],"FineTS0":[],"FineTS1":[],"FineTS2":[],"FineTS3":[],"EvtNumber":[], "TS":[]}
+read=range(4)
+trigger_old=0
+i=0
+while i<n:
+ PostVetoTrig = board.read("PostVetoTriggersR")
+ if PostVetoTrig!=trigger_old:
+ f.write("word "+str(hex(i))+"\n")
+ for j in range(4):
+ read[j] = board.read("EventFifoData")
+ f.write(str(hex(read[j]))+"\n")
+ trigger_old = PostVetoTrig
+ else: continue
+ data["EvtType"].append(read[0] >> 28)
+ data["InputTrig"].append((read[0]&0xfff0000)>>16)
+ data["CoarseTS"].append(((read[0]&0xffff)<<32) | read[1])
+ data["FineTS0"].append(read[2]>>24)
+ data["FineTS1"].append(read[2]>>16 & 0xff)
+ data["FineTS2"].append(read[2]>>8 & 0xff)
+ data["FineTS3"].append(read[2] & 0xff)
+ data["EvtNumber"].append(read[3])
+ #if read[3]&0x84000000!=0: sys.exit(0)
+
+ if data["InputTrig"][i]==0x800:
+ data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
+ elif data["InputTrig"][i]==0x400:
+ data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS1"][i]>>3)*6.25+(data["FineTS1"][i]&0x7)*0.781)
+ elif data["InputTrig"][i]==0x200:
+ data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS2"][i]>>3)*6.25+(data["FineTS2"][i]&0x7)*0.781)
+ elif data["InputTrig"][i]==0x100:
+ data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS3"][i]>>3)*6.25+(data["FineTS3"][i]&0x7)*0.781)
+ else:
+ data["TS"].append(data["CoarseTS"][i]*25+(data["FineTS0"][i]>>3)*6.25+(data["FineTS0"][i]&0x7)*0.781)
+ #print data["CoarseTS"][i], (data["FineTS0"][i]&0x18)>>3
+ #hFineTS.Fill(data["FineTS0"][i]&0x7)
+ #if i!=0:
+ # print i, data["TS"][i]-data["TS"][i-1], data["EvtNumber"][i]
+ #hTS.Fill(data["TS"][i]-data["TS"][i-1])
+ if TriggerInterval==0 and data["EvtType"][i]==0:
+ print "Error!!! internal trigger detected!"
+ if TriggerInterval!=0 and data["EvtType"][i]!=0:
+ print "Error!!! external trigger detected!",
+ print hex(data["InputTrig"][i]), "EvtNumber:",data["EvtNumber"][i]
+ #time.sleep(.05)
+ #if i%100000==0: board.write("EventFifoCSR",0x2)
+ i+=1
+
+f.close()
+
+meanVal=0
+if len(data["TS"])<500:
+ meanVal=mean(data["TS"])
+else:
+ meanVal=mean(data["TS"][0:500])
+print meanVal
+plotWidth=100
+
+hTS = TH1D("hTS", "hTS", int(plotWidth/0.78), meanVal-plotWidth/2., meanVal+plotWidth/2.)
+hFineTS0 = TH1D("hFineTS0", "hFineTS0", 8, 0, 8)
+hFineTS1 = TH1D("hFineTS1", "hFineTS1", 8, 0, 8)
+hFineTS2 = TH1D("hFineTS2", "hFineTS2", 8, 0, 8)
+hFineTS3 = TH1D("hFineTS3", "hFineTS3", 8, 0, 8)
+h6TS0 = TH1D("h6TS3","h6TS0",4,0,4)
+h6TS1 = TH1D("h6TS3","h6TS1",4,0,4)
+h6TS2 = TH1D("h6TS3","h6TS2",4,0,4)
+h6TS3 = TH1D("h6TS3","h6TS3",4,0,4)
+hEvtNumber = TH1D("hEvtNumber", "hEvtNumber", 11, -1, 10)
+
+hTS.GetXaxis().SetTitle("#Delta Time stamp [ns]")
+hTS.GetYaxis().SetTitle("#events")
+hEvtNumber.GetYaxis().SetTitle("#events")
+
+for i in range(len(data["TS"])):
+ if i!=0:
+ interval=data["TS"][i]-data["TS"][i-1]
+ hTS.Fill(interval)
+ hEvtNumber.Fill(data["EvtNumber"][i]-data["EvtNumber"][i-1])
+
+ hFineTS0.Fill(data["FineTS0"][i]&0x7)
+ hFineTS1.Fill(data["FineTS1"][i]&0x7)
+ hFineTS2.Fill(data["FineTS2"][i]&0x7)
+ hFineTS3.Fill(data["FineTS3"][i]&0x7)
+ h6TS0.Fill(data["FineTS0"][i]>>3)
+ h6TS1.Fill(data["FineTS1"][i]>>3)
+ h6TS2.Fill(data["FineTS2"][i]>>3)
+ h6TS3.Fill(data["FineTS3"][i]>>3)
+
+cPlots = TCanvas("cPlots","cPlots",900,600)
+cPlots.Divide(2)
+cPlots.cd(1)
+hTS.Draw()
+cPlots.cd(2)
+hEvtNumber.Draw()
+
+c6TS = TCanvas("c6TS", "c6TS", 1000,900)
+c6TS.Divide(2,2)
+c6TS.cd(1)
+h6TS0.Draw()
+c6TS.cd(2)
+h6TS1.Draw()
+c6TS.cd(3)
+h6TS2.Draw()
+c6TS.cd(4)
+h6TS3.Draw()
+
+cFineTS = TCanvas("cFineTS","cFineTS",1000,900)
+cFineTS.Divide(2,2)
+cFineTS.cd(1)
+hFineTS0.Draw()
+cFineTS.cd(2)
+hFineTS1.Draw()
+cFineTS.cd(3)
+hFineTS2.Draw()
+cFineTS.cd(4)
+hFineTS3.Draw()
diff --git a/firmware/minitlu/scripts/test_aida_tlu.sh b/firmware/minitlu/scripts/test_aida_tlu.sh
new file mode 100755
index 0000000000000000000000000000000000000000..dca0744c1ecda45ff9e0f4a47cd9705dab29604f
--- /dev/null
+++ b/firmware/minitlu/scripts/test_aida_tlu.sh
@@ -0,0 +1,5 @@
+#!/bin/bash
+#
+export PYTHONPATH=~/PyChips_1_4_3/src
+
+python test_aida_tlu.py
diff --git a/firmware/minitlu/scripts/test_aida_tlu_thresholds.py b/firmware/minitlu/scripts/test_aida_tlu_thresholds.py
new file mode 100644
index 0000000000000000000000000000000000000000..efbc2387c384d665c19034ae0a5757bdc61a7a3a
--- /dev/null
+++ b/firmware/minitlu/scripts/test_aida_tlu_thresholds.py
@@ -0,0 +1,43 @@
+from PyChipsUser import *
+from FmcTluI2c import *
+import time
+
+boardIpAddr = "192.168.200.16"
+boardPortNum = 50001
+
+addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+boardFirmware = board.read("FirmwareId")
+print "Firmware version = " , hex(boardFirmware)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+#dacValue = 0x4100
+#dacValue = 0xFFFF
+#dacValue = 0x0000
+#dacValue = 0x7FFF
+#print "Setting Vthreshold for all DACs. Code = ", dacValue
+#boardi2c.set_dac(7,dacValue)
+
+#time.sleep(2.0)
+
+#dacValue = 0x6000
+#print "Setting Vthreshold for DAC 0. Code = ", dacValue
+#boardi2c.set_dac(0,dacValue)
+
+#time.sleep(2.0)
+
+# set DACs to -100mV
+Vthresh = -0.10
+print "Setting Vthreshold for all DACs. Voltage = " , Vthresh
+boardi2c.set_threshold_voltage(7, Vthresh)
diff --git a/firmware/minitlu/scripts/test_aida_tlu_trig_counter.py b/firmware/minitlu/scripts/test_aida_tlu_trig_counter.py
new file mode 100644
index 0000000000000000000000000000000000000000..35c91e6d81ccdfc25b8879d28d31e1029f33bdd2
--- /dev/null
+++ b/firmware/minitlu/scripts/test_aida_tlu_trig_counter.py
@@ -0,0 +1,106 @@
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+boardIpAddr = "192.168.200.16"
+boardPortNum = 50001
+
+addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+boardFirmware = board.read("FirmwareId")
+print "Firmware version = " , hex(boardFirmware)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+resetSerdes = 0
+
+# set DACs to -200mV
+print "Setting all threshold DAC to -50mV "
+boardi2c.set_threshold_voltage(7, -0.050)
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+ print "Resetting clocks"
+ board.write("LogicRst", 1 )
+
+ clockStatus = board.read("LogicClocksCSR")
+ print "Clock status after reset = " , hex(clockStatus)
+
+#print "Setting PLL input to ext. clk"
+#board.write("LogicRst", 0 )
+#clockStatus = board.read("LogicClocksCSR")
+#print "Clock status = " , hex(clockStatus)
+
+
+inputStatus = board.read("SerdesRstR")
+print "Input status = " , hex(inputStatus)
+
+if resetSerdes:
+ board.write("SerdesRst", 0x00000003 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status during reset = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000000 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status after reset = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000004 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status during calibration = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000000 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status after calibration = " , hex(inputStatus)
+
+
+# Look at status of input IODELAYs
+numLoops = 100
+
+oldCount = [0,0,0,0]
+sleepTime = 1.0
+
+for iLoop in range(0,numLoops):
+
+ inputStatus = board.read("SerdesRstR")
+ print "Input status = " , hex(inputStatus)
+
+ count0 = board.read("ThrCount0R")
+ rate0 = (count0 - oldCount[0])/sleepTime
+ oldCount[0] = count0
+ print " Count , rate 0 = " , count0 , rate0
+
+ count1 = board.read("ThrCount1R")
+ rate1 = (count1 - oldCount[1])/sleepTime
+ oldCount[1] = count1
+ print " Count , rate 1 = " , count1 , rate1
+
+ count2 = board.read("ThrCount2R")
+ rate2 = (count2 - oldCount[2])/sleepTime
+ oldCount[2] = count2
+ print " Count , rate 2 = " , count2 ,rate2
+
+ count3 = board.read("ThrCount3R")
+ rate3 = (count3 - oldCount[3])/sleepTime
+ oldCount[3] = count3
+ print " Count ,rate 3 = " , count3 ,rate3
+
+ print "\n\n"
+
+ time.sleep(sleepTime)
+
+
diff --git a/firmware/minitlu/simulation/questa/fmc_tlu.cr.mti b/firmware/minitlu/simulation/questa/fmc_tlu.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..9657c10db9d769217dac46d416545e642e420e4a
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/fmc_tlu.cr.mti
@@ -0,0 +1,31 @@
+/afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc-tlu_sp601.vhdl {1 {vcom -work work -2008 -explicit -vopt /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc-tlu_sp601.vhdl
+QuestaSim vcom 6.6d Compiler 2010.11 Nov 1 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package vcomponents
+-- Compiling entity fmc_tlu_sp601
+-- Compiling architecture rtl of fmc_tlu_sp601
+
+} {} {}} /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fd.vhdl {1 {vcom -work work -2008 -explicit -vopt /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fd.vhdl
+QuestaSim vcom 6.6d Compiler 2010.11 Nov 1 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Compiling entity dtype_fd
+-- Compiling architecture rtl of dtype_fd
+
+} {} {}} /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/pulse_shaper.vhdl {1 {vcom -work work -2008 -explicit -vopt /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/pulse_shaper.vhdl
+QuestaSim vcom 6.6d Compiler 2010.11 Nov 1 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Loading package vcomponents
+-- Compiling entity pulse_shaper
+-- Compiling architecture rtl of pulse_shaper
+
+} {} {}} /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fdpe.vhdl {1 {vcom -work work -2008 -explicit -vopt /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fdpe.vhdl
+QuestaSim vcom 6.6d Compiler 2010.11 Nov 1 2010
+-- Loading package standard
+-- Loading package std_logic_1164
+-- Compiling entity dtype_fdpe
+-- Compiling architecture dtype_v of dtype_fdpe
+
+} {} {}}
diff --git a/firmware/minitlu/simulation/questa/fmc_tlu.mpf b/firmware/minitlu/simulation/questa/fmc_tlu.mpf
new file mode 100644
index 0000000000000000000000000000000000000000..f146724b70b1a7c1d51d6ec0bfd88abdeedab138
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/fmc_tlu.mpf
@@ -0,0 +1,1592 @@
+; Copyright 1991-2010 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+; to use Vital 1995 version of the standard
+; IEEE library must be mapped to the vital1995 library
+; one cannot use the vital1995 library directly because it assume that it
+; is the IEEE library. If vital1995 and vital2000 are being mixed together then
+; ieee must be mapped to vital1995 and vital200 mapped to vital2000
+; ieee = $MODEL_TECH/../vital1995
+; for compatiblity with previously the VITAL2000 maps to a seperate library from IEEE
+; if one should not reference vital from both the ieee library and the vital library becasue
+; the vital packages are effectively different. If one needs to reference both libraies the
+; vital2000 and ieee MUST be mapped to the same library either $MODEL_TECH/../ieee
+; or $MODEL_TECH/../vital2000
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+unisim = $XILINX/vhdl/questa/6.6d/lin64/unisim
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message.
+; Or stop the simulator after SystemVerilog severity system task.
+; The severity of VHDL assertion or severity system task
+; should be higher or equal.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file using system lockd locking mechanism.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: At this time, the "auto" setting is equivalent to the "bdd" setting.
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 20000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 20000000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 5
+Project_File_0 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc-tlu_sp601.vhdl
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298653495 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2008
+Project_File_1 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/pulse_shaper.vhdl
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298654919 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2008
+Project_File_2 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fd.vhdl
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298563433 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008
+Project_File_3 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/fmc_tlu_sp601_tb.vhdl
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298652988 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 1 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2008
+Project_File_4 = /afs/phy.bris.ac.uk/cad/designs/fmc-mtlu/trunk/firmware/src/dtype_fdpe.vhdl
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1298458157 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2008
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+Project_Major_Version = 6
+Project_Minor_Version = 6
diff --git a/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.fdo b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.fdo
new file mode 100644
index 0000000000000000000000000000000000000000..415ecc20d3d440f52cd3dbfacdc084c8ee749245
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.fdo
@@ -0,0 +1,115 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench.fdo
+## Created on: Fri Feb 28 10:49:46 GMT 2014
+##
+## Auto generated by Project Navigator for Behavioral Simulation
+##
+## ---------------------DO NOT EDIT THIS FILE-------------------------
+## You may want to add additional commands to control the simulation
+## in the user specific do file (<module>.udo) which is automatically
+## generated in the project directory and will not be removed on
+## subsequent simulation flows run from Project Navigator.
+## ---------------------DO NOT EDIT THIS FILE-------------------------
+##
+######################################################################
+#
+# Create work library
+#
+vlib work
+#
+# Compile sources
+#
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_if.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd"
+vcom -explicit -93 "ipbus/firmware/example_designs/hdl/clock_div.vhd"
+vcom -explicit -93 "ipcore_dir/tri_mode_eth_mac_v5_4.vhd"
+vcom -explicit -93 "ipcore_dir/mac_fifo_axi4.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/trans_arb.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/stretcher.vhd"
+vcom -explicit -93 "ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_registers.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_byte_ctrl.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_bit_ctrl.vhd"
+vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd"
+vlog "../fmc-mtlu/firmware/hdl/test/clock_divider_s6.v"
+vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd"
+vcom -explicit -93 "ipcore_dir/tlu_event_fifo.vhd"
+vcom -explicit -93 "ipcore_dir/internalTriggerGenerator.vhd"
+vcom -explicit -93 "ipcore_dir/FIFO.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd"
+vcom -explicit -93 "ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_top.vhd"
+vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd"
+vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd"
+vlog "/automount/users/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//verilog/src/glbl.v"
+#
+# Call vsim to invoke simulator
+#
+vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.fmctlu_v0_1_testbench glbl
+#
+# Source the wave do file
+#
+do {fmctlu_v0_1_testbench_wave.fdo}
+#
+# Set the window types
+#
+view wave
+view structure
+view signals
+#
+# Source the user do file
+#
+do {fmctlu_v0_1_testbench.udo}
+#
+# Run simulation for this time
+#
+run 1000ns
+#
+# End
+#
diff --git a/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.udo b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.udo
new file mode 100644
index 0000000000000000000000000000000000000000..82867cb7c556110958f2cb00d2771e8428bd0a94
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench.udo
@@ -0,0 +1,10 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench.udo
+## Created on: Wed Feb 26 17:46:18 GMT 2014
+##
+## Auto generated by Project Navigator for Post-Behavioral Simulation
+##
+## You may want to edit this file to control your simulation.
+##
+######################################################################
diff --git a/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench_wave.fdo b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench_wave.fdo
new file mode 100644
index 0000000000000000000000000000000000000000..26b485303eebe0a31bc7123d58210f42ed281562
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/fmctlu_v0_1_testbench_wave.fdo
@@ -0,0 +1,12 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench_wave.fdo
+## Created on: Wed Feb 26 17:46:21 GMT 2014
+##
+## Auto generated by Project Navigator for Post-Behavioral Simulation
+##
+## You may want to edit this file to control your simulation windows.
+##
+######################################################################
+add wave *
+# add wave /glbl/GSR
diff --git a/firmware/minitlu/simulation/questa/modelsim.ini b/firmware/minitlu/simulation/questa/modelsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..b025bbdacc06d8e98eb8be87f7020f1804ac766b
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+++ b/firmware/minitlu/simulation/questa/modelsim.ini
@@ -0,0 +1,1868 @@
+; Copyright 1991-2013 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+unimacro = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unimacro
+simprim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/simprim
+unisim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unisim
+xilinxcorelib = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/xilinxcorelib
+unimacro_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unimacro_ver
+simprims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/simprims_ver
+unisims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unisims_ver
+xilinxcorelib_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/xilinxcorelib_ver
+secureip = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/secureip
+
+[DefineOptionset]
+; Define optionset entries for the various compilers, vmake, and vsim.
+; These option sets can be used with the "-optionset <optionsetname>" syntax.
+; i.e.
+; vlog -optionset COMPILEDEBUG top.sv
+; vsim -optionset UVMDEBUG my_top
+;
+; Following are some useful examples.
+
+; define a vsim optionset for uvm debugging
+UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
+
+; define a vopt optionset for debugging
+VOPTDEBUG = +acc -debugdb
+
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl", "sccts", "iddp" and "atpi".
+; SVExtensions = uslt,spsl,sccts
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 20000
+
+; Set XPROP assertion fail limit. Default is 5.
+; Any positive integer, -1 for infinity.
+; XpropAssertionLimit = 5
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is 0 (disabled). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase
+DefaultRadix = hexadecimal
+DefaultRadixFlags = showbase
+; Set to 1 for make the signal_force VHDL and Verilog functions use the
+; default radix when processing the force value. Prior to 10.2 signal_force
+; used the default radix, now it always uses symbolic unless value explicitly indicates base
+;SignalForceFunctionUseDefaultRadix = 0
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Make VHDL packages in PDUs have there own copy of a package instead
+; of sharing the package between PDUs. By default share packages
+; VhdlSeparatePduPackage = 0
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+; The default is UVMControl = struct
+
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+; Specify the WildcardFilter setting.
+; A space separated list of object types to be excluded when performing
+; wildcard matches with log, wave, etc commands. The default value for this variable is:
+; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
+; See "Using the WildcardFilter Preference Variable" in the documentation for
+; details on how to use this variable and for descriptions of the filter types.
+WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
+
+; Specify the WildcardSizeThreshold setting.
+; This integer setting specifies the size at which objects will be excluded when
+; performing wildcard matches with log, wave, etc commands. Objects of size equal
+; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
+; matches. The size is a simple calculation of number of bits or items in the object.
+; The default value is 8k (8192). Setting this value to 0 will disable the checking
+; of object size against this threshold and allow all objects of any size to be logged.
+WildcardSizeThreshold = 8192
+
+; Specify whether warning messages are output when objects are filtered out due to the
+; WildcardSizeThreshold. The default is 0 (no messages generated).
+WildcardSizeThresholdVerbose = 0
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file.
+; Value is the number of seconds between updated. After at least the
+; interval number of seconds, the wlf file is flushed, ensuring that the data
+; is correct when viewed from a separate live viewer. Setting to 0 means no
+; updating. Default is 10 seconds, which has a tiny performance impact
+; WLFUpdateInterval = 10
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
+; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Specify the size of objects that will trigger "large object" messages
+; at log/wave/list time. The size calculation of the object is the same as that
+; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
+; Setting LargeObjectSize to 0 will disable these messages.
+; LargeObjectSize = 500000
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Set SystemC thread stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). The stack size for sc_thread depends
+; on the amount of data on the sc_thread stack and the memory required
+; to succesfully execute the thread.
+; ScStackSize = 1 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+; Print "simstats" result in Tcl list form
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStatsList = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; This option applies to condition and expression coverage UDP tables. It
+; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
+; If this option is used and a match occurs in more than one row in the UDP table,
+; none of the counts for all matching rows is incremented. By default, counts are
+; incremented for all matching rows.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Turn off automatic inclusion of VHDL records in toggle coverage.
+; Default is to include them.
+; ToggleVHDLRecords = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; FecCountLimit = 1
+
+; Limit the counts that are tracked for UDP Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; UdpCountLimit = 1
+
+; Control toggle coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
+; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; ToggleDeglitchPeriod = 10.0ps
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
+; and report. This variable sets the default value of type_option.merge_instances.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroupMergeInstancesDefault = 0
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Error message severity for suppressible errors that are detected in a
+; solve/before constraint.
+; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveBeforeErrorSeverity = 3
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable basic debug (with no
+; performance penalty). Set to 2 for enhanced debug (will result in slower
+; runtime performance).
+; SolveFailDebug = 0
+
+; Upon encountering a randomize() failure, generate a simplified testcase that
+; will reproduce the failure. Optionally output the testcase to a file.
+; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
+; is enabled (see above).
+; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
+; command line switch.
+; The default is OFF (do not generate a testcase). To enable testcase
+; generation, uncomment this variable. To redirect testcase generation to a
+; file, specify the name of the output file.
+; SolveFailTestcase =
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 2000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 2000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveACTMaxOps = 10000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMax[Tests|Ops] threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Specify the memory threshold for the System Verilog garbage collector.
+; The value is the number of megabytes of class objects that must accumulate
+; before the garbage collector is run.
+; The GCThreshold setting is used when class debug mode is disabled to allow
+; less frequent garbage collection and better simulation performance.
+; The GCThresholdClassDebug setting is used when class debug mode is enabled
+; to allow for more frequent garbage collection.
+; GCThreshold = 100
+; GCThresholdClassDebug = 5
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+; Controls the formatting of '%p' and '%P' conversion specification, used in $display
+; and similar system tasks.
+; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
+; The 'I' flag when present causes relevant data types to be expanded and indented into
+; a more readable format.
+; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
+; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
+; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
+; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
+; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
+; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
+; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
+; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
+; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
+; 7. Items 1-6 above can be combined as a comma separated list.
+; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5)
+; SVPrettyPrintFlags=I4S
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
+
+[utils]
+; Default Library Type
+; Set to determine the default type for a library created with "vlib"
+; 0 - legacy library using subdirectories for design units
+; 1 - archive library (deprecated)
+; 2 - flat library
+; DefaultLibType = 2
+
+; Archive Library Compact Value
+; Sets compaction trigger for archive libraries. The value is the percentage
+; of free space in the archive.
+; ArchiveLibCompact = 0.5
+
+; Flat Library Page Size
+; Set the size in bytes for flat library file pages. Very large libraries
+; may benefit from a larger value, at the expense of disk space.
+; FlatLibPageSize = 8192
+
+; Flat Library Page Cleanup Percentage
+; Set the percentage of total pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeleteThreshold.
+; FlatLibPageDeletePercentage = 50
+
+; Flat Library Page Cleanup Threshold
+; Set the number of pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeletePercentage.
+; FlatLibPageDeleteThreshold = 1000
+
diff --git a/firmware/minitlu/simulation/questa/vish_stacktrace.vstf b/firmware/minitlu/simulation/questa/vish_stacktrace.vstf
new file mode 100644
index 0000000000000000000000000000000000000000..605b44990d05cbfe04cdcef12be90bc73b4cc92e
--- /dev/null
+++ b/firmware/minitlu/simulation/questa/vish_stacktrace.vstf
@@ -0,0 +1,140 @@
+# Current time Fri Feb 25 16:14:05 2011
+# QuestaSim Stack Trace
+# Program = vish
+# Id = "6.6d"
+# Version = "2010.11"
+# Date = "Nov 1 2010"
+# Platform = linux
+# 0 0x00be3430: '<unknown (@0xbe3430)>'
+# 1 0x083c6903: 'TclpObjNormalizePath + 0x41b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 2 0x083c6c2a: 'TclpMatchInDirectory + 0x292' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 3 0x083a4f62: 'Tcl_FSMatchInDirectory + 0x3e' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 4 0x083927b9: 'TclDoGlob + 0x235' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 5 0x08392b2f: 'TclDoGlob + 0x5ab' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 6 0x08392ec2: 'TclGlob + 0x10e' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 7 0x08393c6f: 'Tcl_GlobObjCmd + 0xa8f' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 8 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 9 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 10 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 11 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 12 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 13 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 14 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 15 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 16 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 17 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 18 0x0836657f: 'Tcl_EvalObjEx + 0x5f' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 19 0x083b3eff: 'Tcl_UplevelObjCmd + 0x93' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 20 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 21 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 22 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 23 0x083665b8: 'Tcl_EvalObjEx + 0x98' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 24 0x00b6eac0: 'Itcl_EvalMemberCode + 0x17c' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 25 0x00b6f895: 'Itcl_ExecMethod + 0xc1' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 26 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 27 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 28 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 29 0x083665b8: 'Tcl_EvalObjEx + 0x98' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 30 0x00b6eac0: 'Itcl_EvalMemberCode + 0x17c' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 31 0x00b6f895: 'Itcl_ExecMethod + 0xc1' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 32 0x00b761ed: 'Itcl_EvalArgs + 0x65' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 33 0x00b701ea: 'Itcl_HandleInstance + 0x17e' in '/net/asimov/users/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/linux/libitcl3.2.so'
+# 34 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 35 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 36 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 37 0x083665b8: 'Tcl_EvalObjEx + 0x98' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 38 0x083ab9af: 'Tcl_NamespaceObjCmd + 0xe3b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 39 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 40 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 41 0x083516df: 'Tk_BindEvent + 0xecb' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 42 0x083528f1: 'TkBindEventProc + 0xb1' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 43 0x082d5945: 'Tk_HandleEvent + 0x45d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 44 0x082d6149: 'TkQueueEventForAllChildren + 0xad' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 45 0x083ac0bc: 'Tcl_ServiceEvent + 0x54' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 46 0x083ac2ee: 'Tcl_DoOneEvent + 0x72' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 47 0x08353144: 'Tk_TkwaitObjCmd + 0x204' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 48 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 49 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 50 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 51 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 52 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 53 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 54 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 55 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 56 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 57 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 58 0x0836657f: 'Tcl_EvalObjEx + 0x5f' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 59 0x08369be5: 'Tcl_EvalObjCmd + 0x45' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 60 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 61 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 62 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 63 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 64 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 65 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 66 0x0836657f: 'Tcl_EvalObjEx + 0x5f' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 67 0x08369be5: 'Tcl_EvalObjCmd + 0x45' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 68 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 69 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 70 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 71 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 72 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 73 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 74 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 75 0x083665b8: 'Tcl_EvalObjEx + 0x98' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 76 0x082e4cd0: 'TkInvokeButton + 0x4c' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 77 0x082e4ec7: 'TkInvokeButton + 0x243' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 78 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 79 0x0836638a: 'Tcl_EvalObjv + 0x8a' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 80 0x083666bd: 'Tcl_EvalObjEx + 0x19d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 81 0x083b3eff: 'Tcl_UplevelObjCmd + 0x93' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 82 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 83 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 84 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 85 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 86 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 87 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 88 0x083516df: 'Tk_BindEvent + 0xecb' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 89 0x083528f1: 'TkBindEventProc + 0xb1' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 90 0x082d5945: 'Tk_HandleEvent + 0x45d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 91 0x082d6149: 'TkQueueEventForAllChildren + 0xad' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 92 0x083ac0bc: 'Tcl_ServiceEvent + 0x54' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 93 0x083ac2ee: 'Tcl_DoOneEvent + 0x72' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 94 0x08353144: 'Tk_TkwaitObjCmd + 0x204' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 95 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 96 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 97 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 98 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 99 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 100 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 101 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 102 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 103 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 104 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 105 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 106 0x083665b8: 'Tcl_EvalObjEx + 0x98' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 107 0x082ef89b: 'TkInvokeMenu + 0xa3' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 108 0x082f18f4: 'TkFreeMenuReferences + 0x139c' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 109 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 110 0x0836638a: 'Tcl_EvalObjv + 0x8a' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 111 0x083666bd: 'Tcl_EvalObjEx + 0x19d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 112 0x083b3eff: 'Tcl_UplevelObjCmd + 0x93' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 113 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 114 0x08389f57: 'TclExprFloatError + 0x2a1b' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 115 0x0838f03f: 'TclCompEvalObj + 0x107' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 116 0x083b4895: 'TclObjInterpProc + 0x24d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 117 0x08364625: 'TclEvalObjvInternal + 0x341' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 118 0x08365ab9: 'Tcl_EvalEx + 0x1cd' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 119 0x083516df: 'Tk_BindEvent + 0xecb' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 120 0x083528f1: 'TkBindEventProc + 0xb1' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 121 0x082d5945: 'Tk_HandleEvent + 0x45d' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 122 0x082d6149: 'TkQueueEventForAllChildren + 0xad' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 123 0x083ac0bc: 'Tcl_ServiceEvent + 0x54' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 124 0x083ac2ee: 'Tcl_DoOneEvent + 0x72' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 125 0x082d620d: 'Tk_MainLoop + 0x19' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 126 0x082dd3e0: 'Tk_MainEx + 0x298' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 127 0x0816da78: 'vish_inner_loop + 0x238' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 128 0x0816e78c: 'main + 0x87c' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# 129 0x003f9bb1: '_libc_start_main + 0xe1' in '/lib/libc.so.6'
+# 130 0x080bd18c: 'start + 0x1c' in '/software/CAD/Mentor/2010_2011/HDS2008.1b/questasim/bin/../linux/vish'
+# End of Stack Trace
+
diff --git a/firmware/minitlu/simulation/questa/vsim.wlf b/firmware/minitlu/simulation/questa/vsim.wlf
new file mode 100644
index 0000000000000000000000000000000000000000..53122dbe80bed5188883e3dbcf2580985d4c202a
Binary files /dev/null and b/firmware/minitlu/simulation/questa/vsim.wlf differ
diff --git a/firmware/minitlu/simulation/scripts/README b/firmware/minitlu/simulation/scripts/README
new file mode 100644
index 0000000000000000000000000000000000000000..0a4c8cca2e54aa262e908cfb3cf5b45b90e6f0d8
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/README
@@ -0,0 +1,6 @@
+
+add_files.tcl - Works, but crude
+
+addfiles_sim.tcl - Dave N's script. ( used as basis for add_files.tcl )
+
+setup.sh - Dave N's script to build Modelsim FLI MAC hardware. Doesn't work yet
diff --git a/firmware/minitlu/simulation/scripts/add_files.tcl b/firmware/minitlu/simulation/scripts/add_files.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..86382b5e6b9181e740a8d869c8995dfaf443d014
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/add_files.tcl
@@ -0,0 +1,86 @@
+set xlib_vhdl $::env(ISE_VHDL_MTI)
+set xlib_vlog $::env(ISE_VLOG_MTI)
+
+project new ./ fmc_tlu_sim
+vmap unisim $xlib_vhdl/unisim
+vmap unimacro $xlib_vhdl/unimacro
+vmap secureip $xlib_vlog/secureip
+vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
+
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/mac_fifo_axi4.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_registers.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/tlu_event_fifo.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/internalTriggerGenerator.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipcore_dir/FIFO.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/external/opencores_i2c/i2c_master_top.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/ipbus/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
+project addfile $::env(FW_WORKSPACE)/workspace/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
+
+project calculateorder
+project close
+quit
+
diff --git a/firmware/minitlu/simulation/scripts/addfiles_sim.tcl b/firmware/minitlu/simulation/scripts/addfiles_sim.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..128b3fbfb6eb95def37148effa69b2e5b0411bb8
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/addfiles_sim.tcl
@@ -0,0 +1,38 @@
+# Horrible hacky TCL script to build ISE project from hierarchy of source lists
+
+proc dofile {f} {
+ set fp [open $f r]
+ set files [read $fp]
+ close $fp
+ foreach f_line [split $files "\n"] {
+ if {$f_line == "" || [string index $f_line 0] == "#"} {
+ continue
+ }
+ set l [split $f_line]
+ set cmd [lindex $l 0]
+ set arg1 [lindex $l 1]
+ set arg2 [lindex $l 2]
+ set f_list [glob $::env(REPOS_FW_DIR)/$arg1]
+ foreach f_loc $f_list {
+ set f_loc_s [exec basename $f_loc]
+ if {$cmd == "hdl"} {
+ addfile $f_loc $arg2
+ } elseif {$cmd == "core"} {
+ addcore $f_loc $arg2
+ } elseif {$cmd == "include"} {
+ dofile $f_loc
+ }
+ }
+ }
+}
+
+proc addfile {f lib} {
+ project addfile $f
+}
+
+proc addcore {f lib} {
+ addfile [file rootname $f].vhd $lib
+}
+
+dofile $::env(REPOS_BUILD_DIR)/file_list
+
diff --git a/firmware/minitlu/simulation/scripts/file_list b/firmware/minitlu/simulation/scripts/file_list
new file mode 100644
index 0000000000000000000000000000000000000000..04242c09ad6ac56365e752016ef98506de2e9397
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/file_list
@@ -0,0 +1,67 @@
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/mac_fifo_axi4.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_registers.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/tlu_event_fifo.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/internalTriggerGenerator.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/FIFO.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_top.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
diff --git a/firmware/minitlu/simulation/scripts/file_list.sav b/firmware/minitlu/simulation/scripts/file_list.sav
new file mode 100644
index 0000000000000000000000000000000000000000..a071b6366ac4724d1e3e7ffed59b5affb768cad9
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/file_list.sav
@@ -0,0 +1,7 @@
+hdl ipbus/firmware/sim/hdl/top_sim.vhd
+hdl ipbus/firmware/sim/hdl/clock_sim.vhd
+hdl ipbus/firmware/ethernet/sim/eth_mac_sim.vhd
+hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+include ipbus/firmware/ipbus_core/cfg/file_list
+include ipbus/firmware/example_designs/cfg/file_list
+
diff --git a/firmware/minitlu/simulation/scripts/files.txt b/firmware/minitlu/simulation/scripts/files.txt
new file mode 100644
index 0000000000000000000000000000000000000000..2c0379cd357643ef7cfe9b20debc02646c273efc
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/files.txt
@@ -0,0 +1,68 @@
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
+$FW_WORKSPACE/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+$FW_WORKSPACE/workspace/ipcore_dir/mac_fifo_axi4.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+$FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_registers.vhd
+$FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+$FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+$FW_WORKSPACE/workspace/ipcore_dir/tlu_event_fifo.vhd
+$FW_WORKSPACE/workspace/ipcore_dir/internalTriggerGenerator.vhd
+$FW_WORKSPACE/workspace/ipcore_dir/FIFO.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+$FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_top.vhd
+$FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+$FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+
diff --git a/firmware/minitlu/simulation/scripts/fmc_tlu_sim.cr.mti b/firmware/minitlu/simulation/scripts/fmc_tlu_sim.cr.mti
new file mode 100644
index 0000000000000000000000000000000000000000..8f30acbb98015bac29cc9e11348d3ab9ae4db291
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/fmc_tlu_sim.cr.mti
@@ -0,0 +1,717 @@
+/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_top.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_top.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Compiling entity i2c_master_top
+-- Compiling architecture arch of i2c_master_top
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package fmcTLU
+-- Loading package VCOMPONENTS
+-- Compiling entity triggerInputs
+-- Compiling architecture rtl of triggerInputs
+-- Loading entity dualSERDES_1to4
+-- Loading entity arrivalTimeLUT
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd(174): (vcom-1436) Actual expression (infix expression) of formal "deserialized_data_i" is not globally static.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd(207): (vcom-1436) Actual expression (infix expression) of formal "deserialized_data_i" is not globally static.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd(228): VHDL Compiler exiting
+
+} {14.0 17.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity top_extphy
+-- Loading package ipbus
+-- Loading package emac_hostbus_decl
+-- Loading package fmcTLU
+-- Loading package VCOMPONENTS
+-- Compiling architecture struct of top_extphy
+-- Loading entity DUTInterfaces
+-- Loading entity IPBusInterface
+-- Loading entity eventBuffer
+-- Loading entity eventFormatter
+-- Loading entity i2c_master
+-- Loading entity logic_clocks
+-- Loading entity triggerInputs
+-- Loading entity triggerLogic
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Compiling entity i2c_master
+-- Compiling architecture rtl of i2c_master
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Loading entity i2c_master_top
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package VCOMPONENTS
+-- Compiling entity DUTInterfaces
+-- Compiling architecture rtl of DUTInterfaces
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_byte_ctrl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Compiling entity i2c_master_byte_ctrl
+-- Compiling architecture arch of i2c_master_byte_ctrl
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_w.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_w.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity syncreg_w
+-- Compiling architecture rtl of syncreg_w
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_bit_ctrl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Compiling entity i2c_master_bit_ctrl
+-- Compiling architecture arch of i2c_master_bit_ctrl
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_DualPortRAM_tx
+-- Compiling architecture v3 of udp_DualPortRAM_tx
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/emac_hostbus_decl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package emac_hostbus_decl
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package ipbus_trans_decl
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_payload.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_payload.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_build_payload
+-- Compiling architecture rtl of udp_build_payload
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_rxtransactor_if
+-- Compiling architecture simple of udp_rxtransactor_if
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_buffer_selector.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_buffer_selector
+-- Compiling architecture simple of udp_buffer_selector
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_mux.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_rxram_mux
+-- Compiling architecture rtl of udp_rxram_mux
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_registers.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_registers.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Compiling entity i2c_master_registers
+-- Compiling architecture arch of i2c_master_registers
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_status_buffer.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_status_buffer
+-- Compiling architecture rtl of udp_status_buffer
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_do_rx_reset
+-- Compiling architecture rtl of udp_do_rx_reset
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rarp_block.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_rarp_block
+-- Compiling architecture rtl of udp_rarp_block
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_if.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_if.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus_trans_decl
+-- Compiling entity transactor_if
+-- Compiling architecture rtl of transactor_if
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_resend.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_resend.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_build_resend
+-- Compiling architecture rtl of udp_build_resend
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_sm.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_sm.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Compiling entity transactor_sm
+-- Compiling architecture rtl of transactor_sm
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Compiling package body fmcTLU
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package fmcTLU
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Compiling entity triggerLogic
+-- Compiling architecture rtl of triggerLogic
+** Error: (vcom-11) Could not find work.sync_reg.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(142): (vcom-1195) Cannot find expanded name "work.sync_reg".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(142): Unknown expanded name.
+** Error: (vcom-11) Could not find work.internaltriggergenerator.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(227): (vcom-1195) Cannot find expanded name "work.internalTriggerGenerator".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(227): Unknown expanded name.
+** Error: (vcom-11) Could not find work.sync_reg.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(260): (vcom-1195) Cannot find expanded name "work.sync_reg".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(260): Unknown expanded name.
+** Error: (vcom-11) Could not find work.sync_reg.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(268): (vcom-1195) Cannot find expanded name "work.sync_reg".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(268): Unknown expanded name.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd(301): VHDL Compiler exiting
+
+} {10.0 23.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_clock_crossing_if
+-- Compiling architecture rtl of udp_clock_crossing_if
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Compiling entity eventBuffer
+-- Compiling architecture rtl of eventBuffer
+** Error: (vcom-11) Could not find work.tlu_event_fifo.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd(133): (vcom-1195) Cannot find expanded name "work.tlu_event_fifo".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd(133): Unknown expanded name.
+-- Loading entity registerCounter
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd(173): VHDL Compiler exiting
+
+} {10.0 13.0 14.0 15.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package VCOMPONENTS
+-- Compiling entity logic_clocks
+-- Compiling architecture rtl of logic_clocks
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd(300): (vcom-1436) Actual expression (infix expression) of formal "RST" is not globally static.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd(380): VHDL Compiler exiting
+
+} {11.0 13.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_DualPortRAM
+-- Compiling architecture initial of udp_DualPortRAM
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_status.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_status.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_build_status
+-- Compiling architecture rtl of udp_build_status
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/example_designs/hdl/clock_div.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/example_designs/hdl/clock_div.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Loading package VCOMPONENTS
+-- Compiling entity clock_div
+-- Compiling architecture rtl of clock_div
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity arrivalTimeLUT
+-- Compiling architecture rtl of arrivalTimeLUT
+** Error: (vcom-11) Could not find work.counterup.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd(178): (vcom-1195) Cannot find expanded name "work.CounterUp".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd(178): Unknown expanded name.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd(187): VHDL Compiler exiting
+
+} {9.0 13.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/trans_arb.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/trans_arb.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus_trans_decl
+-- Compiling entity trans_arb
+-- Compiling architecture rtl of trans_arb
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tlu_event_fifo.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tlu_event_fifo.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tlu_event_fifo.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_tx_mux.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_tx_mux
+-- Compiling architecture rtl of udp_tx_mux
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_ping.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_ping.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_build_ping
+-- Compiling architecture rtl of udp_build_ping
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_packet_parser.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity udp_packet_parser
+-- Compiling architecture v3 of udp_packet_parser
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_txtransactor_if
+-- Compiling architecture simple of udp_txtransactor_if
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Compiling package ipbus_addr_decode
+-- Compiling package body ipbus_addr_decode
+-- Loading package ipbus_addr_decode
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_r.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_r.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity syncreg_r
+-- Compiling architecture rtl of syncreg_r
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_ctrl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package ipbus
+-- Loading package ipbus_trans_decl
+-- Compiling entity ipbus_ctrl
+-- Compiling architecture rtl of ipbus_ctrl
+-- Loading package NUMERIC_STD
+-- Loading entity UDP_if
+-- Loading entity trans_arb
+-- Loading entity transactor
+-- Loading entity stretcher
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package ipbus_trans_decl
+-- Compiling entity transactor
+-- Compiling architecture rtl of transactor
+-- Loading entity transactor_if
+-- Loading entity transactor_sm
+-- Loading entity transactor_cfg
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_fabric.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package ipbus
+-- Loading package NUMERIC_STD
+-- Loading package ipbus_addr_decode
+-- Compiling entity ipbus_fabric
+-- Compiling architecture rtl of ipbus_fabric
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_arp.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_arp.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_build_arp
+-- Compiling architecture rtl of udp_build_arp
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package emac_hostbus_decl
+-- Compiling entity IPBusInterface
+-- Compiling architecture rtl of IPBusInterface
+-- Loading package VCOMPONENTS
+-- Loading entity clocks_s6_extphy
+-- Loading entity eth_s6_gmii
+-- Loading package ipbus_trans_decl
+-- Loading entity ipbus_ctrl
+-- Loading package ipbus_addr_decode
+-- Loading entity ipbus_fabric
+-- Loading entity ipbus_ver
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity registerCounter
+-- Compiling architecture rtl of registerCounter
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_syncreg_v.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package ipbus_reg_types
+-- Compiling entity ipbus_syncreg_v
+-- Compiling architecture rtl of ipbus_syncreg_v
+-- Loading entity syncreg_w
+-- Loading entity syncreg_r
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package VCOMPONENTS
+-- Compiling entity clocks_s6_extphy
+-- Compiling architecture rtl of clocks_s6_extphy
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package VCOMPONENTS
+-- Compiling entity dualSERDES_1to4
+-- Compiling architecture rtl of dualSERDES_1to4
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/stretcher.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/stretcher.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling entity stretcher
+-- Compiling architecture rtl of stretcher
+-- Loading package std_logic_arith
+-- Loading package STD_LOGIC_UNSIGNED
+-- Loading package VCOMPONENTS
+-- Loading entity clock_div
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/internalTriggerGenerator.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/internalTriggerGenerator.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/internalTriggerGenerator.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package ipbus
+-- Compiling entity ipbus_ver
+-- Compiling architecture rtl of ipbus_ver
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_if_flat.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_if_flat.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity UDP_if
+-- Compiling architecture flat of UDP_if
+-- Loading entity udp_ipaddr_block
+-- Loading entity udp_rarp_block
+-- Loading entity udp_build_arp
+-- Loading entity udp_build_payload
+-- Loading entity udp_build_ping
+-- Loading entity udp_build_resend
+-- Loading entity udp_build_status
+-- Loading entity udp_status_buffer
+-- Loading entity udp_byte_sum
+-- Loading entity udp_do_rx_reset
+-- Loading entity udp_packet_parser
+-- Loading entity udp_rxram_mux
+-- Loading entity udp_DualPortRAM
+-- Loading entity udp_buffer_selector
+-- Loading entity udp_rxram_shim
+-- Loading entity udp_DualPortRAM_rx
+-- Loading entity udp_DualPortRAM_tx
+-- Loading entity udp_rxtransactor_if
+-- Loading entity udp_tx_mux
+-- Loading entity udp_txtransactor_if
+-- Loading entity udp_clock_crossing_if
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package ipbus
+-- Loading package ipbus_reg_types
+-- Compiling entity ipbus_ctrlreg_v
+-- Compiling architecture rtl of ipbus_ctrlreg_v
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/mac_fifo_axi4.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/mac_fifo_axi4.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/mac_fifo_axi4.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Loading package fmcTLU
+-- Loading package ipbus
+-- Compiling entity eventFormatter
+-- Compiling architecture rtl of eventFormatter
+** Warning: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd(135): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+** Warning: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd(151): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+** Error: (vcom-11) Could not find work.fifo.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd(312): (vcom-1195) Cannot find expanded name "work.FIFO".
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd(312): Unknown expanded name.
+** Error: /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd(410): VHDL Compiler exiting
+
+} {13.0 17.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_ipaddr_block
+-- Compiling architecture rtl of udp_ipaddr_block
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/eth_s6_gmii.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/eth_s6_gmii.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package VCOMPONENTS
+-- Loading package emac_hostbus_decl
+-- Compiling entity eth_s6_gmii
+-- Compiling architecture rtl of eth_s6_gmii
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_shim.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_rxram_shim
+-- Compiling architecture simple of udp_rxram_shim
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v {1 {vlog -work work -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+QuestaSim vlog 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Compiling module clock_divider_s6
+
+Top level modules:
+ clock_divider_s6
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_DualPortRAM_rx
+-- Compiling architecture striped of udp_DualPortRAM_rx
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_package.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_package.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package ipbus
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package ipbus_reg_types
+-- Compiling package body ipbus_reg_types
+-- Loading package ipbus_reg_types
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_cfg.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_cfg.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity transactor_cfg
+-- Compiling architecture rtl of transactor_cfg
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_byte_sum.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Loading package NUMERIC_STD
+-- Compiling entity udp_byte_sum
+-- Compiling architecture rtl of udp_byte_sum
+
+} {} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/FIFO.vhd {0 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/FIFO.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+** Error: (vcom-7) Failed to open design unit file "/automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/FIFO.vhd" in read mode.
+No such file or directory. (errno = ENOENT)
+
+} {3.0 4.0} {}} /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd {1 {vcom -work work -2002 -explicit -vopt /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+QuestaSim vcom 10.2c_5 Compiler 2013.11 Nov 19 2013
+-- Loading package STANDARD
+-- Loading package TEXTIO
+-- Loading package std_logic_1164
+-- Compiling package fmcTLU
+
+} {} {}}
diff --git a/firmware/minitlu/simulation/scripts/fmc_tlu_sim.mpf b/firmware/minitlu/simulation/scripts/fmc_tlu_sim.mpf
new file mode 100644
index 0000000000000000000000000000000000000000..0319b813f71627c859037dff11ba7e873cc6177e
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/fmc_tlu_sim.mpf
@@ -0,0 +1,2067 @@
+; Copyright 1991-2013 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = modelsim.ini
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+
+work = work
+unisim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64//unisim
+unimacro = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64//unimacro
+secureip = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64//secureip
+xilinxcorelib = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64//xilinxcorelib
+[DefineOptionset]
+; Define optionset entries for the various compilers, vmake, and vsim.
+; These option sets can be used with the "-optionset <optionsetname>" syntax.
+; i.e.
+; vlog -optionset COMPILEDEBUG top.sv
+; vsim -optionset UVMDEBUG my_top
+;
+; Following are some useful examples.
+
+; define a vsim optionset for uvm debugging
+UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
+
+; define a vopt optionset for debugging
+VOPTDEBUG = +acc -debugdb
+
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl", "sccts", "iddp" and "atpi".
+; SVExtensions = uslt,spsl,sccts
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 20000
+
+; Set XPROP assertion fail limit. Default is 5.
+; Any positive integer, -1 for infinity.
+; XpropAssertionLimit = 5
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is 0 (disabled). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase
+DefaultRadix = hexadecimal
+DefaultRadixFlags = showbase
+; Set to 1 for make the signal_force VHDL and Verilog functions use the
+; default radix when processing the force value. Prior to 10.2 signal_force
+; used the default radix, now it always uses symbolic unless value explicitly indicates base
+;SignalForceFunctionUseDefaultRadix = 0
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Make VHDL packages in PDUs have there own copy of a package instead
+; of sharing the package between PDUs. By default share packages
+; VhdlSeparatePduPackage = 0
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+; The default is UVMControl = struct
+
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+; Specify the WildcardFilter setting.
+; A space separated list of object types to be excluded when performing
+; wildcard matches with log, wave, etc commands. The default value for this variable is:
+; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
+; See "Using the WildcardFilter Preference Variable" in the documentation for
+; details on how to use this variable and for descriptions of the filter types.
+WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
+
+; Specify the WildcardSizeThreshold setting.
+; This integer setting specifies the size at which objects will be excluded when
+; performing wildcard matches with log, wave, etc commands. Objects of size equal
+; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
+; matches. The size is a simple calculation of number of bits or items in the object.
+; The default value is 8k (8192). Setting this value to 0 will disable the checking
+; of object size against this threshold and allow all objects of any size to be logged.
+WildcardSizeThreshold = 8192
+
+; Specify whether warning messages are output when objects are filtered out due to the
+; WildcardSizeThreshold. The default is 0 (no messages generated).
+WildcardSizeThresholdVerbose = 0
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file.
+; Value is the number of seconds between updated. After at least the
+; interval number of seconds, the wlf file is flushed, ensuring that the data
+; is correct when viewed from a separate live viewer. Setting to 0 means no
+; updating. Default is 10 seconds, which has a tiny performance impact
+; WLFUpdateInterval = 10
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
+; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Specify the size of objects that will trigger "large object" messages
+; at log/wave/list time. The size calculation of the object is the same as that
+; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
+; Setting LargeObjectSize to 0 will disable these messages.
+; LargeObjectSize = 500000
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Set SystemC thread stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). The stack size for sc_thread depends
+; on the amount of data on the sc_thread stack and the memory required
+; to succesfully execute the thread.
+; ScStackSize = 1 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+; Print "simstats" result in Tcl list form
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStatsList = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; This option applies to condition and expression coverage UDP tables. It
+; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
+; If this option is used and a match occurs in more than one row in the UDP table,
+; none of the counts for all matching rows is incremented. By default, counts are
+; incremented for all matching rows.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Turn off automatic inclusion of VHDL records in toggle coverage.
+; Default is to include them.
+; ToggleVHDLRecords = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; FecCountLimit = 1
+
+; Limit the counts that are tracked for UDP Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; UdpCountLimit = 1
+
+; Control toggle coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
+; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; ToggleDeglitchPeriod = 10.0ps
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
+; and report. This variable sets the default value of type_option.merge_instances.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroupMergeInstancesDefault = 0
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Error message severity for suppressible errors that are detected in a
+; solve/before constraint.
+; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveBeforeErrorSeverity = 3
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable basic debug (with no
+; performance penalty). Set to 2 for enhanced debug (will result in slower
+; runtime performance).
+; SolveFailDebug = 0
+
+; Upon encountering a randomize() failure, generate a simplified testcase that
+; will reproduce the failure. Optionally output the testcase to a file.
+; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
+; is enabled (see above).
+; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
+; command line switch.
+; The default is OFF (do not generate a testcase). To enable testcase
+; generation, uncomment this variable. To redirect testcase generation to a
+; file, specify the name of the output file.
+; SolveFailTestcase =
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 2000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 2000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveACTMaxOps = 10000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMax[Tests|Ops] threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Specify the memory threshold for the System Verilog garbage collector.
+; The value is the number of megabytes of class objects that must accumulate
+; before the garbage collector is run.
+; The GCThreshold setting is used when class debug mode is disabled to allow
+; less frequent garbage collection and better simulation performance.
+; The GCThresholdClassDebug setting is used when class debug mode is enabled
+; to allow for more frequent garbage collection.
+; GCThreshold = 100
+; GCThresholdClassDebug = 5
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+; Controls the formatting of '%p' and '%P' conversion specification, used in $display
+; and similar system tasks.
+; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
+; The 'I' flag when present causes relevant data types to be expanded and indented into
+; a more readable format.
+; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
+; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
+; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
+; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
+; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
+; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
+; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
+; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
+; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
+; 7. Items 1-6 above can be combined as a comma separated list.
+; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5)
+; SVPrettyPrintFlags=I4S
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
+
+[utils]
+; Default Library Type
+; Set to determine the default type for a library created with "vlib"
+; 0 - legacy library using subdirectories for design units
+; 1 - archive library (deprecated)
+; 2 - flat library
+; DefaultLibType = 2
+
+; Archive Library Compact Value
+; Sets compaction trigger for archive libraries. The value is the percentage
+; of free space in the archive.
+; ArchiveLibCompact = 0.5
+
+; Flat Library Page Size
+; Set the size in bytes for flat library file pages. Very large libraries
+; may benefit from a larger value, at the expense of disk space.
+; FlatLibPageSize = 8192
+
+; Flat Library Page Cleanup Percentage
+; Set the percentage of total pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeleteThreshold.
+; FlatLibPageDeletePercentage = 50
+
+; Flat Library Page Cleanup Threshold
+; Set the number of pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeletePercentage.
+; FlatLibPageDeleteThreshold = 1000
+
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 72
+Project_File_0 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_top.vhd
+Project_File_P_0 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213197 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 49 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+Project_File_P_1 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 64 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+Project_File_P_2 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212915 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 53 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+Project_File_P_3 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 51 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+Project_File_P_4 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 52 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+Project_File_P_5 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213197 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 36 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+Project_File_P_6 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 68 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_w.vhd
+Project_File_P_7 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213045 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 38 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+Project_File_P_8 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213197 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 37 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+Project_File_P_9 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 12 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+Project_File_P_10 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213054 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 32 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_11 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+Project_File_P_11 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 1 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_payload.vhd
+Project_File_P_12 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 21 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+Project_File_P_13 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 6 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+Project_File_P_14 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 23 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+Project_File_P_15 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 8 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_16 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/external/opencores_i2c/i2c_master_registers.vhd
+Project_File_P_16 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213197 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 35 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_17 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+Project_File_P_17 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 5 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_18 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+Project_File_P_18 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 15 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+Project_File_P_19 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 9 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_20 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_if.vhd
+Project_File_P_20 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 25 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_21 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+Project_File_P_21 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212915 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 44 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_22 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_resend.vhd
+Project_File_P_22 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 19 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_23 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_sm.vhd
+Project_File_P_23 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 24 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_24 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+Project_File_P_24 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 63 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_25 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+Project_File_P_25 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 16 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_26 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+Project_File_P_26 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 67 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_27 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+Project_File_P_27 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 65 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_28 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram.vhd
+Project_File_P_28 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213041 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 14 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_29 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_status.vhd
+Project_File_P_29 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213041 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 18 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_30 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/example_designs/hdl/clock_div.vhd
+Project_File_P_30 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213032 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 27 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_31 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+Project_File_P_31 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 62 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_32 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/trans_arb.vhd
+Project_File_P_32 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 29 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_33 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+Project_File_P_33 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 3 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_34 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_ping.vhd
+Project_File_P_34 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 20 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_35 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tlu_event_fifo.vhd
+Project_File_P_35 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 59 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_36 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+Project_File_P_36 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 10 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_37 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+Project_File_P_37 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 4 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_38 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+Project_File_P_38 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 34 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_39 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/syncreg_r.vhd
+Project_File_P_39 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213045 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 39 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_40 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+Project_File_P_40 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213041 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 42 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_41 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
+Project_File_P_41 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 69 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_42 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor.vhd
+Project_File_P_42 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 30 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_43 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+Project_File_P_43 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 41 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_44 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_build_arp.vhd
+Project_File_P_44 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 22 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_45 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+Project_File_P_45 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 50 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_46 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
+Project_File_P_46 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 70 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_47 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+Project_File_P_47 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 45 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_48 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+Project_File_P_48 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213045 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 55 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_49 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+Project_File_P_49 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 58 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_50 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+Project_File_P_50 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 48 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_51 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+Project_File_P_51 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 47 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_52 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/internalTriggerGenerator.vhd
+Project_File_P_52 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 60 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_53 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/stretcher.vhd
+Project_File_P_53 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 31 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_54 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+Project_File_P_54 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 56 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_55 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_if_flat.vhd
+Project_File_P_55 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 28 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_56 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/mac_fifo_axi4.vhd
+Project_File_P_56 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 57 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_57 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+Project_File_P_57 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212879 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 46 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_58 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+Project_File_P_58 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 66 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_59 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd
+Project_File_P_59 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213045 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 54 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_60 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+Project_File_P_60 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 11 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_61 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+Project_File_P_61 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 7 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_62 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ethernet/hdl/eth_s6_gmii.vhd
+Project_File_P_62 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213055 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 43 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_63 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+Project_File_P_63 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1390212863 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_64 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+Project_File_P_64 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 13 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_65 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/ipbus_package.vhd
+Project_File_P_65 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 2 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_66 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd
+Project_File_P_66 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213045 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 40 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_67 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/workspace/ipcore_dir/FIFO.vhd
+Project_File_P_67 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 0 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 61 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 1 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_68 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/transactor_cfg.vhd
+Project_File_P_68 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 26 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_69 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/IPBus2/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+Project_File_P_69 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390213042 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 17 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_70 = /automount/users/phdgc/IPBus_stuff/fmc_tlu_test/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+Project_File_P_70 = cover_exttoggle 0 vhdl_noload 0 vlog_nodebug 0 last_compile 1390212915 vhdl_showsource 0 compile_to work file_type vhdl cover_cond 0 vhdl_disableopt 0 folder {Top Level} cover_fsm 0 vlog_noload 0 cover_excludedefault 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 vhdl_options {} compile_order 33 cover_nosub 0 vlog_protect 0 cover_toggle 0 vhdl_nodebug 0 vhdl_synth 0 vlog_disableopt 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_0InOptions {} vhdl_warn3 1 vhdl_warn4 1 voptflow 1 vhdl_warn5 1 ood 0 vlog_upper 0 vhdl_use93 2002 vhdl_novitalcheck 0 cover_nofec 0 group_id 0 vhdl_1164 1 vlog_1995compat 0 vhdl_enable0In 0 cover_branch 0 vlog_enable0In 0 vhdl_vital 0 vhdl_explicit 1 cover_covercells 0 vlog_0InOptions {} toggle - cover_noshort 0 vlog_options {} cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_71 = /users/phdgc/IPBus_stuff/fmc_tlu_alvaro_test_oct14/aida_minitlu_pinoutTest/fmc-mtlu/firmware/hdl/test/comb_generator_rtl.vhd
+Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1414060593 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 71 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+TDB_DoubleClick = Edit
+TDB_CustomDoubleClick =
+UPF_DoubleClick = Edit
+UPF_CustomDoubleClick =
+PCF_DoubleClick = Edit
+PCF_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+VRM_DoubleClick = Edit
+VRM_CustomDoubleClick =
+DEBUGDATABASE_DoubleClick = Edit
+DEBUGDATABASE_CustomDoubleClick =
+DEBUGARCHIVE_DoubleClick = Edit
+DEBUGARCHIVE_CustomDoubleClick =
+Project_Major_Version = 10
+Project_Minor_Version = 2
diff --git a/firmware/minitlu/simulation/scripts/modelsim.ini b/firmware/minitlu/simulation/scripts/modelsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..b025bbdacc06d8e98eb8be87f7020f1804ac766b
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/modelsim.ini
@@ -0,0 +1,1868 @@
+; Copyright 1991-2013 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+unimacro = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unimacro
+simprim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/simprim
+unisim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unisim
+xilinxcorelib = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/xilinxcorelib
+unimacro_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unimacro_ver
+simprims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/simprims_ver
+unisims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unisims_ver
+xilinxcorelib_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/xilinxcorelib_ver
+secureip = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/secureip
+
+[DefineOptionset]
+; Define optionset entries for the various compilers, vmake, and vsim.
+; These option sets can be used with the "-optionset <optionsetname>" syntax.
+; i.e.
+; vlog -optionset COMPILEDEBUG top.sv
+; vsim -optionset UVMDEBUG my_top
+;
+; Following are some useful examples.
+
+; define a vsim optionset for uvm debugging
+UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
+
+; define a vopt optionset for debugging
+VOPTDEBUG = +acc -debugdb
+
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl", "sccts", "iddp" and "atpi".
+; SVExtensions = uslt,spsl,sccts
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 20000
+
+; Set XPROP assertion fail limit. Default is 5.
+; Any positive integer, -1 for infinity.
+; XpropAssertionLimit = 5
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is 0 (disabled). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase
+DefaultRadix = hexadecimal
+DefaultRadixFlags = showbase
+; Set to 1 for make the signal_force VHDL and Verilog functions use the
+; default radix when processing the force value. Prior to 10.2 signal_force
+; used the default radix, now it always uses symbolic unless value explicitly indicates base
+;SignalForceFunctionUseDefaultRadix = 0
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Make VHDL packages in PDUs have there own copy of a package instead
+; of sharing the package between PDUs. By default share packages
+; VhdlSeparatePduPackage = 0
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+; The default is UVMControl = struct
+
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+; Specify the WildcardFilter setting.
+; A space separated list of object types to be excluded when performing
+; wildcard matches with log, wave, etc commands. The default value for this variable is:
+; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
+; See "Using the WildcardFilter Preference Variable" in the documentation for
+; details on how to use this variable and for descriptions of the filter types.
+WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
+
+; Specify the WildcardSizeThreshold setting.
+; This integer setting specifies the size at which objects will be excluded when
+; performing wildcard matches with log, wave, etc commands. Objects of size equal
+; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
+; matches. The size is a simple calculation of number of bits or items in the object.
+; The default value is 8k (8192). Setting this value to 0 will disable the checking
+; of object size against this threshold and allow all objects of any size to be logged.
+WildcardSizeThreshold = 8192
+
+; Specify whether warning messages are output when objects are filtered out due to the
+; WildcardSizeThreshold. The default is 0 (no messages generated).
+WildcardSizeThresholdVerbose = 0
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file.
+; Value is the number of seconds between updated. After at least the
+; interval number of seconds, the wlf file is flushed, ensuring that the data
+; is correct when viewed from a separate live viewer. Setting to 0 means no
+; updating. Default is 10 seconds, which has a tiny performance impact
+; WLFUpdateInterval = 10
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
+; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Specify the size of objects that will trigger "large object" messages
+; at log/wave/list time. The size calculation of the object is the same as that
+; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
+; Setting LargeObjectSize to 0 will disable these messages.
+; LargeObjectSize = 500000
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Set SystemC thread stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). The stack size for sc_thread depends
+; on the amount of data on the sc_thread stack and the memory required
+; to succesfully execute the thread.
+; ScStackSize = 1 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+; Print "simstats" result in Tcl list form
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStatsList = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; This option applies to condition and expression coverage UDP tables. It
+; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
+; If this option is used and a match occurs in more than one row in the UDP table,
+; none of the counts for all matching rows is incremented. By default, counts are
+; incremented for all matching rows.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Turn off automatic inclusion of VHDL records in toggle coverage.
+; Default is to include them.
+; ToggleVHDLRecords = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; FecCountLimit = 1
+
+; Limit the counts that are tracked for UDP Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; UdpCountLimit = 1
+
+; Control toggle coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
+; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; ToggleDeglitchPeriod = 10.0ps
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
+; and report. This variable sets the default value of type_option.merge_instances.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroupMergeInstancesDefault = 0
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Error message severity for suppressible errors that are detected in a
+; solve/before constraint.
+; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveBeforeErrorSeverity = 3
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable basic debug (with no
+; performance penalty). Set to 2 for enhanced debug (will result in slower
+; runtime performance).
+; SolveFailDebug = 0
+
+; Upon encountering a randomize() failure, generate a simplified testcase that
+; will reproduce the failure. Optionally output the testcase to a file.
+; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
+; is enabled (see above).
+; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
+; command line switch.
+; The default is OFF (do not generate a testcase). To enable testcase
+; generation, uncomment this variable. To redirect testcase generation to a
+; file, specify the name of the output file.
+; SolveFailTestcase =
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 2000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 2000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveACTMaxOps = 10000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMax[Tests|Ops] threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Specify the memory threshold for the System Verilog garbage collector.
+; The value is the number of megabytes of class objects that must accumulate
+; before the garbage collector is run.
+; The GCThreshold setting is used when class debug mode is disabled to allow
+; less frequent garbage collection and better simulation performance.
+; The GCThresholdClassDebug setting is used when class debug mode is enabled
+; to allow for more frequent garbage collection.
+; GCThreshold = 100
+; GCThresholdClassDebug = 5
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+; Controls the formatting of '%p' and '%P' conversion specification, used in $display
+; and similar system tasks.
+; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
+; The 'I' flag when present causes relevant data types to be expanded and indented into
+; a more readable format.
+; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
+; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
+; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
+; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
+; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
+; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
+; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
+; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
+; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
+; 7. Items 1-6 above can be combined as a comma separated list.
+; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5)
+; SVPrettyPrintFlags=I4S
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
+
+[utils]
+; Default Library Type
+; Set to determine the default type for a library created with "vlib"
+; 0 - legacy library using subdirectories for design units
+; 1 - archive library (deprecated)
+; 2 - flat library
+; DefaultLibType = 2
+
+; Archive Library Compact Value
+; Sets compaction trigger for archive libraries. The value is the percentage
+; of free space in the archive.
+; ArchiveLibCompact = 0.5
+
+; Flat Library Page Size
+; Set the size in bytes for flat library file pages. Very large libraries
+; may benefit from a larger value, at the expense of disk space.
+; FlatLibPageSize = 8192
+
+; Flat Library Page Cleanup Percentage
+; Set the percentage of total pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeleteThreshold.
+; FlatLibPageDeletePercentage = 50
+
+; Flat Library Page Cleanup Threshold
+; Set the number of pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeletePercentage.
+; FlatLibPageDeleteThreshold = 1000
+
diff --git a/firmware/minitlu/simulation/scripts/setup.sh b/firmware/minitlu/simulation/scripts/setup.sh
new file mode 100644
index 0000000000000000000000000000000000000000..391f528eba045bed4c4d2bf3323ae8295120d200
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/setup.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+export MODELSIM_ROOT="/software/CAD/Mentor/2013_2014/Questa/HDS_2012.2b/questasim/"
+export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/"
+export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/"
+
+vsim -c -do $REPOS_FW_DIR/ipbus/firmware/sim/scripts/setup_project.tcl
+cp -r $REPOS_FW_DIR/ipbus/firmware/ethernet/sim/modelsim_fli ./
+cd modelsim_fli
+./mac_fli_compile.sh
+cd ..
+ln -s modelsim_fli/mac_fli.so
+
diff --git a/firmware/minitlu/simulation/scripts/setup_project.tcl b/firmware/minitlu/simulation/scripts/setup_project.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..dd555fa2adf72c0279ad3ded581fa63c20eda946
--- /dev/null
+++ b/firmware/minitlu/simulation/scripts/setup_project.tcl
@@ -0,0 +1,24 @@
+# Creates a new Questa project for ipbus demo
+#
+# You will want to amend the path to compiled Xilinx libraries to suit
+# your system.
+#
+# Dave Newbold, April 2011
+#
+# $Id$
+
+set xlib_vhdl $::env(ISE_VHDL_MTI)
+set xlib_vlog $::env(ISE_VLOG_MTI)
+
+project new ./ ipbus_sim_demo
+vmap unisim $xlib_vhdl/unisim
+vmap unimacro $xlib_vhdl/unimacro
+vmap secureip $xlib_vlog/secureip
+vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
+
+source $::env(REPOS_FW_DIR)/ipbus/firmware/sim/scripts/addfiles_sim.tcl
+
+project calculateorder
+project close
+quit
+
diff --git a/firmware/minitlu/simulation_src/fmc-tlu_v0-1_test-bench.vhd b/firmware/minitlu/simulation_src/fmc-tlu_v0-1_test-bench.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6c6b70a7344739017d93e6962c3fd402cb948144
--- /dev/null
+++ b/firmware/minitlu/simulation_src/fmc-tlu_v0-1_test-bench.vhd
@@ -0,0 +1,182 @@
+--=============================================================================
+--! @file fmc-tlu_v0-1_test-bench.vhd
+--=============================================================================
+
+--! @brief Test-bench for FMC format mini-TLU for AIDA
+--
+--! @details
+--
+--! @author David Cussans, 31/07/12
+--! @date 11:49:20 02/21/2014
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY fmctlu_v0_1_testbench IS
+END fmctlu_v0_1_testbench;
+
+ARCHITECTURE behavior OF fmctlu_v0_1_testbench IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top_extphy
+ PORT(
+ busy_n_i : IN std_logic_vector(2 downto 0);
+ busy_p_i : IN std_logic_vector(2 downto 0);
+ cfd_discr_n_i : IN std_logic_vector(3 downto 0);
+ cfd_discr_p_i : IN std_logic_vector(3 downto 0);
+ dip_switch_i : IN std_logic_vector(3 downto 0);
+ dut_clk_n_i : IN std_logic_vector(2 downto 0);
+ dut_clk_p_i : IN std_logic_vector(2 downto 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector(7 downto 0);
+ sysclk_n_i : IN std_logic;
+ sysclk_p_i : IN std_logic;
+ threshold_discr_n_i : IN std_logic_vector(3 downto 0);
+ threshold_discr_p_i : IN std_logic_vector(3 downto 0);
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector(7 downto 0);
+ gpio_hdr : OUT std_logic_vector(7 downto 0);
+ leds_o : OUT std_logic_vector(3 downto 0);
+ phy_rstb_o : OUT std_logic;
+ reset_or_clk_n_o : OUT std_logic_vector(2 downto 0);
+ reset_or_clk_p_o : OUT std_logic_vector(2 downto 0);
+ triggers_n_o : OUT std_logic_vector(2 downto 0);
+ triggers_p_o : OUT std_logic_vector(2 downto 0);
+ extclk_n_b : INOUT std_logic;
+ extclk_p_b : INOUT std_logic;
+ i2c_scl_b : INOUT std_logic;
+ i2c_sda_b : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal busy_n_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal busy_p_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal cfd_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal cfd_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal dip_switch_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal dut_clk_n_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal dut_clk_p_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal gmii_rx_clk_i : std_logic := '0';
+ signal gmii_rx_dv_i : std_logic := '0';
+ signal gmii_rx_er_i : std_logic := '0';
+ signal gmii_rxd_i : std_logic_vector(7 downto 0) := (others => '0');
+ signal sysclk_n_i : std_logic := '0';
+ signal sysclk_p_i : std_logic := '0';
+ signal threshold_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal threshold_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal s_threshold_discr : std_logic_vector(3 downto 0) := (others => '0');
+
+ --BiDirs
+ signal extclk_n_b : std_logic;
+ signal extclk_p_b : std_logic;
+ signal i2c_scl_b : std_logic;
+ signal i2c_sda_b : std_logic;
+
+ --Outputs
+ signal gmii_gtx_clk_o : std_logic;
+ signal gmii_tx_en_o : std_logic;
+ signal gmii_tx_er_o : std_logic;
+ signal gmii_txd_o : std_logic_vector(7 downto 0);
+ signal gpio_hdr : std_logic_vector(7 downto 0);
+ signal leds_o : std_logic_vector(3 downto 0);
+ signal phy_rstb_o : std_logic;
+ signal reset_or_clk_n_o : std_logic_vector(2 downto 0);
+ signal reset_or_clk_p_o : std_logic_vector(2 downto 0);
+ signal triggers_n_o : std_logic_vector(2 downto 0);
+ signal triggers_p_o : std_logic_vector(2 downto 0);
+
+ signal sysclock : std_logic := '0';
+ constant sysclock_period : time := 5 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top_extphy PORT MAP (
+ busy_n_i => busy_n_i,
+ busy_p_i => busy_p_i,
+ cfd_discr_n_i => cfd_discr_n_i,
+ cfd_discr_p_i => cfd_discr_p_i,
+ dip_switch_i => dip_switch_i,
+ dut_clk_n_i => dut_clk_n_i,
+ dut_clk_p_i => dut_clk_p_i,
+ gmii_rx_clk_i => gmii_rx_clk_i,
+ gmii_rx_dv_i => gmii_rx_dv_i,
+ gmii_rx_er_i => gmii_rx_er_i,
+ gmii_rxd_i => gmii_rxd_i,
+ sysclk_n_i => sysclk_n_i,
+ sysclk_p_i => sysclk_p_i,
+ threshold_discr_n_i => threshold_discr_n_i,
+ threshold_discr_p_i => threshold_discr_p_i,
+ gmii_gtx_clk_o => gmii_gtx_clk_o,
+ gmii_tx_en_o => gmii_tx_en_o,
+ gmii_tx_er_o => gmii_tx_er_o,
+ gmii_txd_o => gmii_txd_o,
+ gpio_hdr => gpio_hdr,
+ leds_o => leds_o,
+ phy_rstb_o => phy_rstb_o,
+ reset_or_clk_n_o => reset_or_clk_n_o,
+ reset_or_clk_p_o => reset_or_clk_p_o,
+ triggers_n_o => triggers_n_o,
+ triggers_p_o => triggers_p_o,
+ extclk_n_b => extclk_n_b,
+ extclk_p_b => extclk_p_b,
+ i2c_scl_b => i2c_scl_b,
+ i2c_sda_b => i2c_sda_b
+ );
+
+ -- Clock process definitions
+ sysclock_process :process
+ begin
+ sysclock <= '0';
+ wait for sysclock_period/2;
+ sysclock <= '1';
+ wait for sysclock_period/2;
+ end process;
+ sysclk_n_i <= not sysclock;
+ sysclk_p_i <= sysclock;
+
+
+ -- Generate pulses
+ cmp_pulseGen: entity work.pmtPulseGenerator
+ generic map (
+ g_NUM_CHANNELS => 4)
+ port map (
+ pulses_o => s_threshold_discr,
+ numPulses_i => 50,
+ averagePulseInterval_i => 10 us,
+ averagePulseWidth_i => 10 ns,
+ pulseJitter_i => 2 ns,
+ sysclock_i => sysclock,
+ simulationDone_o => open);
+
+ threshold_discr_p_i <= s_threshold_discr;
+ threshold_discr_n_i <= not s_threshold_discr;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for sysclock_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/firmware/minitlu/simulation_src/pmtPulseGenerator_rtl.vhd b/firmware/minitlu/simulation_src/pmtPulseGenerator_rtl.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d95688bdf409b2f667ddfefa5ff5078aeb9cae21
--- /dev/null
+++ b/firmware/minitlu/simulation_src/pmtPulseGenerator_rtl.vhd
@@ -0,0 +1,152 @@
+--=============================================================================
+--! @file pmtPulseGenerator_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+-------------------------------------------------------------------------------
+-- VHDL Architecture pmtPulseGenerator.rtl
+--
+--! @brief Produce a series of random pulses. Timing can be optionally
+--! referered to system clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--
+--! @date 4/3/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+use IEEE.Math_real.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+entity pmtPulseGenerator is
+
+ generic (
+ g_NUM_CHANNELS : positive := 4); -- --! Number of signal lines
+
+ port (
+ pulses_o : out std_logic_vector(g_NUM_CHANNELS-1 downto 0); --! Output pulses
+ -- pulseRecord_o : out t_pulseRecord ; --! Record describing the output pulses
+ numPulses_i : in positive; --! Number of pulses/events to generate
+ averagePulseInterval_i : in time; --! Mean interval between pulses
+ averagePulseWidth_i : in time; --! Mean pulse width (must be smaller than interval)
+ pulseJitter_i : in time; --! Time spread between outputs.
+ sysclock_i : in std_logic; -- --! Pulses can be optionally referred to rising edge
+ simulationDone_o : out boolean --! Goes high when pulse generation is finished
+ );
+end pmtPulseGenerator;
+
+ARCHITECTURE behavior OF pmtPulseGenerator IS
+
+ signal s_masterPulse : std_logic := '0';
+
+BEGIN
+
+ -- Generate "master" pulse
+ stim_proc: process
+ variable v_seed1 : POSITIVE := 28;
+ variable v_seed2 : POSITIVE := 17;
+ variable v_pulseWidth , v_pulseLow : time ;
+ variable Rand : real;
+
+ begin
+
+ assert ( averagePulseInterval_i > averagePulseWidth_i ) report "Pulse width can't be larger than pulse interval!!" severity failure;
+
+ simulationDone_o <= False;
+ s_masterPulse <= '0';
+
+ for I in 1 to numPulses_i loop
+
+ -- wait for random gap between pulses
+ uniform(v_seed1, v_seed2, Rand);
+ v_pulseLow := Rand * (averagePulseInterval_i - averagepulseWidth_i);
+ wait for v_pulseLow;
+
+ s_masterPulse <= '1'; --! Take pulse high.
+
+ -- wait for random pulse width
+ uniform(v_seed1, v_seed2, Rand);
+ v_pulseWidth := Rand * averagePulseWidth_i;
+ wait for v_pulseWidth;
+
+ s_masterPulse <= '0'; --! Return pulse low.
+
+ end loop;
+
+ simulationDone_o <= True;
+ wait;
+ end process;
+
+ --! Generate separate outputs that follow the main pulse with timing jitter.
+ gen_PulseOutputs: for v_output in 0 to g_NUM_CHANNELS-1 generate
+ -- purpose: Sets the individual output pulses based on master pulse
+ -- output: pulses_o(v_output)
+ p_setOutputs: process
+ variable v_timeOffset : time := 0 ns; -- --! offset between master pulse changing and output changing.
+ variable Rand : real;
+ variable v_seed1 : POSITIVE := 19*(v_output+1);
+ variable v_seed2 : POSITIVE := 47*(v_output+1);
+
+ begin -- process p_setOutputs
+
+ -- set the output low
+ -- pulses_o(v_output) <= '0';
+
+ wait on s_masterPulse;
+
+ if rising_edge(s_masterPulse) then
+
+ --report "Pulse output proc: found rising edge" severity note;
+
+ -- Generate some jitter
+ uniform(v_seed1, v_seed2, Rand);
+ v_timeOffset := Rand * pulseJitter_i;
+
+ --report "Pulse output proc: waiting to set output pulse" severity note;
+
+ -- wait for that jitter
+ wait for v_timeOffset;
+
+ -- set the output high
+ pulses_o(v_output) <= '1';
+
+ else
+ -- falling edge....
+ -- wait for jitter time
+ wait for v_timeOffset;
+
+ -- return the output low.
+ pulses_o(v_output) <= '0';
+
+ end if;
+
+ end process p_setOutputs;
+
+ end generate gen_PulseOutputs;
+END;
diff --git a/firmware/minitlu/tlu_scripts.zip b/firmware/minitlu/tlu_scripts.zip
new file mode 100644
index 0000000000000000000000000000000000000000..5f63e8430ec64bdf4ef5a4f20512022254950368
Binary files /dev/null and b/firmware/minitlu/tlu_scripts.zip differ
diff --git a/firmware/minitlu/ucf/SP601_RevC_annotated_master_ucf_8-28-09.ucf b/firmware/minitlu/ucf/SP601_RevC_annotated_master_ucf_8-28-09.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..522eef37936025d2c4100427f95b05d82e24e25e
--- /dev/null
+++ b/firmware/minitlu/ucf/SP601_RevC_annotated_master_ucf_8-28-09.ucf
@@ -0,0 +1,252 @@
+NET "CPU_RESET" LOC = "N4"; ## 2 on SW9 pushbutton
+##
+NET "DDR2_A0" LOC = "J7"; | IOSTANDARD = SSTL18_II ; ## M8 on U2
+NET "DDR2_A1" LOC = "J6"; | IOSTANDARD = SSTL18_II ; ## M3 on U2
+NET "DDR2_A2" LOC = "H5"; | IOSTANDARD = SSTL18_II ; ## M7 on U2
+NET "DDR2_A3" LOC = "L7"; | IOSTANDARD = SSTL18_II ; ## N2 on U2
+NET "DDR2_A4" LOC = "F3"; | IOSTANDARD = SSTL18_II ; ## N8 on U2
+NET "DDR2_A5" LOC = "H4"; | IOSTANDARD = SSTL18_II ; ## N3 on U2
+NET "DDR2_A6" LOC = "H3"; | IOSTANDARD = SSTL18_II ; ## N7 on U2
+NET "DDR2_A7" LOC = "H6"; | IOSTANDARD = SSTL18_II ; ## P2 on U2
+NET "DDR2_A8" LOC = "D2"; | IOSTANDARD = SSTL18_II ; ## P8 on U2
+NET "DDR2_A9" LOC = "D1"; | IOSTANDARD = SSTL18_II ; ## P3 on U2
+NET "DDR2_A10" LOC = "F4"; | IOSTANDARD = SSTL18_II ; ## M2 on U2
+NET "DDR2_A11" LOC = "D3"; | IOSTANDARD = SSTL18_II ; ## P7 on U2
+NET "DDR2_A12" LOC = "G6"; | IOSTANDARD = SSTL18_II ; ## R2 on U2
+NET "DDR2_BA0" LOC = "F2"; | IOSTANDARD = SSTL18_II ; ## L2 on U2
+NET "DDR2_BA1" LOC = "F1"; | IOSTANDARD = SSTL18_II ; ## L3 on U2
+NET "DDR2_BA2" LOC = "E1"; | IOSTANDARD = SSTL18_II ; ## L1 on U2
+NET "DDR2_CAS_B" LOC = "K5"; | IOSTANDARD = SSTL18_II ; ## L7 on U2
+NET "DDR2_CKE" LOC = "H7"; | IOSTANDARD = SSTL18_II ; ## K2 on U2
+NET "DDR2_CLK_N" LOC = "G1"; | IOSTANDARD = SSTL18_II ; ## K8 on U2
+NET "DDR2_CLK_P" LOC = "G3"; | IOSTANDARD = SSTL18_II ; ## J8 on U2
+NET "DDR2_DQ0" LOC = "L2"; | IOSTANDARD = SSTL18_II ; ## G8 on U2
+NET "DDR2_DQ1" LOC = "L1"; | IOSTANDARD = SSTL18_II ; ## G2 on U2
+NET "DDR2_DQ2" LOC = "K2"; | IOSTANDARD = SSTL18_II ; ## H7 on U2
+NET "DDR2_DQ3" LOC = "K1"; | IOSTANDARD = SSTL18_II ; ## H3 on U2
+NET "DDR2_DQ4" LOC = "H2"; | IOSTANDARD = SSTL18_II ; ## H1 on U2
+NET "DDR2_DQ5" LOC = "H1"; | IOSTANDARD = SSTL18_II ; ## H9 on U2
+NET "DDR2_DQ6" LOC = "J3"; | IOSTANDARD = SSTL18_II ; ## F1 on U2
+NET "DDR2_DQ7" LOC = "J1"; | IOSTANDARD = SSTL18_II ; ## F9 on U2
+NET "DDR2_DQ8" LOC = "M3"; | IOSTANDARD = SSTL18_II ; ## C8 on U2
+NET "DDR2_DQ9" LOC = "M1"; | IOSTANDARD = SSTL18_II ; ## C2 on U2
+NET "DDR2_DQ10" LOC = "N2"; | IOSTANDARD = SSTL18_II ; ## D7 on U2
+NET "DDR2_DQ11" LOC = "N1"; | IOSTANDARD = SSTL18_II ; ## D3 on U2
+NET "DDR2_DQ12" LOC = "T2"; | IOSTANDARD = SSTL18_II ; ## D1 on U2
+NET "DDR2_DQ13" LOC = "T1"; | IOSTANDARD = SSTL18_II ; ## D9 on U2
+NET "DDR2_DQ14" LOC = "U2"; | IOSTANDARD = SSTL18_II ; ## B1 on U2
+NET "DDR2_DQ15" LOC = "U1"; | IOSTANDARD = SSTL18_II ; ## B9 on U2
+NET "DDR2_LDM" LOC = "K3"; | IOSTANDARD = SSTL18_II ; ## F3 on U2
+NET "DDR2_LDQS_N" LOC = "L3"; | IOSTANDARD = SSTL18_II ; ## E8 on U2
+NET "DDR2_LDQS_P" LOC = "L4"; | IOSTANDARD = SSTL18_II ; ## F7 on U2
+NET "DDR2_ODT" LOC = "K6"; | IOSTANDARD = SSTL18_II ; ## K9 on U2
+NET "DDR2_RAS_B" LOC = "L5"; | IOSTANDARD = SSTL18_II ; ## K7 on U2
+NET "DDR2_UDM" LOC = "K4"; | IOSTANDARD = SSTL18_II ; ## B3 on U2
+NET "DDR2_UDQS_N" LOC = "P1"; | IOSTANDARD = SSTL18_II ; ## A8 on U2
+NET "DDR2_UDQS_P" LOC = "P2"; | IOSTANDARD = SSTL18_II ; ## B7 on U2
+NET "DDR2_WE_B" LOC = "E3"; | IOSTANDARD = SSTL18_II ; ## K3 on U2
+##
+NET "FLASH_A0" LOC = "K18"; ## 32 on U10
+NET "FLASH_A1" LOC = "K17"; ## 28 on U10
+NET "FLASH_A2" LOC = "J18"; ## 27 on U10
+NET "FLASH_A3" LOC = "J16"; ## 26 on U10
+NET "FLASH_A4" LOC = "G18"; ## 25 on U10
+NET "FLASH_A5" LOC = "G16"; ## 24 on U10
+NET "FLASH_A6" LOC = "H16"; ## 23 on U10
+NET "FLASH_A7" LOC = "H15"; ## 22 on U10
+NET "FLASH_A8" LOC = "H14"; ## 20 on U10
+NET "FLASH_A9" LOC = "H13"; ## 19 on U10
+NET "FLASH_A10" LOC = "F18"; ## 18 on U10
+NET "FLASH_A11" LOC = "F17"; ## 17 on U10
+NET "FLASH_A12" LOC = "K13"; ## 13 on U10
+NET "FLASH_A13" LOC = "K12"; ## 12 on U10
+NET "FLASH_A14" LOC = "E18"; ## 11 on U10
+NET "FLASH_A15" LOC = "E16"; ## 10 on U10
+NET "FLASH_A16" LOC = "G13"; ## 8 on U10
+NET "FLASH_A17" LOC = "H12"; ## 7 on U10
+NET "FLASH_A18" LOC = "D18"; ## 6 on U10
+NET "FLASH_A19" LOC = "D17"; ## 5 on U10
+NET "FLASH_A20" LOC = "G14"; ## 4 on U10
+NET "FLASH_A21" LOC = "F14"; ## 3 on U10
+NET "FLASH_A22" LOC = "C18"; ## 1 on U10
+NET "FLASH_A23" LOC = "C17"; ## 30 on U10
+NET "FLASH_A24" LOC = "F16"; ## 56 on U10
+NET "FLASH_CE_B" LOC = "L17"; ## 14 on U10
+NET "FLASH_D3" LOC = "U5"; ## 40 on U10
+NET "FLASH_D4" LOC = "V5"; ## 44 on U10
+NET "FLASH_D5" LOC = "R3"; ## 46 on U10
+NET "FLASH_D6" LOC = "T3"; ## 49 on U10
+NET "FLASH_D7" LOC = "R5"; ## 51 on U10
+NET "FLASH_OE_B" LOC = "L18"; ## 54 on U10
+NET "FLASH_WE_B" LOC = "M16"; ## 55 on U10
+##
+NET "FMC_CLK0_M2C_N" LOC = "A10"; ## H5 on J1
+NET "FMC_CLK0_M2C_P" LOC = "C10"; ## H4 on J1
+NET "FMC_CLK1_M2C_N" LOC = "V9"; ## G3 on J1
+NET "FMC_CLK1_M2C_P" LOC = "T9"; ## G2 on J1
+NET "FMC_LA00_CC_N" LOC = "C9"; ## G7 on J1
+NET "FMC_LA00_CC_P" LOC = "D9"; ## G6 on J1
+NET "FMC_LA01_CC_N" LOC = "C11"; ## D9 on J1
+NET "FMC_LA01_CC_P" LOC = "D11"; ## D8 on J1
+NET "FMC_LA02_N" LOC = "A15"; ## H8 on J1
+NET "FMC_LA02_P" LOC = "C15"; ## H7 on J1
+NET "FMC_LA03_N" LOC = "A13"; ## G10 on J1
+NET "FMC_LA03_P" LOC = "C13"; ## G9 on J1
+NET "FMC_LA04_N" LOC = "A16"; ## H11 on J1
+NET "FMC_LA04_P" LOC = "B16"; ## H10 on J1
+NET "FMC_LA05_N" LOC = "A14"; ## D12 on J1
+NET "FMC_LA05_P" LOC = "B14"; ## D11 on J1
+NET "FMC_LA06_N" LOC = "C12"; ## C11 on J1
+NET "FMC_LA06_P" LOC = "D12"; ## C10 on J1
+NET "FMC_LA07_N" LOC = "E8"; ## H14 on J1
+NET "FMC_LA07_P" LOC = "E7"; ## H13 on J1
+NET "FMC_LA08_N" LOC = "E11"; ## G13 on J1
+NET "FMC_LA08_P" LOC = "F11"; ## G12 on J1
+NET "FMC_LA09_N" LOC = "F10"; ## D15 on J1
+NET "FMC_LA09_P" LOC = "G11"; ## D14 on J1
+NET "FMC_LA10_N" LOC = "C8"; ## C15 on J1
+NET "FMC_LA10_P" LOC = "D8"; ## C14 on J1
+NET "FMC_LA11_N" LOC = "A12"; ## H17 on J1
+NET "FMC_LA11_P" LOC = "B12"; ## H16 on J1
+NET "FMC_LA12_N" LOC = "C6"; ## G16 on J1
+NET "FMC_LA12_P" LOC = "D6"; ## G15 on J1
+NET "FMC_LA13_N" LOC = "A11"; ## D18 on J1
+NET "FMC_LA13_P" LOC = "B11"; ## D17 on J1
+NET "FMC_LA14_N" LOC = "A2"; ## C19 on J1
+NET "FMC_LA14_P" LOC = "B2"; ## C18 on J1
+NET "FMC_LA15_N" LOC = "F9"; ## H20 on J1
+NET "FMC_LA15_P" LOC = "G9"; ## H19 on J1
+NET "FMC_LA16_N" LOC = "A7"; ## G19 on J1
+NET "FMC_LA16_P" LOC = "C7"; ## G18 on J1
+NET "FMC_LA17_CC_N" LOC = "T8"; ## D21 on J1
+NET "FMC_LA17_CC_P" LOC = "R8"; ## D20 on J1
+NET "FMC_LA18_CC_N" LOC = "T10"; ## C23 on J1
+NET "FMC_LA18_CC_P" LOC = "R10"; ## C22 on J1
+NET "FMC_LA19_N" LOC = "P7"; ## H23 on J1
+NET "FMC_LA19_P" LOC = "N6"; ## H22 on J1
+NET "FMC_LA20_N" LOC = "P8"; ## G22 on J1
+NET "FMC_LA20_P" LOC = "N7"; ## G21 on J1
+NET "FMC_LA21_N" LOC = "V4"; ## H26 on J1
+NET "FMC_LA21_P" LOC = "T4"; ## H25 on J1
+NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
+NET "FMC_LA22_P" LOC = "R7"; ## G24 on J1
+NET "FMC_LA23_N" LOC = "P6"; ## D24 on J1
+NET "FMC_LA23_P" LOC = "N5"; ## D23 on J1
+NET "FMC_LA24_N" LOC = "V8"; ## H29 on J1
+NET "FMC_LA24_P" LOC = "U8"; ## H28 on J1
+NET "FMC_LA25_N" LOC = "N11"; ## G28 on J1
+NET "FMC_LA25_P" LOC = "M11"; ## G27 on J1
+NET "FMC_LA26_N" LOC = "V7"; ## D27 on J1
+NET "FMC_LA26_P" LOC = "U7"; ## D26 on J1
+NET "FMC_LA27_N" LOC = "T11"; ## C27 on J1
+NET "FMC_LA27_P" LOC = "R11"; ## C26 on J1
+NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
+NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
+NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
+NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
+NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
+NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
+NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
+NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
+NET "FMC_LA32_N" LOC = "V15"; ## H38 on J1
+NET "FMC_LA32_P" LOC = "U15"; ## H37 on J1
+NET "FMC_LA33_N" LOC = "N9"; ## G37 on J1
+NET "FMC_LA33_P" LOC = "M10"; ## G36 on J1
+NET "FMC_PRSNT_M2C_L" LOC = "U13"; ## H2 on J1
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3"; ## D1 on J1, 16 on U10
+##
+NET "FPGA_AWAKE" LOC = "P15"; ## 2 on DS8 LED
+NET "FPGA_CCLK" LOC = "R15"; ## 16 on U17, 7 on J12
+NET "FPGA_CMP_CLK" LOC = "U16"; ## 3 on J3
+NET "FPGA_CMP_CS_B" LOC = "P13"; ## 4 on J3
+NET "FPGA_CMP_MOSI" LOC = "V16"; ## 2 on J3
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13"; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14"; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14"; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_DONE" LOC = "V17"; ## 2 on DS9 LED
+NET "FPGA_HSWAPEN" LOC = "D4"; ## 1 on R81 100 ohm to GND
+NET "FPGA_INIT_B" LOC = "U3"; ## 1 on DS10 (thru series R90 27.4 ohm)
+NET "FPGA_M0_CMP_MISO" LOC = "T15"; ## 1 on J3, 1 on SW2 DIP Sw
+NET "FPGA_M1" LOC = "N12"; ## 2 on SW2 DIP Sw
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13"; ## 15 on U17, 5 on J12
+NET "FPGA_ONCHIP_TERM1" LOC = "L6"; ## ZIO no connect (R86 is DNP)
+NET "FPGA_ONCHIP_TERM2" LOC = "C2"; ## RZQ 100 ohm to GND
+NET "FPGA_PROG_B" LOC = "V2"; ## 1 on SW3 pushbutton
+NET "FPGA_SUSPEND" LOC = "R16"; ## 2 on J14
+NET "FPGA_TCK_BUF" LOC = "A17"; ## 14 on U21, D29 on J1
+NET "FPGA_TDI_BUF" LOC = "D15"; ## 18 on U21
+NET "FPGA_TDO" LOC = "D16"; ## 1 on J4, D30 on J1
+NET "FPGA_TMS_BUF" LOC = "B18"; ## 16 on U21, D31 on J1
+NET "FPGA_VTEMP" LOC = "P3"; ## 2 on R87 150 ohm p/u to VCC1V8
+##
+NET "GPIO_BUTTON0" LOC = "P4"; ## 2 on SW6 pushbutton
+NET "GPIO_BUTTON1" LOC = "F6"; ## 2 on SW4 pushbutton
+NET "GPIO_BUTTON2" LOC = "E4"; ## 2 on SW5 pushbutton
+NET "GPIO_BUTTON3" LOC = "F5"; ## 2 on SW7 pushbutton
+##
+NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
+NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
+NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
+NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
+NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
+NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
+NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
+NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
+##
+NET "GPIO_LED_0" LOC = "E13"; ## 2 on DS11 LED
+NET "GPIO_LED_1" LOC = "C14"; ## 2 on DS12 LED
+NET "GPIO_LED_2" LOC = "C4"; ## 2 on DS13 LED
+NET "GPIO_LED_3" LOC = "A4"; ## 2 on DS14 LED
+##
+NET "GPIO_SWITCH_0" LOC = "D14"; ## 1 on SW8 DIP Sw
+NET "GPIO_SWITCH_1" LOC = "E12"; ## 2 on SW8 DIP Sw
+NET "GPIO_SWITCH_2" LOC = "F12"; ## 3 on SW8 DIP Sw
+NET "GPIO_SWITCH_3" LOC = "V13"; ## 4 on SW8 DIP Sw
+##
+NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
+NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
+##
+NET "PHY_COL" LOC = "L14"; ## 114 on U3
+NET "PHY_CRS" LOC = "M13"; ## 115 on U3
+NET "PHY_INT" LOC = "J13"; ## 32 on U3
+NET "PHY_MDC" LOC = "N14"; ## 35 on U3
+NET "PHY_MDIO" LOC = "P16"; ## 33 on U3
+NET "PHY_RESET" LOC = "L13"; ## 36 on U3
+NET "PHY_RXCLK" LOC = "L16"; ## 7 on U3
+NET "PHY_RXCTL_RXDV" LOC = "N18"; ## 4 on U3
+NET "PHY_RXD0" LOC = "M14"; ## 3 on U3
+NET "PHY_RXD1" LOC = "U18"; ## 128 on U3
+NET "PHY_RXD2" LOC = "U17"; ## 126 on U3
+NET "PHY_RXD3" LOC = "T18"; ## 125 on U3
+NET "PHY_RXD4" LOC = "T17"; ## 124 on U3
+NET "PHY_RXD5" LOC = "N16"; ## 123 on U3
+NET "PHY_RXD6" LOC = "N15"; ## 121 on U3
+NET "PHY_RXD7" LOC = "P18"; ## 120 on U3
+NET "PHY_RXER" LOC = "P17"; ## 8 on U3
+NET "PHY_TXCLK" LOC = "B9"; ## 10 on U3
+NET "PHY_TXCTL_TXEN" LOC = "B8"; ## 16 on U3
+NET "PHY_TXC_GTXCLK" LOC = "A9"; ## 14 on U3
+NET "PHY_TXD0" LOC = "F8"; ## 18 on U3
+NET "PHY_TXD1" LOC = "G8"; ## 19 on U3
+NET "PHY_TXD2" LOC = "A6"; ## 20 on U3
+NET "PHY_TXD3" LOC = "B6"; ## 24 on U3
+NET "PHY_TXD4" LOC = "E6"; ## 25 on U3
+NET "PHY_TXD5" LOC = "F7"; ## 26 on U3
+NET "PHY_TXD6" LOC = "A5"; ## 28 on U3
+NET "PHY_TXD7" LOC = "C5"; ## 29 on U3
+NET "PHY_TXER" LOC = "A8"; ## 13 on U3
+##
+NET "SMACLK_N" LOC = "H18"; ## 1 on J8 SMA
+NET "SMACLK_P" LOC = "H17"; ## 1 on J7 SMA
+##
+NET "SPI_CS_B" LOC = "V3"; ## 1 on J15, 4 on J12
+##
+NET "SYSCLK_N" LOC = "K16"; ## 5 on U5 EG2121CA, 5 of U20 SI500D (DNP)
+NET "SYSCLK_P" LOC = "K15"; ## 6 on U5 EG2121CA, 4 of U20 SI500D (DNP)
+##
+NET "USB_1_CTS" LOC = "U10"; ## 22 on U4
+NET "USB_1_RTS" LOC = "T5"; ## 23 on U4
+NET "USB_1_RX" LOC = "L12"; ## 24 on U4
+NET "USB_1_TX" LOC = "K14"; ## 25 on U4
+##
+NET "USER_CLOCK" LOC = "V10"; ## 5 on X2 USER OSC Socket
\ No newline at end of file
diff --git a/firmware/minitlu/ucf/SP601_fmc_connections.ucf b/firmware/minitlu/ucf/SP601_fmc_connections.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..224e63aef1b509ea9408a50aafabe97a8ed54c56
--- /dev/null
+++ b/firmware/minitlu/ucf/SP601_fmc_connections.ucf
@@ -0,0 +1,73 @@
+NET "FMC_CLK0_M2C_N" LOC = "A10"; ## H5 on J1
+NET "FMC_CLK0_M2C_P" LOC = "C10"; ## H4 on J1
+NET "FMC_CLK1_M2C_N" LOC = "V9"; ## G3 on J1
+NET "FMC_CLK1_M2C_P" LOC = "T9"; ## G2 on J1
+NET "FMC_LA00_CC_N" LOC = "C9"; ## G7 on J1
+NET "FMC_LA00_CC_P" LOC = "D9"; ## G6 on J1
+NET "FMC_LA01_CC_N" LOC = "C11"; ## D9 on J1
+NET "FMC_LA01_CC_P" LOC = "D11"; ## D8 on J1
+NET "FMC_LA02_N" LOC = "A15"; ## H8 on J1
+NET "FMC_LA02_P" LOC = "C15"; ## H7 on J1
+NET "FMC_LA03_N" LOC = "A13"; ## G10 on J1
+NET "FMC_LA03_P" LOC = "C13"; ## G9 on J1
+NET "FMC_LA04_N" LOC = "A16"; ## H11 on J1
+NET "FMC_LA04_P" LOC = "B16"; ## H10 on J1
+NET "FMC_LA05_N" LOC = "A14"; ## D12 on J1
+NET "FMC_LA05_P" LOC = "B14"; ## D11 on J1
+NET "FMC_LA06_N" LOC = "C12"; ## C11 on J1
+NET "FMC_LA06_P" LOC = "D12"; ## C10 on J1
+NET "FMC_LA07_N" LOC = "E8"; ## H14 on J1
+NET "FMC_LA07_P" LOC = "E7"; ## H13 on J1
+NET "FMC_LA08_N" LOC = "E11"; ## G13 on J1
+NET "FMC_LA08_P" LOC = "F11"; ## G12 on J1
+NET "FMC_LA09_N" LOC = "F10"; ## D15 on J1
+NET "FMC_LA09_P" LOC = "G11"; ## D14 on J1
+NET "FMC_LA10_N" LOC = "C8"; ## C15 on J1
+NET "FMC_LA10_P" LOC = "D8"; ## C14 on J1
+NET "FMC_LA11_N" LOC = "A12"; ## H17 on J1
+NET "FMC_LA11_P" LOC = "B12"; ## H16 on J1
+NET "FMC_LA12_N" LOC = "C6"; ## G16 on J1
+NET "FMC_LA12_P" LOC = "D6"; ## G15 on J1
+NET "FMC_LA13_N" LOC = "A11"; ## D18 on J1
+NET "FMC_LA13_P" LOC = "B11"; ## D17 on J1
+NET "FMC_LA14_N" LOC = "A2"; ## C19 on J1
+NET "FMC_LA14_P" LOC = "B2"; ## C18 on J1
+NET "FMC_LA15_N" LOC = "F9"; ## H20 on J1
+NET "FMC_LA15_P" LOC = "G9"; ## H19 on J1
+NET "FMC_LA16_N" LOC = "A7"; ## G19 on J1
+NET "FMC_LA16_P" LOC = "C7"; ## G18 on J1
+NET "FMC_LA17_CC_N" LOC = "T8"; ## D21 on J1
+NET "FMC_LA17_CC_P" LOC = "R8"; ## D20 on J1
+NET "FMC_LA18_CC_N" LOC = "T10"; ## C23 on J1
+NET "FMC_LA18_CC_P" LOC = "R10"; ## C22 on J1
+NET "FMC_LA19_N" LOC = "P7"; ## H23 on J1
+NET "FMC_LA19_P" LOC = "N6"; ## H22 on J1
+NET "FMC_LA20_N" LOC = "P8"; ## G22 on J1
+NET "FMC_LA20_P" LOC = "N7"; ## G21 on J1
+NET "FMC_LA21_N" LOC = "V4"; ## H26 on J1
+NET "FMC_LA21_P" LOC = "T4"; ## H25 on J1
+NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
+NET "FMC_LA22_P" LOC = "R7"; ## G24 on J1
+NET "FMC_LA23_N" LOC = "P6"; ## D24 on J1
+NET "FMC_LA23_P" LOC = "N5"; ## D23 on J1
+NET "FMC_LA24_N" LOC = "V8"; ## H29 on J1
+NET "FMC_LA24_P" LOC = "U8"; ## H28 on J1
+NET "FMC_LA25_N" LOC = "N11"; ## G28 on J1
+NET "FMC_LA25_P" LOC = "M11"; ## G27 on J1
+NET "FMC_LA26_N" LOC = "V7"; ## D27 on J1
+NET "FMC_LA26_P" LOC = "U7"; ## D26 on J1
+NET "FMC_LA27_N" LOC = "T11"; ## C27 on J1
+NET "FMC_LA27_P" LOC = "R11"; ## C26 on J1
+NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
+NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
+NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
+NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
+NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
+NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
+NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
+NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
+NET "FMC_LA32_N" LOC = "V15"; ## H38 on J1
+NET "FMC_LA32_P" LOC = "U15"; ## H37 on J1
+NET "FMC_LA33_N" LOC = "N9"; ## G37 on J1
+NET "FMC_LA33_P" LOC = "M10"; ## G36 on J1
+
diff --git a/firmware/minitlu/ucf/SP601_fmc_connections.xlsx b/firmware/minitlu/ucf/SP601_fmc_connections.xlsx
new file mode 100644
index 0000000000000000000000000000000000000000..ab8d0fdadc39c3878f139dfbd188cf0d7518d76f
Binary files /dev/null and b/firmware/minitlu/ucf/SP601_fmc_connections.xlsx differ
diff --git a/firmware/minitlu/ucf/SP601_fmc_connections_v2.ucf b/firmware/minitlu/ucf/SP601_fmc_connections_v2.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..ee14437327ca4dbc7fd330448a3c4e1b1deb2210
--- /dev/null
+++ b/firmware/minitlu/ucf/SP601_fmc_connections_v2.ucf
@@ -0,0 +1,94 @@
+NET "FMC_CLK0_M2C_N" LOC = "A10"; ## H5 on J1
+NET "FMC_CLK0_M2C_P" LOC = "C10"; ## H4 on J1
+NET "FMC_CLK1_M2C_N" LOC = "V9"; ## G3 on J1
+NET "FMC_CLK1_M2C_P" LOC = "T9"; ## G2 on J1
+NET "FMC_LA00_CC_N" LOC = "C9"; ## G7 on J1
+NET "FMC_LA00_CC_P" LOC = "D9"; ## G6 on J1
+NET "FMC_LA01_CC_N" LOC = "C11"; ## D9 on J1
+NET "FMC_LA01_CC_P" LOC = "D11"; ## D8 on J1
+NET "FMC_LA02_N" LOC = "A15"; ## H8 on J1
+NET "FMC_LA02_P" LOC = "C15"; ## H7 on J1
+NET "FMC_LA03_N" LOC = "A13"; ## G10 on J1
+NET "FMC_LA03_P" LOC = "C13"; ## G9 on J1
+NET "FMC_LA04_N" LOC = "A16"; ## H11 on J1
+NET "FMC_LA04_P" LOC = "B16"; ## H10 on J1
+NET "FMC_LA05_N" LOC = "A14"; ## D12 on J1
+NET "FMC_LA05_P" LOC = "B14"; ## D11 on J1
+NET "FMC_LA06_N" LOC = "C12"; ## C11 on J1
+NET "FMC_LA06_P" LOC = "D12"; ## C10 on J1
+NET "FMC_LA07_N" LOC = "E8"; ## H14 on J1
+NET "FMC_LA07_P" LOC = "E7"; ## H13 on J1
+NET "FMC_LA08_N" LOC = "E11"; ## G13 on J1
+NET "FMC_LA08_P" LOC = "F11"; ## G12 on J1
+NET "FMC_LA09_N" LOC = "F10"; ## D15 on J1
+NET "FMC_LA09_P" LOC = "G11"; ## D14 on J1
+NET "FMC_LA10_N" LOC = "C8"; ## C15 on J1
+NET "FMC_LA10_P" LOC = "D8"; ## C14 on J1
+NET "FMC_LA11_N" LOC = "A12"; ## H17 on J1
+NET "FMC_LA11_P" LOC = "B12"; ## H16 on J1
+NET "FMC_LA12_N" LOC = "C6"; ## G16 on J1
+NET "FMC_LA12_P" LOC = "D6"; ## G15 on J1
+NET "FMC_LA13_N" LOC = "A11"; ## D18 on J1
+NET "FMC_LA13_P" LOC = "B11"; ## D17 on J1
+NET "FMC_LA14_N" LOC = "A2"; ## C19 on J1
+NET "FMC_LA14_P" LOC = "B2"; ## C18 on J1
+NET "FMC_LA15_N" LOC = "F9"; ## H20 on J1
+NET "FMC_LA15_P" LOC = "G9"; ## H19 on J1
+NET "FMC_LA16_N" LOC = "A7"; ## G19 on J1
+NET "FMC_LA16_P" LOC = "C7"; ## G18 on J1
+NET "FMC_LA17_CC_N" LOC = "T8"; ## D21 on J1
+NET "FMC_LA17_CC_P" LOC = "R8"; ## D20 on J1
+NET "FMC_LA18_CC_N" LOC = "T10"; ## C23 on J1
+NET "FMC_LA18_CC_P" LOC = "R10"; ## C22 on J1
+NET "FMC_LA19_N" LOC = "P7"; ## H23 on J1
+NET "FMC_LA19_P" LOC = "N6"; ## H22 on J1
+NET "FMC_LA20_N" LOC = "P8"; ## G22 on J1
+NET "FMC_LA20_P" LOC = "N7"; ## G21 on J1
+NET "FMC_LA21_N" LOC = "V4"; ## H26 on J1
+NET "FMC_LA21_P" LOC = "T4"; ## H25 on J1
+NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
+NET "FMC_LA22_P" LOC = "R7"; ## G24 on J1
+NET "FMC_LA23_N" LOC = "P6"; ## D24 on J1
+NET "FMC_LA23_P" LOC = "N5"; ## D23 on J1
+NET "FMC_LA24_N" LOC = "V8"; ## H29 on J1
+NET "FMC_LA24_P" LOC = "U8"; ## H28 on J1
+NET "FMC_LA25_N" LOC = "N11"; ## G28 on J1
+NET "FMC_LA25_P" LOC = "M11"; ## G27 on J1
+NET "FMC_LA26_N" LOC = "V7"; ## D27 on J1
+NET "FMC_LA26_P" LOC = "U7"; ## D26 on J1
+NET "FMC_LA27_N" LOC = "T11"; ## C27 on J1
+NET "FMC_LA27_P" LOC = "R11"; ## C26 on J1
+NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
+NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
+NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
+NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
+NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
+NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
+NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
+NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
+NET "FMC_LA32_N" LOC = "V15"; ## H38 on J1
+NET "FMC_LA32_P" LOC = "U15"; ## H37 on J1
+NET "FMC_LA33_N" LOC = "N9"; ## G37 on J1
+NET "FMC_LA33_P" LOC = "M10"; ## G36 on J1
+NET "FMC_PRSNT_M2C_L" LOC = "U13"; ## H2 on J1
+NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3"; ## D1 on J1, 16 on U10
+NET "FPGA_CCLK" LOC = "R15"; ## 16 on U17, 7 on J12
+NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13"; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
+NET "FPGA_D1_MISO2" LOC = "T14"; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
+NET "FPGA_D2_MISO3" LOC = "V14"; ## 1 on U17, 38 on U10, 2 on J12
+NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13"; ## 15 on U17, 5 on J12
+NET "FPGA_SUSPEND" LOC = "R16"; ## 2 on J14
+NET "FPGA_TCK_BUF" LOC = "A17"; ## 14 on U21, D29 on J1
+NET "FPGA_TDO" LOC = "D16"; ## 1 on J4, D30 on J1
+NET "FPGA_TMS_BUF" LOC = "B18"; ## 16 on U21, D31 on J1
+NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
+NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
+NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
+NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
+NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
+NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
+NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
+NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
+NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
+NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
+NET "SPI_CS_B" LOC = "V3"; ## 1 on J15, 4 on J12
diff --git a/firmware/minitlu/ucf/fmcTLU_fmc_connections.txt b/firmware/minitlu/ucf/fmcTLU_fmc_connections.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e1f03f6d975953be17a7347f452032971aced306
--- /dev/null
+++ b/firmware/minitlu/ucf/fmcTLU_fmc_connections.txt
@@ -0,0 +1,50 @@
+BEAM_TRIGGER*<0> J4 D9 ASP-134606-01
+BEAM_TRIGGER*<1> J4 D18 ASP-134606-01
+BEAM_TRIGGER*<2> J4 D24 ASP-134606-01
+BEAM_TRIGGER*<3> J4 G31 ASP-134606-01
+BEAM_TRIGGER<0> J4 D8 ASP-134606-01
+BEAM_TRIGGER<1> J4 D17 ASP-134606-01
+BEAM_TRIGGER<2> J4 D23 ASP-134606-01
+BEAM_TRIGGER<3> J4 G30 ASP-134606-01
+BEAM_TRIGGER_CFD*<0> J4 G7 ASP-134606-01
+BEAM_TRIGGER_CFD*<1> J4 C19 ASP-134606-01
+BEAM_TRIGGER_CFD*<2> J4 C23 ASP-134606-01
+BEAM_TRIGGER_CFD*<3> J4 C27 ASP-134606-01
+BEAM_TRIGGER_CFD<0> J4 G6 ASP-134606-01
+BEAM_TRIGGER_CFD<1> J4 C18 ASP-134606-01
+BEAM_TRIGGER_CFD<2> J4 C22 ASP-134606-01
+BEAM_TRIGGER_CFD<3> J4 C26 ASP-134606-01
+BUSY0 J4 C10 ASP-134606-01
+BUSY0* J4 C11 ASP-134606-01
+BUSY1 J4 H31 ASP-134606-01
+BUSY1* J4 H32 ASP-134606-01
+BUSY2 J4 H13 ASP-134606-01
+BUSY2* J4 H14 ASP-134606-01
+CLK1 J4 H25 ASP-134606-01
+CLK1* J4 H26 ASP-134606-01
+CLK2 J4 H10 ASP-134606-01
+CLK2* J4 H11 ASP-134606-01
+CONT0 J4 G36 ASP-134606-01
+CONT0* J4 G37 ASP-134606-01
+CONT1 J4 H28 ASP-134606-01
+CONT1* J4 H29 ASP-134606-01
+CONT2 J4 G12 ASP-134606-01
+CONT2* J4 G13 ASP-134606-01
+DUT_CLK0 J4 G33 ASP-134606-01
+DUT_CLK0* J4 G34 ASP-134606-01
+FRONT_PANEL_CLK J4 H4 ASP-134606-01
+FRONT_PANEL_CLK* J4 H5 ASP-134606-01
+HDMI_POWER_ENABLE1 J4 H7 ASP-134606-01
+HDMI_POWER_ENABLE2 J4 H8 ASP-134606-01
+SCL J4 C30 ASP-134606-01
+SDA J4 C31 ASP-134606-01
+SPARE1 J4 H34 ASP-134606-01
+SPARE1* J4 H35 ASP-134606-01
+SPARE2 J4 D20 ASP-134606-01
+SPARE2* J4 D21 ASP-134606-01
+TRIG0 J4 C14 ASP-134606-01
+TRIG0* J4 C15 ASP-134606-01
+TRIG1 J4 H37 ASP-134606-01
+TRIG1* J4 H38 ASP-134606-01
+TRIG2 J4 D14 ASP-134606-01
+TRIG2* J4 D15 ASP-134606-01
diff --git a/firmware/minitlu/ucf/fmc_pins.ucf b/firmware/minitlu/ucf/fmc_pins.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..a02d8cbca502aed761c35b87c84c55a1d9d8676e
--- /dev/null
+++ b/firmware/minitlu/ucf/fmc_pins.ucf
@@ -0,0 +1,50 @@
+NET "BUSY_P<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
+NET "BUSY_N<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
+NET "TRIG_P<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
+NET "TRIG_N<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
+NET "BEAM_TRIGGER_CFD_P<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
+NET "BEAM_TRIGGER_CFD_N<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+NET "BEAM_TRIGGER_CFD_P<2>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
+NET "BEAM_TRIGGER_CFD_N<2>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+NET "BEAM_TRIGGER_CFD_P<3>" LOC = "R11"; ## "FMC_LA27_P" , C26 on FMC
+NET "BEAM_TRIGGER_CFD_N<3>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
+NET "SCL" LOC = "P11"; ## C30 on FMC
+NET "SDA" LOC = "N10"; ## C31 on FMC
+NET "TRIG_P<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
+NET "TRIG_N<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
+NET "BEAM_TRIGGER_P<1>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
+NET "BEAM_TRIGGER_N<1>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
+NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
+NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
+NET "BEAM_TRIGGER_P<2>" LOC = "N5"; ## "FMC_LA23_P" , D23 on FMC
+NET "BEAM_TRIGGER_N<2>" LOC = "P6"; ## "FMC_LA23_N" , D24 on FMC
+NET "BEAM_TRIGGER_P<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
+NET "BEAM_TRIGGER_N<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "CONT_P<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
+NET "CONT_N<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
+NET "BEAM_TRIGGER_P<3>" LOC = "M8"; ## "FMC_LA29_P" , G30 on FMC
+NET "BEAM_TRIGGER_N<3>" LOC = "N8"; ## "FMC_LA29_N" , G31 on FMC
+NET "DUT_CLK_P<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC
+NET "DUT_CLK_N<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC
+NET "CONT_P<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC
+NET "CONT_N<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC
+NET "BEAM_TRIGGER_CFD_P<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "BEAM_TRIGGER_CFD_N<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
+NET "CLK_P<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+NET "CLK_N<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC
+NET "BUSY_P<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
+NET "BUSY_N<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+NET "CLK_P<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC
+NET "CLK_N<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
+NET "CONT_P<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC
+NET "CONT_N<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC
+NET "BUSY_P<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
+NET "BUSY_N<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
+NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
+NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
+NET "TRIG_P<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
+NET "TRIG_N<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
+NET "FRONT_PANEL_CLK_P" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC
+NET "FRONT_PANEL_CLK_N" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC
+NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
+NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
diff --git a/firmware/minitlu/ucf/generate_fmcTLU_ucf.pl b/firmware/minitlu/ucf/generate_fmcTLU_ucf.pl
new file mode 100755
index 0000000000000000000000000000000000000000..a44e3675a9da99b07b7314a5c5b03a981782b9ce
--- /dev/null
+++ b/firmware/minitlu/ucf/generate_fmcTLU_ucf.pl
@@ -0,0 +1,82 @@
+#!/usr/bin/perl -w
+#
+use strict;
+#
+# script to take extract from dialcnet.dat from
+# FMC-TLU design (connections to FMC connector)
+# and SP601 master UCF
+# and produce a section of UCF to include in FMC-TLU firmware.
+#
+# extract from dialcnet.dat is like:
+# SPARE1 J4 H34 ASP-134606-01
+#
+# master UCF contains lines like:
+# NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
+#
+#
+# two args. First is master UCF , second is extract from dialcnet.dat
+#
+# David Cussans, November 2012
+#
+
+my $masterUCF = $ARGV[0];
+my $netlist = $ARGV[1];
+
+print "ucf , netlist = $masterUCF , $netlist\n";
+
+open UCF , "<$masterUCF" or die "Can't open master UCF: $!";
+open NETLIST , "<$netlist" or die "Can't open netlist: $!";
+
+my %fpga_fmc_pins;
+my %fmc_nets;
+my %fpga_fmc_labels;
+
+while ( <UCF> ) {
+ next unless /FMC/;
+ # print $_;
+ my @fields = split;
+ my $fpga_pin = $fields[4];
+ my $fmc_pin = $fields[6];
+ $fpga_pin =~ s/[\";]//g;
+
+ my $fmc_label = $fields[1];
+ $fpga_fmc_labels{$fmc_pin} = $fmc_label;
+
+ #print $fields[4], $fields[6] , "\n"
+ #print $fpga_pin , $fmc_pin , "\n";
+ $fpga_fmc_pins{$fmc_pin} = $fpga_pin;
+
+}
+#while (<>){
+#print %fpga_fmc_pins;
+
+while (<NETLIST>) {
+ my @fields = split;
+ my $netname = $fields[0];
+ my $fmc_pin = $fields[2];
+
+ my $inverted_signal;
+ if ($netname =~ s/\*//) { $inverted_signal = 1 } else { $inverted_signal = 0}
+ if ( $netname = /^(\D+)(\d+)/) {
+ $netname =~ s/[<>]//g;
+ my $netbase = $1;
+ my $netindex = $2;
+ ## print "$netbase , $netindex\n";
+ # we have an name like NET000
+ if ($inverted_signal) { $netbase = $netbase . "_N"} else {$netbase = $netbase . "_P"}
+ ## print "$netbase , $netindex\n";
+ $netname = $netbase . "<" . $netindex . ">";
+ ## print "netname = $netname\n";
+ }
+ #if ($netname =~ s/\*//) { $netname = $netname . "_N" } else { $netname = $netname . "_P" } ;
+ ## print "netname , fmcpin = $netname $fmc_pin\n";
+ $fmc_nets{$fmc_pin} = $netname;
+}
+
+my $fmc_pin;
+
+foreach $fmc_pin ( sort keys %fmc_nets ) {
+
+# print "$fmc_pin , $fmc_nets{$fmc_pin} , $fpga_fmc_pins{$fmc_pin} \n";
+ print "NET \"$fmc_nets{$fmc_pin}\"\t\tLOC = \"$fpga_fmc_pins{$fmc_pin}\"; ## $fpga_fmc_labels{$fmc_pin} , $fmc_pin on FMC\n";
+}
diff --git a/firmware/minitlu/ucf/sp601_FMC_mTLU.ucf b/firmware/minitlu/ucf/sp601_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..d65e6bd3e38ae44aa091f0783dab529133988d4c
--- /dev/null
+++ b/firmware/minitlu/ucf/sp601_FMC_mTLU.ucf
@@ -0,0 +1,152 @@
+NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET I6/s_clk_is_xtal TIG;
+
+NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=D14;
+NET dip_switch_i<1> LOC=E12;
+NET dip_switch_i<2> LOC=F12;
+NET dip_switch_i<3> LOC=V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
+
+# Main I2C bus
+NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
+NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
+
+#
+# I/O to devices under test
+
+
+NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
+NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
+NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
+NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
+NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
+NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+
+NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
+NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
+NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
+
+# Remove for now.
+#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
+##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
+##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
+##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
+
+NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , DUT_CLK_P_I<0>
+NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N_I<0>
+NET "DUT_CLK_P_I<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , DUT_CLK_P_I<0>
+#NET "DUT_CLK_P_I<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , DUT_CLK_N_I<0>
+NET "DUT_CLK_P_I<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , DUT_CLK_P_I<0>
+#NET "DUT_CLK_P_I<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , DUT_CLK_N_I<0>
+
+NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+#NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+NET "RESET_OR_CLK_P_O<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+NET "RESET_OR_CLK_N_O<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+NET "RESET_OR_CLK_P_O<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+NET "RESET_OR_CLK_N_O<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
+
+NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
+NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+
+NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
+NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
+
+NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
+NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
+
+# Threshold comparator outputs
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
+NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
+
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
+NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
+NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
+NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+
+#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+
+# GPIO pins for debugging.
+NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
+NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
+NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
+NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
+NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
+NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
+NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
+NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
\ No newline at end of file
diff --git a/firmware/minitlu/ucf/sp601_FMC_mTLU_v1a.ucf b/firmware/minitlu/ucf/sp601_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..9e528074d9741ccfe3c7af3377b9c9ba1d64f3cc
--- /dev/null
+++ b/firmware/minitlu/ucf/sp601_FMC_mTLU_v1a.ucf
@@ -0,0 +1,220 @@
+#
+# UCF for version 1a of updated mini-TLU
+#
+
+NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
+NET "sysclk_p_i" LOC = K15;
+NET "sysclk_p_i" IOSTANDARD = LVDS_25;
+NET "sysclk_p_i" DIFF_TERM = "TRUE";
+NET "sysclk_n_i" LOC = K16;
+NET "sysclk_n_i" IOSTANDARD = LVDS_25;
+NET "sysclk_n_i" DIFF_TERM = "TRUE";
+
+TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET "I6/s_clk_is_xtal" TIG;
+
+NET "leds_o[0]" LOC = E13;
+NET "leds_o[0]" IOSTANDARD = LVCMOS25;
+NET "leds_o[1]" LOC = C14;
+NET "leds_o[1]" IOSTANDARD = LVCMOS25;
+NET "leds_o[2]" LOC = C4;
+NET "leds_o[2]" IOSTANDARD = LVCMOS25;
+NET "leds_o[3]" LOC = A4;
+NET "leds_o[3]" IOSTANDARD = LVCMOS25;
+
+NET "dip_switch_i[0]" LOC = D14;
+NET "dip_switch_i[1]" LOC = E12;
+NET "dip_switch_i[2]" LOC = F12;
+NET "dip_switch_i[3]" LOC = V13;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
+TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET "gmii_gtx_clk_o" LOC = A9;
+NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
+NET "gmii_gtx_clk_o" SLEW = FAST;
+NET "gmii_txd_o[0]" LOC = F8;
+NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[1]" LOC = G8;
+NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[2]" LOC = A6;
+NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[3]" LOC = B6;
+NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[4]" LOC = E6;
+NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[5]" LOC = F7;
+NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[6]" LOC = A5;
+NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_txd_o[7]" LOC = C5;
+NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_en_o" LOC = B8;
+NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
+NET "gmii_tx_er_o" LOC = A8;
+NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;
+
+NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
+NET "gmii_rx_clk_i" LOC = L16;
+NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
+TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
+OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
+NET "gmii_rxd_i[0]" LOC = M14;
+NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[1]" LOC = U18;
+NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[2]" LOC = U17;
+NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[3]" LOC = T18;
+NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[4]" LOC = T17;
+NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[5]" LOC = N16;
+NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[6]" LOC = N15;
+NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
+NET "gmii_rxd_i[7]" LOC = P18;
+NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_dv_i" LOC = N18;
+NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
+NET "gmii_rx_er_i" LOC = P17;
+NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;
+
+NET "phy_rstb_o" LOC = L13;
+NET "phy_rstb_o" IOSTANDARD = LVCMOS25;
+
+# Main I2C bus
+## C30 on FMC
+NET "i2c_scl_b" LOC = P11;
+## C31 on FMC
+NET "i2c_sda_b" LOC = N10;
+
+#
+# I/O to devices under test
+
+#NET "BUSY_N_I<0>" LOC = "P7"; ## "FMC_LA19_N" , H23 on FMC
+#NET "BUSY_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+#NET "BUSY_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+## "FMC_LA19_P" , H22 on FMC
+NET "busy_p_i[0]" LOC = N6;
+## "FMC_LA14_P" , C18 on FMC
+NET "busy_p_i[1]" LOC = B2;
+## "FMC_LA12_P" , G15 on FMC
+NET "busy_p_i[2]" LOC = D6;
+
+#NET "TRIGGERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+## "FMC_LA20_P" , G21 on FMC
+NET "triggers_p_o[0]" LOC = N7;
+## "FMC_LA03_P" , G9 on FMC
+NET "triggers_p_o[1]" LOC = C13;
+## "FMC_LA16_P" , G18 on FMC
+NET "triggers_p_o[2]" LOC = C7;
+
+# Remove shutters ( also known as SPARE ) for now
+#NET "SPARE_N_O<1>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
+#NET "SPARE_N_O<2>" LOC = "A12"; ## "FMC_LA11_N" , H17 on FMC
+#NET "SPARE_P_O<1>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
+#NET "SPARE_P_O<2>" LOC = "B12"; ## "FMC_LA11_P" , H16 on FMC
+
+# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
+#NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
+#NET "DUT_CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
+#NET "DUT_CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+## "FMC_LA21_P" , H25 on FMC
+NET "dut_clk_p_o[0]" LOC = T4;
+## "FMC_LA27_P" , C26 on FMC
+NET "dut_clk_p_o[1]" LOC = R11;
+## "FMC_LA02_P" , H7 on FMC
+NET "dut_clk_p_o[2]" LOC = C15;
+
+# Labelled CONT on schematic.
+#NET "RESET_OR_CLK_N_O<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
+#NET "RESET_OR_CLK_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "RESET_OR_CLK_N_O<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+## "FMC_LA22_P" , G24 on FMC
+NET "reset_or_clk_p_o[0]" LOC = R7;
+## "FMC_LA18_CC_P" , C22 on FMC
+NET "reset_or_clk_p_o[1]" LOC = R10;
+## "FMC_LA07_P" , H13 on FMC
+NET "reset_or_clk_p_o[2]" LOC = E7;
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+## "FMC_LA32_N" , H38 on FMC
+NET "cfd_discr_n_i[0]" LOC = V15;
+## "FMC_LA30_N" , H35 on FMC
+NET "cfd_discr_n_i[1]" LOC = V12;
+## "FMC_LA28_N" , H32 on FMC
+NET "cfd_discr_n_i[2]" LOC = V11;
+## "FMC_LA24_N" , H29 on FMC
+NET "cfd_discr_n_i[3]" LOC = V8;
+## "FMC_LA32_P" , H37 on FMC
+NET "cfd_discr_p_i[0]" LOC = U15;
+## "FMC_LA30_P" , H34 on FMC
+NET "cfd_discr_p_i[1]" LOC = T12;
+## "FMC_LA28_P" , H31 on FMC
+NET "cfd_discr_p_i[2]" LOC = U11;
+## "FMC_LA24_P" , H28 on FMC
+NET "cfd_discr_p_i[3]" LOC = U8;
+
+# Threshold comparator outputs
+## "FMC_LA33_N" , G37 on FMC
+NET "threshold_discr_n_i[0]" LOC = N9;
+## "FMC_LA31_N" , G34 on FMC
+NET "threshold_discr_n_i[1]" LOC = V6;
+## "FMC_LA29_N" , G31 on FMC
+NET "threshold_discr_n_i[2]" LOC = N8;
+## "FMC_LA25_N" , G28 on FMC
+NET "threshold_discr_n_i[3]" LOC = N11;
+## "FMC_LA33_P" , G36 on FMC
+NET "threshold_discr_p_i[0]" LOC = M10;
+## "FMC_LA31_P" , G33 on FMC
+NET "threshold_discr_p_i[1]" LOC = T6;
+## "FMC_LA29_P" , G30 on FMC
+NET "threshold_discr_p_i[2]" LOC = M8;
+## "FMC_LA25_P" , G27 on FMC
+NET "threshold_discr_p_i[3]" LOC = M11;
+
+############
+# External clock pins
+## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "extclk_p_b" LOC = C10;
+## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+NET "extclk_n_b" LOC = A10;
+
+
+#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
+
+# GPIO pins for debugging.
+## 1 on J13 (thru series R100 200 ohm)
+NET "gpio_hdr[0]" LOC = N17;
+## 3 on J13 (thru series R102 200 ohm)
+NET "gpio_hdr[1]" LOC = M18;
+## 5 on J13 (thru series R101 200 ohm)
+NET "gpio_hdr[2]" LOC = A3;
+## 7 on J13 (thru series R103 200 ohm)
+NET "gpio_hdr[3]" LOC = L15;
+## 2 on J13 (thru series R99 200 ohm)
+NET "gpio_hdr[4]" LOC = F15;
+## 4 on J13 (thru series R98 200 ohm)
+NET "gpio_hdr[5]" LOC = B4;
+## 6 on J13 (thru series R97 200 ohm)
+NET "gpio_hdr[6]" LOC = F13;
+## 8 on J13 (thru series R96 20
+NET "gpio_hdr[7]" LOC = P12;
diff --git a/firmware/minitlu/ucf/sp605_FMC_mTLU.ucf b/firmware/minitlu/ucf/sp605_FMC_mTLU.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..3b4820582b10bab8ebd10a2606141ba34f2e1559
--- /dev/null
+++ b/firmware/minitlu/ucf/sp605_FMC_mTLU.ucf
@@ -0,0 +1,138 @@
+NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
+NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
+
+TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
+
+#NET Reset_i LOC=F3; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+
+NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
+NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
+NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
+NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
+
+NET dip_switch_i<0> LOC=C18;
+NET dip_switch_i<1> LOC=Y6;
+NET dip_switch_i<2> LOC=W6;
+NET dip_switch_i<3> LOC=E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
+TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+
+
+# Main I2C bus
+#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
+#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
+NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
+NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
+
+#
+# I/O to devices under test
+
+NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
+NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
+NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
+NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
+NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
+NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
+
+NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
+#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
+NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
+#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
+NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
+#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
+
+#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
+#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
+#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
+#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
+
+NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
+NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
+NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
+NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
+NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
+NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
+
+NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
+#NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
+NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
+#NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
+NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
+#NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
+
+
+# Trigger inputs
+# first constant-fraction-discrimiator comparator outputs
+NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
+NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
+NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
+NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
+NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
+NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
+NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
+#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
+#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
+#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
+#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
+# then threshold comparator outputs
+# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
+#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
+#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
+#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+
+#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
+#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
+#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
+#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
+
+NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
diff --git a/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a.ucf b/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..3536b6ee44e4bc20e34fa76aef169f7ec9e4b80e
--- /dev/null
+++ b/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a.ucf
@@ -0,0 +1,185 @@
+#
+# UCF for version 1a of updated mini-TLU
+#
+
+NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
+NET "sysclk_p_i" LOC = K21;
+NET "sysclk_p_i" IOSTANDARD = LVDS_25;
+NET "sysclk_p_i" DIFF_TERM = "TRUE";
+NET "sysclk_n_i" LOC = K22;
+NET "sysclk_n_i" IOSTANDARD = LVDS_25;
+NET "sysclk_n_i" DIFF_TERM = "TRUE";
+
+TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+NET "I6/s_clk_is_xtal" TIG;
+
+NET "leds_o[0]" LOC = D17;
+NET "leds_o[0]" IOSTANDARD = LVCMOS25;
+NET "leds_o[1]" LOC = AB4;
+NET "leds_o[1]" IOSTANDARD = LVCMOS25;
+NET "leds_o[2]" LOC = D21;
+NET "leds_o[2]" IOSTANDARD = LVCMOS25;
+NET "leds_o[3]" LOC = W15;
+NET "leds_o[3]" IOSTANDARD = LVCMOS25;
+
+NET "dip_switch_i[0]" LOC = C18;
+NET "dip_switch_i[1]" LOC = Y6;
+NET "dip_switch_i[2]" LOC = W6;
+NET "dip_switch_i[3]" LOC = E4;
+
+# Ethernet PHY
+
+TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
+TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
+
+NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
+NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
+NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
+NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
+
+NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
+TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
+OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
+NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
+NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
+NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
+
+NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
+
+# Main I2C bus
+## C30 on FMC
+NET "i2c_scl_b" LOC = T21;
+## C31 on FMC
+NET "i2c_sda_b" LOC = R22;
+
+#
+# I/O to devices under test
+
+## "FMC_LA19_P" , H22 on FMC
+NET "busy_p_i[0]" LOC = R11;
+## "FMC_LA12_P" , G15 on FMC
+NET "busy_p_i[1]" LOC = H13;
+## "FMC_LA14_P" , C18 on FMC
+NET "busy_p_i[2]" LOC = C17;
+
+## "FMC_LA20_P" , G21 on FMC
+NET "triggers_p_o[0]" LOC = R9;
+## "FMC_LA16_P" , G18 on FMC
+NET "triggers_p_o[1]" LOC = C5;
+## "FMC_LA03_P" , G9 on FMC
+NET "triggers_p_o[2]" LOC = B18;
+
+# Remove shutters ( also known as SPARE ) for now
+#NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
+#NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+#NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
+#NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+
+# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
+## "FMC_LA27_P" , C26 on FMC
+NET "dut_clk_p_o[0]" LOC = AA10;
+## "FMC_LA21_P" , H25 on FMC
+NET "dut_clk_p_o[1]" LOC = V11;
+## "FMC_LA02_P" , H7 on FMC
+NET "dut_clk_p_o[2]" LOC = G8;
+
+
+# Labelled CONT on schematic.
+## "FMC_LA22_P" , G24 on FMC
+NET "reset_or_clk_p_o[0]" LOC = V7;
+## "FMC_LA07_CC_P" , H13 on FMC
+NET "reset_or_clk_p_o[1]" LOC = B2;
+## "FMC_LA18_P" , C22 on FMC
+NET "reset_or_clk_p_o[2]" LOC = T12;
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+## "FMC_LA32_N" , H38 on FMC
+NET "cfd_discr_n_i[0]" LOC = Y18;
+## "FMC_LA30_N" , H35 on FMC
+NET "cfd_discr_n_i[1]" LOC = AB15;
+## "FMC_LA28_N" , H32 on FMC
+NET "cfd_discr_n_i[2]" LOC = AB16;
+## "FMC_LA24_N" , H29 on FMC
+NET "cfd_discr_n_i[3]" LOC = AB14;
+## "FMC_LA32_P" , H37 on FMC
+NET "cfd_discr_p_i[0]" LOC = W17;
+## "FMC_LA30_P" , H34 on FMC
+NET "cfd_discr_p_i[1]" LOC = Y15;
+## "FMC_LA28_P" , H31 on FMC
+NET "cfd_discr_p_i[2]" LOC = AA16;
+## "FMC_LA24_P" , H28 on FMC
+NET "cfd_discr_p_i[3]" LOC = AA14;
+
+# Threshold comparator outputs
+## "FMC_LA33_N" , G37 on FMC
+NET "threshold_discr_n_i[0]" LOC = AB17;
+## "FMC_LA31_N" , G34 on FMC
+NET "threshold_discr_n_i[1]" LOC = V15;
+## "FMC_LA29_N" , G31 on FMC
+NET "threshold_discr_n_i[2]" LOC = U15;
+## "FMC_LA25_N" , G28 on FMC
+NET "threshold_discr_n_i[3]" LOC = Y14;
+## "FMC_LA33_P" , G36 on FMC
+NET "threshold_discr_p_i[0]" LOC = Y17;
+## "FMC_LA31_P" , G33 on FMC
+NET "threshold_discr_p_i[1]" LOC = U16;
+## "FMC_LA29_P" , G30 on FMC
+NET "threshold_discr_p_i[2]" LOC = T15;
+## "FMC_LA25_P" , G27 on FMC
+NET "threshold_discr_p_i[3]" LOC = W14;
+
+############
+# External clock pins
+## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "extclk_p_b" LOC = H12;
+## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+NET "extclk_n_b" LOC = G11;
+
+
+#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
+
+
+## GPIO pins for debugging.
+### 1 on J13 (thru series R100 200 ohm)
+#NET "gpio_hdr[0]" LOC = N17;
+### 3 on J13 (thru series R102 200 ohm)
+#NET "gpio_hdr[1]" LOC = M18;
+### 5 on J13 (thru series R101 200 ohm)
+#NET "gpio_hdr[2]" LOC = A3;
+### 7 on J13 (thru series R103 200 ohm)
+#NET "gpio_hdr[3]" LOC = L15;
+### 2 on J13 (thru series R99 200 ohm)
+#NET "gpio_hdr[4]" LOC = F15;
+### 4 on J13 (thru series R98 200 ohm)
+#NET "gpio_hdr[5]" LOC = B4;
+### 6 on J13 (thru series R97 200 ohm)
+#NET "gpio_hdr[6]" LOC = F13;
+### 8 on J13 (thru series R96 20
+#NET "gpio_hdr[7]" LOC = P12;
diff --git a/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a_pintest.ucf b/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a_pintest.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..cda11ab333b4c9e414210350d1e12dd6334612e4
--- /dev/null
+++ b/firmware/minitlu/ucf/sp605_FMC_mTLU_v1a_pintest.ucf
@@ -0,0 +1,155 @@
+#
+# UCF for version 1a of updated mini-TLU
+#
+
+NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
+NET "sysclk_p_i" LOC = K21;
+NET "sysclk_p_i" IOSTANDARD = LVDS_25;
+NET "sysclk_p_i" DIFF_TERM = "TRUE";
+NET "sysclk_n_i" LOC = K22;
+NET "sysclk_n_i" IOSTANDARD = LVDS_25;
+NET "sysclk_n_i" DIFF_TERM = "TRUE";
+
+TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
+
+# remove for now
+#NET Reset_i LOC=P4; ## Global Reset
+
+#NET ipb_clk TNM_NET = tnm_ipb_clk;
+#NET clk125 TNM_NET = tnm_clk125;
+#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
+#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
+
+# NET clocks/rst* TIG;
+#NET "I6/s_clk_is_xtal" TIG;
+
+NET "leds_o[0]" LOC = D17;
+NET "leds_o[0]" IOSTANDARD = LVCMOS25;
+NET "leds_o[1]" LOC = AB4;
+NET "leds_o[1]" IOSTANDARD = LVCMOS25;
+NET "leds_o[2]" LOC = D21;
+NET "leds_o[2]" IOSTANDARD = LVCMOS25;
+NET "leds_o[3]" LOC = W15;
+NET "leds_o[3]" IOSTANDARD = LVCMOS25;
+
+NET "dip_switch_i[0]" LOC = C18;
+NET "dip_switch_i[1]" LOC = Y6;
+NET "dip_switch_i[2]" LOC = W6;
+NET "dip_switch_i[3]" LOC = E4;
+
+# Ethernet PHY
+
+
+# Main I2C bus
+## C30 on FMC
+NET "i2c_scl_b" LOC = T21;
+## C31 on FMC
+NET "i2c_sda_b" LOC = R22;
+
+#
+# I/O to devices under test
+
+## "FMC_LA19_P" , H22 on FMC
+NET "busy_p_o[0]" LOC = R11;
+## "FMC_LA12_P" , G15 on FMC
+NET "busy_p_o[1]" LOC = H13;
+## "FMC_LA14_P" , C18 on FMC
+NET "busy_p_o[2]" LOC = C17;
+
+## "FMC_LA20_P" , G21 on FMC
+NET "triggers_p_o[0]" LOC = R9;
+## "FMC_LA16_P" , G18 on FMC
+NET "triggers_p_o[1]" LOC = C5;
+## "FMC_LA03_P" , G9 on FMC
+NET "triggers_p_o[2]" LOC = B18;
+
+# Remove shutters ( also known as SPARE ) for now
+NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
+NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
+NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
+NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
+
+# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
+## "FMC_LA27_P" , C26 on FMC
+NET "dut_clk_p_o[0]" LOC = AA10;
+## "FMC_LA21_P" , H25 on FMC
+NET "dut_clk_p_o[1]" LOC = V11;
+## "FMC_LA02_P" , H7 on FMC
+NET "dut_clk_p_o[2]" LOC = G8;
+
+
+# Labelled CONT on schematic.
+## "FMC_LA22_P" , G24 on FMC
+NET "reset_or_clk_p_o[0]" LOC = V7;
+## "FMC_LA07_CC_P" , H13 on FMC
+NET "reset_or_clk_p_o[1]" LOC = B2;
+## "FMC_LA18_P" , C22 on FMC
+NET "reset_or_clk_p_o[2]" LOC = T12;
+
+# Trigger Inputs
+
+# Constant-fraction-discrimiator comparator outputs
+## "FMC_LA32_N" , H38 on FMC
+NET "cfd_discr_n_i[0]" LOC = Y18;
+## "FMC_LA30_N" , H35 on FMC
+NET "cfd_discr_n_i[1]" LOC = AB15;
+## "FMC_LA28_N" , H32 on FMC
+NET "cfd_discr_n_i[2]" LOC = AB16;
+## "FMC_LA24_N" , H29 on FMC
+NET "cfd_discr_n_i[3]" LOC = AB14;
+## "FMC_LA32_P" , H37 on FMC
+NET "cfd_discr_p_i[0]" LOC = W17;
+## "FMC_LA30_P" , H34 on FMC
+NET "cfd_discr_p_i[1]" LOC = Y15;
+## "FMC_LA28_P" , H31 on FMC
+NET "cfd_discr_p_i[2]" LOC = AA16;
+## "FMC_LA24_P" , H28 on FMC
+NET "cfd_discr_p_i[3]" LOC = AA14;
+
+# Threshold comparator outputs
+## "FMC_LA33_N" , G37 on FMC
+NET "threshold_discr_n_i[0]" LOC = AB17;
+## "FMC_LA31_N" , G34 on FMC
+NET "threshold_discr_n_i[1]" LOC = V15;
+## "FMC_LA29_N" , G31 on FMC
+NET "threshold_discr_n_i[2]" LOC = U15;
+## "FMC_LA25_N" , G28 on FMC
+NET "threshold_discr_n_i[3]" LOC = Y14;
+## "FMC_LA33_P" , G36 on FMC
+NET "threshold_discr_p_i[0]" LOC = Y17;
+## "FMC_LA31_P" , G33 on FMC
+NET "threshold_discr_p_i[1]" LOC = U16;
+## "FMC_LA29_P" , G30 on FMC
+NET "threshold_discr_p_i[2]" LOC = T15;
+## "FMC_LA25_P" , G27 on FMC
+NET "threshold_discr_p_i[3]" LOC = W14;
+
+############
+# External clock pins
+## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
+NET "extclk_p_o" LOC = H12;
+## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
+NET "extclk_n_o" LOC = G11;
+
+
+#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
+
+
+## GPIO pins for debugging.
+### 1 on J13 (thru series R100 200 ohm)
+#NET "gpio_hdr[0]" LOC = N17;
+### 3 on J13 (thru series R102 200 ohm)
+#NET "gpio_hdr[1]" LOC = M18;
+### 5 on J13 (thru series R101 200 ohm)
+#NET "gpio_hdr[2]" LOC = A3;
+### 7 on J13 (thru series R103 200 ohm)
+#NET "gpio_hdr[3]" LOC = L15;
+### 2 on J13 (thru series R99 200 ohm)
+#NET "gpio_hdr[4]" LOC = F15;
+### 4 on J13 (thru series R98 200 ohm)
+#NET "gpio_hdr[5]" LOC = B4;
+### 6 on J13 (thru series R97 200 ohm)
+#NET "gpio_hdr[6]" LOC = F13;
+### 8 on J13 (thru series R96 20
+#NET "gpio_hdr[7]" LOC = P12;
diff --git a/firmware/minitlu/xdc/ax3_pm3_mTLUvC.xdc b/firmware/minitlu/xdc/ax3_pm3_mTLUvC.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..8ba1064658293761a501e40ee6056de99763e53e
--- /dev/null
+++ b/firmware/minitlu/xdc/ax3_pm3_mTLUvC.xdc
@@ -0,0 +1,377 @@
+# -------------------------------------------------------------------------------------------------
+# -- Project : Mars AX3
+# -- File description : User Constraint File for Mars PM3 Base Board
+# -- File name : mars_ax3_pm3.xdc
+# -- Authors : Kanishk Sugand / Marc Oberholzer
+# -------------------------------------------------------------------------------------------------
+# -- Copyright © 2012 by Enclustra GmbH, Switzerland. All rights are reserved.
+# -- Unauthorized duplication of this document, in whole or in part, by any means is prohibited
+# -- without the prior written permission of Enclustra GmbH, Switzerland.
+# --
+# -- Although Enclustra GmbH believes that the information included in this publication is correct
+# -- as of the date of publication, Enclustra GmbH reserves the right to make changes at any time
+# -- without notice.
+# --
+# -- All information in this document may only be published by Enclustra GmbH, Switzerland.
+# -------------------------------------------------------------------------------------------------
+# -- Notes:
+# -- 1. For best I/O timing, it is necessary to set the following options in Xilinx ISE/PlanAhead:
+# -- map option "Pack I/O registers into IOBs" to "Inputs and Outputs"
+# -- 2. The IO standards for banks 0, 2 and 3 are only valid if VCCO_0/VCCO_2/VCCO_3 = 3.3 V
+# -------------------------------------------------------------------------------------------------
+# -- File history:
+# --
+# -- Version | Date | Author | Remarks
+# -- ----------------------------------------------------------------------------------------------
+# -- 1.0 | 11.4.14 | C. Glattfelder | converted from UCF
+# -------------------------------------------------------------------------------------------------
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: global clock inputs
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN P17 [get_ports {Clk_50}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Clk_50}]
+set_property PACKAGE_PIN L16 [get_ports {Fpga_Emcclk}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Fpga_Emcclk}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ddr3 sdram
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[8]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[5]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cas_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_P[0]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Odt]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[4]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Cke]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[2]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_We_N]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_N]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Ras_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[12]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports Ddr3_Clk_P]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[11]}]
+set_property IOSTANDARD SSTL15 [get_ports Ddr3_Reset_N]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_A[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dm[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {Ddr3_Dqs_N[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN A15 [get_ports {Ddr3_Dq[2]}]
+set_property PACKAGE_PIN E15 [get_ports {Ddr3_Dq[3]}]
+set_property PACKAGE_PIN B11 [get_ports {Ddr3_Dq[15]}]
+set_property PACKAGE_PIN B18 [get_ports {Ddr3_Dq[4]}]
+set_property PACKAGE_PIN F14 [get_ports {Ddr3_Dq[14]}]
+set_property PACKAGE_PIN B17 [get_ports {Ddr3_Dq[5]}]
+set_property PACKAGE_PIN A11 [get_ports {Ddr3_Dq[13]}]
+set_property PACKAGE_PIN A16 [get_ports {Ddr3_Dq[6]}]
+set_property PACKAGE_PIN F13 [get_ports {Ddr3_Dq[12]}]
+set_property PACKAGE_PIN B16 [get_ports {Ddr3_Dq[7]}]
+set_property PACKAGE_PIN D14 [get_ports {Ddr3_Dq[11]}]
+set_property PACKAGE_PIN B14 [get_ports {Ddr3_Dq[8]}]
+set_property PACKAGE_PIN B13 [get_ports {Ddr3_Dq[10]}]
+set_property PACKAGE_PIN C14 [get_ports {Ddr3_Dq[9]}]
+set_property PACKAGE_PIN E16 [get_ports {Ddr3_Dq[1]}]
+set_property PACKAGE_PIN A14 [get_ports {Ddr3_Dqs_N[0]}]
+set_property PACKAGE_PIN A18 [get_ports {Ddr3_Dq[0]}]
+set_property PACKAGE_PIN D12 [get_ports {Ddr3_Dm[1]}]
+set_property PACKAGE_PIN D15 [get_ports {Ddr3_Dm[0]}]
+set_property PACKAGE_PIN A13 [get_ports {Ddr3_Dqs_P[0]}]
+set_property PACKAGE_PIN C16 [get_ports Ddr3_Clk_P]
+set_property PACKAGE_PIN C17 [get_ports Ddr3_Clk_N]
+set_property PACKAGE_PIN G14 [get_ports Ddr3_Cke]
+set_property PACKAGE_PIN B12 [get_ports {Ddr3_Dqs_N[1]}]
+set_property PACKAGE_PIN F16 [get_ports Ddr3_Cas_N]
+set_property PACKAGE_PIN K15 [get_ports {Ddr3_Ba[2]}]
+set_property PACKAGE_PIN H14 [get_ports {Ddr3_Ba[1]}]
+set_property PACKAGE_PIN C12 [get_ports {Ddr3_Dqs_P[1]}]
+set_property PACKAGE_PIN D17 [get_ports {Ddr3_Ba[0]}]
+set_property PACKAGE_PIN F18 [get_ports {Ddr3_A[9]}]
+set_property PACKAGE_PIN H17 [get_ports {Ddr3_A[8]}]
+set_property PACKAGE_PIN K16 [get_ports Ddr3_Odt]
+set_property PACKAGE_PIN E18 [get_ports {Ddr3_A[7]}]
+set_property PACKAGE_PIN K13 [get_ports {Ddr3_A[6]}]
+set_property PACKAGE_PIN E17 [get_ports {Ddr3_A[5]}]
+set_property PACKAGE_PIN F15 [get_ports Ddr3_Ras_N]
+set_property PACKAGE_PIN J13 [get_ports {Ddr3_A[4]}]
+set_property PACKAGE_PIN D18 [get_ports {Ddr3_A[3]}]
+set_property PACKAGE_PIN J18 [get_ports {Ddr3_A[2]}]
+set_property PACKAGE_PIN G13 [get_ports Ddr3_Reset_N]
+set_property PACKAGE_PIN G17 [get_ports {Ddr3_A[13]}]
+set_property PACKAGE_PIN H16 [get_ports {Ddr3_A[12]}]
+set_property PACKAGE_PIN G18 [get_ports {Ddr3_A[11]}]
+set_property PACKAGE_PIN J15 [get_ports Ddr3_We_N]
+set_property PACKAGE_PIN G16 [get_ports {Ddr3_A[10]}]
+set_property PACKAGE_PIN J14 [get_ports {Ddr3_A[1]}]
+set_property PACKAGE_PIN J17 [get_ports {Ddr3_A[0]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: ethernet
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rxc]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rst_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdio]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Mdc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Rxd[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Txc]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports Eth_Link_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Tx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Eth_Rx_Ctl]
+set_property IOSTANDARD LVCMOS33 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN T16 [get_ports Eth_Tx_Ctl]
+set_property PACKAGE_PIN R18 [get_ports {Eth_Txd[0]}]
+set_property PACKAGE_PIN V16 [get_ports {Eth_Rxd[3]}]
+set_property PACKAGE_PIN V15 [get_ports {Eth_Rxd[2]}]
+set_property PACKAGE_PIN V17 [get_ports {Eth_Rxd[1]}]
+set_property PACKAGE_PIN T18 [get_ports {Eth_Txd[1]}]
+set_property PACKAGE_PIN U16 [get_ports {Eth_Rxd[0]}]
+set_property PACKAGE_PIN T14 [get_ports Eth_Rxc]
+set_property PACKAGE_PIN R16 [get_ports Eth_Rx_Ctl]
+set_property PACKAGE_PIN U17 [get_ports {Eth_Txd[2]}]
+set_property PACKAGE_PIN M13 [get_ports Eth_Rst_N]
+set_property PACKAGE_PIN N14 [get_ports Eth_Mdio]
+set_property PACKAGE_PIN P14 [get_ports Eth_Mdc]
+set_property PACKAGE_PIN U18 [get_ports {Eth_Txd[3]}]
+set_property PACKAGE_PIN C15 [get_ports Eth_Link_N]
+set_property PACKAGE_PIN N16 [get_ports Eth_Txc]
+set_property PACKAGE_PIN T15 [get_ports Eth_Int_N]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: i2c
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R17 [get_ports I2c_Int_N]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Int_N]
+set_property PACKAGE_PIN N17 [get_ports I2c_Scl]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Scl]
+set_property PACKAGE_PIN P18 [get_ports I2c_Sda]
+set_property IOSTANDARD LVCMOS33 [get_ports I2c_Sda]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: spi flash
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN L13 [get_ports Flash_Cs_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Cs_N]
+set_property PACKAGE_PIN K17 [get_ports Flash_Di]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Di]
+set_property PACKAGE_PIN M14 [get_ports Flash_Hold_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Hold_N]
+set_property PACKAGE_PIN L14 [get_ports Flash_Wp_N]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Wp_N]
+set_property PACKAGE_PIN R10 [get_ports Flash_Clk]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Clk]
+set_property PACKAGE_PIN K18 [get_ports Flash_Do]
+set_property IOSTANDARD LVCMOS33 [get_ports Flash_Do]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: led
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN M17 [get_ports {Led_N[1]}]
+set_property PACKAGE_PIN M16 [get_ports {Led_N[0]}]
+set_property PACKAGE_PIN M18 [get_ports {Led_N[3]}]
+set_property PACKAGE_PIN L18 [get_ports {Led_N[2]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars ax3: system
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN R11 [get_ports Pwr_Good]
+set_property IOSTANDARD LVCMOS33 [get_ports Pwr_Good]
+set_property PACKAGE_PIN N15 [get_ports {Reset_N}]
+set_property IOSTANDARD LVCMOS33 [get_ports {Reset_N}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: fmc lpc connector
+# -------------------------------------------------------------------------------------------------
+set_property PACKAGE_PIN T4 [get_ports {CLK_TO_FPGA_N}]
+set_property PACKAGE_PIN T5 [get_ports {CLK_TO_FPGA_P}]
+set_property PACKAGE_PIN D3 [get_ports {CLK_FROM_FPGA_N}]
+set_property PACKAGE_PIN E3 [get_ports {CLK_FROM_FPGA_P}]
+
+set_property PACKAGE_PIN N5 [get_ports {CLK_GEN_LOL_N}]
+set_property PACKAGE_PIN C1 [get_ports {CLK_GEN_RST_N}]
+set_property PACKAGE_PIN C2 [get_ports {I2C_RESET_N}]
+set_property PACKAGE_PIN F6 [get_ports {GPIO}]
+
+set_property PACKAGE_PIN P5 [get_ports {CONT_TO_FPGA[0]}]
+set_property PACKAGE_PIN P3 [get_ports {CONT_TO_FPGA[1]}]
+set_property PACKAGE_PIN N6 [get_ports {CONT_TO_FPGA[2]}]
+set_property PACKAGE_PIN L5 [get_ports {CONT_TO_FPGA[3]}]
+
+# Warning - can't find CONT_FROM_FPGA[0] in Allegro netlist ....
+set_property PACKAGE_PIN P4 [get_ports {CONT_FROM_FPGA[1]}]
+set_property PACKAGE_PIN M6 [get_ports {CONT_FROM_FPGA[2]}]
+set_property PACKAGE_PIN L6 [get_ports {CONT_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN M1 [get_ports {SPARE_TO_FPGA[0]}]
+set_property PACKAGE_PIN N4 [get_ports {SPARE_TO_FPGA[1]}]
+set_property PACKAGE_PIN N1 [get_ports {SPARE_TO_FPGA[2]}]
+set_property PACKAGE_PIN M2 [get_ports {SPARE_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN L1 [get_ports {SPARE_FROM_FPGA[0]}]
+set_property PACKAGE_PIN M4 [get_ports {SPARE_FROM_FPGA[1]}]
+set_property PACKAGE_PIN N2 [get_ports {SPARE_FROM_FPGA[2]}]
+set_property PACKAGE_PIN M3 [get_ports {SPARE_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN R5 [get_ports {TRIG_TO_FPGA[0]}]
+set_property PACKAGE_PIN R2 [get_ports {TRIG_TO_FPGA[1]}]
+set_property PACKAGE_PIN T1 [get_ports {TRIG_TO_FPGA[2]}]
+set_property PACKAGE_PIN V1 [get_ports {TRIG_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R6 [get_ports {TRIG_FROM_FPGA[0]}]
+set_property PACKAGE_PIN P2 [get_ports {TRIG_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R1 [get_ports {TRIG_FROM_FPGA[2]}]
+set_property PACKAGE_PIN U1 [get_ports {TRIG_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN T6 [get_ports {BUSY_TO_FPGA[0]}]
+set_property PACKAGE_PIN U3 [get_ports {BUSY_TO_FPGA[1]}]
+set_property PACKAGE_PIN T8 [get_ports {BUSY_TO_FPGA[2]}]
+set_property PACKAGE_PIN L4 [get_ports {BUSY_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN R7 [get_ports {BUSY_FROM_FPGA[0]}]
+set_property PACKAGE_PIN U4 [get_ports {BUSY_FROM_FPGA[1]}]
+set_property PACKAGE_PIN R8 [get_ports {BUSY_FROM_FPGA[2]}]
+set_property PACKAGE_PIN K5 [get_ports {BUSY_FROM_FPGA[3]}]
+
+set_property PACKAGE_PIN L3 [get_ports {DUT_CLK_TO_FPGA[0]}]
+set_property PACKAGE_PIN F3 [get_ports {DUT_CLK_TO_FPGA[1]}]
+set_property PACKAGE_PIN D2 [get_ports {DUT_CLK_TO_FPGA[2]}]
+set_property PACKAGE_PIN G3 [get_ports {DUT_CLK_TO_FPGA[3]}]
+
+set_property PACKAGE_PIN K3 [get_ports {DUT_CLK_FROM_FPGA_P[0]}]
+set_property PACKAGE_PIN F4 [get_ports {DUT_CLK_FROM_FPGA_P[1]}]
+set_property PACKAGE_PIN E2 [get_ports {DUT_CLK_FROM_FPGA_P[2]}]
+set_property PACKAGE_PIN G4 [get_ports {DUT_CLK_FROM_FPGA_P[3]}]
+
+set_property PACKAGE_PIN A1 [get_ports {BEAM_TRIGGER_N[0]}]
+set_property PACKAGE_PIN B1 [get_ports {BEAM_TRIGGER_P[0]}]
+set_property PACKAGE_PIN B4 [get_ports {BEAM_TRIGGER_N[1]}]
+set_property PACKAGE_PIN C4 [get_ports {BEAM_TRIGGER_P[1]}]
+set_property PACKAGE_PIN K1 [get_ports {BEAM_TRIGGER_N[2]}]
+set_property PACKAGE_PIN K2 [get_ports {BEAM_TRIGGER_P[2]}]
+set_property PACKAGE_PIN C5 [get_ports {BEAM_TRIGGER_N[3]}]
+set_property PACKAGE_PIN C6 [get_ports {BEAM_TRIGGER_P[3]}]
+set_property PACKAGE_PIN H4 [get_ports {BEAM_TRIGGER_N[4]}]
+set_property PACKAGE_PIN J4 [get_ports {BEAM_TRIGGER_P[4]}]
+set_property PACKAGE_PIN G1 [get_ports {BEAM_TRIGGER_N[5]}]
+set_property PACKAGE_PIN H1 [get_ports {BEAM_TRIGGER_P[5]}]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ft232 uart interface
+# -------------------------------------------------------------------------------------------------
+
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B3 [get_ports FTDI_TXD]
+set_property PACKAGE_PIN B2 [get_ports FTDI_RXD]
+
+# -------------------------------------------------------------------------------------------------
+# mars pm3: ez-usb fx3 interface
+# -------------------------------------------------------------------------------------------------
+
+set_property PACKAGE_PIN V2 [get_ports FX3_A1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_A1]
+set_property PACKAGE_PIN V7 [get_ports FX3_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_CLK]
+set_property PACKAGE_PIN U12 [get_ports FX3_DQ0]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ0]
+set_property PACKAGE_PIN R15 [get_ports FX3_DQ1]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ1]
+set_property PACKAGE_PIN U9 [get_ports FX3_DQ10]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ10]
+set_property PACKAGE_PIN V5 [get_ports FX3_DQ11]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ11]
+set_property PACKAGE_PIN T3 [get_ports FX3_DQ12]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ12]
+set_property PACKAGE_PIN R3 [get_ports FX3_DQ13]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ13]
+set_property PACKAGE_PIN V4 [get_ports FX3_DQ14]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ14]
+set_property PACKAGE_PIN U7 [get_ports FX3_DQ15]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ15]
+set_property PACKAGE_PIN V12 [get_ports FX3_DQ2]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ2]
+set_property PACKAGE_PIN P15 [get_ports FX3_DQ3]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ3]
+set_property PACKAGE_PIN U11 [get_ports FX3_DQ4]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ4]
+set_property PACKAGE_PIN U13 [get_ports FX3_DQ5]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ5]
+set_property PACKAGE_PIN T13 [get_ports FX3_DQ6]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ6]
+set_property PACKAGE_PIN T11 [get_ports FX3_DQ7]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ7]
+set_property PACKAGE_PIN V9 [get_ports FX3_DQ8]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ8]
+set_property PACKAGE_PIN U6 [get_ports FX3_DQ9]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_DQ9]
+set_property PACKAGE_PIN V6 [get_ports FX3_FLAGA]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGA]
+set_property PACKAGE_PIN U2 [get_ports FX3_FLAGB]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_FLAGB]
+set_property PACKAGE_PIN T10 [get_ports FX3_PKTEND_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_PKTEND_N]
+set_property PACKAGE_PIN T9 [get_ports FX3_SLOE_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLOE_N]
+set_property PACKAGE_PIN R12 [get_ports FX3_SLRD_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLRD_N]
+set_property PACKAGE_PIN R13 [get_ports FX3_SLWR_N]
+set_property IOSTANDARD LVCMOS33 [get_ports FX3_SLWR_N]
+
+# -------------------------------------------------------------------------------------------------
+# timing constraints
+# -------------------------------------------------------------------------------------------------
+
+
+create_clock -name {Clk_50} -period 20.000 [get_ports {Clk_50}]
+
+
+# -------------------------------------------------------------------------------------------------
+# eof
+# -------------------------------------------------------------------------------------------------
+
+
+