From 9fe99a24dd6b67b49daa00cd3e49732b3041bfdf Mon Sep 17 00:00:00 2001
From: David Cussans <David.Cussans@bristol.ac.uk>
Date: Fri, 4 May 2018 17:18:33 +0100
Subject: [PATCH] * Tidying up build files ( removing references to unused top
level file) * Edited T0_Shutter_Iface_rtl.vhd to enable shutter when T0 is
pulsed. Modified TLU_v1e.py and startTLU_v1e.py accordingly ( N.B. **** There
is a bug in the code that enables/disables shutter when pulseT0 is written. )
---
.../firmware/cfg/enclustra_ax3_pm3_a35.dep | 2 +-
.../firmware/cfg/enclustra_ax3_pm3_a50.dep | 2 +-
.../tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd | 35 ++++-----
.../firmware/cfg/enclustra_ax3_pm3_a50.dep | 2 +-
projects/TLU_v1e/firmware/cfg/tlu_1e.dep | 10 +--
.../TLU_v1e/firmware/hdl/ipbus_decode_top.vhd | 51 -------------
projects/TLU_v1e/firmware/ucf/I2C_constr.xdc | 71 +++++++++++++++++++
.../firmware/ucf/TLU_enclustra_v1e.xdc | 17 ++---
projects/TLU_v1e/scripts/TLU_v1e.py | 35 +++++++--
projects/TLU_v1e/scripts/localConf.conf | 4 +-
projects/TLU_v1e/scripts/startTLU_v1e.py | 3 +-
11 files changed, 137 insertions(+), 95 deletions(-)
delete mode 100644 projects/TLU_v1e/firmware/hdl/ipbus_decode_top.vhd
diff --git a/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep b/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep
index 7dbd068f..bfe69db8 100644
--- a/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep
+++ b/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep
@@ -5,7 +5,7 @@
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
-src top_enclustra_ax3_pm3.vhd
+# src top_enclustra_ax3_pm3.vhd
include enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src --cd ../ucf enclustra_ax3_pm3.tcl
diff --git a/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep b/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep
index 0f93b8f0..83f08bf1 100644
--- a/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep
+++ b/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a50.dep
@@ -5,7 +5,7 @@
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
-src top_enclustra_ax3_pm3.vhd
+# src top_enclustra_ax3_pm3.vhd
include enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src --cd ../ucf enclustra_ax3_pm3.tcl
diff --git a/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd b/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
index 26a3c637..6a08d1fc 100644
--- a/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
+++ b/components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
@@ -81,15 +81,15 @@ ARCHITECTURE rtl OF T0_Shutter_Iface IS
signal s_enable_sequence : std_logic ; --! take high to enable sequence
signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
signal s_T0_ipbus : std_logic; --! T0 synchronization signal on IPBus clock domain.
-
- constant c_NUM_CTRL_REGS : integer := 8;
+ signal s_run_active : std_logic; --! Take active to issue T0 pulse and enable shutters
+ constant c_NUM_CTRL_REGS : integer := 9;
constant c_NUM_STAT_REGS : integer := 1;
signal s_ipbus_statusregs: ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1'));
- constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write here for T0 pulse
+ constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write 1 to bit 0 of this address to produce a enable shutters and produce T0 pulse
begin
@@ -131,7 +131,9 @@ begin
rstb => open
);
- s_enable_sequence <= s_ipbus_controlregs(0)(0);
+ s_enable_sequence <= ( s_ipbus_controlregs(0)(0) and s_run_active ) when (rising_edge(clk_4x_i) and (clk_4x_strobe_i = '1'));
+ s_run_active <= s_ipbus_controlregs(8)(0); --! Set to 1 to issue T0 and start shutter
+
s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
s_trigger_source_select <= s_ipbus_controlregs(1);
@@ -141,28 +143,29 @@ begin
s_internal_cycle_length <= s_ipbus_controlregs(2);
+
-- A bodge. I can't figure out which standard IPBus register generates a
-- pulse, so put this logic in parallel.
--------------------
- ipbus_generateT0: process (ipbus_clk_i)
- begin -- process ipbus_clk_i
- if rising_edge(ipbus_clk_i) then
-
- if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
- s_T0_ipbus <= '1'; -- set T0 signal high
- else
- s_T0_ipbus <= '0';
- end if;
+ -- ipbus_generateT0: process (ipbus_clk_i)
+ -- begin -- process ipbus_clk_i
+ -- if rising_edge(ipbus_clk_i) then
+--
+-- if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
+-- s_T0_ipbus <= '1'; -- set T0 signal high
+-- else
+-- s_T0_ipbus <= '0';
+-- end if;
- end if;
- end process ipbus_generateT0;
+-- end if;
+-- end process ipbus_generateT0;
--! Retime T0 generated by IPBus onto clk_4x and align with strobe
cmp_T0_retime: entity work.stretchPulse4x
port map (
clk_4x_i => clk_4x_i,
clk_4x_strobe_i => clk_4x_strobe_i,
- pulse_i => s_T0_ipbus,
+ pulse_i => s_run_active,
pulse_o => T0_o);
END rtl;
diff --git a/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep b/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep
index 32eca904..188aaf40 100644
--- a/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep
+++ b/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a50.dep
@@ -5,7 +5,7 @@
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
-src top_enclustra_ax3_pm3.vhd
+# src top_enclustra_ax3_pm3.vhd
include -c boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src -c components/pdts --cd ../ucf pc053_ax3_pm3.tcl
diff --git a/projects/TLU_v1e/firmware/cfg/tlu_1e.dep b/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
index 53e8dcc6..4b212e4c 100644
--- a/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
+++ b/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
@@ -8,7 +8,6 @@ src -c ipbus-firmware:components/ipbus_slaves ipbus_syncreg_v.vhd
src -c ipbus-firmware:components/ipbus_slaves syncreg_w.vhd
src -c ipbus-firmware:components/ipbus_slaves syncreg_r.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
-src ipbus_decode_top.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
@@ -41,14 +40,7 @@ src -c components/tlu single_pulse_rtl.vhd
src -c components/tlu stretchPulse_rtl.vhd
src -c components/tlu coincidenceLogic_rtl.vhd
-# ***** CHANGE ME ******
-# Hand-hacked IPBus address deocde.
-# replace with version generated by IPBus tools
-# Move the constants in this file to fmcTLU package.
-#src -c components/tlu ipbus_decode_tlu.vhd
-# ***** CHANGE ME ******
-# Fixed ?
-#src -c components/tlu ipbus_decode_TLUaddrmap.vhd
+# IPBus address map generated from XML file
src -c projects/TLU_v1e ipbus_decode_TLUaddrmap.vhd
diff --git a/projects/TLU_v1e/firmware/hdl/ipbus_decode_top.vhd b/projects/TLU_v1e/firmware/hdl/ipbus_decode_top.vhd
deleted file mode 100644
index d0131543..00000000
--- a/projects/TLU_v1e/firmware/hdl/ipbus_decode_top.vhd
+++ /dev/null
@@ -1,51 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_top is
-
- constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL the Thu Mar 16 19:57:25 2017
- constant N_SLV_CSR: integer := 0;
- constant N_SLV_IO: integer := 1;
- constant N_SLAVES: integer := 2;
--- END automatically generated VHDL
-
-
-end ipbus_decode_top;
-
-package body ipbus_decode_top is
-
- function ipbus_sel_top(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL the Thu Mar 16 19:57:25 2017
- if std_match(addr, "-------------------------0------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x00000040
- elsif std_match(addr, "-------------------------1------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_IO, IPBUS_SEL_WIDTH)); -- io / base 0x00000040 / mask 0x00000040
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_top;
-
-end ipbus_decode_top;
-
diff --git a/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc b/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
index f756f4ae..54f54f3d 100644
--- a/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
+++ b/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
@@ -21,3 +21,74 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
+
+create_debug_core u_ila_0 ila
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
+set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 4 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property port_width 1 [get_debug_ports u_ila_0/clk]
+connect_debug_port u_ila_0/clk [get_nets [list I4/clk_4x_logic_o]]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+set_property port_width 6 [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {I5/trigger_o[0]} {I5/trigger_o[1]} {I5/trigger_o[2]} {I5/trigger_o[3]} {I5/trigger_o[4]} {I5/trigger_o[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+set_property port_width 6 [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {I10/trigger_o[0]} {I10/trigger_o[1]} {I10/trigger_o[2]} {I10/trigger_o[3]} {I10/trigger_o[4]} {I10/trigger_o[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+set_property port_width 6 [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {triggers[0]} {triggers[1]} {triggers[2]} {triggers[3]} {triggers[4]} {triggers[5]}]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+set_property port_width 1 [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list buffer_full_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+set_property port_width 1 [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list s_shutter]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+set_property port_width 1 [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list I8/cmp_SyncGen/s_shutter]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+set_property port_width 1 [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list shutter_veto_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+set_property port_width 1 [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list I6/trigger_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+set_property port_width 1 [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list I10/cmp_coincidence_logic/trigger_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+set_property port_width 1 [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list veto_i]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+set_property port_width 1 [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list I9/veto_o]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+set_property port_width 1 [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list I10/s_post_veto_trigger0]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+set_property port_width 1 [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list I10/s_post_veto_trigger1]]
+create_debug_port u_ila_0 probe
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+set_property port_width 1 [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list I10/s_pre_veto_trigger_reg_n_0]]
+set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk_4x_logic]
diff --git a/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc b/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
index 909d903c..31129fd6 100644
--- a/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
+++ b/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
@@ -5,18 +5,18 @@
#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
-set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
-set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
+set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
-set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
+set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
-set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
+set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
-set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
+set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
-set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
+set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
+set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
## Miscellaneous I/O
set_property IOSTANDARD LVCMOS25 [get_ports clk_gen_rst]
@@ -27,8 +27,8 @@ set_property PACKAGE_PIN F6 [get_ports gpio]
## Crystal clock
set_property IOSTANDARD LVDS_25 [get_ports sysclk_40_i_p]
-set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
set_property PACKAGE_PIN T5 [get_ports sysclk_40_i_p]
+set_property PACKAGE_PIN T4 [get_ports sysclk_40_i_n]
## Output clock (currently not working so set to 0)
set_property IOSTANDARD LVCMOS25 [get_ports sysclk_50_o_p]
@@ -116,7 +116,8 @@ set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-# -false_path
+# -false_path
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {sysclk clk_ipb_i}] -group [get_clocks -include_generated_clocks {s_clk160 sysclk_40_i_p}]
+
diff --git a/projects/TLU_v1e/scripts/TLU_v1e.py b/projects/TLU_v1e/scripts/TLU_v1e.py
index d1e31038..8fc95bf8 100644
--- a/projects/TLU_v1e/scripts/TLU_v1e.py
+++ b/projects/TLU_v1e/scripts/TLU_v1e.py
@@ -401,6 +401,12 @@ class TLU:
print "\tShutter control read back as:" , hex(shutterControl)
return shutterControl
+ def getShutterSource(self):
+ shutterSource = self.hw.getNode("Shutter.ShutterSelectW").read()
+ self.hw.dispatch()
+ print "\tShutter source read back as:" , shutterSource
+ return shutterSource
+
def getShutterInternalInterval(self):
shutterInternalInterval = self.hw.getNode("Shutter.InternalShutterPeriodW").read()
self.hw.dispatch()
@@ -424,14 +430,18 @@ class TLU:
self.hw.dispatch()
print "\tVeto off time:" , vetoofftime
return vetoofftime
-
-
-
- def pulseT0(self):
+
+ def setRunActive(self):
cmd = int("0x1",16)
self.hw.getNode("Shutter.PulseT0").write(cmd)
self.hw.dispatch()
- print "\tPulsing T0"
+ print "\tSet run active (pulsing T0)"
+
+ def setRunInactive(self):
+ cmd = int("0x0",16)
+ self.hw.getNode("Shutter.PulseT0").write(cmd)
+ self.hw.dispatch()
+ print "\tSet run inactive"
def readEEPROM(self, startadd, bytes):
mystop= 1
@@ -553,6 +563,12 @@ class TLU:
self.hw.dispatch()
self.getShutterControl()
+ def setShutterSource(self, source):
+ print " SHUTTER SOURCE:", hex(source)
+ self.hw.getNode("Shutter.ShutterSelectW").write(source)
+ self.hw.dispatch()
+ self.getShutterSource()
+
def setShutterInternalInterval(self, interval):
print " SHUTTER INTERNAL INTERVAL:", interval
self.hw.getNode("Shutter.InternalShutterPeriodW").write(interval)
@@ -900,6 +916,9 @@ class TLU:
triggerInterval= parsed_cfg.getint(section_name, "InternalTriggerFreq")
self.setInternalTrg(triggerInterval)
+ shutterSource = int(parsed_cfg.get(section_name, "ShutterSource"), 16)
+ self.setShutterSource(shutterSource)
+
shutterControl = int(parsed_cfg.get(section_name, "ShutterControl"), 16)
self.setShutterControl(shutterControl)
@@ -936,7 +955,8 @@ class TLU:
self.setRecordDataStatus(False)
# Pulse T0
- self.pulseT0()
+ #self.pulseT0()
+ self.setRunActive()
print " Turning off software trigger veto"
self.setTriggerVetoStatus( int("0x0",16) )
@@ -959,6 +979,9 @@ class TLU:
print " Turning on software trigger veto"
self.setTriggerVetoStatus( int("0x1",16) )
+ print "Turning off shutter (setting run inactive)"
+ self.setRunInactive()
+
nFifoWords= int(eventFifoFillLevel)
fifoData= self.getFifoData(nFifoWords)
diff --git a/projects/TLU_v1e/scripts/localConf.conf b/projects/TLU_v1e/scripts/localConf.conf
index 3746af91..4150cfc9 100644
--- a/projects/TLU_v1e/scripts/localConf.conf
+++ b/projects/TLU_v1e/scripts/localConf.conf
@@ -61,8 +61,10 @@ DUTIgnoreShutterVeto = 0x0
# Generate internal triggers (in Hz, 0= no triggers)
InternalTriggerFreq = 1000000
+#InternalTriggerFreq = 0
-ShutterControl = 3
+ShutterControl = 0
+ShutterSource = 5
InternalShutterInterval = 1024
ShutterOnTime = 200
ShutterVetoOffTime = 300
diff --git a/projects/TLU_v1e/scripts/startTLU_v1e.py b/projects/TLU_v1e/scripts/startTLU_v1e.py
index 1961e017..ae476118 100644
--- a/projects/TLU_v1e/scripts/startTLU_v1e.py
+++ b/projects/TLU_v1e/scripts/startTLU_v1e.py
@@ -83,7 +83,8 @@ class MyPrompt(cmd.Cmd):
else:
runN= arglist[0]
- logdata= True
+# logdata= True
+ logdata= False
#TLU.start(logdata)
if (TLU.isRunning): #Prevent double start
--
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