From 56e9fb165d324f9de968e91e414fe0a25fd0c9b5 Mon Sep 17 00:00:00 2001
From: David Cussans <David.Cussans@bristol.ac.uk>
Date: Tue, 18 Mar 2014 14:22:38 +0000
Subject: [PATCH] Checking in modified build scripts (*.tcl), more work on
simulation ( test-bench, pulse generator )
---
firmware/Introduction.markdown | 4 +-
firmware/README.markdown | 44 -
.../config/ise14/sp601/build_bitstream.tcl | 2 +-
firmware/config/ise14/sp601/setup_project.tcl | 21 +-
.../config/ise14/sp605/build_bitstream.tcl | 2 +-
firmware/config/ise14/sp605/setup_project.tcl | 17 +-
firmware/hdl/common/IPBusInterface_rtl.vhd | 8 +-
firmware/hdl/common/clocks_s6_extphy.vhd | 3 +-
firmware/hdl/common/counterWithReset_rtl.vhd | 2 +-
firmware/hdl/common/dualSERDES_1to4_rtl.vhd | 83 +-
firmware/hdl/common/eventBuffer_rtl.vhd | 14 +-
firmware/hdl/common/ipbus_addr_decode.vhd | 2 -
firmware/hdl/common/ipbus_ver.vhd | 2 +-
firmware/hdl/common/logic_clocks_rtl.vhd | 163 +-
firmware/hdl/common/triggerInputs_rtl.vhd | 101 +-
firmware/hdl/test/clock_divider_s6.v | 3 +-
.../fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd | 3 +
.../fmc_mTLU_lib/hdl/top_extphy_struct.vhd | 8 +-
firmware/scripts/FmcTluI2c.py | 28 +-
firmware/scripts/aida_mini_tlu_addr_map.txt | 6 +-
firmware/scripts/setup.sh | 88 -
firmware/scripts/test_aida_tlu_thresholds.py | 19 +-
.../scripts/test_aida_tlu_trig_counter.py | 93 +
.../questa/fmctlu_v0_1_testbench.fdo | 115 +
.../questa/fmctlu_v0_1_testbench.udo | 10 +
.../questa/fmctlu_v0_1_testbench_wave.fdo | 12 +
firmware/simulation/questa/modelsim.ini | 1868 +++++++++++++++++
firmware/simulation/scripts/addfiles_sim.tcl | 38 +
firmware/simulation/scripts/file_list | 67 +
firmware/simulation/scripts/setup.sh | 12 +
firmware/simulation/scripts/setup_project.tcl | 24 +
.../fmc-tlu_v0-1_test-bench.vhd | 182 ++
.../simulation_src/pmtPulseGenerator_rtl.vhd | 152 ++
33 files changed, 2867 insertions(+), 329 deletions(-)
delete mode 100755 firmware/README.markdown
delete mode 100755 firmware/scripts/setup.sh
create mode 100644 firmware/scripts/test_aida_tlu_trig_counter.py
create mode 100644 firmware/simulation/questa/fmctlu_v0_1_testbench.fdo
create mode 100644 firmware/simulation/questa/fmctlu_v0_1_testbench.udo
create mode 100644 firmware/simulation/questa/fmctlu_v0_1_testbench_wave.fdo
create mode 100644 firmware/simulation/questa/modelsim.ini
create mode 100644 firmware/simulation/scripts/addfiles_sim.tcl
create mode 100644 firmware/simulation/scripts/file_list
create mode 100644 firmware/simulation/scripts/setup.sh
create mode 100644 firmware/simulation/scripts/setup_project.tcl
create mode 100644 firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
create mode 100644 firmware/simulation_src/pmtPulseGenerator_rtl.vhd
diff --git a/firmware/Introduction.markdown b/firmware/Introduction.markdown
index 0f253ed0..474bbb1d 100644
--- a/firmware/Introduction.markdown
+++ b/firmware/Introduction.markdown
@@ -41,8 +41,10 @@ necessary to use HDL-Designer to build the firmware. In fact the VHDL
files produced by HDL-Designer can also be edited "by hand" without
using the tool.
+A block diagram, generated by HDL-Designer, is [here](http://www.ohwr.org/attachments/2710/hdl_designer_test_print_2.pdf)
+
Building Firmware
-----------------
Instructions on building the firmware are found
-[here](@ref buildingfirmware).
+[here](http://www.ohwr.org/projects/fmc-mtlu/wiki/FirmwareBuild).
diff --git a/firmware/README.markdown b/firmware/README.markdown
deleted file mode 100755
index 374a652f..00000000
--- a/firmware/README.markdown
+++ /dev/null
@@ -1,44 +0,0 @@
-
-Firmware for AIDA miniTLU {#buildingfirmware}
-=========================
-
-Uses the "IPBus" system to communuicate via Ethernet to host.
-
-Needs Xilinx ISE tools to build. The scripts assume ISE 14.6 or newer.
-
-Needs a licence for the Xilinx Gigabit ethernet soft core (
-tri_mode_eth_mac ) if using an external Physical interface chip
-(e.g. for "Copper" Ethernet interface).
-
-Needs "IPBus" to communuicate via Ethernet to host.
-
-Scripts developed on a Linux PC. Need to use custom scripts because the
-standard Xilinx auto-generated ones "contaminate" directories that are under
-version-management control with files generated by core regeneration process.
-
-Firmware build scripts may work under Windows/Cygwin or Windows/MinGW
-but not tested.
-
-To build firmware:
-
-1. Install Xilinx ISE 14.6 (or newer) and set up the environment variables.
-2. Create a working directory somewhere , <working_directory>
-3. <pre> cd <working_directory> </pre>
-4. Get a copy of the build scripts:
- + <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/setup_workspace.sh > setup_workspace.sh </pre>
- + <pre> svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/build_bitstream.sh > build_bitstream.sh </pre>
- + Edit setup_workspace.sh to reflect which FPGA carrier board you want to build the firmware for.Currently supported boards: Xilinx SP601 , Xilinx SP605 . Default is SP601
-5. Execute the script to set-up the ISE project:
-<pre> sh setup_workspace.sh </pre>
-This will check out copies of the IPBus and AIDA mini-TLU repositories,
-create a directory for the files produced by firmware synthesise
-and create a Xilinx ISE project file.
-6. Produce the bit-stream
- + either:
- + - Open the Xilinx project file at <working_directory>/workspace/fmc-mtlu.xise
- + - Select Tools->COREGEN
- + - When Coregen starts select Project->Upgrade and Regenerate all project IP ( this will take several minutes )
- + - Make sure the top-level file is selected and click on "Generate Programming File"
- + or:
- + - Execute the build_bitstream.sh script.
-
diff --git a/firmware/config/ise14/sp601/build_bitstream.tcl b/firmware/config/ise14/sp601/build_bitstream.tcl
index 879b8b51..baa74278 100644
--- a/firmware/config/ise14/sp601/build_bitstream.tcl
+++ b/firmware/config/ise14/sp601/build_bitstream.tcl
@@ -7,7 +7,7 @@ catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
-catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
diff --git a/firmware/config/ise14/sp601/setup_project.tcl b/firmware/config/ise14/sp601/setup_project.tcl
index 51160aec..52976d9e 100644
--- a/firmware/config/ise14/sp601/setup_project.tcl
+++ b/firmware/config/ise14/sp601/setup_project.tcl
@@ -68,6 +68,12 @@ xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_v.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
+#xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
+#xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
@@ -85,7 +91,7 @@ exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_di
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
-xfile add ipcore_dir/CounterUp.xco
+# xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
@@ -107,16 +113,19 @@ xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
-xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
-xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
+# xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
+xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
diff --git a/firmware/config/ise14/sp605/build_bitstream.tcl b/firmware/config/ise14/sp605/build_bitstream.tcl
index 879b8b51..baa74278 100644
--- a/firmware/config/ise14/sp605/build_bitstream.tcl
+++ b/firmware/config/ise14/sp605/build_bitstream.tcl
@@ -7,7 +7,7 @@ catch {exec coregen -r -b mac_fifo_axi4.xco -p coregen.cgp}
catch {exec coregen -r -b tlu_event_fifo.xco -p coregen.cgp}
catch {exec coregen -r -b FIFO.xco -p coregen.cgp}
-catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
+# catch {exec coregen -r -b CounterUp.xco -p coregen.cgp}
catch {exec coregen -r -b internalTriggerGenerator.xco -p coregen.cgp}
diff --git a/firmware/config/ise14/sp605/setup_project.tcl b/firmware/config/ise14/sp605/setup_project.tcl
index b9ae8fa0..bd36bd53 100644
--- a/firmware/config/ise14/sp605/setup_project.tcl
+++ b/firmware/config/ise14/sp605/setup_project.tcl
@@ -67,6 +67,11 @@ xfile add ipbus/firmware/ipbus_core/hdl/stretcher.vhd
xfile add ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
xfile add ipbus/firmware/example_designs/hdl/clock_div.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+xfile add ipbus/firmware/slaves/hdl/syncreg_r.vhd
+xfile add ipbus/firmware/slaves/hdl/syncreg_w.vhd
+xfile add ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+
# Add Opencores files for i2c interface
xfile add external/opencores_i2c/i2c_master_bit_ctrl.vhd
xfile add external/opencores_i2c/i2c_master_byte_ctrl.vhd
@@ -84,7 +89,7 @@ exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_di
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
-xfile add ipcore_dir/CounterUp.xco
+#xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
@@ -106,16 +111,18 @@ xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
-xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
-xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
+xfile add fmc-mtlu/firmware/hdl/common/serdesCalibrateFSM_rtl.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
+#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
+xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
# Then add the HDL-Designer generated files..
xfile add fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
diff --git a/firmware/hdl/common/IPBusInterface_rtl.vhd b/firmware/hdl/common/IPBusInterface_rtl.vhd
index 8d94dd84..3916f8a9 100644
--- a/firmware/hdl/common/IPBusInterface_rtl.vhd
+++ b/firmware/hdl/common/IPBusInterface_rtl.vhd
@@ -78,7 +78,7 @@ END ENTITY IPBusInterface ;
ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
- constant c_NUM_INTERNAL_SLAVES : positive := 2;
+ constant c_NUM_INTERNAL_SLAVES : positive := 1;
signal clk125, locked, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
@@ -194,11 +194,9 @@ BEGIN
-- Slave: firmware ID
firmware_id: entity work.ipbus_ver
port map(
- ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2),
- ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-2)
+ ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
+ ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
);
- -- N.B. Remove port to s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
- -- No longer used by hostbus
END ARCHITECTURE rtl;
diff --git a/firmware/hdl/common/clocks_s6_extphy.vhd b/firmware/hdl/common/clocks_s6_extphy.vhd
index 296872f3..c64f1777 100644
--- a/firmware/hdl/common/clocks_s6_extphy.vhd
+++ b/firmware/hdl/common/clocks_s6_extphy.vhd
@@ -29,7 +29,8 @@ end clocks_s6_extphy;
architecture rtl of clocks_s6_extphy is
- signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk , sysclk_in: std_logic;
+ signal clk_ipb_i, clk_ipb_b, clk_125_i, clk_125_b, sysclk : std_logic;
+ -- signal sysclk_in : std_logic;
signal d25, d25_d, dcm_locked: std_logic;
signal rst: std_logic := '1';
signal s_xtal_dcm_locked: std_logic;
diff --git a/firmware/hdl/common/counterWithReset_rtl.vhd b/firmware/hdl/common/counterWithReset_rtl.vhd
index f88057de..ebe40030 100644
--- a/firmware/hdl/common/counterWithReset_rtl.vhd
+++ b/firmware/hdl/common/counterWithReset_rtl.vhd
@@ -59,7 +59,7 @@ END counterWithReset;
ARCHITECTURE rtl OF counterWithReset IS
type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
- signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0); -- --! Output registers.
+ signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0')); -- --! Output registers.
BEGIN
diff --git a/firmware/hdl/common/dualSERDES_1to4_rtl.vhd b/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
index c2092b1d..b2857a0f 100644
--- a/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+++ b/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
@@ -48,14 +48,16 @@ use unisim.vcomponents.all;
ENTITY dualSERDES_1to4 IS
PORT(
- serdes_reset_i : IN std_logic; --! Starts recalibration sequence and resets the ISERDES
- data_i : IN std_logic;
+ reset_i : IN std_logic; --! Resets IODELAY
+ calibrate_i : IN std_logic; --! Starts IODELAY calibration.
+ data_i : IN std_logic; --! from input buffer.
fastClk_i : IN std_logic; --! 4x fabric clock. e.g. 640MHz
fabricClk_i : IN std_logic; --! clock for output to FPGA. e.g. 160MHz
strobe_i : IN std_logic; --! Strobes once every 4 cycles of fastClk
data_o : OUT std_logic_vector (7 DOWNTO 0); --! Deserialized data. Interleaved between prompt and delayed serdes.
--! data_o(0) is the oldest data
- serdes_ready_o : OUT std_logic --! goes low during calibration sequence.
+ status_o : OUT std_logic_vector(1 downto 0) --! outputs from IODELAY "busy" 0=prompt,1=delayed
+
);
-- Declarations
@@ -69,11 +71,11 @@ ARCHITECTURE rtl OF dualSERDES_1to4 IS
signal s_Data_i_d_p : std_logic;
signal s_Data_i_d_d : std_logic;
- signal s_busy_idelay_m : std_logic; -- Indicates that the IDELAY isn't calibrating.
- signal s_busy_idelay_s : std_logic; -- Indicates that the IDELAY isn't calibrating.
+-- signal s_busy_idelay_m : std_logic; -- Indicates that the IDELAY isn't calibrating.
+-- signal s_busy_idelay_s : std_logic; -- Indicates that the IDELAY isn't calibrating.
signal s_data_o : std_logic_vector(7 downto 0); --! Deserialized data
- signal s_rst : std_logic := '0'; -- IODELAY and ISERDES reset
- signal s_cal_FSM : std_logic := '0'; --! Take high to calibrate the IDELAY components
+-- signal s_rst : std_logic := '0'; -- IODELAY and ISERDES reset
+-- signal s_cal_FSM : std_logic := '0'; --! Take high to calibrate the IDELAY components
@@ -81,35 +83,34 @@ ARCHITECTURE rtl OF dualSERDES_1to4 IS
BEGIN
- calibration_fsm: entity work.serdesCalibrateFSM
- port map (
- fsm_clk_i => fabricClk_i,
- serdes_reset_i => serdes_reset_i,
- busy_idelay_m_i => s_busy_idelay_m,
- calibrate_o => s_cal_FSM,
- reset_o => s_rst);
+
+-- calibration_fsm: entity work.serdesCalibrateFSM
+-- port map (
+-- fsm_clk_i => fabricClk_i,
+-- serdes_reset_i => serdes_reset_i,
+-- busy_idelay_m_i => s_busy_idelay_m,
+-- calibrate_o => s_cal_FSM,
+-- reset_o => s_rst);
IODELAY2_Prompt : IODELAY2
generic map (
- COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- "STAY_AT_LIMIT" or "WRAPAROUND"
+ COUNTER_WRAPAROUND => "WRAPAROUND" , -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
- IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
- IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
- -- or "DIFF_PHASE_DETECTOR"
+ IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255)
- IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
- ODELAY_VALUE => 0 -- Amount of taps fixed output delay (0-255)
- --SIM_TAPDELAY_VALUE=> 50 -- Per tap delay used for simulation in ps
+ SIM_TAPDELAY_VALUE=> 75 -- Per tap delay used for simulation in ps
)
port map (
- BUSY => s_busy_idelay_m, -- 1-bit output: Busy output after CAL
+-- BUSY => s_busy_idelay_m, -- 1-bit output: Busy output after CAL
+ BUSY => status_o(1), -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_p, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
+ -- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
+ CAL => calibrate_i, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
@@ -117,8 +118,9 @@ BEGIN
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
- RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
- T => '0' -- 1-bit input: 3-state input signal
+ --RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
+ RST => reset_i, -- 1-bit input: reset_i to 1/2 of total delay period
+ T => '1' -- 1-bit input: 3-state input signal
);
@@ -127,22 +129,22 @@ BEGIN
COUNTER_WRAPAROUND => "WRAPAROUND", -- "STAY_AT_LIMIT" or "WRAPAROUND"
DATA_RATE => "SDR", -- "SDR" or "DDR"
DELAY_SRC => "IDATAIN", -- "IO", "ODATAIN" or "IDATAIN"
- IDELAY_MODE => "NORMAL", -- "NORMAL" or "PCI"
SERDES_MODE => "NONE", -- <NONE>, MASTER, SLAVE
- IDELAY_TYPE => "VARIABLE_FROM_ZERO", -- "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX"
- -- or "DIFF_PHASE_DETECTOR"
+ IDELAY_TYPE => "VARIABLE_FROM_ZERO",
IDELAY_VALUE => 0, -- Amount of taps for fixed input delay (0-255) 10->0.75nS, 11->0.825nS
IDELAY2_VALUE => 0, -- Delay value when IDELAY_MODE="PCI" (0-255)
- ODELAY_VALUE => 0 -- Amount of taps fixed output delay (0-255)
- --SIM_TAPDELAY_VALUE => 43 -- Per tap delay used for simulation in ps
+ ODELAY_VALUE => 0, -- Amount of taps fixed output delay (0-255)
+ SIM_TAPDELAY_VALUE => 75 -- Per tap delay used for simulation in ps
)
port map (
- BUSY => s_busy_idelay_s, -- 1-bit output: Busy output after CAL
+-- BUSY => s_busy_idelay_s, -- 1-bit output: Busy output after CAL
+ BUSY => status_o(0), -- 1-bit output: Busy output after CAL
DATAOUT => s_Data_i_d_d, -- 1-bit output: Delayed data output to ISERDES/input register
DATAOUT2 => open, -- 1-bit output: Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit output: Delayed data output
TOUT => open, -- 1-bit output: Delayed 3-state output
- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
+-- CAL => s_cal_FSM, -- 1-bit input: Initiate calibration input
+ CAL => calibrate_i, -- 1-bit input: Initiate calibration input
CE => '0', -- 1-bit input: Enable INC input
CLK => fabricClk_i, -- 1-bit input: Clock input
IDATAIN => data_i, -- 1-bit input: Data input (connect to top-level port or I/O buffer)
@@ -150,8 +152,9 @@ BEGIN
IOCLK0 => fastClk_i, -- 1-bit input: Input from the I/O clock network
IOCLK1 => '0', -- 1-bit input: Input from the I/O clock network
ODATAIN => '0', -- 1-bit input: Output data input from output register or OSERDES2.
- RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
- T => '0' -- 1-bit input: 3-state input signal
+ --RST => s_rst, -- 1-bit input: reset_i to zero or 1/2 of total delay period
+ RST => reset_i, -- 1-bit input: reset_i to zero
+ T => '1' -- 1-bit input: 3-state input signal
);
@@ -159,13 +162,13 @@ BEGIN
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
- DATA_WIDTH => c_S, -- Parallel data width selection (2-8)
+ DATA_WIDTH => 4, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
- Q1 => s_Data_o(0), -- oldest data
+ Q1 => s_Data_o(0), -- oldest data
Q2 => s_Data_o(2),
Q3 => s_Data_o(4),
Q4 => s_Data_o(6), -- most recent data
@@ -178,7 +181,7 @@ BEGIN
CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_p, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
- RST => serdes_reset_i, -- 1-bit input Asynchronous reset_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
@@ -186,13 +189,13 @@ BEGIN
generic map (
BITSLIP_ENABLE => FALSE, -- Enable Bitslip Functionality (TRUE/FALSE)
DATA_RATE => "SDR", -- Data-rate ("SDR" or "DDR")
- DATA_WIDTH => c_S, -- Parallel data width selection (2-8)
+ DATA_WIDTH => 4, -- Parallel data width selection (2-8)
INTERFACE_TYPE => "RETIMED", -- "NETWORKING", "NETWORKING_PIPELINED" or "RETIMED"
SERDES_MODE => "NONE" -- "NONE", "MASTER" or "SLAVE"
)
port map (
-- Q1 - Q4: 1-bit (each) output Registered outputs to FPGA logic
- Q1 => s_Data_o(1), -- Oldest data
+ Q1 => s_Data_o(1), -- Oldest data
Q2 => s_Data_o(3),
Q3 => s_Data_o(5),
Q4 => s_Data_o(7), -- most recent data
@@ -205,7 +208,7 @@ BEGIN
CLKDIV => fabricClk_i, -- 1-bit input FPGA logic domain clock input
D => s_Data_i_d_d, -- 1-bit input Input data
IOCE => strobe_i, -- 1-bit input Data strobe_i input
- RST => serdes_reset_i, -- 1-bit input Asynchronous reset_i input
+ RST => reset_i, -- 1-bit input Asynchronous reset_i input
SHIFTIN => '0' -- 1-bit input Cascade input signal for master/slave I/O
);
diff --git a/firmware/hdl/common/eventBuffer_rtl.vhd b/firmware/hdl/common/eventBuffer_rtl.vhd
index 9a637149..9f004c25 100644
--- a/firmware/hdl/common/eventBuffer_rtl.vhd
+++ b/firmware/hdl/common/eventBuffer_rtl.vhd
@@ -93,6 +93,7 @@ ARCHITECTURE rtl OF eventBuffer IS
signal s_fifo_dout : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- ! Output from FIFO ( fall-through mode)
signal s_fifo_valid : std_logic := '1'; -- ! High when data in FIFO
signal s_fifo_full, s_fifo_almost_full, s_fifo_empty, s_fifo_almost_empty : std_logic := '0'; -- ! full and empty FIFO flags
+ signal s_fifo_status_ipb , s_fifo_fill_level_d1 : std_logic_vector(ipbus_o.ipb_rdata'range) := (others => '0'); -- data registered onto IPBus clock
BEGIN
@@ -109,10 +110,10 @@ BEGIN
--! Multiplex output data.
with ipbus_i.ipb_addr(1 downto 0) select ipbus_o.ipb_rdata <=
- s_fifo_dout when "00",
- X"0000" & "00" & std_logic_vector(s_fifo_fill_level) when "01",
- X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty when "11",
- (others => '1') when others;
+ s_fifo_dout when "00",
+ s_fifo_fill_level_d1 when "01",
+ s_fifo_status_ipb when "10",
+ (others => '1') when others;
ipbus_write: process (ipbus_clk_i)
begin -- process ipbus_write
@@ -123,6 +124,11 @@ BEGIN
s_rst_fifo <= '0';
end if;
end if;
+
+ -- Register data onto IPBus clock domain to ease timing closure.
+ s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
+ s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
+
end process ipbus_write;
-----------------------------------------------------------------------------
diff --git a/firmware/hdl/common/ipbus_addr_decode.vhd b/firmware/hdl/common/ipbus_addr_decode.vhd
index e5cdb092..f30ca75d 100644
--- a/firmware/hdl/common/ipbus_addr_decode.vhd
+++ b/firmware/hdl/common/ipbus_addr_decode.vhd
@@ -45,8 +45,6 @@ package body ipbus_addr_decode is
sel := 9; -- Event_Formatter / base 00000140 / mask 0000001f
elsif std_match(addr, "-----------------------0000---0-") then
sel := 10; -- version / base 00000000 / mask 00000000
- elsif std_match(addr, "-----------------------0000---1-") then
- sel := 11; -- emac_hostbus / base 00000002 / mask 00000001
else
sel := 99;
end if;
diff --git a/firmware/hdl/common/ipbus_ver.vhd b/firmware/hdl/common/ipbus_ver.vhd
index 9e7d5319..55e79c5a 100644
--- a/firmware/hdl/common/ipbus_ver.vhd
+++ b/firmware/hdl/common/ipbus_ver.vhd
@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
- ipbus_out.ipb_rdata <= X"a5e4" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
+ ipbus_out.ipb_rdata <= X"a5ea" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
diff --git a/firmware/hdl/common/logic_clocks_rtl.vhd b/firmware/hdl/common/logic_clocks_rtl.vhd
index 5538c036..328521bf 100644
--- a/firmware/hdl/common/logic_clocks_rtl.vhd
+++ b/firmware/hdl/common/logic_clocks_rtl.vhd
@@ -80,8 +80,8 @@ ENTITY logic_clocks IS
ipbus_o : OUT ipb_rbus;
strobe_16x_logic_o : OUT std_logic; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic; -- one pulse every 4 cycles of clk_4x
- extclk_p_b : INOUT std_logic; -- either external clock in, or a clock being driven out
- extclk_n_b : INOUT std_logic;
+ extclk_p_b : OUT std_logic; -- either external clock in, or a clock being driven out
+ extclk_n_b : OUT std_logic;
clk_logic_o : OUT std_logic;
logic_clocks_locked_o : OUT std_logic;
logic_reset_o : OUT std_logic -- Goes high to reset counters etc. Sync with clk_4x_logic
@@ -97,17 +97,19 @@ ARCHITECTURE rtl OF logic_clocks IS
signal s_clk40 , s_clk40_internal : std_logic;
signal s_clk160 ,s_clk160_internal : std_logic;
signal s_clk640 , s_clk640_internal : std_logic;
- signal s_clk40_out , s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
+ signal s_clk40_out : std_logic; -- Clock generated by DDR register to feed out of chip.
+-- signal s_clk40_copy : std_logic; -- Clock generated by DDR register to feed out of chip.
-- Eventually connect up clock control & status lines to IPBus
signal s_extclk_is_input : std_logic := '1';
- signal s_extclk_is_input_buf : std_logic;
+-- signal s_extclk_is_input_buf : std_logic := '1';
signal s_clk_is_xtal : std_logic := '1';
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
- signal s_extclk, s_clk : std_logic;
- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
+ signal s_clk : std_logic;
+ --signal s_extclk : std_logic;
+ -- signal s_clk_d1 , s_strobe_4x_p1 , s_strobe_4x_logic : std_logic;
signal s_clkfbout_buf , s_clkfbout : std_logic;
signal s_strobe_generator : std_logic_vector(3 downto 0) := "1000"; -- ! Store state of ring buffer to generate strobe
@@ -123,7 +125,11 @@ ARCHITECTURE rtl OF logic_clocks IS
signal s_reset_pll : std_logic := '0';
--signal s_Reset : std_logic := '0';
- -- ! Global Reset signal
+ -- ! Global Reset signal
+
+ signal s_extclk_internal : std_logic := '0';
+
+ signal s_clock_status_ipb : std_logic_vector( ipbus_o.ipb_rdata'range ); --! Hold status of clocks
BEGIN
@@ -155,7 +161,9 @@ BEGIN
s_logic_reset_ipb_d1 <= s_logic_reset_ipb;
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
-
+
+ -- register the clock status signals onto IPBus domain.
+ s_clock_status_ipb <= x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll;
end if;
end process ipbus_write;
@@ -167,8 +175,8 @@ BEGIN
-----------------------------------------------------------------------------
with ipbus_i.ipb_addr(1 downto 0) select
ipbus_o.ipb_rdata <=
- x"0000000" & s_extclk_is_input & s_clk_is_xtal & s_locked_bufpll & s_locked_pll when "00",
- (others => '1') when others;
+ s_clock_status_ipb when "00",
+ (others => '1') when others;
-----------------------------------------------------------------------------
@@ -187,75 +195,46 @@ BEGIN
logic_reset_o <= s_logic_reset;
logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
+
+ ext_clk_obuf : OBUFDS
+ generic map (
+ IOSTANDARD => "LVDS_25")
+ port map (
+ O => extclk_p_b , -- Diff_p output (connect directly to top-level port)
+ OB => extclk_n_b , -- Diff_n output (connect directly to top-level port)
+ I => s_extclk_internal -- Buffer input
+ );
+
+ ddr_for_extclk_output : ODDR2
+ generic map(
+ DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
+ INIT => '0', -- Sets initial state of the Q output to '0' or '1'
+ SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+ port map (
+ Q => s_extclk_internal, -- 1-bit output data
+ C0 => s_clk160_internal, -- 1-bit clock input
+ C1 => not s_clk160_internal, -- 1-bit clock input
+ CE => '1', -- 1-bit clock enable input
+ D0 => '0', -- 1-bit data input (associated with C0)
+ D1 => '1', -- 1-bit data input (associated with C1)
+ R => '0', -- 1-bit reset input
+ S => '0' -- 1-bit set input
+ );
+
+ s_clk <= clk_logic_xtal_i;
--- --! Buffer external clock
--- ext_clk_io : IOBUFDS
+-- --! For now just connect input of PLL to clock from Xtal...
+-- clock_mux : BUFGMUX
-- generic map (
--- IOSTANDARD => "BLVDS_25")
+-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
+-- )
-- port map (
--- O => s_extclk, -- Buffer output
--- IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
--- IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
--- I => s_clk40_out, -- Buffer input
--- T => s_extclk_is_input_buf -- 3-state enable input, high=input, low=output
+-- O => s_clk, -- 1-bit output: Clock buffer output
+-- I0 => s_extclk, -- 1-bit input: Clock buffer input (S=0)
+-- I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
+-- S => s_clk_is_xtal -- 1-bit input: Clock buffer select
-- );
---
---
--- -- Somewhat bizzare, but if data line of an IOBUF is driven by
--- -- ODDR2 , then tri-state line must also be driven by ODDR2....
--- ddr_for_40MHz_tristate : ODDR2
--- generic map(
--- DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
--- INIT => '0', -- Sets initial state of the Q output to '0' or '1'
--- SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
--- port map (
--- Q => s_extclk_is_input_buf, -- 1-bit output data
--- C0 => s_clk40_internal, -- 1-bit clock input
--- C1 => not s_clk40_internal, -- 1-bit clock input
--- CE => '1', -- 1-bit clock enable input
--- D0 => s_extclk_is_input, -- 1-bit data input (associated with C0)
--- D1 => s_extclk_is_input, -- 1-bit data input (associated with C1)
--- R => '0', -- 1-bit reset input
--- S => '0' -- 1-bit set input
--- );
---
----- ddr_for_40MHz_output : ODDR2
----- generic map(
----- DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
----- INIT => '0', -- Sets initial state of the Q output to '0' or '1'
----- SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
----- port map (
----- Q => s_clk40_out, -- 1-bit output data
----- C0 => s_clk40_internal, -- 1-bit clock input
----- C1 => not s_clk40_internal, -- 1-bit clock input
----- CE => '1', -- 1-bit clock enable input
----- D0 => '0', -- 1-bit data input (associated with C0)
----- D1 => '1', -- 1-bit data input (associated with C1)
----- R => '0', -- 1-bit reset input
----- S => '0' -- 1-bit set input
----- );
---
- --! For now just connect input of PLL to clock from Xtal...
- clock_mux : BUFGMUX
- generic map (
- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
- )
- port map (
- O => s_clk, -- 1-bit output: Clock buffer output
- I0 => s_extclk, -- 1-bit input: Clock buffer input (S=0)
- I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
- S => s_clk_is_xtal -- 1-bit input: Clock buffer select
- );
-
- --! Buffer external clock
- ext_clk_io : IBUFGDS
- generic map (
- IOSTANDARD => "LVDS_25")
- port map (
- O => s_extclk, -- Buffer output
- I => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
- IB => extclk_n_b );
-- IBUFG_inst : IBUFG
-- generic map (
@@ -274,18 +253,19 @@ BEGIN
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
- CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT",
+ --CLK_FEEDBACK => "CLKOUT0", --"CLKFBOUT",
+ CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
- CLKOUT0_DIVIDE => 1,
+ CLKOUT0_DIVIDE => 2, -- 1-->2 move from 640 to 320
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
- CLKOUT1_DIVIDE => 4,
+ CLKOUT1_DIVIDE => 8, -- 4-->8 move from 160 to 80
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
- CLKOUT2_DIVIDE => 16,
+ CLKOUT2_DIVIDE => 32, -- 16--> 32 move from 40 to 20
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 25.000,
@@ -304,7 +284,8 @@ BEGIN
-- RST => s_logic_clk_rst,
RST => s_reset_pll,
-- Input clock control
- CLKFBIN => s_clkfbout_buf,
+-- CLKFBIN => s_clkfbout_buf,
+ CLKFBIN => s_clkfbout,
CLKIN => s_clk);
s_reset_pll <= Reset_i or s_logic_reset;
@@ -351,19 +332,21 @@ BEGIN
strobe_4x_logic_o <= s_strobe_generator(3);
s_clk40_out <= s_logic_clk_generator(3);
-
+
+ -- Try fbout out again....
-- buffer feedback clock
-------------------------------------
--- clkf_buf : BUFG
--- port map(
--- O => s_clkfbout_buf,
--- I => s_clkfbout);
-
- clkf_buf : BUFIO2FB
- port map (
- O => s_clkfbout_buf, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
- I => s_clk640_internal -- 1-bit input: Feedback clock input (connect to input port)
- );
+ --clkf_buf : BUFG
+ --port map(
+ -- O => s_clkfbout_buf,
+ -- I => s_clkfbout);
+ ---
+
+-- clkf_buf : BUFIO2FB
+-- port map (
+-- O => s_clkfbout_buf, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
+-- I => s_clk640_internal -- 1-bit input: Feedback clock input (connect to input port)
+-- );
-- buffer 160MHz (4x) clock
--------------------------------------
diff --git a/firmware/hdl/common/triggerInputs_rtl.vhd b/firmware/hdl/common/triggerInputs_rtl.vhd
index 3467822a..ec95d8a5 100644
--- a/firmware/hdl/common/triggerInputs_rtl.vhd
+++ b/firmware/hdl/common/triggerInputs_rtl.vhd
@@ -21,7 +21,43 @@
--! @version v0.1
--
--! @details
+--! IPBus address 0 = control and status
+--! bit0 = reset serdes
+--! bit1 = reset counter
+--! bit2 = calibrate IDELAYs
+--! bit3 = not connected
--!
+--! bit4 = Thresh discr IDelay(0) status prompt
+--! bit5 = Thresh discr IDelay(0) status delayed
+--! bit6 = Thresh discr IDelay(1) status prompt
+--! bit7 = Thresh discr IDelay(1) status delayed
+--! bit8 = Thresh discr IDelay(2) status prompt
+--! bit9 = Thresh discr IDelay(2) status delayed
+--! bit10= Thresh discr IDelay(3) status prompt
+--! bit11= Thresh discr IDelay(3) status delayed
+--!
+--! bit12= CFD discr IDelay(0) status prompt
+--! bit13= CFD discr IDelay(0) status delayed
+--! bit14= CFD discr IDelay(1) status prompt
+--! bit15= CFD discr IDelay(1) status delayed
+--! bit16= CFD discr IDelay(2) status prompt
+--! bit17= CFD discr IDelay(2) status delayed
+--! bit18= CFD discr IDelay(3) status prompt
+--! bit19= CFD discr IDelay(3) status delayed
+--!
+--! bit20= Thresh deserialized data monitor(0)
+--! bit21= Thresh deserialized data monitor(1)
+--! bit22= Thresh deserialized data monitor(2)
+--! bit23= Thresh deserialized data monitor(3)
+--! bit24= CFD deserialized data monitor(0)
+--! bit25= CFD deserialized data monitor(1)
+--! bit26= CFD deserialized data monitor(2)
+--! bit27= CFD deserialized data monitor(3)
+--!
+--! IPBus address 1 = edge rising(0) counter
+--! IPBus address 2 = edge rising(1) counter
+--! IPBus address 3 = edge rising(2) counter
+--! IPBus address 4 = edge rising(3) counter
--!
--! <b>Dependencies:</b>\n
--!
@@ -85,7 +121,7 @@ END ENTITY triggerInputs ;
--
ARCHITECTURE rtl OF triggerInputs IS
- signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and calibrate IODELAY
+ signal s_rst_iserdes : std_logic := '0'; --! Reset ISERDES and IDELAY
signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0); --! inputs from comparator
@@ -95,8 +131,6 @@ ARCHITECTURE rtl OF triggerInputs IS
type t_deserialized_trigger_data_array_l is array ( natural range <> ) of std_logic_vector(8 downto 0); --
signal s_deserialized_threshold_data_l , s_deserialized_cfd_data_l : t_deserialized_trigger_data_array_l(g_NUM_INPUTS-1 downto 0);
- signal s_serdes_reset : std_logic := '0'; --! Take high to reset serdes and initiate IODELAY calibration
-
signal s_cfd_trigger_times : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
signal s_CFD_rising_edge : std_logic_vector(g_NUM_INPUTS-1 downto 0);
@@ -116,8 +150,8 @@ ARCHITECTURE rtl OF triggerInputs IS
constant c_N_STAT : positive := g_NUM_INPUTS+1 ;
signal s_status_to_ipbus , s_sync_status_to_ipbus: ipb_reg_v(c_N_STAT-1 downto 0);
signal s_control_from_ipbus , s_sync_control_from_ipbus: ipb_reg_v(c_N_CTRL-1 downto 0);
- signal s_reset_serdes_reg : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
- signal s_counter_reset: std_logic := '0';
+-- signal s_reset_reg , s_status_reg: std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others => '0');
+ signal s_counter_reset, s_calibrate_idelay: std_logic := '0';
BEGIN
@@ -135,32 +169,43 @@ BEGIN
reset => ipbus_reset_i ,
ipbus_in => ipbus_i,
ipbus_out => ipbus_o,
- d=> s_status_to_ipbus,
+ d=> s_sync_status_to_ipbus,
q=> s_control_from_ipbus,
stb => open
);
+ -- sync data from I/O logic to IPBus
sync_registers: entity work.synchronizeRegisters
generic map (
g_NUM_REGISTERS => c_N_STAT )
port map (
clk_input_i => clk_4x_logic,
- data_i => s_status_to_ipbus,
+ data_i => s_status_to_ipbus,
data_o => s_sync_status_to_ipbus,
clk_output_i => ipbus_clk_i);
+ -- sync data from I/O logic to IPBus
+ sync_ipbus: entity work.synchronizeRegisters
+ generic map (
+ g_NUM_REGISTERS => c_N_CTRL )
+ port map (
+ clk_input_i => ipbus_clk_i,
+ data_i => s_control_from_ipbus,
+ data_o => s_sync_control_from_ipbus,
+ clk_output_i => clk_4x_logic);
+
-- Map the control registers...
-- Register that controls IODELAY and ISERDES reset is at address 0
- -- temporarily disable control signals ( need to register them to aid timing
- -- closure... )
- --s_reset_serdes_reg <= s_control_from_ipbus(0);
- --s_rst_iserdes <= s_reset_serdes_reg(0);
- --s_counter_reset <= s_reset_serdes_reg(1);
- --s_reset_serdes_reg <= '0';
- s_rst_iserdes <= '0';
- s_counter_reset <= '0';
+ s_rst_iserdes <= s_sync_control_from_ipbus(0)(0);
+ s_counter_reset <= s_sync_control_from_ipbus(0)(1);
+ s_calibrate_idelay <= s_sync_control_from_ipbus(0)(2);
+ s_status_to_ipbus(0)(0) <= s_rst_iserdes;
+ s_status_to_ipbus(0)(1) <= s_counter_reset;
+ s_status_to_ipbus(0)(2) <= s_calibrate_idelay;
+ -- Connect up unused lines in status regiser to 0.
+ s_status_to_ipbus(0)(3) <= '0';
+ s_status_to_ipbus(0)(g_IPBUS_WIDTH-1 downto 28) <= (others => '0');
-
-----------------------------------------------------------------------------
-- Connect up trigger inputs to deserializers and a LUT to determine
-- arrival time
@@ -181,12 +226,14 @@ BEGIN
thresholdDeserializer: entity work.dualSERDES_1to4
port map (
- serdes_reset_i => s_rst_iserdes,
+ reset_i => s_rst_iserdes,
+ calibrate_i => s_calibrate_idelay,
data_i => s_threshold_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
- data_o => s_deserialized_threshold_data(triggerInput)
+ data_o => s_deserialized_threshold_data(triggerInput),
+ status_o => s_status_to_ipbus(0)(5+(2*triggerInput) downto 4+(2*triggerInput))
);
s_deserialized_threshold_data_l(triggerInput) <= s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput);
@@ -227,12 +274,14 @@ BEGIN
CFDDeserializer: entity work.dualSERDES_1to4
port map (
- serdes_reset_i => s_rst_iserdes,
+ reset_i => s_rst_iserdes,
+ calibrate_i => s_calibrate_idelay,
data_i => s_CFD_discr_input(triggerInput),
fastClk_i => clk_16x_logic_i,
fabricClk_i => clk_4x_logic,
strobe_i => strobe_16x_logic_i,
- data_o => s_deserialized_CFD_data(triggerInput)
+ data_o => s_deserialized_CFD_data(triggerInput),
+ status_o => s_status_to_ipbus(0)(13+(2*triggerInput) downto 12+(2*triggerInput))
);
s_deserialized_CFD_data_l(triggerInput) <= s_deserialized_CFD_data(triggerInput) & s_CFD_previous_late_bit(triggerInput);
@@ -253,6 +302,13 @@ BEGIN
if rising_edge(clk_4x_logic) then
s_threshold_previous_late_bit(triggerInput) <= s_deserialized_threshold_data(triggerInput)(7);
s_CFD_previous_late_bit(triggerInput) <= s_deserialized_CFD_data(triggerInput)(7);
+
+ -- Monitor output of serdes - just look at one per serdes
+ -- Don't care about latency so put a couple of registers in to aid
+ -- timing closure.
+ s_status_to_ipbus(0)(20+triggerInput) <= s_threshold_previous_late_bit(triggerInput);
+ s_status_to_ipbus(0)(24+triggerInput) <= s_CFD_previous_late_bit(triggerInput);
+
end if ;
end process;
@@ -271,7 +327,10 @@ BEGIN
trigger_debug_o( (g_NUM_INPUTS-1) downto 0) <= s_threshold_discr_input;
--trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_CFD_discr_input;
- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+ --trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
+ --! Monitor output of deserializer
+ -- trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_status_to_ipbus(0)(23 downto 20);
+ trigger_debug_o( ((2*g_NUM_INPUTS)-1) downto g_NUM_INPUTS) <= s_edge_rising;
END ARCHITECTURE rtl;
diff --git a/firmware/hdl/test/clock_divider_s6.v b/firmware/hdl/test/clock_divider_s6.v
index e5a3ef9a..3e29a336 100755
--- a/firmware/hdl/test/clock_divider_s6.v
+++ b/firmware/hdl/test/clock_divider_s6.v
@@ -9,7 +9,8 @@ module clock_divider_s6(
wire [6:0] q;
reg [5:0] qr = 0;
reg [2:0] ctr = 0;
-
+ //wire unconnected; // horrid hack
+
assign q[0] = 1'b1;
generate
diff --git a/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd b/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
index 5c52e8c3..6c3004bd 100644
--- a/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+++ b/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
@@ -16,9 +16,12 @@ PACKAGE fmcTLU IS
constant c_NUM_TIME_BITS : natural := 5;
constant c_NUM_TRIG_INPUTS : natural := 4;
constant c_EVENT_DATA_WIDTH : natural := 32;
+ constant c_DATA_WIDTH : natural := 32;
--subtype t_triggerTime is std_logic_vector(c_NUM_TIME_BITS-1 downto 0);
--type t_triggerTimeArray is array(natural range <>) of t_triggerTime;
type t_triggerTimeArray is array(natural range <>) of std_logic_vector(c_NUM_TIME_BITS-1 downto 0) ;
+
+ type t_registerArray is array(natural range <>) of std_logic_vector(c_DATA_WIDTH-1 downto 0) ;
END fmcTLU;
diff --git a/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd b/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
index 05dc22a9..810a41cb 100644
--- a/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+++ b/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
@@ -47,8 +47,8 @@ ENTITY top_extphy IS
reset_or_clk_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_n_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0);
triggers_p_o : OUT std_logic_vector (g_NUM_DUTS-1 DOWNTO 0); --! Trigger lines to DUT
- extclk_n_b : INOUT std_logic;
- extclk_p_b : INOUT std_logic; --! either external clock in, or a clock being driven out
+ extclk_n_b : OUT std_logic;
+ extclk_p_b : OUT std_logic; --! either external clock in, or a clock being driven out
i2c_scl_b : INOUT std_logic;
i2c_sda_b : INOUT std_logic
);
@@ -287,8 +287,8 @@ ARCHITECTURE struct OF top_extphy IS
ipbus_o : OUT ipb_rbus ;
strobe_16x_logic_o : OUT std_logic ; -- strobes once every 4 cycles of clk_16x
strobe_4x_logic_o : OUT std_logic ; -- one pulse every 4 cycles of clk_4x
- extclk_p_b : INOUT std_logic ; -- either external clock in, or a clock being driven out
- extclk_n_b : INOUT std_logic ;
+ extclk_p_b : OUT std_logic ; -- either external clock in, or a clock being driven out
+ extclk_n_b : OUT std_logic ;
clk_logic_o : OUT std_logic ;
logic_clocks_locked_o : OUT std_logic ;
logic_reset_o : OUT std_logic -- Goes high TO reset counters etc. Sync with clk_4x_logic
diff --git a/firmware/scripts/FmcTluI2c.py b/firmware/scripts/FmcTluI2c.py
index 47f706f7..64f7ff5b 100644
--- a/firmware/scripts/FmcTluI2c.py
+++ b/firmware/scripts/FmcTluI2c.py
@@ -88,7 +88,7 @@ class FmcTluI2c:
#################
### set DAC value
#################
- def set_dac(self,channel,value):
+ def set_dac(self,channel,value , vrefOn = 0 , i2cSlaveAddrDac = 0x1F):
if channel<0 or channel>7:
print "set_dac ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
@@ -96,10 +96,17 @@ class FmcTluI2c:
print "set_dac ERROR: value",value,"not in range 0-0xFFFF"
return -1
# AD5665R chip with A0,A1 tied to ground
- i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
+ #i2cSlaveAddrDac = 0x1F # seven bit address, binary 00011111
+ print "I2C address of DAC = " , hex(i2cSlaveAddrDac)
dac = RawI2cAccess(self.i2cBusProps, i2cSlaveAddrDac)
- # enter vref-on mode:
- dac.write([0x38,0x00,0x01])
+ # if we want to enable internal voltage reference:
+ if vrefOn:
+ # enter vref-on mode:
+ print "Turning internal reference ON"
+ dac.write([0x38,0x00,0x01])
+ else:
+ print "Turning internal reference OFF"
+ dac.write([0x38,0x00,0x00])
# now set the actual value
sequence=[( 0x18 + ( channel &0x7 ) ) , (value/256)&0xff , value&0xff]
print sequence
@@ -110,13 +117,20 @@ class FmcTluI2c:
##################################################
### convert required threshold voltage to DAC code
##################################################
- # WARNING THIS CODE IS BUGGY.
- def convert_voltage_to_dac(self,desiredVoltage):
- Vref = 2.50
+ def convert_voltage_to_dac(self,desiredVoltage, Vref=1.300):
Vdaq = ( desiredVoltage + Vref ) / 2
dacCode = 0xFFFF * Vdaq / Vref
return int(dacCode)
+ ##################################################
+ ### calculate the DAC code required and set DAC
+ ##################################################
+ def set_threshold_voltage(self, channel , voltage ):
+ dacCode = self.convert_voltage_to_dac(voltage)
+ print " requested voltage, calculated DAC code = " , voltage , dacCode
+ self.set_dac(channel , dacCode)
+
+
diff --git a/firmware/scripts/aida_mini_tlu_addr_map.txt b/firmware/scripts/aida_mini_tlu_addr_map.txt
index 3742faed..76d98a2a 100644
--- a/firmware/scripts/aida_mini_tlu_addr_map.txt
+++ b/firmware/scripts/aida_mini_tlu_addr_map.txt
@@ -4,7 +4,11 @@ FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
*
* trigger inputs = 0x040
-SerdesRst 0x00000040 0xffffffff 0 1
+SerdesRst 0x00000040 0xffffffff 1 1
+ThrCount0 0x00000041 0xffffffff 1 0
+ThrCount1 0x00000042 0xffffffff 1 0
+ThrCount2 0x00000043 0xffffffff 1 0
+ThrCount3 0x00000044 0xffffffff 1 0
*
* trigger logic = 0x060
PostVetoTriggers 0x00000060 0xffffffff 1 0
diff --git a/firmware/scripts/setup.sh b/firmware/scripts/setup.sh
deleted file mode 100755
index 32a436c3..00000000
--- a/firmware/scripts/setup.sh
+++ /dev/null
@@ -1,88 +0,0 @@
-#!/bin/sh
-#
-# Script to build firmware for FMC-based AIDA mini-TLU
-#
-# Create a working directory and execute this script....
-
-export FW_WORKSPACE=`pwd`
-echo "Current directory = " $FW_WORKSPACE
-export BOARD_TYPE=sp601
-export ISE_VER=ise14
-
-# Check out FMC-MTLU code
-TLUDir=`pwd`/fmc-mtlu
-if [ ! -d "$TLUDir" ]; then
- echo "Checking out CBC code"
- mkdir fmc-mtlu
- pushd fmc-mtlu
- svn co http://svn.ohwr.org/fmc-mtlu/trunk/firmware
- popd
- echo "Checked out FMC-MTLU code"
-fi
-
-# Check out IPBus code
-IPBusDir=`pwd`/IPBus2
-if [ ! -d "$IPBusDir" ]; then
- mkdir $IPBusDir
- pushd $IPBusDir
- svn co http://svn.cern.ch/guest/cactus/tags/ipbus_2_0_v1/firmware
- echo "Checked out IPBus2 code"
- popd
-fi
-
-# Check out directory for external cores ( e.g. I2C)
-if [ ! -d "external" ]; then
- echo "Checking out I2C code"
- svn co http://cactus.hepforge.org/svn/tags/firmware_pre_131_RAL/firmware/external
-fi
-
-# Create a directory contain the build products.
-WorkDir=workspace
-if [ ! -d "$WorkDir" ]; then
- mkdir workspace
- mkdir workspace/ipcore_dir
- echo "Made workspace"
-fi
-
-export REPOS_BUILD_DIR=`pwd`/workspace
-
-pushd workspace
-
-# Create soft links to ipbus, fmc-mtlu code , i2c code
-if [ ! -e "ipbus" ]; then
- ln -s $IPBusDir ipbus
-fi
-
-if [ ! -e "fmc-mtlu" ]; then
- ln -s ../fmc-mtlu .
-fi
-
-if [ ! -e "external" ]; then
- ln -s ../external .
-fi
-
-
-if [ ! -e "file_list" ]; then
- ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
-fi
-
-if [ ! -e "ipbus" ]; then
- ln -s ../$IPBusDir/firmware/config/$ISE_VER/$BOARD_TYPE/file_list .
-fi
-
-
-pushd ipcore_dir
-if [ ! -e "coregen.cgp" ]; then
- ln -s $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/coregen.cgp .
-fi
-popd
-
-#export REPOS_FW_DIR=$IPBusDir
-export REPOS_FW_DIR=ipbus
-
-echo "IPBus directory = " $IPBusDir
-echo "FMC-MTLU directry = " $TLUDir
-
-xtclsh $TLUDir/firmware/config/$ISE_VER/$BOARD_TYPE/setup_project.tcl
-
-echo "Finished setting up ISE project. Open in $ISE_VER and build bit-stream"
diff --git a/firmware/scripts/test_aida_tlu_thresholds.py b/firmware/scripts/test_aida_tlu_thresholds.py
index 4a38d0b0..db240e04 100644
--- a/firmware/scripts/test_aida_tlu_thresholds.py
+++ b/firmware/scripts/test_aida_tlu_thresholds.py
@@ -14,13 +14,22 @@ boardi2c = FmcTluI2c(board)
boardFirmware = board.read("FirmwareId")
print "Firmware version = " , hex(boardFirmware)
-#scanResults = boardi2c.i2c_scan()
-#print scanResults
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
-# Set thresholds at about -0.1V ( with 1MOhm f/back resistors )
-print "Setting Vthreshold to about -0.1V"
-boardi2c.set_dac(7,0x4100)
+#dacValue = 0x4100
+dacValue = 0xFFFF
+print "Setting Vthreshold for all DACs. Code = ", dacValue
+boardi2c.set_dac(7,dacValue)
+
+dacValue = 0x6000
+print "Setting Vthreshold for DAC 0. Code = ", dacValue
+boardi2c.set_dac(0,dacValue)
+
+# set DACs to -5mV
+#boardi2c.set_threshold_voltage(7, -0.005)
diff --git a/firmware/scripts/test_aida_tlu_trig_counter.py b/firmware/scripts/test_aida_tlu_trig_counter.py
new file mode 100644
index 00000000..8cbd3244
--- /dev/null
+++ b/firmware/scripts/test_aida_tlu_trig_counter.py
@@ -0,0 +1,93 @@
+from PyChipsUser import *
+from FmcTluI2c import *
+
+import sys
+import time
+
+boardIpAddr = "192.168.200.16"
+boardPortNum = 50001
+
+addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
+
+board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
+
+# Check the bus for I2C devices
+boardi2c = FmcTluI2c(board)
+
+boardFirmware = board.read("FirmwareId")
+print "Firmware version = " , hex(boardFirmware)
+
+print "Scanning I2C bus:"
+scanResults = boardi2c.i2c_scan()
+print scanResults
+
+boardId = boardi2c.get_serial_number()
+print "FMC-TLU serial number = " , boardId
+
+resetClocks = 0
+resetSerdes = 1
+
+# set DACs to -200mV
+print "Setting all threshold DAC to -200mV "
+boardi2c.set_threshold_voltage(7, -0.200)
+
+clockStatus = board.read("LogicClocksCSR")
+print "Clock status = " , hex(clockStatus)
+
+if resetClocks:
+ print "Resetting clocks"
+ board.write("LogicRst", 1 )
+
+ clockStatus = board.read("LogicClocksCSR")
+ print "Clock status after reset = " , hex(clockStatus)
+
+#print "Setting PLL input to ext. clk"
+#board.write("LogicRst", 0 )
+#clockStatus = board.read("LogicClocksCSR")
+#print "Clock status = " , hex(clockStatus)
+
+
+inputStatus = board.read("SerdesRst")
+print "Input status = " , hex(inputStatus)
+
+if resetSerdes:
+ board.write("SerdesRst", 0x00000003 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status during reset = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000000 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status after reset = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000004 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status during calibration = " , hex(inputStatus)
+
+ board.write("SerdesRst", 0x00000000 )
+ inputStatus = board.read("SerdesRst")
+ print "Input status after calibration = " , hex(inputStatus)
+
+
+# Look at status of input IODELAYs
+numLoops = 5
+
+for iLoop in range(0,numLoops):
+
+ inputStatus = board.read("SerdesRst")
+ print "Input status = " , hex(inputStatus)
+
+ count0 = board.read("ThrCount0")
+ print " Count 0 = " , count0
+
+ count1 = board.read("ThrCount1")
+ print " Count 1 = " , count1
+
+ count2 = board.read("ThrCount2")
+ print " Count 2 = " , count2
+
+ count3 = board.read("ThrCount3")
+ print " Count 3 = " , count3
+
+ time.sleep(1.0)
+
+
diff --git a/firmware/simulation/questa/fmctlu_v0_1_testbench.fdo b/firmware/simulation/questa/fmctlu_v0_1_testbench.fdo
new file mode 100644
index 00000000..415ecc20
--- /dev/null
+++ b/firmware/simulation/questa/fmctlu_v0_1_testbench.fdo
@@ -0,0 +1,115 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench.fdo
+## Created on: Fri Feb 28 10:49:46 GMT 2014
+##
+## Auto generated by Project Navigator for Behavioral Simulation
+##
+## ---------------------DO NOT EDIT THIS FILE-------------------------
+## You may want to add additional commands to control the simulation
+## in the user specific do file (<module>.udo) which is automatically
+## generated in the project directory and will not be removed on
+## subsequent simulation flows run from Project Navigator.
+## ---------------------DO NOT EDIT THIS FILE-------------------------
+##
+######################################################################
+#
+# Create work library
+#
+vlib work
+#
+# Compile sources
+#
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_if.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd"
+vcom -explicit -93 "ipbus/firmware/example_designs/hdl/clock_div.vhd"
+vcom -explicit -93 "ipcore_dir/tri_mode_eth_mac_v5_4.vhd"
+vcom -explicit -93 "ipcore_dir/mac_fifo_axi4.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/trans_arb.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/transactor.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/stretcher.vhd"
+vcom -explicit -93 "ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_registers.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_byte_ctrl.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_bit_ctrl.vhd"
+vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_reg_types.vhd"
+vlog "../fmc-mtlu/firmware/hdl/test/clock_divider_s6.v"
+vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd"
+vcom -explicit -93 "ipcore_dir/tlu_event_fifo.vhd"
+vcom -explicit -93 "ipcore_dir/internalTriggerGenerator.vhd"
+vcom -explicit -93 "ipcore_dir/FIFO.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd"
+vcom -explicit -93 "ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd"
+vcom -explicit -93 "ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd"
+vcom -explicit -93 "external/opencores_i2c/i2c_master_top.vhd"
+vcom -explicit -93 "../IPBus2/firmware/slaves/hdl/ipbus_ctrlreg_v.vhd"
+vcom -explicit -93 "../fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd"
+vcom -explicit -93 "fmc-mtlu/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd"
+vlog "/automount/users/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//verilog/src/glbl.v"
+#
+# Call vsim to invoke simulator
+#
+vsim -voptargs="+acc" -t 1ps -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work work.fmctlu_v0_1_testbench glbl
+#
+# Source the wave do file
+#
+do {fmctlu_v0_1_testbench_wave.fdo}
+#
+# Set the window types
+#
+view wave
+view structure
+view signals
+#
+# Source the user do file
+#
+do {fmctlu_v0_1_testbench.udo}
+#
+# Run simulation for this time
+#
+run 1000ns
+#
+# End
+#
diff --git a/firmware/simulation/questa/fmctlu_v0_1_testbench.udo b/firmware/simulation/questa/fmctlu_v0_1_testbench.udo
new file mode 100644
index 00000000..82867cb7
--- /dev/null
+++ b/firmware/simulation/questa/fmctlu_v0_1_testbench.udo
@@ -0,0 +1,10 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench.udo
+## Created on: Wed Feb 26 17:46:18 GMT 2014
+##
+## Auto generated by Project Navigator for Post-Behavioral Simulation
+##
+## You may want to edit this file to control your simulation.
+##
+######################################################################
diff --git a/firmware/simulation/questa/fmctlu_v0_1_testbench_wave.fdo b/firmware/simulation/questa/fmctlu_v0_1_testbench_wave.fdo
new file mode 100644
index 00000000..26b48530
--- /dev/null
+++ b/firmware/simulation/questa/fmctlu_v0_1_testbench_wave.fdo
@@ -0,0 +1,12 @@
+######################################################################
+##
+## Filename: fmctlu_v0_1_testbench_wave.fdo
+## Created on: Wed Feb 26 17:46:21 GMT 2014
+##
+## Auto generated by Project Navigator for Post-Behavioral Simulation
+##
+## You may want to edit this file to control your simulation windows.
+##
+######################################################################
+add wave *
+# add wave /glbl/GSR
diff --git a/firmware/simulation/questa/modelsim.ini b/firmware/simulation/questa/modelsim.ini
new file mode 100644
index 00000000..b025bbda
--- /dev/null
+++ b/firmware/simulation/questa/modelsim.ini
@@ -0,0 +1,1868 @@
+; Copyright 1991-2013 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+
+unimacro = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unimacro
+simprim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/simprim
+unisim = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/unisim
+xilinxcorelib = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/xilinxcorelib
+unimacro_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unimacro_ver
+simprims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/simprims_ver
+unisims_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/unisims_ver
+xilinxcorelib_ver = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/xilinxcorelib_ver
+secureip = /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/secureip
+
+[DefineOptionset]
+; Define optionset entries for the various compilers, vmake, and vsim.
+; These option sets can be used with the "-optionset <optionsetname>" syntax.
+; i.e.
+; vlog -optionset COMPILEDEBUG top.sv
+; vsim -optionset UVMDEBUG my_top
+;
+; Following are some useful examples.
+
+; define a vsim optionset for uvm debugging
+UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
+
+; define a vopt optionset for debugging
+VOPTDEBUG = +acc -debugdb
+
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; CoverExpandReductionPrefix = 1
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl", "sccts", "iddp" and "atpi".
+; SVExtensions = uslt,spsl,sccts
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 20000
+
+; Set XPROP assertion fail limit. Default is 5.
+; Any positive integer, -1 for infinity.
+; XpropAssertionLimit = 5
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog immediate assertion
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog immediate assertions that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is 0 (disabled). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase
+DefaultRadix = hexadecimal
+DefaultRadixFlags = showbase
+; Set to 1 for make the signal_force VHDL and Verilog functions use the
+; default radix when processing the force value. Prior to 10.2 signal_force
+; used the default radix, now it always uses symbolic unless value explicitly indicates base
+;SignalForceFunctionUseDefaultRadix = 0
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable changes in VHDL elaboration to allow for Variable Logging
+; This trades off simulation performance for the ability to log variables
+; efficiently. By default this is disable for maximum simulation performance
+; VhdlVariableLogging = 1
+
+; Make VHDL packages in PDUs have there own copy of a package instead
+; of sharing the package between PDUs. By default share packages
+; VhdlSeparatePduPackage = 0
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+; The default is UVMControl = struct
+
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+; Specify the WildcardFilter setting.
+; A space separated list of object types to be excluded when performing
+; wildcard matches with log, wave, etc commands. The default value for this variable is:
+; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
+; See "Using the WildcardFilter Preference Variable" in the documentation for
+; details on how to use this variable and for descriptions of the filter types.
+WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
+
+; Specify the WildcardSizeThreshold setting.
+; This integer setting specifies the size at which objects will be excluded when
+; performing wildcard matches with log, wave, etc commands. Objects of size equal
+; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
+; matches. The size is a simple calculation of number of bits or items in the object.
+; The default value is 8k (8192). Setting this value to 0 will disable the checking
+; of object size against this threshold and allow all objects of any size to be logged.
+WildcardSizeThreshold = 8192
+
+; Specify whether warning messages are output when objects are filtered out due to the
+; WildcardSizeThreshold. The default is 0 (no messages generated).
+WildcardSizeThresholdVerbose = 0
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file.
+; Value is the number of seconds between updated. After at least the
+; interval number of seconds, the wlf file is flushed, ensuring that the data
+; is correct when viewed from a separate live viewer. Setting to 0 means no
+; updating. Default is 10 seconds, which has a tiny performance impact
+; WLFUpdateInterval = 10
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 2000M per open WLF file on most
+; platforms; on Windows, the setting is 1000M to help avoid filling process memory.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Specify the size of objects that will trigger "large object" messages
+; at log/wave/list time. The size calculation of the object is the same as that
+; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
+; Setting LargeObjectSize to 0 will disable these messages.
+; LargeObjectSize = 500000
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Set SystemC thread stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). The stack size for sc_thread depends
+; on the amount of data on the sc_thread stack and the memory required
+; to succesfully execute the thread.
+; ScStackSize = 1 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStats = 1
+
+; Print "simstats" result in Tcl list form
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of run
+; 3 == print at end of run and end of simulation
+; default == 0
+; PrintSimStatsList = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCover = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; This option applies to condition and expression coverage UDP tables. It
+; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
+; If this option is used and a match occurs in more than one row in the UDP table,
+; none of the counts for all matching rows is incremented. By default, counts are
+; incremented for all matching rows.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Turn off automatic inclusion of VHDL records in toggle coverage.
+; Default is to include them.
+; ToggleVHDLRecords = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; FecCountLimit = 1
+
+; Limit the counts that are tracked for UDP Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; UdpCountLimit = 1
+
+; Control toggle coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
+; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; ToggleDeglitchPeriod = 10.0ps
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
+; and report. This variable sets the default value of type_option.merge_instances.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroupMergeInstancesDefault = 0
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Error message severity for suppressible errors that are detected in a
+; solve/before constraint.
+; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveBeforeErrorSeverity = 3
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable basic debug (with no
+; performance penalty). Set to 2 for enhanced debug (will result in slower
+; runtime performance).
+; SolveFailDebug = 0
+
+; Upon encountering a randomize() failure, generate a simplified testcase that
+; will reproduce the failure. Optionally output the testcase to a file.
+; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
+; is enabled (see above).
+; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
+; command line switch.
+; The default is OFF (do not generate a testcase). To enable testcase
+; generation, uncomment this variable. To redirect testcase generation to a
+; file, specify the name of the output file.
+; SolveFailTestcase =
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 2000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 2000000
+
+; Specify the maximum number of operations that the ACT solver may perform
+; before abandoning an attempt to solve a particular constraint scenario. The
+; value is specified in 1000000s of operations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveACTMaxOps = 10000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMax[Tests|Ops] threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Specify the memory threshold for the System Verilog garbage collector.
+; The value is the number of megabytes of class objects that must accumulate
+; before the garbage collector is run.
+; The GCThreshold setting is used when class debug mode is disabled to allow
+; less frequent garbage collection and better simulation performance.
+; The GCThresholdClassDebug setting is used when class debug mode is enabled
+; to allow for more frequent garbage collection.
+; GCThreshold = 100
+; GCThresholdClassDebug = 5
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior. Valid extensions are "feci",
+; "pae", "uslt", "spsl" and "sccts".
+; SVExtensions = uslt,spsl,sccts
+
+; Controls the formatting of '%p' and '%P' conversion specification, used in $display
+; and similar system tasks.
+; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
+; The 'I' flag when present causes relevant data types to be expanded and indented into
+; a more readable format.
+; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
+; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
+; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
+; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
+; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
+; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
+; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
+; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
+; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
+; 7. Items 1-6 above can be combined as a comma separated list.
+; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5)
+; SVPrettyPrintFlags=I4S
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
+
+[utils]
+; Default Library Type
+; Set to determine the default type for a library created with "vlib"
+; 0 - legacy library using subdirectories for design units
+; 1 - archive library (deprecated)
+; 2 - flat library
+; DefaultLibType = 2
+
+; Archive Library Compact Value
+; Sets compaction trigger for archive libraries. The value is the percentage
+; of free space in the archive.
+; ArchiveLibCompact = 0.5
+
+; Flat Library Page Size
+; Set the size in bytes for flat library file pages. Very large libraries
+; may benefit from a larger value, at the expense of disk space.
+; FlatLibPageSize = 8192
+
+; Flat Library Page Cleanup Percentage
+; Set the percentage of total pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeleteThreshold.
+; FlatLibPageDeletePercentage = 50
+
+; Flat Library Page Cleanup Threshold
+; Set the number of pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeletePercentage.
+; FlatLibPageDeleteThreshold = 1000
+
diff --git a/firmware/simulation/scripts/addfiles_sim.tcl b/firmware/simulation/scripts/addfiles_sim.tcl
new file mode 100644
index 00000000..128b3fbf
--- /dev/null
+++ b/firmware/simulation/scripts/addfiles_sim.tcl
@@ -0,0 +1,38 @@
+# Horrible hacky TCL script to build ISE project from hierarchy of source lists
+
+proc dofile {f} {
+ set fp [open $f r]
+ set files [read $fp]
+ close $fp
+ foreach f_line [split $files "\n"] {
+ if {$f_line == "" || [string index $f_line 0] == "#"} {
+ continue
+ }
+ set l [split $f_line]
+ set cmd [lindex $l 0]
+ set arg1 [lindex $l 1]
+ set arg2 [lindex $l 2]
+ set f_list [glob $::env(REPOS_FW_DIR)/$arg1]
+ foreach f_loc $f_list {
+ set f_loc_s [exec basename $f_loc]
+ if {$cmd == "hdl"} {
+ addfile $f_loc $arg2
+ } elseif {$cmd == "core"} {
+ addcore $f_loc $arg2
+ } elseif {$cmd == "include"} {
+ dofile $f_loc
+ }
+ }
+ }
+}
+
+proc addfile {f lib} {
+ project addfile $f
+}
+
+proc addcore {f lib} {
+ addfile [file rootname $f].vhd $lib
+}
+
+dofile $::env(REPOS_BUILD_DIR)/file_list
+
diff --git a/firmware/simulation/scripts/file_list b/firmware/simulation/scripts/file_list
new file mode 100644
index 00000000..04242c09
--- /dev/null
+++ b/firmware/simulation/scripts/file_list
@@ -0,0 +1,67 @@
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_trans_decl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_package.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_tx_mux.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_txtransactor_if_simple.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_status_buffer.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxtransactor_if_simple.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_shim.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rxram_mux.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_rarp_block.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_packet_parser.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_ipaddr_block.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram_rx.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_dualportram.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_do_rx_reset.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_clock_crossing_if.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_byte_sum.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_status.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_resend.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_ping.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_payload.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_build_arp.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_buffer_selector.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_sm.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_if.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor_cfg.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/example_designs/hdl/clock_div.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/tri_mode_eth_mac_v5_4.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/mac_fifo_axi4.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/udp_if_flat.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/trans_arb.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/transactor.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/stretcher.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_registers.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_byte_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_bit_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_w.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/syncreg_r.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_reg_types.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/tlu_event_fifo.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/internalTriggerGenerator.vhd
+hdl $FW_WORKSPACE/workspace/ipcore_dir/FIFO.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_fabric.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/fmcTLU_pkg_body.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/ipbus_ver.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
+hdl $FW_WORKSPACE/workspace/external/opencores_i2c/i2c_master_top.vhd
+hdl $FW_WORKSPACE/workspace/ipbus/firmware/slaves/hdl/ipbus_syncreg_v.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd
+hdl $FW_WORKSPACE/workspace/fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
diff --git a/firmware/simulation/scripts/setup.sh b/firmware/simulation/scripts/setup.sh
new file mode 100644
index 00000000..391f528e
--- /dev/null
+++ b/firmware/simulation/scripts/setup.sh
@@ -0,0 +1,12 @@
+#!/bin/sh
+export MODELSIM_ROOT="/software/CAD/Mentor/2013_2014/Questa/HDS_2012.2b/questasim/"
+export ISE_VHDL_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/vhdl/questasim/10.2c_5/lin64/"
+export ISE_VLOG_MTI="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/verilog/questasim/10.2c_5/lin64/"
+
+vsim -c -do $REPOS_FW_DIR/ipbus/firmware/sim/scripts/setup_project.tcl
+cp -r $REPOS_FW_DIR/ipbus/firmware/ethernet/sim/modelsim_fli ./
+cd modelsim_fli
+./mac_fli_compile.sh
+cd ..
+ln -s modelsim_fli/mac_fli.so
+
diff --git a/firmware/simulation/scripts/setup_project.tcl b/firmware/simulation/scripts/setup_project.tcl
new file mode 100644
index 00000000..dd555fa2
--- /dev/null
+++ b/firmware/simulation/scripts/setup_project.tcl
@@ -0,0 +1,24 @@
+# Creates a new Questa project for ipbus demo
+#
+# You will want to amend the path to compiled Xilinx libraries to suit
+# your system.
+#
+# Dave Newbold, April 2011
+#
+# $Id$
+
+set xlib_vhdl $::env(ISE_VHDL_MTI)
+set xlib_vlog $::env(ISE_VLOG_MTI)
+
+project new ./ ipbus_sim_demo
+vmap unisim $xlib_vhdl/unisim
+vmap unimacro $xlib_vhdl/unimacro
+vmap secureip $xlib_vlog/secureip
+vmap xilinxcorelib $xlib_vhdl/xilinxcorelib
+
+source $::env(REPOS_FW_DIR)/ipbus/firmware/sim/scripts/addfiles_sim.tcl
+
+project calculateorder
+project close
+quit
+
diff --git a/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd b/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
new file mode 100644
index 00000000..6c6b70a7
--- /dev/null
+++ b/firmware/simulation_src/fmc-tlu_v0-1_test-bench.vhd
@@ -0,0 +1,182 @@
+--=============================================================================
+--! @file fmc-tlu_v0-1_test-bench.vhd
+--=============================================================================
+
+--! @brief Test-bench for FMC format mini-TLU for AIDA
+--
+--! @details
+--
+--! @author David Cussans, 31/07/12
+--! @date 11:49:20 02/21/2014
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY fmctlu_v0_1_testbench IS
+END fmctlu_v0_1_testbench;
+
+ARCHITECTURE behavior OF fmctlu_v0_1_testbench IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT top_extphy
+ PORT(
+ busy_n_i : IN std_logic_vector(2 downto 0);
+ busy_p_i : IN std_logic_vector(2 downto 0);
+ cfd_discr_n_i : IN std_logic_vector(3 downto 0);
+ cfd_discr_p_i : IN std_logic_vector(3 downto 0);
+ dip_switch_i : IN std_logic_vector(3 downto 0);
+ dut_clk_n_i : IN std_logic_vector(2 downto 0);
+ dut_clk_p_i : IN std_logic_vector(2 downto 0);
+ gmii_rx_clk_i : IN std_logic;
+ gmii_rx_dv_i : IN std_logic;
+ gmii_rx_er_i : IN std_logic;
+ gmii_rxd_i : IN std_logic_vector(7 downto 0);
+ sysclk_n_i : IN std_logic;
+ sysclk_p_i : IN std_logic;
+ threshold_discr_n_i : IN std_logic_vector(3 downto 0);
+ threshold_discr_p_i : IN std_logic_vector(3 downto 0);
+ gmii_gtx_clk_o : OUT std_logic;
+ gmii_tx_en_o : OUT std_logic;
+ gmii_tx_er_o : OUT std_logic;
+ gmii_txd_o : OUT std_logic_vector(7 downto 0);
+ gpio_hdr : OUT std_logic_vector(7 downto 0);
+ leds_o : OUT std_logic_vector(3 downto 0);
+ phy_rstb_o : OUT std_logic;
+ reset_or_clk_n_o : OUT std_logic_vector(2 downto 0);
+ reset_or_clk_p_o : OUT std_logic_vector(2 downto 0);
+ triggers_n_o : OUT std_logic_vector(2 downto 0);
+ triggers_p_o : OUT std_logic_vector(2 downto 0);
+ extclk_n_b : INOUT std_logic;
+ extclk_p_b : INOUT std_logic;
+ i2c_scl_b : INOUT std_logic;
+ i2c_sda_b : INOUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal busy_n_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal busy_p_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal cfd_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal cfd_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal dip_switch_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal dut_clk_n_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal dut_clk_p_i : std_logic_vector(2 downto 0) := (others => '0');
+ signal gmii_rx_clk_i : std_logic := '0';
+ signal gmii_rx_dv_i : std_logic := '0';
+ signal gmii_rx_er_i : std_logic := '0';
+ signal gmii_rxd_i : std_logic_vector(7 downto 0) := (others => '0');
+ signal sysclk_n_i : std_logic := '0';
+ signal sysclk_p_i : std_logic := '0';
+ signal threshold_discr_n_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal threshold_discr_p_i : std_logic_vector(3 downto 0) := (others => '0');
+ signal s_threshold_discr : std_logic_vector(3 downto 0) := (others => '0');
+
+ --BiDirs
+ signal extclk_n_b : std_logic;
+ signal extclk_p_b : std_logic;
+ signal i2c_scl_b : std_logic;
+ signal i2c_sda_b : std_logic;
+
+ --Outputs
+ signal gmii_gtx_clk_o : std_logic;
+ signal gmii_tx_en_o : std_logic;
+ signal gmii_tx_er_o : std_logic;
+ signal gmii_txd_o : std_logic_vector(7 downto 0);
+ signal gpio_hdr : std_logic_vector(7 downto 0);
+ signal leds_o : std_logic_vector(3 downto 0);
+ signal phy_rstb_o : std_logic;
+ signal reset_or_clk_n_o : std_logic_vector(2 downto 0);
+ signal reset_or_clk_p_o : std_logic_vector(2 downto 0);
+ signal triggers_n_o : std_logic_vector(2 downto 0);
+ signal triggers_p_o : std_logic_vector(2 downto 0);
+
+ signal sysclock : std_logic := '0';
+ constant sysclock_period : time := 5 ns;
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: top_extphy PORT MAP (
+ busy_n_i => busy_n_i,
+ busy_p_i => busy_p_i,
+ cfd_discr_n_i => cfd_discr_n_i,
+ cfd_discr_p_i => cfd_discr_p_i,
+ dip_switch_i => dip_switch_i,
+ dut_clk_n_i => dut_clk_n_i,
+ dut_clk_p_i => dut_clk_p_i,
+ gmii_rx_clk_i => gmii_rx_clk_i,
+ gmii_rx_dv_i => gmii_rx_dv_i,
+ gmii_rx_er_i => gmii_rx_er_i,
+ gmii_rxd_i => gmii_rxd_i,
+ sysclk_n_i => sysclk_n_i,
+ sysclk_p_i => sysclk_p_i,
+ threshold_discr_n_i => threshold_discr_n_i,
+ threshold_discr_p_i => threshold_discr_p_i,
+ gmii_gtx_clk_o => gmii_gtx_clk_o,
+ gmii_tx_en_o => gmii_tx_en_o,
+ gmii_tx_er_o => gmii_tx_er_o,
+ gmii_txd_o => gmii_txd_o,
+ gpio_hdr => gpio_hdr,
+ leds_o => leds_o,
+ phy_rstb_o => phy_rstb_o,
+ reset_or_clk_n_o => reset_or_clk_n_o,
+ reset_or_clk_p_o => reset_or_clk_p_o,
+ triggers_n_o => triggers_n_o,
+ triggers_p_o => triggers_p_o,
+ extclk_n_b => extclk_n_b,
+ extclk_p_b => extclk_p_b,
+ i2c_scl_b => i2c_scl_b,
+ i2c_sda_b => i2c_sda_b
+ );
+
+ -- Clock process definitions
+ sysclock_process :process
+ begin
+ sysclock <= '0';
+ wait for sysclock_period/2;
+ sysclock <= '1';
+ wait for sysclock_period/2;
+ end process;
+ sysclk_n_i <= not sysclock;
+ sysclk_p_i <= sysclock;
+
+
+ -- Generate pulses
+ cmp_pulseGen: entity work.pmtPulseGenerator
+ generic map (
+ g_NUM_CHANNELS => 4)
+ port map (
+ pulses_o => s_threshold_discr,
+ numPulses_i => 50,
+ averagePulseInterval_i => 10 us,
+ averagePulseWidth_i => 10 ns,
+ pulseJitter_i => 2 ns,
+ sysclock_i => sysclock,
+ simulationDone_o => open);
+
+ threshold_discr_p_i <= s_threshold_discr;
+ threshold_discr_n_i <= not s_threshold_discr;
+
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+
+ wait for sysclock_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/firmware/simulation_src/pmtPulseGenerator_rtl.vhd b/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
new file mode 100644
index 00000000..d95688bd
--- /dev/null
+++ b/firmware/simulation_src/pmtPulseGenerator_rtl.vhd
@@ -0,0 +1,152 @@
+--=============================================================================
+--! @file pmtPulseGenerator_rtl.vhd
+--=============================================================================
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+-------------------------------------------------------------------------------
+-- VHDL Architecture pmtPulseGenerator.rtl
+--
+--! @brief Produce a series of random pulses. Timing can be optionally
+--! referered to system clock.
+--
+--! @author David Cussans , David.Cussans@bristol.ac.uk
+--!
+--
+--! @date 4/3/14
+--
+--! @version v0.1
+--
+--! @details
+--!
+--!
+--! <b>Dependencies:</b>\n
+--!
+--! <b>References:</b>\n
+--!
+--! <b>Modified by: </b>\n
+--! Author:
+-------------------------------------------------------------------------------
+--! \n\n<b>Last changes:</b>\n
+-------------------------------------------------------------------------------
+--! @todo Implement a periodic calibration sequence \n
+--! <another thing to do> \n
+--
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+use IEEE.Math_real.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+USE ieee.numeric_std.ALL;
+
+entity pmtPulseGenerator is
+
+ generic (
+ g_NUM_CHANNELS : positive := 4); -- --! Number of signal lines
+
+ port (
+ pulses_o : out std_logic_vector(g_NUM_CHANNELS-1 downto 0); --! Output pulses
+ -- pulseRecord_o : out t_pulseRecord ; --! Record describing the output pulses
+ numPulses_i : in positive; --! Number of pulses/events to generate
+ averagePulseInterval_i : in time; --! Mean interval between pulses
+ averagePulseWidth_i : in time; --! Mean pulse width (must be smaller than interval)
+ pulseJitter_i : in time; --! Time spread between outputs.
+ sysclock_i : in std_logic; -- --! Pulses can be optionally referred to rising edge
+ simulationDone_o : out boolean --! Goes high when pulse generation is finished
+ );
+end pmtPulseGenerator;
+
+ARCHITECTURE behavior OF pmtPulseGenerator IS
+
+ signal s_masterPulse : std_logic := '0';
+
+BEGIN
+
+ -- Generate "master" pulse
+ stim_proc: process
+ variable v_seed1 : POSITIVE := 28;
+ variable v_seed2 : POSITIVE := 17;
+ variable v_pulseWidth , v_pulseLow : time ;
+ variable Rand : real;
+
+ begin
+
+ assert ( averagePulseInterval_i > averagePulseWidth_i ) report "Pulse width can't be larger than pulse interval!!" severity failure;
+
+ simulationDone_o <= False;
+ s_masterPulse <= '0';
+
+ for I in 1 to numPulses_i loop
+
+ -- wait for random gap between pulses
+ uniform(v_seed1, v_seed2, Rand);
+ v_pulseLow := Rand * (averagePulseInterval_i - averagepulseWidth_i);
+ wait for v_pulseLow;
+
+ s_masterPulse <= '1'; --! Take pulse high.
+
+ -- wait for random pulse width
+ uniform(v_seed1, v_seed2, Rand);
+ v_pulseWidth := Rand * averagePulseWidth_i;
+ wait for v_pulseWidth;
+
+ s_masterPulse <= '0'; --! Return pulse low.
+
+ end loop;
+
+ simulationDone_o <= True;
+ wait;
+ end process;
+
+ --! Generate separate outputs that follow the main pulse with timing jitter.
+ gen_PulseOutputs: for v_output in 0 to g_NUM_CHANNELS-1 generate
+ -- purpose: Sets the individual output pulses based on master pulse
+ -- output: pulses_o(v_output)
+ p_setOutputs: process
+ variable v_timeOffset : time := 0 ns; -- --! offset between master pulse changing and output changing.
+ variable Rand : real;
+ variable v_seed1 : POSITIVE := 19*(v_output+1);
+ variable v_seed2 : POSITIVE := 47*(v_output+1);
+
+ begin -- process p_setOutputs
+
+ -- set the output low
+ -- pulses_o(v_output) <= '0';
+
+ wait on s_masterPulse;
+
+ if rising_edge(s_masterPulse) then
+
+ --report "Pulse output proc: found rising edge" severity note;
+
+ -- Generate some jitter
+ uniform(v_seed1, v_seed2, Rand);
+ v_timeOffset := Rand * pulseJitter_i;
+
+ --report "Pulse output proc: waiting to set output pulse" severity note;
+
+ -- wait for that jitter
+ wait for v_timeOffset;
+
+ -- set the output high
+ pulses_o(v_output) <= '1';
+
+ else
+ -- falling edge....
+ -- wait for jitter time
+ wait for v_timeOffset;
+
+ -- return the output low.
+ pulses_o(v_output) <= '0';
+
+ end if;
+
+ end process p_setOutputs;
+
+ end generate gen_PulseOutputs;
+END;
--
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