From 2784c11e67a0b2f4e32dd59b702bcc28ce61fb83 Mon Sep 17 00:00:00 2001
From: David Cussans <David.Cussans@bristol.ac.uk>
Date: Tue, 20 Feb 2018 16:06:06 +0000
Subject: [PATCH] Pushing changes to dep files and tidying up VHDL files. Still
have problems with constraints
---
README.md | 9 +
components/tlu/firmware/hdl/GPP_rtl.vhd | 312 ------------------
components/tlu/firmware/hdl/counterDown.vhd | 50 ---
components/tlu/firmware/hdl/eth_7s_gmii.vhd | 183 ----------
components/tlu/firmware/hdl/eth_7s_rgmii.vhd | 184 -----------
.../tlu/firmware/hdl/ipbus_addr_decode.vhd | 50 ---
.../hdl/ipbus_decode_ipbus_example.vhd | 69 ----
.../tlu/firmware/hdl/ipbus_decode_tlu.vhd | 73 ----
projects/TLU_v1e/addr_table/TLUaddrmap.xml | 18 +-
projects/TLU_v1e/firmware/cfg/tlu_1e.dep | 13 +-
.../TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep | 2 -
.../firmware/hdl/top_enclustra_tlu_v1e.vhd | 53 +--
projects/TLU_v1e/firmware/ucf/I2C_constr.xdc | 2 +
.../firmware/ucf/TLU_enclustra_v1e.xdc | 18 +-
14 files changed, 72 insertions(+), 964 deletions(-)
delete mode 100644 components/tlu/firmware/hdl/GPP_rtl.vhd
delete mode 100644 components/tlu/firmware/hdl/counterDown.vhd
delete mode 100644 components/tlu/firmware/hdl/eth_7s_gmii.vhd
delete mode 100644 components/tlu/firmware/hdl/eth_7s_rgmii.vhd
delete mode 100644 components/tlu/firmware/hdl/ipbus_addr_decode.vhd
delete mode 100644 components/tlu/firmware/hdl/ipbus_decode_ipbus_example.vhd
delete mode 100644 components/tlu/firmware/hdl/ipbus_decode_tlu.vhd
diff --git a/README.md b/README.md
index 1db423c7..a461e64f 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,16 @@ Set up the environment for Xilinx Vivado, then:
# Edit the files in the IPBus repostitory to expose the 200MHz clock
sed -i 's/onehz);/onehz); clk_200_o<=clk200;/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
sed -i 's/clk125_o: out std_logic/clk125_o, clk_200_o: out std_logic/' ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra.vhd
+ # Comment out the cfg signals in the IPBus constraints file.
+ patch < ../../src/firmware_AIDA/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
ipbb vivado impl
ipbb vivado bitfile
ipbb vivado package
deactivate
+
+In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
+
+ pushd firmware_AIDA/projects/TLU_v1e/addr_table
+ /opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
+ copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/firmware_AIDA/components/tlu/firmware/hdl/
+
\ No newline at end of file
diff --git a/components/tlu/firmware/hdl/GPP_rtl.vhd b/components/tlu/firmware/hdl/GPP_rtl.vhd
deleted file mode 100644
index bc02a5ef..00000000
--- a/components/tlu/firmware/hdl/GPP_rtl.vhd
+++ /dev/null
@@ -1,312 +0,0 @@
---=============================================================================
---! @file GPP_rtl.vhd
---=============================================================================
---
--------------------------------------------------------------------------------
--- --
--- University of Santiago de Compostela, High Energy Physics Group.
--- --
-------------------------------------------------------------------------------- --
---
---
---! @brief GPP - General purpose pulser. Generates a sycronous custom pulse \n
---! IPBus address map:\n
---
---! @author Alvaro Dosil , alvaro.dosil@usc.es
---
---! @date 15:42:31 01/15/2013
---
---! @version v0.1
---
---! @details
---!
---!
---! <b>Dependencies:</b>\n
---!
---! <b>References:</b>\n
---!
---! <b>Modified by:
---! Author:
--------------------------------------------------------------------------------
---! \n\n<b>Last changes:</b>\n
--------------------------------------------------------------------------------
---! @todo <next thing to do> \n
---! <another thing to do> \n
---
---------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity GPP is
- GENERIC(
- g_IPBUS_WIDTH : positive := 32
- );
- PORT( clk_i : IN std_logic; --! Rising edge active
- Enable_i : IN std_logic; --
- Reset_i : IN std_logic; --
- RstPulsCnt_i : IN std_logic; -- Reset pulse counter
- Trigger_i : IN std_logic; -- Trigger input signal
- NMaxPulses_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Max number of pulses
- SuDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Startup dead time
- PulsLen_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse length
- IpDTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Interpulse dead time
- RearmTime_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Time before rearm after reach the max number of pulses
- Force_PullDown_i : IN std_logic; -- Force pull down
- WU_i : IN std_logic; -- Output trigger signal with update
- PulseDelay_i : IN std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Pulse delay
- event_number_o : OUT std_logic_vector(g_IPBUS_WIDTH-1 downto 0); -- Event number
- MaxPulses_o : OUT std_logic; -- Maximun number of pulses reached
- Pulse_o : OUT std_logic; --! pulse output
- Pulse_d_o : OUT std_logic --! pulse output delayed
- );
-end GPP;
-
-architecture rtl of GPP is
- --! FSM state values
- type state_values is (st0, st1, st2, st3, st4, st5, st6);
- signal pres_state, next_state: state_values;
-
- signal s_PulsCnt_en : std_logic := '0'; --! Pulse counter enable
- signal s_RstPulsCnt : std_logic := '0'; --! Reset pulse counter
- signal s_RstPulsCnt_int : std_logic := '0'; --! Reset pulse counter internal signal
- signal s_PulsLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Pulse Length
- signal s_PulsCnt : unsigned(g_IPBUS_WIDTH-1 downto 0) := (others => '0'); --! Pulse counter value
- signal s_MaxPulses : std_logic := '0'; --! Max number of pulses reached
- signal s_Pulse : std_logic := '0'; --! Active pulse signal
- signal s_Pulse_d : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others=>'0'); --! Active pulse signal delayed
-
- signal s_load_SuDTime : std_logic := '1'; --! Counter load signal
- signal s_SuDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
- signal EOSDT : std_logic := '0'; --! End of startup dead time signal
-
- signal s_load_PulsLen : std_logic := '1'; --! Counter load
- signal EOP : std_logic := '0'; --! End of pulse length signal
-
- signal s_load_IpDTime : std_logic := '1'; --! Counter load signal
- signal s_IpDTime : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Interpulse dead time counter
- signal EOIDT : std_logic := '0'; --! End of interpulse dead time signal
-
- signal s_load_RearmTime : std_logic := '1'; --! Rearm counter load signal
- signal s_RearmLen : std_logic_vector(g_IPBUS_WIDTH-1 downto 0); --! Startup dead time counter
- signal EOREARM : std_logic := '0'; --! End of startup dead time signal
-
-begin
- -----------------------------------------------------------------------------
- -- Counters
- -----------------------------------------------------------------------------
- --! Startup dead time counter
- c_startup_dtime : entity work.CounterDown
- generic map(
- MAX_WIDTH => g_IPBUS_WIDTH
- )
- port map(
- Clk => clk_i,
- Reset => '0',
- Load => s_load_SuDTime,
- InitVal => std_logic_vector(unsigned(s_SuDTime)-1),
- Count => open,
- Q => EOSDT
- );
- s_SuDTime <= x"00000001" when SuDTime_i = x"00000000" -- At least one clock cycle pulse is generated
- else SuDTime_i;
-
- --! Pulse time counter
- c_pulse_time : entity work.CounterDown
- generic map(
- MAX_WIDTH => g_IPBUS_WIDTH
- )
- port map(
- Clk => clk_i,
- Reset => '0',
- Load => s_load_PulsLen,
- InitVal => std_logic_vector(unsigned(s_PulsLen)-1),
- Count => open,
- Q => EOP
- );
- s_PulsLen <= x"00000001" when PulsLen_i = x"00000000" -- At least one clock cycle pulse is generated
- else PulsLen_i;
-
- --! Interpulse dead time counter
- c_interpulse_dtime : entity work.CounterDown
- generic map(
- MAX_WIDTH => g_IPBUS_WIDTH
- )
- port map(
- Clk => clk_i,
- Reset => '0',
- Load => s_load_IpDTime,
- InitVal => std_logic_vector(unsigned(s_IpDTime)-1),
- Count => open,
- Q => EOIDT
- );
- s_IpDTime <= x"00000001" when IpDTime_i = x"00000000" -- At least one clock cycle pulse is generated
- else IpDTime_i;
-
- --! Rearm time after the max pulses reached
- c_rearm_dtime : entity work.CounterDown
- generic map(
- MAX_WIDTH => g_IPBUS_WIDTH
- )
- port map(
- Clk => clk_i,
- Reset => '0',
- Load => s_load_RearmTime,
- InitVal => std_logic_vector(unsigned(s_RearmLen)-1),
- Count => open,
- Q => EOREARM
- );
- s_RearmLen <= x"00000001" when RearmTime_i = x"00000000" -- At least one clock cycle pulse is generated
- else RearmTime_i;
-
-
- --! FSM register
- statereg: process(clk_i, Enable_i, Reset_i)
- begin
- if Enable_i = '0' then
- pres_state <= st0; -- Move to st0 - INITIAL STATE
-
- elsif Reset_i = '1' then
- pres_state <= st0; -- Move to st0 - INITIAL STATE
-
- elsif rising_edge(clk_i) then
- pres_state <= next_state; -- Move to next state
-
- end if;
- end process statereg;
-
-
- --! FSM combinational block
- fsm: process(pres_state, Enable_i, Reset_i, Trigger_i, s_MaxPulses, EOP, EOSDT, EOIDT, Force_PullDown_i)
- begin
- next_state <= pres_state;
- -- Default values
- s_Pulse <= '0';
- s_load_SuDTime <= '1';
- s_load_PulsLen <= '1';
- s_load_IpDTime <= '1';
- s_load_RearmTime <= '1';
- s_RstPulsCnt_int <= '0';
-
- case pres_state is
-
- -- st0 - INITIAL STATE
- when st0=>
- if (Enable_i = '1') and (Reset_i = '0') then
- next_state <= st1; -- Next state is "st1 - IDLE"
- end if;
-
- -- st1 - IDLE STATE
- when st1=>
- if s_MaxPulses = '1' then
- next_state <= st5; -- Next state is "st5 - NMAX PULSES REACHED"
- else
- if Trigger_i = '1' and Force_PullDown_i = '0' then
- if (to_integer(unsigned(SuDTime_i)) = 0) then
- next_state <= st3; -- Next state is "st3 - PULSE"
- else
- next_state <= st2; -- Next state is "st2 - STARTUP DEAD-TIME"
- end if;
- end if;
- end if;
-
- -- st2 - STARTUP DEAD-TIME
- when st2=>
- s_load_SuDTime <= '0';
- if EOSDT = '1' then
- next_state <= st3; -- Next state is "st3 - PULSE"
- end if;
-
- -- st3 - PULSE
- when st3=>
- s_Pulse <= '1';
- s_load_PulsLen <= '0';
-
- if (EOP = '1') or (Force_PullDown_i = '1')then
- if (to_integer(unsigned(IpDTime_i)) = 0) then
- next_state <= st1; -- Next state is "st1 - IDLE"
- else
- next_state <= st4; -- Next state is "st4 - INTERPULSE DEAD-TIME"
- end if;
- end if;
-
- if Trigger_i = '1' then
- if (WU_i = '1') then
- next_state <= st6; -- Next state is "st6 - RELOAD PULSE TIMER"
- end if;
- end if;
-
-
- -- st4 - INTERPULSE DEAD-TIME
- when st4=>
- s_load_IpDTime <= '0';
- if EOIDT = '1' then
- next_state <= st1; -- Next state is "st1 - IDLE"
- end if;
-
- -- st5 - NMAX PULSES REACHED
- when st5=>
- s_load_RearmTime <= '0';
- if EOREARM = '1' then
- next_state <= st1; -- Next state is "st1 - IDLE"
- s_RstPulsCnt_int <= '1';
- end if;
-
- -- st6 - RELOAD PULSE TIMER
- when st6=>
- s_Pulse <= '1';
- next_state <= st3; -- Next state is "st3 - PULSE"
-
--- when others=>
--- next_state<=st0; -- Next state is "st0 - INITIAL STATE"
-
- end case;
-
- end process fsm;
-
- -- Pulse reg
- p_reg_pulse : process ( clk_i , Reset_i )
- begin
- if Reset_i = '1' then
- s_Pulse_d <= (others => '0');
-
- elsif rising_edge(clk_i) then
- for i in 0 to g_IPBUS_WIDTH-2 loop
- s_Pulse_d(i+1) <= s_Pulse_d(i);
- end loop;
- s_Pulse_d(0) <= s_Pulse;
- end if;
- end process p_reg_pulse;
-
- event_number_o <= std_logic_vector(s_PulsCnt);
- MaxPulses_o <= s_MaxPulses;
- Pulse_o <= s_Pulse;
- Pulse_d_o <= s_Pulse when PulseDelay_i = x"00000000" else
- s_Pulse_d(to_integer(unsigned(PulseDelay_i)-1));
-
-
- -----------------------------------------------------------------------------
- -- Count runs and synchronization
- -----------------------------------------------------------------------------
- p_PulsCounter : process (clk_i )
- begin -- process p_run_counter
-
- if rising_edge(clk_i) then
- if s_RstPulsCnt = '1' then
- s_PulsCnt <= (others => '0');
- elsif s_PulsCnt_en = '1' then
- s_PulsCnt <= s_PulsCnt + 1;
- end if;
-
- end if;
- end process p_PulsCounter;
-
- s_RstPulsCnt <= Reset_i or RstPulsCnt_i or s_RstPulsCnt_int;
- s_PulsCnt_en <= '1' when (s_Pulse = '1') and (s_Pulse_d(0) = '0') and (s_MaxPulses = '0')
- else '0';
- s_MaxPulses <= '1' when (s_PulsCnt = unsigned(NMaxPulses_i)) and (NMaxPulses_i /= x"00000000")
- else '0';
-
-
-END ARCHITECTURE rtl;
-
diff --git a/components/tlu/firmware/hdl/counterDown.vhd b/components/tlu/firmware/hdl/counterDown.vhd
deleted file mode 100644
index de150900..00000000
--- a/components/tlu/firmware/hdl/counterDown.vhd
+++ /dev/null
@@ -1,50 +0,0 @@
---Counter down
---Outputs: Q<='1' while counting
--- Q<='0' if not counting
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
-ENTITY CounterDown IS
- GENERIC(
- MAX_WIDTH: positive := 32
- );
- PORT(
- Clk : in std_logic;
- Reset : in std_logic;
- Load : in std_logic;
- InitVal : in std_logic_vector(MAX_WIDTH-1 downto 0);
- Count : out Std_logic_vector(MAX_WIDTH-1 downto 0);
- Q : out std_logic
- );
-END ENTITY CounterDown;
-
-architecture rtl of CounterDown is
- signal cnt : std_logic_vector(MAX_WIDTH-1 downto 0);
- signal Qtmp : std_logic;
-
-begin
- Counter: process (Clk, Reset)
- begin
- if (Reset='1') then
- cnt <= (others =>'0');
- elsif rising_edge(Clk) then
- if (Load='1') then
- cnt <= InitVal;
- else
- if Qtmp='0' then
- cnt <= std_logic_vector(unsigned(cnt) - 1);
- end if;
- end if;
- end if;
- end process;
-
- Qtmp <= '1' when cnt=(cnt'range=>'0') else
- '0';
-
- Count <= cnt;
- Q <= Qtmp;
-end rtl;
diff --git a/components/tlu/firmware/hdl/eth_7s_gmii.vhd b/components/tlu/firmware/hdl/eth_7s_gmii.vhd
deleted file mode 100644
index 4db967ad..00000000
--- a/components/tlu/firmware/hdl/eth_7s_gmii.vhd
+++ /dev/null
@@ -1,183 +0,0 @@
--- Contains the instantiation of the Xilinx MAC IP plus the GMII PHY interface
---
--- Do not change signal names in here without corresponding alteration to the timing contraints file
---
--- Dave Newbold, April 2011
---
--- $Id$
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library unisim;
-use unisim.VComponents.all;
-
-use work.emac_hostbus_decl.all;
-
-entity eth_7s_gmii is
- port(
- clk125: in std_logic;
- clk200: in std_logic;
- rst: in std_logic;
- gmii_gtx_clk: out std_logic;
- gmii_txd: out std_logic_vector(7 downto 0);
- gmii_tx_en: out std_logic;
- gmii_tx_er: out std_logic;
- gmii_rx_clk: in std_logic;
- gmii_rxd: in std_logic_vector(7 downto 0);
- gmii_rx_dv: in std_logic;
- gmii_rx_er: in std_logic;
- tx_data: in std_logic_vector(7 downto 0);
- tx_valid: in std_logic;
- tx_last: in std_logic;
- tx_error: in std_logic;
- tx_ready: out std_logic;
- rx_data: out std_logic_vector(7 downto 0);
- rx_valid: out std_logic;
- rx_last: out std_logic;
- rx_error: out std_logic;
- hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
- hostbus_out: out emac_hostbus_out
- );
-
-end eth_7s_gmii;
-
-architecture rtl of eth_7s_gmii is
-
- COMPONENT temac_gbe_v9_0_rgmii
- PORT (
- gtx_clk : IN STD_LOGIC;
- glbl_rstn : IN STD_LOGIC;
- rx_axi_rstn : IN STD_LOGIC;
- tx_axi_rstn : IN STD_LOGIC;
- rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
- rx_statistics_valid : OUT STD_LOGIC;
- rx_mac_aclk : OUT STD_LOGIC;
- rx_reset : OUT STD_LOGIC;
- rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- rx_axis_mac_tvalid : OUT STD_LOGIC;
- rx_axis_mac_tlast : OUT STD_LOGIC;
- rx_axis_mac_tuser : OUT STD_LOGIC;
- tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- tx_statistics_valid : OUT STD_LOGIC;
- tx_mac_aclk : OUT STD_LOGIC;
- tx_reset : OUT STD_LOGIC;
- tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- tx_axis_mac_tvalid : IN STD_LOGIC;
- tx_axis_mac_tlast : IN STD_LOGIC;
- tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- tx_axis_mac_tready : OUT STD_LOGIC;
- pause_req : IN STD_LOGIC;
- pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- speedis100 : OUT STD_LOGIC;
- speedis10100 : OUT STD_LOGIC;
- gmii_txd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- gmii_tx_en : OUT STD_LOGIC;
- gmii_tx_er : OUT STD_LOGIC;
- gmii_tx_clk : OUT STD_LOGIC;
- gmii_rxd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- gmii_rx_dv : IN STD_LOGIC;
- gmii_rx_er : IN STD_LOGIC;
- gmii_rx_clk : IN STD_LOGIC;
- rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
- tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT mac_fifo_axi4
- PORT (
- m_aclk : IN STD_LOGIC;
- s_aclk : IN STD_LOGIC;
- s_aresetn : IN STD_LOGIC;
- s_axis_tvalid : IN STD_LOGIC;
- s_axis_tready : OUT STD_LOGIC;
- s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- s_axis_tlast : IN STD_LOGIC;
- s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- m_axis_tvalid : OUT STD_LOGIC;
- m_axis_tready : IN STD_LOGIC;
- m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- m_axis_tlast : OUT STD_LOGIC;
- m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
- );
- END COMPONENT;
-
- signal rx_data_e: std_logic_vector(7 downto 0);
- signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
- signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
-
-begin
-
- idelayctrl0: idelayctrl port map(
- refclk => clk200,
- rst => rst
- );
-
- rstn <= not rst;
-
- emac0: temac_gbe_v9_0_rgmii
- port map(
- gtx_clk => clk125,
- glbl_rstn => rstn,
- rx_axi_rstn => '1',
- tx_axi_rstn => '1',
- rx_statistics_vector => open,
- rx_statistics_valid => open,
- rx_mac_aclk => rx_clk_e,
- rx_reset => rx_rst_e,
- rx_axis_mac_tdata => rx_data_e,
- rx_axis_mac_tvalid => rx_valid_e,
- rx_axis_mac_tlast => rx_last_e,
- rx_axis_mac_tuser => rx_user_e,
- tx_ifg_delay => X"00",
- tx_statistics_vector => open,
- tx_statistics_valid => open,
- tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
- tx_reset => open,
- tx_axis_mac_tdata => tx_data,
- tx_axis_mac_tvalid => tx_valid,
- tx_axis_mac_tlast => tx_last,
- tx_axis_mac_tuser(0) => tx_error,
- tx_axis_mac_tready => tx_ready,
- pause_req => '0',
- pause_val => X"0000",
- speedis100 => open,
- speedis10100 => open,
- gmii_txd => gmii_txd,
- gmii_tx_en => gmii_tx_en,
- gmii_tx_er => gmii_tx_er,
- gmii_tx_clk => gmii_gtx_clk,
- gmii_rxd => gmii_rxd,
- gmii_rx_dv => gmii_rx_dv,
- gmii_rx_er => gmii_rx_er,
- gmii_rx_clk => gmii_rx_clk,
- rx_configuration_vector => X"0000_0000_0000_0000_0812",
- tx_configuration_vector => X"0000_0000_0000_0000_0012"
- );
-
- rx_user_ef(0) <= rx_user_e;
- rx_error <= rx_user_f(0);
- rx_rst_en <= not rx_rst_e;
-
- fifo: mac_fifo_axi4
- port map(
- m_aclk => clk125,
- s_aclk => rx_clk_e,
- s_aresetn => rx_rst_en,
- s_axis_tvalid => rx_valid_e,
- s_axis_tready => open,
- s_axis_tdata => rx_data_e,
- s_axis_tlast => rx_last_e,
- s_axis_tuser => rx_user_ef,
- m_axis_tvalid => rx_valid,
- m_axis_tready => '1',
- m_axis_tdata => rx_data,
- m_axis_tlast => rx_last,
- m_axis_tuser => rx_user_f
- ); -- Clock domain crossing FIFO
-
- hostbus_out.hostrddata <= (others => '0');
- hostbus_out.hostmiimrdy <= '0';
-
-end rtl;
diff --git a/components/tlu/firmware/hdl/eth_7s_rgmii.vhd b/components/tlu/firmware/hdl/eth_7s_rgmii.vhd
deleted file mode 100644
index 3e2e1670..00000000
--- a/components/tlu/firmware/hdl/eth_7s_rgmii.vhd
+++ /dev/null
@@ -1,184 +0,0 @@
--- Contains the instantiation of the Xilinx MAC & PHY interface for RGMII
---
--- Do not change signal names in here without corresponding alteration to the timing contraints file
---
--- Dave Newbold, October 2016
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-library unisim;
-use unisim.VComponents.all;
-use work.emac_hostbus_decl.all;
-
-entity eth_7s_rgmii is
- port(
- clk125: in std_logic;
- clk125_90: in std_logic;
- clk200: in std_logic;
- rst: in std_logic;
- rgmii_txd: out std_logic_vector(3 downto 0);
- rgmii_tx_ctl: out std_logic;
- rgmii_txc: out std_logic;
- rgmii_rxd: in std_logic_vector(3 downto 0);
- rgmii_rx_ctl: in std_logic;
- rgmii_rxc: in std_logic;
- tx_data: in std_logic_vector(7 downto 0);
- tx_valid: in std_logic;
- tx_last: in std_logic;
- tx_error: in std_logic;
- tx_ready: out std_logic;
- rx_data: out std_logic_vector(7 downto 0);
- rx_valid: out std_logic;
- rx_last: out std_logic;
- rx_error: out std_logic;
- hostbus_in: in emac_hostbus_in := ('0', "00", "0000000000", X"00000000", '0', '0', '0');
- hostbus_out: out emac_hostbus_out;
- status: out std_logic_vector(3 downto 0)
- );
-
-end eth_7s_rgmii;
-
-architecture rtl of eth_7s_rgmii is
-
- COMPONENT temac_gbe_v9_rgmii
- PORT (
- gtx_clk : IN STD_LOGIC;
- gtx_clk90 : IN STD_LOGIC;
- glbl_rstn : IN STD_LOGIC;
- rx_axi_rstn : IN STD_LOGIC;
- tx_axi_rstn : IN STD_LOGIC;
- rx_statistics_vector : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
- rx_statistics_valid : OUT STD_LOGIC;
- rx_mac_aclk : OUT STD_LOGIC;
- rx_reset : OUT STD_LOGIC;
- rx_axis_mac_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- rx_axis_mac_tvalid : OUT STD_LOGIC;
- rx_axis_mac_tlast : OUT STD_LOGIC;
- rx_axis_mac_tuser : OUT STD_LOGIC;
- tx_ifg_delay : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- tx_statistics_vector : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
- tx_statistics_valid : OUT STD_LOGIC;
- tx_mac_aclk : OUT STD_LOGIC;
- tx_reset : OUT STD_LOGIC;
- tx_axis_mac_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- tx_axis_mac_tvalid : IN STD_LOGIC;
- tx_axis_mac_tlast : IN STD_LOGIC;
- tx_axis_mac_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- tx_axis_mac_tready : OUT STD_LOGIC;
- pause_req : IN STD_LOGIC;
- pause_val : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- speedis100 : OUT STD_LOGIC;
- speedis10100 : OUT STD_LOGIC;
- rgmii_txd : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
- rgmii_tx_ctl : OUT STD_LOGIC;
- rgmii_txc : OUT STD_LOGIC;
- rgmii_rxd : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
- rgmii_rx_ctl : IN STD_LOGIC;
- rgmii_rxc : IN STD_LOGIC;
- inband_link_status : OUT STD_LOGIC;
- inband_clock_speed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- inband_duplex_status : OUT STD_LOGIC;
- rx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0);
- tx_configuration_vector : IN STD_LOGIC_VECTOR(79 DOWNTO 0)
- );
- END COMPONENT;
-
- COMPONENT mac_fifo_axi4
- PORT (
- m_aclk : IN STD_LOGIC;
- s_aclk : IN STD_LOGIC;
- s_aresetn : IN STD_LOGIC;
- s_axis_tvalid : IN STD_LOGIC;
- s_axis_tready : OUT STD_LOGIC;
- s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- s_axis_tlast : IN STD_LOGIC;
- s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- m_axis_tvalid : OUT STD_LOGIC;
- m_axis_tready : IN STD_LOGIC;
- m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- m_axis_tlast : OUT STD_LOGIC;
- m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
- );
- END COMPONENT;
-
- signal rx_data_e: std_logic_vector(7 downto 0);
- signal rx_clk_e, rx_valid_e, rx_last_e, rx_user_e, rx_rst_e, rx_rst_en, rstn: std_logic;
- signal rx_user_f, rx_user_ef: std_logic_vector(0 downto 0);
-
-begin
-
- idelayctrl0: idelayctrl port map(
- refclk => clk200,
- rst => rst
- );
-
- rstn <= not rst;
-
- emac0: temac_gbe_v9_rgmii
- port map(
- gtx_clk => clk125,
- gtx_clk90 => clk125_90,
- glbl_rstn => rstn,
- rx_axi_rstn => '1',
- tx_axi_rstn => '1',
- rx_statistics_vector => open,
- rx_statistics_valid => open,
- rx_mac_aclk => rx_clk_e,
- rx_reset => rx_rst_e,
- rx_axis_mac_tdata => rx_data_e,
- rx_axis_mac_tvalid => rx_valid_e,
- rx_axis_mac_tlast => rx_last_e,
- rx_axis_mac_tuser => rx_user_e,
- tx_ifg_delay => X"00",
- tx_statistics_vector => open,
- tx_statistics_valid => open,
- tx_mac_aclk => open, -- Internally connected to gtx_clk inside core
- tx_reset => open,
- tx_axis_mac_tdata => tx_data,
- tx_axis_mac_tvalid => tx_valid,
- tx_axis_mac_tlast => tx_last,
- tx_axis_mac_tuser(0) => tx_error,
- tx_axis_mac_tready => tx_ready,
- pause_req => '0',
- pause_val => X"0000",
- speedis100 => open,
- speedis10100 => open,
- rgmii_txd => rgmii_txd,
- rgmii_tx_ctl => rgmii_tx_ctl,
- rgmii_txc => rgmii_txc,
- rgmii_rxd => rgmii_rxd,
- rgmii_rx_ctl => rgmii_rx_ctl,
- rgmii_rxc => rgmii_rxc,
- inband_link_status => status(0),
- inband_clock_speed => status(3 downto 2),
- inband_duplex_status => status(1),
- rx_configuration_vector => X"0000_0000_0000_0000_0812",
- tx_configuration_vector => X"0000_0000_0000_0000_0012"
- );
-
- rx_user_ef(0) <= rx_user_e;
- rx_error <= rx_user_f(0);
- rx_rst_en <= not rx_rst_e;
-
- fifo: mac_fifo_axi4
- port map(
- m_aclk => clk125,
- s_aclk => rx_clk_e,
- s_aresetn => rx_rst_en,
- s_axis_tvalid => rx_valid_e,
- s_axis_tready => open,
- s_axis_tdata => rx_data_e,
- s_axis_tlast => rx_last_e,
- s_axis_tuser => rx_user_ef,
- m_axis_tvalid => rx_valid,
- m_axis_tready => '1',
- m_axis_tdata => rx_data,
- m_axis_tlast => rx_last,
- m_axis_tuser => rx_user_f
- ); -- Clock domain crossing FIFO
-
- hostbus_out.hostrddata <= (others => '0');
- hostbus_out.hostmiimrdy <= '0';
-
-end rtl;
diff --git a/components/tlu/firmware/hdl/ipbus_addr_decode.vhd b/components/tlu/firmware/hdl/ipbus_addr_decode.vhd
deleted file mode 100644
index dc630e87..00000000
--- a/components/tlu/firmware/hdl/ipbus_addr_decode.vhd
+++ /dev/null
@@ -1,50 +0,0 @@
--- Address decode logic for ipbus fabric
---
--- This file has been AUTOGENERATED from the address table - do not hand edit
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-use work.ipbus.all;
-
-package ipbus_addr_decode is
-
- function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer;
-
-end ipbus_addr_decode;
-
-package body ipbus_addr_decode is
-
- function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
- variable sel : integer;
- begin
- if std_match(addr, "-----------------------0001-----") then
- sel := 0; -- DUTInterfaces / base 00000020 / mask 0000001f
- elsif std_match(addr, "-----------------------0010-----") then
- sel := 1; -- triggerInputs / base 00000040 / mask 0000001f
- elsif std_match(addr, "-----------------------0011-----") then
- sel := 2; -- triggerLogic / base 00000060 / mask 0000001f
- elsif std_match(addr, "-----------------------0100-----") then
- sel := 3; -- eventBuffer / base 00000080 / mask 0000001f
- elsif std_match(addr, "-----------------------0101-----") then
- sel := 4; -- logic_clocks / base 000000a0 / mask 0000001f
- elsif std_match(addr, "-----------------------0110-----") then
- sel := 5; -- i2c_master / base 000000c0 / mask 00000007
- elsif std_match(addr, "-----------------------1010-----") then
- sel := 6; -- Event_Formatter / base 00000140 / mask 0000001f
- elsif std_match(addr, "-----------------------1011-----") then
- sel := 7; -- TPix3_iface / base 00000160 / mask 0000001f
- elsif std_match(addr, "-----------------------0000-----") then
- sel := 8; -- version / base 00000000 / mask 00000000
- else
- sel := 99;
- end if;
- return sel;
- end ipbus_addr_sel;
-
-end ipbus_addr_decode;
diff --git a/components/tlu/firmware/hdl/ipbus_decode_ipbus_example.vhd b/components/tlu/firmware/hdl/ipbus_decode_ipbus_example.vhd
deleted file mode 100644
index a315ed03..00000000
--- a/components/tlu/firmware/hdl/ipbus_decode_ipbus_example.vhd
+++ /dev/null
@@ -1,69 +0,0 @@
--- Address decode logic for ipbus fabric
---
---
--- We assume the synthesis tool is clever enough to recognise exclusive conditions
--- in the if statement.
---
--- Dave Newbold, February 2011
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_ipbus_example is
-
- constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- constant N_SLV_CTRL_REG: integer := 0; --for tests
- constant N_SLV_REG: integer := 1; -- for tests
- constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
- constant N_SLV_DUT: integer :=3;
- constant N_SLV_SHUT: integer :=4;
- constant N_SLV_EVBUF: integer :=5;
- constant N_SLV_EVFMT: integer :=6;
- constant N_SLV_TRGIN: integer :=7;
- constant N_SLV_TRGLGC: integer :=8;
- constant N_SLV_LGCCLK: integer :=9;
-
- constant N_SLAVES: integer := 10; --Total number of slaves
--- END automatically generated VHDL
- --constant N_I2C_CORES: integer := 3; --How many I2C cores
-
-end ipbus_decode_ipbus_example;
-
-package body ipbus_decode_ipbus_example is
-
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- if std_match(addr, "-----------------000----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
- elsif std_match(addr, "-----------------000----------1-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
- --elsif std_match(addr, "-----------------001------------") then
- --sel := ipbus_sel_t(to_unsigned(N_SLV_RAM, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
- --elsif std_match(addr, "-----------------010----------0-") then
- -- sel := ipbus_sel_t(to_unsigned(N_SLV_PRAM, IPBUS_SEL_WIDTH)); -- pram / base 0x00002000 / mask 0x00003002
- elsif std_match(addr, "-----------------011------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
- elsif std_match(addr, "-----------------100------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- i2c / base 0x00004000 / mask 0x00003002
- elsif std_match(addr, "-----------------101------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- i2c / base 0x00005000 / mask 0x00003002
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_ipbus_example;
-
-end ipbus_decode_ipbus_example;
-
diff --git a/components/tlu/firmware/hdl/ipbus_decode_tlu.vhd b/components/tlu/firmware/hdl/ipbus_decode_tlu.vhd
deleted file mode 100644
index 114da401..00000000
--- a/components/tlu/firmware/hdl/ipbus_decode_tlu.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
--- Address decode logic for ipbus fabric
---
---
---
--- Paolo Baesso, February 2017
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use ieee.numeric_std.all;
-
-package ipbus_decode_tlu is
-
- constant IPBUS_SEL_WIDTH: positive := 5; -- Should be enough for now?
- subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- constant N_SLV_CTRL_REG: integer := 0; --for tests
- constant N_SLV_REG: integer := 1; -- for tests
- constant N_SLV_I2C_0: integer := 2; --I2C core for the TLU
- constant N_SLV_DUT: integer :=3;
- constant N_SLV_SHUT: integer :=4;
- constant N_SLV_EVBUF: integer :=5;
- constant N_SLV_EVFMT: integer :=6;
- constant N_SLV_TRGIN: integer :=7;
- constant N_SLV_TRGLGC: integer :=8;
- constant N_SLV_LGCCLK: integer :=9;
-
- constant N_SLAVES: integer := 10; --Total number of IPBus slaves
--- END automatically generated VHDL
- --constant N_I2C_CORES: integer := 3; --How many I2C cores
-
-end ipbus_decode_tlu;
-
-package body ipbus_decode_tlu is
-
- function ipbus_sel_ipbus_example(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t is
- variable sel: ipbus_sel_t;
- begin
-
--- START automatically generated VHDL the Fri Oct 7 12:10:31 2016
- if std_match(addr, "----------------0000----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_CTRL_REG, IPBUS_SEL_WIDTH)); -- ctrl_reg / base 0x00000000 / mask 0x00003002
- elsif std_match(addr, "----------------0000----------1-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_REG, IPBUS_SEL_WIDTH)); -- reg / base 0x00000002 / mask 0x00003002
- elsif std_match(addr, "----------------0001------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_DUT, IPBUS_SEL_WIDTH)); -- ram / base 0x00001000 / mask 0x00003000
- elsif std_match(addr, "----------------0010----------0-") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_SHUT, IPBUS_SEL_WIDTH)); -- shutter / base 0x00002000 / mask 0x00003002
- elsif std_match(addr, "----------------0011------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_I2C_0, IPBUS_SEL_WIDTH)); -- i2c / base 0x00003000 / mask 0x00003002
- elsif std_match(addr, "----------------0100------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_EVBUF, IPBUS_SEL_WIDTH)); -- event buffer / base 0x00004000 / mask 0x00003002
- elsif std_match(addr, "----------------0101------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_EVFMT, IPBUS_SEL_WIDTH)); -- event formatter / base 0x00005000 / mask 0x00003002
- elsif std_match(addr, "----------------0110------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGIN, IPBUS_SEL_WIDTH)); -- trigger inputs / base 0x00006000 / mask 0x00003002
- elsif std_match(addr, "----------------0111------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_TRGLGC, IPBUS_SEL_WIDTH)); -- trigger logic / base 0x00007000 / mask 0x00003002
- elsif std_match(addr, "----------------1000------------") then
- sel := ipbus_sel_t(to_unsigned(N_SLV_LGCCLK, IPBUS_SEL_WIDTH)); -- logic clocks / base 0x00008000 / mask 0x00003002
--- END automatically generated VHDL
-
- else
- sel := ipbus_sel_t(to_unsigned(N_SLAVES, IPBUS_SEL_WIDTH));
- end if;
-
- return sel;
-
- end function ipbus_sel_ipbus_example;
-
-end ipbus_decode_tlu;
-
diff --git a/projects/TLU_v1e/addr_table/TLUaddrmap.xml b/projects/TLU_v1e/addr_table/TLUaddrmap.xml
index 65fb5340..0ecc4993 100644
--- a/projects/TLU_v1e/addr_table/TLUaddrmap.xml
+++ b/projects/TLU_v1e/addr_table/TLUaddrmap.xml
@@ -3,7 +3,7 @@
<node id="TLU">
<!-- Registers for the DUTs. These should be correct -->
-<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
+<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers" fwinfo="endpoint;width=4">
<node id="DutMaskW" address="0x0" permission="w" description="" />
<node id="IgnoreDUTBusyW" address="0x1" permission="w" description="" />
<node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
@@ -16,12 +16,12 @@
<node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
</node>
-<node id="Shutter" address="0x2000" description="Shutter/T0 control">
+<node id="Shutter" address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4">
<node id="ShutterStateW" address="0x0" permission="w" description=""/>
<node id="PulseT0" address="0x1" permission="w" description=""/>
</node>
<!-- I2C registers. Tested ok.-->
-<node id="i2c_master" address="0x3000" description="I2C Master interface">
+<node id="i2c_master" address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3">
<node id="i2c_pre_lo" address="0x0" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_pre_hi" address="0x1" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_ctrl" address="0x2" mask="0x000000ff" permission="rw" description="" />
@@ -29,21 +29,21 @@
<node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
</node>
<!-- Not sure about the FillLevelFlags register -->
-<node id="eventBuffer" address="0x4000" description="Event buffer">
+<node id="eventBuffer" address="0x4000" description="Event buffer" fwinfo="endpoint;width=2">
<node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
<node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
<node id="EventFifoCSR" address="0x2" permission="rw" description="" />
<node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
</node>
<!-- Event formatter registers. Should be ok -->
-<node id="Event_Formatter" address="0x5000" description="Event formatter configuration">
+<node id="Event_Formatter" address="0x5000" description="Event formatter configuration" fwinfo="endpoint;width=3">
<node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
<node id="ResetTimestampW" address="0x1" permission="w" description="" />
<node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
<node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
</node>
<!-- This needs checking. The counters work, not sure about the reset -->
-<node id="triggerInputs" address="0x6000" description="Inputs configuration">
+<node id="triggerInputs" address="0x6000" description="Inputs configuration" fwinfo="endpoint;width=4">
<node id="SerdesRstW" address="0x0" permission="w" description="" />
<node id="SerdesRstR" address="0x8" permission="r" description="" />
<node id="ThrCount0R" address="0x9" permission="r" description="" />
@@ -54,7 +54,7 @@
<node id="ThrCount5R" address="0xe" permission="r" description="" />
</node>
<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
-<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
+<node id="triggerLogic" address="0x7000" description="Trigger logic configuration" fwinfo="endpoint;width=4">
<node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
<node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
<node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
@@ -89,12 +89,12 @@
-->
</node>
-<node id="logic_clocks" address="0x8000" description="Clocks configuration">
+<node id="logic_clocks" address="0x8000" description="Clocks configuration" fwinfo="endpoint;width=2">
<node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
<node id="LogicRst" address="0x1" permission="w" description="" />
</node>
-<node id="version" address="0x1" description="firmware version" permission="r">
+<node id="version" address="0x1" description="firmware version" permission="r" fwinfo="endpoint;width=0">
</node>
<!--
diff --git a/projects/TLU_v1e/firmware/cfg/tlu_1e.dep b/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
index c75a248d..b40b5e78 100644
--- a/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
+++ b/projects/TLU_v1e/firmware/cfg/tlu_1e.dep
@@ -1,10 +1,12 @@
# Entity payload is in tlu_1e.vhd
# src tlu_1e.vhd
+addrtab -t TLUaddrmap.xml
+
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd
src ipbus_decode_top.vhd
-addrtab -t TLUaddrmap.xml
+
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
src -c components/tlu fmcTLU_pkg.vhd
@@ -15,6 +17,10 @@ src -c components/tlu logic_clocks_rtl.vhd
src -c components/tlu trigger/triggerInputs_newTLU_rtl.vhd
src -c components/tlu eventFormatter_rtl.vhd
src -c components/tlu T0_Shutter_Iface_rtl.vhd
+src -c components/tlu counterDownGated_rtl.vhd
+src -c components/tlu delayPulse4x_rtl.vhd
+src -c components/tlu stretchPulse4x_rtl.vhd
+
src -c components/tlu dut/DUTInterfaces_rtl.vhd
src -c components/tlu dut/DUTInterface_AIDA_rtl.vhd
src -c components/tlu dut/DUTInterface_EUDET_rtl.vhd
@@ -34,8 +40,11 @@ src -c components/tlu coincidenceLogic_rtl.vhd
# Hand-hacked IPBus address deocde.
# replace with version generated by IPBus tools
# Move the constants in this file to fmcTLU package.
-src -c components/tlu ipbus_decode_tlu.vhd
+#src -c components/tlu ipbus_decode_tlu.vhd
# ***** CHANGE ME ******
+# Fixed ?
+src -c components/tlu ipbus_decode_TLUaddrmap.vhd
+
# Include I2C components
src -c components/external/opencores_i2c i2c_master_top.vhd
diff --git a/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep b/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep
index c3f7600e..612b72c2 100644
--- a/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep
+++ b/projects/TLU_v1e/firmware/cfg/top_tlu_1e_a35.dep
@@ -1,4 +1,2 @@
include enclustra_ax3_pm3_a35.dep
include tlu_1e.dep
-
-# setup set_top.tcl
diff --git a/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd b/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
index d4e4eee5..d8edf6f4 100644
--- a/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
+++ b/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
@@ -11,7 +11,7 @@ library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.fmcTLU.all;
-use work.ipbus_decode_tlu.all;
+use work.ipbus_decode_TLUaddrmap.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
use UNISIM.vcomponents.all;
@@ -138,8 +138,8 @@ architecture rtl of top_tlu_v1e is
SIGNAL strobe_8x_logic : std_logic; --! Pulses one cycle every 4 of 16x clock.
SIGNAL strobe_4x_logic : std_logic; -- one pulse every 4 cycles of clk_4x
SIGNAL trigger_count : std_logic_vector(g_IPBUS_WIDTH-1 DOWNTO 0);
- SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- ! trigger arrival time ( w.r.t. logic_strobe)
- SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0);
+ SIGNAL trigger_times : t_triggerTimeArray(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! trigger arrival time ( w.r.t. logic_strobe)
+ SIGNAL triggers : std_logic_vector(g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Rising edge of trigger inputs
SIGNAL veto_o : std_logic; --! goes high when one or more DUT are busy
signal ctrl, stat: ipb_reg_v(0 downto 0);
--My signals
@@ -178,12 +178,16 @@ architecture rtl of top_tlu_v1e is
----------------------------------------------
----------------------------------------------
COMPONENT T0_Shutter_Iface
+ generic (
+ g_NUM_ACCELERATOR_SIGNALS: positive := 6
+ );
PORT (
clk_4x_i : IN std_logic;
- clk_4x_strobe : IN std_logic;
+ clk_4x_strobe_i : IN std_logic;
ipbus_clk_i : IN std_logic;
ipbus_i : IN ipb_wbus;
T0_o : OUT std_logic;
+ accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 DOWNTO 0);
ipbus_o : OUT ipb_rbus;
shutter_o : OUT std_logic
);
@@ -454,8 +458,8 @@ begin
port map(
clk => clk_ipb,
reset => rst_ipb,
- ipbus_in => ipbww(N_SLV_CTRL_REG),
- ipbus_out => ipbrr(N_SLV_CTRL_REG),
+ ipbus_in => ipbww(N_SLV_VERSION),
+ ipbus_out => ipbrr(N_SLV_VERSION),
d => stat,
q => ctrl
);
@@ -471,7 +475,7 @@ begin
port map(
ipb_in => ipb_out,
ipb_out => ipb_in,
- sel => ipbus_sel_ipbus_example(ipb_out.ipb_addr),
+ sel => ipbus_sel_TLUaddrmap(ipb_out.ipb_addr),
ipb_to_slaves => ipbww,
ipb_from_slaves => ipbrr
);
@@ -482,11 +486,11 @@ begin
i2c_scl_i => i2c_scl_b,
i2c_sda_i => i2c_sda_b,
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_I2C_0),
+ ipbus_i => ipbww(N_SLV_I2C_MASTER),
ipbus_reset_i => rst_ipb,
i2c_scl_enb_o => s_i2c_scl_enb,
i2c_sda_enb_o => s_i2c_sda_enb,
- ipbus_o => ipbrr(N_SLV_I2C_0)
+ ipbus_o => ipbrr(N_SLV_I2C_MASTER)
);
----------------------------------------------
@@ -496,13 +500,13 @@ begin
)
PORT MAP (
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_LGCCLK),
+ ipbus_i => ipbww(N_SLV_LOGIC_CLOCKS),
ipbus_reset_i => rst_ipb,
Reset_i => logic_clocks_reset,
clk_logic_xtal_i => sysclk_40, -- Not sure this is correct
clk_8x_logic_o => clk_8x_logic,
clk_4x_logic_o => clk_4x_logic,
- ipbus_o => ipbrr(N_SLV_LGCCLK),
+ ipbus_o => ipbrr(N_SLV_LOGIC_CLOCKS),
strobe_8x_logic_o => strobe_8x_logic,
strobe_4x_logic_o => strobe_4x_logic,
DUT_clk_o => open,
@@ -532,8 +536,8 @@ begin
edge_falling_o => s_edge_falling,
ipbus_clk_i => clk_ipb,
ipbus_reset_i => rst_ipb,
- ipbus_i => ipbww(N_SLV_TRGIN),
- ipbus_o => ipbrr(N_SLV_TRGIN),
+ ipbus_i => ipbww(N_SLV_TRIGGERINPUTS),
+ ipbus_o => ipbrr(N_SLV_TRIGGERINPUTS),
clk_8x_logic_i => clk_8x_logic,
strobe_8x_logic_i => strobe_8x_logic
);
@@ -569,8 +573,8 @@ begin
edge_fall_i => s_edge_falling,
edge_rise_time_i => s_edge_rise_times,
edge_fall_time_i => s_edge_fall_times,
- ipbus_i => ipbww(N_SLV_EVFMT),
- ipbus_o => ipbrr(N_SLV_EVFMT),
+ ipbus_i => ipbww(N_SLV_EVENT_FORMATTER),
+ ipbus_o => ipbrr(N_SLV_EVENT_FORMATTER),
data_strobe_o => data_strobe,
event_data_o => event_data,
reset_timestamp_i => T0_o,
@@ -590,12 +594,12 @@ begin
data_strobe_i => data_strobe,
event_data_i => event_data,
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_EVBUF),
+ ipbus_i => ipbww(N_SLV_EVENTBUFFER),
ipbus_reset_i => rst_ipb,
strobe_4x_logic_i => strobe_4x_logic,
rst_fifo_o => rst_fifo_o,
buffer_full_o => buffer_full_o,
- ipbus_o => ipbrr(N_SLV_EVBUF),
+ ipbus_o => ipbrr(N_SLV_EVENTBUFFER),
logic_reset_i => logic_reset
);
@@ -603,12 +607,13 @@ begin
I8 : T0_Shutter_Iface
PORT MAP (
clk_4x_i => clk_4x_logic,
- clk_4x_strobe => strobe_4x_logic,
+ clk_4x_strobe_i => strobe_4x_logic,
+ accelerator_signals_i => triggers,
T0_o => T0_o,
shutter_o => s_shutter,
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_SHUT),
- ipbus_o => ipbrr(N_SLV_SHUT)
+ ipbus_i => ipbww(N_SLV_SHUTTER),
+ ipbus_o => ipbrr(N_SLV_SHUTTER)
);
------------------------------------------
@@ -625,9 +630,9 @@ begin
reset_or_clk_to_dut_i => T0_o,
shutter_to_dut_i => s_shutter,
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_DUT),
+ ipbus_i => ipbww(N_SLV_DUTINTERFACES),
ipbus_reset_i => rst_ipb,
- ipbus_o => ipbrr(N_SLV_DUT),
+ ipbus_o => ipbrr(N_SLV_DUTINTERFACES),
busy_from_dut => busy_i,
busy_to_dut => open,
clk_from_dut => dut_clk_i,
@@ -651,7 +656,7 @@ begin
PORT MAP (
clk_4x_logic_i => clk_4x_logic,
ipbus_clk_i => clk_ipb,
- ipbus_i => ipbww(N_SLV_TRGLGC),
+ ipbus_i => ipbww(N_SLV_TRIGGERLOGIC),
ipbus_reset_i => rst_ipb,
logic_reset_i => s_triggerLogic_reset,
logic_strobe_i => strobe_4x_logic,
@@ -661,7 +666,7 @@ begin
trigger_o => postVetotrigger,
trigger_times_o => postVetoTrigger_times,
event_number_o => trigger_count,
- ipbus_o => ipbrr(N_SLV_TRGLGC),
+ ipbus_o => ipbrr(N_SLV_TRIGGERLOGIC),
post_veto_trigger_o => overall_trigger,
pre_veto_trigger_o => OPEN,
trigger_active_o => leds(2)
diff --git a/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc b/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
index 14375021..f756f4ae 100644
--- a/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
+++ b/projects/TLU_v1e/firmware/ucf/I2C_constr.xdc
@@ -19,3 +19,5 @@ set_property PACKAGE_PIN P18 [get_ports i2c_sda_b]
+
+
diff --git a/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc b/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
index a83119b3..909d903c 100644
--- a/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
+++ b/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc
@@ -5,16 +5,16 @@
#set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
set_property IOSTANDARD LVDS_25 [get_ports {threshold_discr_n_i[*]}]
-set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
set_property PACKAGE_PIN A1 [get_ports {threshold_discr_n_i[0]}]
-set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
+set_property PACKAGE_PIN B1 [get_ports {threshold_discr_p_i[0]}]
set_property PACKAGE_PIN B4 [get_ports {threshold_discr_n_i[1]}]
-set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
+set_property PACKAGE_PIN C4 [get_ports {threshold_discr_p_i[1]}]
set_property PACKAGE_PIN K1 [get_ports {threshold_discr_n_i[2]}]
-set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
+set_property PACKAGE_PIN K2 [get_ports {threshold_discr_p_i[2]}]
set_property PACKAGE_PIN C5 [get_ports {threshold_discr_n_i[3]}]
-set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
+set_property PACKAGE_PIN C6 [get_ports {threshold_discr_p_i[3]}]
set_property PACKAGE_PIN H4 [get_ports {threshold_discr_n_i[4]}]
+set_property PACKAGE_PIN J4 [get_ports {threshold_discr_p_i[4]}]
set_property PACKAGE_PIN G1 [get_ports {threshold_discr_n_i[5]}]
set_property PACKAGE_PIN H1 [get_ports {threshold_discr_p_i[5]}]
@@ -107,10 +107,16 @@ create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_po
# What has gone wrong ....
# FIXME
#set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p pll_base_inst_n_2 s_clk160}
-set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p s_clk160}
+#set_clock_groups -asynchronous -group {sysclk clk_ipb_i} -group {sysclk_40_i_p s_clk160}
+#set_clock_groups -asynchronous -group { [get_nets sysclk] } -group { [get_nets *sysclk_40_i*]}
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 0.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+
+# -false_path
+
+set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks {sysclk clk_ipb_i}] -group [get_clocks -include_generated_clocks {s_clk160 sysclk_40_i_p}]
+
--
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