|
shift_reg | ( MASK_WIDTH downto 0 ) := ( others = > ' 0 ' ) |
| Asynchronous preload shift register holding '1's to be shifted out.
|
preload | ( MASK_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' ) |
| Mask register holding '1's to be shifted out.
|
vetoed_pulse | := ' 0 ' |
| input signal after internal veto
|
Q_R1 | := ' 0 ' |
| Output, input delayed by one clock. Used.
|
Q_R2 | := ' 0 ' |
| Output, input delayed by one clock. Used.
|
D_R1 | := ' 0 ' |
| Output, input delayed by one clock. Used.
|
Shift in zero at start of SReg.
Generate a shift register out of flip-flops. Unfortunately SRL16 , SRL32 don't have async. load.
Take output from end of SR.
Delay the output signal
The documentation for this class was generated from the following file:
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper_async_dtypes.vhdl