AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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rtl Architecture Reference

Processes

ipbus_write  ( ipbus_clk_i )
trigGen  ( clk_4x_logic_i )
 Produce triggers....
p_internal_triggers  ( clk_4x_logic_i )
p_trigger_counter  ( clk_4x_logic_i )

Signals

s_trigger_pattern  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )
 vector that stores trigger output for each combination of trigger inputs.
s_trigger_pattern_ipb  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )
s_external_trigger  std_logic := ' 0 '
s_internal_veto  std_logic := ' 0 '
s_internal_veto_ipb  std_logic := ' 0 '
s_internal_trigger_interval  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_pre_veto_trigger_counter  unsigned ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_post_veto_trigger_counter  unsigned ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_pre_veto_trigger_counter_ipb  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_post_veto_trigger_counter_ipb  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_internal_trigger  std_logic := ' 0 '
s_internal_trigger_timer  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_internal_trigger_timer_d  std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_internal_trigger_active  std_logic := ' 0 '
s_internal_trigger_active_ipb  std_logic := ' 0 '
s_ipbus_ack  std_logic := ' 0 '
s_pre_veto_trigger  std_logic := ' 0 '
s_post_veto_trigger  std_logic := ' 0 '

Instantiations

register_trigger_pattern  sync_reg <Entity sync_reg>
c_internal_triggers  work.internaltriggergenerator
register_pre_veto_trigs  sync_reg <Entity sync_reg>
register_post_veto_trigs  sync_reg <Entity sync_reg>

The documentation for this class was generated from the following files: