AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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dualSERDES_1to4 Entity Reference
Inheritance diagram for dualSERDES_1to4:

Entities

rtl  architecture
 goes low during calibration sequence. More...
 

Libraries

unisim 

Use Clauses

numeric_std 
vcomponents 

Ports

serdes_reset_i   in std_logic
 Starts recalibration sequence and resets the ISERDES.
data_i   in std_logic
fastClk_i   in std_logic
 4x fabric clock. e.g. 640MHz
fabricClk_i   in std_logic
 clock for output to FPGA. e.g. 160MHz
strobe_i   in std_logic
 Strobes once every 4 cycles of fastClk.
data_o   out std_logic_vector ( 7 downto 0 )
 --! Deserialized data. Interleaved between prompt and delayed serdes.
serdes_ready_o   out std_logic

Member Data Documentation

serdes_ready_o out std_logic
Port

data_o(0) is the oldest data


The documentation for this class was generated from the following file: