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fmc_tlu_sp601 Entity Reference
Inheritance diagram for fmc_tlu_sp601:
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Collaboration diagram for fmc_tlu_sp601:
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## Entities

rtl | architecture

## Libraries

UNISIM |
| Use library for instantiating Xilinx primitive components.

## Use Clauses

vcomponents |

## Ports

SYSCLK_N | in std_logic
| 200MHz crystal clock
SYSCLK_P | in std_logic
| 200MHz crystal clock
D | in std_logic
| pulse input
Q | out std_logic
| pulse_output
RST | in std_logic
| active high. Syncronous
pulse_length | in std_logic_vector ( 3 downto 0 )

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/fmc-tlu_sp601_pulse_shaper.vhdl