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arrivalTimeLUT Entity Reference
Inheritance diagram for arrivalTimeLUT:
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## Entities

rtl | architecture

## Use Clauses

numeric_std |

## Generics

g_NUM_FINE_BITS | positive := 3
g_NUM_COARSE_BITS | positive := 2

## Ports

clk_4x_logic_i | in std_logic
| Rising edge active.
strobe_4x_logic_i | in std_logic
| Pulses high once every 4 cycles of clk_4x_logic.
deserialized_data_i | in std_logic_vector ( 8 downto 0 )
first_rising_edge_time_o | out std_logic_vector ( g_NUM_FINE_BITS + g_NUM_COARSE_BITS - 1 downto 0 )
last_falling_edge_time_o | out std_logic_vector ( g_NUM_FINE_BITS + g_NUM_COARSE_BITS - 1 downto 0 )
rising_edge_o | out std_logic
falling_edge_o | out std_logic
multiple_edges_o | out std_logic

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/arrivalTimeLUT_rtl.vhd