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Behavioral Architecture Reference

## Processes

reg_out | ( hclk_i )

## Signals

s_Data_i_d_m | std_logic
s_Data_i_d_2m | std_logic
s_Data_i_d_s | std_logic
s_Data_i_d_2s | std_logic
s_Data_o | std_logic_vector ( 2 * g_S - 1 downto 0 )

## Instantiations

iodelay2_m | iodelay2
iodelay2_s | iodelay2
iserdes2_m | iserdes2
iserdes2_s | iserdes2

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/serdes_1_to_n_SDR.vhd