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triggerLogic Entity Reference
Inheritance diagram for triggerLogic:
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Collaboration diagram for triggerLogic:
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## Entities

rtl | architecture

## Use Clauses

numeric_std |
ipbus |

## Generics

g_NUM_INPUTS | positive := 4
g_IPBUS_WIDTH | positive := 32

## Ports

clk_4x_logic_i | in std_logic
ipbus_clk_i | in std_logic
ipbus_i | in ipb_wbus
ipbus_reset_i | in std_logic
logic_reset_i | in std_logic
logic_strobe_i | in std_logic
trigger_i | in std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
veto_i | in std_logic
event_number_o | out std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 )
ipbus_o | out ipb_rbus
post_veto_trigger_o | out std_logic
pre_veto_trigger_o | out std_logic
trigger_active_o | out std_logic
| Goes high when triggers are active ( ie. not veoted)

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/triggerLogic_rtl.vhd