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top_extphy Entity Reference
Inheritance diagram for top_extphy:
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Collaboration diagram for top_extphy:
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## Entities

rtl | architecture
struct | architecture

## Use Clauses

numeric_std |

## Generics

NUM_DUTS | positive := 3
NUM_TRIG_INPUTS | positive := 4
g_NUM_DUTS | positive := 3
g_NUM_TRIG_INPUTS | positive := 4
g_NUM_EXT_SLAVES | positive := 10
| Number of slaves outside IPBus interface.
g_EVENT_DATA_WIDTH | positive := 64
g_IPBUS_WIDTH | positive := 32
g_NUM_EDGE_INPUTS | positive := 4
g_SPILL_COUNTER_WIDTH | positive := 12

## Ports

busy_i | in std_logic_vector ( NUM_DUTS - 1 downto 0 )
cfd_discr_i | in std_logic_vector ( NUM_TRIG_INPUTS - 1 downto 0 )
dut_clk | in std_logic_vector ( NUM_DUTS - 1 downto 0 )
gmii_rx_clk_i | in std_logic
gmii_rx_dv_i | in std_logic
gmii_rx_er_i | in std_logic
gmii_rxd_i | in std_logic_vector ( 7 downto 0 )
sysclk_n_i | in std_logic
| 200 MHz xtal clock
sysclk_p_i | in std_logic
threshold_discr_i | in std_logic_vector ( NUM_TRIG_INPUTS - 1 downto 0 )
gmii_gtx_clk_o | out std_logic
gmii_tx_en_o | out std_logic
gmii_tx_er_o | out std_logic
gmii_txd_o | out std_logic_vector ( 7 downto 0 )
i2c_scl_o | out std_logic
leds_o | out std_logic_vector ( 3 downto 0 )
phy_rstb_o | out std_logic
reset_or_clk_o | out std_logic_vector ( NUM_DUTS - 1 downto 0 )
triggers_o | out std_logic_vector ( NUM_DUTS - 1 downto 0 )
i2c_sda_d | inout std_logic
busy_n_i | in std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
busy_p_i | in std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
| Busy lines from DUTs ( active high )
cfd_discr_n_i | in std_logic_vector ( g_NUM_TRIG_INPUTS - 1 downto 0 )
cfd_discr_p_i | in std_logic_vector ( g_NUM_TRIG_INPUTS - 1 downto 0 )
dip_switch_i | in std_logic_vector ( 3 downto 0 )
dut_clk_n_i | in std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
dut_clk_p_i | in std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
threshold_discr_n_i | in std_logic_vector ( g_NUM_TRIG_INPUTS - 1 downto 0 )
threshold_discr_p_i | in std_logic_vector ( g_NUM_TRIG_INPUTS - 1 downto 0 )
gpio_hdr | out std_logic_vector ( 7 downto 0 )
reset_or_clk_n_o | out std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
reset_or_clk_p_o | out std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
triggers_n_o | out std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
triggers_p_o | out std_logic_vector ( g_NUM_DUTS - 1 downto 0 )
| Trigger lines to DUT.
extclk_n_b | inout std_logic
extclk_p_b | inout std_logic
| either external clock in, or a clock being driven out
i2c_scl_b | inout std_logic
i2c_sda_b | inout std_logic

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_rtl.vhd
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd