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rtl Architecture Reference

goes low during calibration sequence. More...

## Processes

statereg | ( fabricClk_i , serdes_reset_i )
| Calibration start condition.
fsm | ( pres_state , s_calibration , s_busy_idelay_m )
| Calibration FSM register.
reg_out | ( fabricClk_i )

## Constants

c_S | positive := 4

## Types

state_values | is ( st0 , st1 , st2 , st3 , st4 )
| Calibration FSM state values.

## Signals

s_Data_i_d_p | std_logic
s_Data_i_d_d | std_logic
s_busy_idelay_m | std_logic
s_busy_idelay_s | std_logic
s_data_o | std_logic_vector ( 7 downto 0 )
| Deserialized data.
s_rst | std_logic := ' 0 '
s_cal_FSM | std_logic := ' 0 '
| Take high to calibrate the IDELAY components.
s_rst_FSM | std_logic := ' 0 '
s_initial_cal | std_logic := ' 1 '
s_calibration | std_logic := ' 0 '
pres_state | state_values := st0
next_state | state_values := st0

## Instantiations

iodelay2_prompt | iodelay2
| Calibration FSM combinational block.
iodelay2_delayed | iodelay2
iserdes2_prompt | iserdes2
iserdes2_delayed | iserdes2

## Detailed Description

goes low during calibration sequence.

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/dualSERDES_1to4_rtl.vhd