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Firmware for AIDA miniTLU

Uses the "IPBus" system to communuicate via Ethernet to host.

Needs Xilinx ISE tools to build. The scripts assume ISE 14.6 or newer.

Needs a licence for the Xilinx Gigabit ethernet soft core ( tri_mode_eth_mac ) if using an external Physical interface chip (e.g. for "Copper" Ethernet interface).

Needs "IPBus" to communuicate via Ethernet to host.

Scripts developed on a Linux PC. Need to use custom scripts because the standard Xilinx auto-generated ones "contaminate" directories that are under version-management control with files generated by core regeneration process.

Firmware build scripts may work under Windows/Cygwin or Windows/MinGW but not tested.

To build firmware:

1. Install Xilinx ISE 14.6 (or newer) and set up the environment variables.
2. Create a working directory somewhere , <working_directory>

3.      cd <working_directory>

4. Get a copy of the build scripts:

   -      svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/setup_workspace.sh > setup_workspace.sh

   -      svn cat http://svn.ohwr.org/fmc-mtlu/branches/dgc_scripted_build_ipbus2/firmware/scripts/build_bitstream.sh > build_bitstream.sh

   - Edit setup_workspace.sh to reflect which FPGA carrier board you want to build the firmware for.Currently supported boards: Xilinx SP601 , Xilinx SP605 . Default is SP601
5. Execute the script to set-up the ISE project:

        sh setup_workspace.sh

   This will check out copies of the IPBus and AIDA mini-TLU repositories, create a directory for the files produced by firmware synthesise and create a Xilinx ISE project file.
6. Produce the bit-stream
   - either:
   - - Open the Xilinx project file at <working_directory>/workspace/fmc-mtlu.xise
   - - Select Tools->COREGEN
   - - When Coregen starts select Project->Upgrade and Regenerate all project IP ( this will take several minutes )
   - - Make sure the top-level file is selected and click on "Generate Programming File"
   - or:
   - - Execute the build_bitstream.sh script.