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clocks_s6_extphy Entity Reference
Inheritance diagram for clocks_s6_extphy:
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## Entities

rtl | architecture

## Libraries

unisim |

## Use Clauses

VComponents |

## Ports

sysclk_p | in std_logic
sysclk_n | in std_logic
clk_logic_xtal_o | out std_logic
clko_125 | out std_logic
clko_ipb | out std_logic
locked | out std_logic
rsto_125 | out std_logic
rsto_ipb | out std_logic
onehz | out std_logic

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/clocks_s6_extphy.vhd
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/clocks_s6_extphy.vhd