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sync_reg Entity Reference
Inheritance diagram for sync_reg:
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Collaboration diagram for sync_reg:
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## Entities

Behavioral | architecture

## Generics

g_Data_width | positive := 32

## Ports

clk_i | in std_logic
| synchronous clock
Async_i | in std_logic_vector ( g_Data_width - 1 downto 0 )
| Asynchronous input data.
Sync_o | out std_logic_vector ( g_Data_width - 1 downto 0 )
| Synchronous output data.

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/sync_reg.vhd