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rtl Architecture Reference

## Processes

ipbus_write | ( ipbus_clk_i )
| Generate FIFO read enable.

## Signals

s_wr_data_count | std_logic_vector ( g_WRITE_COUNTER_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
| Counters for input and ouput to/from FIFO.
s_wr_data_count_reg | std_logic_vector ( g_WRITE_COUNTER_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_rd_data_count | std_logic_vector ( g_READ_COUNTER_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_fifo_fill_level | unsigned ( g_READ_COUNTER_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_write_strobe | std_logic := ' 0 '
s_rst_fifo | std_logic := ' 0 '
s_fifo_prog_full | std_logic := ' 0 '
s_fifo_rd_en | std_logic := ' 0 '
s_fifo_dout | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 )
s_fifo_valid | std_logic := ' 1 '
s_fifo_full | std_logic := ' 0 '
s_fifo_almost_full | std_logic := ' 0 '
s_fifo_empty | std_logic := ' 0 '
s_fifo_almost_empty | std_logic := ' 0 '

## Instantiations

event_fifo | work.tlu_event_fifo
| Multiplex output data.
register_counter_inst | registerCounter <Entity registerCounter>

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/eventBuffer_rtl.vhd