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Behavioral Architecture Reference

## Signals

s_async_i | std_logic_vector ( g_Data_width - 1 downto 0 )
s_sync_o | std_logic_vector ( g_Data_width - 1 downto 0 )

## Instantiations

reg | Reg_2clks <Entity Reg_2clks>

## Detailed Description

Synchronize words (n bits)of data

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/sync_reg.vhd