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top_extphy Member List

This is the complete list of members for top_extphy, including all inherited members.

Async_i | sync_reg | Port
async_i | Reg_2clks | Port
buffer_full_o | eventBuffer | Port
busy_from_dut_n_i (defined in DUTInterfaces) | DUTInterfaces | Port
busy_from_dut_p_i (defined in DUTInterfaces) | DUTInterfaces | Port
busy_i (defined in top_extphy) | top_extphy | Port
busy_n_i (defined in top_extphy) | top_extphy | Port
busy_p_i | top_extphy | Port
cfd_discr_i (defined in top_extphy) | top_extphy | Port
cfd_discr_n_i (defined in top_extphy) | top_extphy | Port
cfd_discr_p_i (defined in top_extphy) | top_extphy | Port
clk_16x_logic_i | triggerInputs | Port
clk_16x_logic_o (defined in logic_clocks) | logic_clocks | Port
clk_4x_logic (defined in triggerInputs) | triggerInputs | Port
clk_4x_logic_i (defined in DUTInterfaces) | DUTInterfaces | Port
clk_4x_logic_i (defined in eventBuffer) | eventBuffer | Port
clk_4x_logic_i (defined in eventFormatter) | eventFormatter | Port
triggerInputs.clk_4x_logic_i | arrivalTimeLUT | Port
clk_4x_logic_i (defined in triggerLogic) | triggerLogic | Port
clk_4x_logic_o (defined in logic_clocks) | logic_clocks | Port
clk_from_dut_n_i (defined in DUTInterfaces) | DUTInterfaces | Port
clk_from_dut_p_i (defined in DUTInterfaces) | DUTInterfaces | Port
clk_i | sync_reg | Port
clk_input_i (defined in registerCounter) | registerCounter | Port
clk_logic_o (defined in logic_clocks) | logic_clocks | Port
clk_logic_xtal_i (defined in logic_clocks) | logic_clocks | Port
clk_logic_xtal_o (defined in IPBusInterface) | IPBusInterface | Port
clk_output_i (defined in registerCounter) | registerCounter | Port
clko_125 (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
clko_ipb (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
clocks_locked_o (defined in IPBusInterface) | IPBusInterface | Port
data_i (defined in registerCounter) | registerCounter | Port
data_i (defined in dualSERDES_1to4) | dualSERDES_1to4 | Port
data_o (defined in registerCounter) | registerCounter | Port
triggerInputs.data_o | dualSERDES_1to4 | Port
data_strobe_i (defined in eventBuffer) | eventBuffer | Port
data_strobe_o (defined in eventFormatter) | eventFormatter | Port
deserialized_data_i (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
dip_switch_i (defined in top_extphy) | top_extphy | Port
dut_clk (defined in top_extphy) | top_extphy | Port
dut_clk_n_i (defined in top_extphy) | top_extphy | Port
dut_clk_p_i (defined in top_extphy) | top_extphy | Port
edge_fall_i (defined in eventFormatter) | eventFormatter | Port
edge_fall_time_i (defined in eventFormatter) | eventFormatter | Port
edge_falling_o (defined in triggerInputs) | triggerInputs | Port
edge_falling_times_o (defined in triggerInputs) | triggerInputs | Port
edge_rise_i (defined in eventFormatter) | eventFormatter | Port
edge_rise_time_i (defined in eventFormatter) | eventFormatter | Port
edge_rising_o (defined in triggerInputs) | triggerInputs | Port
edge_rising_times_o (defined in triggerInputs) | triggerInputs | Port
emac_hostbus_decl (defined in IPBusInterface) | IPBusInterface | use clause
event_data_i (defined in eventBuffer) | eventBuffer | Port
event_data_o (defined in eventFormatter) | eventFormatter | Port
event_number_i (defined in eventFormatter) | eventFormatter | Port
event_number_o (defined in triggerLogic) | triggerLogic | Port
extclk_n_b (defined in top_extphy) | top_extphy | Port
extclk_p_b | top_extphy | Port
fabricClk_i | dualSERDES_1to4 | Port
falling_edge_o (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
fastClk_i | dualSERDES_1to4 | Port
first_rising_edge_time_o (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
fmcTLU (defined in eventFormatter) | eventFormatter | use clause
fmcTLU (defined in triggerInputs) | triggerInputs | use clause
g_COUNTER_TRIG_WIDTH (defined in eventFormatter) | eventFormatter | Generic
g_COUNTER_WIDTH (defined in eventFormatter) | eventFormatter | Generic
g_Data_width (defined in sync_reg) | sync_reg | Generic
g_DATA_WIDTH (defined in registerCounter) | registerCounter | Generic
g_EVENT_DATA_WIDTH (defined in top_extphy) | top_extphy | Generic
g_EVTTYPE_WIDTH (defined in eventFormatter) | eventFormatter | Generic
g_IPBUS_WIDTH (defined in top_extphy) | top_extphy | Generic
g_NUM_COARSE_BITS (defined in arrivalTimeLUT) | arrivalTimeLUT | Generic
g_NUM_DUTS (defined in top_extphy) | top_extphy | Generic
g_NUM_EDGE_INPUTS (defined in top_extphy) | top_extphy | Generic
g_NUM_EXT_SLAVES | top_extphy | Generic
g_NUM_FINE_BITS (defined in arrivalTimeLUT) | arrivalTimeLUT | Generic
g_NUM_INPUTS (defined in triggerInputs) | triggerInputs | Generic
g_NUM_INPUTS (defined in triggerLogic) | triggerLogic | Generic
g_NUM_TRIG_INPUTS (defined in top_extphy) | top_extphy | Generic
g_READ_COUNTER_WIDTH (defined in eventBuffer) | eventBuffer | Generic
g_SPILL_COUNTER_WIDTH (defined in top_extphy) | top_extphy | Generic
g_WRITE_COUNTER_WIDTH (defined in eventBuffer) | eventBuffer | Generic
gmii_gtx_clk_o (defined in top_extphy) | top_extphy | Port
gmii_rx_clk_i (defined in top_extphy) | top_extphy | Port
gmii_rx_dv_i (defined in top_extphy) | top_extphy | Port
gmii_rx_er_i (defined in top_extphy) | top_extphy | Port
gmii_rxd_i (defined in top_extphy) | top_extphy | Port
gmii_tx_en_o (defined in top_extphy) | top_extphy | Port
gmii_tx_er_o (defined in top_extphy) | top_extphy | Port
gmii_txd_o (defined in top_extphy) | top_extphy | Port
gpio_hdr (defined in top_extphy) | top_extphy | Port
i2c_scl_b (defined in top_extphy) | top_extphy | Port
i2c_scl_enb_o (defined in i2c_master) | i2c_master | Port
i2c_scl_i (defined in i2c_master) | i2c_master | Port
i2c_scl_o (defined in top_extphy) | top_extphy | Port
i2c_sda_b (defined in top_extphy) | top_extphy | Port
i2c_sda_d (defined in top_extphy) | top_extphy | Port
i2c_sda_enb_o (defined in i2c_master) | i2c_master | Port
i2c_sda_i (defined in i2c_master) | i2c_master | Port
ipb_clk_o (defined in IPBusInterface) | IPBusInterface | Port
ipb_rst_o (defined in IPBusInterface) | IPBusInterface | Port
ipbr_i (defined in IPBusInterface) | IPBusInterface | Port
ipbus (defined in DUTInterfaces) | DUTInterfaces | use clause
ipbus (defined in IPBusInterface) | IPBusInterface | use clause
ipbus (defined in eventBuffer) | eventBuffer | use clause
ipbus (defined in eventFormatter) | eventFormatter | use clause
ipbus (defined in i2c_master) | i2c_master | use clause
ipbus (defined in logic_clocks) | logic_clocks | use clause
ipbus (defined in triggerInputs) | triggerInputs | use clause
ipbus (defined in triggerLogic) | triggerLogic | use clause
ipbus_clk_i (defined in DUTInterfaces) | DUTInterfaces | Port
ipbus_clk_i (defined in eventBuffer) | eventBuffer | Port
ipbus_clk_i (defined in eventFormatter) | eventFormatter | Port
ipbus_clk_i (defined in i2c_master) | i2c_master | Port
ipbus_clk_i (defined in logic_clocks) | logic_clocks | Port
ipbus_clk_i (defined in triggerInputs) | triggerInputs | Port
ipbus_clk_i (defined in triggerLogic) | triggerLogic | Port
ipbus_i (defined in DUTInterfaces) | DUTInterfaces | Port
ipbus_i (defined in eventBuffer) | eventBuffer | Port
ipbus_i (defined in eventFormatter) | eventFormatter | Port
ipbus_i (defined in i2c_master) | i2c_master | Port
ipbus_i (defined in logic_clocks) | logic_clocks | Port
ipbus_i (defined in triggerInputs) | triggerInputs | Port
ipbus_i (defined in triggerLogic) | triggerLogic | Port
ipbus_in (defined in ipbus_ver) | ipbus_ver | Port
ipbus_o (defined in DUTInterfaces) | DUTInterfaces | Port
ipbus_o (defined in eventBuffer) | eventBuffer | Port
ipbus_o (defined in eventFormatter) | eventFormatter | Port
ipbus_o (defined in i2c_master) | i2c_master | Port
ipbus_o (defined in logic_clocks) | logic_clocks | Port
ipbus_o (defined in triggerInputs) | triggerInputs | Port
ipbus_o (defined in triggerLogic) | triggerLogic | Port
ipbus_out (defined in ipbus_ver) | ipbus_ver | Port
ipbus_reset_i (defined in DUTInterfaces) | DUTInterfaces | Port
ipbus_reset_i (defined in eventBuffer) | eventBuffer | Port
ipbus_reset_i (defined in i2c_master) | i2c_master | Port
ipbus_reset_i (defined in logic_clocks) | logic_clocks | Port
ipbus_reset_i (defined in triggerInputs) | triggerInputs | Port
ipbus_reset_i (defined in triggerLogic) | triggerLogic | Port
ipbw_o (defined in IPBusInterface) | IPBusInterface | Port
last_falling_edge_time_o (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
leds_o (defined in top_extphy) | top_extphy | Port
locked (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
logic_clocks_locked_o (defined in logic_clocks) | logic_clocks | Port
logic_reset_i (defined in eventBuffer) | eventBuffer | Port
logic_reset_i (defined in eventFormatter) | eventFormatter | Port
logic_reset_i (defined in triggerLogic) | triggerLogic | Port
logic_reset_o (defined in logic_clocks) | logic_clocks | Port
logic_strobe_i (defined in eventFormatter) | eventFormatter | Port
logic_strobe_i (defined in triggerLogic) | triggerLogic | Port
multiple_edges_o (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
NUM_DUTS (defined in top_extphy) | top_extphy | Generic
NUM_EXT_SLAVES (defined in IPBusInterface) | IPBusInterface | Generic
NUM_TRIG_INPUTS (defined in top_extphy) | top_extphy | Generic
numeric_std (defined in top_extphy) | top_extphy | use clause
onehz (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
onehz_o (defined in IPBusInterface) | IPBusInterface | Port
phy_rstb_o (defined in top_extphy) | top_extphy | Port
post_veto_trigger_o (defined in triggerLogic) | triggerLogic | Port
pre_veto_trigger_o (defined in triggerLogic) | triggerLogic | Port
Reset_i (defined in logic_clocks) | logic_clocks | Port
reset_or_clk_n_o (defined in top_extphy) | top_extphy | Port
reset_or_clk_o (defined in top_extphy) | top_extphy | Port
reset_or_clk_p_o (defined in top_extphy) | top_extphy | Port
reset_or_clk_to_dut_n_o (defined in DUTInterfaces) | DUTInterfaces | Port
reset_or_clk_to_dut_p_o (defined in DUTInterfaces) | DUTInterfaces | Port
rising_edge_o (defined in arrivalTimeLUT) | arrivalTimeLUT | Port
rsto_125 (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
rsto_ipb (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
serdes_ready_o | dualSERDES_1to4 | Port
serdes_reset_i | dualSERDES_1to4 | Port
shutter_cnt_i (defined in eventFormatter) | eventFormatter | Port
shutter_i (defined in eventFormatter) | eventFormatter | Port
spill_cnt_i (defined in eventFormatter) | eventFormatter | Port
spill_i (defined in eventFormatter) | eventFormatter | Port
strobe_16x_logic_i | triggerInputs | Port
strobe_16x_logic_o (defined in logic_clocks) | logic_clocks | Port
strobe_4x_logic_i (defined in DUTInterfaces) | DUTInterfaces | Port
strobe_4x_logic_i (defined in eventBuffer) | eventBuffer | Port
strobe_4x_logic_i (defined in triggerInputs) | triggerInputs | Port
strobe_4x_logic_o (defined in logic_clocks) | logic_clocks | Port
strobe_i | dualSERDES_1to4 | Port
Sync_o | sync_reg | Port
sync_o | Reg_2clks | Port
sysclk_n (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
sysclk_n_i | top_extphy | Port
sysclk_p (defined in clocks_s6_extphy) | clocks_s6_extphy | Port
sysclk_p_i (defined in top_extphy) | top_extphy | Port
threshold_discr_i (defined in top_extphy) | top_extphy | Port
threshold_discr_n_i (defined in top_extphy) | top_extphy | Port
threshold_discr_p_i (defined in top_extphy) | top_extphy | Port
trigger_active_o | triggerLogic | Port
trigger_cnt_i (defined in eventFormatter) | eventFormatter | Port
trigger_count_i | eventBuffer | Port
trigger_count_o (defined in eventFormatter) | eventFormatter | Port
trigger_counter_i (defined in DUTInterfaces) | DUTInterfaces | Port
trigger_debug_o (defined in triggerInputs) | triggerInputs | Port
trigger_i (defined in DUTInterfaces) | DUTInterfaces | Port
eventFormatter.trigger_i | eventFormatter | Port
trigger_i (defined in triggerLogic) | triggerLogic | Port
trigger_inputs_fired_i (defined in eventFormatter) | eventFormatter | Port
trigger_o (defined in triggerInputs) | triggerInputs | Port
trigger_times_i (defined in eventFormatter) | eventFormatter | Port
trigger_times_o (defined in triggerInputs) | triggerInputs | Port
trigger_to_dut_n_o (defined in DUTInterfaces) | DUTInterfaces | Port
trigger_to_dut_p_o (defined in DUTInterfaces) | DUTInterfaces | Port
triggers_n_o (defined in top_extphy) | top_extphy | Port
triggers_o (defined in top_extphy) | top_extphy | Port
triggers_p_o | top_extphy | Port
unisim (defined in DUTInterfaces) | DUTInterfaces | Library
unisim (defined in clocks_s6_extphy) | clocks_s6_extphy | Library
unisim (defined in logic_clocks) | logic_clocks | Library
unisim (defined in triggerInputs) | triggerInputs | Library
vcomponents (defined in logic_clocks) | logic_clocks | use clause
vcomponents (defined in triggerInputs) | triggerInputs | use clause
VComponents (defined in DUTInterfaces) | DUTInterfaces | use clause
VComponents (defined in clocks_s6_extphy) | clocks_s6_extphy | use clause
veto_i (defined in triggerLogic) | triggerLogic | Port
veto_o (defined in DUTInterfaces) | DUTInterfaces | Port