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Reg_2clks Entity Reference
Inheritance diagram for Reg_2clks:
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## Entities

Behavioral | architecture

## Ports

clk_i | in std_logic
| Synchronous clock.
async_i | in std_logic
| Asynchronous input data.
sync_o | out std_logic
| Synchronous output data.

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/Reg_2clks.vhd