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pulse_shaper_async_dtypes Entity Reference
Inheritance diagram for pulse_shaper_async_dtypes:
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Collaboration diagram for pulse_shaper_async_dtypes:
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## Entities

rtl | architecture

## Generics

MASK_WIDTH | integer := 16
| Width of shift register and hence maximum width of pulse.

## Ports

D | in std_logic
| Input pulse.
Q | out std_logic
| output pulse
CLK | in std_logic
| Clock , rising edge active.
PULSE_MASK | in std_logic_vector ( MASK_WIDTH - 1 downto 0 )

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper_async_dtypes.vhdl