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logic_clocks Entity Reference
Inheritance diagram for logic_clocks:
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## Entities

rtl | architecture

## Libraries

unisim |

## Use Clauses

numeric_std |
ipbus |
vcomponents |

## Ports

ipbus_clk_i | in std_logic
ipbus_i | in ipb_wbus
ipbus_reset_i | in std_logic
Reset_i | in std_logic
clk_logic_xtal_i | in std_logic
clk_16x_logic_o | out std_logic
clk_4x_logic_o | out std_logic
ipbus_o | out ipb_rbus
strobe_16x_logic_o | out std_logic
strobe_4x_logic_o | out std_logic
extclk_p_b | inout std_logic
extclk_n_b | inout std_logic
clk_logic_o | out std_logic
logic_clocks_locked_o | out std_logic
logic_reset_o | out std_logic

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/logic_clocks_rtl.vhd