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pulseClockDomainCrossing Entity Reference

## Entities

rtl | architecture

## Ports

clk_input_i | in std_logic
| clock for input
pulse_i | in std_logic
| input pulse. Active high
clk_output_i | in std_logic
| clock for output
pulse_o | out std_logic
| Single cycle pulse synchronized to clock_output_i.

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd