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rtl Architecture Reference

## Processes

PROCESS_0 | ( sysclk )
PROCESS_1 | ( clk_ipb_b )
PROCESS_2 | ( clk_125_b )
PROCESS_4 | ( sysclk )
PROCESS_5 | ( clk_ipb_b )
PROCESS_6 | ( clk_125_b )

## Components

clock_divider_s6 |

## Signals

clk_ipb_i | std_logic
clk_ipb_b | std_logic
clk_125_i | std_logic
clk_125_b | std_logic
sysclk | std_logic
sysclk_in | std_logic
d25 | std_logic
d25_d | std_logic
dcm_locked | std_logic
rst | std_logic := ' 1 '
s_xtal_dcm_locked | std_logic
s_clk_logic_xtal | std_logic

## Instantiations

ibufgds0 | ibufgds
bufg_125 | bufg
bufg_ipb | bufg
bufg_clk_logic_xtal | bufg
dcm0 | dcm_clkgen
clkdiv | clock_divider_s6
sys40_gen | bufio2
ibufgds0 | ibufgds
bufg_125 | bufg
bufg_ipb | bufg
dcm0 | dcm_clkgen
clkdiv | clock_divider_s6

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/clocks_s6_extphy.vhd
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/clocks_s6_extphy.vhd