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rtl Architecture Reference

## Components

dtype_fdpe | <Entity dtype_fdpe>
| Output.

## Signals

shift_reg | std_logic_vector ( MASK_WIDTH downto 0 ) := ( others = > ' 0 ' )
| Asynchronous preload shift register holding '1's to be shifted out.
preload | std_logic_vector ( MASK_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
| Mask register holding '1's to be shifted out.
vetoed_pulse | std_logic := ' 0 '
| input signal after internal veto
Q_R1 | std_logic := ' 0 '
| Output, input delayed by one clock. Used.
Q_R2 | std_logic := ' 0 '
| Output, input delayed by one clock. Used.
D_R1 | std_logic := ' 0 '
| Output, input delayed by one clock. Used.

## Instantiations

dtype | dtype_fdpe <Entity dtype_fdpe>
| Shift in zero at start of SReg.
q_reg | dtype_fdpe <Entity dtype_fdpe>
| Take output from end of SR.
d_reg | dtype_fdpe <Entity dtype_fdpe>
| Delay the input signal.

## Member Data Documentation

dtype dtype_fdpe

Instantiation

Shift in zero at start of SReg.

Generate a shift register out of flip-flops. Unfortunately SRL16 , SRL32 don't have async. load.

q_reg dtype_fdpe

Instantiation

Take output from end of SR.

Delay the output signal

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper_async_dtypes.vhdl