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rtl Architecture Reference

## Components

dtype_fdpe | <Entity dtype_fdpe>
| Output.
dtype_fd | <Entity dtype_fd>
| Asynchronous preload.
dtype_fds | <Entity dtype_fds>
| Input.
dtype_fdr | <Entity dtype_fdr>
| Input.

## Signals

s_vetoed_pulse_a | std_logic := ' 0 '
| Input input signal after internal veto.
s_async_pulse_a | std_logic := ' 0 '
s_srl_ce | std_logic := ' 0 '
s_srl_d | std_logic := ' 0 '
s_srl_q | std_logic := ' 0 '
s_Q_d1 | std_logic := ' 0 '
| Output, delayed by one clock. Used to form veto.
s_Q_d2 | std_logic := ' 0 '
| Output, delayed by one clock. Used to form veto.
s_Q_d3 | std_logic := ' 0 '
| Output, delayed by one clock. Used to form veto.
s_D_d1 | std_logic := ' 0 '
| Input, delayed by one clock. Used to form veto.
s_D_d2 | std_logic := ' 0 '
| Input, delayed by one clock. Used to form veto.

## Instantiations

srl16e_inst | srl16e
| Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST.
async_reg | dtype_fdpe <Entity dtype_fdpe>
| Clock in zero when shift reg. spits out a '1'.
q_reg1 | dtype_fdr <Entity dtype_fdr>
| Delay the output signal.
q_reg2 | dtype_fds <Entity dtype_fds>
| Delay the output signal.
q_reg3 | dtype_fdr <Entity dtype_fdr>
| Delay the output signal.
d_reg1 | dtype_fd <Entity dtype_fd>
| Delay the input.
d_reg2 | dtype_fds <Entity dtype_fds>
| Delay the input.

## Member Data Documentation

async_reg dtype_fdpe

Instantiation

Clock in zero when shift reg. spits out a '1'.

In order for a pulse to get to the PREset input, the output must be low and the input must be low. Goes low on RST high

q_reg2 dtype_fds

Instantiation

Delay the output signal.

Take high on reset.

q_reg3 dtype_fdr

Instantiation

Delay the output signal.

Take low on reset

srl16e_inst srl16e

Instantiation

Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST.

Clock the SRL if the output is high ( or if the output of the SRL is high.... )

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper.vhdl