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dtype_fdr Entity Reference

Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop. More...

Inheritance diagram for dtype_fdr:
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## Entities

rtl | architecture

## Ports

Q | out std_logic
| Output.
CLK | in std_logic
| Clock - rising edge active.
RST | in std_logic
| Active high, synchronous.
D | in STD_LOGIC
| Input.

## Detailed Description

Aims to be the same as the Xilinx "FD" primitive - D-Type flip-flop.

## Member Data Documentation

Q out std_logic

Port

Output.

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The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/dtype_fdr.vhdl