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struct Architecture Reference

## Libraries

work |
unisim |

## Use Clauses

numeric_std |
ipbus |
emac_hostbus_decl |
fmcTLU | Package <fmcTLU>
vcomponents |

## Components

DUTInterfaces | <Entity DUTInterfaces>
IPBusInterface | <Entity IPBusInterface>
eventBuffer | <Entity eventBuffer>
| Not yet used.
eventFormatter | <Entity eventFormatter>
| Goes high when event buffer almost full.
i2c_master | <Entity i2c_master>
| goes high TO load trigger data. One cycle of clk_4x_logic
logic_clocks | <Entity logic_clocks>
triggerInputs | <Entity triggerInputs>
| 640MHz clock ( 16x 40MHz )
triggerLogic | <Entity triggerLogic>
| Pulses one cycle every 4 of 16x clock.

## Signals

buffer_full_o | std_logic
| Goes high when event buffer almost full.
clk_16x_logic | std_logic
clk_4x_logic | std_logic
| normally 160MHz
clk_logic_xtal | std_logic
data_strobe | std_logic
edge_fall_i | std_logic_vector ( g_NUM_EDGE_INPUTS - 1 downto 0 )
edge_fall_time_i | t_triggerTimeArray ( g_NUM_EDGE_INPUTS - 1 downto 0 )
edge_rise_i | std_logic_vector ( g_NUM_EDGE_INPUTS - 1 downto 0 )
edge_rise_time_i | t_triggerTimeArray ( g_NUM_EDGE_INPUTS - 1 downto 0 )
event_data | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 )
event_number_o | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 )
ipbr | ipb_rbus_array ( g_NUM_EXT_SLAVES - 1 downto 0 )
| IPBus read signals.
ipbus_clk | std_logic
ipbus_clk_i | std_logic
ipbus_reset | std_logic
ipbus_rst | std_logic
ipbw | ipb_wbus_array ( g_NUM_EXT_SLAVES - 1 downto 0 )
| IBus write signals.
logic_clocks_reset | std_logic
logic_reset | std_logic
overall_trigger | std_logic
| goes high to load trigger data
overall_veto | std_logic
| Halts triggers when high.
s_i2c_scl_enb | std_logic
s_i2c_sda_enb | std_logic
shutter_cnt_i | std_logic_vector ( g_SPILL_COUNTER_WIDTH - 1 downto 0 )
shutter_i | std_logic
spill_cnt_i | std_logic_vector ( g_SPILL_COUNTER_WIDTH - 1 downto 0 )
spill_i | std_logic
strobe_16x_logic | std_logic
| Pulses one cycle every 4 of 16x clock.
strobe_4x_logic | std_logic
trigger_cnt_i | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 )
trigger_count | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 )
trigger_times | t_triggerTimeArray ( g_NUM_TRIG_INPUTS - 1 downto 0 )
triggers | std_logic_vector ( g_NUM_TRIG_INPUTS - 1 downto 0 )
veto_o | std_logic
| goes high when one or more DUT are busy

## Instantiations

i0 | DUTInterfaces <Entity DUTInterfaces>
| Goes high when triggers are active ( ie. not veoted)
i4 | IPBusInterface <Entity IPBusInterface>
i5 | eventBuffer <Entity eventBuffer>
i2 | eventFormatter <Entity eventFormatter>
i7 | i2c_master <Entity i2c_master>
i6 | logic_clocks <Entity logic_clocks>
i1 | triggerInputs <Entity triggerInputs>
i3 | triggerLogic <Entity triggerLogic>

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hdl/top_extphy_struct.vhd