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rtl Architecture Reference

## Processes

ipbus_write | ( ipbus_clk_i )
p_signals_clk_domain | ( clk_4x_logic_i )
p_reg | ( clk_4x_logic_i )
p_FIFO_rd | ( s_FIFO_empty )
p_timestamp | ( clk_4x_logic_i , logic_reset_i )

## Constants

c_NUM_INPUT_TYPES | positive := 3 + g_NUM_EDGE_INPUTS
c_COARSE_TIMESTAMP_WIDTH | positive := 48

## Types

t_fifo_io | is array ( natural range<> ) of std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 )
t_evttype | is array ( natural range<> ) of std_logic_vector ( g_EVTTYPE_WIDTH - 1 downto 0 )
t_var | is array ( natural range<> ) of std_logic_vector ( g_COUNTER_WIDTH - 1 downto 0 )

## Signals

s_event_strobe | std_logic := ' 0 '
| delayed strobes
s_event_strobe_d1 | std_logic := ' 0 '
s_event_strobe_d2 | std_logic := ' 0 '
s_event_strobe_d3 | std_logic := ' 0 '
shutter_i_d1 | std_logic := ' 0 '
shutter_i_d2 | std_logic := ' 0 '
edge_i_d1 | std_logic := ' 0 '
edge_i_d2 | std_logic := ' 0 '
spill_i_d1 | std_logic := ' 0 '
spill_i_d2 | std_logic := ' 0 '
s_evttype | t_evttype ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
s_var | t_var ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
s_FIFO_wr | std_logic_vector ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' )
s_FIFO_rd | std_logic_vector ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' )
s_FIFO_rd_d | std_logic_vector ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' )
s_FIFO_rd_mask | unsigned ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( 0 = > ' 1 ' , others = > ' 0 ' )
s_FIFO_empty | std_logic_vector ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' )
s_FIFO_i | t_fifo_io ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
s_FIFO_o | t_fifo_io ( 3 + g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) )
s_data_o | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 )
s_coarse_timestamp | unsigned ( c_COARSE_TIMESTAMP_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_word0 | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_word1 | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_word2 | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_word3 | std_logic_vector ( g_EVENT_DATA_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
s_ipbus_ack | std_logic := ' 0 '
s_enable_record | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( 2 downto 0 = > ' 1 ' , others = > ' 0 ' )
s_enable_record_ipb | std_logic_vector ( g_IPBUS_WIDTH - 1 downto 0 ) := ( 2 downto 0 = > ' 1 ' , others = > ' 0 ' )
s_enable_trigger | std_logic := ' 1 '
s_enable_shutter | std_logic := ' 1 '
s_enable_spill | std_logic := ' 1 '
s_enable_edges | std_logic_vector ( g_NUM_EDGE_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' )

## Instantiations

fifo_i | work.fifo
| If there is data in the FIFO output we put the strobe signal at high level.

## Member Data Documentation

fifo_i work.fifo

Instantiation

If there is data in the FIFO output we put the strobe signal at high level.

Could also output data on trigger_i , but let's use the delayed signals.
The counters are one cicle delayed from the signal generation

The documentation for this class was generated from the following files:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/eventFormatter_rtl.vhd