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registerCounter Entity Reference
Inheritance diagram for registerCounter:
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## Entities

rtl | architecture

## Generics

g_DATA_WIDTH | positive := 15

## Ports

clk_input_i | in std_logic
data_i | in std_logic_vector ( g_DATA_WIDTH - 1 downto 0 )
data_o | out std_logic_vector ( g_DATA_WIDTH - 1 downto 0 )
clk_output_i | in std_logic

The documentation for this class was generated from the following file:

- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/common/registerCounter_rtl.vhd