AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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triggerInputs Entity Reference
Inheritance diagram for triggerInputs:
Collaboration diagram for triggerInputs:

Entities

rtl  architecture
 

Libraries

unisim 

Use Clauses

numeric_std 
ipbus 
fmcTLU  Package <fmcTLU>
vcomponents 

Generics

g_NUM_INPUTS  natural := 1

Ports

cfd_discr_p_i   in std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
cfd_discr_n_i   in std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
clk_4x_logic   in std_logic
strobe_4x_logic_i   in std_logic
threshold_discr_p_i   in std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
threshold_discr_n_i   in std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
trigger_times_o   out t_triggerTimeArray ( g_NUM_INPUTS - 1 downto 0 )
trigger_o   out std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
trigger_debug_o   out std_logic_vector ( ( ( 2 * g_NUM_INPUTS ) - 1 ) downto 0 )
edge_rising_times_o   out t_triggerTimeArray ( g_NUM_INPUTS - 1 downto 0 )
edge_falling_times_o   out t_triggerTimeArray ( g_NUM_INPUTS - 1 downto 0 )
edge_rising_o   out std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
edge_falling_o   out std_logic_vector ( g_NUM_INPUTS - 1 downto 0 )
ipbus_clk_i   in std_logic
ipbus_reset_i   in std_logic
ipbus_i   in ipb_wbus
ipbus_o   out ipb_rbus
clk_16x_logic_i   in std_logic
 640MHz clock ( 16x 40MHz )
strobe_16x_logic_i   in std_logic
 Pulses one cycle every 4 of 16x clock.

The documentation for this class was generated from the following file: