|
s_vetoed_pulse_a | := ' 0 ' |
| Input input signal after internal veto.
|
s_async_pulse_a | := ' 0 ' |
s_srl_ce | := ' 0 ' |
s_srl_d | := ' 0 ' |
s_srl_q | := ' 0 ' |
s_Q_d1 | := ' 0 ' |
| Output, delayed by one clock. Used to form veto.
|
s_Q_d2 | := ' 0 ' |
| Output, delayed by one clock. Used to form veto.
|
s_Q_d3 | := ' 0 ' |
| Output, delayed by one clock. Used to form veto.
|
s_D_d1 | := ' 0 ' |
| Input, delayed by one clock. Used to form veto.
|
s_D_d2 | := ' 0 ' |
| Input, delayed by one clock. Used to form veto.
|
Clock in zero when shift reg. spits out a '1'.
In order for a pulse to get to the PREset input, the output must be low and the input must be low. Goes low on RST high
Delay the output signal.
Take high on reset.
Delay the output signal.
Take low on reset
Input to SRL16 pulses high for one cycle on rising edge. Goes high on RST.
Clock the SRL if the output is high ( or if the output of the SRL is high.... )
The documentation for this class was generated from the following file:
- /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/firmware/hdl/test/pulse_shaper.vhdl