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AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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Processes | |
ipbus_write | ( ipbus_clk_i ) |
p_signals_clk_domain | ( clk_4x_logic ) |
p_register_delayed_bits | ( clk_4x_logic ) |
Types | |
t_deserialized_trigger_data_array | is array ( natural range<> ) of std_logic_vector ( 7 downto 0 ) |
Signals | |
s_rst_iserdes | std_logic := ' 0 ' |
Reset ISERDES and calibrate IODELAY. | |
s_rst_iserdes_ipb | std_logic := ' 0 ' |
Reset ISERDES and calibrate IODELAY. | |
s_threshold_discr_input | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) |
s_cfd_discr_input | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) |
s_deserialized_threshold_data | t_deserialized_trigger_data_array ( g_NUM_INPUTS - 1 downto 0 ) |
s_deserialized_cfd_data | t_deserialized_trigger_data_array ( g_NUM_INPUTS - 1 downto 0 ) |
s_serdes_reset | std_logic := ' 0 ' |
s_cfd_trigger_times | t_triggerTimeArray ( g_NUM_INPUTS - 1 downto 0 ) |
s_CFD_rising_edge | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) |
s_CFD_falling_edge | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) |
s_threshold_previous_late_bit | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' ) |
s_CFD_previous_late_bit | std_logic_vector ( g_NUM_INPUTS - 1 downto 0 ) := ( others = > ' 0 ' ) |
s_ipbus_ack | std_logic := ' 0 ' |
Instantiations | |
thresholdinputbuffer | ibufds |
thresholddeserializer | dualSERDES_1to4 <Entity dualSERDES_1to4> |
thresholdlut | arrivalTimeLUT <Entity arrivalTimeLUT> |
cfdinputbuffer | ibufds |
cfddeserializer | dualSERDES_1to4 <Entity dualSERDES_1to4> |
cfdlut | arrivalTimeLUT <Entity arrivalTimeLUT> |