AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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top_extphy Member List

This is the complete list of members for top_extphy, including all inherited members.

Async_isync_regPort
async_iReg_2clksPort
buffer_full_oeventBufferPort
busy_from_dut_n_i (defined in DUTInterfaces)DUTInterfacesPort
busy_from_dut_p_i (defined in DUTInterfaces)DUTInterfacesPort
busy_i (defined in top_extphy)top_extphyPort
busy_n_i (defined in top_extphy)top_extphyPort
busy_p_itop_extphyPort
cfd_discr_i (defined in top_extphy)top_extphyPort
cfd_discr_n_i (defined in top_extphy)top_extphyPort
cfd_discr_p_i (defined in top_extphy)top_extphyPort
clk_16x_logic_itriggerInputsPort
clk_16x_logic_o (defined in logic_clocks)logic_clocksPort
clk_4x_logic (defined in triggerInputs)triggerInputsPort
clk_4x_logic_i (defined in DUTInterfaces)DUTInterfacesPort
clk_4x_logic_i (defined in eventBuffer)eventBufferPort
clk_4x_logic_i (defined in eventFormatter)eventFormatterPort
triggerInputs.clk_4x_logic_iarrivalTimeLUTPort
clk_4x_logic_i (defined in triggerLogic)triggerLogicPort
clk_4x_logic_o (defined in logic_clocks)logic_clocksPort
clk_from_dut_n_i (defined in DUTInterfaces)DUTInterfacesPort
clk_from_dut_p_i (defined in DUTInterfaces)DUTInterfacesPort
clk_isync_regPort
clk_input_i (defined in registerCounter)registerCounterPort
clk_logic_o (defined in logic_clocks)logic_clocksPort
clk_logic_xtal_i (defined in logic_clocks)logic_clocksPort
clk_logic_xtal_o (defined in IPBusInterface)IPBusInterfacePort
clk_output_i (defined in registerCounter)registerCounterPort
clko_125 (defined in clocks_s6_extphy)clocks_s6_extphyPort
clko_ipb (defined in clocks_s6_extphy)clocks_s6_extphyPort
clocks_locked_o (defined in IPBusInterface)IPBusInterfacePort
data_i (defined in registerCounter)registerCounterPort
data_i (defined in dualSERDES_1to4)dualSERDES_1to4Port
data_o (defined in registerCounter)registerCounterPort
triggerInputs.data_odualSERDES_1to4Port
data_strobe_i (defined in eventBuffer)eventBufferPort
data_strobe_o (defined in eventFormatter)eventFormatterPort
deserialized_data_i (defined in arrivalTimeLUT)arrivalTimeLUTPort
dip_switch_i (defined in top_extphy)top_extphyPort
dut_clk (defined in top_extphy)top_extphyPort
dut_clk_n_i (defined in top_extphy)top_extphyPort
dut_clk_p_i (defined in top_extphy)top_extphyPort
edge_fall_i (defined in eventFormatter)eventFormatterPort
edge_fall_time_i (defined in eventFormatter)eventFormatterPort
edge_falling_o (defined in triggerInputs)triggerInputsPort
edge_falling_times_o (defined in triggerInputs)triggerInputsPort
edge_rise_i (defined in eventFormatter)eventFormatterPort
edge_rise_time_i (defined in eventFormatter)eventFormatterPort
edge_rising_o (defined in triggerInputs)triggerInputsPort
edge_rising_times_o (defined in triggerInputs)triggerInputsPort
emac_hostbus_decl (defined in IPBusInterface)IPBusInterfaceuse clause
event_data_i (defined in eventBuffer)eventBufferPort
event_data_o (defined in eventFormatter)eventFormatterPort
event_number_i (defined in eventFormatter)eventFormatterPort
event_number_o (defined in triggerLogic)triggerLogicPort
extclk_n_b (defined in top_extphy)top_extphyPort
extclk_p_btop_extphyPort
fabricClk_idualSERDES_1to4Port
falling_edge_o (defined in arrivalTimeLUT)arrivalTimeLUTPort
fastClk_idualSERDES_1to4Port
first_rising_edge_time_o (defined in arrivalTimeLUT)arrivalTimeLUTPort
fmcTLU (defined in eventFormatter)eventFormatteruse clause
fmcTLU (defined in triggerInputs)triggerInputsuse clause
g_COUNTER_TRIG_WIDTH (defined in eventFormatter)eventFormatterGeneric
g_COUNTER_WIDTH (defined in eventFormatter)eventFormatterGeneric
g_Data_width (defined in sync_reg)sync_regGeneric
g_DATA_WIDTH (defined in registerCounter)registerCounterGeneric
g_EVENT_DATA_WIDTH (defined in top_extphy)top_extphyGeneric
g_EVTTYPE_WIDTH (defined in eventFormatter)eventFormatterGeneric
g_IPBUS_WIDTH (defined in top_extphy)top_extphyGeneric
g_NUM_COARSE_BITS (defined in arrivalTimeLUT)arrivalTimeLUTGeneric
g_NUM_DUTS (defined in top_extphy)top_extphyGeneric
g_NUM_EDGE_INPUTS (defined in top_extphy)top_extphyGeneric
g_NUM_EXT_SLAVEStop_extphyGeneric
g_NUM_FINE_BITS (defined in arrivalTimeLUT)arrivalTimeLUTGeneric
g_NUM_INPUTS (defined in triggerInputs)triggerInputsGeneric
g_NUM_INPUTS (defined in triggerLogic)triggerLogicGeneric
g_NUM_TRIG_INPUTS (defined in top_extphy)top_extphyGeneric
g_READ_COUNTER_WIDTH (defined in eventBuffer)eventBufferGeneric
g_SPILL_COUNTER_WIDTH (defined in top_extphy)top_extphyGeneric
g_WRITE_COUNTER_WIDTH (defined in eventBuffer)eventBufferGeneric
gmii_gtx_clk_o (defined in top_extphy)top_extphyPort
gmii_rx_clk_i (defined in top_extphy)top_extphyPort
gmii_rx_dv_i (defined in top_extphy)top_extphyPort
gmii_rx_er_i (defined in top_extphy)top_extphyPort
gmii_rxd_i (defined in top_extphy)top_extphyPort
gmii_tx_en_o (defined in top_extphy)top_extphyPort
gmii_tx_er_o (defined in top_extphy)top_extphyPort
gmii_txd_o (defined in top_extphy)top_extphyPort
gpio_hdr (defined in top_extphy)top_extphyPort
i2c_scl_b (defined in top_extphy)top_extphyPort
i2c_scl_enb_o (defined in i2c_master)i2c_masterPort
i2c_scl_i (defined in i2c_master)i2c_masterPort
i2c_scl_o (defined in top_extphy)top_extphyPort
i2c_sda_b (defined in top_extphy)top_extphyPort
i2c_sda_d (defined in top_extphy)top_extphyPort
i2c_sda_enb_o (defined in i2c_master)i2c_masterPort
i2c_sda_i (defined in i2c_master)i2c_masterPort
ipb_clk_o (defined in IPBusInterface)IPBusInterfacePort
ipb_rst_o (defined in IPBusInterface)IPBusInterfacePort
ipbr_i (defined in IPBusInterface)IPBusInterfacePort
ipbus (defined in DUTInterfaces)DUTInterfacesuse clause
ipbus (defined in IPBusInterface)IPBusInterfaceuse clause
ipbus (defined in eventBuffer)eventBufferuse clause
ipbus (defined in eventFormatter)eventFormatteruse clause
ipbus (defined in i2c_master)i2c_masteruse clause
ipbus (defined in logic_clocks)logic_clocksuse clause
ipbus (defined in triggerInputs)triggerInputsuse clause
ipbus (defined in triggerLogic)triggerLogicuse clause
ipbus_clk_i (defined in DUTInterfaces)DUTInterfacesPort
ipbus_clk_i (defined in eventBuffer)eventBufferPort
ipbus_clk_i (defined in eventFormatter)eventFormatterPort
ipbus_clk_i (defined in i2c_master)i2c_masterPort
ipbus_clk_i (defined in logic_clocks)logic_clocksPort
ipbus_clk_i (defined in triggerInputs)triggerInputsPort
ipbus_clk_i (defined in triggerLogic)triggerLogicPort
ipbus_i (defined in DUTInterfaces)DUTInterfacesPort
ipbus_i (defined in eventBuffer)eventBufferPort
ipbus_i (defined in eventFormatter)eventFormatterPort
ipbus_i (defined in i2c_master)i2c_masterPort
ipbus_i (defined in logic_clocks)logic_clocksPort
ipbus_i (defined in triggerInputs)triggerInputsPort
ipbus_i (defined in triggerLogic)triggerLogicPort
ipbus_in (defined in ipbus_ver)ipbus_verPort
ipbus_o (defined in DUTInterfaces)DUTInterfacesPort
ipbus_o (defined in eventBuffer)eventBufferPort
ipbus_o (defined in eventFormatter)eventFormatterPort
ipbus_o (defined in i2c_master)i2c_masterPort
ipbus_o (defined in logic_clocks)logic_clocksPort
ipbus_o (defined in triggerInputs)triggerInputsPort
ipbus_o (defined in triggerLogic)triggerLogicPort
ipbus_out (defined in ipbus_ver)ipbus_verPort
ipbus_reset_i (defined in DUTInterfaces)DUTInterfacesPort
ipbus_reset_i (defined in eventBuffer)eventBufferPort
ipbus_reset_i (defined in i2c_master)i2c_masterPort
ipbus_reset_i (defined in logic_clocks)logic_clocksPort
ipbus_reset_i (defined in triggerInputs)triggerInputsPort
ipbus_reset_i (defined in triggerLogic)triggerLogicPort
ipbw_o (defined in IPBusInterface)IPBusInterfacePort
last_falling_edge_time_o (defined in arrivalTimeLUT)arrivalTimeLUTPort
leds_o (defined in top_extphy)top_extphyPort
locked (defined in clocks_s6_extphy)clocks_s6_extphyPort
logic_clocks_locked_o (defined in logic_clocks)logic_clocksPort
logic_reset_i (defined in eventBuffer)eventBufferPort
logic_reset_i (defined in eventFormatter)eventFormatterPort
logic_reset_i (defined in triggerLogic)triggerLogicPort
logic_reset_o (defined in logic_clocks)logic_clocksPort
logic_strobe_i (defined in eventFormatter)eventFormatterPort
logic_strobe_i (defined in triggerLogic)triggerLogicPort
multiple_edges_o (defined in arrivalTimeLUT)arrivalTimeLUTPort
NUM_DUTS (defined in top_extphy)top_extphyGeneric
NUM_EXT_SLAVES (defined in IPBusInterface)IPBusInterfaceGeneric
NUM_TRIG_INPUTS (defined in top_extphy)top_extphyGeneric
numeric_std (defined in top_extphy)top_extphyuse clause
onehz (defined in clocks_s6_extphy)clocks_s6_extphyPort
onehz_o (defined in IPBusInterface)IPBusInterfacePort
phy_rstb_o (defined in top_extphy)top_extphyPort
post_veto_trigger_o (defined in triggerLogic)triggerLogicPort
pre_veto_trigger_o (defined in triggerLogic)triggerLogicPort
Reset_i (defined in logic_clocks)logic_clocksPort
reset_or_clk_n_o (defined in top_extphy)top_extphyPort
reset_or_clk_o (defined in top_extphy)top_extphyPort
reset_or_clk_p_o (defined in top_extphy)top_extphyPort
reset_or_clk_to_dut_n_o (defined in DUTInterfaces)DUTInterfacesPort
reset_or_clk_to_dut_p_o (defined in DUTInterfaces)DUTInterfacesPort
rising_edge_o (defined in arrivalTimeLUT)arrivalTimeLUTPort
rsto_125 (defined in clocks_s6_extphy)clocks_s6_extphyPort
rsto_ipb (defined in clocks_s6_extphy)clocks_s6_extphyPort
serdes_ready_odualSERDES_1to4Port
serdes_reset_idualSERDES_1to4Port
shutter_cnt_i (defined in eventFormatter)eventFormatterPort
shutter_i (defined in eventFormatter)eventFormatterPort
spill_cnt_i (defined in eventFormatter)eventFormatterPort
spill_i (defined in eventFormatter)eventFormatterPort
strobe_16x_logic_itriggerInputsPort
strobe_16x_logic_o (defined in logic_clocks)logic_clocksPort
strobe_4x_logic_i (defined in DUTInterfaces)DUTInterfacesPort
strobe_4x_logic_i (defined in eventBuffer)eventBufferPort
strobe_4x_logic_i (defined in triggerInputs)triggerInputsPort
strobe_4x_logic_o (defined in logic_clocks)logic_clocksPort
strobe_idualSERDES_1to4Port
Sync_osync_regPort
sync_oReg_2clksPort
sysclk_n (defined in clocks_s6_extphy)clocks_s6_extphyPort
sysclk_n_itop_extphyPort
sysclk_p (defined in clocks_s6_extphy)clocks_s6_extphyPort
sysclk_p_i (defined in top_extphy)top_extphyPort
threshold_discr_i (defined in top_extphy)top_extphyPort
threshold_discr_n_i (defined in top_extphy)top_extphyPort
threshold_discr_p_i (defined in top_extphy)top_extphyPort
trigger_active_otriggerLogicPort
trigger_cnt_i (defined in eventFormatter)eventFormatterPort
trigger_count_ieventBufferPort
trigger_count_o (defined in eventFormatter)eventFormatterPort
trigger_counter_i (defined in DUTInterfaces)DUTInterfacesPort
trigger_debug_o (defined in triggerInputs)triggerInputsPort
trigger_i (defined in DUTInterfaces)DUTInterfacesPort
eventFormatter.trigger_ieventFormatterPort
trigger_i (defined in triggerLogic)triggerLogicPort
trigger_inputs_fired_i (defined in eventFormatter)eventFormatterPort
trigger_o (defined in triggerInputs)triggerInputsPort
trigger_times_i (defined in eventFormatter)eventFormatterPort
trigger_times_o (defined in triggerInputs)triggerInputsPort
trigger_to_dut_n_o (defined in DUTInterfaces)DUTInterfacesPort
trigger_to_dut_p_o (defined in DUTInterfaces)DUTInterfacesPort
triggers_n_o (defined in top_extphy)top_extphyPort
triggers_o (defined in top_extphy)top_extphyPort
triggers_p_otop_extphyPort
unisim (defined in DUTInterfaces)DUTInterfacesLibrary
unisim (defined in clocks_s6_extphy)clocks_s6_extphyLibrary
unisim (defined in logic_clocks)logic_clocksLibrary
unisim (defined in triggerInputs)triggerInputsLibrary
vcomponents (defined in logic_clocks)logic_clocksuse clause
vcomponents (defined in triggerInputs)triggerInputsuse clause
VComponents (defined in DUTInterfaces)DUTInterfacesuse clause
VComponents (defined in clocks_s6_extphy)clocks_s6_extphyuse clause
veto_i (defined in triggerLogic)triggerLogicPort
veto_o (defined in DUTInterfaces)DUTInterfacesPort