AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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pulse_shaper Entity Reference

Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again. More...

Inheritance diagram for pulse_shaper:
Collaboration diagram for pulse_shaper:

Entities

rtl  architecture
 

Libraries

UNISIM 
 Xilinx library.

Use Clauses

vcomponents 
 Xilinx component.

Ports

D_a_i   in std_logic
 Input pulse.
Q_a_o   out std_logic
 output pulse
CLK_i   in std_logic
 Clock , rising edge active.
RST_i   in std_logic
 Hold high for PULSE_LENGTH+4.
PULSE_LENGTH_i   in std_logic_vector ( 3 downto 0 )
 length of output pulse

Detailed Description

Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again.

Member Data Documentation

D_a_i in std_logic
Port

Input pulse.

Todo:
Broaden pulse fed into set/reset flip-flop

The documentation for this class was generated from the following file: