AIDA FMC Mini-TLU
Firmware for FMC-based mini-TLU (Trigger/Timing/Tagging Logic Unit) for AIDA
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Design Unit List
Here is a list of all design unit members with links to the Entities they belong to:
[detail level 12]
oNFmcTluI2c
|\CFmcTluI2c
oNI2cBusProperties
|\CI2cBusPropertiesI2cBusProperties - simple encapsulation of all items required to control an I2C bus
oNRawI2cAccess
|\CRawI2cAccess
oNtop
|\Ctop.rtl
oCarrivalTimeLUT
|\CarrivalTimeLUT.rtl
oCclocks_s6_extphy
|\Cclocks_s6_extphy.rtl
oCdtype_fd
|\Cdtype_fd.rtl
oCdtype_fdpe
|\Cdtype_fdpe.dtype_V
oCdtype_fdrAims to be the same as the Xilinx "FD" primitive - D-Type flip-flop
|\Cdtype_fdr.rtl
oCdtype_fdsAims to be the same as the Xilinx "FDS" primitive - D-Type flip-flop
|\Cdtype_fds.rtl
oCdualSERDES_1to4
|\CdualSERDES_1to4.rtlGoes low during calibration sequence
oCDUTInterfaces
|\CDUTInterfaces.rtl
oCeventBuffer
|\CeventBuffer.rtl
oCeventFormatter
|\CeventFormatter.rtl
oCfmc_tlu_sp601
|\Cfmc_tlu_sp601.rtl
oCfmc_tlu_sp601_tb
|\Cfmc_tlu_sp601_tb.behavior
oCfmc_tlu_top
oCi2c_master
|\Ci2c_master.rtl
oCipbus_ver
|\Cipbus_ver.rtl
oCIPBusInterface
|\CIPBusInterface.rtl
oClogic_clocks
|\Clogic_clocks.rtl
oCpulse_shaperOutput goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again
|\Cpulse_shaper.rtl
oCpulse_shaper_async_dtypes
|\Cpulse_shaper_async_dtypes.rtl
oCpulse_shaper_scorerChecks that pulse_shaper is behaving correctly. Check for Output goes high when input goes high ( asyncnronous to system clock). Output goes low again a controllable number of clock cycles later, synchronous with the rising edge of the clock. Gap of at least one clock cycle before output goes high again
|\Cpulse_shaper_scorer.rtl
oCpulseClockDomainCrossing
|\CpulseClockDomainCrossing.rtl
oCReg_2clks
|\CReg_2clks.Behavioral
oCregisterCounter
|\CregisterCounter.rtl
oCserdes_1_to_n_SDR
|\Cserdes_1_to_n_SDR.Behavioral
oCslaves
|\Cslaves.rtl
oCsync_reg
|\Csync_reg.Behavioral
oCtop_extphy
|oCtop_extphy.rtl
|\Ctop_extphy.struct
oCtriggerInputs
|\CtriggerInputs.rtl
\CtriggerLogic
 \CtriggerLogic.rtl